mirror of https://github.com/bsnes-emu/bsnes.git
74 lines
1.6 KiB
C++
74 lines
1.6 KiB
C++
#include <processor/processor.hpp>
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#include "r65816.hpp"
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namespace Processor {
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#include "algorithms.cpp"
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#include "disassembler.cpp"
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#include "serialization.cpp"
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#define L last_cycle();
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#define call(op) (this->*op)()
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#include "opcode_read.cpp"
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#include "opcode_write.cpp"
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#include "opcode_rmw.cpp"
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#include "opcode_pc.cpp"
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#include "opcode_misc.cpp"
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#include "switch.cpp"
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#undef L
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#undef call
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//immediate, 2-cycle opcodes with I/O cycle will become bus read
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//when an IRQ is to be triggered immediately after opcode completion.
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//this affects the following opcodes:
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// clc, cld, cli, clv, sec, sed, sei,
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// tax, tay, txa, txy, tya, tyx,
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// tcd, tcs, tdc, tsc, tsx, txs,
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// inc, inx, iny, dec, dex, dey,
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// asl, lsr, rol, ror, nop, xce.
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auto R65816::op_io_irq() -> void {
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if(interrupt_pending()) {
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//modify I/O cycle to bus read cycle, do not increment PC
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op_read(regs.pc.d);
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} else {
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op_io();
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}
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}
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auto R65816::op_io_cond2() -> void {
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if(regs.d.l != 0x00) {
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op_io();
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}
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}
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auto R65816::op_io_cond4(uint16 x, uint16 y) -> void {
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if(!regs.p.x || (x & 0xff00) != (y & 0xff00)) {
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op_io();
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}
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}
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auto R65816::op_io_cond6(uint16 addr) -> void {
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if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
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op_io();
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}
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}
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auto R65816::op_irq() -> void {
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op_read(regs.pc.d);
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op_io();
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if(!regs.e) op_writestack(regs.pc.b);
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op_writestack(regs.pc.h);
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op_writestack(regs.pc.l);
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op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
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rd.l = op_read(regs.vector + 0);
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regs.pc.b = 0x00;
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regs.p.i = 1;
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regs.p.d = 0;
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rd.h = op_read(regs.vector + 1);
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regs.pc.w = rd.w;
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}
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}
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