mirror of https://github.com/bsnes-emu/bsnes.git
782 lines
24 KiB
C++
782 lines
24 KiB
C++
#ifdef PROCESSOR_ARM_HPP
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auto ARM::disassemble_arm_instruction(uint32 pc) -> string {
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static string conditions[] = {
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"eq", "ne", "cs", "cc",
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"mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt",
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"gt", "le", "", "nv",
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};
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static string opcodes[] = {
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"and", "eor", "sub", "rsb",
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"add", "adc", "sbc", "rsc",
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"tst", "teq", "cmp", "cmn",
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"orr", "mov", "bic", "mvn",
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};
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static string registers[] = {
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"r0", "r1", "r2", "r3",
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"r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11",
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"r12", "sp", "lr", "pc",
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};
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static string indices[] = {
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"da", "ia", "db", "ib",
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};
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static auto is_move = [](uint4 opcode) { return opcode == 13 || opcode == 15; };
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static auto is_comp = [](uint4 opcode) { return opcode >= 8 && opcode <= 11; };
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static auto is_math = [](uint4 opcode) { return opcode < 8 || opcode == 12 || opcode == 14; };
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string output{hex(pc, 8L), " "};
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uint32 instruction = read(Word | Nonsequential, pc & ~3);
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output.append(hex(instruction, 8L), " ");
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//multiply()
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//mul{condition}{s} rd,rm,rs
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//mla{condition}{s} rd,rm,rs,rn
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if((instruction & 0x0fc000f0) == 0x00000090) {
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uint4 condition = instruction >> 28;
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uint1 accumulate = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rd = instruction >> 16;
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uint4 rn = instruction >> 12;
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uint4 rs = instruction >> 8;
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uint4 rm = instruction;
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output.append(accumulate ? "mla" : "mul", conditions[condition], save ? "s " : " ");
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output.append(registers[rd], ",", registers[rm], ",", registers[rs]);
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if(accumulate) output.append(",", registers[rn]);
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return output;
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}
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//multiply_long()
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//(u,s)mull{condition}{s} rdlo,rdhi,rm,rs
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//(u,s)mlal{condition}{s} rdlo,rdhi,rm,rs
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if((instruction & 0x0f8000f0) == 0x00800090) {
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uint4 condition = instruction >> 28;
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uint1 signextend = instruction >> 22;
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uint1 accumulate = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rdhi = instruction >> 16;
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uint4 rdlo = instruction >> 12;
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uint4 rs = instruction >> 8;
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uint4 rm = instruction;
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output.append(signextend ? "s" : "u", accumulate ? "mlal" : "mull", conditions[condition], save ? "s " : " ");
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output.append(registers[rdlo], ",", registers[rdhi], ",", registers[rm], ",", registers[rs]);
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return output;
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}
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//memory_swap()
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//swp{condition}{b} rd,rm,[rn]
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if((instruction & 0x0fb000f0) == 0x01000090) {
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uint4 condition = instruction >> 28;
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uint1 byte = instruction >> 22;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 rm = instruction;
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output.append("swp", conditions[condition], byte ? "b " : " ");
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output.append(registers[rd], ",", registers[rm], "[", registers[rn], "]");
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return output;
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}
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//move_half_register()
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//(ldr,str){condition}h rd,[rn,rm]{!}
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//(ldr,str){condition}h rd,[rn],rm
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if((instruction & 0x0e4000f0) == 0x000000b0) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 writeback = instruction >> 21;
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uint1 load = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 rm = instruction;
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output.append(load ? "ldr" : "str", conditions[condition], "h ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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output.append(",", up ? "+" : "-", registers[rm]);
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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return output;
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}
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//move_half_immediate()
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//(ldr,str){condition}h rd,[rd{,+/-offset}]{!}
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//(ldr,str){condition}h rd,[rn]{,+/-offset}
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if((instruction & 0x0e4000f0) == 0x004000b0) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 writeback = instruction >> 21;
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uint1 load = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 ih = instruction >> 8;
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uint4 il = instruction >> 0;
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uint8 immediate = (ih << 4) + (il << 0);
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output.append(load ? "ldr" : "str", conditions[condition], "h ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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if(immediate) output.append(",", up ? "+" : "-", "0x", hex(immediate, 2L));
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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if(rn == 15) output.append(" =0x", hex(read(Half | Nonsequential, pc + 8 + (up ? +immediate : -immediate)), 4L));
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return output;
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}
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//load_register()
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//ldr{condition}s(h,b) rd,[rn,rm]{!}
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//ldr{condition}s(h,b) rd,[rn],rm
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if((instruction & 0x0e5000d0) == 0x001000b0) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 writeback = instruction >> 21;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint1 half = instruction >> 5;
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uint4 rm = instruction;
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output.append("ldr", conditions[condition], half ? "sh " : "sb ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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output.append(",", up ? "+" : "-", registers[rm]);
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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return output;
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}
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//load_immediate()
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//ldr{condition}s(h,b) rd,[rn{,+/-offset}]{!}
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//ldr{condition}s(h,b) rd,[rn]{,+/-offset}
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if((instruction & 0x0e5000b0) == 0x005000b0) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 writeback = instruction >> 21;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 ih = instruction >> 8;
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uint1 half = instruction >> 5;
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uint4 il = instruction;
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uint8 immediate = (ih << 4) + (il << 0);
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output.append("ldr", conditions[condition], half ? "sh " : "sb ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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if(immediate) output.append(",", up ? "+" : "-", "0x", hex(immediate, 2L));
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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if(rn == 15 && half == 1) output.append(" =0x", hex(read(Half | Nonsequential, pc + 8 + (up ? +immediate : -immediate)), 4L));
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if(rn == 15 && half == 0) output.append(" =0x", hex(read(Byte | Nonsequential, pc + 8 + (up ? +immediate : -immediate)), 2L));
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return output;
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}
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//move_to_register_from_status()
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//mrs{condition} rd,(c,s)psr
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if((instruction & 0x0fb000f0) == 0x01000000) {
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uint4 condition = instruction >> 28;
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uint1 psr = instruction >> 22;
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uint4 rd = instruction >> 12;
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output.append("mrs", conditions[condition], " ");
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output.append(registers[rd], ",", psr ? "spsr" : "cpsr");
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return output;
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}
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//move_to_status_from_register()
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//msr{condition} (c,s)psr:{fields},rm
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if((instruction & 0x0fb000f0) == 0x01200000) {
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uint4 condition = instruction >> 28;
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uint1 psr = instruction >> 22;
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uint4 field = instruction >> 16;
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uint4 rm = instruction;
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output.append("msr", conditions[condition], " ");
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output.append(psr ? "spsr:" : "cpsr:");
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output.append(
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field & 1 ? "c" : "",
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field & 2 ? "x" : "",
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field & 4 ? "s" : "",
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field & 8 ? "f" : ""
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);
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output.append(",", registers[rm]);
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return output;
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}
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//branch_exchange_register()
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//bx{condition} rm
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if((instruction & 0x0ff000f0) == 0x01200010) {
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uint4 condition = instruction >> 28;
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uint4 rm = instruction;
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output.append("bx", conditions[condition], " ");
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output.append(registers[rm]);
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return output;
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}
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//move_to_status_from_immediate()
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//msr{condition} (c,s)psr:{fields},#immediate
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if((instruction & 0x0fb00000) == 0x03200000) {
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uint4 condition = instruction >> 28;
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uint1 psr = instruction >> 22;
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uint4 field = instruction >> 16;
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uint4 rotate = instruction >> 8;
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uint8 immediate = instruction;
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uint32 rm = (immediate >> (rotate * 2)) | (immediate << (32 - (rotate * 2)));
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output.append("msr", conditions[condition], " ");
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output.append(psr ? "spsr:" : "cpsr:");
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output.append(
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field & 1 ? "c" : "",
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field & 2 ? "x" : "",
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field & 4 ? "s" : "",
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field & 8 ? "f" : ""
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);
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output.append(",#0x", hex(immediate, 8L));
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return output;
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}
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//data_immediate_shift()
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//{opcode}{condition}{s} rd,rm {shift} #immediate
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//{opcode}{condition} rn,rm {shift} #immediate
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//{opcode}{condition}{s} rd,rn,rm {shift} #immediate
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if((instruction & 0x0e000010) == 0x00000000) {
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uint4 condition = instruction >> 28;
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uint4 opcode = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint5 shift = instruction >> 7;
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uint2 op = instruction >> 5;
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uint4 rm = instruction;
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output.append(opcodes[opcode], conditions[condition]);
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if(is_move(opcode)) output.append(save ? "s " : " ", registers[rd]);
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if(is_comp(opcode)) output.append(" ", registers[rn]);
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if(is_math(opcode)) output.append(save ? "s " : " ", registers[rd], ",", registers[rn]);
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output.append(",", registers[rm]);
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if(op == 0 && shift != 0) output.append(" lsl #", shift);
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if(op == 1) output.append(" lsr #", shift == 0 ? 32u : (unsigned)shift);
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if(op == 2) output.append(" asr #", shift == 0 ? 32u : (unsigned)shift);
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if(op == 3 && shift != 0) output.append(" ror #", shift);
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if(op == 3 && shift == 0) output.append(" rrx");
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return output;
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}
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//data_register_shift()
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//{opcode}{condition}{s} rd,rm {shift} rs
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//{opcode}{condition} rn,rm {shift} rs
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//{opcode}{condition}{s} rd,rn,rm {shift} rs
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if((instruction & 0x0e000090) == 0x00000010) {
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uint4 condition = instruction >> 28;
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uint4 opcode = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 rs = instruction >> 8;
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uint2 mode = instruction >> 5;
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uint4 rm = instruction;
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output.append(opcodes[opcode], conditions[condition]);
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if(is_move(opcode)) output.append(save ? "s " : " ", registers[rd], ",");
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if(is_comp(opcode)) output.append(registers[rn], ",");
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if(is_math(opcode)) output.append(save ? "s " : " ", registers[rd], ",", registers[rn], ",");
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output.append(registers[rm]);
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if(mode == 0) output.append(" lsl ");
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if(mode == 1) output.append(" lsr ");
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if(mode == 2) output.append(" asr ");
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if(mode == 3) output.append(" ror ");
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output.append(registers[rs]);
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return output;
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}
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//data_immediate()
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//{opcode}{condition}{s} rd,#immediate
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//{opcode}{condition} rn,#immediate
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//{opcode}{condition}{s} rd,rn,#immediate
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if((instruction & 0x0e000000) == 0x02000000) {
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uint4 condition = instruction >> 28;
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uint4 opcode = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 rotate = instruction >> 8;
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uint8 immediate = instruction;
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uint32 rm = (immediate >> (rotate << 1)) | (immediate << (32 - (rotate << 1)));
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output.append(opcodes[opcode], conditions[condition]);
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if(is_move(opcode)) output.append(save ? "s " : " ", registers[rd]);
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if(is_comp(opcode)) output.append(" ", registers[rn]);
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if(is_math(opcode)) output.append(save ? "s " : " ", registers[rd], ",", registers[rn]);
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output.append(",#0x", hex(rm, 8L));
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return output;
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}
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//move_immediate_offset()
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//(ldr,str){condition}{b} rd,[rn{,+/-offset}]{!}
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//(ldr,str){condition}{b} rd,[rn]{,+/-offset}
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if((instruction & 0x0e000000) == 0x04000000) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 byte = instruction >> 22;
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uint1 writeback = instruction >> 21;
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uint1 load = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint12 immediate = instruction;
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output.append(load ? "ldr" : "str", conditions[condition], byte ? "b " : " ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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if(immediate) output.append(",", up ? "+" : "-", "0x", hex(immediate, 3L));
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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if(rn == 15) output.append(" =0x", hex(read((byte ? Byte : Word) | Nonsequential, pc + 8 + (up ? +immediate : -immediate)), 8L));
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return output;
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}
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//move_register_offset()
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//(ldr,str){condition}{b} rd,[rn,rm {mode} #immediate]{1}
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//(ldr,str){condition}{b} rd,[rn],rm {mode} #immediate
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if((instruction & 0x0e000010) == 0x06000000) {
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uint4 condition = instruction >> 28;
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uint1 pre = instruction >> 24;
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uint1 up = instruction >> 23;
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uint1 byte = instruction >> 22;
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uint1 writeback = instruction >> 21;
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uint1 load = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint5 shift = instruction >> 7;
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uint2 mode = instruction >> 5;
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uint4 rm = instruction;
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output.append(load ? "ldr" : "str", conditions[condition], byte ? "b " : " ");
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output.append(registers[rd], ",[", registers[rn]);
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if(pre == 0) output.append("]");
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output.append(",", up ? "+" : "-", registers[rm]);
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if(mode == 0 && shift != 0) output.append(" lsl #", shift);
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if(mode == 1) output.append(" lsr #", shift == 0 ? 32u : (unsigned)shift);
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if(mode == 2) output.append(" asr #", shift == 0 ? 32u : (unsigned)shift);
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if(mode == 3 && shift != 0) output.append(" ror #", shift);
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if(mode == 3 && shift == 0) output.append(" rrx");
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if(pre == 1) output.append("]");
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if(pre == 0 || writeback == 1) output.append("!");
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return output;
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}
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//move_multiple()
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//(ldm,stm) {condition}{mode} rn{!},{r...}{^}
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if((instruction & 0x0e000000) == 0x08000000) {
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uint4 condition = instruction >> 28;
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uint2 index = instruction >> 23;
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uint1 s = instruction >> 22;
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uint1 writeback = instruction >> 21;
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uint1 load = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint16 list = instruction;
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output.append(load ? "ldm" : "stm", conditions[condition], indices[index], " ");
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output.append(registers[rn], writeback ? "!" : "", ",{");
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for(unsigned n = 0; n < 16; n++) if(list & (1 << n)) output.append(registers[n], ",");
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output.rtrim(",");
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output.append("}", s ? "^" : "");
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return output;
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}
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//branch()
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//b{l}{condition} address
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if((instruction & 0x0e000000) == 0x0a000000) {
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uint4 condition = instruction >> 28;
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uint1 link = instruction >> 24;
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output.append("b", link ? "l" : "", conditions[condition], " ");
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output.append("0x", hex(pc + 8 + (int24)instruction * 4, 8L));
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return output;
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}
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//software_interrupt()
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//swi #immediate
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if((instruction & 0x0f000000) == 0x0f000000) {
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uint24 immediate = instruction;
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output.append("swi #0x", hex(immediate, 6L));
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return output;
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}
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output.append("???");
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return output;
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}
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auto ARM::disassemble_thumb_instruction(uint32 pc) -> string {
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static string conditions[] = {
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"eq", "ne", "cs", "cc",
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"mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt",
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"gt", "le", "", "",
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};
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static string registers[] = {
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"r0", "r1", "r2", "r3",
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"r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11",
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"r12", "sp", "lr", "pc",
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};
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string output{hex(pc, 8L), " "};
|
|
|
|
uint16 instruction = read(Half | Nonsequential, pc & ~1);
|
|
output.append(hex(instruction, 4L), " ");
|
|
|
|
//adjust_register()
|
|
//(add,sub) rd,rn,rm
|
|
if((instruction & 0xfc00) == 0x1800) {
|
|
uint1 opcode = instruction >> 9;
|
|
uint3 rm = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(opcode == 0 ? "add" : "sub", " ", registers[rd], ",", registers[rn], ",", registers[rm]);
|
|
|
|
return output;
|
|
}
|
|
|
|
//adjust_immediate()
|
|
//(add,sub) rd,rn,#immediate
|
|
if((instruction & 0xfc00) == 0x1c00) {
|
|
uint1 opcode = instruction >> 9;
|
|
uint3 immediate = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(opcode == 0 ? "add" : "sub", " ", registers[rd], ",", registers[rn], ",#", hex(immediate, 1L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//shift_immediate()
|
|
//(lsl,lsr,asar) rd,rm,#immmediate
|
|
if((instruction & 0xe000) == 0x0000) {
|
|
static string opcodes[] = { "lsl", "lsr", "asr", "" };
|
|
|
|
uint2 opcode = instruction >> 11;
|
|
uint5 immediate = instruction >> 6;
|
|
uint3 rm = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm], ",#", immediate);
|
|
|
|
return output;
|
|
}
|
|
|
|
//immediate()
|
|
//(mov,cmp,add,sub) (rd,rn),#immediate
|
|
if((instruction & 0xe000) == 0x2000) {
|
|
static string opcodes[] = { "mov", "cmp", "add", "sub" };
|
|
|
|
uint2 opcode = instruction >> 11;
|
|
uint3 rd = instruction >> 8;
|
|
uint8 immediate = instruction;
|
|
|
|
output.append(opcodes[opcode], " ", registers[rd], ",#0x", hex(immediate, 2L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//alu()
|
|
//{opcode} rd,rm
|
|
if((instruction & 0xfc00) == 0x4000) {
|
|
static string opcodes[] = {
|
|
"and", "eor", "lsl", "lsr",
|
|
"asr", "adc", "sbc", "ror",
|
|
"tst", "neg", "cmp", "cmn",
|
|
"orr", "mul", "bic", "mvn",
|
|
};
|
|
|
|
uint4 opcode = instruction >> 6;
|
|
uint3 rm = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm]);
|
|
|
|
return output;
|
|
}
|
|
|
|
//branch_exchange()
|
|
//bx rm
|
|
if((instruction & 0xff80) == 0x4700) {
|
|
uint4 rm = instruction >> 3;
|
|
|
|
output.append("bx ", registers[rm]);
|
|
|
|
return output;
|
|
}
|
|
|
|
//alu_hi()
|
|
//{opcode} rd,rm
|
|
if((instruction & 0xfc00) == 0x4400) {
|
|
static string opcodes[] = { "add", "sub", "mov", "" };
|
|
|
|
uint2 opcode = instruction >> 8;
|
|
uint4 rm = instruction >> 3;
|
|
uint4 rd = ((uint1)(instruction >> 7) << 3) + (uint3)instruction;
|
|
|
|
if(opcode == 2 && rm == 8 && rd == 8) {
|
|
output.append("nop");
|
|
return output;
|
|
}
|
|
|
|
output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm]);
|
|
|
|
return output;
|
|
}
|
|
|
|
//load_literal()
|
|
//ldr rd,[pc,#+/-offset]
|
|
if((instruction & 0xf800) == 0x4800) {
|
|
uint3 rd = instruction >> 8;
|
|
uint8 displacement = instruction;
|
|
|
|
unsigned rm = ((pc + 4) & ~3) + displacement * 4;
|
|
output.append("ldr ", registers[rd], ",[pc,#0x", hex(rm, 3L), "]");
|
|
output.append(" =0x", hex(read(Word | Nonsequential, rm), 8L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_register_offset()
|
|
//(ld(r,s),str){b,h} rd,[rn,rm]
|
|
if((instruction & 0xf000) == 0x5000) {
|
|
static string opcodes[] = {
|
|
"str", "strh", "strb", "ldsb",
|
|
"ldr", "ldrh", "ldrb", "ldsh",
|
|
};
|
|
|
|
uint3 opcode = instruction >> 9;
|
|
uint3 rm = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(opcodes[opcode], " ", registers[rd], ",[", registers[rn], ",", registers[rm], "]");
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_word_immediate()
|
|
//(ldr,str) rd,[rn,#offset]
|
|
if((instruction & 0xf000) == 0x6000) {
|
|
uint1 load = instruction >> 11;
|
|
uint5 offset = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(load ? "ldr " : "str ", registers[rd], ",[", registers[rn], ",#0x", hex(offset * 4, 2L), "]");
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_byte_immediate()
|
|
//(ldr,str)b rd,[rn,#offset]
|
|
if((instruction & 0xf000) == 0x7000) {
|
|
uint1 load = instruction >> 11;
|
|
uint5 offset = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(load ? "ldrb " : "strb ", registers[rd], ",[", registers[rn], ",#0x", hex(offset, 2L), "]");
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_half_immediate()
|
|
//(ldr,str)h rd,[rn,#offset]
|
|
if((instruction & 0xf000) == 0x8000) {
|
|
uint1 load = instruction >> 11;
|
|
uint5 offset = instruction >> 6;
|
|
uint3 rn = instruction >> 3;
|
|
uint3 rd = instruction >> 0;
|
|
|
|
output.append(load ? "ldrh " : "strh ", registers[rd], ",[", registers[rn], ",#0x", hex(offset * 2, 2L), "]");
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_stack()
|
|
//(ldr,str) rd,[sp,#relative]
|
|
if((instruction & 0xf000) == 0x9000) {
|
|
uint1 opcode = instruction >> 11;
|
|
uint3 rd = instruction >> 8;
|
|
int8 relative = instruction;
|
|
|
|
output.append(opcode ? "ldr" : "str", " ", registers[rd], ",[sp,#0x", hex(relative * 4, 3L), "]");
|
|
|
|
return output;
|
|
}
|
|
|
|
//add_register_hi()
|
|
//add rd,{pc,sp},#immediate
|
|
if((instruction & 0xf000) == 0xa000) {
|
|
uint1 sp = instruction >> 11;
|
|
uint3 rd = instruction >> 8;
|
|
uint8 immediate = instruction;
|
|
|
|
output.append("add ", registers[rd], ",", sp ? "sp" : "pc", ",#0x", hex(immediate, 2L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//adjust_stack()
|
|
//(add,sub) sp,#immediate
|
|
if((instruction & 0xff00) == 0xb000) {
|
|
uint1 opcode = instruction >> 7;
|
|
uint7 immediate = instruction;
|
|
|
|
output.append(opcode == 0 ? "add" : "sub", " sp,#0x", hex(immediate * 4, 3L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//stack_multiple()
|
|
//push {r...{,lr}}
|
|
//pop {r...{,pc}}
|
|
if((instruction & 0xf600) == 0xb400) {
|
|
uint1 load = instruction >> 11;
|
|
uint1 branch = instruction >> 8;
|
|
uint8 list = instruction;
|
|
|
|
output.append(load == 0 ? "push" : "pop", " {");
|
|
for(unsigned l = 0; l < 8; l++) {
|
|
if(list & (1 << l)) output.append(registers[l], ",");
|
|
}
|
|
if(branch) output.append(load == 0 ? "lr," : "pc,");
|
|
output.rtrim(",");
|
|
output.append("}");
|
|
|
|
return output;
|
|
}
|
|
|
|
//move_multiple()
|
|
//(ldmia,stmia) rn,{r...}
|
|
if((instruction & 0xf000) == 0xc000) {
|
|
uint1 load = instruction >> 11;
|
|
uint3 rn = instruction >> 8;
|
|
uint8 list = instruction;
|
|
|
|
output.append(load ? "ldmia " : "stmia ", registers[rn], "!,{");
|
|
for(unsigned l = 0; l < 8; l++) {
|
|
if(list & (1 << l)) output.append(registers[l], ",");
|
|
}
|
|
output.rtrim(",");
|
|
output.append("}");
|
|
|
|
return output;
|
|
}
|
|
|
|
//software_interrupt()
|
|
//swi #immediate
|
|
if((instruction & 0xff00) == 0xdf00) {
|
|
uint8 immediate = instruction;
|
|
|
|
output.append("swi #0x", hex(immediate, 2L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//branch_conditional()
|
|
//b{condition} address
|
|
if((instruction & 0xf000) == 0xd000) {
|
|
uint4 condition = instruction >> 8;
|
|
int8 displacement = instruction;
|
|
|
|
uint32 offset = pc + 4 + displacement * 2;
|
|
output.append("b", conditions[condition], " 0x", hex(offset, 8L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//branch_short()
|
|
//b address
|
|
if((instruction & 0xf800) == 0xe000) {
|
|
int11 displacement = instruction;
|
|
|
|
output.append("b 0x", hex(pc + 4 + displacement * 2, 8L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//branch_long_prefix()
|
|
//bl address
|
|
if((instruction & 0xf800) == 0xf000) {
|
|
uint11 offsethi = instruction;
|
|
instruction = read(Half | Nonsequential, (pc & ~1) + 2);
|
|
uint11 offsetlo = instruction;
|
|
|
|
int22 displacement = (offsethi << 11) | (offsetlo << 0);
|
|
output.append("bl 0x", hex(pc + 4 + displacement * 2, 8L));
|
|
|
|
return output;
|
|
}
|
|
|
|
//branch_long_suffix()
|
|
//bl address
|
|
if((instruction & 0xf800) == 0xf800) {
|
|
output.append("...");
|
|
|
|
return output;
|
|
}
|
|
|
|
output.append("???");
|
|
return output;
|
|
}
|
|
|
|
auto ARM::disassemble_registers() -> string {
|
|
string output;
|
|
output.append( "r0:", hex(r( 0), 8L), " r1:", hex(r( 1), 8L), " r2:", hex(r( 2), 8L), " r3:", hex(r( 3), 8L), " ");
|
|
output.append( "r4:", hex(r( 4), 8L), " r5:", hex(r( 5), 8L), " r6:", hex(r( 6), 8L), " r7:", hex(r( 7), 8L), " ");
|
|
output.append("cpsr:", cpsr().n ? "N" : "n", cpsr().z ? "Z" : "z", cpsr().c ? "C" : "c", cpsr().v ? "V" : "v");
|
|
output.append("/", cpsr().i ? "I" : "i", cpsr().f ? "F" : "f", cpsr().t ? "T" : "t");
|
|
output.append("/", hex(cpsr().m, 2L), "\n");
|
|
output.append( "r8:", hex(r( 8), 8L), " r9:", hex(r( 9), 8L), " r10:", hex(r(10), 8L), " r11:", hex(r(11), 8L), " ");
|
|
output.append("r12:", hex(r(12), 8L), " sp:", hex(r(13), 8L), " lr:", hex(r(14), 8L), " pc:", hex(r(15), 8L), " ");
|
|
output.append("spsr:");
|
|
if(mode() == Processor::Mode::USR || mode() == Processor::Mode::SYS) { output.append("----/---/--"); return output; }
|
|
output.append( spsr().n ? "N" : "n", spsr().z ? "Z" : "z", spsr().c ? "C" : "c", spsr().v ? "V" : "v");
|
|
output.append("/", spsr().i ? "I" : "i", spsr().f ? "F" : "f", spsr().t ? "T" : "t");
|
|
output.append("/", hex(spsr().m, 2L));
|
|
return output;
|
|
}
|
|
|
|
#endif
|