mirror of https://github.com/bsnes-emu/bsnes.git
590 lines
15 KiB
C++
590 lines
15 KiB
C++
#ifdef PROCESSOR_ARM_HPP
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auto ARM::arm_opcode(uint32 rm) {
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uint4 opcode = instruction() >> 21;
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uint1 save = instruction() >> 20;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint32 rn = r(n);
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switch(opcode) {
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case 0: r(d) = bit(rn & rm); break; //AND
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case 1: r(d) = bit(rn ^ rm); break; //EOR
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case 2: r(d) = sub(rn, rm, 1); break; //SUB
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case 3: r(d) = sub(rm, rn, 1); break; //RSB
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case 4: r(d) = add(rn, rm, 0); break; //ADD
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case 5: r(d) = add(rn, rm, cpsr().c); break; //ADC
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case 6: r(d) = sub(rn, rm, cpsr().c); break; //SBC
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case 7: r(d) = sub(rm, rn, cpsr().c); break; //RSC
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case 8: bit(rn & rm); break; //TST
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case 9: bit(rn ^ rm); break; //TEQ
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case 10: sub(rn, rm, 1); break; //CMP
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case 11: add(rn, rm, 0); break; //CMN
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case 12: r(d) = bit(rn | rm); break; //ORR
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case 13: r(d) = bit(rm); break; //MOV
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case 14: r(d) = bit(rn & ~rm); break; //BIC
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case 15: r(d) = bit(~rm); break; //MVN
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}
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if(exceptionMode() && d == 15 && save) {
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cpsr() = spsr();
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processor.setMode((Processor::Mode)cpsr().m);
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}
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}
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auto ARM::arm_move_to_status(uint32 rm) {
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uint1 source = instruction() >> 22;
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uint4 field = instruction() >> 16;
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if(source == 1) {
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if(mode() == Processor::Mode::USR) return;
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if(mode() == Processor::Mode::SYS) return;
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}
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PSR &psr = source ? spsr() : cpsr();
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if(field & 1) {
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if(source == 1 || privilegedMode()) {
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psr.i = rm & 0x00000080;
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psr.f = rm & 0x00000040;
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psr.t = rm & 0x00000020;
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psr.m = rm & 0x0000001f;
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if(source == 0) processor.setMode((Processor::Mode)psr.m);
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}
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}
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if(field & 8) {
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psr.n = rm & 0x80000000;
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psr.z = rm & 0x40000000;
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psr.c = rm & 0x20000000;
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psr.v = rm & 0x10000000;
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}
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}
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//mul{condition}{s} rd,rm,rs
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//mla{condition}{s} rd,rm,rs,rn
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//cccc 0000 00as dddd nnnn ssss 1001 mmmm
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//c = condition
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//a = accumulate
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//s = save flags
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//d = rd
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//n = rn
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//s = rs
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//m = rm
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auto ARM::arm_op_multiply() {
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uint1 accumulate = instruction() >> 21;
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uint1 save = instruction() >> 20;
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uint4 d = instruction() >> 16;
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uint4 n = instruction() >> 12;
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uint4 s = instruction() >> 8;
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uint4 m = instruction();
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r(d) = mul(accumulate ? r(n) : 0u, r(m), r(s));
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}
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//(u,s)mull{condition}{s} rdlo,rdhi,rm,rs
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//(u,s)mlal{condition}{s} rdlo,rdhi,rm,rs
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//cccc 0000 1sas hhhh llll ssss 1001 mmmm
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//c = condition
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//s = sign-extend
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//a = accumulate
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//s = save flags
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//h = rdhi
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//l = rdlo
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//s = rs
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//m = rm
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auto ARM::arm_op_multiply_long() {
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uint1 signextend = instruction() >> 22;
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uint1 accumulate = instruction() >> 21;
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uint1 save = instruction() >> 20;
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uint4 dhi = instruction() >> 16;
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uint4 dlo = instruction() >> 12;
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uint4 s = instruction() >> 8;
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uint4 m = instruction();
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uint64 rm = r(m);
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uint64 rs = r(s);
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if(signextend) {
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rm = (int32)rm;
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rs = (int32)rs;
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}
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uint64 rd = rm * rs;
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if(accumulate) rd += ((uint64)r(dhi) << 32) + ((uint64)r(dlo) << 0);
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r(dhi) = rd >> 32;
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r(dlo) = rd >> 0;
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if(save) {
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cpsr().n = r(dhi) >> 31;
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cpsr().z = r(dhi) == 0 && r(dlo) == 0;
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//cpsr().c = 0; //(undefined)
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//cpsr().v = 0; //(undefined)
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}
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}
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//swp{condition}{b} rd,rm,[rn]
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//cccc 0001 0b00 nnnn dddd ---- 1001 mmmm
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//c = condition
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//b = byte (0 = word)
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//n = rn
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//d = rd
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//m = rm
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auto ARM::arm_op_memory_swap() {
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uint1 byte = instruction() >> 22;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint4 m = instruction();
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uint32 word = load((byte ? Byte : Word) | Nonsequential, r(n));
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store((byte ? Byte : Word) | Nonsequential, r(n), r(m));
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r(d) = word;
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}
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//(ldr,str){condition}h rd,[rn,rm]{!}
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//(ldr,str){condition}h rd,[rn],rm
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//cccc 000p u0wl nnnn dddd ---- 1011 mmmm
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//c = condition
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//p = pre (0 = post)
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//u = up
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//w = writeback
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//l = load (0 = save)
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//n = rn
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//d = rd
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//m = rm
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auto ARM::arm_op_move_half_register() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 writeback = instruction() >> 21;
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uint1 l = instruction() >> 20;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint4 m = instruction();
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uint32 rn = r(n);
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uint32 rm = r(m);
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uint32 rd = r(d);
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if(pre == 1) rn = up ? rn + rm : rn - rm;
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if(l == 1) rd = load(Half | Nonsequential, rn);
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if(l == 0) store(Half | Nonsequential, rn, rd);
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if(pre == 0) rn = up ? rn + rm : rn - rm;
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if(pre == 0 || writeback == 1) r(n) = rn;
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if(l == 1) r(d) = rd;
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}
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//(ldr,str){condition}h rd,[rn{,+/-offset}]{!}
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//(ldr,str){condition}h rd,[rn]{,+/-offset}
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//cccc 000p u1wl nnnn dddd iiii 1011 iiii
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//c = condition
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//p = pre (0 = post)
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//u = up
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//w = writeback
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//l = load (0 = save)
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//n = rn
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//d = rd
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//i = immediate hi
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//i = immediate lo
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auto ARM::arm_op_move_half_immediate() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 writeback = instruction() >> 21;
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uint1 l = instruction() >> 20;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint4 ih = instruction() >> 8;
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uint4 il = instruction();
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uint32 rn = r(n);
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uint32 rd = r(d);
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uint8 immediate = (ih << 4) + (il << 0);
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if(pre == 1) rn = up ? rn + immediate : rn - immediate;
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if(l == 1) rd = load(Half | Nonsequential, rn);
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if(l == 0) store(Half | Nonsequential, rn, rd);
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if(pre == 0) rn = up ? rn + immediate : rn - immediate;
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if(pre == 0 || writeback == 1) r(n) = rn;
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if(l == 1) r(d) = rd;
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}
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//ldr{condition}s(h,b) rd,[rn,rm]{!}
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//ldr{condition}s(h,b) rd,[rn],rm
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//cccc 000p u0w1 nnnn dddd ---- 11h1 mmmm
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//c = condition
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//p = pre (0 = post)
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//u = up
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//w = writeback
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//n = rn
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//d = rd
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//h = half (0 = byte)
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//m = rm
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auto ARM::arm_op_load_register() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 writeback = instruction() >> 21;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint1 half = instruction() >> 5;
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uint4 m = instruction();
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uint32 rn = r(n);
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uint32 rm = r(m);
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uint32 rd = r(d);
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if(pre == 1) rn = up ? rn + rm : rn - rm;
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rd = load((half ? Half : Byte) | Nonsequential | Signed, rn);
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if(pre == 0) rn = up ? rn + rm : rn - rm;
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if(pre == 0 || writeback == 1) r(n) = rn;
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r(d) = rd;
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}
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//ldr{condition}s(h,b) rd,[rn{,+/-offset}]{!}
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//ldr{condition}s(h,b) rd,[rn]{,+/-offset}
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//cccc 000p u1w1 nnnn dddd iiii 11h1 iiii
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//c = condition
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//p = pre (0 = post)
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//u = up
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//w = writeback
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//n = rn
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//d = rd
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//i = immediate hi
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//h = half (0 = byte)
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//i = immediate lo
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auto ARM::arm_op_load_immediate() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 writeback = instruction() >> 21;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint4 ih = instruction() >> 8;
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uint1 half = instruction() >> 5;
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uint4 il = instruction();
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uint32 rn = r(n);
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uint32 rd = r(d);
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uint8 immediate = (ih << 4) + (il << 0);
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if(pre == 1) rn = up ? rn + immediate : rn - immediate;
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rd = load((half ? Half : Byte) | Nonsequential | Signed, rn);
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if(pre == 0) rn = up ? rn + immediate : rn - immediate;
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if(pre == 0 || writeback == 1) r(n) = rn;
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r(d) = rd;
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}
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//mrs{condition} rd,(c,s)psr
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//cccc 0001 0r00 ++++ dddd ---- 0000 ----
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//c = condition
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//r = SPSR (0 = CPSR)
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//d = rd
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auto ARM::arm_op_move_to_register_from_status() {
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uint1 source = instruction() >> 22;
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uint4 d = instruction() >> 12;
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if(source) {
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if(mode() == Processor::Mode::USR) return;
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if(mode() == Processor::Mode::SYS) return;
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}
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r(d) = source ? spsr() : cpsr();
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}
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//msr{condition} (c,s)psr:{fields},rm
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//cccc 0001 0r10 ffff ++++ ---- 0000 mmmm
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//c = condition
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//r = SPSR (0 = CPSR)
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//f = field mask
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//m = rm
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auto ARM::arm_op_move_to_status_from_register() {
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uint4 m = instruction();
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arm_move_to_status(r(m));
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}
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//bx{condition} rm
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//cccc 0001 0010 ++++ ++++ ++++ 0001 mmmm
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//c = condition
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//m = rm
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auto ARM::arm_op_branch_exchange_register() {
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uint4 m = instruction();
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cpsr().t = r(m) & 1;
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r(15) = r(m);
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}
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//msr{condition} (c,s)psr:{fields},#immediate
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//cccc 0011 0r10 ffff ++++ rrrr iiii iiii
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//c = condition
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//r = SPSR (0 = CPSR)
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//f = field mask
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//r = rotate
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//i = immediate
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auto ARM::arm_op_move_to_status_from_immediate() {
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uint4 rotate = instruction() >> 8;
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uint8 immediate = instruction();
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uint32 rm = immediate;
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if(rotate) rm = ror(rm, 2 * rotate);
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arm_move_to_status(rm);
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}
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//{opcode}{condition}{s} rd,rm {shift} #immediate
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//{opcode}{condition} rn,rm {shift} #immediate
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//{opcode}{condition}{s} rd,rn,rm {shift} #immediate
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//cccc 000o ooos nnnn dddd llll lss0 mmmm
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//c = condition
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//o = opcode
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//s = save flags
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//n = rn
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//d = rd
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//l = shift immediate
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//s = shift
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//m = rm
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auto ARM::arm_op_data_immediate_shift() {
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uint1 save = instruction() >> 20;
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uint5 shift = instruction() >> 7;
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uint2 mode = instruction() >> 5;
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uint4 m = instruction();
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uint32 rs = shift;
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uint32 rm = r(m);
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carryout() = cpsr().c;
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if(mode == 0) rm = lsl(rm, rs);
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if(mode == 1) rm = lsr(rm, rs ? rs : 32);
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if(mode == 2) rm = asr(rm, rs ? rs : 32);
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if(mode == 3) rm = rs ? ror(rm, rs) : rrx(rm);
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arm_opcode(rm);
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}
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//{opcode}{condition}{s} rd,rm {shift} rs
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//{opcode}{condition} rn,rm {shift} rs
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//{opcode}{condition}{s} rd,rn,rm {shift} rs
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//cccc 000o ooos nnnn dddd ssss 0ss1 mmmm
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//c = condition
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//o = opcode
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//s = save flags
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//n = rn
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//d = rd
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//s = rs
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//s = shift
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//m = rm
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auto ARM::arm_op_data_register_shift() {
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uint1 save = instruction() >> 20;
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uint4 s = instruction() >> 8;
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uint2 mode = instruction() >> 5;
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uint4 m = instruction();
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uint8 rs = r(s) + (s == 15 ? 4 : 0);
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uint32 rm = r(m) + (m == 15 ? 4 : 0);
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carryout() = cpsr().c;
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if(mode == 0 ) rm = lsl(rm, rs < 33 ? rs : 33);
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if(mode == 1 ) rm = lsr(rm, rs < 33 ? rs : 33);
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if(mode == 2 ) rm = asr(rm, rs < 32 ? rs : 32);
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if(mode == 3 && rs) rm = ror(rm, rs & 31 == 0 ? 32 : rs & 31);
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arm_opcode(rm);
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}
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//{opcode}{condition}{s} rd,#immediate
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//{opcode}{condition} rn,#immediate
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//{opcode}{condition}{s} rd,rn,#immediate
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//cccc 001o ooos nnnn dddd ssss iiii iiii
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//c = condition
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//o = opcode
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//s = save flags
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//n = rn
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//d = rd
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//s = shift immediate
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//i = immediate
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auto ARM::arm_op_data_immediate() {
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uint1 save = instruction() >> 20;
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uint4 shift = instruction() >> 8;
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uint8 immediate = instruction();
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uint32 rm = immediate;
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carryout() = cpsr().c;
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if(shift) rm = ror(immediate, 2 * shift);
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arm_opcode(rm);
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}
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//(ldr,str){condition}{b} rd,[rn{,+/-offset}]{!}
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//(ldr,str){condition}{b} rd,[rn]{,+/-offset}
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//cccc 010p ubwl nnnn dddd iiii iiii iiii
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//c = condition
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//p = pre (0 = post-indexed addressing)
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//u = up (add/sub offset to base)
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//b = byte (1 = word)
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//w = writeback
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//l = load (0 = save)
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//n = rn
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//d = rd
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//i = immediate
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auto ARM::arm_op_move_immediate_offset() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 byte = instruction() >> 22;
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uint1 writeback = instruction() >> 21;
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uint1 l = instruction() >> 20;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint12 rm = instruction();
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uint32 rn = r(n);
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uint32 rd = r(d);
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if(pre == 1) rn = up ? rn + rm : rn - rm;
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if(l == 1) rd = load((byte ? Byte : Word) | Nonsequential, rn);
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if(l == 0) store((byte ? Byte : Word) | Nonsequential, rn, rd);
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if(pre == 0) rn = up ? rn + rm : rn - rm;
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if(pre == 0 || writeback == 1) r(n) = rn;
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if(l == 1) r(d) = rd;
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}
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//(ldr,str){condition}{b} rd,[rn,rm {mode} #immediate]{!}
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//(ldr,str){condition}{b} rd,[rn],rm {mode} #immediate
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//cccc 011p ubwl nnnn dddd llll lss0 mmmm
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//c = condition
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//p = pre (0 = post-indexed addressing)
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//u = up
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//b = byte (1 = word)
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//w = writeback
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//l = load (0 = save)
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//n = rn
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//d = rd
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//l = shift immediate
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//s = shift mode
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//m = rm
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auto ARM::arm_op_move_register_offset() {
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uint1 pre = instruction() >> 24;
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uint1 up = instruction() >> 23;
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uint1 byte = instruction() >> 22;
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uint1 writeback = instruction() >> 21;
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uint1 l = instruction() >> 20;
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uint4 n = instruction() >> 16;
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uint4 d = instruction() >> 12;
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uint5 immediate = instruction() >> 7;
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uint2 mode = instruction() >> 5;
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uint4 m = instruction();
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uint32 rn = r(n);
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uint32 rd = r(d);
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uint32 rs = immediate;
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uint32 rm = r(m);
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bool c = cpsr().c;
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if(mode == 0) rm = lsl(rm, rs);
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if(mode == 1) rm = lsr(rm, rs ? rs : 32);
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if(mode == 2) rm = asr(rm, rs ? rs : 32);
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if(mode == 3) rm = rs ? ror(rm, rs) : rrx(rm);
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|
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if(pre == 1) rn = up ? rn + rm : rn - rm;
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|
if(l == 1) rd = load((byte ? Byte : Word) | Nonsequential, rn);
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if(l == 0) store((byte ? Byte : Word) | Nonsequential, rn, rd);
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|
if(pre == 0) rn = up ? rn + rm : rn - rm;
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|
|
|
if(pre == 0 || writeback == 1) r(n) = rn;
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if(l == 1) r(d) = rd;
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|
}
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|
|
|
//(ldm,stm){condition}{mode} rn{!},{r...}
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//cccc 100p uswl nnnn llll llll llll llll
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|
//c = condition
|
|
//p = pre (0 = post-indexed addressing)
|
|
//u = up (add/sub offset to base)
|
|
//s = spsr copy -or- usr register copy
|
|
//w = writeback
|
|
//l = load (0 = save)
|
|
//n = rn
|
|
//l = register list
|
|
auto ARM::arm_op_move_multiple() {
|
|
uint1 pre = instruction() >> 24;
|
|
uint1 up = instruction() >> 23;
|
|
uint1 s = instruction() >> 22;
|
|
uint1 writeback = instruction() >> 21;
|
|
uint1 l = instruction() >> 20;
|
|
uint4 n = instruction() >> 16;
|
|
uint16 list = instruction();
|
|
|
|
uint32 rn = r(n);
|
|
if(pre == 0 && up == 1) rn = rn + 0; //IA
|
|
if(pre == 1 && up == 1) rn = rn + 4; //IB
|
|
if(pre == 1 && up == 0) rn = rn - bit::count(list) * 4 + 0; //DB
|
|
if(pre == 0 && up == 0) rn = rn - bit::count(list) * 4 + 4; //DA
|
|
|
|
if(writeback && l == 1) {
|
|
if(up == 1) r(n) = r(n) + bit::count(list) * 4; //IA, IB
|
|
if(up == 0) r(n) = r(n) - bit::count(list) * 4; //DA, DB
|
|
}
|
|
|
|
Processor::Mode pmode = mode();
|
|
bool usr = false;
|
|
if(s && l == 1 && (list & 0x8000) == 0) usr = true;
|
|
if(s && l == 0) usr = true;
|
|
if(usr) processor.setMode(Processor::Mode::USR);
|
|
|
|
unsigned sequential = Nonsequential;
|
|
for(unsigned m = 0; m < 16; m++) {
|
|
if(list & 1 << m) {
|
|
if(l == 1) r(m) = read(Word | sequential, rn);
|
|
if(l == 0) write(Word | sequential, rn, r(m));
|
|
rn += 4;
|
|
sequential = Sequential;
|
|
}
|
|
}
|
|
|
|
if(usr) processor.setMode(pmode);
|
|
|
|
if(l == 1) {
|
|
idle();
|
|
if(s && (list & 0x8000)) {
|
|
if(mode() != Processor::Mode::USR && mode() != Processor::Mode::SYS) {
|
|
cpsr() = spsr();
|
|
processor.setMode((Processor::Mode)cpsr().m);
|
|
}
|
|
}
|
|
} else {
|
|
pipeline.nonsequential = true;
|
|
}
|
|
|
|
if(writeback && l == 0) {
|
|
if(up == 1) r(n) = r(n) + bit::count(list) * 4; //IA, IB
|
|
if(up == 0) r(n) = r(n) - bit::count(list) * 4; //DA, DB
|
|
}
|
|
}
|
|
|
|
//b{l}{condition} address
|
|
//cccc 101l dddd dddd dddd dddd dddd dddd
|
|
//c = condition
|
|
//l = link
|
|
//d = displacement (24-bit signed)
|
|
auto ARM::arm_op_branch() {
|
|
uint1 link = instruction() >> 24;
|
|
int24 displacement = instruction();
|
|
|
|
if(link) r(14) = r(15) - 4;
|
|
r(15) += displacement * 4;
|
|
}
|
|
|
|
//swi #immediate
|
|
//cccc 1111 iiii iiii iiii iiii iiii iiii
|
|
//c = condition
|
|
//i = immediate
|
|
auto ARM::arm_op_software_interrupt() {
|
|
uint24 immediate = instruction();
|
|
|
|
vector(0x00000008, Processor::Mode::SVC);
|
|
}
|
|
|
|
#endif
|