mirror of https://github.com/bsnes-emu/bsnes.git
154 lines
4.0 KiB
C++
154 lines
4.0 KiB
C++
#include <sfc/sfc.hpp>
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namespace SuperFamicom {
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CPU cpu;
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#include "serialization.cpp"
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#include "dma/dma.cpp"
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#include "memory/memory.cpp"
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#include "mmio/mmio.cpp"
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#include "timing/timing.cpp"
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CPU::CPU() {
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PPUcounter::scanline = {&CPU::scanline, this};
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}
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auto CPU::step(uint clocks) -> void {
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smp.clock -= clocks * (uint64)smp.frequency;
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ppu.clock -= clocks;
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for(unsigned i = 0; i < coprocessors.size(); i++) {
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auto& chip = *coprocessors[i];
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chip.clock -= clocks * (uint64)chip.frequency;
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}
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device.controllerPort1->clock -= clocks * (uint64)device.controllerPort1->frequency;
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device.controllerPort2->clock -= clocks * (uint64)device.controllerPort2->frequency;
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synchronizeDevices();
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}
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auto CPU::synchronizeSMP() -> void {
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if(SMP::Threaded == true) {
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if(smp.clock < 0) co_switch(smp.thread);
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} else {
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while(smp.clock < 0) smp.enter();
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}
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}
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auto CPU::synchronizePPU() -> void {
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if(PPU::Threaded == true) {
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if(ppu.clock < 0) co_switch(ppu.thread);
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} else {
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while(ppu.clock < 0) ppu.enter();
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}
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}
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auto CPU::synchronizeCoprocessors() -> void {
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for(unsigned i = 0; i < coprocessors.size(); i++) {
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auto& chip = *coprocessors[i];
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if(chip.clock < 0) co_switch(chip.thread);
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}
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}
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auto CPU::synchronizeDevices() -> void {
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if(device.controllerPort1->clock < 0) co_switch(device.controllerPort1->thread);
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if(device.controllerPort2->clock < 0) co_switch(device.controllerPort2->thread);
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}
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auto CPU::Enter() -> void { cpu.enter(); }
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auto CPU::enter() -> void {
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while(true) {
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if(scheduler.sync == Scheduler::SynchronizeMode::CPU) {
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scheduler.sync = Scheduler::SynchronizeMode::All;
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scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
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}
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if(status.interrupt_pending) {
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status.interrupt_pending = false;
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if(status.nmi_pending) {
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status.nmi_pending = false;
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regs.vector = (regs.e == false ? 0xffea : 0xfffa);
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op_irq();
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debugger.op_nmi();
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} else if(status.irq_pending) {
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status.irq_pending = false;
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regs.vector = (regs.e == false ? 0xffee : 0xfffe);
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op_irq();
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debugger.op_irq();
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} else if(status.reset_pending) {
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status.reset_pending = false;
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add_clocks(186);
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regs.pc.l = bus.read(0xfffc, regs.mdr);
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regs.pc.h = bus.read(0xfffd, regs.mdr);
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}
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}
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op_step();
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}
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}
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auto CPU::op_step() -> void {
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debugger.op_exec(regs.pc.d);
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op_exec();
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}
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auto CPU::enable() -> void {
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function<auto (uint, uint8) -> uint8> reader{&CPU::mmio_read, (CPU*)&cpu};
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function<auto (uint, uint8) -> void> writer{&CPU::mmio_write, (CPU*)&cpu};
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bus.map(reader, writer, 0x00, 0x3f, 0x2140, 0x2183);
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bus.map(reader, writer, 0x80, 0xbf, 0x2140, 0x2183);
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bus.map(reader, writer, 0x00, 0x3f, 0x4016, 0x4017);
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bus.map(reader, writer, 0x80, 0xbf, 0x4016, 0x4017);
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bus.map(reader, writer, 0x00, 0x3f, 0x4200, 0x421f);
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bus.map(reader, writer, 0x80, 0xbf, 0x4200, 0x421f);
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bus.map(reader, writer, 0x00, 0x3f, 0x4300, 0x437f);
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bus.map(reader, writer, 0x80, 0xbf, 0x4300, 0x437f);
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reader = [](uint addr, uint8) -> uint8 { return cpu.wram[addr]; };
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writer = [](uint addr, uint8 data) -> void { cpu.wram[addr] = data; };
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bus.map(reader, writer, 0x00, 0x3f, 0x0000, 0x1fff, 0x002000);
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bus.map(reader, writer, 0x80, 0xbf, 0x0000, 0x1fff, 0x002000);
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bus.map(reader, writer, 0x7e, 0x7f, 0x0000, 0xffff, 0x020000);
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}
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auto CPU::power() -> void {
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for(auto& byte : wram) byte = random(0x55);
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regs.a = regs.x = regs.y = 0x0000;
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regs.s = 0x01ff;
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mmio_power();
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dma_power();
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timing_power();
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}
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auto CPU::reset() -> void {
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create(Enter, system.cpuFrequency());
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coprocessors.reset();
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PPUcounter::reset();
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//note: some registers are not fully reset by SNES
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regs.pc = 0x000000;
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regs.x.h = 0x00;
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regs.y.h = 0x00;
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regs.s.h = 0x01;
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regs.d = 0x0000;
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regs.db = 0x00;
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regs.p = 0x34;
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regs.e = 1;
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regs.mdr = 0x00;
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regs.wai = false;
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regs.vector = 0xfffc; //reset vector address
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mmio_reset();
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dma_reset();
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timing_reset();
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}
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}
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