mirror of https://github.com/bsnes-emu/bsnes.git
311 lines
6.8 KiB
C++
311 lines
6.8 KiB
C++
auto CPU::readAPU(uint24 addr, uint8 data) -> uint8 {
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synchronize(smp);
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return smp.portRead(addr.bits(0,1));
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}
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auto CPU::readCPU(uint24 addr, uint8 data) -> uint8 {
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switch((uint16)addr) {
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//WMDATA
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case 0x2180: {
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return bus.read(0x7e0000 | io.wramAddress++, r.mdr);
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}
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//JOYSER0
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//7-2 = MDR
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//1-0 = Joypad serial data
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case 0x4016: {
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uint8 v = r.mdr & 0xfc;
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v |= controllerPort1.device->data();
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return v;
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}
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//JOYSER1
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case 0x4017: {
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//7-5 = MDR
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//4-2 = Always 1 (pins are connected to GND)
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//1-0 = Joypad serial data
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uint8 v = (r.mdr & 0xe0) | 0x1c;
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v |= controllerPort2.device->data();
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return v;
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}
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//RDNMI
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case 0x4210: {
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//7 = NMI acknowledge
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//6-4 = MDR
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//3-0 = CPU (5a22) version
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uint8 v = (r.mdr & 0x70);
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v |= (uint8)(rdnmi()) << 7;
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v |= (version & 0x0f);
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return v;
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}
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//TIMEUP
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case 0x4211: {
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//7 = IRQ acknowledge
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//6-0 = MDR
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uint8 v = (r.mdr & 0x7f);
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v |= (uint8)(timeup()) << 7;
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return v;
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}
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//HVBJOY
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case 0x4212: {
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//7 = VBLANK acknowledge
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//6 = HBLANK acknowledge
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//5-1 = MDR
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//0 = JOYPAD acknowledge
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uint8 v = (r.mdr & 0x3e);
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if(status.autoJoypadActive) v |= 0x01;
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if(hcounter() <= 2 || hcounter() >= 1096) v |= 0x40; //hblank
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if(vcounter() >= ppu.vdisp()) v |= 0x80; //vblank
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return v;
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}
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//RDIO
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case 0x4213: {
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return io.pio;
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}
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//RDDIVL
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case 0x4214: {
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return io.rddiv.byte(0);
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}
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//RDDIVH
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case 0x4215: {
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return io.rddiv.byte(1);
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}
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//RDMPYL
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case 0x4216: {
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return io.rdmpy.byte(0);
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}
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//RDMPYH
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case 0x4217: {
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return io.rdmpy.byte(1);
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}
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case 0x4218: return io.joy1.byte(0); //JOY1L
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case 0x4219: return io.joy1.byte(1); //JOY1H
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case 0x421a: return io.joy2.byte(0); //JOY2L
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case 0x421b: return io.joy2.byte(1); //JOY2H
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case 0x421c: return io.joy3.byte(0); //JOY3L
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case 0x421d: return io.joy3.byte(1); //JOY3H
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case 0x421e: return io.joy4.byte(0); //JOY4L
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case 0x421f: return io.joy4.byte(1); //JOY4H
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}
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return data;
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}
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auto CPU::readDMA(uint24 addr, uint8 data) -> uint8 {
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auto& channel = this->channel[addr.bits(4,6)];
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switch(addr & 0xff0f) {
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//DMAPx
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case 0x4300: return (
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channel.transferMode << 0
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| channel.fixedTransfer << 3
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| channel.reverseTransfer << 4
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| channel.unused << 5
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| channel.indirect << 6
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| channel.direction << 7
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);
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//BBADx
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case 0x4301: return channel.targetAddress;
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//A1TxL
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case 0x4302: return channel.sourceAddress >> 0;
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//A1TxH
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case 0x4303: return channel.sourceAddress >> 8;
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//A1Bx
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case 0x4304: return channel.sourceBank;
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//DASxL -- union { uint16 transferSize; uint16 indirectAddress; };
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case 0x4305: return channel.transferSize.byte(0);
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//DASxH -- union { uint16 transferSize; uint16 indirectAddress; };
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case 0x4306: return channel.transferSize.byte(1);
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//DASBx
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case 0x4307: return channel.indirectBank;
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//A2AxL
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case 0x4308: return channel.hdmaAddress.byte(0);
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//A2AxH
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case 0x4309: return channel.hdmaAddress.byte(1);
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//NTRLx
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case 0x430a: return channel.lineCounter;
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//???
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case 0x430b:
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case 0x430f: return channel.unknown;
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}
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return data;
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}
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auto CPU::writeAPU(uint24 addr, uint8 data) -> void {
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synchronize(smp);
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return smp.portWrite(addr.bits(0,1), data);
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}
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auto CPU::writeCPU(uint24 addr, uint8 data) -> void {
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switch((uint16)addr) {
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//WMDATA
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case 0x2180: {
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return bus.write(0x7e0000 | io.wramAddress++, data);
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}
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case 0x2181: io.wramAddress.bits( 0, 7) = data; return; //WMADDL
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case 0x2182: io.wramAddress.bits( 8,15) = data; return; //WMADDM
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case 0x2183: io.wramAddress.bit (16 ) = data.bit(0); return; //WMADDH
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//JOYSER0
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case 0x4016: {
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//bit 0 is shared between JOYSER0 and JOYSER1, therefore
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//strobing $4016.d0 affects both controller port latches.
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//$4017 bit 0 writes are ignored.
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controllerPort1.device->latch(data.bit(0));
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controllerPort2.device->latch(data.bit(0));
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return;
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}
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//NMITIMEN
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case 0x4200: {
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io.autoJoypadPoll = data.bit(0);
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nmitimenUpdate(data);
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return;
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}
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//WRIO
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case 0x4201: {
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if(io.pio.bit(7) && !data.bit(7)) ppu.latchCounters();
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io.pio = data;
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return;
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}
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//WRMPYA
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case 0x4202: io.wrmpya = data; return;
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//WRMPYB
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case 0x4203: {
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io.rdmpy = 0;
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if(alu.mpyctr || alu.divctr) return;
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io.wrmpyb = data;
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io.rddiv = (io.wrmpyb << 8) | io.wrmpya;
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alu.mpyctr = 8; //perform multiplication over the next eight cycles
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alu.shift = io.wrmpyb;
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return;
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}
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case 0x4204: { io.wrdiva.byte(0) = data; return; } //WRDIVL
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case 0x4205: { io.wrdiva.byte(1) = data; return; } //WRDIVH
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//WRDIVB
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case 0x4206: {
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io.rdmpy = io.wrdiva;
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if(alu.mpyctr || alu.divctr) return;
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io.wrdivb = data;
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alu.divctr = 16; //perform division over the next sixteen cycles
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alu.shift = io.wrdivb << 16;
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return;
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}
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case 0x4207: io.hirqPos.bits(0,7) = data; return; //HTIMEL
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case 0x4208: io.hirqPos.bit (8 ) = data.bit(0); return; //HTIMEH
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case 0x4209: io.virqPos.bits(0,7) = data; return; //VTIMEL
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case 0x420a: io.virqPos.bit (8 ) = data.bit(0); return; //VTIMEH
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//DMAEN
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case 0x420b: {
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for(auto n : range(8)) channel[n].dmaEnabled = data.bit(n);
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if(data) status.dmaPending = true;
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return;
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}
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//HDMAEN
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case 0x420c: {
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for(auto n : range(8)) channel[n].hdmaEnabled = data.bit(n);
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return;
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}
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//MEMSEL
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case 0x420d: {
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io.romSpeed = data.bit(0) ? 6 : 8;
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return;
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}
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}
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}
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auto CPU::writeDMA(uint24 addr, uint8 data) -> void {
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auto& channel = this->channel[addr.bits(4,6)];
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switch(addr & 0xff0f) {
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//DMAPx
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case 0x4300: {
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channel.transferMode = data.bits(0,2);
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channel.fixedTransfer = data.bit (3);
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channel.reverseTransfer = data.bit (4);
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channel.unused = data.bit (5);
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channel.indirect = data.bit (6);
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channel.direction = data.bit (7);
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return;
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}
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//DDBADx
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case 0x4301: channel.targetAddress = data; return;
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//A1TxL
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case 0x4302: channel.sourceAddress.byte(0) = data; return;
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//A1TxH
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case 0x4303: channel.sourceAddress.byte(1) = data; return;
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//A1Bx
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case 0x4304: channel.sourceBank = data; return;
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//DASxL -- union { uint16 transferSize; uint16 indirectAddress; };
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case 0x4305: channel.transferSize.byte(0) = data; return;
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//DASxH -- union { uint16 transferSize; uint16 indirectAddress; };
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case 0x4306: channel.transferSize.byte(1) = data; return;
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//DASBx
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case 0x4307: channel.indirectBank = data; return;
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//A2AxL
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case 0x4308: channel.hdmaAddress.byte(0) = data; return;
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//A2AxH
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case 0x4309: channel.hdmaAddress.byte(1) = data; return;
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//NTRLx
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case 0x430a: channel.lineCounter = data; return;
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//???
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case 0x430b:
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case 0x430f: channel.unknown = data; return;
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}
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}
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