bsnes/higan/sfc/coprocessor
Tim Allen 6871e0e32a Update to v106r78 release.
byuu says:

I've implemented a lot more TLCS900H instructions. There are currently
20 missing spots, all of which are unique instructions (well, MINC and
MDEC could be considered pairs of 3 each), from a map of 1024 slots.

After that, I have to write the disassembler. Then the memory bus. Then
I get to start the fun process of debugging this monstrosity.

Also new is nall/inline-if.hpp. Note that this file is technically a war
crime, so be careful when opening it. This replaces ternary() from the
previous WIP.
2019-01-14 17:16:28 +11:00
..
armdsp Update to v106r14 release. 2018-04-15 15:49:53 +10:00
dip Update to v106r20 release. 2018-05-15 00:13:30 +10:00
epsonrtc Update to v106r52 release. 2018-07-25 22:24:03 +10:00
event Update to v106r61 release. 2018-09-04 15:44:35 +10:00
hitachidsp Update to v106r61 release. 2018-09-04 15:44:35 +10:00
icd Update to v106r67 release. 2018-12-21 11:01:14 +11:00
mcc Update to v106r64 release. 2018-09-13 21:13:00 +10:00
msu1 Update to v106r52 release. 2018-07-25 22:24:03 +10:00
necdsp Update to v105r1 release. 2017-11-07 09:05:54 +11:00
obc1 Update to v106r61 release. 2018-09-04 15:44:35 +10:00
sa1 Update to v106r77 release. 2019-01-13 17:25:14 +11:00
sdd1 Update to v106r61 release. 2018-09-04 15:44:35 +10:00
sharprtc Update to v106r52 release. 2018-07-25 22:24:03 +10:00
spc7110 Update to v106r78 release. 2019-01-14 17:16:28 +11:00
superfx Update to v106r61 release. 2018-09-04 15:44:35 +10:00
coprocessor.hpp Update to v106r20 release. 2018-05-15 00:13:30 +10:00