mirror of https://github.com/bsnes-emu/bsnes.git
279 lines
6.4 KiB
C++
279 lines
6.4 KiB
C++
auto CPU::wram_addr(uint16 addr) const -> uint {
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addr &= 0x1fff;
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if(addr < 0x1000) return addr;
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auto bank = status.wram_bank + (status.wram_bank == 0);
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return (bank * 0x1000) + (addr & 0x0fff);
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}
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auto CPU::mmio_joyp_poll() -> void {
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uint button = 0, dpad = 0;
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button |= interface->inputPoll(0, 0, (uint)Input::Start) << 3;
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button |= interface->inputPoll(0, 0, (uint)Input::Select) << 2;
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button |= interface->inputPoll(0, 0, (uint)Input::B) << 1;
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button |= interface->inputPoll(0, 0, (uint)Input::A) << 0;
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dpad |= interface->inputPoll(0, 0, (uint)Input::Down) << 3;
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dpad |= interface->inputPoll(0, 0, (uint)Input::Up) << 2;
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dpad |= interface->inputPoll(0, 0, (uint)Input::Left) << 1;
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dpad |= interface->inputPoll(0, 0, (uint)Input::Right) << 0;
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if(system.revision() != System::Revision::SuperGameBoy) {
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//D-pad pivot makes it impossible to press opposing directions at the same time
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//however, Super Game Boy BIOS is able to set these bits together
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if(dpad & 4) dpad &= ~8; //disallow up+down
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if(dpad & 2) dpad &= ~1; //disallow left+right
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}
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status.joyp = 0x0f;
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if(status.p15 == 1 && status.p14 == 1) status.joyp -= status.mlt_req;
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if(status.p15 == 0) status.joyp &= button ^ 0x0f;
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if(status.p14 == 0) status.joyp &= dpad ^ 0x0f;
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if(status.joyp != 0x0f) interrupt_raise(Interrupt::Joypad);
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}
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auto CPU::mmio_read(uint16 addr) -> uint8 {
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if(addr >= 0xc000 && addr <= 0xfdff) return wram[wram_addr(addr)];
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if(addr >= 0xff80 && addr <= 0xfffe) return hram[addr & 0x7f];
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if(addr == 0xff00) { //JOYP
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mmio_joyp_poll();
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return 0xc0
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| (status.p15 << 5)
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| (status.p14 << 4)
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| (status.joyp << 0);
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}
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if(addr == 0xff01) { //SB
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return 0x00;
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}
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if(addr == 0xff02) { //SC
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return (status.serial_transfer << 7)
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| 0x7e
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| (status.serial_clock << 0);
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}
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if(addr == 0xff04) { //DIV
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return status.div >> 8;
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}
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if(addr == 0xff05) { //TIMA
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return status.tima;
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}
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if(addr == 0xff06) { //TMA
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return status.tma;
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}
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if(addr == 0xff07) { //TAC
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return 0xf8
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| (status.timer_enable << 2)
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| (status.timer_clock << 0);
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}
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if(addr == 0xff0f) { //IF
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return 0xe0
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| (status.interrupt_request_joypad << 4)
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| (status.interrupt_request_serial << 3)
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| (status.interrupt_request_timer << 2)
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| (status.interrupt_request_stat << 1)
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| (status.interrupt_request_vblank << 0);
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}
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if(addr == 0xff4d) { //KEY1
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return (status.speed_double << 7);
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}
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if(addr == 0xff55) { //HDMA5
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return (status.dma_completed << 7)
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| (((status.dma_length / 16) - 1) & 0x7f);
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}
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if(addr == 0xff56) { //RP
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return 0x02;
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}
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if(addr == 0xff6c) { //???
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return 0xfe | status.ff6c;
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}
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if(addr == 0xff70) { //SVBK
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return status.wram_bank;
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}
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if(addr == 0xff72) { //???
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return status.ff72;
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}
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if(addr == 0xff73) { //???
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return status.ff73;
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}
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if(addr == 0xff74) { //???
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return status.ff74;
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}
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if(addr == 0xff75) { //???
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return 0x8f | status.ff75;
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}
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if(addr == 0xff76) { //???
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return 0xff;
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}
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if(addr == 0xff77) { //???
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return 0xff;
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}
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if(addr == 0xffff) { //IE
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return 0xe0
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| (status.interrupt_enable_joypad << 4)
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| (status.interrupt_enable_serial << 3)
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| (status.interrupt_enable_timer << 2)
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| (status.interrupt_enable_stat << 1)
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| (status.interrupt_enable_vblank << 0);
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}
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return 0xff;
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}
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auto CPU::mmio_write(uint16 addr, uint8 data) -> void {
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if(addr >= 0xc000 && addr <= 0xfdff) { wram[wram_addr(addr)] = data; return; }
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if(addr >= 0xff80 && addr <= 0xfffe) { hram[addr & 0x7f] = data; return; }
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if(addr == 0xff00) { //JOYP
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status.p15 = data & 0x20;
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status.p14 = data & 0x10;
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interface->joypWrite(status.p15, status.p14);
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return;
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}
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if(addr == 0xff01) { //SB
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status.serial_data = data;
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return;
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}
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if(addr == 0xff02) { //SC
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status.serial_transfer = data & 0x80;
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status.serial_clock = data & 0x01;
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if(status.serial_transfer) status.serial_bits = 8;
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return;
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}
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if(addr == 0xff04) { //DIV
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status.div = 0;
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return;
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}
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if(addr == 0xff05) { //TIMA
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status.tima = data;
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return;
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}
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if(addr == 0xff06) { //TMA
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status.tma = data;
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return;
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}
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if(addr == 0xff07) { //TAC
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status.timer_enable = data & 0x04;
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status.timer_clock = data & 0x03;
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return;
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}
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if(addr == 0xff0f) { //IF
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status.interrupt_request_joypad = data & 0x10;
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status.interrupt_request_serial = data & 0x08;
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status.interrupt_request_timer = data & 0x04;
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status.interrupt_request_stat = data & 0x02;
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status.interrupt_request_vblank = data & 0x01;
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return;
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}
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if(addr == 0xff4d) { //KEY1
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status.speed_switch = data & 0x01;
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return;
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}
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if(addr == 0xff51) { //HDMA1
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status.dma_source = (status.dma_source & 0x00ff) | (data << 8);
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return;
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}
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if(addr == 0xff52) { //HDMA2
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status.dma_source = (status.dma_source & 0xff00) | (data & 0xf0);
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return;
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}
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if(addr == 0xff53) { //HDMA3
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status.dma_target = (status.dma_target & 0x00ff) | (data << 8);
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return;
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}
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if(addr == 0xff54) { //HDMA4
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status.dma_target = (status.dma_target & 0xff00) | (data & 0xf0);
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return;
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}
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if(addr == 0xff55) { //HDMA5
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status.dma_mode = data & 0x80;
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status.dma_length = ((data & 0x7f) + 1) * 16;
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status.dma_completed = !status.dma_mode;
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if(status.dma_mode == 0) {
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do {
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for(auto n : range(16)) {
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dma_write(status.dma_target++, dma_read(status.dma_source++));
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}
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add_clocks(8 << status.speed_double);
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status.dma_length -= 16;
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} while(status.dma_length);
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}
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return;
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}
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if(addr == 0xff56) { //RP
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return;
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}
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if(addr == 0xff6c) { //???
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status.ff6c = data & 0x01;
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return;
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}
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if(addr == 0xff72) { //???
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status.ff72 = data;
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return;
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}
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if(addr == 0xff73) { //???
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status.ff73 = data;
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return;
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}
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if(addr == 0xff74) { //???
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status.ff74 = data;
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return;
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}
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if(addr == 0xff75) { //???
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status.ff75 = data & 0x70;
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return;
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}
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if(addr == 0xff70) { //SVBK
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status.wram_bank = data & 0x07;
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return;
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}
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if(addr == 0xffff) { //IE
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status.interrupt_enable_joypad = data & 0x10;
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status.interrupt_enable_serial = data & 0x08;
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status.interrupt_enable_timer = data & 0x04;
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status.interrupt_enable_stat = data & 0x02;
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status.interrupt_enable_vblank = data & 0x01;
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return;
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}
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}
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