mirror of https://github.com/bsnes-emu/bsnes.git
158 lines
3.7 KiB
C++
158 lines
3.7 KiB
C++
#ifdef PPU_CPP
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void PPU::latch_counters() {
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regs.hcounter = cpu.hdot();
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regs.vcounter = cpu.vcounter();
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regs.counters_latched = true;
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}
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uint16 PPU::get_vram_address() {
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uint16 addr = regs.vram_addr;
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switch(regs.vram_mapping) {
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case 0: break; //direct mapping
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case 1: addr = (addr & 0xff00) | ((addr & 0x001f) << 3) | ((addr >> 5) & 7); break;
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case 2: addr = (addr & 0xfe00) | ((addr & 0x003f) << 3) | ((addr >> 6) & 7); break;
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case 3: addr = (addr & 0xfc00) | ((addr & 0x007f) << 3) | ((addr >> 7) & 7); break;
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}
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return (addr << 1);
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}
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//NOTE: all VRAM writes during active display are invalid. Unlike OAM and CGRAM, they will
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//not be written anywhere at all. The below address ranges for where writes are invalid have
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//been validated on hardware, as has the edge case where the S-CPU MDR can be written if the
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//write occurs during the very last clock cycle of vblank.
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uint8 PPU::vram_mmio_read(uint16 addr) {
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uint8 data;
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if(regs.display_disabled == true) {
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data = vram[addr];
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} else {
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uint16 v = cpu.vcounter();
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uint16 h = cpu.hcounter();
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uint16 ls = ((system.region() == System::Region::NTSC ? 525 : 625) >> 1) - 1;
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if(interlace() && !cpu.field()) ls++;
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if(v == ls && h == 1362) {
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data = 0x00;
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} else if(v < (!overscan() ? 224 : 239)) {
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data = 0x00;
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} else if(v == (!overscan() ? 224 : 239)) {
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if(h == 1362) {
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data = vram[addr];
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} else {
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data = 0x00;
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}
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} else {
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data = vram[addr];
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}
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}
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return data;
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}
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void PPU::vram_mmio_write(uint16 addr, uint8 data) {
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if(regs.display_disabled == true) {
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vram[addr] = data;
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} else {
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uint16 v = cpu.vcounter();
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uint16 h = cpu.hcounter();
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if(v == 0) {
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if(h <= 4) {
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vram[addr] = data;
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} else if(h == 6) {
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vram[addr] = cpu.regs.mdr;
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} else {
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//no write
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}
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} else if(v < (!overscan() ? 225 : 240)) {
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//no write
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} else if(v == (!overscan() ? 225 : 240)) {
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if(h <= 4) {
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//no write
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} else {
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vram[addr] = data;
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}
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} else {
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vram[addr] = data;
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}
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}
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}
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uint8 PPU::oam_mmio_read(uint16 addr) {
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addr &= 0x03ff;
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if(addr & 0x0200) addr &= 0x021f;
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uint8 data;
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if(regs.display_disabled == true) {
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data = oam[addr];
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} else {
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if(cpu.vcounter() < (!overscan() ? 225 : 240)) {
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data = oam[regs.ioamaddr];
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} else {
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data = oam[addr];
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}
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}
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return data;
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}
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void PPU::oam_mmio_write(uint16 addr, uint8 data) {
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addr &= 0x03ff;
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if(addr & 0x0200) addr &= 0x021f;
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sprite_list_valid = false;
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if(regs.display_disabled == true) {
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oam[addr] = data;
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update_sprite_list(addr, data);
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} else {
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if(cpu.vcounter() < (!overscan() ? 225 : 240)) {
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oam[regs.ioamaddr] = data;
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update_sprite_list(regs.ioamaddr, data);
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} else {
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oam[addr] = data;
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update_sprite_list(addr, data);
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}
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}
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}
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uint8 PPU::cgram_mmio_read(uint16 addr) {
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addr &= 0x01ff;
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uint8 data;
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if(1 || regs.display_disabled == true) {
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data = cgram[addr];
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} else {
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uint16 v = cpu.vcounter();
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uint16 h = cpu.hcounter();
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if(v < (!overscan() ? 225 : 240) && h >= 128 && h < 1096) {
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data = cgram[regs.icgramaddr] & 0x7f;
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} else {
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data = cgram[addr];
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}
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}
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if(addr & 1) data &= 0x7f;
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return data;
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}
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void PPU::cgram_mmio_write(uint16 addr, uint8 data) {
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addr &= 0x01ff;
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if(addr & 1) data &= 0x7f;
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if(1 || regs.display_disabled == true) {
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cgram[addr] = data;
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} else {
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uint16 v = cpu.vcounter();
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uint16 h = cpu.hcounter();
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if(v < (!overscan() ? 225 : 240) && h >= 128 && h < 1096) {
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cgram[regs.icgramaddr] = data & 0x7f;
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} else {
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cgram[addr] = data;
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}
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}
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}
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#endif
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