byuu says:
Changelog:
- PCE: split VCE from VDC
- HuC6280: changed bus from (uint21 addr) to (uint8 bank, uint13 addr)
- added SuperGrafx emulation (adds secondary VDC, plus new VPC)
The VDC now has no concept of the actual display raster timing, and
instead is driven by Vpulse (start of frame) and Hpulse (start of
scanline) signals from the VCE. One still can't render the start of the
next scanline onto the current scanline through overly aggressive
timings, but it shouldn't be too much more difficult to allow that to
occur now. This process incurs quite a major speed hit, so low-end
systems with Atom CPUs can't run things at 60fps anymore.
The timing needs a lot of work. The pixels end up very jagged if the VCE
doesn't output batches of 2-4 pixels at a time. But this should not be a
requirement at all, so I'm not sure what's going wrong there.
Yo, Bro and the 512-width mode of TV Sports Basketball is now broken as
a result of these changes, and I'm not sure why.
To load SuperGrafx games, you're going to have to change the .pce
extensions to .sg or .sgx. Or you can manually move the games from the
PC Engine folder to the SuperGrafx folder and change the game folder
extensions. I have no way to tell the games apart. Mednafen uses CRC32
comparisons, and I may consider that since there's only five games, but
I'm not sure yet.
The only SuperGrafx game that's playable right now is Aldynes. And the
priorities are all screwed up. I don't understand how the windows or the
priorities work at all from sgxtech.txt, so ... yeah. It's pretty
broken, but it's a start.
I could really use some help with this, as I'm very lost right now with
rendering :/
-----
Note that the SuperGrafx is technically its own system, it's not an
add-on.
As such, I'm giving it a separate .sys folder, and a separate library.
There's debate over how to name this thing. "SuperGrafx" appears more
popular than "Super Grafx". And you might also call it the "PC Engine
SuperGrafx", but I decided to leave off the prefix so it appears more
distinct.
byuu says:
Changelog:
- MS, MD, PCE: remove controllers from scheduler in destructor
[hex_usr]
- PCE: no controller should return all bits set (still causing errant
key presses when swapping gamepads)
- PCE: emulate MDR for hardware I/O $0800-$17ff
- PCE: change video resolution to 1140x242
- PCE: added tertiary background Vscroll register (secondary cache)
- PCE: create classes out of VDC VRAM, SATB, CRAM for cleaner access
and I/O registers
- PCE: high bits of CRAM read should be set
- PCE: partially emulated VCE display registers: color frequency, HDS,
HDW, VDS, VDW
- PCE: 32-width sprites now split to two 16-width sprites to handle
overflow properly
- PCE: hopefully emulated sprite zero hit correctly (it's not well
documented, and not often used)
- PCE: trigger line coincidence interrupts during the previous
scanline's Hblank period
- tomoko: raise viewport from 320x240 to 326x242 to accommodate PC
Engine's max resolution
- nall: workaround for Clang compilation bug that can't figure out
that a char is an integral data type
byuu says (in the public announcement):
This release adds very preliminary emulation of the Sega Master System
(Mark III), Sega Game Gear, Sega Mega Drive (Genesis), and NEC PC Engine
(Turbografx-16). These cores do not yet offer sound emulation, save
states or cheat codes.
I'm always very hesitant to release a new emulation core in its alpha
stages, as in the past this has resulted in lasting bad impressions
of cores that have since improved greatly. For instance, the Game Boy
Advance emulation offered today is easily the second most accurate around,
yet it is still widely judged by its much older alpha implementation.
However, it's always been tradition with higan to not hold onto code
in secret. Rather than delay future releases for another year or two,
I'll put my faith in you all to understand that the emulation of these
systems will improve over time.
I hope that by releasing things as they are now, I might be able to
receive some much needed assistance in improving these cores, as the
documentation for these new systems is very much less than ideal.
byuu says (in the WIP forum):
Changelog:
- PCE: latch background scroll registers (fixes Neutopia scrolling)
- PCE: clip background attribute table scrolling (fixes Blazing Lazers
scrolling)
- PCE: support background/sprite enable/disable bits
- PCE: fix large sprite indexing (fixes Blazing Lazers title screen
sprites)
- HuC6280: wrap zeropage accesses to never go beyond $20xx
- HuC6280: fix alternating addresses for block move instructions
(fixes Neutopia II)
- HuC6280: block move instructions save and restore A,X,Y registers
- HuC6280: emulate BCD mode (may not be 100% correct, based on SNES
BCD) (fixes Blazing Lazers scoring)
byuu says:
Changelog:
- PCE: added 384KB HuCard ROM mirroring mode
- PCE: corrected D-pad polling order
- PCE: corrected palette color ordering (GRB, not RGB -- yes,
seriously)
- PCE: corrected SATB DMA -- should write to SATB, not to VRAM
- PCE: broke out Background, Sprite VDC settings to separate
subclasses
- PCE: emulated VDC backgrounds
- PCE: emulated VDC sprites
- PCE: emulated VDC sprite overflow, collision interrupts
- HuC6280: fixed disassembler output for STi instructions
- HuC6280: added missing LastCycle check to interrupt()
- HuC6280: fixed BIT, CMP, CPX, CPY, TRB, TSB, TST flag testing and
result
- HuC6280: added extra cycle delays to the block move instructions
- HuC6280: fixed ordering for flag set/clear instructions (happens
after LastCycle check)
- HuC6280: removed extra cycle from immediate instructions
- HuC6280: fixed indirectLoad, indirectYStore absolute addressing
- HuC6280: fixed BBR, BBS zeropage value testing
- HuC6280: fixed stack push/pull direction
Neutopia looks okay until the main title screen, then there's some
gibberish on the bottom. The game also locks up with some gibberish once
you actually start a new game. So, still not playable just yet =(
byuu says:
Changelog:
- PCE: emulated gamepad polling
- PCE: emulated CPU interrupt sources
- PCE: emulated timer
- PCE: smarter emulation of ST0,ST1,ST2 instructions
- PCE: better structuring of CPU, VDP IO registers
- PCE: connected palette generation to the interface
- PCE: emulated basic VDC timing
- PCE: emulated VDC Vblank, Coincidence, and DMA completion IRQs
- PCE: emulated VRAM, SATB DMA transfers
- PCE: emulated VDC I/O registers
Everything I've implemented today likely has lots of bugs, and is
untested for obvious reasons.
So basically, after I fix many horrendous bugs, it should now be
possible to implement the VDC and start getting graphical output.
Tim Allen