byuu says:
Changelog:
- sfc/cx4: added missing instructions [info from Overload]
- sfc/cx4: added instruction cache emulation [info from ikari]
- sfc/sa1: don't let CPU access SA1-only I/O registers, and vice versa
- sfc/sa1: fixed IRQs that were broken from the recent WIP
- sfc/sa1: significantly improved bus conflict emulation
- all tests match hardware now, other than HDMA ROM↔ROM, which
is 0.5 - 0.8% too fast
- sfc/cpu: fixed a bug with DMA→CPU alignment timing
- sfc/cpu: removed the DMA pipe; performs writes on the same cycles as
reads [info from nocash]
- sfc/memory: fix a crashing bug due to not clearing Memory size field
[hex_usr]
- bsnes/gb: use .rtc for real-time clock file extensions on the Game
Boy [hex_usr]
- ruby/cgl: compilation fix [Sintendo]
Now let's see if I can accept being off by ~0.65% on one of twelve SA1
timing tests for the time being and prioritize much more important
things or not.
byuu says:
This release adds ikari's Cx4 notes to bsnes. It fixes the MMX2 intro's
boss fight sequence to be frame perfect to real hardware. It's also very
slightly faster than before.
I've also added an option to toggle the CPU↔coprocessor cycle
synchronization to the emulation settings panel, so you don't have to
recompile to get the more accurate SA1 timings. I'm most likely going to
default this to disabled in bsnes, and *maybe* enabled in higan out of
the box.
StaticRAM (wasn't used) and MappedRAM are gone from the Super Famicom
core. Instead, there's now ReadableMemory, WritableMemory, and
ProtectedMemory (WritableMemory with a toggle for write protection.)
Cartridge::loadMap now takes a template Memory object, which bypasses an
extra virtual function call on memory accesses, but it doesn't really
impact speed much. Whatever.
Tim Allen