mirror of https://github.com/bsnes-emu/bsnes.git
Update to 20160215 release.
byuu says: Got it. Wow, that didn't hurt nearly as much as I thought it was going to. Dropped from 127.5fps to 123.5fps to use Natural/Integer for (u)int(8,16,32,64). That's totally worth the cost.
This commit is contained in:
Tim Allen
parent
0d0af39b44
commit
ef65bb862a
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@ -17,9 +17,9 @@ auto Interface::videoColor(uint16 r, uint16 g, uint16 b) -> uint32 {
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if(gamma != 1.0) {
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double reciprocal = 1.0 / 32767.0;
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r = r > 32767 ? r : 32767 * pow(r * reciprocal, gamma);
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g = g > 32767 ? g : 32767 * pow(g * reciprocal, gamma);
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b = b > 32767 ? b : 32767 * pow(b * reciprocal, gamma);
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r = r > 32767 ? r : uint16(32767 * pow(r * reciprocal, gamma));
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g = g > 32767 ? g : uint16(32767 * pow(g * reciprocal, gamma));
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b = b > 32767 ? b : uint16(32767 * pow(b * reciprocal, gamma));
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}
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if(luminance != 1.0) {
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@ -4,27 +4,9 @@
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#include <nall/dsp.hpp>
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using namespace nall;
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//todo: update code to support Natural<8,16,32>
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//using int8 = Integer<8>;
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//using int16 = Integer<16>;
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//using int32 = Integer<32>;
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//using int64 = Integer<64>;
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//using uint32 = Natural<32>;
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//using uint64 = Natural<64>;
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using int8 = int8_t;
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using int16 = int16_t;
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using int32 = int32_t;
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using int64 = int64_t;
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using uint8 = uint8_t;
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using uint16 = uint16_t;
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using uint32 = uint32_t;
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using uint64 = uint64_t;
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using varuint = varuint_t<uint>;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "097.14";
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static const string Version = "097.15";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -35,6 +17,8 @@ namespace Emulator {
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static const string Profile = "Balanced";
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#elif defined(PROFILE_PERFORMANCE)
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static const string Profile = "Performance";
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#else
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static const string Profile = "Accuracy";
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#endif
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}
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@ -27,7 +27,7 @@ struct BandaiFCG : Board {
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auto prg_read(uint addr) -> uint8 {
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if(addr & 0x8000) {
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bool region = addr & 0x4000;
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uint bank = (region == 0 ? prg_bank : 0x0f);
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uint bank = (region == 0 ? prg_bank : (uint8)0x0f);
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return prgrom.read((bank << 14) | (addr & 0x3fff));
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}
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return cpu.mdr();
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@ -36,10 +36,10 @@ Board::Board(Markup::Node& document) {
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chrrom.size = crom["size"].natural();
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chrram.size = cram["size"].natural();
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if(prgrom.size) prgrom.data = new uint8[prgrom.size]();
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if(prgram.size) prgram.data = new uint8[prgram.size]();
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if(chrrom.size) chrrom.data = new uint8[chrrom.size]();
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if(chrram.size) chrram.data = new uint8[chrram.size]();
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if(prgrom.size) prgrom.data = new uint8_t[prgrom.size]();
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if(prgram.size) prgram.data = new uint8_t[prgram.size]();
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if(chrrom.size) chrrom.data = new uint8_t[chrrom.size]();
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if(chrram.size) chrram.data = new uint8_t[chrram.size]();
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if(auto name = prom["name"].text()) interface->loadRequest(ID::ProgramROM, name, true);
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if(auto name = pram["name"].text()) interface->loadRequest(ID::ProgramRAM, name, false);
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@ -88,7 +88,7 @@ struct MMC5 : Chip {
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auto prg_write(uint addr, uint8 data) -> void {
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if((addr & 0xfc00) == 0x5c00) {
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//writes 0x00 *during* Vblank (not during screen rendering ...)
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if(exram_mode == 0 || exram_mode == 1) exram[addr & 0x03ff] = in_frame ? data : 0x00;
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if(exram_mode == 0 || exram_mode == 1) exram[addr & 0x03ff] = in_frame ? data : (uint8)0x00;
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if(exram_mode == 2) exram[addr & 0x03ff] = data;
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return;
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}
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@ -271,7 +271,7 @@ struct MMC5 : Chip {
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switch(nametable_mode[(addr >> 10) & 3]) {
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case 0: return ppu.ciram_read(0x0000 | (addr & 0x03ff));
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case 1: return ppu.ciram_read(0x0400 | (addr & 0x03ff));
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case 2: return exram_mode < 2 ? exram[addr & 0x03ff] : 0x00;
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case 2: return exram_mode < 2 ? exram[addr & 0x03ff] : (uint8)0x00;
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case 3: return (hcounter & 2) == 0 ? fillmode_tile : fillmode_color;
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}
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}
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@ -84,8 +84,8 @@ struct VRC3 : Chip {
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uint16 irq_latch;
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struct {
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union {
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uint16 w;
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struct { uint8 order_lsb2(l, h); };
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uint16_t w;
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struct { uint8_t order_lsb2(l, h); };
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};
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} irq_counter;
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bool irq_line;
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@ -102,15 +102,15 @@ auto Interface::load(uint id, const stream& stream) -> void {
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}
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if(id == ID::GameBoyBootROM) {
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stream.read(system.bootROM.dmg, min( 256u, stream.size()));
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stream.read((uint8_t*)system.bootROM.dmg, min( 256u, stream.size()));
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}
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if(id == ID::SuperGameBoyBootROM) {
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stream.read(system.bootROM.sgb, min( 256u, stream.size()));
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stream.read((uint8_t*)system.bootROM.sgb, min( 256u, stream.size()));
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}
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if(id == ID::GameBoyColorBootROM) {
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stream.read(system.bootROM.cgb, min(2048u, stream.size()));
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stream.read((uint8_t*)system.bootROM.cgb, min(2048u, stream.size()));
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}
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if(id == ID::Manifest) {
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@ -118,17 +118,17 @@ auto Interface::load(uint id, const stream& stream) -> void {
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}
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if(id == ID::ROM) {
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stream.read(cartridge.romdata, min(cartridge.romsize, stream.size()));
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stream.read((uint8_t*)cartridge.romdata, min(cartridge.romsize, stream.size()));
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}
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if(id == ID::RAM) {
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stream.read(cartridge.ramdata, min(stream.size(), cartridge.ramsize));
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stream.read((uint8_t*)cartridge.ramdata, min(stream.size(), cartridge.ramsize));
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}
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}
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auto Interface::save(uint id, const stream& stream) -> void {
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if(id == ID::RAM) {
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stream.write(cartridge.ramdata, cartridge.ramsize);
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stream.write((uint8_t*)cartridge.ramdata, cartridge.ramsize);
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}
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}
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@ -16,13 +16,13 @@ auto Memory::operator[](uint addr) -> uint8& {
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auto Memory::allocate(uint size_) -> void {
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free();
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size = size_;
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data = new uint8_t[size]();
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data = new uint8[size];
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}
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auto Memory::copy(const uint8_t* data_, unsigned size_) -> void {
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auto Memory::copy(const uint8* data_, unsigned size_) -> void {
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free();
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size = size_;
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data = new uint8_t[size];
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data = new uint8[size];
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memcpy(data, data_, size);
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}
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@ -1,4 +1,4 @@
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APU::Registers::SoundBias::operator uint16() const {
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APU::Registers::SoundBias::operator uint16_t() const {
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return (
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(level << 0)
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| (amplitude << 14)
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@ -8,5 +8,5 @@ APU::Registers::SoundBias::operator uint16() const {
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auto APU::Registers::SoundBias::operator=(uint16 source) -> uint16 {
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level = (source >> 0) & 1023;
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amplitude = (source >> 14) & 3;
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return operator uint16();
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return operator uint16_t();
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}
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@ -3,7 +3,7 @@ struct Registers {
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uint10 level;
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uint2 amplitude;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const SoundBias&) -> SoundBias& = delete;
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} bias;
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@ -1,4 +1,4 @@
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CPU::Registers::DMAControl::operator uint16() const {
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CPU::Registers::DMAControl::operator uint16_t() const {
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return (
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(targetmode << 5)
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| (sourcemode << 7)
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@ -20,10 +20,10 @@ auto CPU::Registers::DMAControl::operator=(uint16 source) -> uint16 {
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timingmode = source >> 12;
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irq = source >> 14;
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enable = source >> 15;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::TimerControl::operator uint16() const {
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CPU::Registers::TimerControl::operator uint16_t() const {
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return (
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(frequency << 0)
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| (cascade << 2)
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@ -37,10 +37,10 @@ auto CPU::Registers::TimerControl::operator=(uint16 source) -> uint16 {
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cascade = source >> 2;
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irq = source >> 6;
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enable = source >> 7;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::SerialControl::operator uint16() const {
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CPU::Registers::SerialControl::operator uint16_t() const {
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return (
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(shiftclockselect << 0)
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| (shiftclockfrequency << 1)
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@ -60,10 +60,10 @@ auto CPU::Registers::SerialControl::operator=(uint16 source) -> uint16 {
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startbit = source >> 7;
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transferlength = source >> 12;
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irqenable = source >> 14;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::KeypadControl::operator uint16() const {
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CPU::Registers::KeypadControl::operator uint16_t() const {
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return (
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(flag[0] << 0)
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| (flag[1] << 1)
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@ -93,10 +93,10 @@ auto CPU::Registers::KeypadControl::operator=(uint16 source) -> uint16 {
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flag[9] = source >> 9;
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enable = source >> 14;
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condition = source >> 15;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::JoybusSettings::operator uint16() const {
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CPU::Registers::JoybusSettings::operator uint16_t() const {
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return (
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(sc << 0)
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| (sd << 1)
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@ -122,10 +122,10 @@ auto CPU::Registers::JoybusSettings::operator=(uint16 source) -> uint16 {
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somode = source >> 7;
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irqenable = source >> 8;
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mode = source >> 14;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::JoybusControl::operator uint16() const {
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CPU::Registers::JoybusControl::operator uint16_t() const {
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return (
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(resetsignal << 0)
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| (receivecomplete << 1)
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@ -139,10 +139,10 @@ auto CPU::Registers::JoybusControl::operator=(uint16 source) -> uint16 {
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receivecomplete = source >> 1;
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sendcomplete = source >> 2;
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irqenable = source >> 6;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::JoybusStatus::operator uint16() const {
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CPU::Registers::JoybusStatus::operator uint16_t() const {
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return (
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(receiveflag << 1)
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| (sendflag << 3)
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@ -154,10 +154,10 @@ auto CPU::Registers::JoybusStatus::operator=(uint16 source) -> uint16 {
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receiveflag = source >> 1;
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sendflag = source >> 3;
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generalflag = source >> 4;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::Interrupt::operator uint16() const {
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CPU::Registers::Interrupt::operator uint16_t() const {
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return (
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(vblank << 0)
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| (hblank << 1)
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@ -191,10 +191,10 @@ auto CPU::Registers::Interrupt::operator=(uint16 source) -> uint16 {
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dma[3] = source >> 11;
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keypad = source >> 12;
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cartridge = source >> 13;
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::WaitControl::operator uint16() const {
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CPU::Registers::WaitControl::operator uint16_t() const {
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return (
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(nwait[3] << 0)
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| (nwait[0] << 2)
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@ -221,10 +221,10 @@ auto CPU::Registers::WaitControl::operator=(uint16 source) -> uint16 {
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prefetch = (source >> 14) & 1;
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gametype = (source >> 15) & 1;
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swait[3] = nwait[3];
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return operator uint16();
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return operator uint16_t();
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}
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CPU::Registers::MemoryControl::operator uint32() const {
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CPU::Registers::MemoryControl::operator uint32_t() const {
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return (
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(disable << 0)
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| (unknown1 << 1)
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@ -240,5 +240,5 @@ auto CPU::Registers::MemoryControl::operator=(uint32 source) -> uint32 {
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ewram = source >> 5;
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ewramwait = source >> 24;
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unknown2 = source >> 28;
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return operator uint32();
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return operator uint32_t();
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}
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@ -9,24 +9,24 @@ struct Registers {
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uint1 irq;
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uint1 enable;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const DMAControl&) -> DMAControl& = delete;
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};
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struct DMA {
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varuint source;
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varuint target;
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varuint length;
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varuint_t<uint> source;
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varuint_t<uint> target;
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varuint_t<uint> length;
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uint32 data;
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DMAControl control;
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//internal
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bool pending;
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struct Run {
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varuint target;
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varuint source;
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varuint length;
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varuint_t<uint> target;
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varuint_t<uint> source;
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varuint_t<uint> length;
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} run;
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} dma[4];
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@ -36,7 +36,7 @@ struct Registers {
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uint1 irq;
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uint1 enable;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const TimerControl&) -> TimerControl& = delete;
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};
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@ -57,7 +57,7 @@ struct Registers {
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uint1 transferlength;
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uint1 irqenable;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const SerialControl&) -> SerialControl& = delete;
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};
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@ -73,7 +73,7 @@ struct Registers {
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uint1 enable;
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uint1 condition;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const KeypadControl&) -> KeypadControl& = delete;
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};
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@ -94,7 +94,7 @@ struct Registers {
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uint1 irqenable;
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uint2 mode;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const JoybusSettings&) -> JoybusSettings& = delete;
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};
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@ -105,7 +105,7 @@ struct Registers {
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uint1 sendcomplete;
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uint1 irqenable;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const JoybusControl&) -> JoybusControl& = delete;
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};
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@ -115,7 +115,7 @@ struct Registers {
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uint1 sendflag;
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uint2 generalflag;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const JoybusStatus&) -> JoybusStatus& = delete;
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};
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@ -140,7 +140,7 @@ struct Registers {
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uint1 keypad;
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uint1 cartridge;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const Interrupt&) -> Interrupt& = delete;
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};
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@ -157,7 +157,7 @@ struct Registers {
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uint1 prefetch;
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uint1 gametype;
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operator uint16() const;
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operator uint16_t() const;
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auto operator=(uint16 source) -> uint16;
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auto operator=(const WaitControl&) -> WaitControl& = delete;
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};
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@ -173,7 +173,7 @@ struct Registers {
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uint4 ewramwait;
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uint4 unknown2;
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operator uint32() const;
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operator uint32_t() const;
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auto operator=(uint32 source) -> uint32;
|
||||
auto operator=(const MemoryControl&) -> MemoryControl& = delete;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
}
|
||||
|
||||
if(id == ID::BIOS) {
|
||||
stream.read(bios.data, min(bios.size, stream.size()));
|
||||
stream.read((uint8_t*)bios.data, min(bios.size, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::Manifest) {
|
||||
|
|
@ -100,33 +100,33 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
}
|
||||
|
||||
if(id == ID::MROM) {
|
||||
stream.read(cartridge.mrom.data, min(cartridge.mrom.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.mrom.data, min(cartridge.mrom.size, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::SRAM) {
|
||||
stream.read(cartridge.sram.data, min(cartridge.sram.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.sram.data, min(cartridge.sram.size, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::EEPROM) {
|
||||
stream.read(cartridge.eeprom.data, min(cartridge.eeprom.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.eeprom.data, min(cartridge.eeprom.size, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::FLASH) {
|
||||
stream.read(cartridge.flash.data, min(cartridge.flash.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.flash.data, min(cartridge.flash.size, stream.size()));
|
||||
}
|
||||
}
|
||||
|
||||
auto Interface::save(uint id, const stream& stream) -> void {
|
||||
if(id == ID::SRAM) {
|
||||
stream.write(cartridge.sram.data, cartridge.sram.size);
|
||||
stream.write((uint8_t*)cartridge.sram.data, cartridge.sram.size);
|
||||
}
|
||||
|
||||
if(id == ID::EEPROM) {
|
||||
stream.write(cartridge.eeprom.data, cartridge.eeprom.size);
|
||||
stream.write((uint8_t*)cartridge.eeprom.data, cartridge.eeprom.size);
|
||||
}
|
||||
|
||||
if(id == ID::FLASH) {
|
||||
stream.write(cartridge.flash.data, cartridge.flash.size);
|
||||
stream.write((uint8_t*)cartridge.flash.data, cartridge.flash.size);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -59,9 +59,9 @@ auto Player::frame() -> void {
|
|||
auto Player::keyinput() -> maybe<uint16> {
|
||||
if(status.logoDetected) {
|
||||
switch(status.logoCounter) {
|
||||
case 0: return 0x03ff;
|
||||
case 1: return 0x03ff;
|
||||
case 2: return 0x030f;
|
||||
case 0: return {0x03ff};
|
||||
case 1: return {0x03ff};
|
||||
case 2: return {0x030f};
|
||||
}
|
||||
}
|
||||
return nothing;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
PPU::Registers::Control::operator uint16() const {
|
||||
PPU::Registers::Control::operator uint16_t() const {
|
||||
return (
|
||||
(bgmode << 0)
|
||||
| (cgbmode << 3)
|
||||
|
|
@ -32,10 +32,10 @@ auto PPU::Registers::Control::operator=(uint16 source) -> uint16 {
|
|||
enablewindow[In0] = source >> 13;
|
||||
enablewindow[In1] = source >> 14;
|
||||
enablewindow[Obj] = source >> 15;
|
||||
return operator uint16();
|
||||
return operator uint16_t();
|
||||
}
|
||||
|
||||
PPU::Registers::Status::operator uint16() const {
|
||||
PPU::Registers::Status::operator uint16_t() const {
|
||||
return (
|
||||
(vblank << 0)
|
||||
| (hblank << 1)
|
||||
|
|
@ -55,10 +55,10 @@ auto PPU::Registers::Status::operator=(uint16 source) -> uint16 {
|
|||
irqhblank = source >> 4;
|
||||
irqvcoincidence = source >> 5;
|
||||
vcompare = source >> 8;
|
||||
return operator uint16();
|
||||
return operator uint16_t();
|
||||
}
|
||||
|
||||
PPU::Registers::BackgroundControl::operator uint16() const {
|
||||
PPU::Registers::BackgroundControl::operator uint16_t() const {
|
||||
return (
|
||||
(priority << 0)
|
||||
| (characterbaseblock << 2)
|
||||
|
|
@ -80,10 +80,10 @@ auto PPU::Registers::BackgroundControl::operator=(uint16 source) -> uint16 {
|
|||
screenbaseblock = source >> 8;
|
||||
affinewrap = source >> 13;
|
||||
screensize = source >> 14;
|
||||
return operator uint16();
|
||||
return operator uint16_t();
|
||||
}
|
||||
|
||||
PPU::Registers::WindowFlags::operator uint8() const {
|
||||
PPU::Registers::WindowFlags::operator uint8_t() const {
|
||||
return (
|
||||
(enable[BG0] << 0)
|
||||
| (enable[BG1] << 1)
|
||||
|
|
@ -101,10 +101,10 @@ auto PPU::Registers::WindowFlags::operator=(uint8 source) -> uint8 {
|
|||
enable[BG3] = source >> 3;
|
||||
enable[OBJ] = source >> 4;
|
||||
enable[SFX] = source >> 5;
|
||||
return operator uint8();
|
||||
return operator uint8_t();
|
||||
}
|
||||
|
||||
PPU::Registers::BlendControl::operator uint16() const {
|
||||
PPU::Registers::BlendControl::operator uint16_t() const {
|
||||
return (
|
||||
(above[BG0] << 0)
|
||||
| (above[BG1] << 1)
|
||||
|
|
@ -136,5 +136,5 @@ auto PPU::Registers::BlendControl::operator=(uint16 source) -> uint16 {
|
|||
below[BG3] = source >> 11;
|
||||
below[OBJ] = source >> 12;
|
||||
below[SFX] = source >> 13;
|
||||
return operator uint16();
|
||||
return operator uint16_t();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ struct Registers {
|
|||
uint1 enable[5];
|
||||
uint1 enablewindow[3];
|
||||
|
||||
operator uint16() const;
|
||||
operator uint16_t() const;
|
||||
auto operator=(uint16 source) -> uint16;
|
||||
auto operator=(const Control&) -> Control& = delete;
|
||||
} control;
|
||||
|
|
@ -28,7 +28,7 @@ struct Registers {
|
|||
uint1 irqvcoincidence;
|
||||
uint8 vcompare;
|
||||
|
||||
operator uint16() const;
|
||||
operator uint16_t() const;
|
||||
auto operator=(uint16 source) -> uint16;
|
||||
auto operator=(const Status&) -> Status& = delete;
|
||||
} status;
|
||||
|
|
@ -45,7 +45,7 @@ struct Registers {
|
|||
uint1 affinewrap; //BG2,3 only
|
||||
uint2 screensize;
|
||||
|
||||
operator uint16() const;
|
||||
operator uint16_t() const;
|
||||
auto operator=(uint16 source) -> uint16;
|
||||
auto operator=(const BackgroundControl&) -> BackgroundControl& = delete;
|
||||
};
|
||||
|
|
@ -69,7 +69,7 @@ struct Registers {
|
|||
struct WindowFlags {
|
||||
uint1 enable[6];
|
||||
|
||||
operator uint8() const;
|
||||
operator uint8_t() const;
|
||||
auto operator=(uint8 source) -> uint8;
|
||||
auto operator=(const WindowFlags&) -> WindowFlags& = delete;
|
||||
};
|
||||
|
|
@ -93,7 +93,7 @@ struct Registers {
|
|||
uint1 below[6];
|
||||
uint2 mode;
|
||||
|
||||
operator uint16() const;
|
||||
operator uint16_t() const;
|
||||
auto operator=(uint16 source) -> uint16;
|
||||
auto operator=(const BlendControl&) -> BlendControl& = delete;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -354,8 +354,8 @@ auto ARM::arm_op_data_immediate_shift() {
|
|||
carryout() = cpsr().c;
|
||||
|
||||
if(mode == 0) rm = lsl(rm, rs);
|
||||
if(mode == 1) rm = lsr(rm, rs ? rs : 32);
|
||||
if(mode == 2) rm = asr(rm, rs ? rs : 32);
|
||||
if(mode == 1) rm = lsr(rm, rs ? rs : (uint32)32);
|
||||
if(mode == 2) rm = asr(rm, rs ? rs : (uint32)32);
|
||||
if(mode == 3) rm = rs ? ror(rm, rs) : rrx(rm);
|
||||
|
||||
arm_opcode(rm);
|
||||
|
|
@ -383,9 +383,9 @@ auto ARM::arm_op_data_register_shift() {
|
|||
uint32 rm = r(m) + (m == 15 ? 4 : 0);
|
||||
carryout() = cpsr().c;
|
||||
|
||||
if(mode == 0 ) rm = lsl(rm, rs < 33 ? rs : 33);
|
||||
if(mode == 1 ) rm = lsr(rm, rs < 33 ? rs : 33);
|
||||
if(mode == 2 ) rm = asr(rm, rs < 32 ? rs : 32);
|
||||
if(mode == 0 ) rm = lsl(rm, rs < 33 ? rs : (uint8)33);
|
||||
if(mode == 1 ) rm = lsr(rm, rs < 33 ? rs : (uint8)33);
|
||||
if(mode == 2 ) rm = asr(rm, rs < 32 ? rs : (uint8)32);
|
||||
if(mode == 3 && rs) rm = ror(rm, rs & 31 == 0 ? 32 : rs & 31);
|
||||
|
||||
arm_opcode(rm);
|
||||
|
|
@ -482,8 +482,8 @@ auto ARM::arm_op_move_register_offset() {
|
|||
bool c = cpsr().c;
|
||||
|
||||
if(mode == 0) rm = lsl(rm, rs);
|
||||
if(mode == 1) rm = lsr(rm, rs ? rs : 32);
|
||||
if(mode == 2) rm = asr(rm, rs ? rs : 32);
|
||||
if(mode == 1) rm = lsr(rm, rs ? rs : (uint32)32);
|
||||
if(mode == 2) rm = asr(rm, rs ? rs : (uint32)32);
|
||||
if(mode == 3) rm = rs ? ror(rm, rs) : rrx(rm);
|
||||
|
||||
if(pre == 1) rn = up ? rn + rm : rn - rm;
|
||||
|
|
|
|||
|
|
@ -47,8 +47,8 @@ auto ARM::arm_step() -> void {
|
|||
if(condition(instruction() >> 28) == false) return;
|
||||
|
||||
#define decode(pattern, execute) if( \
|
||||
(instruction() & std::integral_constant<uint32, bit::mask(pattern)>::value) \
|
||||
== std::integral_constant<uint32, bit::test(pattern)>::value \
|
||||
(instruction() & std::integral_constant<uint32_t, bit::mask(pattern)>::value) \
|
||||
== std::integral_constant<uint32_t, bit::test(pattern)>::value \
|
||||
) return arm_op_ ## execute()
|
||||
|
||||
decode("???? 0001 0010 ++++ ++++ ++++ 0001 ????", branch_exchange_register);
|
||||
|
|
@ -102,8 +102,8 @@ auto ARM::thumb_step() -> void {
|
|||
}
|
||||
|
||||
#define decode(pattern, execute) if( \
|
||||
(instruction() & std::integral_constant<uint32, bit::mask(pattern)>::value) \
|
||||
== std::integral_constant<uint32, bit::test(pattern)>::value \
|
||||
(instruction() & std::integral_constant<uint32_t, bit::mask(pattern)>::value) \
|
||||
== std::integral_constant<uint32_t, bit::test(pattern)>::value \
|
||||
) return thumb_op_ ## execute()
|
||||
|
||||
decode("0001 10?? ???? ????", adjust_register);
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@ struct Registers {
|
|||
|
||||
struct Register16 {
|
||||
union {
|
||||
uint16 w;
|
||||
struct { uint8 order_lsb2(l, h); };
|
||||
uint16_t w;
|
||||
struct { uint8_t order_lsb2(l, h); };
|
||||
};
|
||||
} abs, iabs;
|
||||
|
||||
|
|
|
|||
|
|
@ -22,8 +22,8 @@ struct flag_t {
|
|||
|
||||
struct reg16_t {
|
||||
union {
|
||||
uint16 w = 0;
|
||||
struct { uint8 order_lsb2(l, h); };
|
||||
uint16_t w = 0;
|
||||
struct { uint8_t order_lsb2(l, h); };
|
||||
};
|
||||
|
||||
inline operator unsigned() const { return w; }
|
||||
|
|
@ -42,9 +42,9 @@ struct reg16_t {
|
|||
|
||||
struct reg24_t {
|
||||
union {
|
||||
uint32 d = 0;
|
||||
struct { uint16 order_lsb2(w, wh); };
|
||||
struct { uint8 order_lsb4(l, h, b, bh); };
|
||||
uint32_t d = 0;
|
||||
struct { uint16_t order_lsb2(w, wh); };
|
||||
struct { uint8_t order_lsb4(l, h, b, bh); };
|
||||
};
|
||||
|
||||
inline operator unsigned() const { return d; }
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#define call (this->*op)
|
||||
|
||||
template<auto (SPC700::*op)(uint8) -> uint8>
|
||||
auto SPC700::op_adjust(uint8& r) -> void {
|
||||
auto SPC700::op_adjust(uint8_t& r) -> void {
|
||||
op_io();
|
||||
r = call(r);
|
||||
}
|
||||
|
|
@ -61,7 +61,7 @@ auto SPC700::op_branch_bit() -> void {
|
|||
regs.pc += (int8)rd;
|
||||
}
|
||||
|
||||
auto SPC700::op_pull(uint8& r) -> void {
|
||||
auto SPC700::op_pull(uint8_t& r) -> void {
|
||||
op_io();
|
||||
op_io();
|
||||
r = op_readsp();
|
||||
|
|
@ -74,7 +74,7 @@ auto SPC700::op_push(uint8 r) -> void {
|
|||
}
|
||||
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8>
|
||||
auto SPC700::op_read_addr(uint8& r) -> void {
|
||||
auto SPC700::op_read_addr(uint8_t& r) -> void {
|
||||
dp.l = op_readpc();
|
||||
dp.h = op_readpc();
|
||||
rd = op_read(dp);
|
||||
|
|
@ -82,7 +82,7 @@ auto SPC700::op_read_addr(uint8& r) -> void {
|
|||
}
|
||||
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8>
|
||||
auto SPC700::op_read_addri(uint8& r) -> void {
|
||||
auto SPC700::op_read_addri(uint8_t& r) -> void {
|
||||
dp.l = op_readpc();
|
||||
dp.h = op_readpc();
|
||||
op_io();
|
||||
|
|
@ -91,20 +91,20 @@ auto SPC700::op_read_addri(uint8& r) -> void {
|
|||
}
|
||||
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8>
|
||||
auto SPC700::op_read_const(uint8& r) -> void {
|
||||
auto SPC700::op_read_const(uint8_t& r) -> void {
|
||||
rd = op_readpc();
|
||||
r = call(r, rd);
|
||||
}
|
||||
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8>
|
||||
auto SPC700::op_read_dp(uint8& r) -> void {
|
||||
auto SPC700::op_read_dp(uint8_t& r) -> void {
|
||||
dp = op_readpc();
|
||||
rd = op_readdp(dp);
|
||||
r = call(r, rd);
|
||||
}
|
||||
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8>
|
||||
auto SPC700::op_read_dpi(uint8& r, uint8& i) -> void {
|
||||
auto SPC700::op_read_dpi(uint8_t& r, uint8_t& i) -> void {
|
||||
dp = op_readpc();
|
||||
op_io();
|
||||
rd = op_readdp(dp + i);
|
||||
|
|
@ -204,7 +204,7 @@ auto SPC700::op_test_addr(bool set) -> void {
|
|||
op_write(dp, set ? rd | regs.a : rd & ~regs.a);
|
||||
}
|
||||
|
||||
auto SPC700::op_transfer(uint8& from, uint8& to) -> void {
|
||||
auto SPC700::op_transfer(uint8_t& from, uint8_t& to) -> void {
|
||||
op_io();
|
||||
to = from;
|
||||
if(&to == ®s.s) return;
|
||||
|
|
@ -212,14 +212,14 @@ auto SPC700::op_transfer(uint8& from, uint8& to) -> void {
|
|||
regs.p.z = (to == 0);
|
||||
}
|
||||
|
||||
auto SPC700::op_write_addr(uint8& r) -> void {
|
||||
auto SPC700::op_write_addr(uint8_t& r) -> void {
|
||||
dp.l = op_readpc();
|
||||
dp.h = op_readpc();
|
||||
op_read(dp);
|
||||
op_write(dp, r);
|
||||
}
|
||||
|
||||
auto SPC700::op_write_addri(uint8& i) -> void {
|
||||
auto SPC700::op_write_addri(uint8_t& i) -> void {
|
||||
dp.l = op_readpc();
|
||||
dp.h = op_readpc();
|
||||
op_io();
|
||||
|
|
@ -228,13 +228,13 @@ auto SPC700::op_write_addri(uint8& i) -> void {
|
|||
op_write(dp, regs.a);
|
||||
}
|
||||
|
||||
auto SPC700::op_write_dp(uint8& r) -> void {
|
||||
auto SPC700::op_write_dp(uint8_t& r) -> void {
|
||||
dp = op_readpc();
|
||||
op_readdp(dp);
|
||||
op_writedp(dp, r);
|
||||
}
|
||||
|
||||
auto SPC700::op_write_dpi(uint8& r, uint8& i) -> void {
|
||||
auto SPC700::op_write_dpi(uint8_t& r, uint8_t& i) -> void {
|
||||
dp = op_readpc() + i;
|
||||
op_io();
|
||||
op_readdp(dp);
|
||||
|
|
|
|||
|
|
@ -35,17 +35,17 @@ struct Word {
|
|||
inline auto operator&=(uint data) -> uint { return w &= data; }
|
||||
|
||||
union {
|
||||
uint16 w;
|
||||
struct { uint8 order_lsb2(l, h); };
|
||||
uint16_t w;
|
||||
struct { uint8_t order_lsb2(l, h); };
|
||||
};
|
||||
};
|
||||
|
||||
struct Regs {
|
||||
Word pc;
|
||||
union {
|
||||
uint16 ya;
|
||||
struct { uint8 order_lsb2(a, y); };
|
||||
uint16_t ya;
|
||||
struct { uint8_t order_lsb2(a, y); };
|
||||
};
|
||||
uint8 x, s;
|
||||
uint8_t x, s;
|
||||
Flag p;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,20 +41,20 @@ protected:
|
|||
auto op_ldw(uint16, uint16) -> uint16;
|
||||
auto op_sbw(uint16, uint16) -> uint16;
|
||||
|
||||
template<auto (SPC700::*op)(uint8) -> uint8> auto op_adjust(uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8) -> uint8> auto op_adjust(uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8) -> uint8> auto op_adjust_addr() -> void;
|
||||
template<auto (SPC700::*op)(uint8) -> uint8> auto op_adjust_dp() -> void;
|
||||
auto op_adjust_dpw(int) -> void;
|
||||
template<auto (SPC700::*op)(uint8) -> uint8> auto op_adjust_dpx() -> void;
|
||||
auto op_branch(bool) -> void;
|
||||
auto op_branch_bit() -> void;
|
||||
auto op_pull(uint8&) -> void;
|
||||
auto op_pull(uint8_t&) -> void;
|
||||
auto op_push(uint8) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_addr(uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_addri(uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_const(uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_dp(uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_dpi(uint8&, uint8&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_addr(uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_addri(uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_const(uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_dp(uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_dpi(uint8_t&, uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint16, uint16) -> uint16> auto op_read_dpw() -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_idpx() -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_read_idpy() -> void;
|
||||
|
|
@ -63,11 +63,11 @@ protected:
|
|||
auto op_set_bit() -> void;
|
||||
auto op_set_flag(bool&, bool) -> void;
|
||||
auto op_test_addr(bool) -> void;
|
||||
auto op_transfer(uint8&, uint8&) -> void;
|
||||
auto op_write_addr(uint8&) -> void;
|
||||
auto op_write_addri(uint8&) -> void;
|
||||
auto op_write_dp(uint8&) -> void;
|
||||
auto op_write_dpi(uint8&, uint8&) -> void;
|
||||
auto op_transfer(uint8_t&, uint8_t&) -> void;
|
||||
auto op_write_addr(uint8_t&) -> void;
|
||||
auto op_write_addri(uint8_t&) -> void;
|
||||
auto op_write_dp(uint8_t&) -> void;
|
||||
auto op_write_dpi(uint8_t&, uint8_t&) -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_write_dp_const() -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_write_dp_dp() -> void;
|
||||
template<auto (SPC700::*op)(uint8, uint8) -> uint8> auto op_write_ix_iy() -> void;
|
||||
|
|
|
|||
|
|
@ -48,23 +48,23 @@ struct uPD96050 {
|
|||
};
|
||||
|
||||
struct Regs {
|
||||
uint16 stack[16]; //LIFO
|
||||
varuint pc; //program counter
|
||||
varuint rp; //ROM pointer
|
||||
varuint dp; //data pointer
|
||||
uint4 sp; //stack pointer
|
||||
uint16 stack[16]; //LIFO
|
||||
varuint_t<uint> pc; //program counter
|
||||
varuint_t<uint> rp; //ROM pointer
|
||||
varuint_t<uint> dp; //data pointer
|
||||
uint4 sp; //stack pointer
|
||||
int16 k;
|
||||
int16 l;
|
||||
int16 m;
|
||||
int16 n;
|
||||
int16 a; //accumulator
|
||||
int16 b; //accumulator
|
||||
int16 a; //accumulator
|
||||
int16 b; //accumulator
|
||||
Flag flaga;
|
||||
Flag flagb;
|
||||
uint16 tr; //temporary register
|
||||
uint16 trb; //temporary register
|
||||
Status sr; //status register
|
||||
uint16 dr; //data register
|
||||
uint16 tr; //temporary register
|
||||
uint16 trb; //temporary register
|
||||
Status sr; //status register
|
||||
uint16 dr; //data register
|
||||
uint16 si;
|
||||
uint16 so;
|
||||
} regs;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ auto V30MZ::disassemble(uint16 cs, uint16 ip, bool registers, bool bytes) -> str
|
|||
};
|
||||
auto readByteSigned = [&]() -> string {
|
||||
uint8 byte = fetch();
|
||||
return {"$", byte & 0x80 ? "-" : "+", hex(byte & 0x80 ? 256 - byte : byte, 2L)};
|
||||
return {"$", byte & 0x80 ? "-" : "+", hex(byte & 0x80 ? uint8(256 - byte) : byte, 2L)};
|
||||
};
|
||||
auto readRelativeByte = [&]() -> string {
|
||||
uint8 byte = fetch();
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ auto V30MZ::opMultiplySignedRegMemImm(Size size) {
|
|||
//45 inc bp
|
||||
//46 inc si
|
||||
//47 inc di
|
||||
auto V30MZ::opIncReg(uint16& reg) {
|
||||
auto V30MZ::opIncReg(uint16_t& reg) {
|
||||
reg++;
|
||||
}
|
||||
|
||||
|
|
@ -157,7 +157,7 @@ auto V30MZ::opIncReg(uint16& reg) {
|
|||
//4d dec bp
|
||||
//4e dec si
|
||||
//4f dec di
|
||||
auto V30MZ::opDecReg(uint16& reg) {
|
||||
auto V30MZ::opDecReg(uint16_t& reg) {
|
||||
reg--;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -132,11 +132,11 @@ auto V30MZ::opLeave() {
|
|||
r.bp = pop();
|
||||
}
|
||||
|
||||
auto V30MZ::opPushReg(uint16& reg) {
|
||||
auto V30MZ::opPushReg(uint16_t& reg) {
|
||||
push(reg);
|
||||
}
|
||||
|
||||
auto V30MZ::opPopReg(uint16& reg) {
|
||||
auto V30MZ::opPopReg(uint16_t& reg) {
|
||||
reg = pop();
|
||||
if(® == &r.ss) state.poll = false;
|
||||
}
|
||||
|
|
@ -185,7 +185,8 @@ auto V30MZ::opPopAll() {
|
|||
//68 push imm16
|
||||
//6a push imm8s
|
||||
auto V30MZ::opPushImm(Size size) {
|
||||
push(size == Word ? fetch(Word) : (int8_t)fetch(Byte));
|
||||
if(size == Byte) push((int8)fetch(Byte));
|
||||
if(size == Word) push(fetch(Word));
|
||||
}
|
||||
|
||||
auto V30MZ::opPopMem() {
|
||||
|
|
|
|||
|
|
@ -5,7 +5,10 @@
|
|||
auto V30MZ::opGroup1MemImm(Size size, bool sign) {
|
||||
modRM();
|
||||
auto mem = getMem(size);
|
||||
auto imm = sign ? (int8_t)fetch() : size == Byte ? fetch() : fetch(Word);
|
||||
uint16 imm = 0;
|
||||
if(sign) imm = (int8)fetch();
|
||||
else if(size == Byte) imm = fetch();
|
||||
else imm = fetch(Word);
|
||||
switch(modrm.reg) {
|
||||
case 0: setMem(size, alAdd(size, mem, imm)); break;
|
||||
case 1: setMem(size, alOr (size, mem, imm)); break;
|
||||
|
|
|
|||
|
|
@ -31,11 +31,11 @@ auto V30MZ::opMoveMemAcc(Size size) {
|
|||
write(size, segment(r.ds), fetch(Word), getAcc(size));
|
||||
}
|
||||
|
||||
auto V30MZ::opMoveRegImm(uint8& reg) {
|
||||
auto V30MZ::opMoveRegImm(uint8_t& reg) {
|
||||
reg = fetch(Byte);
|
||||
}
|
||||
|
||||
auto V30MZ::opMoveRegImm(uint16& reg) {
|
||||
auto V30MZ::opMoveRegImm(uint16_t& reg) {
|
||||
reg = fetch(Word);
|
||||
}
|
||||
|
||||
|
|
@ -44,7 +44,7 @@ auto V30MZ::opMoveMemImm(Size size) {
|
|||
setMem(size, fetch(size));
|
||||
}
|
||||
|
||||
auto V30MZ::opExchange(uint16& x, uint16& y) {
|
||||
auto V30MZ::opExchange(uint16_t& x, uint16_t& y) {
|
||||
wait(2);
|
||||
uint16 z = x;
|
||||
x = y;
|
||||
|
|
@ -65,7 +65,7 @@ auto V30MZ::opLoadEffectiveAddressRegMem() {
|
|||
setReg(Word, modrm.address);
|
||||
}
|
||||
|
||||
auto V30MZ::opLoadSegmentMem(uint16& reg) {
|
||||
auto V30MZ::opLoadSegmentMem(uint16_t& reg) {
|
||||
wait(5);
|
||||
modRM();
|
||||
reg = getMem(Word);
|
||||
|
|
|
|||
|
|
@ -18,14 +18,14 @@ auto V30MZ::setAcc(Size size, uint32 data) -> void {
|
|||
|
||||
//
|
||||
|
||||
V30MZ::Registers::Flags::operator uint16() const {
|
||||
V30MZ::Registers::Flags::operator uint16_t() const {
|
||||
return m << 15 | 1 << 14 | 1 << 13 | 1 << 12
|
||||
| v << 11 | d << 10 | i << 9 | b << 8
|
||||
| s << 7 | z << 6 | h << 4 | p << 2
|
||||
| 1 << 1 | c << 0;
|
||||
}
|
||||
|
||||
auto V30MZ::Registers::Flags::operator=(uint16 data) {
|
||||
auto V30MZ::Registers::Flags::operator=(uint16_t data) {
|
||||
m = (uint1)(data >> 15);
|
||||
v = (uint1)(data >> 11);
|
||||
d = (uint1)(data >> 10);
|
||||
|
|
|
|||
|
|
@ -250,10 +250,10 @@ auto V30MZ::instruction() -> void {
|
|||
case 0xcd: return opIntImm();
|
||||
case 0xce: return opInto();
|
||||
case 0xcf: return opReturnInt();
|
||||
case 0xd0: return opGroup2MemImm(Byte, 1);
|
||||
case 0xd1: return opGroup2MemImm(Word, 1);
|
||||
case 0xd2: return opGroup2MemImm(Byte, r.cl);
|
||||
case 0xd3: return opGroup2MemImm(Word, r.cl);
|
||||
case 0xd0: return opGroup2MemImm(Byte, (uint8)1);
|
||||
case 0xd1: return opGroup2MemImm(Word, (uint8)1);
|
||||
case 0xd2: return opGroup2MemImm(Byte, (uint8)r.cl);
|
||||
case 0xd3: return opGroup2MemImm(Word, (uint8)r.cl);
|
||||
case 0xd4: return opAdjustAfterMultiply();
|
||||
case 0xd5: return opAdjustAfterDivide();
|
||||
case 0xd6: return;
|
||||
|
|
|
|||
|
|
@ -108,8 +108,8 @@ struct V30MZ {
|
|||
auto opTestMemReg(Size);
|
||||
auto opTestAcc(Size);
|
||||
auto opMultiplySignedRegMemImm(Size);
|
||||
auto opIncReg(uint16&);
|
||||
auto opDecReg(uint16&);
|
||||
auto opIncReg(uint16_t&);
|
||||
auto opDecReg(uint16_t&);
|
||||
auto opSignExtendByte();
|
||||
auto opSignExtendWord();
|
||||
|
||||
|
|
@ -132,8 +132,8 @@ struct V30MZ {
|
|||
auto opInto();
|
||||
auto opEnter();
|
||||
auto opLeave();
|
||||
auto opPushReg(uint16&);
|
||||
auto opPopReg(uint16&);
|
||||
auto opPushReg(uint16_t&);
|
||||
auto opPopReg(uint16_t&);
|
||||
auto opPushFlags();
|
||||
auto opPopFlags();
|
||||
auto opPushAll();
|
||||
|
|
@ -175,13 +175,13 @@ struct V30MZ {
|
|||
auto opMoveSegMem();
|
||||
auto opMoveAccMem(Size);
|
||||
auto opMoveMemAcc(Size);
|
||||
auto opMoveRegImm(uint8&);
|
||||
auto opMoveRegImm(uint16&);
|
||||
auto opMoveRegImm(uint8_t&);
|
||||
auto opMoveRegImm(uint16_t&);
|
||||
auto opMoveMemImm(Size);
|
||||
auto opExchange(uint16&, uint16&);
|
||||
auto opExchange(uint16_t&, uint16_t&);
|
||||
auto opExchangeMemReg(Size);
|
||||
auto opLoadEffectiveAddressRegMem();
|
||||
auto opLoadSegmentMem(uint16&);
|
||||
auto opLoadSegmentMem(uint16_t&);
|
||||
|
||||
//instructions-string.cpp
|
||||
auto opInString(Size);
|
||||
|
|
@ -216,28 +216,28 @@ struct V30MZ {
|
|||
} modrm;
|
||||
|
||||
struct Registers {
|
||||
union { uint16 ax; struct { uint8 order_lsb2(al, ah); }; };
|
||||
union { uint16 cx; struct { uint8 order_lsb2(cl, ch); }; };
|
||||
union { uint16 dx; struct { uint8 order_lsb2(dl, dh); }; };
|
||||
union { uint16 bx; struct { uint8 order_lsb2(bl, bh); }; };
|
||||
uint16 sp;
|
||||
uint16 bp;
|
||||
uint16 si;
|
||||
uint16 di;
|
||||
uint16 es;
|
||||
uint16 cs;
|
||||
uint16 ss;
|
||||
uint16 ds;
|
||||
uint16 ip;
|
||||
union { uint16_t ax; struct { uint8_t order_lsb2(al, ah); }; };
|
||||
union { uint16_t cx; struct { uint8_t order_lsb2(cl, ch); }; };
|
||||
union { uint16_t dx; struct { uint8_t order_lsb2(dl, dh); }; };
|
||||
union { uint16_t bx; struct { uint8_t order_lsb2(bl, bh); }; };
|
||||
uint16_t sp;
|
||||
uint16_t bp;
|
||||
uint16_t si;
|
||||
uint16_t di;
|
||||
uint16_t es;
|
||||
uint16_t cs;
|
||||
uint16_t ss;
|
||||
uint16_t ds;
|
||||
uint16_t ip;
|
||||
|
||||
uint8* b[8]{&al, &cl, &dl, &bl, &ah, &ch, &dh, &bh};
|
||||
uint16* w[8]{&ax, &cx, &dx, &bx, &sp, &bp, &si, &di};
|
||||
uint16* s[8]{&es, &cs, &ss, &ds, &es, &cs, &ss, &ds};
|
||||
uint8_t* b[8]{&al, &cl, &dl, &bl, &ah, &ch, &dh, &bh};
|
||||
uint16_t* w[8]{&ax, &cx, &dx, &bx, &sp, &bp, &si, &di};
|
||||
uint16_t* s[8]{&es, &cs, &ss, &ds, &es, &cs, &ss, &ds};
|
||||
|
||||
struct Flags {
|
||||
//registers.cpp
|
||||
operator uint16() const;
|
||||
auto operator=(uint16 data);
|
||||
operator uint16_t() const;
|
||||
auto operator=(uint16_t data);
|
||||
|
||||
bool m; //mode
|
||||
bool v; //overflow
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ auto ICD2::read(uint addr, uint8 data) -> uint8 {
|
|||
|
||||
//LY counter
|
||||
if(addr == 0x6000) {
|
||||
uint y = min(143u, GameBoy::ppu.status.ly);
|
||||
uint y = min((uint8)143, GameBoy::ppu.status.ly);
|
||||
return (y & ~7) | write_bank;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ auto SPC7110::dcu_read() -> uint8 {
|
|||
break;
|
||||
}
|
||||
|
||||
uint seek = r480b & 1 ? r4807 : 1;
|
||||
uint seek = r480b & 1 ? r4807 : (uint8)1;
|
||||
while(seek--) decompressor->decode();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ struct CPU : Processor::R65816, Thread, public PPUcounter {
|
|||
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
uint8 wram[128 * 1024] = {0};
|
||||
uint8 wram[128 * 1024];
|
||||
vector<Thread*> coprocessors;
|
||||
|
||||
privileged:
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ auto CPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) -> void {
|
|||
dma_write(dma_transfer_valid(bbus, abus), 0x2100 | bbus, regs.mdr);
|
||||
} else {
|
||||
dma_add_clocks(4);
|
||||
regs.mdr = dma_transfer_valid(bbus, abus) ? bus.read(0x2100 | bbus, regs.mdr) : 0x00;
|
||||
regs.mdr = dma_transfer_valid(bbus, abus) ? bus.read(0x2100 | bbus, regs.mdr) : (uint8)0x00;
|
||||
dma_add_clocks(4);
|
||||
dma_write(dma_addr_valid(abus), abus, regs.mdr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@ struct {
|
|||
|
||||
//$43x5-$43x6
|
||||
union {
|
||||
uint16 transfer_size;
|
||||
uint16 indirect_addr;
|
||||
uint16_t transfer_size;
|
||||
uint16_t indirect_addr;
|
||||
};
|
||||
|
||||
//$43x7
|
||||
|
|
|
|||
|
|
@ -248,7 +248,7 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
}
|
||||
|
||||
if(id == ID::IPLROM) {
|
||||
stream.read(smp.iplrom, min(64u, stream.size()));
|
||||
stream.read((uint8_t*)smp.iplrom, min(64u, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::Manifest) cartridge.information.markup.cartridge = stream.text();
|
||||
|
|
@ -308,13 +308,13 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
|
||||
if(id == ID::EpsonRTC) {
|
||||
uint8 data[16] = {0};
|
||||
stream.read(data, min(stream.size(), sizeof data));
|
||||
stream.read((uint8_t*)data, min(stream.size(), sizeof data));
|
||||
epsonrtc.load(data);
|
||||
}
|
||||
|
||||
if(id == ID::SharpRTC) {
|
||||
uint8 data[16] = {0};
|
||||
stream.read(data, min(stream.size(), sizeof data));
|
||||
stream.read((uint8_t*)data, min(stream.size(), sizeof data));
|
||||
sharprtc.load(data);
|
||||
}
|
||||
|
||||
|
|
@ -363,17 +363,17 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
}
|
||||
|
||||
auto Interface::save(uint id, const stream& stream) -> void {
|
||||
if(id == ID::RAM) stream.write(cartridge.ram.data(), cartridge.ram.size());
|
||||
if(id == ID::EventRAM) stream.write(event.ram.data(), event.ram.size());
|
||||
if(id == ID::SA1IRAM) stream.write(sa1.iram.data(), sa1.iram.size());
|
||||
if(id == ID::SA1BWRAM) stream.write(sa1.bwram.data(), sa1.bwram.size());
|
||||
if(id == ID::SuperFXRAM) stream.write(superfx.ram.data(), superfx.ram.size());
|
||||
if(id == ID::RAM) stream.write((uint8_t*)cartridge.ram.data(), cartridge.ram.size());
|
||||
if(id == ID::EventRAM) stream.write((uint8_t*)event.ram.data(), event.ram.size());
|
||||
if(id == ID::SA1IRAM) stream.write((uint8_t*)sa1.iram.data(), sa1.iram.size());
|
||||
if(id == ID::SA1BWRAM) stream.write((uint8_t*)sa1.bwram.data(), sa1.bwram.size());
|
||||
if(id == ID::SuperFXRAM) stream.write((uint8_t*)superfx.ram.data(), superfx.ram.size());
|
||||
|
||||
if(id == ID::ArmDSPRAM) {
|
||||
for(auto n : range(16 * 1024)) stream.write(armdsp.programRAM[n]);
|
||||
}
|
||||
|
||||
if(id == ID::HitachiDSPRAM) stream.write(hitachidsp.ram.data(), hitachidsp.ram.size());
|
||||
if(id == ID::HitachiDSPRAM) stream.write((uint8_t*)hitachidsp.ram.data(), hitachidsp.ram.size());
|
||||
if(id == ID::HitachiDSPDRAM) {
|
||||
for(auto n : range(3072)) stream.writel(hitachidsp.dataRAM[n], 1);
|
||||
}
|
||||
|
|
@ -388,27 +388,27 @@ auto Interface::save(uint id, const stream& stream) -> void {
|
|||
if(id == ID::EpsonRTC) {
|
||||
uint8 data[16] = {0};
|
||||
epsonrtc.save(data);
|
||||
stream.write(data, sizeof data);
|
||||
stream.write((uint8_t*)data, sizeof data);
|
||||
}
|
||||
|
||||
if(id == ID::SharpRTC) {
|
||||
uint8 data[16] = {0};
|
||||
sharprtc.save(data);
|
||||
stream.write(data, sizeof data);
|
||||
stream.write((uint8_t*)data, sizeof data);
|
||||
}
|
||||
|
||||
if(id == ID::SPC7110RAM) stream.write(spc7110.ram.data(), spc7110.ram.size());
|
||||
if(id == ID::SDD1RAM) stream.write(sdd1.ram.data(), sdd1.ram.size());
|
||||
if(id == ID::OBC1RAM) stream.write(obc1.ram.data(), obc1.ram.size());
|
||||
if(id == ID::SPC7110RAM) stream.write((uint8_t*)spc7110.ram.data(), spc7110.ram.size());
|
||||
if(id == ID::SDD1RAM) stream.write((uint8_t*)sdd1.ram.data(), sdd1.ram.size());
|
||||
if(id == ID::OBC1RAM) stream.write((uint8_t*)obc1.ram.data(), obc1.ram.size());
|
||||
|
||||
if(id == ID::GameBoyRAM) {
|
||||
GameBoy::interface->save(GameBoy::ID::RAM, stream);
|
||||
}
|
||||
|
||||
if(id == ID::MCCRAM) stream.write(mcc.ram.data(), mcc.ram.size());
|
||||
if(id == ID::MCCRAM) stream.write((uint8_t*)mcc.ram.data(), mcc.ram.size());
|
||||
|
||||
if(id == ID::SufamiTurboSlotARAM) stream.write(sufamiturboA.ram.data(), sufamiturboA.ram.size());
|
||||
if(id == ID::SufamiTurboSlotBRAM) stream.write(sufamiturboB.ram.data(), sufamiturboB.ram.size());
|
||||
if(id == ID::SufamiTurboSlotARAM) stream.write((uint8_t*)sufamiturboA.ram.data(), sufamiturboA.ram.size());
|
||||
if(id == ID::SufamiTurboSlotBRAM) stream.write((uint8_t*)sufamiturboB.ram.data(), sufamiturboB.ram.size());
|
||||
}
|
||||
|
||||
auto Interface::unload() -> void {
|
||||
|
|
|
|||
|
|
@ -37,11 +37,11 @@ auto MappedRAM::copy(const stream& memory) -> void {
|
|||
//round size up to multiple of 256-bytes
|
||||
size_ = (memory.size() & ~255) + ((bool)(memory.size() & 255) << 8);
|
||||
data_ = new uint8[size_]();
|
||||
memory.read(data_, memory.size());
|
||||
memory.read((uint8_t*)data_, memory.size());
|
||||
}
|
||||
|
||||
auto MappedRAM::read(const stream& memory) -> void {
|
||||
memory.read(data_, min(memory.size(), size_));
|
||||
memory.read((uint8_t*)data_, min(memory.size(), size_));
|
||||
}
|
||||
|
||||
auto MappedRAM::write_protect(bool status) -> void { write_protect_ = status; }
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@ struct PPU : Thread, public PPUcounter {
|
|||
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
uint8 vram[64 * 1024] = {0};
|
||||
uint8 oam[544] = {0};
|
||||
uint8 cgram[512] = {0};
|
||||
uint8 vram[64 * 1024];
|
||||
uint8 oam[544];
|
||||
uint8 cgram[512];
|
||||
|
||||
privileged:
|
||||
uint ppu1_version = 1; //allowed: 1
|
||||
|
|
|
|||
|
|
@ -60,10 +60,10 @@ auto PPU::Screen::get_pixel_sub(bool hires) -> uint16 {
|
|||
if(math.transparent = (priority == 0)) math.sub.color = get_color(0);
|
||||
|
||||
if(!hires) return 0;
|
||||
if(!math.sub.color_enable) return math.main.color_enable ? math.sub.color : 0;
|
||||
if(!math.sub.color_enable) return math.main.color_enable ? math.sub.color : (uint16)0;
|
||||
|
||||
return addsub(
|
||||
math.main.color_enable ? math.sub.color : 0,
|
||||
math.main.color_enable ? math.sub.color : (uint16)0,
|
||||
math.addsub_mode ? math.main.color : fixed_color()
|
||||
);
|
||||
}
|
||||
|
|
@ -108,7 +108,7 @@ auto PPU::Screen::get_pixel_main() -> uint16 {
|
|||
|
||||
if(!self.window.output.sub.color_enable) math.sub.color_enable = false;
|
||||
math.main.color_enable = self.window.output.main.color_enable;
|
||||
if(!math.sub.color_enable) return math.main.color_enable ? math.main.color : 0;
|
||||
if(!math.sub.color_enable) return math.main.color_enable ? math.main.color : (uint16)0;
|
||||
|
||||
if(regs.addsub_mode && math.transparent) {
|
||||
math.addsub_mode = false;
|
||||
|
|
@ -119,7 +119,7 @@ auto PPU::Screen::get_pixel_main() -> uint16 {
|
|||
}
|
||||
|
||||
return addsub(
|
||||
math.main.color_enable ? math.main.color : 0,
|
||||
math.main.color_enable ? math.main.color : (uint16)0,
|
||||
math.addsub_mode ? math.sub.color : fixed_color()
|
||||
);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ struct SMP : Processor::SPC700, Thread {
|
|||
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
uint8 iplrom[64] = {0};
|
||||
uint8 apuram[64 * 1024] = {0};
|
||||
uint8 iplrom[64];
|
||||
uint8 apuram[64 * 1024];
|
||||
|
||||
privileged:
|
||||
struct {
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ auto Program::loadRequest(uint id, string filename, bool required) -> void {
|
|||
if(filename == "manifest.bml" && pathname && !pathname.find(".sys/")) {
|
||||
if(!file::exists(location) || settings["Library/IgnoreManifests"].boolean()) {
|
||||
if(auto manifest = execute("icarus", "--manifest", pathname)) {
|
||||
memorystream stream{(const uint8*)manifest.data(), manifest.size()};
|
||||
memorystream stream{(const uint8_t*)manifest.data(), manifest.size()};
|
||||
return emulator->load(id, stream);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ StateManager::StateManager(TabFrame* parent) : TabFrameItem(parent) {
|
|||
}
|
||||
|
||||
auto StateManager::doUpdateControls() -> void {
|
||||
vector<uint8> buffer;
|
||||
vector<uint8_t> buffer;
|
||||
if(auto item = stateList.selected()) {
|
||||
buffer = file::read(program->stateName(1 + item.offset(), true));
|
||||
}
|
||||
|
|
@ -43,7 +43,7 @@ auto StateManager::doUpdateControls() -> void {
|
|||
}
|
||||
|
||||
auto StateManager::doChangeSelected() -> void {
|
||||
vector<uint8> buffer;
|
||||
vector<uint8_t> buffer;
|
||||
if(auto item = stateList.selected()) {
|
||||
buffer = file::read(program->stateName(1 + item.offset(), true));
|
||||
if(buffer.size() >= 584) {
|
||||
|
|
|
|||
|
|
@ -43,10 +43,10 @@ struct CPU : Processor::V30MZ, Thread, IO {
|
|||
uint20 dmaSource;
|
||||
|
||||
//$0044-0045 DMA_DST
|
||||
uint16_ dmaTarget;
|
||||
uint16 dmaTarget;
|
||||
|
||||
//$0046-0047 DMA_LEN
|
||||
uint16_ dmaLength;
|
||||
uint16 dmaLength;
|
||||
|
||||
//$0048 DMA_CTRL
|
||||
bool dmaEnable;
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
auto CPU::portRead(uint16 addr) -> uint8 {
|
||||
//DMA_SRC
|
||||
if(addr == 0x0040) return r.dmaSource.b0;
|
||||
if(addr == 0x0041) return r.dmaSource.b1;
|
||||
if(addr == 0x0042) return r.dmaSource.b2;
|
||||
if(addr == 0x0040) return r.dmaSource.byte(0);
|
||||
if(addr == 0x0041) return r.dmaSource.byte(1);
|
||||
if(addr == 0x0042) return r.dmaSource.byte(2);
|
||||
|
||||
//DMA_DST
|
||||
if(addr == 0x0044) return r.dmaTarget.b0;
|
||||
if(addr == 0x0045) return r.dmaTarget.b1;
|
||||
if(addr == 0x0044) return r.dmaTarget.byte(0);
|
||||
if(addr == 0x0045) return r.dmaTarget.byte(1);
|
||||
|
||||
//DMA_LEN
|
||||
if(addr == 0x0046) return r.dmaLength.b0;
|
||||
if(addr == 0x0047) return r.dmaLength.b1;
|
||||
if(addr == 0x0046) return r.dmaLength.byte(0);
|
||||
if(addr == 0x0047) return r.dmaLength.byte(1);
|
||||
|
||||
//DMA_CTRL
|
||||
if(addr == 0x0048) return r.dmaEnable << 7 | r.dmaMode << 0;
|
||||
|
|
@ -47,22 +47,22 @@ auto CPU::portRead(uint16 addr) -> uint8 {
|
|||
|
||||
auto CPU::portWrite(uint16 addr, uint8 data) -> void {
|
||||
//DMA_SRC
|
||||
if(addr == 0x0040) { r.dmaSource.b0 = data & ~1; return; }
|
||||
if(addr == 0x0041) { r.dmaSource.b1 = data; return; }
|
||||
if(addr == 0x0042) { r.dmaSource.b2 = data; return; }
|
||||
if(addr == 0x0040) { r.dmaSource.byte(0) = data & ~1; return; }
|
||||
if(addr == 0x0041) { r.dmaSource.byte(1) = data; return; }
|
||||
if(addr == 0x0042) { r.dmaSource.byte(2) = data; return; }
|
||||
|
||||
//DMA_DST
|
||||
if(addr == 0x0044) { r.dmaTarget.b0 = data & ~1; return; }
|
||||
if(addr == 0x0045) { r.dmaTarget.b1 = data; return; }
|
||||
if(addr == 0x0044) { r.dmaTarget.byte(0) = data & ~1; return; }
|
||||
if(addr == 0x0045) { r.dmaTarget.byte(1) = data; return; }
|
||||
|
||||
//DMA_LEN
|
||||
if(addr == 0x0046) { r.dmaLength.b0 = data & ~1; return; }
|
||||
if(addr == 0x0047) { r.dmaLength.b1 = data; return; }
|
||||
if(addr == 0x0046) { r.dmaLength.byte(0) = data & ~1; return; }
|
||||
if(addr == 0x0047) { r.dmaLength.byte(1) = data; return; }
|
||||
|
||||
//DMA_CTRL
|
||||
if(addr == 0x0048) {
|
||||
r.dmaEnable = (uint1)(data >> 7);
|
||||
r.dmaMode = (uint1)(data >> 0);
|
||||
r.dmaEnable = data.bit(7);
|
||||
r.dmaMode = data.bit(0);
|
||||
if(r.dmaEnable) dmaTransfer();
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -119,17 +119,17 @@ auto Interface::load(uint id, const stream& stream) -> void {
|
|||
}
|
||||
|
||||
if(id == ID::ROM) {
|
||||
stream.read(cartridge.rom.data, min(cartridge.rom.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.rom.data, min(cartridge.rom.size, stream.size()));
|
||||
}
|
||||
|
||||
if(id == ID::RAM) {
|
||||
stream.read(cartridge.ram.data, min(cartridge.ram.size, stream.size()));
|
||||
stream.read((uint8_t*)cartridge.ram.data, min(cartridge.ram.size, stream.size()));
|
||||
}
|
||||
}
|
||||
|
||||
auto Interface::save(uint id, const stream& stream) -> void {
|
||||
if(id == ID::RAM) {
|
||||
stream.write(cartridge.ram.data, cartridge.ram.size);
|
||||
stream.write((uint8_t*)cartridge.ram.data, cartridge.ram.size);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ struct PPU : Thread, IO {
|
|||
auto portRead(uint16 addr) -> uint8 override;
|
||||
auto portWrite(uint16 addr, uint8 data) -> void override;
|
||||
|
||||
uint16 output[224 * 144] = {0};
|
||||
uint16_t output[224 * 144] = {0};
|
||||
|
||||
struct Status {
|
||||
uint vclk;
|
||||
|
|
|
|||
|
|
@ -49,22 +49,10 @@ static_assert(sizeof(float) >= 4, "float32_t is not of the correct size")
|
|||
static_assert(sizeof(double) >= 8, "float64_t is not of the correct size");
|
||||
static_assert(sizeof(long double) >= 10, "float80_t is not of the correct size");
|
||||
|
||||
//using int8 = int8_t;
|
||||
//using int16 = int16_t;
|
||||
//using int32 = int32_t;
|
||||
//using int64 = int64_t;
|
||||
using intmax = intmax_t;
|
||||
using intptr = intptr_t;
|
||||
|
||||
using uint = unsigned int;
|
||||
//using uint8 = uint8_t;
|
||||
//using uint16 = uint16_t;
|
||||
//using uint32 = uint32_t;
|
||||
//using uint64 = uint64_t;
|
||||
using uintmax = uintmax_t;
|
||||
using uintptr = uintptr_t;
|
||||
|
||||
#if defined(__SIZEOF_INT128__)
|
||||
//using int128 = int128_t;
|
||||
//using uint128 = uint128_t;
|
||||
#endif
|
||||
using uint = unsigned int;
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ using int4 = nall::Integer< 4>;
|
|||
using int5 = nall::Integer< 5>;
|
||||
using int6 = nall::Integer< 6>;
|
||||
using int7 = nall::Integer< 7>;
|
||||
using int8_= nall::Integer< 8>;
|
||||
using int8 = nall::Integer< 8>;
|
||||
using int9 = nall::Integer< 9>;
|
||||
using int10 = nall::Integer<10>;
|
||||
using int11 = nall::Integer<11>;
|
||||
|
|
@ -94,7 +94,7 @@ using int12 = nall::Integer<12>;
|
|||
using int13 = nall::Integer<13>;
|
||||
using int14 = nall::Integer<14>;
|
||||
using int15 = nall::Integer<15>;
|
||||
using int16_= nall::Integer<16>;
|
||||
using int16 = nall::Integer<16>;
|
||||
using int17 = nall::Integer<17>;
|
||||
using int18 = nall::Integer<18>;
|
||||
using int19 = nall::Integer<19>;
|
||||
|
|
@ -110,7 +110,7 @@ using int28 = nall::Integer<28>;
|
|||
using int29 = nall::Integer<29>;
|
||||
using int30 = nall::Integer<30>;
|
||||
using int31 = nall::Integer<31>;
|
||||
using int32_= nall::Integer<32>;
|
||||
using int32 = nall::Integer<32>;
|
||||
using int33 = nall::Integer<33>;
|
||||
using int34 = nall::Integer<34>;
|
||||
using int35 = nall::Integer<35>;
|
||||
|
|
@ -142,7 +142,7 @@ using int60 = nall::Integer<60>;
|
|||
using int61 = nall::Integer<61>;
|
||||
using int62 = nall::Integer<62>;
|
||||
using int63 = nall::Integer<63>;
|
||||
using int64_= nall::Integer<64>;
|
||||
using int64 = nall::Integer<64>;
|
||||
|
||||
using uint1 = nall::Natural< 1>;
|
||||
using uint2 = nall::Natural< 2>;
|
||||
|
|
@ -151,7 +151,7 @@ using uint4 = nall::Natural< 4>;
|
|||
using uint5 = nall::Natural< 5>;
|
||||
using uint6 = nall::Natural< 6>;
|
||||
using uint7 = nall::Natural< 7>;
|
||||
using uint8_= nall::Natural< 8>;
|
||||
using uint8 = nall::Natural< 8>;
|
||||
using uint9 = nall::Natural< 9>;
|
||||
using uint10 = nall::Natural<10>;
|
||||
using uint11 = nall::Natural<11>;
|
||||
|
|
@ -159,7 +159,7 @@ using uint12 = nall::Natural<12>;
|
|||
using uint13 = nall::Natural<13>;
|
||||
using uint14 = nall::Natural<14>;
|
||||
using uint15 = nall::Natural<15>;
|
||||
using uint16_= nall::Natural<16>;
|
||||
using uint16 = nall::Natural<16>;
|
||||
using uint17 = nall::Natural<17>;
|
||||
using uint18 = nall::Natural<18>;
|
||||
using uint19 = nall::Natural<19>;
|
||||
|
|
@ -175,7 +175,7 @@ using uint28 = nall::Natural<28>;
|
|||
using uint29 = nall::Natural<29>;
|
||||
using uint30 = nall::Natural<30>;
|
||||
using uint31 = nall::Natural<31>;
|
||||
using uint32_= nall::Natural<32>;
|
||||
using uint32 = nall::Natural<32>;
|
||||
using uint33 = nall::Natural<33>;
|
||||
using uint34 = nall::Natural<34>;
|
||||
using uint35 = nall::Natural<35>;
|
||||
|
|
@ -207,4 +207,4 @@ using uint60 = nall::Natural<60>;
|
|||
using uint61 = nall::Natural<61>;
|
||||
using uint62 = nall::Natural<62>;
|
||||
using uint63 = nall::Natural<63>;
|
||||
using uint64_= nall::Natural<64>;
|
||||
using uint64 = nall::Natural<64>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue