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Update to v106r72 release. 

byuu says:

For this WIP, I added more TLCS900H instructions. All of the
ADC,ADD,SBB/SBC,SUB,AND,OR,XOR.CP,PUSH,POP instructions are in.

Still an incredible amount of work left to do on this core ... it has all kinds
of novel instructions that aren't on any other processors.

Still no disassembler support yet, so I can't even test what I'm doing. Fun!
This commit is contained in:
Tim Allen 2019-01-05 18:04:27 +11:00
parent 1a889ae232
commit cb86cd116c
10 changed files with 548 additions and 204 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
higan/emulator/emulator.hpp
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@ -30,7 +30,7 @@ using namespace nall;
namespace Emulator { namespace Emulator {
static const string Name = "higan"; static const string Name = "higan";
static const string Version = "106.71"; static const string Version = "106.72";
static const string Author = "byuu"; static const string Author = "byuu";
static const string License = "GPLv3"; static const string License = "GPLv3";
static const string Website = "https://byuu.org/"; static const string Website = "https://byuu.org/";

85
higan/processor/tlcs900h/algorithms.cpp
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@ -1,32 +1,77 @@
template<> auto TLCS900H::algorithmAdd<Byte>(uint8 target, uint8 source, uint1 carry) -> uint8 { template<> auto TLCS900H::parity(Byte data) const -> bool {
data ^= data >> 4;
data ^= data >> 2;
data ^= data >> 1;
return !(data & 1);
}
template<> auto TLCS900H::parity(Word data) const -> bool {
data ^= data >> 8;
data ^= data >> 4;
data ^= data >> 2;
data ^= data >> 1;
return !(data & 1);
}
template<> auto TLCS900H::parity(Long data) const -> bool {
return Undefined;
}
//
template<typename Size> auto TLCS900H::algorithmAdd(Size target, Size source, uint1 carry) -> Size {
uint64 result = target + source + carry; uint64 result = target + source + carry;
CF = result.bit(8); CF = result.bit(Size::bits());
NF = 0; NF = 0;
VF = uint8(~(target ^ source) & (target ^ result)).bit(7); VF = Size(~(target ^ source) & (target ^ result)).negative();
HF = uint8(target ^ source ^ result).bit(4); HF = Size(target ^ source ^ result).bit(4);
ZF = uint8(result) == 0; if constexpr(isLong<Size>()) HF = Undefined;
SF = result.bit(7); ZF = Size(result).zero();
SF = result.negative();
return result; return result;
} }
template<> auto TLCS900H::algorithmAdd<Word>(uint16 target, uint16 source, uint1 carry) -> uint16 { template<typename Size> auto TLCS900H::algorithmAnd(Size target, Size source) -> Size {
uint64 result = target + source + carry; Size result = target & source;
CF = result.bit(16); CF = 0;
NF = 0; NF = 0;
VF = uint16(~(target ^ source) & (target ^ result)).bit(15); VF = parity(result);
HF = uint16(target ^ source ^ result).bit(4); HF = 1;
ZF = uint16(result) == 0; ZF = result.zero();
SF = result.bit(15); SF = result.negative();
return result; return result;
} }
template<> auto TLCS900H::algorithmAdd<Long>(uint32 target, uint32 source, uint1 carry) -> uint32 { template<typename Size> auto TLCS900H::algorithmOr(Size target, Size source) -> Size {
uint64 result = target + source + carry; Size result = target | source;
CF = result.bit(32); CF = 0;
NF = 0; NF = 0;
VF = uint32(~(target ^ source) & (target ^ result)).bit(31); VF = parity(result);
HF = undefined; HF = 0;
ZF = uint32(result) == 0; ZF = result.zero();
SF = result.bit(31); SF = result.negative();
return result;
}
template<typename Size> auto TLCS900H::algorithmSubtract(Size target, Size source, uint1 carry) -> Size {
uint64 result = target - source - carry;
CF = result.bit(Size::bits());
NF = 1;
VF = Size((target ^ source) & (target ^ result)).negative();
HF = Size(target ^ source ^ result).bit(4);
if constexpr(isLong<Size>()) HF = Undefined;
ZF = Size(result).zero();
SF = result.negative();
return result;
}
template<typename Size> auto TLCS900H::algorithmXor(Size target, Size source) -> Size {
Size result = target ^ source;
CF = 0;
NF = 0;
VF = parity(result);
HF = 0;
ZF = result.zero();
SF = result.negative();
return result; return result;
} }

20
higan/processor/tlcs900h/conditions.cpp Normal file
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@ -0,0 +1,20 @@
auto TLCS900H::condition(uint4 code) -> bool {
switch(code) {
case 0: return 0 == 1; //F (false)
case 1: return (SF ^ VF) == 1; //LT (signed less than)
case 2: return (ZF | (SF ^ VF)) == 1; //LE (signed less than or equal)
case 3: return (CF | ZF) == 1; //ULE (unsigned less than or equal)
case 4: return VF == 1; //OV (overflow)
case 5: return SF == 1; //MI (minus)
case 6: return ZF == 1; //EQ (equal)
case 7: return CF == 1; //ULT (unsigned less than)
case 8: return 0 == 0; //T (true)
case 9: return (SF ^ VF) == 0; //GE (signed greater than or equal)
case 10: return (ZF | (SF ^ VF)) == 0; //GT (signed greater than)
case 11: return (CF | ZF) == 0; //UGT (unsigned greater than)
case 12: return VF == 0; //NOV (no overflow)
case 13: return SF == 0; //PL (plus)
case 14: return ZF == 0; //NE (not equal)
case 15: return CF == 0; //UGE (unsigned greater than or equal)
} unreachable;
}

189
higan/processor/tlcs900h/instruction.cpp
View File

@ -1,14 +1,45 @@
template<> auto TLCS900H::registerLookup<Byte>(uint3 code) -> Register {
return {0xe0 | code >> 1 << 2 | code & 1 ^ 1}; //W, A, B, C, D, E, H, L
}
template<> auto TLCS900H::registerLookup<Word>(uint3 code) -> Register {
return {0xe0 | code << 2}; //WA, BC, DE, HL, IX, IY, IZ, SP
}
template<> auto TLCS900H::registerLookup<Long>(uint3 code) -> Register {
return {0xe0 | code << 2}; //XWA, XBC, XDE, XHL, XIX, XIY, XIZ, XSP
}
auto TLCS900H::instruction() -> void { auto TLCS900H::instruction() -> void {
auto data = fetch(); auto data = fetch();
static const Register registers[] = {W, A, B, C, D, E, H, L};
Register register; Register register;
Memory memory; Memory memory;
switch(data) { switch(data) {
case 0x00: return instructionNoOperation(); case 0x00: return instructionNoOperation();
case 0x04: return; //undefined case 0x02: return instructionPush<Word>(r.sr);
case 0x03: return instructionPop<Word>(r.sr);
case 0x04: return (void)Undefined;
case 0x09: return instructionPush<Byte>(Immediate{fetch<Byte>()});
case 0x0b: return instructionPush<Word>(Immediate{fetch<Word>()});
case 0x12: return instructionComplementCarry(); case 0x12: return instructionComplementCarry();
case 0x1f: return; //undefined case 0x14: return instructionPush<Byte>(A);
case 0x15: return instructionPop<Byte>(A);
case 0x18: return instructionPush<Byte>(r.sr.f);
case 0x19: return instructionPop<Byte>(r.sr.f);
case 0x1f: return (void)Undefined;
case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
return instructionPush<Word>(registerLookup<Word>(data));
case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
return instructionPush<Long>(registerLookup<Long>(data));
case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
return instructionPop<Word>(registerLookup<Word>(data));
case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
return instructionPop<Long>(registerLookup<Long>(data));
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
memory = {read<Long>(register)}; memory = {read<Long>(register)};
@ -53,36 +84,37 @@ auto TLCS900H::instruction() -> void {
return instructionSourceMemory<Byte>(memory); return instructionSourceMemory<Byte>(memory);
case 0xc3: case 0xc3:
data = fetch(); data = fetch();
memory = {read<Long>(Register{data & ~3})}; memory = {read<Long>(Register{data})};
if((data & 3) == 1) memory.value += (int16)fetch<uint16>(); if((data & 3) == 1) memory.value += (int16)fetch<uint16>();
if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()}); if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()});
if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch() & ~1}); if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch()});
return instructionSourceMemory<Byte>(memory); return instructionSourceMemory<Byte>(memory);
case 0xc4: case 0xc4:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4);
if((data & 3) == 3) Undefined;
memory = {read<Long>(register)}; memory = {read<Long>(register)};
return instructionSourceMemory<Byte>(memory); return instructionSourceMemory<Byte>(memory);
case 0xc5: case 0xc5:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
memory = {read<Long>(register)}; memory = {read<Long>(register)};
instructionSourceMemory<Byte>(memory); instructionSourceMemory<Byte>(memory);
if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4);
if((data & 3) == 3) Undefined;
return; return;
case 0xc6: case 0xc6:
//undefined return (void)Undefined;
return;
case 0xc7: case 0xc7:
register = {fetch()}; register = {fetch()};
return instructionRegister<Byte>(register); return instructionRegister<Byte>(register);
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
register = registers[data & 7]; register = registerLookup<Byte>(data);
return instructionRegister<Byte>(register); return instructionRegister<Byte>(register);
case 0xd0: case 0xd0:
@ -96,36 +128,37 @@ auto TLCS900H::instruction() -> void {
return instructionSourceMemory<Word>(memory); return instructionSourceMemory<Word>(memory);
case 0xd3: case 0xd3:
data = fetch(); data = fetch();
memory = {read<Long>(Register{data & ~3})}; memory = {read<Long>(Register{data})};
if((data & 3) == 1) memory.value += (int16)fetch<uint16>(); if((data & 3) == 1) memory.value += (int16)fetch<uint16>();
if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()}); if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()});
if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch() & ~1}); if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch()});
return instructionSourceMemory<Word>(memory); return instructionSourceMemory<Word>(memory);
case 0xd4: case 0xd4:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4);
if((data & 3) == 3) Undefined;
memory = {read<Long>(register)}; memory = {read<Long>(register)};
return instructionSourceMemory<Word>(memory); return instructionSourceMemory<Word>(memory);
case 0xd5: case 0xd5:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
memory = {read<Long>(register)}; memory = {read<Long>(register)};
instructionSourceMemory<Word>(memory); instructionSourceMemory<Word>(memory);
if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4);
if((data & 3) == 3) Undefined;
return; return;
case 0xd6: case 0xd6:
//undefined return (void)Undefined;
return;
case 0xd7: case 0xd7:
register = {fetch() & ~1}; register = {fetch()};
return instructionRegister<Word>(register); return instructionRegister<Word>(register);
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf: case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
register = registers[data & 7]; register = registerLookup<Word>(data);
return instructionRegister<Word>(register); return instructionRegister<Word>(register);
case 0xe0: case 0xe0:
@ -139,36 +172,37 @@ auto TLCS900H::instruction() -> void {
return instructionSourceMemory<Long>(memory); return instructionSourceMemory<Long>(memory);
case 0xe3: case 0xe3:
data = fetch(); data = fetch();
memory = {read<Long>(Register{data & ~3})}; memory = {read<Long>(Register{data})};
if((data & 3) == 1) memory.value += (int16)fetch<uint16>(); if((data & 3) == 1) memory.value += (int16)fetch<uint16>();
if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()}); if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()});
if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch() & ~1}); if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch()});
return instructionSourceMemory<Long>(memory); return instructionSourceMemory<Long>(memory);
case 0xe4: case 0xe4:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4);
if((data & 3) == 3) Undefined;
memory = {read<Long>(register)}; memory = {read<Long>(register)};
return instructionSourceMemory<Long>(memory); return instructionSourceMemory<Long>(memory);
case 0xe5: case 0xe5:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
memory = {read<Long>(register)}; memory = {read<Long>(register)};
instructionSourceMemory<Long>(memory); instructionSourceMemory<Long>(memory);
if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4);
if((data & 3) == 3) Undefined;
return; return;
case 0xe6: case 0xe6:
//undefined return (void)Undefined;
return;
case 0xe7: case 0xe7:
register = {fetch() & ~3}; register = {fetch()};
return instructionRegister<Long>(register); return instructionRegister<Long>(register);
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef: case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
register = registers[data & 7]; register = registerLookup<Long>(data);
return instructionRegister<Long>(register); return instructionRegister<Long>(register);
case 0xf0: case 0xf0:
@ -182,31 +216,32 @@ auto TLCS900H::instruction() -> void {
return instructionTargetMemory(memory); return instructionTargetMemory(memory);
case 0xf3: case 0xf3:
data = fetch(); data = fetch();
memory = {read<Long>(Register{data & ~3})}; memory = {read<Long>(Register{data})};
if((data & 3) == 1) memory.value += (int16)fetch<uint16>(); if((data & 3) == 1) memory.value += (int16)fetch<uint16>();
if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()}); if((data & 3) == 2) memory.value += (int8)read<Byte>(Register{fetch()});
if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch() & ~1}); if((data & 3) == 3) memory.value += (int16)read<Word>(Register{fetch()});
return instructionTargetMemory(memory); return instructionTargetMemory(memory);
case 0xf4: case 0xf4:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) - 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) - 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) - 4);
if((data & 3) == 3) Undefined;
memory = {read<Long>(register)}; memory = {read<Long>(register)};
return instructionTargetMemory(memory); return instructionTargetMemory(memory);
case 0xf5: case 0xf5:
data = fetch(); data = fetch();
register = {data & ~3}; register = {data};
memory = {read<Long>(register)}; memory = {read<Long>(register)};
instructionTargetMemory(memory); instructionTargetMemory(memory);
if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1); if((data & 3) == 0) write<Long>(register, read<Long>(register) + 1);
if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2); if((data & 3) == 1) write<Long>(register, read<Long>(register) + 2);
if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4); if((data & 3) == 2) write<Long>(register, read<Long>(register) + 4);
if((data & 3) == 3) Undefined;
return; return;
case 0xf6: case 0xf7: case 0xf6: case 0xf7:
//undefined return (void)Undefined;
return;
case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
return instructionSoftwareInterrupt(Immediate{data.bits(0,2)}); return instructionSoftwareInterrupt(Immediate{data.bits(0,2)});
@ -214,38 +249,102 @@ auto TLCS900H::instruction() -> void {
} }
template<typename Size> template<typename Size>
auto TLCS900H::instructionRegister(Register input) -> void { auto TLCS900H::instructionRegister(Register register) -> void {
auto data = fetch(); auto data = fetch();
static const Register registers[] = {W, A, B, C, D, E, H, L};
Register register = registers[data.bits(0,2)];
switch(data) { switch(data) {
case 0x04: return instructionPush<Size>(register);
case 0x05: return instructionPop<Size>(register);
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
return instructionAdd<Size>(register, input); return instructionAdd<Size>(registerLookup<Size>(data), register);
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
return instructionAddCarry<Size>(register, input); return instructionAddCarry<Size>(registerLookup<Size>(data), register);
case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
return instructionSubtract<Size>(registerLookup<Size>(data), register);
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
return instructionSubtractCarry<Size>(registerLookup<Size>(data), register);
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
return instructionAnd<Size>(registerLookup<Size>(data), register);
case 0xc8: return instructionAdd<Size>(register, Immediate{fetch<Size>()});
case 0xc9: return instructionAddCarry<Size>(register, Immediate{fetch<Size>()});
case 0xca: return instructionSubtract<Size>(register, Immediate{fetch<Size>()});
case 0xcb: return instructionSubtractCarry<Size>(register, Immediate{fetch<Size>()});
case 0xcc: return instructionAnd<Size>(register, Immediate{fetch<Size>()});
case 0xcd: return instructionXor<Size>(register, Immediate{fetch<Size>()});
case 0xce: return instructionOr<Size>(register, Immediate{fetch<Size>()});
case 0xcf: return instructionCompare<Size>(register, Immediate{fetch<Size>()});
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
return instructionXor<Size>(registerLookup<Size>(data), register);
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
return instructionCompare<Size>(register, Immediate{data & 7});
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
return instructionOr<Size>(registerLookup<Size>(data), register);
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
return instructionCompare<Size>(registerLookup<Size>(data), register);
} }
} }
template<typename Size> template<typename Size>
auto TLCS900H::instructionSourceMemory(Memory input) -> void { auto TLCS900H::instructionSourceMemory(Memory memory) -> void {
auto data = fetch(); auto data = fetch();
static const Register registers[] = {W, A, B, C, D, E, H, L};
Register register = registers[data.bits(0,2)];
switch(data) { switch(data) {
case 0x04:
if constexpr(isLong<Size>()) return (void)Undefined;
return instructionPush<Size>(memory);
case 0x38:
if constexpr(isLong<Size>()) return (void)Undefined;
return instructionAdd<Size>(memory, Immediate{fetch<Size>()});
case 0x39:
if constexpr(isLong<Size>()) return (void)Undefined;
return instructionAddCarry<Size>(memory, Immediate{fetch<Size>()});
case 0x3a:
if constexpr(isLong<Size>()) return (void)Undefined;
return instructionSubtract<Size>(memory, Immediate{fetch<Size>()});
case 0x3b:
if constexpr(isLong<Size>()) return (void)Undefined;
return instructionSubtractCarry<Size>(memory, Immediate{fetch<Size>()});
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
return instructionAdd<Size>(register, input); return instructionAdd<Size>(registerLookup<Size>(data), memory);
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
return instructionAdd<Size>(memory, registerLookup<Size>(data));
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
return instructionAddCarry<Size>(register, input); return instructionAddCarry<Size>(registerLookup<Size>(data), memory);
case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
return instructionAddCarry<Size>(memory, registerLookup<Size>(data));
case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
return instructionSubtract<Size>(registerLookup<Size>(data), memory);
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
return instructionSubtract<Size>(memory, registerLookup<Size>(data));
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
return instructionSubtractCarry<Size>(registerLookup<Size>(data), memory);
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
return instructionSubtractCarry<Size>(memory, registerLookup<Size>(data));
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
return instructionAnd<Size>(registerLookup<Size>(data), memory);
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
return instructionAnd<Size>(memory, registerLookup<Size>(data));
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
return instructionXor<Size>(registerLookup<Size>(data), memory);
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
return instructionXor<Size>(memory, registerLookup<Size>(data));
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
return instructionOr<Size>(registerLookup<Size>(data), memory);
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
return instructionOr<Size>(memory, registerLookup<Size>(data));
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
return instructionCompare<Size>(registerLookup<Size>(data), memory);
case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
return instructionCompare<Size>(memory, registerLookup<Size>(data));
} }
} }
auto TLCS900H::instructionTargetMemory(Memory input) -> void { auto TLCS900H::instructionTargetMemory(Memory memory) -> void {
auto data = fetch(); auto data = fetch();
static const Register registers[] = {W, A, B, C, D, E, H, L};
Register register = registers[data.bits(0,2)];
switch(data) { switch(data) {
case 0x04: return instructionPop<Byte>(memory);
case 0x06: return instructionPop<Word>(memory);
} }
} }

56
higan/processor/tlcs900h/instructions.cpp
View File

@ -1,11 +1,27 @@
#define read read<Size>
#define write write<Size>
#define push push<Size>
#define pop pop<Size>
#define algorithm(name, ...) algorithm##name<Size>(__VA_ARGS__)
template<typename Size, typename Target, typename Source> template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionAdd(Target target, Source source) -> void { auto TLCS900H::instructionAdd(Target target, Source source) -> void {
write<Size>(target, algorithmAdd<Size>(read<Size>(target), read<Size>(source))); write(target, algorithm(Add, read(target), read(source)));
} }
template<typename Size, typename Target, typename Source> template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionAddCarry(Target target, Source source) -> void { auto TLCS900H::instructionAddCarry(Target target, Source source) -> void {
write<Size>(target, algorithmAdd<Size>(read<Size>(target), read<Size>(source), CF)); write(target, algorithm(Add, read(target), read(source), CF));
}
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionAnd(Target target, Source source) -> void {
write(target, algorithm(And, read(target), read(source)));
}
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionCompare(Target target, Source source) -> void {
algorithm(Subtract, read(target), read(source));
} }
auto TLCS900H::instructionComplementCarry() -> void { auto TLCS900H::instructionComplementCarry() -> void {
@ -15,5 +31,41 @@ auto TLCS900H::instructionComplementCarry() -> void {
auto TLCS900H::instructionNoOperation() -> void { auto TLCS900H::instructionNoOperation() -> void {
} }
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionOr(Target target, Source source) -> void {
write(target, algorithm(Or, read(target), read(source)));
}
template<typename Size, typename Target>
auto TLCS900H::instructionPop(Target target) -> void {
write(target, pop());
}
template<typename Size, typename Source>
auto TLCS900H::instructionPush(Source source) -> void {
push(read(source));
}
auto TLCS900H::instructionSoftwareInterrupt(Immediate interrupt) -> void { auto TLCS900H::instructionSoftwareInterrupt(Immediate interrupt) -> void {
} }
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionSubtract(Target target, Source source) -> void {
write(target, algorithm(Subtract, read(target), read(source)));
}
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionSubtractCarry(Target target, Source source) -> void {
write(target, algorithm(Subtract, read(target), read(source), CF));
}
template<typename Size, typename Target, typename Source>
auto TLCS900H::instructionXor(Target target, Source source) -> void {
write(target, algorithm(Xor, read(target), read(source)));
}
#undef read
#undef write
#undef push
#undef pop
#undef algorithm

48
higan/processor/tlcs900h/memory.cpp
View File

@ -10,16 +10,58 @@ template<> auto TLCS900H::fetch<uint16>() -> uint16 {
template<> auto TLCS900H::fetch<uint24>() -> uint24 { template<> auto TLCS900H::fetch<uint24>() -> uint24 {
uint24 data = fetch<uint8>(); uint24 data = fetch<uint8>();
data |= fetch<uint8>() << 8; data |= fetch<uint8>() << 8;
return data | fetch<uint8>() << 16; return data |= fetch<uint8>() << 16;
} }
template<> auto TLCS900H::fetch<uint32>() -> uint32 { template<> auto TLCS900H::fetch<uint32>() -> uint32 {
uint32 data = fetch<uint8>(); uint32 data = fetch<uint8>();
data |= fetch<uint8>() << 8; data |= fetch<uint8>() << 8;
data |= fetch<uint8>() << 16; data |= fetch<uint8>() << 16;
return data | fetch<uint8>() << 24; return data |= fetch<uint8>() << 24;
} }
//
#define XSP r.xsp.l.l0
template<> auto TLCS900H::push<Byte>(Byte data) -> void {
write(--XSP, data);
}
template<> auto TLCS900H::push<Word>(Word data) -> void {
write(--XSP, data >> 0);
write(--XSP, data >> 8);
}
template<> auto TLCS900H::push<Long>(Long data) -> void {
write(--XSP, data >> 0);
write(--XSP, data >> 8);
write(--XSP, data >> 16);
write(--XSP, data >> 24);
}
//
template<> auto TLCS900H::pop<Byte>() -> Byte {
return read(XSP++);
}
template<> auto TLCS900H::pop<Word>() -> Word {
uint16 data = read(XSP++) << 0;
return data | read(XSP++) << 8;
}
template<> auto TLCS900H::pop<Long>() -> Long {
uint32 data = read(XSP++) << 0;
data |= read(XSP++) << 8;
data |= read(XSP++) << 16;
return data |= read(XSP++) << 24;
}
#undef XSP
//
template<> auto TLCS900H::read<Byte>(Memory memory) -> uint8 { template<> auto TLCS900H::read<Byte>(Memory memory) -> uint8 {
uint32 address = memory.value; uint32 address = memory.value;
return read(address); return read(address);
@ -36,7 +78,7 @@ template<> auto TLCS900H::read<Long>(Memory memory) -> uint32 {
uint32 data = read(address + 0) << 0; uint32 data = read(address + 0) << 0;
data |= read(address + 1) << 8; data |= read(address + 1) << 8;
data |= read(address + 2) << 16; data |= read(address + 2) << 16;
return data | read(address + 3) << 24; return data |= read(address + 3) << 24;
} }
template<> auto TLCS900H::write<Byte>(Memory memory, uint8 data) -> void { template<> auto TLCS900H::write<Byte>(Memory memory, uint8 data) -> void {

174
higan/processor/tlcs900h/registers.cpp
View File

@ -1,11 +1,11 @@
#define PC r.pc.l.l0 #define PC r.pc.l.l0
#define CF r.sr.f.c #define CF r.sr.f.c
#define NF r.sr.f.n #define NF r.sr.f.n
#define VF r.sr.f.v #define VF r.sr.f.v
#define HF r.sr.f.h #define HF r.sr.f.h
#define ZF r.sr.f.z #define ZF r.sr.f.z
#define SF r.sr.f.s #define SF r.sr.f.s
#define RFP r.sr.rfp #define RFP r.sr.rfp
#define RFPP r.sr.rfpp #define RFPP r.sr.rfpp
@ -14,74 +14,74 @@
#define a RFP #define a RFP
#define p RFPP #define p RFPP
template<> auto TLCS900H::map<Byte>(Register register) -> maybe<uint8&> { template<> auto TLCS900H::map<Byte>(Register register) -> maybe<Byte&> {
switch(register.value) { switch(register.value) {
#define r(id, name) case id: return r.name; #define r(id, name) case id: return r.name;
r(RA0, xwa[0].b.b0) r(RW0, xwa[0].b.b1) r(QA0, xwa[0].b.b2) r(QW0, xwa[0].b.b3) r(0x00, xwa[0].b.b0) r(0x01, xwa[0].b.b1) r(0x02, xwa[0].b.b2) r(0x03, xwa[0].b.b3)
r(RC0, xbc[0].b.b0) r(RB0, xbc[0].b.b1) r(QC0, xbc[0].b.b2) r(QB0, xbc[0].b.b3) r(0x04, xbc[0].b.b0) r(0x05, xbc[0].b.b1) r(0x06, xbc[0].b.b2) r(0x07, xbc[0].b.b3)
r(RE0, xde[0].b.b0) r(RD0, xde[0].b.b1) r(QE0, xde[0].b.b2) r(QD0, xde[0].b.b3) r(0x08, xde[0].b.b0) r(0x09, xde[0].b.b1) r(0x0a, xde[0].b.b2) r(0x0b, xde[0].b.b3)
r(RL0, xhl[0].b.b0) r(RH0, xhl[0].b.b1) r(QL0, xhl[0].b.b2) r(QH0, xhl[0].b.b3) r(0x0c, xhl[0].b.b0) r(0x0d, xhl[0].b.b1) r(0x0e, xhl[0].b.b2) r(0x0f, xhl[0].b.b3)
r(RA1, xwa[1].b.b0) r(RW1, xwa[1].b.b1) r(QA1, xwa[1].b.b2) r(QW1, xwa[1].b.b3) r(0x10, xwa[1].b.b0) r(0x11, xwa[1].b.b1) r(0x12, xwa[1].b.b2) r(0x13, xwa[1].b.b3)
r(RC1, xbc[1].b.b0) r(RB1, xbc[1].b.b1) r(QC1, xbc[1].b.b2) r(QB1, xbc[1].b.b3) r(0x14, xbc[1].b.b0) r(0x15, xbc[1].b.b1) r(0x16, xbc[1].b.b2) r(0x17, xbc[1].b.b3)
r(RE1, xde[1].b.b0) r(RD1, xde[1].b.b1) r(QE1, xde[1].b.b2) r(QD1, xde[1].b.b3) r(0x18, xde[1].b.b0) r(0x19, xde[1].b.b1) r(0x1a, xde[1].b.b2) r(0x1b, xde[1].b.b3)
r(RL1, xhl[1].b.b0) r(RH1, xhl[1].b.b1) r(QL1, xhl[1].b.b2) r(QH1, xhl[1].b.b3) r(0x1c, xhl[1].b.b0) r(0x1d, xhl[1].b.b1) r(0x1e, xhl[1].b.b2) r(0x1f, xhl[1].b.b3)
r(RA2, xwa[2].b.b0) r(RW2, xwa[2].b.b1) r(QA2, xwa[2].b.b2) r(QW2, xwa[2].b.b3) r(0x20, xwa[2].b.b0) r(0x21, xwa[2].b.b1) r(0x22, xwa[2].b.b2) r(0x23, xwa[2].b.b3)
r(RC2, xbc[2].b.b0) r(RB2, xbc[2].b.b1) r(QC2, xbc[2].b.b2) r(QB2, xbc[2].b.b3) r(0x24, xbc[2].b.b0) r(0x25, xbc[2].b.b1) r(0x26, xbc[2].b.b2) r(0x27, xbc[2].b.b3)
r(RE2, xde[2].b.b0) r(RD2, xde[2].b.b1) r(QE2, xde[2].b.b2) r(QD2, xde[2].b.b3) r(0x28, xde[2].b.b0) r(0x29, xde[2].b.b1) r(0x2a, xde[2].b.b2) r(0x2b, xde[2].b.b3)
r(RL2, xhl[2].b.b0) r(RH2, xhl[2].b.b1) r(QL2, xhl[2].b.b2) r(QH2, xhl[2].b.b3) r(0x2c, xhl[2].b.b0) r(0x2d, xhl[2].b.b1) r(0x2e, xhl[2].b.b2) r(0x2f, xhl[2].b.b3)
r(RA3, xwa[3].b.b0) r(RW3, xwa[3].b.b1) r(QA3, xwa[3].b.b2) r(QW3, xwa[3].b.b3) r(0x30, xwa[3].b.b0) r(0x31, xwa[3].b.b1) r(0x32, xwa[3].b.b2) r(0x33, xwa[3].b.b3)
r(RC3, xbc[3].b.b0) r(RB3, xbc[3].b.b1) r(QC3, xbc[3].b.b2) r(QB3, xbc[3].b.b3) r(0x34, xbc[3].b.b0) r(0x35, xbc[3].b.b1) r(0x36, xbc[3].b.b2) r(0x37, xbc[3].b.b3)
r(RE3, xde[3].b.b0) r(RD3, xde[3].b.b1) r(QE3, xde[3].b.b2) r(QD3, xde[3].b.b3) r(0x38, xde[3].b.b0) r(0x39, xde[3].b.b1) r(0x3a, xde[3].b.b2) r(0x3b, xde[3].b.b3)
r(RL3, xhl[3].b.b0) r(RH3, xhl[3].b.b1) r(QL3, xhl[3].b.b2) r(QH3, xhl[3].b.b3) r(0x3c, xhl[3].b.b0) r(0x3d, xhl[3].b.b1) r(0x3e, xhl[3].b.b2) r(0x3f, xhl[3].b.b3)
r( AP, xwa[p].b.b0) r( WP, xwa[p].b.b1) r(QAP, xwa[p].b.b2) r(QWP, xwa[p].b.b3) r(0xd0, xwa[p].b.b0) r(0xd1, xwa[p].b.b1) r(0xd2, xwa[p].b.b2) r(0xd3, xwa[p].b.b3)
r( CP, xbc[p].b.b0) r( BP, xbc[p].b.b1) r(QCP, xbc[p].b.b2) r(QBP, xbc[p].b.b3) r(0xd4, xbc[p].b.b0) r(0xd5, xbc[p].b.b1) r(0xd6, xbc[p].b.b2) r(0xd7, xbc[p].b.b3)
r( EP, xde[p].b.b0) r( DP, xde[p].b.b1) r(QEP, xde[p].b.b2) r(QDP, xde[p].b.b3) r(0xd8, xde[p].b.b0) r(0xd9, xde[p].b.b1) r(0xda, xde[p].b.b2) r(0xdb, xde[p].b.b3)
r( LP, xhl[p].b.b0) r( HP, xhl[p].b.b1) r(QLP, xhl[p].b.b2) r(QHP, xhl[p].b.b3) r(0xdc, xhl[p].b.b0) r(0xdd, xhl[p].b.b1) r(0xde, xhl[p].b.b2) r(0xdf, xhl[p].b.b3)
r( A, xwa[a].b.b0) r( W, xwa[a].b.b1) r(QA, xwa[a].b.b2) r(QW, xwa[a].b.b3) r(0xe0, xwa[a].b.b0) r(0xe1, xwa[a].b.b1) r(0xe2, xwa[a].b.b2) r(0xe3, xwa[a].b.b3)
r( C, xbc[a].b.b0) r( B, xbc[a].b.b1) r(QC, xbc[a].b.b2) r(QB, xbc[a].b.b3) r(0xe4, xbc[a].b.b0) r(0xe5, xbc[a].b.b1) r(0xe6, xbc[a].b.b2) r(0xe7, xbc[a].b.b3)
r( E, xde[a].b.b0) r( D, xde[a].b.b1) r(QE, xde[a].b.b2) r(QD, xde[a].b.b3) r(0xe8, xde[a].b.b0) r(0xe9, xde[a].b.b1) r(0xea, xde[a].b.b2) r(0xeb, xde[a].b.b3)
r( L, xhl[a].b.b0) r( H, xhl[a].b.b1) r(QL, xhl[a].b.b2) r(QH, xhl[a].b.b3) r(0xec, xhl[a].b.b0) r(0xed, xhl[a].b.b1) r(0xee, xhl[a].b.b2) r(0xef, xhl[a].b.b3)
r(IXL, xix.b.b0) r(IXH, xix.b.b1) r(QIXL, xix.b.b2) r(QIXH, xix.b.b3) r(0xf0, xix .b.b0) r(0xf1, xix .b.b1) r(0xf2, xix .b.b2) r(0xf3, xix .b.b3)
r(IYL, xiy.b.b0) r(IYH, xiy.b.b1) r(QIYL, xiy.b.b2) r(QIYH, xiy.b.b3) r(0xf4, xiy .b.b0) r(0xf5, xiy .b.b1) r(0xf6, xiy .b.b2) r(0xf7, xiy .b.b3)
r(IZL, xiz.b.b0) r(IZH, xiz.b.b1) r(QIZL, xiz.b.b2) r(QIZH, xiz.b.b3) r(0xf8, xiz .b.b0) r(0xf9, xiz .b.b1) r(0xfa, xiz .b.b2) r(0xfb, xiz .b.b3)
r(SPL, xsp.b.b0) r(SPH, xsp.b.b1) r(QSPL, xsp.b.b2) r(QSPH, xsp.b.b3) r(0xfc, xsp .b.b0) r(0xfd, xsp .b.b1) r(0xfe, xsp .b.b2) r(0xff, xsp .b.b3)
#undef r #undef r
} }
return nothing; return nothing;
} }
template<> auto TLCS900H::map<Word>(Register register) -> maybe<uint16&> { template<> auto TLCS900H::map<Word>(Register register) -> maybe<Word&> {
switch(register.value) { switch(register.value & ~1) {
#define r(id, name) case id: return r.name; #define r(id, name) case id: return r.name;
r(RWA0, xwa[0].w.w0) r(QWA0, xwa[0].w.w1) r(RBC0, xbc[0].w.w0) r(QBC0, xbc[0].w.w1) r(0x00, xwa[0].w.w0) r(0x02, xwa[0].w.w1) r(0x04, xbc[0].w.w0) r(0x06, xbc[0].w.w1)
r(RDE0, xde[0].w.w0) r(QDE0, xde[0].w.w1) r(RHL0, xhl[0].w.w0) r(QHL0, xhl[0].w.w1) r(0x08, xde[0].w.w0) r(0x0a, xde[0].w.w1) r(0x0c, xhl[0].w.w0) r(0x0e, xhl[0].w.w1)
r(RWA1, xwa[1].w.w0) r(QWA1, xwa[1].w.w1) r(RBC1, xbc[1].w.w0) r(QBC1, xbc[1].w.w1) r(0x10, xwa[1].w.w0) r(0x12, xwa[1].w.w1) r(0x14, xbc[1].w.w0) r(0x16, xbc[1].w.w1)
r(RDE1, xde[1].w.w0) r(QDE1, xde[1].w.w1) r(RHL1, xhl[1].w.w0) r(QHL1, xhl[1].w.w1) r(0x18, xde[1].w.w0) r(0x1a, xde[1].w.w1) r(0x1c, xhl[1].w.w0) r(0x1e, xhl[1].w.w1)
r(RWA2, xwa[2].w.w0) r(QWA2, xwa[2].w.w1) r(RBC2, xbc[2].w.w0) r(QBC2, xbc[2].w.w1) r(0x20, xwa[2].w.w0) r(0x22, xwa[2].w.w1) r(0x24, xbc[2].w.w0) r(0x26, xbc[2].w.w1)
r(RDE2, xde[2].w.w0) r(QDE2, xde[2].w.w1) r(RHL2, xhl[2].w.w0) r(QHL2, xhl[2].w.w1) r(0x28, xde[2].w.w0) r(0x2a, xde[2].w.w1) r(0x2c, xhl[2].w.w0) r(0x2e, xhl[2].w.w1)
r(RWA3, xwa[3].w.w0) r(QWA3, xwa[3].w.w1) r(RBC3, xbc[3].w.w0) r(QBC3, xbc[3].w.w1) r(0x30, xwa[3].w.w0) r(0x32, xwa[3].w.w1) r(0x34, xbc[3].w.w0) r(0x36, xbc[3].w.w1)
r(RDE3, xde[3].w.w0) r(QDE3, xde[3].w.w1) r(RHL3, xhl[3].w.w0) r(QHL3, xhl[3].w.w1) r(0x38, xde[3].w.w0) r(0x3a, xde[3].w.w1) r(0x3c, xhl[3].w.w0) r(0x3e, xhl[3].w.w1)
r( WAP, xwa[p].w.w0) r(QWAP, xwa[p].w.w1) r( BCP, xbc[p].w.w0) r(QBCP, xbc[p].w.w1) r(0xd0, xwa[p].w.w0) r(0xd2, xwa[p].w.w1) r(0xd4, xbc[p].w.w0) r(0xd6, xbc[p].w.w1)
r( DEP, xde[p].w.w0) r(QDEP, xde[p].w.w1) r( HLP, xhl[p].w.w0) r(QHLP, xhl[p].w.w1) r(0xd8, xde[p].w.w0) r(0xda, xde[p].w.w1) r(0xdc, xhl[p].w.w0) r(0xde, xhl[p].w.w1)
r( WA, xwa[p].w.w0) r(QWA, xwa[p].w.w1) r( BC, xbc[p].w.w0) r(QBC, xbc[p].w.w1) r(0xe0, xwa[p].w.w0) r(0xe2, xwa[p].w.w1) r(0xe4, xbc[p].w.w0) r(0xe6, xbc[p].w.w1)
r( DE, xde[p].w.w0) r(QDE, xde[p].w.w1) r( HL, xhl[p].w.w0) r(QHL, xhl[p].w.w1) r(0xe8, xde[p].w.w0) r(0xea, xde[p].w.w1) r(0xec, xhl[p].w.w0) r(0xee, xhl[p].w.w1)
r(IX, xix.w.w0) r(QIX, xix.w.w1) r(IY, xiy.w.w0) r(QIY, xiy.w.w1) r(0xf0, xix .w.w0) r(0xf2, xix .w.w1) r(0xf4, xiy .w.w0) r(0xf6, xiy .w.w1)
r(IZ, xiz.w.w0) r(QIZ, xiz.w.w1) r(SP, xsp.w.w0) r(QSP, xsp.w.w0) r(0xf8, xiz .w.w0) r(0xfa, xiz .w.w1) r(0xfc, xsp .w.w0) r(0xfe, xsp .w.w0)
#undef r #undef r
} }
return nothing; return nothing;
} }
template<> auto TLCS900H::map<Long>(Register register) -> maybe<uint32&> { template<> auto TLCS900H::map<Long>(Register register) -> maybe<Long&> {
switch(register.value) { switch(register.value & ~3) {
#define r(id, name) case id: return r.name; #define r(id, name) case id: return r.name;
r(XWA0, xwa[0].l.l0) r(XBC0, xbc[0].l.l0) r(XDE0, xde[0].l.l0) r(XHL0, xhl[0].l.l0) r(0x00, xwa[0].l.l0) r(0x04, xbc[0].l.l0) r(0x08, xde[0].l.l0) r(0x0c, xhl[0].l.l0)
r(XWA1, xwa[1].l.l0) r(XBC1, xbc[1].l.l0) r(XDE1, xde[1].l.l0) r(XHL1, xhl[1].l.l0) r(0x10, xwa[1].l.l0) r(0x14, xbc[1].l.l0) r(0x18, xde[1].l.l0) r(0x1c, xhl[1].l.l0)
r(XWA2, xwa[2].l.l0) r(XBC2, xbc[2].l.l0) r(XDE2, xde[2].l.l0) r(XHL2, xhl[2].l.l0) r(0x20, xwa[2].l.l0) r(0x24, xbc[2].l.l0) r(0x28, xde[2].l.l0) r(0x2c, xhl[2].l.l0)
r(XWA3, xwa[3].l.l0) r(XBC3, xbc[3].l.l0) r(XDE3, xde[3].l.l0) r(XHL3, xhl[3].l.l0) r(0x30, xwa[3].l.l0) r(0x34, xbc[3].l.l0) r(0x38, xde[3].l.l0) r(0x3c, xhl[3].l.l0)
r(XWAP, xwa[p].l.l0) r(XBCP, xbc[p].l.l0) r(XDEP, xde[p].l.l0) r(XHLP, xhl[p].l.l0) r(0xd0, xwa[p].l.l0) r(0xd4, xbc[p].l.l0) r(0xd8, xde[p].l.l0) r(0xdc, xhl[p].l.l0)
r(XWA, xwa[a].l.l0) r(XBC, xbc[a].l.l0) r(XDE, xde[a].l.l0) r(XHL, xhl[a].l.l0) r(0xe0, xwa[a].l.l0) r(0xe4, xbc[a].l.l0) r(0xe8, xde[a].l.l0) r(0xec, xhl[a].l.l0)
r(XIX, xix.l.l0) r(XIY, xiy.l.l0) r(XIZ, xiz.l.l0) r(XSP, xsp.l.l0) r(0xf0, xix .l.l0) r(0xf4, xiy .l.l0) r(0xf8, xiz .l.l0) r(0xfc, xsp .l.l0)
#undef r #undef r
} }
return nothing; return nothing;
@ -90,26 +90,64 @@ template<> auto TLCS900H::map<Long>(Register register) -> maybe<uint32&> {
#undef a #undef a
#undef p #undef p
template<> auto TLCS900H::read<Byte>(Register register) -> uint8 { template<> auto TLCS900H::read<Byte>(Register register) -> Byte {
return map<Byte>(register)(0); return map<Byte>(register)(0);
} }
template<> auto TLCS900H::read<Word>(Register register) -> uint16 { template<> auto TLCS900H::read<Word>(Register register) -> Word {
return map<Word>(register)(0); return map<Word>(register)(0);
} }
template<> auto TLCS900H::read<Long>(Register register) -> uint32 { template<> auto TLCS900H::read<Long>(Register register) -> Long {
return map<Long>(register)(0); return map<Long>(register)(0);
} }
template<> auto TLCS900H::write<Byte>(Register register, uint8 data) -> void { template<> auto TLCS900H::write<Byte>(Register register, Byte data) -> void {
if(auto r = map<Byte>(register)) r() = data; if(auto r = map<Byte>(register)) r() = data;
} }
template<> auto TLCS900H::write<Word>(Register register, uint16 data) -> void { template<> auto TLCS900H::write<Word>(Register register, Word data) -> void {
if(auto r = map<Word>(register)) r() = data; if(auto r = map<Word>(register)) r() = data;
} }
template<> auto TLCS900H::write<Long>(Register register, uint32 data) -> void { template<> auto TLCS900H::write<Long>(Register register, Long data) -> void {
if(auto r = map<Word>(register)) r() = data; if(auto r = map<Long>(register)) r() = data;
}
//
//todo: this is pretty hacky ... the templates pass by-value, but we need to modify the status register
//since there's only one, we ignore the parameter and access the underlying register directly instead
template<> auto TLCS900H::read<Word>(StatusRegister) -> Word {
return r.sr.f.c << 0 | r.sr.f.n << 1 | r.sr.f.v << 2 | r.sr.f.h << 4 | r.sr.f.z << 6 | r.sr.f.s << 7
| r.sr.rfp << 8 | 1 << 11 | r.sr.iff << 12 | 1 << 15;
}
template<> auto TLCS900H::write<Word>(StatusRegister, Word data) -> void {
r.sr.f.c = data.bit(0);
r.sr.f.n = data.bit(1);
r.sr.f.v = data.bit(2);
r.sr.f.h = data.bit(4);
r.sr.f.z = data.bit(6);
r.sr.f.s = data.bit(7);
r.sr.rfp = data.bits(8,9);
r.sr.iff = data.bits(12,14);
r.sr.rfpp = r.sr.rfp - 1;
}
//todo: the same thing for the flag register
template<> auto TLCS900H::read<Byte>(FlagRegister) -> Byte {
return r.sr.f.c << 0 | r.sr.f.n << 1 | r.sr.f.v << 2 | r.sr.f.h << 4 | r.sr.f.z << 6 | r.sr.f.s << 7;
}
template<> auto TLCS900H::write<Byte>(FlagRegister, Byte data) -> void {
r.sr.f.c = data.bit(0);
r.sr.f.n = data.bit(1);
r.sr.f.v = data.bit(2);
r.sr.f.h = data.bit(4);
r.sr.f.z = data.bit(6);
r.sr.f.s = data.bit(7);
} }

6
higan/processor/tlcs900h/tlcs900h.cpp
View File

@ -3,12 +3,18 @@
namespace Processor { namespace Processor {
//todo: these defines should not be necessary; yet ADL doesn't work without them ... why not?
#define Byte uint8 #define Byte uint8
#define Word uint16 #define Word uint16
#define Long uint32 #define Long uint32
template<typename Size> static constexpr auto isByte() -> bool { return is_same<Size, Byte>::value; }
template<typename Size> static constexpr auto isWord() -> bool { return is_same<Size, Word>::value; }
template<typename Size> static constexpr auto isLong() -> bool { return is_same<Size, Long>::value; }
#include "registers.cpp" #include "registers.cpp"
#include "memory.cpp" #include "memory.cpp"
#include "conditions.cpp"
#include "algorithms.cpp" #include "algorithms.cpp"
#include "instruction.cpp" #include "instruction.cpp"
#include "instructions.cpp" #include "instructions.cpp"

158
higan/processor/tlcs900h/tlcs900h.hpp
View File

@ -1,5 +1,12 @@
//Toshiba TLCS900/H //Toshiba TLCS900/H
/* open questions:
*
* what happens when a prohibited instruction operand size is used? (eg adc.l (memory),#immediate)
* what happens when %11 is used for pre-decrement and post-increment addressing?
* what happens when using 8-bit register indexing and d0 is set (Word) or d1/d0 is set (Long)?
*/
#pragma once #pragma once
namespace Processor { namespace Processor {
@ -13,43 +20,6 @@ struct TLCS900H {
struct Memory { Long value; }; struct Memory { Long value; };
struct Immediate { Long value; }; struct Immediate { Long value; };
virtual auto read(uint32 address) -> uint8 = 0;
virtual auto write(uint32 address, uint8 data) -> void = 0;
template<typename Size> auto read(Immediate immediate) -> Size { return immediate.value; }
//tlcs900h.cpp
auto power() -> void;
//registers.cpp
template<typename Size> auto map(Register register) -> maybe<Size&>;
template<typename Size> auto read(Register) -> Size;
template<typename Size> auto write(Register, Size data) -> void;
//memory.cpp
template<typename Size = Byte> auto fetch() -> Size;
template<typename Size> auto read(Memory memory) -> Size;
template<typename Size> auto write(Memory memory, Size data) -> void;
//algorithms.cpp
template<typename Size> auto algorithmAdd(Size target, Size source, uint1 carry = 0) -> Size;
//instruction.cpp
auto instruction() -> void;
template<typename Size> auto instructionRegister(Register input) -> void;
template<typename Size> auto instructionSourceMemory(Memory input) -> void;
auto instructionTargetMemory(Memory input) -> void;
//instructions.cpp
template<typename Size, typename Target, typename Source> auto instructionAdd(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionAddCarry(Target target, Source source) -> void;
auto instructionComplementCarry() -> void;
auto instructionNoOperation() -> void;
auto instructionSoftwareInterrupt(Immediate interrupt) -> void;
//serialization.cpp
auto serialize(serializer&) -> void;
struct DataRegister { struct DataRegister {
union { union {
struct { Long order_lsb1(l0); } l; struct { Long order_lsb1(l0); } l;
@ -75,6 +45,67 @@ struct TLCS900H {
FlagRegister fp; FlagRegister fp;
}; };
virtual auto read(uint32 address) -> uint8 = 0;
virtual auto write(uint32 address, uint8 data) -> void = 0;
template<typename Size> auto read(Immediate immediate) -> Size { return immediate.value; }
//tlcs900h.cpp
auto power() -> void;
//registers.cpp
template<typename Size> auto map(Register register) -> maybe<Size&>;
template<typename Size> auto read(Register) -> Size;
template<typename Size> auto write(Register, Size data) -> void;
template<typename Size> auto read(StatusRegister) -> Size;
template<typename Size> auto write(StatusRegister, Size) -> void;
template<typename Size> auto read(FlagRegister) -> Size;
template<typename Size> auto write(FlagRegister, Size) -> void;
//memory.cpp
template<typename Size = Byte> auto fetch() -> Size;
template<typename Size> auto push(Size) -> void;
template<typename Size> auto pop() -> Size;
template<typename Size> auto read(Memory memory) -> Size;
template<typename Size> auto write(Memory memory, Size data) -> void;
//conditions.cpp
auto condition(uint4 code) -> bool;
//algorithms.cpp
template<typename Size> auto parity(Size) const -> bool;
template<typename Size> auto algorithmAdd(Size target, Size source, uint1 carry = 0) -> Size;
template<typename Size> auto algorithmAnd(Size target, Size source) -> Size;
template<typename Size> auto algorithmOr(Size target, Size source) -> Size;
template<typename Size> auto algorithmSubtract(Size target, Size source, uint1 carry = 0) -> Size;
template<typename Size> auto algorithmXor(Size target, Size source) -> Size;
//instruction.cpp
template<typename Size> auto registerLookup(uint3 code) -> Register;
auto instruction() -> void;
template<typename Size> auto instructionRegister(Register) -> void;
template<typename Size> auto instructionSourceMemory(Memory) -> void;
auto instructionTargetMemory(Memory) -> void;
//instructions.cpp
template<typename Size, typename Target, typename Source> auto instructionAdd(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionAddCarry(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionAnd(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionCompare(Target target, Source source) -> void;
auto instructionComplementCarry() -> void;
auto instructionNoOperation() -> void;
template<typename Size, typename Target, typename Source> auto instructionOr(Target target, Source source) -> void;
template<typename Size, typename Target> auto instructionPop(Target target) -> void;
template<typename Size, typename Source> auto instructionPush(Source source) -> void;
auto instructionSoftwareInterrupt(Immediate interrupt) -> void;
template<typename Size, typename Target, typename Source> auto instructionSubtract(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionSubtractCarry(Target target, Source source) -> void;
template<typename Size, typename Target, typename Source> auto instructionXor(Target target, Source source) -> void;
//serialization.cpp
auto serialize(serializer&) -> void;
struct Registers { struct Registers {
DataRegister xwa[4]; DataRegister xwa[4];
DataRegister xbc[4]; DataRegister xbc[4];
@ -88,37 +119,34 @@ struct TLCS900H {
StatusRegister sr; StatusRegister sr;
} r; } r;
enum : uint { static inline const Register A{0xe0};
RA0, RW0, QA0, QW0, RC0, RB0, QC0, QB0, RE0, RD0, QE0, QD0, RL0, RH0, QL0, QH0, static inline const Register W{0xe1};
RA1, RW1, QA1, QW1, RC1, RB1, QC1, QB1, RE1, RD1, QE1, QD1, RL1, RH1, QL1, QH1, static inline const Register C{0xe4};
RA2, RW2, QA2, QW2, RC2, RB2, QC2, QB2, RE2, RD2, QE2, QD2, RL2, RH2, QL2, QH2, static inline const Register B{0xe5};
RA3, RW3, QA3, QW3, RC3, RB3, QC3, QB3, RE3, RD3, QE3, QD3, RL3, RH3, QL3, QH3, SPC = 0xcf, //AP = 0xd0 static inline const Register E{0xe8};
AP, WP, QAP, QWP, CP, BP, QCP, QBP, EP, DP, QEP, QDP, LP, HP, QLP, QHP, static inline const Register D{0xe9};
A, W, QA, QW, C, B, QC, QB, E, D, QE, QD, L, H, QL, QH, static inline const Register L{0xec};
IXL, IXH, QIXL,QIXH,IYL, IYH, QIYL,QIYH,IZL, IZH, QIZL,QIZH,SPL, SPH, QSPL,QSPH, static inline const Register H{0xed};
};
enum : uint { static inline const Register WA{0xe0};
RWA0 = 0x00, QWA0 = 0x02, RBC0 = 0x04, QBC0 = 0x06, RDE0 = 0x08, QDE0 = 0x0a, RHL0 = 0x0c, QHL0 = 0x0e, static inline const Register BC{0xe4};
RWA1 = 0x10, QWA1 = 0x12, RBC1 = 0x14, QBC1 = 0x16, RDE1 = 0x18, QDE1 = 0x1a, RHL1 = 0x1c, QHL1 = 0x1e, static inline const Register DE{0xe8};
RWA2 = 0x20, QWA2 = 0x22, RBC2 = 0x24, QBC2 = 0x26, RDE2 = 0x28, QDE2 = 0x2a, RHL2 = 0x2c, QHL2 = 0x2e, static inline const Register HL{0xec};
RWA3 = 0x30, QWA3 = 0x32, RBC3 = 0x34, QBC3 = 0x36, RDE3 = 0x38, QDE3 = 0x3a, RHL3 = 0x3c, QHL3 = 0x3e, static inline const Register IX{0xf0};
WAP = 0xd0, QWAP = 0xd2, BCP = 0xd4, QBCP = 0xd6, DEP = 0xd8, QDEP = 0xda, HLP = 0xdc, QHLP = 0xde, static inline const Register IY{0xf4};
WA = 0xe0, QWA = 0xe2, BC = 0xe4, QBC = 0xe6, DE = 0xe8, QDE = 0xea, HL = 0xec, QHL = 0xee, static inline const Register IZ{0xf8};
IX = 0xf0, QIX = 0xf2, IY = 0xf4, QIY = 0xf6, IZ = 0xf8, QIZ = 0xfa, SP = 0xfc, QSP = 0xfe, static inline const Register SP{0xfc};
};
enum : uint { static inline const Register XWA{0xe0};
XWA0 = 0x00, XBC0 = 0x04, XDE0 = 0x08, XHL0 = 0x0c, static inline const Register XBC{0xe4};
XWA1 = 0x10, XBC1 = 0x14, XDE1 = 0x18, XHL1 = 0x1c, static inline const Register XDE{0xe8};
XWA2 = 0x20, XBC2 = 0x24, XDE2 = 0x28, XHL2 = 0x2c, static inline const Register XHL{0xec};
XWA3 = 0x30, XBC3 = 0x34, XDE3 = 0x38, XHL3 = 0x3c, static inline const Register XIX{0xf0};
XWAP = 0xd0, XBCP = 0xd4, XDEP = 0xd8, XHLP = 0xdc, static inline const Register XIY{0xf4};
XWA = 0xe0, XBC = 0xe4, XDE = 0xe8, XHL = 0xec, static inline const Register XIZ{0xf8};
XIX = 0xf0, XIY = 0xf4, XIZ = 0xf8, XSP = 0xfc, static inline const Register XSP{0xfc};
};
const uint1 undefined = 0; static inline const uint1 Undefined = 0;
}; };
} }

14
nall/primitives.hpp
View File

@ -36,6 +36,8 @@ template<uint Bits> struct Natural {
enum : type { Mask = ~0ull >> (64 - Bits) }; enum : type { Mask = ~0ull >> (64 - Bits) };
static inline constexpr auto bits() -> uint { return Bits; }
inline Natural() : data(0) {} inline Natural() : data(0) {}
template<typename T> inline Natural(const T& value) { set(value); } template<typename T> inline Natural(const T& value) { set(value); }
@ -101,6 +103,10 @@ template<uint Bits> struct Natural {
const type Hi; const type Hi;
}; };
inline auto zero() const -> bool { return data == 0; }
inline auto positive() const -> bool { return (data >> bits() - 1) == 0; }
inline auto negative() const -> bool { return (data >> bits() - 1) == 1; }
inline auto bits(uint lo, uint hi) -> Reference { return {*this, lo < hi ? lo : hi, hi > lo ? hi : lo}; } inline auto bits(uint lo, uint hi) -> Reference { return {*this, lo < hi ? lo : hi, hi > lo ? hi : lo}; }
inline auto bit(uint index) -> Reference { return {*this, index, index}; } inline auto bit(uint index) -> Reference { return {*this, index, index}; }
inline auto byte(uint index) -> Reference { return {*this, index * 8 + 0, index * 8 + 7}; } inline auto byte(uint index) -> Reference { return {*this, index * 8 + 0, index * 8 + 7}; }
@ -140,6 +146,8 @@ template<uint Bits> struct Integer {
enum : utype { Mask = ~0ull >> (64 - Bits), Sign = 1ull << (Bits - 1) }; enum : utype { Mask = ~0ull >> (64 - Bits), Sign = 1ull << (Bits - 1) };
static inline constexpr auto bits() -> uint { return Bits; }
inline Integer() : data(0) {} inline Integer() : data(0) {}
template<typename T> inline Integer(const T& value) { set(value); } template<typename T> inline Integer(const T& value) { set(value); }
@ -205,6 +213,10 @@ template<uint Bits> struct Integer {
const uint Hi; const uint Hi;
}; };
inline auto zero() const -> bool { return data == 0; }
inline auto positive() const -> bool { return data >= 0; }
inline auto negative() const -> bool { return data < 0; }
inline auto bits(uint lo, uint hi) -> Reference { return {*this, lo < hi ? lo : hi, hi > lo ? hi : lo}; } inline auto bits(uint lo, uint hi) -> Reference { return {*this, lo < hi ? lo : hi, hi > lo ? hi : lo}; }
inline auto bit(uint index) -> Reference { return {*this, index, index}; } inline auto bit(uint index) -> Reference { return {*this, index, index}; }
inline auto byte(uint index) -> Reference { return {*this, index * 8 + 0, index * 8 + 7}; } inline auto byte(uint index) -> Reference { return {*this, index * 8 + 0, index * 8 + 7}; }
@ -239,6 +251,8 @@ template<uint Bits> struct Real {
typename conditional<Bits == 64, float64_t, typename conditional<Bits == 64, float64_t,
void>::type>::type; void>::type>::type;
static inline constexpr auto bits() -> uint { return Bits; }
inline Real() : data(0.0) {} inline Real() : data(0.0) {}
template<typename T> inline Real(const T& value) : data((type)value) {} template<typename T> inline Real(const T& value) : data((type)value) {}