mirror of https://github.com/bsnes-emu/bsnes.git
Update to v087r16 release.
byuu says: Fixed the r15 mask per Cydrak. Added DMA support (immediate + Vblank + Hblank + HDMA) with IRQ support. Basically only missing FIFO reload mode for the APU on channel 2. Added background linear renderer (tilemap mode.) Added really inefficient pixel priority selector, so that all BGs+OBJ could be visible onscreen at the same time. As a result of the above: * Mr. Driller is our first fully playable game * Bakunetsu Dodge Ball Fighters is also fully playable * Pinobee no Daibouken is also fully playable Most games (15 of 16 tested) are now showing *something*, many things look really really good in fact. Absolutely essential missing components: - APU - CPU timers and their interrupts - DMA FIFO mode - OBJ affine mode - BG affine mode - BG bitmap mode - PPU windows (BG and OBJ) - PPU mosaic - PPU blending modes - SRAM / EEPROM (going to rely on a database, not heuristics. Homebrew will require a manifest file.)
This commit is contained in:
Tim Allen
parent
79a47d133a
commit
b8d0ec29b2
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@ -1,7 +1,7 @@
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#ifndef BASE_HPP
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#define BASE_HPP
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static const char Version[] = "087.15";
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static const char Version[] = "087.16";
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#include <nall/platform.hpp>
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#include <nall/algorithm.hpp>
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@ -4,6 +4,7 @@ namespace GBA {
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#include "registers.cpp"
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#include "mmio.cpp"
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#include "dma.cpp"
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CPU cpu;
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void CPU::Enter() { cpu.enter(); }
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@ -28,6 +29,7 @@ void CPU::enter() {
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regs.mode = Registers::Mode::Normal;
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}
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dma_run();
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exec();
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}
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}
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@ -72,6 +74,10 @@ void CPU::power() {
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regs.mode = Registers::Mode::Normal;
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regs.memory.control = 0x0d000020;
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pending.dma.vblank = 0;
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pending.dma.hblank = 0;
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pending.dma.hdma = 0;
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for(unsigned n = 0x0b0; n <= 0x0df; n++) bus.mmio[n] = this; //DMA
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for(unsigned n = 0x100; n <= 0x10f; n++) bus.mmio[n] = this; //Timers
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for(unsigned n = 0x130; n <= 0x133; n++) bus.mmio[n] = this; //Keypad
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@ -2,6 +2,7 @@ struct CPU : Processor::ARM, Thread, MMIO {
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StaticMemory iwram;
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StaticMemory ewram;
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#include "registers.hpp"
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#include "state.hpp"
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static void Enter();
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void enter();
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@ -14,6 +15,9 @@ struct CPU : Processor::ARM, Thread, MMIO {
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uint8 read(uint32 addr);
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void write(uint32 addr, uint8 byte);
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void dma_run();
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void dma_transfer(uint2 channel);
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CPU();
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};
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@ -0,0 +1,45 @@
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void CPU::dma_run() {
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for(unsigned n = 0; n < 4; n++) {
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if(regs.dma[n].control.enable == false) continue;
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switch(regs.dma[n].control.timingmode) {
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case 0: break;
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case 1: if(pending.dma.vblank == false) continue; break;
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case 2: if(pending.dma.hblank == false) continue; break;
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case 3: if(pending.dma.hdma == false || n != 3) continue; break;
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}
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dma_transfer(n);
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}
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pending.dma.vblank = false;
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pending.dma.hblank = false;
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pending.dma.hdma = false;
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}
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void CPU::dma_transfer(uint2 n) {
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auto &channel = regs.dma[n];
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unsigned size = channel.control.size ? Word : Half;
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unsigned seek = channel.control.size ? 4 : 2;
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uint16 length = channel.length;
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channel.basetarget = channel.target;
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do {
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uint32 word = bus.read(channel.source, size);
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bus.write(channel.target, size, word);
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switch(channel.control.sourcemode) {
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case 0: channel.source += seek; break;
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case 1: channel.source -= seek; break;
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}
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switch(channel.control.targetmode) {
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case 0: channel.target += seek; break;
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case 1: channel.target -= seek; break;
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case 3: channel.target += seek; break;
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}
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} while(--length);
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if(channel.control.targetmode == 3) channel.target = channel.basetarget;
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channel.control.enable = false;
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if(channel.control.irq) regs.irq.flag.dma[n] = 1;
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}
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@ -5,7 +5,7 @@ CPU::Registers::DMA::Control::operator uint16() const {
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| (repeat << 9)
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| (size << 10)
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| (drq << 11)
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| (timing << 12)
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| (timingmode << 12)
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| (irq << 14)
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| (enable << 15)
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);
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@ -17,7 +17,7 @@ uint16 CPU::Registers::DMA::Control::operator=(uint16 source) {
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repeat = source >> 9;
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size = source >> 10;
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drq = source >> 11;
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timing = source >> 12;
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timingmode = source >> 12;
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irq = source >> 14;
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enable = source >> 15;
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return operator uint16();
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@ -78,15 +78,15 @@ CPU::Registers::Interrupt::operator uint16() const {
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(vblank << 0)
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| (hblank << 1)
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| (vcoincidence << 2)
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| (timer0 << 3)
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| (timer1 << 4)
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| (timer2 << 5)
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| (timer3 << 6)
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| (timer[0] << 3)
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| (timer[1] << 4)
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| (timer[2] << 5)
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| (timer[3] << 6)
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| (serial << 7)
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| (dma0 << 8)
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| (dma1 << 9)
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| (dma2 << 10)
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| (dma3 << 11)
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| (dma[0] << 8)
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| (dma[1] << 9)
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| (dma[2] << 10)
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| (dma[3] << 11)
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| (keypad << 12)
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| (cartridge << 13)
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);
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@ -96,15 +96,15 @@ uint16 CPU::Registers::Interrupt::operator=(uint16 source) {
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vblank = source & (1 << 0);
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hblank = source & (1 << 1);
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vcoincidence = source & (1 << 2);
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timer0 = source & (1 << 3);
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timer1 = source & (1 << 4);
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timer2 = source & (1 << 5);
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timer3 = source & (1 << 6);
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timer[0] = source & (1 << 3);
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timer[1] = source & (1 << 4);
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timer[2] = source & (1 << 5);
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timer[3] = source & (1 << 6);
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serial = source & (1 << 7);
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dma0 = source & (1 << 8);
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dma1 = source & (1 << 9);
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dma2 = source & (1 << 10);
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dma3 = source & (1 << 11);
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dma[0] = source & (1 << 8);
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dma[1] = source & (1 << 9);
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dma[2] = source & (1 << 10);
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dma[3] = source & (1 << 11);
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keypad = source & (1 << 12);
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cartridge = source & (1 << 13);
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return operator uint16();
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@ -9,7 +9,7 @@ struct Registers {
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uint1 repeat;
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uint1 size;
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uint1 drq;
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uint2 timing;
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uint2 timingmode;
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uint1 irq;
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uint1 enable;
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@ -17,6 +17,9 @@ struct Registers {
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uint16 operator=(uint16 source);
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DMA& operator=(const DMA&) = delete;
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} control;
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//internal
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uint32 basetarget;
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} dma[4];
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struct TimerControl {
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bool vblank;
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bool hblank;
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bool vcoincidence;
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bool timer0;
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bool timer1;
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bool timer2;
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bool timer3;
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bool timer[4];
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bool serial;
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bool dma0;
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bool dma1;
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bool dma2;
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bool dma3;
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bool dma[4];
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bool keypad;
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bool cartridge;
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@ -0,0 +1,7 @@
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struct Pending {
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struct DMA {
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bool vblank;
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bool hblank;
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bool hdma;
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} dma;
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} pending;
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@ -13,7 +13,7 @@ namespace GBA {
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/*
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bgba - Game Boy Advance emulator
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author: byuu
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authors: byuu, Cydrak
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license: GPLv3
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project started: 2012-03-19
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*/
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@ -0,0 +1,72 @@
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void PPU::render_backgrounds() {
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if(regs.control.bgmode == 0) {
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render_background_linear(0);
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render_background_linear(1);
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render_background_linear(2);
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render_background_linear(3);
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}
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if(regs.control.bgmode == 1) {
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render_background_linear(0);
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render_background_linear(1);
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//render_background_affine(2);
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}
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if(regs.control.bgmode == 2) {
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//render_background_affine(2);
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//render_background_affine(3);
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}
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}
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void PPU::render_background_linear(unsigned bgnumber) {
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for(unsigned n = 0; n < 240; n++) pixel[bgnumber][n].exists = false;
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if(regs.control.enablebg[bgnumber] == false) return;
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auto &bg = regs.bg[bgnumber];
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uint9 voffset = regs.vcounter + bg.voffset;
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uint9 hoffset = bg.hoffset;
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unsigned basemap = bg.control.screenbaseblock << 11;
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unsigned basechr = bg.control.characterbaseblock << 14;
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unsigned px = hoffset & 7, py = voffset & 7;
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Tile tile;
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uint8 data[8];
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for(unsigned x = 0; x < 240; x++) {
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if(x == 0 || px & 8) {
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px &= 7;
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unsigned tx = hoffset / 8, ty = voffset / 8;
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unsigned offset = (ty & 31) * 32 + (tx & 31);
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if(bg.control.screensize & 1) if(tx & 32) offset += 32 * 32;
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if(bg.control.screensize & 2) if(ty & 32) offset += 32 * 32 * (1 + (bg.control.screensize & 1));
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offset = basemap + offset * 2;
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uint16 mapdata = vram.read(offset, Half);
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tile.character = mapdata >> 0;
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tile.hflip = mapdata >> 10;
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tile.vflip = mapdata >> 11;
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tile.palette = mapdata >> 12;
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if(bg.control.colormode == 0) {
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offset = basechr + tile.character * 32 + (py ^ (tile.vflip ? 7 : 0)) * 4;
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uint32 word = vram.read(offset, Word);
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for(unsigned n = 0; n < 8; n++) data[n] = (word >> (n * 4)) & 15;
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} else {
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offset = basechr + tile.character * 64 + (py ^ (tile.vflip ? 7 : 0)) * 8;
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uint32 wordlo = vram.read(offset + 0, Word);
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uint32 wordhi = vram.read(offset + 4, Word);
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for(unsigned n = 0; n < 4; n++) data[0 + n] = (wordlo >> (n * 8)) & 255;
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for(unsigned n = 0; n < 4; n++) data[4 + n] = (wordhi >> (n * 8)) & 255;
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}
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}
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hoffset++;
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uint8 color = data[px++ ^ (tile.hflip ? 7 : 0)];
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if(color == 0) continue; //transparent
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if(bg.control.colormode == 0) pixel[bgnumber][x] = { true, palette(tile.palette * 16 + color), bg.control.priority };
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if(bg.control.colormode == 1) pixel[bgnumber][x] = { true, palette(color), bg.control.priority };
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}
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}
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@ -1,5 +1,6 @@
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void PPU::render_objects() {
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for(unsigned n = 0; n < 240; n++) pixel[n].exists = false;
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for(unsigned n = 0; n < 240; n++) pixel[4][n].exists = false;
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if(regs.control.enableobj == false) return;
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for(unsigned n = 0; n < 128; n++) {
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auto &obj = object[n];
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@ -72,8 +73,8 @@ void PPU::render_object_linear(Object &obj) {
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if(obj.colors == 0) color = (px & 1) ? color >> 4 : color & 15;
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if(color == 0) continue; //transparent
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if(obj.colors == 0) pixel[sx] = { true, palette(256 + obj.palette * 16 + color), obj.priority };
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if(obj.colors == 1) pixel[sx] = { true, palette(256 + color), obj.priority };
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if(obj.colors == 0) pixel[4][sx] = { true, palette(256 + obj.palette * 16 + color), obj.priority };
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if(obj.colors == 1) pixel[4][sx] = { true, palette(256 + color), obj.priority };
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}
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}
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@ -13,6 +13,7 @@
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namespace GBA {
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#include "registers.cpp"
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#include "background.cpp"
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#include "object.cpp"
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#include "screen.cpp"
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#include "mmio.cpp"
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@ -85,6 +86,7 @@ void PPU::scanline() {
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if(regs.vcounter == 160) {
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if(regs.status.irqvblank) cpu.regs.irq.flag.vblank = 1;
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cpu.pending.dma.vblank = true;
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}
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if(regs.status.irqvcoincidence) {
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@ -92,17 +94,21 @@ void PPU::scanline() {
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}
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if(regs.vcounter < 160) {
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render_backgrounds();
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render_objects();
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render_screen();
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}
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step(256 * 4);
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step(1024);
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regs.status.hblank = 1;
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if(regs.status.irqhblank) cpu.regs.irq.flag.hblank = 1;
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cpu.pending.dma.hblank = true;
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step( 52 * 4);
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step(200);
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regs.status.hblank = 0;
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cpu.pending.dma.hdma = true;
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step(8);
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if(++regs.vcounter == 228) regs.vcounter = 0;
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}
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@ -17,6 +17,9 @@ struct PPU : Thread, MMIO {
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uint8 read(uint32 addr);
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void write(uint32 addr, uint8 byte);
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void render_backgrounds();
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void render_background_linear(unsigned bgnumber);
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void render_objects();
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void render_object_linear(Object&);
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void render_object_affine(Object&);
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@ -9,7 +9,14 @@ void PPU::render_screen() {
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uint16 *line = output + regs.vcounter * 240;
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for(unsigned x = 0; x < 240; x++) {
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if(pixel[x].exists) line[x] = pixel[x].color;
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else line[x] = palette(0) & 0x7fff;
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uint15 color = palette(0) & 0x7fff;
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for(signed p = 3; p >= 0; p--) {
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if(pixel[3][x].exists && pixel[3][x].priority == p) color = pixel[3][x].color;
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if(pixel[2][x].exists && pixel[2][x].priority == p) color = pixel[2][x].color;
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if(pixel[1][x].exists && pixel[1][x].priority == p) color = pixel[1][x].color;
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if(pixel[0][x].exists && pixel[0][x].priority == p) color = pixel[0][x].color;
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if(pixel[4][x].exists && pixel[4][x].priority == p) color = pixel[4][x].color;
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}
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line[x] = color;
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}
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}
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|
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@ -2,7 +2,7 @@ struct Pixel {
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bool exists;
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uint15 color;
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uint2 priority;
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} pixel[256];
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} pixel[5][256];
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struct Object {
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uint8 y;
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@ -27,3 +27,10 @@ struct Object {
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unsigned width;
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unsigned height;
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} object[128];
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struct Tile {
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uint10 character;
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uint1 hflip;
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uint1 vflip;
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uint4 palette;
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};
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|
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|
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@ -16,7 +16,6 @@ void ARM::power() {
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crash = false;
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r(15).modify = [&] {
|
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pipeline.reload = true;
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r(15).data &= cpsr().t ? ~1 : ~3;
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};
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trace = false;
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|
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@ -5,8 +5,8 @@ void ARM::arm_step() {
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pipeline.reload = false;
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r(15).data &= ~3;
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pipeline.fetch.address = r(15);
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pipeline.fetch.instruction = read(r(15), Word);
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pipeline.fetch.address = r(15) & ~3;
|
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pipeline.fetch.instruction = read(pipeline.fetch.address, Word);
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pipeline_step();
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step(2);
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|
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|
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@ -5,8 +5,8 @@ void ARM::thumb_step() {
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pipeline.reload = false;
|
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r(15).data &= ~1;
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pipeline.fetch.address = r(15);
|
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pipeline.fetch.instruction = read(r(15), Half);
|
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pipeline.fetch.address = r(15) & ~1;
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pipeline.fetch.instruction = read(pipeline.fetch.address, Half);
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pipeline_step();
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step(1);
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@ -66,12 +66,12 @@ void ARM::pipeline_step() {
|
|||
|
||||
if(cpsr().t == 0) {
|
||||
r(15).data += 4;
|
||||
pipeline.fetch.address = r(15);
|
||||
pipeline.fetch.instruction = read(r(15), Word);
|
||||
pipeline.fetch.address = r(15) & ~3;
|
||||
pipeline.fetch.instruction = read(pipeline.fetch.address, Word);
|
||||
} else {
|
||||
r(15).data += 2;
|
||||
pipeline.fetch.address = r(15);
|
||||
pipeline.fetch.instruction = read(r(15), Half);
|
||||
pipeline.fetch.address = r(15) & ~1;
|
||||
pipeline.fetch.instruction = read(pipeline.fetch.address, Half);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue