mirror of https://github.com/bsnes-emu/bsnes.git
v107.13
* libco: added ppc64v2 implementation [Shawn Anastasio]
This commit is contained in:
byuu
parent
30c606fdc8
commit
b637ae34fe
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@ -32,7 +32,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "bsnes";
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static const string Version = "107.12";
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static const string Version = "107.13";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "https://byuu.org/";
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@ -1,5 +1,9 @@
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#if defined(__clang__)
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#pragma clang diagnostic ignored "-Wparentheses"
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//placing code in section(text) does not mark it executable with Clang.
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#undef LIBCO_MPROTECT
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#define LIBCO_MPROTECT
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#endif
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#if defined(__clang__) || defined(__GNUC__)
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@ -11,6 +15,8 @@
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#include "arm.c"
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#elif defined(__aarch64__)
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#include "aarch64.c"
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#elif defined(__powerpc64__) && defined(_CALL_ELF) && _CALL_ELF == 2
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#include "ppc64v2.c"
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#elif defined(_ARCH_PPC) && !defined(__LITTLE_ENDIAN__)
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#include "ppc.c"
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#elif defined(_WIN32)
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@ -0,0 +1,277 @@
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/* author: Shawn Anastasio */
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#define LIBCO_C
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#include "libco.h"
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#include "settings.h"
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#include <stdint.h>
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#include <stdlib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct ppc64_context {
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//GPRs
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uint64_t gprs[32];
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uint64_t lr;
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uint64_t ccr;
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//FPRs
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uint64_t fprs[32];
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#ifdef __ALTIVEC__
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//Altivec (VMX)
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uint64_t vmx[12 * 2];
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uint32_t vrsave;
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#endif
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};
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static thread_local struct ppc64_context* co_active_handle = 0;
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#define MAX(x, y) ((x) > (y) ? (x) : (y))
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#define ALIGN(p, x) ((void*)((uintptr_t)(p) & ~((x) - 1)))
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#define MIN_STACK 0x10000lu
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#define MIN_STACK_FRAME 0x20lu
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#define STACK_ALIGN 0x10lu
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void swap_context(struct ppc64_context* read, struct ppc64_context* write);
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__asm__(
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".text\n"
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".align 4\n"
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".type swap_context @function\n"
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"swap_context:\n"
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".cfi_startproc\n"
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//save GPRs
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"std 1, 8(4)\n"
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"std 2, 16(4)\n"
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"std 12, 96(4)\n"
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"std 13, 104(4)\n"
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"std 14, 112(4)\n"
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"std 15, 120(4)\n"
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"std 16, 128(4)\n"
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"std 17, 136(4)\n"
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"std 18, 144(4)\n"
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"std 19, 152(4)\n"
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"std 20, 160(4)\n"
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"std 21, 168(4)\n"
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"std 22, 176(4)\n"
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"std 23, 184(4)\n"
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"std 24, 192(4)\n"
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"std 25, 200(4)\n"
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"std 26, 208(4)\n"
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"std 27, 216(4)\n"
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"std 28, 224(4)\n"
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"std 29, 232(4)\n"
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"std 30, 240(4)\n"
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"std 31, 248(4)\n"
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//save LR
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"mflr 5\n"
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"std 5, 256(4)\n"
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//save CCR
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"mfcr 5\n"
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"std 5, 264(4)\n"
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//save FPRs
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"stfd 14, 384(4)\n"
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"stfd 15, 392(4)\n"
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"stfd 16, 400(4)\n"
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"stfd 17, 408(4)\n"
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"stfd 18, 416(4)\n"
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"stfd 19, 424(4)\n"
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"stfd 20, 432(4)\n"
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"stfd 21, 440(4)\n"
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"stfd 22, 448(4)\n"
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"stfd 23, 456(4)\n"
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"stfd 24, 464(4)\n"
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"stfd 25, 472(4)\n"
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"stfd 26, 480(4)\n"
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"stfd 27, 488(4)\n"
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"stfd 28, 496(4)\n"
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"stfd 29, 504(4)\n"
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"stfd 30, 512(4)\n"
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"stfd 31, 520(4)\n"
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#ifdef __ALTIVEC__
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//save VMX
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"li 5, 528\n"
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"stvxl 20, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 21, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 22, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 23, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 24, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 25, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 26, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 27, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 28, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 29, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 30, 4, 5\n"
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"addi 5, 5, 16\n"
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"stvxl 31, 4, 5\n"
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"addi 5, 5, 16\n"
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//save VRSAVE
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"mfvrsave 5\n"
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"stw 5, 736(4)\n"
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#endif
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//restore GPRs
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"ld 1, 8(3)\n"
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"ld 2, 16(3)\n"
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"ld 12, 96(3)\n"
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"ld 13, 104(3)\n"
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"ld 14, 112(3)\n"
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"ld 15, 120(3)\n"
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"ld 16, 128(3)\n"
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"ld 17, 136(3)\n"
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"ld 18, 144(3)\n"
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"ld 19, 152(3)\n"
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"ld 20, 160(3)\n"
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"ld 21, 168(3)\n"
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"ld 22, 176(3)\n"
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"ld 23, 184(3)\n"
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"ld 24, 192(3)\n"
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"ld 25, 200(3)\n"
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"ld 26, 208(3)\n"
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"ld 27, 216(3)\n"
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"ld 28, 224(3)\n"
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"ld 29, 232(3)\n"
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"ld 30, 240(3)\n"
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"ld 31, 248(3)\n"
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//restore LR
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"ld 5, 256(3)\n"
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"mtlr 5\n"
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//restore CCR
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"ld 5, 264(3)\n"
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"mtcr 5\n"
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//restore FPRs
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"lfd 14, 384(3)\n"
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"lfd 15, 392(3)\n"
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"lfd 16, 400(3)\n"
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"lfd 17, 408(3)\n"
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"lfd 18, 416(3)\n"
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"lfd 19, 424(3)\n"
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"lfd 20, 432(3)\n"
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"lfd 21, 440(3)\n"
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"lfd 22, 448(3)\n"
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"lfd 23, 456(3)\n"
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"lfd 24, 464(3)\n"
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"lfd 25, 472(3)\n"
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"lfd 26, 480(3)\n"
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"lfd 27, 488(3)\n"
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"lfd 28, 496(3)\n"
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"lfd 29, 504(3)\n"
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"lfd 30, 512(3)\n"
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"lfd 31, 520(3)\n"
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#ifdef __ALTIVEC__
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//restore VMX
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"li 5, 528\n"
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"lvxl 20, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 21, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 22, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 23, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 24, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 25, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 26, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 27, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 28, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 29, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 30, 3, 5\n"
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"addi 5, 5, 16\n"
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"lvxl 31, 3, 5\n"
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"addi 5, 5, 16\n"
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//restore VRSAVE
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"lwz 5, 720(3)\n"
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"mtvrsave 5\n"
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#endif
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//branch to LR
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"blr\n"
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".cfi_endproc\n"
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".size swap_context, .-swap_context\n"
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);
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cothread_t co_active() {
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if(!co_active_handle) {
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co_active_handle = (struct ppc64_context*)malloc(MIN_STACK + sizeof(struct ppc64_context));
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}
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return (cothread_t)co_active_handle;
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}
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cothread_t co_derive(void* memory, unsigned int size, void (*coentry)(void)) {
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uint8_t* sp;
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struct ppc64_context* context = (struct ppc64_context*)memory;
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//save current context into new context to initialize it
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swap_context(context, context);
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//align stack
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sp = (uint8_t*)memory + size - STACK_ALIGN;
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sp = (uint8_t*)ALIGN(sp, STACK_ALIGN);
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//write 0 for initial backchain
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*(uint64_t*)sp = 0;
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//create new frame with backchain
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sp -= MIN_STACK_FRAME;
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*(uint64_t*)sp = (uint64_t)(sp + MIN_STACK_FRAME);
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//update context with new stack (r1) and entrypoint (r12, lr)
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context->gprs[ 1] = (uint64_t)sp;
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context->gprs[12] = (uint64_t)coentry;
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context->lr = (uint64_t)coentry;
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return (cothread_t)memory;
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}
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cothread_t co_create(unsigned int size, void (*coentry)(void)) {
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size_t total = MAX(size, MIN_STACK) + sizeof(struct ppc64_context);
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void* memory = malloc(total);
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if(!memory) return (cothread_t)0;
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return co_derive(memory, total, coentry);
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}
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void co_delete(cothread_t handle) {
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free(handle);
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}
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void co_switch(cothread_t to) {
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struct ppc64_context* from = co_active_handle;
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co_active_handle = (struct ppc64_context*)to;
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swap_context((struct ppc64_context*)to, from);
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}
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#ifdef __cplusplus
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}
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#endif
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