mirror of https://github.com/bsnes-emu/bsnes.git
Update to v101r05 release.
byuu says:
Changelog:
- 68K: fixed bug that affected BSR return address
- VDP: added very preliminary emulation of planes A, B, W (W is
entirely broken though)
- VDP: added command/address stuff so you can write to VRAM, CRAM,
VSRAM
- VDP: added VRAM fill DMA
I would be really surprised if any commercial games showed anything at
all, so I'd probably recommend against wasting your time trying, unless
you're really bored :P
Also, I wanted to add: I am accepting patches\! So if anyone wants to
look over the 68K core for bugs, that would save me untold amounts of
time in the near future :D
This commit is contained in:
Tim Allen
parent
1df2549d18
commit
ac2d0ba1cf
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@ -12,7 +12,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "101.04";
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static const string Version = "101.05";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -15,6 +15,12 @@ auto CPU::boot() -> void {
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}
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auto CPU::main() -> void {
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#if 0
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static file fp;
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if(!fp) fp.open({Path::user(), "Desktop/trace.log"}, file::mode::write);
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fp.print(pad(disassemble(r.pc), -60, ' '), " ", disassembleRegisters().replace("\n", " "), "\n");
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#endif
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instruction();
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}
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@ -61,9 +61,9 @@ auto Interface::videoColors() -> uint32 {
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}
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auto Interface::videoColor(uint32 color) -> uint64 {
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uint B = color.bits(0,2);
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uint R = color.bits(0,2);
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uint G = color.bits(3,5);
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uint R = color.bits(6,8);
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uint B = color.bits(6,8);
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uint64 r = image::normalize(R, 3, 16);
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uint64 g = image::normalize(G, 3, 16);
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@ -0,0 +1,32 @@
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auto VDP::Background::scanline() -> void {
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}
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auto VDP::Background::run(uint x, uint y) -> void {
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output.priority = 0;
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output.color = 0;
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uint tileX = x >> 3;
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uint tileY = y >> 3;
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uint15 nametableAddress = io.nametableAddress;
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nametableAddress += (tileY << io.nametableWidth) + tileX;
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uint16 tileAttributes = vdp.vram[nametableAddress];
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uint15 tileAddress = tileAttributes.bits(0,10) << 4;
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uint pixelX = (x & 7) ^ (tileAttributes.bit(11) ? 7 : 0);
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uint pixelY = (y & 7) ^ (tileAttributes.bit(12) ? 7 : 0);
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tileAddress += pixelY << 1 | pixelX >> 2;
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uint16 tileData = vdp.vram[tileAddress];
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uint4 palette = tileData >> (((pixelX & 3) ^ 3) << 2);
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if(palette) {
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output.color = tileAttributes.bits(13,14) << 4 | palette;
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output.priority = tileAttributes.bit(15);
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}
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}
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auto VDP::Background::power() -> void {
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}
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auto VDP::Background::reset() -> void {
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memory::fill(&io, sizeof(IO));
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}
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@ -0,0 +1,18 @@
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auto VDP::dmaRun() -> void {
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if(!io.dmaEnable) return;
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if(!io.dmaActive) return;
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if(io.dmaMode == 2) return dmaFillVRAM();
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}
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auto VDP::dmaFillVRAM() -> void {
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auto address = io.address.bits(1,15);
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auto data = io.dmaFillWord;
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if(io.address.bit(0)) data = data >> 8 | data << 8;
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vram[address] = data;
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io.address += io.dataIncrement;
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if(--io.dmaLength == 0) {
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io.dmaActive = false;
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}
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}
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@ -1,10 +1,25 @@
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//todo: does data mirroring occur for all VDP addresses; or just data/control ports?
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auto VDP::readByte(uint24 addr) -> uint8 {
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return 0x00;
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auto data = readWord(addr & ~1);
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return data << 8 | data << 0;
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}
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auto VDP::writeByte(uint24 addr, uint8 data) -> void {
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return writeWord(addr & ~1, data << 8 | data << 0);
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}
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//
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auto VDP::readWord(uint24 addr) -> uint16 {
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switch(addr & 0xc0001f) {
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//data port
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case 0xc00000: case 0xc00002: {
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return readDataPort();
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}
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//control port
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case 0xc00004: case 0xc00006: {
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return readControlPort();
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}
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@ -14,19 +29,19 @@ auto VDP::readWord(uint24 addr) -> uint16 {
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return 0x0000;
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}
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auto VDP::writeByte(uint24 addr, uint8 data) -> void {
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//print("[VDP] ", hex(addr, 6L), "=", hex(data, 2L), "\n");
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}
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auto VDP::writeWord(uint24 addr, uint16 data) -> void {
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//print("[VDP] ", hex(addr, 6L), "=", hex(data, 4L), "\n");
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switch(addr & 0xc0001f) {
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//data port
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case 0xc00000: case 0xc00002: {
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return writeDataPort(data);
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}
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//control port
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case 0xc00004: case 0xc00006: {
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if(!data.bit(15)) return;
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return writeControlPort(data.bits(8,14), data.bits(0,7));
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return writeControlPort(data);
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}
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}
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@ -34,15 +49,99 @@ auto VDP::writeWord(uint24 addr, uint16 data) -> void {
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//
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auto VDP::readDataPort() -> uint16 {
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io.commandPending = false;
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//VRAM read
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if(io.command.bits(0,3) == 0) {
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return 0x0000;
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}
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//VSRAM read
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if(io.command.bits(0,3) == 4) {
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return 0x0000;
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}
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//CRAM read
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if(io.command.bits(0,3) == 8) {
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return 0x0000;
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}
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}
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auto VDP::writeDataPort(uint16 data) -> void {
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io.commandPending = false;
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//DMA VRAM fill
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if(io.command.bits(4,5) == 2) {
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io.dmaActive = true;
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io.dmaFillWord = data;
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return;
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}
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//VRAM write
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if(io.command.bits(0,3) == 1) {
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auto address = io.address.bits(1,15);
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if(io.address.bit(0)) data = data >> 8 | data << 8;
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vram[address] = data;
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io.address += io.dataIncrement;
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return;
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}
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//VSRAM write
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if(io.command.bits(0,3) == 5) {
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auto address = io.address.bits(1,6);
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if(address >= 40) return;
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//data format: ---- --yy yyyy yyyy
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vsram[address] = data.bits(0,9);
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io.address += io.dataIncrement;
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return;
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}
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//CRAM write
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if(io.command.bits(0,3) == 3) {
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auto address = io.address.bits(1,6);
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//data format: ---- bbb- ggg- rrr-
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cram[address] = data.bits(1,3) << 0 | data.bits(5,7) << 3 | data.bits(9,11) << 6;
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io.address += io.dataIncrement;
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return;
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}
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}
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//
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auto VDP::readControlPort() -> uint16 {
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io.commandPending = false;
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uint16 result = 0b0011'0100'0000'0000;
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result |= io.dmaActive << 1;
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return result;
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}
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auto VDP::writeControlPort(uint7 addr, uint8 data) -> void {
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//print("[VDPC] ", hex(addr, 2L), "=", hex(data, 2L), "\n");
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auto VDP::writeControlPort(uint16 data) -> void {
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//print("[VDPC] ", hex(data, 4L), "\n");
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switch(addr) {
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//command write (lo)
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if(io.commandPending) {
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io.commandPending = false;
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io.command.bits(2,5) = data.bits(4,7);
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io.address.bits(14,15) = data.bits(0,1);
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return;
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}
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//command write (hi)
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if(data.bits(14,15) != 2) {
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io.commandPending = true;
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io.command.bits(0,1) = data.bits(14,15);
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io.address.bits(0,13) = data.bits(0,13);
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return;
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}
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//register write (d13 is ignored)
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if(data.bits(14,15) == 2)
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switch(data.bits(8,12)) {
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//mode register 1
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case 0x00: {
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io.verticalBlankInterruptEnable = data.bit(5);
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io.displayEnable = data.bit(6);
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io.externalVRAM = data.bit(7);
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if(!io.dmaEnable) io.command.bit(5) = 0;
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return;
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}
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//plane A name table location
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case 0x02: {
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io.nametablePlaneA = data.bits(3,6);
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planeA.io.nametableAddress = data.bits(3,6) << 12;
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return;
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}
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//window name table location
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case 0x03: {
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io.nametableWindow = data.bits(1,6);
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window.io.nametableAddress = data.bits(1,6) << 10;
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return;
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}
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//plane B name table location
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case 0x04: {
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io.nametablePlaneB = data.bits(0,3);
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planeB.io.nametableAddress = data.bits(0,3) << 12;
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return;
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}
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//background color
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case 0x07: {
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io.backgroundIndex = data.bits(0,3);
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io.backgroundPalette = data.bits(4,5);
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return;
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}
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//unused
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case 0x08: {
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return;
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}
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//unused
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case 0x09: {
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io.backgroundColor = data.bits(0,5);
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return;
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}
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@ -149,30 +240,64 @@ auto VDP::writeControlPort(uint7 addr, uint8 data) -> void {
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return;
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}
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//VRAM auto-increment value
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//data port auto-increment value
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case 0x0f: {
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io.vramAutoIncrement = data.bits(0,7);
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io.dataIncrement = data.bits(0,7);
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return;
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}
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//plane size
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case 0x10: {
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io.horizontalPlaneSize = data.bits(0,1);
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io.verticalPlaneSize = data.bits(4,5);
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//0 = 32 tiles
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//1 = 64 tiles
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//2 = invalid (repeats first row for every scanline)
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//3 = 128 tiles
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static const uint shift[] = {5, 6, 0, 7};
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planeA.io.nametableWidth = shift[data.bits(0,1)];
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window.io.nametableWidth = shift[data.bits(0,1)];
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planeB.io.nametableWidth = shift[data.bits(0,1)];
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planeA.io.nametableHeight = shift[data.bits(4,5)];
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window.io.nametableHeight = shift[data.bits(4,5)];
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planeB.io.nametableHeight = shift[data.bits(4,5)];
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return;
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}
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//window plane horizontal position
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case 0x11: {
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io.horizontalWindowPlanePosition = data.bits(0,4);
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io.horizontalWindowPlaneRight = data.bit(7);
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if(!data) {
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//disable
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io.windowHorizontalLo = ~0;
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io.windowHorizontalHi = ~0;
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} else if(data.bit(7) == 0) {
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//left
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io.windowHorizontalLo = 0;
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io.windowHorizontalHi = (data.bits(0,4) << 4) - 1;
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} else {
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//right
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io.windowHorizontalLo = (data.bits(0,4) << 4) - 1;
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io.windowHorizontalHi = ~0;
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}
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return;
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}
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//window plane vertical position
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case 0x12: {
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io.verticalWindowPlanePosition = data.bits(0,4);
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io.verticalWindowPlaneDown = data.bit(7);
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if(!data) {
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//disable
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io.windowVerticalLo = ~0;
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io.windowVerticalHi = ~0;
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} else if(data.bit(7) == 0) {
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//up
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io.windowVerticalLo = 0;
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io.windowVerticalHi = (data.bits(0,4) << 3) - 1;
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} else {
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//down
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io.windowVerticalLo = (data.bits(0,4) << 3) - 1;
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io.windowVerticalHi = ~0;
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}
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return;
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}
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@ -207,5 +332,10 @@ auto VDP::writeControlPort(uint7 addr, uint8 data) -> void {
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return;
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}
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//unused
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default: {
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return;
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}
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}
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}
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@ -0,0 +1,36 @@
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auto VDP::scanline() -> void {
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state.x = 0;
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if(++state.y >= 262) state.y = 0;
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if(state.y == 0) scheduler.exit(Scheduler::Event::Frame);
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state.output = buffer + (state.y * 2 + 0) * 1280;
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}
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auto VDP::run() -> void {
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if(!io.displayEnable) return outputPixel(0);
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bool windowed = false; //todo: broken
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windowed &= state.x >= io.windowHorizontalLo && state.x <= io.windowHorizontalHi;
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windowed &= state.y >= io.windowVerticalLo && state.y <= io.windowVerticalHi;
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auto& planeA = windowed ? this->window : this->planeA;
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planeA.run(state.x, state.y);
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planeB.run(state.x, state.y);
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auto output = io.backgroundColor;
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if(auto color = planeB.output.color) output = color;
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if(auto color = planeA.output.color) output = color;
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if(planeB.output.priority) if(auto color = planeB.output.color) output = color;
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if(planeA.output.priority) if(auto color = planeA.output.color) output = color;
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outputPixel(cram[output]);
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state.x++;
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}
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auto VDP::outputPixel(uint9 color) -> void {
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for(auto n : range(4)) {
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state.output[ 0 + n] = color;
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state.output[1280 + n] = color;
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}
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state.output += 4;
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}
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@ -7,32 +7,33 @@ namespace MegaDrive {
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VDP vdp;
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#include "io.cpp"
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#include "dma.cpp"
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#include "render.cpp"
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#include "background.cpp"
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auto VDP::Enter() -> void {
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while(true) scheduler.synchronize(), vdp.main();
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}
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auto VDP::main() -> void {
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for(uint y : range(262)) {
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auto outputLo = buffer + (y * 2 + 0) * 1280;
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auto outputHi = buffer + (y * 2 + 1) * 1280;
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for(uint x : range(342)) {
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if(y < 240 && x < 320) {
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for(uint n : range(4)) {
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*outputLo++ = 511;
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*outputHi++ = 511;
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}
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}
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scanline();
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if(state.y < 240) {
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for(uint x : range(320)) {
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run();
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step(1);
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}
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if(y == 240) scheduler.exit(Scheduler::Event::Frame);
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} else {
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step(342);
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}
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step(22);
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}
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auto VDP::step(uint clocks) -> void {
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Thread::step(clocks);
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synchronize(cpu);
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while(clocks--) {
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dmaRun();
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Thread::step(1);
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synchronize(cpu);
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}
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}
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auto VDP::refresh() -> void {
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@ -40,12 +41,19 @@ auto VDP::refresh() -> void {
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}
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auto VDP::power() -> void {
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planeA.power();
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window.power();
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planeB.power();
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}
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auto VDP::reset() -> void {
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create(VDP::Enter, system.colorburst() * 15.0 / 10.0);
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memory::fill(&io, sizeof(IO));
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planeA.reset();
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window.reset();
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planeB.reset();
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}
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}
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|
|
@ -9,16 +9,67 @@ struct VDP : Thread {
|
|||
auto power() -> void;
|
||||
auto reset() -> void;
|
||||
|
||||
//io.cpp
|
||||
auto readByte(uint24 addr) -> uint8;
|
||||
auto readWord(uint24 addr) -> uint16;
|
||||
auto writeByte(uint24 addr, uint8 data) -> void;
|
||||
|
||||
auto readWord(uint24 addr) -> uint16;
|
||||
auto writeWord(uint24 addr, uint16 data) -> void;
|
||||
|
||||
auto readDataPort() -> uint16;
|
||||
auto writeDataPort(uint16 data) -> void;
|
||||
|
||||
auto readControlPort() -> uint16;
|
||||
auto writeControlPort(uint7 addr, uint8 data) -> void;
|
||||
auto writeControlPort(uint16 data) -> void;
|
||||
|
||||
//dma.cpp
|
||||
auto dmaRun() -> void;
|
||||
auto dmaFillVRAM() -> void;
|
||||
|
||||
//render.cpp
|
||||
auto scanline() -> void;
|
||||
auto run() -> void;
|
||||
auto outputPixel(uint9 color) -> void;
|
||||
|
||||
//background.cpp
|
||||
struct Background {
|
||||
auto scanline() -> void;
|
||||
auto run(uint x, uint y) -> void;
|
||||
|
||||
auto power() -> void;
|
||||
auto reset() -> void;
|
||||
|
||||
struct IO {
|
||||
uint15 nametableAddress;
|
||||
uint3 nametableWidth; //1 << value
|
||||
uint3 nametableHeight; //1 << value
|
||||
} io;
|
||||
|
||||
struct Output {
|
||||
uint6 color;
|
||||
boolean priority;
|
||||
} output;
|
||||
};
|
||||
Background planeA;
|
||||
Background window;
|
||||
Background planeB;
|
||||
|
||||
uint16 vram[32768];
|
||||
uint16 vramExpansion[32768]; //not present in stock Mega Drive hardware
|
||||
uint9 cram[64];
|
||||
uint10 vsram[40];
|
||||
|
||||
private:
|
||||
struct IO {
|
||||
//internal state
|
||||
boolean dmaActive;
|
||||
uint8 dmaFillWord;
|
||||
|
||||
//command
|
||||
uint6 command;
|
||||
uint16 address;
|
||||
boolean commandPending;
|
||||
|
||||
//$00 mode register 1
|
||||
uint1 displayOverlayEnable;
|
||||
uint1 counterLatch;
|
||||
|
|
@ -33,15 +84,6 @@ private:
|
|||
uint1 displayEnable;
|
||||
uint1 externalVRAM;
|
||||
|
||||
//$02 plane A name table location
|
||||
uint4 nametablePlaneA;
|
||||
|
||||
//$03 window name table location
|
||||
uint6 nametableWindow;
|
||||
|
||||
//$04 plane B name table location
|
||||
uint4 nametablePlaneB;
|
||||
|
||||
//$05 sprite attribute table location
|
||||
uint8 attrtableSprite;
|
||||
|
||||
|
|
@ -49,8 +91,7 @@ private:
|
|||
uint1 nametableBaseSprite;
|
||||
|
||||
//$07 background color
|
||||
uint4 backgroundIndex;
|
||||
uint2 backgroundPalette;
|
||||
uint6 backgroundColor;
|
||||
|
||||
//$0a horizontal interrupt counter
|
||||
uint8 horizontalInterruptCounter;
|
||||
|
|
@ -75,20 +116,16 @@ private:
|
|||
uint1 nametableBasePatternA;
|
||||
uint1 nametableBasePatternB;
|
||||
|
||||
//$0f VRAM auto-increment value
|
||||
uint8 vramAutoIncrement;
|
||||
|
||||
//$10 plane size
|
||||
uint2 horizontalPlaneSize;
|
||||
uint2 verticalPlaneSize;
|
||||
//$0f data port auto-increment value
|
||||
uint8 dataIncrement;
|
||||
|
||||
//$11 window plane horizontal position
|
||||
uint5 horizontalWindowPlanePosition;
|
||||
uint1 horizontalWindowPlaneRight;
|
||||
uint10 windowHorizontalLo;
|
||||
uint10 windowHorizontalHi;
|
||||
|
||||
//$12 window plane vertical position
|
||||
uint5 verticalWindowPlanePosition;
|
||||
uint1 verticalWindowPlaneDown;
|
||||
uint10 windowVerticalLo;
|
||||
uint10 windowVerticalHi;
|
||||
|
||||
//$13-$14 DMA length
|
||||
uint16 dmaLength;
|
||||
|
|
@ -98,6 +135,12 @@ private:
|
|||
uint2 dmaMode;
|
||||
} io;
|
||||
|
||||
struct State {
|
||||
uint32* output = nullptr;
|
||||
uint x;
|
||||
uint y;
|
||||
} state;
|
||||
|
||||
uint32 buffer[1280 * 480];
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,14 @@
|
|||
auto M68K::instruction() -> void {
|
||||
instructionsExecuted++;
|
||||
|
||||
//if(instructionsExecuted >= 2000010) trap();
|
||||
//if(instructionsExecuted >= 2000000) {
|
||||
// print(disassembleRegisters(), "\n");
|
||||
// print(disassemble(r.pc), "\n");
|
||||
// print("\n");
|
||||
//}
|
||||
#if 0
|
||||
if(instructionsExecuted >= 10000010) while(true) step(1);
|
||||
if(instructionsExecuted >= 10000000) {
|
||||
print(disassembleRegisters(), "\n");
|
||||
print(disassemble(r.pc), "\n");
|
||||
print("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
opcode = readPC();
|
||||
return instructionTable[opcode]();
|
||||
|
|
|
|||
|
|
@ -248,13 +248,10 @@ auto M68K::instructionASR(EffectiveAddress modify) -> void {
|
|||
|
||||
auto M68K::instructionBCC(uint4 condition, uint8 displacement) -> void {
|
||||
auto extension = readPC<Word>();
|
||||
if(displacement) r.pc -= 2;
|
||||
if(condition >= 2 && !testCondition(condition)) return;
|
||||
if(condition == 1) push<Long>(r.pc);
|
||||
if(condition >= 2 && !testCondition(condition)) { //0 = BRA; 1 = BSR
|
||||
if(displacement) r.pc -= 2;
|
||||
} else {
|
||||
r.pc -= 2;
|
||||
r.pc += displacement ? sign<Byte>(displacement) : sign<Word>(extension);
|
||||
}
|
||||
r.pc += displacement ? (int8_t)displacement : (int16_t)extension - 2;
|
||||
}
|
||||
|
||||
template<uint Size> auto M68K::instructionBCHG(DataRegister bit, EffectiveAddress with) -> void {
|
||||
|
|
|
|||
|
|
@ -35,13 +35,13 @@ struct M68K {
|
|||
};};
|
||||
|
||||
struct Vector { enum : uint {
|
||||
Illegal = 4,
|
||||
DivisionByZero = 5,
|
||||
BoundsCheck = 6,
|
||||
Overflow = 7,
|
||||
Unprivileged = 8,
|
||||
IllegalLineA = 10,
|
||||
IllegalLineF = 11,
|
||||
Illegal = 4,
|
||||
DivisionByZero = 5,
|
||||
BoundsCheck = 6,
|
||||
Overflow = 7,
|
||||
Unprivileged = 8,
|
||||
IllegalLineA = 10,
|
||||
IllegalLineF = 11,
|
||||
};};
|
||||
|
||||
M68K();
|
||||
|
|
|
|||
|
|
@ -112,12 +112,12 @@ auto pCanvas::_paint() -> void {
|
|||
bmi.bmiHeader.biCompression = BI_RGB;
|
||||
bmi.bmiHeader.biWidth = width;
|
||||
bmi.bmiHeader.biHeight = -height; //GDI stores bitmaps upside now; negative height flips bitmap
|
||||
bmi.bmiHeader.biSizeImage = pixels.size() * sizeof(uint32);
|
||||
bmi.bmiHeader.biSizeImage = pixels.size() * sizeof(uint32_t);
|
||||
void* bits = nullptr;
|
||||
HBITMAP bitmap = CreateDIBSection(hdc, &bmi, DIB_RGB_COLORS, &bits, nullptr, 0);
|
||||
if(bits) {
|
||||
auto source = (const uint8*)pixels.data();
|
||||
auto target = (uint8*)bits;
|
||||
auto source = (const uint8_t*)pixels.data();
|
||||
auto target = (uint8_t*)bits;
|
||||
for(auto n : range(width * height)) {
|
||||
target[0] = (source[0] * source[3]) / 255;
|
||||
target[1] = (source[1] * source[3]) / 255;
|
||||
|
|
@ -155,7 +155,7 @@ auto pCanvas::_rasterize() -> void {
|
|||
pixels.resize(width * height);
|
||||
|
||||
if(auto& icon = state().icon) {
|
||||
memory::copy(pixels.data(), icon.data(), width * height * sizeof(uint32));
|
||||
memory::copy(pixels.data(), icon.data(), width * height * sizeof(uint32_t));
|
||||
} else if(auto& gradient = state().gradient) {
|
||||
auto& colors = gradient.state.colors;
|
||||
image fill;
|
||||
|
|
@ -163,7 +163,7 @@ auto pCanvas::_rasterize() -> void {
|
|||
fill.gradient(colors[0].value(), colors[1].value(), colors[2].value(), colors[3].value());
|
||||
memory::copy(pixels.data(), fill.data(), fill.size());
|
||||
} else {
|
||||
uint32 color = state().color.value();
|
||||
uint32_t color = state().color.value();
|
||||
for(auto& pixel : pixels) pixel = color;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ template<uint Bits> struct Natural {
|
|||
|
||||
struct Reference {
|
||||
inline Reference(Natural& source, uint lo, uint hi) : source(source), Lo(lo), Hi(hi) {}
|
||||
inline auto& operator=(Reference& source) { return set(source.get()); }
|
||||
|
||||
inline auto get() const -> type {
|
||||
const type RangeBits = Hi - Lo + 1;
|
||||
|
|
@ -162,6 +163,7 @@ template<uint Bits> struct Integer {
|
|||
|
||||
struct Reference {
|
||||
inline Reference(Integer& source, uint lo, uint hi) : source(source), Lo(lo), Hi(hi) {}
|
||||
inline auto& operator=(const Reference& source) { return set(source.get()); }
|
||||
|
||||
inline auto get() const -> utype {
|
||||
const type RangeBits = Hi - Lo + 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue