mirror of https://github.com/bsnes-emu/bsnes.git
Update to v074r04 release.
byuu says: SuperFXBus was inheriting from Bus, in other words using a copy of the same memory mapping subsystem. I've removed that and made it a simple mask, since only ROM+RAM are mapped there.
This commit is contained in:
parent
2d73086569
commit
a937f9b79b
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@ -1,63 +1,10 @@
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#ifdef SUPERFX_CPP
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#ifdef SUPERFX_CPP
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SuperFXBus superfxbus;
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namespace memory {
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namespace memory {
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SuperFXGSUROM gsurom;
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SuperFXGSURAM gsuram;
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SuperFXCPUROM fxrom;
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SuperFXCPUROM fxrom;
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SuperFXCPURAM fxram;
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SuperFXCPURAM fxram;
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}
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}
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void SuperFXBus::init() {
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map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x7fff, { &SuperFXGSUROM::read, &memory::gsurom }, { &SuperFXGSUROM::write, &memory::gsurom }, 0, memory::gsurom.size());
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map(MapMode::Linear, 0x00, 0x3f, 0x8000, 0xffff, { &SuperFXGSUROM::read, &memory::gsurom }, { &SuperFXGSUROM::write, &memory::gsurom }, 0, memory::gsurom.size());
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map(MapMode::Linear, 0x40, 0x5f, 0x0000, 0xffff, { &SuperFXGSUROM::read, &memory::gsurom }, { &SuperFXGSUROM::write, &memory::gsurom }, 0, memory::gsurom.size());
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map(MapMode::Linear, 0x60, 0x7f, 0x0000, 0xffff, { &SuperFXGSURAM::read, &memory::gsuram }, { &SuperFXGSURAM::write, &memory::gsuram }, 0, memory::gsuram.size());
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}
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//ROM / RAM access from the SuperFX CPU
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unsigned SuperFXGSUROM::size() const {
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return memory::cartrom.size();
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}
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uint8 SuperFXGSUROM::read(unsigned addr) {
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while(!superfx.regs.scmr.ron && scheduler.sync != Scheduler::SynchronizeMode::All) {
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superfx.add_clocks(6);
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superfx.synchronize_cpu();
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}
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return memory::cartrom.read(addr);
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}
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void SuperFXGSUROM::write(unsigned addr, uint8 data) {
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while(!superfx.regs.scmr.ron && scheduler.sync != Scheduler::SynchronizeMode::All) {
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superfx.add_clocks(6);
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superfx.synchronize_cpu();
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}
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memory::cartrom.write(addr, data);
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}
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unsigned SuperFXGSURAM::size() const {
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return memory::cartram.size();
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}
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uint8 SuperFXGSURAM::read(unsigned addr) {
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while(!superfx.regs.scmr.ran && scheduler.sync != Scheduler::SynchronizeMode::All) {
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superfx.add_clocks(6);
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superfx.synchronize_cpu();
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}
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return memory::cartram.read(addr);
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}
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void SuperFXGSURAM::write(unsigned addr, uint8 data) {
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while(!superfx.regs.scmr.ran && scheduler.sync != Scheduler::SynchronizeMode::All) {
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superfx.add_clocks(6);
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superfx.synchronize_cpu();
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}
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memory::cartram.write(addr, data);
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}
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//ROM / RAM access from the S-CPU
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//ROM / RAM access from the S-CPU
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unsigned SuperFXCPUROM::size() const {
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unsigned SuperFXCPUROM::size() const {
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@ -1,19 +1,3 @@
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struct SuperFXBus : Bus {
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void init();
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};
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struct SuperFXGSUROM : Memory {
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unsigned size() const;
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uint8 read(unsigned);
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void write(unsigned, uint8);
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};
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struct SuperFXGSURAM : Memory {
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unsigned size() const;
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uint8 read(unsigned);
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void write(unsigned, uint8);
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};
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struct SuperFXCPUROM : Memory {
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struct SuperFXCPUROM : Memory {
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unsigned size() const;
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unsigned size() const;
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uint8 read(unsigned);
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uint8 read(unsigned);
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@ -27,8 +11,6 @@ struct SuperFXCPURAM : Memory {
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};
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};
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namespace memory {
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namespace memory {
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extern SuperFXGSUROM gsurom;
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extern SuperFXGSURAM gsuram;
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extern SuperFXCPUROM fxrom;
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extern SuperFXCPUROM fxrom;
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extern SuperFXCPURAM fxram;
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extern SuperFXCPURAM fxram;
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}
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}
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@ -66,7 +66,7 @@ uint8 SuperFX::rpix(uint8 x, uint8 y) {
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for(unsigned n = 0; n < bpp; n++) {
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for(unsigned n = 0; n < bpp; n++) {
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unsigned byte = ((n >> 1) << 4) + (n & 1); // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
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unsigned byte = ((n >> 1) << 4) + (n & 1); // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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data |= ((superfxbus.read(addr + byte) >> x) & 1) << n;
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data |= ((bus_read(addr + byte) >> x) & 1) << n;
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}
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}
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return data;
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return data;
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@ -95,10 +95,10 @@ void SuperFX::pixelcache_flush(pixelcache_t &cache) {
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if(cache.bitpend != 0xff) {
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if(cache.bitpend != 0xff) {
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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data &= cache.bitpend;
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data &= cache.bitpend;
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data |= superfxbus.read(addr + byte) & ~cache.bitpend;
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data |= bus_read(addr + byte) & ~cache.bitpend;
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}
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}
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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superfxbus.write(addr + byte, data);
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bus_write(addr + byte, data);
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}
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}
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cache.bitpend = 0x00;
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cache.bitpend = 0x00;
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@ -36,8 +36,8 @@ void SuperFX::disassemble_opcode(char *output) {
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
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#define op0 regs.pipeline
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#define op0 regs.pipeline
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#define op1 superfxbus.read((regs.pbr << 16) + regs.r[15] + 0)
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#define op1 bus_read((regs.pbr << 16) + regs.r[15] + 0)
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#define op2 superfxbus.read((regs.pbr << 16) + regs.r[15] + 1)
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#define op2 bus_read((regs.pbr << 16) + regs.r[15] + 1)
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void SuperFX::disassemble_alt0(char *output) {
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void SuperFX::disassemble_alt0(char *output) {
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char t[256] = "";
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char t[256] = "";
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@ -1,5 +1,41 @@
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#ifdef SUPERFX_CPP
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#ifdef SUPERFX_CPP
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uint8 SuperFX::bus_read(unsigned addr) {
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if((addr & 0xc00000) == 0x000000) { //$00-3f:0000-7fff, $00-3f:8000-ffff
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while(!regs.scmr.ron && scheduler.sync != Scheduler::SynchronizeMode::All) {
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add_clocks(6);
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synchronize_cpu();
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}
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return memory::cartrom.read((((addr & 0x3f0000) >> 1) | (addr & 0x7fff)) & rom_mask);
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}
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if((addr & 0xe00000) == 0x400000) { //$40-5f:0000-ffff
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while(!regs.scmr.ron && scheduler.sync != Scheduler::SynchronizeMode::All) {
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add_clocks(6);
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synchronize_cpu();
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}
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return memory::cartrom.read(addr & rom_mask);
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}
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if((addr & 0xe00000) == 0x600000) { //$60-7f:0000-ffff
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while(!regs.scmr.ran && scheduler.sync != Scheduler::SynchronizeMode::All) {
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add_clocks(6);
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synchronize_cpu();
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}
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return memory::cartram.read(addr & ram_mask);
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}
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}
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void SuperFX::bus_write(unsigned addr, uint8 data) {
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if((addr & 0xe00000) == 0x600000) { //$60-7f:0000-ffff
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while(!regs.scmr.ran && scheduler.sync != Scheduler::SynchronizeMode::All) {
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add_clocks(6);
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synchronize_cpu();
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}
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return memory::cartram.write(addr & ram_mask, data);
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}
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}
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uint8 SuperFX::op_read(uint16 addr) {
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uint8 SuperFX::op_read(uint16 addr) {
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uint16 offset = addr - regs.cbr;
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uint16 offset = addr - regs.cbr;
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if(offset < 512) {
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if(offset < 512) {
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unsigned sp = (regs.pbr << 16) + ((regs.cbr + dp) & 0xfff0);
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unsigned sp = (regs.pbr << 16) + ((regs.cbr + dp) & 0xfff0);
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for(unsigned n = 0; n < 16; n++) {
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for(unsigned n = 0; n < 16; n++) {
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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cache.buffer[dp++] = superfxbus.read(sp++);
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cache.buffer[dp++] = bus_read(sp++);
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}
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}
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cache.valid[offset >> 4] = true;
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cache.valid[offset >> 4] = true;
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} else {
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} else {
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//$[00-5f]:[0000-ffff] ROM
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//$[00-5f]:[0000-ffff] ROM
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rombuffer_sync();
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rombuffer_sync();
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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return superfxbus.read((regs.pbr << 16) + addr);
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return bus_read((regs.pbr << 16) + addr);
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} else {
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} else {
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//$[60-7f]:[0000-ffff] RAM
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//$[60-7f]:[0000-ffff] RAM
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rambuffer_sync();
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rambuffer_sync();
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add_clocks(memory_access_speed);
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add_clocks(memory_access_speed);
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return superfxbus.read((regs.pbr << 16) + addr);
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return bus_read((regs.pbr << 16) + addr);
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}
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}
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}
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}
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}
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}
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void SuperFX::memory_reset() {
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void SuperFX::memory_reset() {
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rom_mask = memory::cartrom.size() - 1;
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ram_mask = memory::cartram.size() - 1;
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for(unsigned n = 0; n < 512; n++) cache.buffer[n] = 0x00;
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for(unsigned n = 0; n < 512; n++) cache.buffer[n] = 0x00;
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for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;
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for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;
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for(unsigned n = 0; n < 2; n++) {
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for(unsigned n = 0; n < 2; n++) {
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unsigned rom_mask; //rom_size - 1
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unsigned ram_mask; //ram_size - 1
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uint8 bus_read(unsigned addr);
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void bus_write(unsigned addr, uint8 data);
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uint8 op_read(uint16 addr);
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uint8 op_read(uint16 addr);
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alwaysinline uint8 peekpipe();
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alwaysinline uint8 peekpipe();
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alwaysinline uint8 pipe();
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alwaysinline uint8 pipe();
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void SuperFX::reset() {
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void SuperFX::reset() {
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create(SuperFX::Enter, system.cpu_frequency());
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create(SuperFX::Enter, system.cpu_frequency());
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superfxbus.init();
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instruction_counter = 0;
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instruction_counter = 0;
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for(unsigned n = 0; n < 16; n++) regs.r[n] = 0x0000;
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for(unsigned n = 0; n < 16; n++) regs.r[n] = 0x0000;
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};
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};
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extern SuperFX superfx;
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extern SuperFX superfx;
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extern SuperFXBus superfxbus;
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regs.romcl -= min(clocks, regs.romcl);
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regs.romcl -= min(clocks, regs.romcl);
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if(regs.romcl == 0) {
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if(regs.romcl == 0) {
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regs.sfr.r = 0;
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regs.sfr.r = 0;
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regs.romdr = superfxbus.read((regs.rombr << 16) + regs.r[14]);
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regs.romdr = bus_read((regs.rombr << 16) + regs.r[14]);
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}
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}
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}
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}
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if(regs.ramcl) {
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if(regs.ramcl) {
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regs.ramcl -= min(clocks, regs.ramcl);
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regs.ramcl -= min(clocks, regs.ramcl);
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if(regs.ramcl == 0) {
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if(regs.ramcl == 0) {
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superfxbus.write(0x700000 + (regs.rambr << 16) + regs.ramar, regs.ramdr);
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bus_write(0x700000 + (regs.rambr << 16) + regs.ramar, regs.ramdr);
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}
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}
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}
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}
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uint8 SuperFX::rambuffer_read(uint16 addr) {
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uint8 SuperFX::rambuffer_read(uint16 addr) {
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rambuffer_sync();
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rambuffer_sync();
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return superfxbus.read(0x700000 + (regs.rambr << 16) + addr);
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return bus_read(0x700000 + (regs.rambr << 16) + addr);
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}
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}
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void SuperFX::rambuffer_write(uint16 addr, uint8 data) {
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void SuperFX::rambuffer_write(uint16 addr, uint8 data) {
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namespace SNES {
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namespace SNES {
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namespace Info {
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namespace Info {
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static const char Name[] = "bsnes";
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static const char Name[] = "bsnes";
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static const char Version[] = "074.03";
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static const char Version[] = "074.04";
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static const unsigned SerializerVersion = 17;
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static const unsigned SerializerVersion = 17;
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}
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}
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}
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}
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