mirror of https://github.com/bsnes-emu/bsnes.git
Update to v103r28 release.
byuu says: Changelog: - processor/arm7tdmi: implemented 10 of 19 ARM instructions - processor/arm7tdmi: implemented 1 of 22 THUMB instructions Today's WIP was 6 hours of work, and yesterday's was 5 hours. Half of today was just trying to come up with the design to use a lambda-based dispatcher to map both instructions and disassembly, similar to the 68K core. The problem is that the ARM core has 28 unique bits, which is just far too many bits to have a full lookup table like the 16-bit 68K core. The thing I wanted more than anything else was to perform the opcode bitfield decoding once, and have it decoded for both instructions and the disassembler. It took three hours to come up with a design that worked for the ARM half ... relying on #defines being able to pull in other #defines that were declared and changed later after the first one. But, I'm happy with it. The decoding is in the table building, as it is with the 68K core. The decoding does happen at run-time on each instruction invocation, but it has to be done. As to the THUMB core, I can create a 64K-entry lambda table to cover all possible encodings, and ... even though it's a cache killer, I've decided to go for it, given the outstanding performance it obtained in the M68K core, as well as considering that THUMB mode is far more common in GBA games. As to both cores ... I'm a little torn between two extremes: On the one hand, I can condense the number of ARM/THUMB instructions further to eliminate more redundant code. On the other, I can split them apart to reduce the number of conditional tests needed to execute each instruction. It's really the disassembler that makes me not want to split them up further ... as I have to split the disassembler functions up equally to the instruction functions. But it may be worth it if it's a speed improvement.
This commit is contained in:
Tim Allen
parent
0b6f1df987
commit
a72ff8b7fa
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@ -12,7 +12,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "103.27";
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static const string Version = "103.28";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -81,7 +81,7 @@ auto ARM::disassembleInstructionARM(uint32 pc) -> string {
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uint4 rm = instruction;
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output.append("swp", conditions[condition], byte ? "b " : " ");
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output.append(registers[rd], ",", registers[rm], "[", registers[rn], "]");
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output.append(registers[rd], ",", registers[rm], ",[", registers[rn], "]");
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return output;
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}
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@ -1,6 +1,6 @@
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auto ARM7TDMI::ADD(uint32 source, uint32 modify, bool carry, bool updateFlags) -> uint32 {
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auto ARM7TDMI::ADD(uint32 source, uint32 modify, bool carry) -> uint32 {
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uint32 result = source + modify + carry;
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if(updateFlags) {
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if(cpsr().t || opcode.bit(20)) {
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uint32 overflow = ~(source ^ modify) & (source ^ result);
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cpsr().v = 1 << 31 & (overflow);
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cpsr().c = 1 << 31 & (overflow ^ source ^ modify ^ result);
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@ -18,8 +18,8 @@ auto ARM7TDMI::ASR(uint32 source, uint8 shift) -> uint32 {
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return source;
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}
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auto ARM7TDMI::BIT(uint32 result, bool updateFlags) -> uint32 {
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if(updateFlags) {
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auto ARM7TDMI::BIT(uint32 result) -> uint32 {
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if(cpsr().t || opcode.bit(20)) {
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cpsr().c = carry;
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cpsr().z = result == 0;
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cpsr().n = result.bit(31);
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@ -43,13 +43,13 @@ auto ARM7TDMI::LSR(uint32 source, uint8 shift) -> uint32 {
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return source;
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}
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auto ARM7TDMI::MUL(uint32 product, uint32 multiplicand, uint32 multiplier, bool updateFlags) -> uint32 {
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auto ARM7TDMI::MUL(uint32 product, uint32 multiplicand, uint32 multiplier) -> uint32 {
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idle();
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if(multiplier >> 8 && multiplier >> 8 != 0xffffff) idle();
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if(multiplier >> 16 && multiplier >> 16 != 0xffff) idle();
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if(multiplier >> 24 && multiplier >> 24 != 0xff) idle();
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product += multiplicand * multiplier;
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if(updateFlags) {
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if(cpsr().t || opcode.bit(20)) {
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cpsr().z = product == 0;
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cpsr().n = product.bit(31);
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}
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@ -69,8 +69,8 @@ auto ARM7TDMI::RRX(uint32 source) -> uint32 {
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return cpsr().c << 31 | source >> 1;
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}
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auto ARM7TDMI::SUB(uint32 source, uint32 modify, bool carry, bool updateFlags) -> uint32 {
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return ADD(source, ~modify, carry, updateFlags);
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auto ARM7TDMI::SUB(uint32 source, uint32 modify, bool carry) -> uint32 {
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return ADD(source, ~modify, carry);
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}
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auto ARM7TDMI::TST(uint4 mode) -> bool {
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@ -10,6 +10,12 @@ namespace Processor {
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#include "instructions-arm.cpp"
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#include "instructions-thumb.cpp"
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#include "serialization.cpp"
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#include "disassembler.cpp"
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ARM7TDMI::ARM7TDMI() {
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armInitialize();
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thumbInitialize();
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}
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auto ARM7TDMI::power() -> void {
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processor = {};
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@ -20,4 +26,21 @@ auto ARM7TDMI::power() -> void {
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irq = 0;
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}
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struct CPU : ARM7TDMI {
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auto step(uint) -> void {}
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auto sleep() -> void {}
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auto get(uint, uint32) -> uint32 {}
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auto set(uint, uint32, uint32) -> void {}
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CPU() {
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/*
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uint32 opcode = 0x00337e92;
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uint12 id = (opcode & 0x0ff00000) >> 16 | (opcode & 0x000000f0) >> 4;
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print("!!", hex(id), "\n");
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armInstruction[id](opcode);
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print(armDisassemble[id](opcode), "\n");
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*/
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}
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} cpu;
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}
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@ -24,6 +24,7 @@ struct ARM7TDMI {
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virtual auto set(uint mode, uint32 address, uint32 word) -> void = 0;
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//arm7tdmi.cpp
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ARM7TDMI();
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auto power() -> void;
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//registers.cpp
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@ -44,31 +45,51 @@ struct ARM7TDMI {
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auto store(uint mode, uint32 address, uint32 word) -> void;
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//algorithms.cpp
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auto ADD(uint32, uint32, bool, bool = true) -> uint32;
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auto ADD(uint32, uint32, bool) -> uint32;
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auto ASR(uint32, uint8) -> uint32;
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auto BIT(uint32, bool = true) -> uint32;
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auto BIT(uint32) -> uint32;
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auto LSL(uint32, uint8) -> uint32;
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auto LSR(uint32, uint8) -> uint32;
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auto MUL(uint32, uint32, uint32, bool = true) -> uint32;
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auto MUL(uint32, uint32, uint32) -> uint32;
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auto ROR(uint32, uint8) -> uint32;
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auto RRX(uint32) -> uint32;
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auto SUB(uint32, uint32, bool, bool = true) -> uint32;
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auto SUB(uint32, uint32, bool) -> uint32;
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auto TST(uint4) -> bool;
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//instruction.cpp
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auto fetch() -> void;
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auto instruction() -> void;
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auto interrupt(uint mode, uint32 address) -> void;
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auto armInitialize() -> void;
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auto thumbInitialize() -> void;
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//instructions-arm.cpp
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auto armALU(uint4 mode, uint4 target, uint4 source, uint32 data, bool save) -> void;
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auto armALU(uint4 mode, uint4 target, uint4 source, uint32 data) -> void;
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auto armMoveToStatus(uint4 field, uint1 source, uint32 data) -> void;
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auto armInstructionBranchExchangeRegister(uint4) -> void;
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auto armInstructionLoadImmediate(uint8, uint1, uint4, uint4, uint1, uint1, uint1) -> void;
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auto armInstructionLoadRegister(uint4, uint1, uint4, uint4, uint1, uint1, uint1) -> void;
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auto armInstructionMemorySwap(uint4, uint4, uint4, uint1) -> void;
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auto armInstructionMoveHalfImmediate(uint8, uint4, uint4, uint1, uint1, uint1, uint1) -> void;
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auto armInstructionMoveHalfRegister(uint4, uint4, uint4, uint1, uint1, uint1, uint1) -> void;
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auto armInstructionMoveToRegisterFromStatus(uint4, uint1) -> void;
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auto armInstructionMoveToStatusFromImmediate(uint8, uint4, uint4, uint1) -> void;
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auto armInstructionMoveToStatusFromRegister(uint4, uint4, uint1) -> void;
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auto armInstructionMultiply(uint4, uint4, uint4, uint4, uint1, uint1) -> void;
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auto armInstructionMultiplyLong(uint4, uint4, uint4, uint4, uint1, uint1, uint1) -> void;
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//instructions-thumb.cpp
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auto thumbALU(uint4 mode, uint4 target, uint4 source) -> void;
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auto thumbInstructionAdjustRegister(uint3, uint3, uint3, uint1) -> void;
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//serialization.cpp
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auto serialize(serializer&) -> void;
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//disassembler.cpp
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auto disassemble(uint32 pc) -> string;
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struct GPR {
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inline operator uint32_t() const {
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return data;
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@ -86,10 +107,15 @@ struct ARM7TDMI {
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struct PSR {
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enum : uint {
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USR26 = 0x00, //26-bit user
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FIQ26 = 0x01, //26-bit fast interrupt
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IRQ26 = 0x02, //26-bit interrupt
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SVC26 = 0x03, //26-bit service
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USR = 0x10, //user
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FIQ = 0x11, //fast interrupt request
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IRQ = 0x12, //interrupt request
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SVC = 0x13, //supervisor (software interrupt)
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FIQ = 0x11, //fast interrupt
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IRQ = 0x12, //interrupt
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SVC = 0x13, //service
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ABT = 0x17, //abort
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UND = 0x1b, //undefined
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SYS = 0x1f, //system
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@ -173,8 +199,30 @@ struct ARM7TDMI {
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Instruction execute;
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} pipeline;
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uint32 opcode;
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boolean carry;
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boolean irq;
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function<void (uint32 opcode)> armInstruction[4096];
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function<void ()> thumbInstruction[65536];
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function<string (uint32 opcode)> armDisassemble[4096];
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function<string ()> thumbDisassemble[65536];
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//disassembler.cpp
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auto armDisassembleBranchExchangeRegister(uint4) -> string;
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auto armDisassembleLoadImmediate(uint8, uint1, uint4, uint4, uint1, uint1, uint1) -> string;
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auto armDisassembleLoadRegister(uint4, uint1, uint4, uint4, uint1, uint1, uint1) -> string;
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auto armDisassembleMemorySwap(uint4, uint4, uint4, uint1) -> string;
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auto armDisassembleMoveHalfImmediate(uint8, uint4, uint4, uint1, uint1, uint1, uint1) -> string;
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auto armDisassembleMoveHalfRegister(uint4, uint4, uint4, uint1, uint1, uint1, uint1) -> string;
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auto armDisassembleMoveToRegisterFromStatus(uint4, uint1) -> string;
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auto armDisassembleMoveToStatusFromImmediate(uint8, uint4, uint4, uint1) -> string;
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auto armDisassembleMoveToStatusFromRegister(uint4, uint4, uint1) -> string;
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auto armDisassembleMultiply(uint4, uint4, uint4, uint4, uint1, uint1) -> string;
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auto armDisassembleMultiplyLong(uint4, uint4, uint4, uint4, uint1, uint1, uint1) -> string;
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auto thumbDisassembleAdjustRegister(uint3, uint3, uint3, uint1) -> string;
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};
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}
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@ -0,0 +1,118 @@
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static uint32 _pc;
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static string _c;
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static string _r[16] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"
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};
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#define _s save ? "s" : ""
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auto ARM7TDMI::disassemble(uint32 pc) -> string {
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return "";
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}
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//
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auto ARM7TDMI::armDisassembleBranchExchangeRegister
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(uint4 m) -> string {
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return {"bx", _c, " ", _r[m]};
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}
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auto ARM7TDMI::armDisassembleLoadImmediate
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(uint8 immediate, uint1 half, uint4 d, uint4 n, uint1 writeback, uint1 up, uint1 pre) -> string {
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string data;
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if(n == 15) data = {" =0x", hex(read((half ? Half : Byte) | Nonsequential,
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_pc + 8 + (up ? +immediate : -immediate)), half ? 4L : 2L)};
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return {"ldr", _c, half ? "sh" : "sb", " ",
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_r[d], ",[", _r[n],
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pre == 0 ? "]" : "",
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immediate ? string{",", up ? "+" : "-", "0x", hex(immediate, 2L)} : string{},
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pre == 1 ? "]" : "",
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pre == 0 || writeback ? "!" : "", data};
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}
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auto ARM7TDMI::armDisassembleLoadRegister
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(uint4 m, uint1 half, uint4 d, uint4 n, uint1 writeback, uint1 up, uint1 pre) -> string {
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return {"ldr", _c, half ? "sh" : "sb", " ",
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_r[d], ",[", _r[n],
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pre == 0 ? "]" : "",
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",", up ? "+" : "-", _r[m],
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pre == 1 ? "]" : "",
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pre == 0 || writeback ? "!" : ""};
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}
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auto ARM7TDMI::armDisassembleMemorySwap
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(uint4 m, uint4 d, uint4 n, uint1 byte) -> string {
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return {"swp", _c, byte ? "b" : "", " ", _r[d], ",", _r[m], ",[", _r[n], "]"};
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}
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auto ARM7TDMI::armDisassembleMoveHalfImmediate
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(uint8 immediate, uint4 d, uint4 n, uint1 mode, uint1 writeback, uint1 up, uint1 pre) -> string {
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string data;
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if(n == 15) data = {" =0x", hex(read(Half | Nonsequential, _pc + (up ? +immediate : -immediate)), 4L)};
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return {mode ? "ldr" : "str", _c, "h ",
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_r[d], ",[", _r[n],
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pre == 0 ? "]" : "",
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immediate ? string{",", up ? "+" : "-", "0x", hex(immediate, 2L)} : string{},
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pre == 1 ? "]" : "",
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pre == 0 || writeback ? "!" : "", data};
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}
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auto ARM7TDMI::armDisassembleMoveHalfRegister
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(uint4 m, uint4 d, uint4 n, uint1 mode, uint1 writeback, uint1 up, uint1 pre) -> string {
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return {mode ? "ldr" : "str", _c, "h ",
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_r[d], ",[", _r[n],
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pre == 0 ? "]" : "",
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",", up ? "+" : "-", _r[m],
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pre == 1 ? "]" : "",
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pre == 0 || writeback ? "!" : ""};
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}
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auto ARM7TDMI::armDisassembleMoveToRegisterFromStatus
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(uint4 d, uint1 mode) -> string {
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return {"mrs", _c, " ", _r[d], ",", mode ? "spsr" : "cpsr"};
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}
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auto ARM7TDMI::armDisassembleMoveToStatusFromImmediate
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(uint8 immediate, uint4 rotate, uint4 field, uint1 mode) -> string {
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uint32 data = immediate >> (rotate << 1) | immediate << 32 - (rotate << 1);
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return {"msr", _c, " ", mode ? "spsr:" : "cpsr:",
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field.bit(0) ? "c" : "",
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field.bit(1) ? "x" : "",
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field.bit(2) ? "s" : "",
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field.bit(3) ? "f" : "",
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",#0x", hex(data, 8L)};
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}
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auto ARM7TDMI::armDisassembleMoveToStatusFromRegister
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(uint4 m, uint4 field, uint1 mode) -> string {
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return {"msr", _c, " ", mode ? "spsr:" : "cpsr:",
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field.bit(0) ? "c" : "",
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field.bit(1) ? "x" : "",
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field.bit(2) ? "s" : "",
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field.bit(3) ? "f" : "",
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",", _r[m]};
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}
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auto ARM7TDMI::armDisassembleMultiply
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(uint4 m, uint4 s, uint4 n, uint4 d, uint1 save, uint1 accumulate) -> string {
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if(accumulate) {
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return {"mla", _c, _s, " ", _r[d], ",", _r[m], ",", _r[s], ",", _r[n]};
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} else {
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return {"mul", _c, _s, " ", _r[d], ",", _r[m], ",", _r[s]};
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}
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}
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auto ARM7TDMI::armDisassembleMultiplyLong
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(uint4 m, uint4 s, uint4 l, uint4 h, uint1 save, uint1 accumulate, uint1 sign) -> string {
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return {sign ? "s" : "u", accumulate ? "mlal" : "mull", _c, _s, " ",
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_r[l], ",", _r[h], ",", _r[m], ",", _r[s]};
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}
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//
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auto ARM7TDMI::thumbDisassembleAdjustRegister
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(uint3 d, uint3 n, uint3 m, uint1 mode) -> string {
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return {!mode ? "add" : "sub", " ", _r[d], ",", _r[n], ",", _r[m]};
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}
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@ -35,9 +35,12 @@ auto ARM7TDMI::instruction() -> void {
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return;
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}
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opcode = pipeline.execute.instruction;
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if(!cpsr().t) {
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if(!TST(pipeline.execute.instruction.bits(28,31))) return;
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if(!TST(opcode.bits(28,31))) return;
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armInstruction[(opcode & 0x0ff00000) >> 16 | (opcode & 0x000000f0) >> 4](opcode);
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} else {
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thumbInstruction[opcode & 0xffff]();
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}
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}
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@ -51,3 +54,188 @@ auto ARM7TDMI::interrupt(uint mode, uint32 address) -> void {
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r(14) = pipeline.decode.address;
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r(15) = address;
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}
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auto ARM7TDMI::armInitialize() -> void {
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#define bind(id, name, ...) { \
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uint index = (id & 0x0ff00000) >> 16 | (id & 0x000000f0) >> 4; \
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assert(!armInstruction[index]); \
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armInstruction[index] = [&](uint32 opcode) { return armInstruction##name(arguments); }; \
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armDisassemble[index] = [&](uint32 opcode) { return armDisassemble##name(arguments); }; \
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}
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#define pattern(s) \
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std::integral_constant<uint32_t, bit::test(s)>::value
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#define arguments \
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opcode.bits( 0, 3) /* m */
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{
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auto opcode = pattern(".... 0001 0010 ---- ---- ---- 0001 ????");
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bind(opcode, BranchExchangeRegister);
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}
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#undef arguments
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#define arguments \
|
||||
opcode.bits( 0, 3) << 0 | opcode.bits( 8,11) << 4, /* immediate */ \
|
||||
opcode.bit ( 5), /* half */ \
|
||||
opcode.bits(12,15), /* d */ \
|
||||
opcode.bits(16,19), /* n */ \
|
||||
opcode.bit (21), /* writeback */ \
|
||||
opcode.bit (23), /* up */ \
|
||||
opcode.bit (24) /* pre */
|
||||
for(uint1 half : range(2))
|
||||
for(uint1 writeback : range(2))
|
||||
for(uint1 up : range(2))
|
||||
for(uint1 pre : range(2)) {
|
||||
auto opcode = pattern(".... 000? ?1?1 ???? ???? ???? 11?1 ????") | half << 5 | writeback << 21 | up << 23 | pre << 24;
|
||||
bind(opcode, LoadImmediate);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bit ( 5), /* half */ \
|
||||
opcode.bits(12,15), /* d */ \
|
||||
opcode.bits(16,19), /* n */ \
|
||||
opcode.bit (21), /* writeback */ \
|
||||
opcode.bit (23), /* up */ \
|
||||
opcode.bit (24) /* pre */
|
||||
for(uint1 half : range(2))
|
||||
for(uint1 writeback : range(2))
|
||||
for(uint1 up : range(2))
|
||||
for(uint1 pre : range(2)) {
|
||||
auto opcode = pattern(".... 000? ?0?1 ???? ???? ---- 11?1 ????") | half << 5 | writeback << 21 | up << 23 | pre << 24;
|
||||
bind(opcode, LoadRegister);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bits(12,15), /* d */ \
|
||||
opcode.bits(16,19), /* n */ \
|
||||
opcode.bit (22) /* byte */
|
||||
for(uint1 byte : range(2)) {
|
||||
auto opcode = pattern(".... 0001 0?00 ???? ???? ---- 1001 ????") | byte << 22;
|
||||
bind(opcode, MemorySwap);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3) << 0 | opcode.bits( 8,11) << 4, /* immediate */ \
|
||||
opcode.bits(12,15), /* d */ \
|
||||
opcode.bits(16,19), /* n */ \
|
||||
opcode.bit (20), /* mode */ \
|
||||
opcode.bit (21), /* writeback */ \
|
||||
opcode.bit (23), /* up */ \
|
||||
opcode.bit (24) /* pre */
|
||||
for(uint1 mode : range(2))
|
||||
for(uint1 writeback : range(2))
|
||||
for(uint1 up : range(2))
|
||||
for(uint1 pre : range(2)) {
|
||||
auto opcode = pattern(".... 000? ?1?? ???? ???? ???? 1011 ????") | mode << 20 | writeback << 21 | up << 23 | pre << 24;
|
||||
bind(opcode, MoveHalfImmediate);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bits(12,15), /* d */ \
|
||||
opcode.bits(16,19), /* n */ \
|
||||
opcode.bit (20), /* mode */ \
|
||||
opcode.bit (21), /* writeback */ \
|
||||
opcode.bit (23), /* up */ \
|
||||
opcode.bit (24) /* pre */
|
||||
for(uint1 mode : range(2))
|
||||
for(uint1 writeback : range(2))
|
||||
for(uint1 up : range(2))
|
||||
for(uint1 pre : range(2)) {
|
||||
auto opcode = pattern(".... 000? ?0?? ???? ???? ---- 1011 ????") | mode << 20 | writeback << 21 | up << 23 | pre << 24;
|
||||
bind(opcode, MoveHalfRegister);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* d */ \
|
||||
opcode.bit (22) /* mode */
|
||||
for(uint1 mode : range(2)) {
|
||||
auto opcode = pattern(".... 0001 0?00 ---- ---- ---- 0000 ????") | mode << 22;
|
||||
bind(opcode, MoveToRegisterFromStatus);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 7), /* immediate */ \
|
||||
opcode.bits( 8,11), /* rotate */ \
|
||||
opcode.bits(16,19), /* field */ \
|
||||
opcode.bit (22) /* mode */
|
||||
for(uint4 immediateHi : range(16))
|
||||
for(uint1 mode : range(2)) {
|
||||
auto opcode = pattern(".... 0011 0?10 ???? ---- ???? ???? ????") | immediateHi << 4 | mode << 22;
|
||||
bind(opcode, MoveToStatusFromImmediate);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bits(16,19), /* field */ \
|
||||
opcode.bit (22) /* mode */
|
||||
for(uint1 mode : range(2)) {
|
||||
auto opcode = pattern(".... 0001 0?10 ???? ---- ---- 0000 ????") | mode << 22;
|
||||
bind(opcode, MoveToStatusFromRegister);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bits( 8,11), /* s */ \
|
||||
opcode.bits(12,15), /* n */ \
|
||||
opcode.bits(16,19), /* d */ \
|
||||
opcode.bit (20), /* save */ \
|
||||
opcode.bit (21) /* accumulate */
|
||||
for(uint1 save : range(2))
|
||||
for(uint1 accumulate : range(2)) {
|
||||
auto opcode = pattern(".... 0000 00?? ???? ???? ???? 1001 ????") | save << 20 | accumulate << 21;
|
||||
bind(opcode, Multiply);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#define arguments \
|
||||
opcode.bits( 0, 3), /* m */ \
|
||||
opcode.bits( 8,11), /* s */ \
|
||||
opcode.bits(12,15), /* l */ \
|
||||
opcode.bits(16,19), /* h */ \
|
||||
opcode.bit (20), /* save */ \
|
||||
opcode.bit (21), /* accumulate */ \
|
||||
opcode.bit (22) /* sign */
|
||||
for(uint1 save : range(2))
|
||||
for(uint1 accumulate : range(2))
|
||||
for(uint1 sign : range(2)) {
|
||||
auto opcode = pattern(".... 0000 1??? ???? ???? ???? 1001 ????") | save << 20 | accumulate << 21 | sign << 22;
|
||||
bind(opcode, MultiplyLong);
|
||||
}
|
||||
#undef arguments
|
||||
|
||||
#undef bind
|
||||
#undef pattern
|
||||
}
|
||||
|
||||
auto ARM7TDMI::thumbInitialize() -> void {
|
||||
#define bind(id, name, ...) { \
|
||||
assert(!thumbInstruction[id]); \
|
||||
thumbInstruction[id] = [=] { return thumbInstruction##name(__VA_ARGS__); }; \
|
||||
thumbDisassemble[id] = [=] { return thumbDisassemble##name(__VA_ARGS__); }; \
|
||||
}
|
||||
|
||||
#define pattern(s) \
|
||||
std::integral_constant<uint16_t, bit::test(s)>::value
|
||||
|
||||
for(uint3 d : range(8))
|
||||
for(uint3 n : range(8))
|
||||
for(uint3 m : range(8))
|
||||
for(uint1 mode : range(2)) {
|
||||
auto opcode = pattern("0001 10?? ???? ????") | d << 0 | n << 3 | m << 6 | mode << 9;
|
||||
bind(opcode, AdjustRegister, d, n, m, mode);
|
||||
}
|
||||
|
||||
#undef bind
|
||||
#undef pattern
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,24 +1,174 @@
|
|||
auto ARM7TDMI::armALU(uint4 mode, uint4 target, uint4 source, uint32 data, bool save) -> void {
|
||||
auto ARM7TDMI::armALU(uint4 mode, uint4 target, uint4 source, uint32 data) -> void {
|
||||
switch(mode) {
|
||||
case 0: r(target) = BIT(r(source) & data, save); break; //AND
|
||||
case 1: r(target) = BIT(r(source) ^ data, save); break; //EOR
|
||||
case 2: r(target) = SUB(r(source), data, 1, save); break; //SUB
|
||||
case 3: r(target) = SUB(data, r(source), 1, save); break; //RSB
|
||||
case 4: r(target) = ADD(r(source), data, 0, save); break; //ADD
|
||||
case 5: r(target) = ADD(r(source), data, cpsr().c, save); break; //ADC
|
||||
case 6: r(target) = SUB(r(source), data, cpsr().c, save); break; //SBC
|
||||
case 7: r(target) = SUB(data, r(source), cpsr().c, save); break; //RSC
|
||||
case 8: BIT(r(source) & data, save); break; //TST
|
||||
case 9: BIT(r(source) ^ data, save); break; //TEQ
|
||||
case 10: SUB(r(source), data, 1, save); break; //CMP
|
||||
case 11: ADD(r(source), data, 0, save); break; //CMN
|
||||
case 12: r(target) = BIT(r(source) | data, save); break; //ORR
|
||||
case 13: r(target) = BIT(data, save); break; //MOV
|
||||
case 14: r(target) = BIT(r(source) & ~data, save); break; //BIC
|
||||
case 15: r(target) = BIT(~data, save); break; //MVN
|
||||
case 0: r(target) = BIT(r(source) & data); break; //AND
|
||||
case 1: r(target) = BIT(r(source) ^ data); break; //EOR
|
||||
case 2: r(target) = SUB(r(source), data, 1); break; //SUB
|
||||
case 3: r(target) = SUB(data, r(source), 1); break; //RSB
|
||||
case 4: r(target) = ADD(r(source), data, 0); break; //ADD
|
||||
case 5: r(target) = ADD(r(source), data, cpsr().c); break; //ADC
|
||||
case 6: r(target) = SUB(r(source), data, cpsr().c); break; //SBC
|
||||
case 7: r(target) = SUB(data, r(source), cpsr().c); break; //RSC
|
||||
case 8: BIT(r(source) & data); break; //TST
|
||||
case 9: BIT(r(source) ^ data); break; //TEQ
|
||||
case 10: SUB(r(source), data, 1); break; //CMP
|
||||
case 11: ADD(r(source), data, 0); break; //CMN
|
||||
case 12: r(target) = BIT(r(source) | data); break; //ORR
|
||||
case 13: r(target) = BIT(data); break; //MOV
|
||||
case 14: r(target) = BIT(r(source) & ~data); break; //BIC
|
||||
case 15: r(target) = BIT(~data); break; //MVN
|
||||
}
|
||||
|
||||
if(exception() && target == 15 && save) {
|
||||
if(exception() && target == 15 && opcode.bit(20)) {
|
||||
cpsr() = spsr();
|
||||
}
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armMoveToStatus(uint4 field, uint1 mode, uint32 data) -> void {
|
||||
if(mode && (cpsr().m == PSR::USR || cpsr().m == PSR::SYS)) return;
|
||||
PSR& psr = mode ? spsr() : cpsr();
|
||||
|
||||
if(field.bit(0)) {
|
||||
if(mode || privileged()) {
|
||||
psr.m = 0x10 | data.bits(0,4);
|
||||
psr.t = data.bit (5);
|
||||
psr.f = data.bit (6);
|
||||
psr.i = data.bit (7);
|
||||
}
|
||||
}
|
||||
|
||||
if(field.bit(3)) {
|
||||
psr.v = data.bit(28);
|
||||
psr.c = data.bit(29);
|
||||
psr.z = data.bit(30);
|
||||
psr.n = data.bit(31);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
auto ARM7TDMI::armInstructionBranchExchangeRegister
|
||||
(uint4 m) -> void {
|
||||
uint32 address = r(m);
|
||||
cpsr().t = address.bit(0);
|
||||
r(15) = address;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionLoadImmediate
|
||||
(uint8 immediate, uint1 half, uint4 d, uint4 n, uint1 writeback, uint1 up, uint1 pre) -> void {
|
||||
uint32 rn = r(n);
|
||||
uint32 rd = r(d);
|
||||
|
||||
if(pre == 1) rn = up ? rn + immediate : rn - immediate;
|
||||
rd = load((half ? Half : Byte) | Nonsequential | Signed, rn);
|
||||
if(pre == 0) rn = up ? rn + immediate : rn - immediate;
|
||||
|
||||
if(pre == 0 || writeback) r(n) = rn;
|
||||
r(d) = rd;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionLoadRegister
|
||||
(uint4 m, uint1 half, uint4 d, uint4 n, uint1 writeback, uint1 up, uint1 pre) -> void {
|
||||
uint32 rn = r(n);
|
||||
uint32 rm = r(m);
|
||||
uint32 rd = r(d);
|
||||
|
||||
if(pre == 1) rn = up ? rn + rm : rn - rm;
|
||||
rd = load((half ? Half : Byte) | Nonsequential | Signed, rn);
|
||||
if(pre == 0) rn = up ? rn + rm : rn - rm;
|
||||
|
||||
if(pre == 0 || writeback) r(n) = rn;
|
||||
r(d) = rd;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMemorySwap
|
||||
(uint4 m, uint4 d, uint4 n, uint1 byte) -> void {
|
||||
uint32 word = load((byte ? Byte : Word) | Nonsequential, r(n));
|
||||
store((byte ? Byte : Word) | Nonsequential, r(n), r(m));
|
||||
r(d) = word;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMoveHalfImmediate
|
||||
(uint8 immediate, uint4 d, uint4 n, uint1 mode, uint1 writeback, uint1 up, uint1 pre) -> void {
|
||||
uint32 rn = r(n);
|
||||
uint32 rd = r(d);
|
||||
|
||||
if(pre == 1) rn = up ? rn + immediate : rn - immediate;
|
||||
if(mode == 1) rd = load(Half | Nonsequential, rn);
|
||||
if(mode == 0) store(Half | Nonsequential, rn, rd);
|
||||
if(pre == 0) rn = up ? rn + immediate : rn - immediate;
|
||||
|
||||
if(pre == 0 || writeback) r(n) = rn;
|
||||
if(mode == 1) r(d) = rd;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMoveHalfRegister
|
||||
(uint4 m, uint4 d, uint4 n, uint1 mode, uint1 writeback, uint1 up, uint1 pre) -> void {
|
||||
uint32 rn = r(n);
|
||||
uint32 rm = r(m);
|
||||
uint32 rd = r(d);
|
||||
|
||||
if(pre == 1) rn = up ? rn + rm : rn - rm;
|
||||
if(mode == 1) rd = load(Half | Nonsequential, rn);
|
||||
if(mode == 0) store(Half | Nonsequential, rn, rd);
|
||||
if(pre == 0) rn = up ? rn + rm : rn - rm;
|
||||
|
||||
if(pre == 0 || writeback) r(n) = rn;
|
||||
if(mode == 1) r(d) = rd;
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMoveToRegisterFromStatus
|
||||
(uint4 d, uint1 mode) -> void {
|
||||
if(mode && (cpsr().m == PSR::USR || cpsr().m == PSR::SYS)) return;
|
||||
r(d) = mode ? spsr() : cpsr();
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMoveToStatusFromImmediate
|
||||
(uint8 immediate, uint4 rotate, uint4 field, uint1 mode) -> void {
|
||||
uint32 data = immediate;
|
||||
if(rotate) data = ROR(data, rotate << 1);
|
||||
armMoveToStatus(field, mode, data);
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMoveToStatusFromRegister
|
||||
(uint4 m, uint4 field, uint1 mode) -> void {
|
||||
armMoveToStatus(field, mode, r(m));
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMultiply
|
||||
(uint4 m, uint4 s, uint4 n, uint4 d, uint1 save, uint1 accumulate) -> void {
|
||||
if(accumulate) idle();
|
||||
r(d) = MUL(accumulate ? r(n) : 0, r(m), r(s));
|
||||
}
|
||||
|
||||
auto ARM7TDMI::armInstructionMultiplyLong
|
||||
(uint4 m, uint4 s, uint4 l, uint4 h, uint1 save, uint1 accumulate, uint1 sign) -> void {
|
||||
uint64 rm = r(m);
|
||||
uint64 rs = r(s);
|
||||
|
||||
idle();
|
||||
idle();
|
||||
if(accumulate) idle();
|
||||
|
||||
if(sign) {
|
||||
if(rs >> 8 && rs >> 8 != 0xffffff) idle();
|
||||
if(rs >> 16 && rs >> 16 != 0xffff) idle();
|
||||
if(rs >> 24 && rs >> 24 != 0xff) idle();
|
||||
rm = (int32)rm;
|
||||
rs = (int32)rs;
|
||||
} else {
|
||||
if(rs >> 8) idle();
|
||||
if(rs >> 16) idle();
|
||||
if(rs >> 24) idle();
|
||||
}
|
||||
|
||||
uint64 rd = rm * rs;
|
||||
if(accumulate) rd += (uint64)r(h) << 32 | (uint64)r(l) << 0;
|
||||
|
||||
r(h) = rd >> 32;
|
||||
r(l) = rd >> 0;
|
||||
|
||||
if(save) {
|
||||
cpsr().z = rd == 0;
|
||||
cpsr().n = rd.bit(63);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,3 +18,13 @@ auto ARM7TDMI::thumbALU(uint4 mode, uint4 target, uint4 source) -> void {
|
|||
case 15: r(target) = BIT(~r(source)); break; //MVN
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
auto ARM7TDMI::thumbInstructionAdjustRegister
|
||||
(uint3 d, uint3 n, uint3 m, uint1 mode) -> void {
|
||||
switch(mode) {
|
||||
case 0: r(d) = ADD(r(n), r(m), 0); break;
|
||||
case 1: r(d) = SUB(r(n), r(m), 1); break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue