mirror of https://github.com/bsnes-emu/bsnes.git
Update to v087r06 release.
byuu says: I believe I've implemented every THUMB instruction now, although I'm sure there are dozens of bugs in the implementation. It seems that the last jump taken is ending up being off-by-two. It's probably due to not masking/adjusting PC correctly at certain points. I don't know if any other bugs are being hit prior to this or not. I don't implement any I/O registers yet, and the BIOS seems to be poking at a few of them along the way, so ... who knows. I could also be reading the log wrong, but it looks to me like there's some PSR setting the mode flag register to 0, which is supposed to be an undefined behavior mode ... perhaps mrs has no effect on the m/t bits, and it just affects the i/f bits?
This commit is contained in:
Tim Allen
parent
04087a74b0
commit
77578cd0a4
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@ -1,7 +1,7 @@
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#ifndef BASE_HPP
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#define BASE_HPP
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static const char Version[] = "087.05";
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static const char Version[] = "087.06";
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#include <nall/platform.hpp>
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#include <nall/algorithm.hpp>
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@ -19,6 +19,7 @@ void ARM::arm_step() {
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pipeline.fetch.instruction = bus.read(r(15), Word);
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step(2);
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//print(disassemble_registers(), "\n");
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print(disassemble_arm_opcode(pipeline.execute.address), "\n");
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if(arm_condition() == false) return;
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@ -270,7 +270,12 @@ string ARM::disassemble_arm_opcode(uint32 pc) {
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}
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string ARM::disassemble_thumb_opcode(uint32 pc) {
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static string opcodes[] = { "mov", "cmp", "add", "sub" };
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static string conditions[] = {
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"eq", "ne", "cs", "cc",
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"mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt",
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"gt", "le", "", "",
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};
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static string registers[] = {
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"r0", "r1", "r2", "r3",
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@ -284,9 +289,52 @@ string ARM::disassemble_thumb_opcode(uint32 pc) {
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uint16 instruction = bus.read(pc, Half);
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output.append(hex<4>(instruction), " ");
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//adjust_register()
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//(add,sub) rd,rn,rm
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if((instruction & 0xfc00) == 0x1800) {
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uint1 opcode = instruction >> 9;
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uint3 rm = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(opcode == 0 ? "add" : "sub", " ", registers[rd], ",", registers[rn], ",", registers[rm]);
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return output;
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}
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//adjust_immediate()
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//(add,sub) rd,rn,#immediate
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if((instruction & 0xfc00) == 0x1c00) {
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uint1 opcode = instruction >> 9;
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uint3 immediate = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(opcode == 0 ? "add" : "sub", " ", registers[rd], ",", registers[rn], ",#", hex<1>(immediate));
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return output;
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}
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//shift_immediate()
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//(lsl,lsr,asar) rd,rm,#immmediate
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if((instruction & 0xe000) == 0x0000) {
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static string opcodes[] = { "lsl", "lsr", "asr", "" };
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uint2 opcode = instruction >> 11;
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uint5 immediate = instruction >> 6;
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uint3 rm = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm], ",#", immediate);
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return output;
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}
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//immediate()
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//(mov,cmp,add,sub) (rd,rn),#immediate
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if((instruction & 0xe000) == 0x2000) {
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static string opcodes[] = { "mov", "cmp", "add", "sub" };
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uint2 opcode = instruction >> 11;
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uint3 rd = instruction >> 8;
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uint8 immediate = instruction;
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@ -296,6 +344,241 @@ string ARM::disassemble_thumb_opcode(uint32 pc) {
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return output;
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}
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//alu()
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//{opcode} rd,rm
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if((instruction & 0xfc00) == 0x4000) {
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static string opcodes[] = {
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"and", "eor", "lsl", "lsr",
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"asr", "adc", "sbc", "ror",
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"tst", "neg", "cmp", "cmn",
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"orr", "mul", "bic", "mvn",
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};
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uint4 opcode = instruction >> 6;
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uint3 rm = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm]);
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return output;
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}
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//branch_exchange()
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//bx rm
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if((instruction & 0xff80) == 0x4700) {
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uint4 rm = instruction >> 3;
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output.append("bx ", registers[rm]);
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return output;
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}
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//alu_hi()
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//{opcode} rd,rm
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if((instruction & 0xfc00) == 0x4400) {
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static string opcodes[] = { "add", "sub", "mov", "" };
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uint2 opcode = instruction >> 8;
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uint4 rm = instruction >> 3;
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uint4 rd = ((uint1)(instruction >> 7) << 3) + (uint3)instruction;
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if(opcode == 2 && rm == 8 && rd == 8) {
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output.append("nop");
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return output;
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}
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output.append(opcodes[opcode], " ", registers[rd], ",", registers[rm]);
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return output;
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}
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//load_literal()
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//ldr rd,[pc,#+/-offset]
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if((instruction & 0xf800) == 0x4800) {
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uint3 rd = instruction >> 8;
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uint8 displacement = instruction;
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unsigned rm = ((pc + 4) & ~3) + displacement * 4;
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output.append("ldr ", registers[rd], ",[pc,#0x", hex<3>(rm), "]");
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output.append(" =0x", hex<8>(bus.read(rm, Word)));
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return output;
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}
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//move_register_offset()
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//(ld(r,s),str){b,h} rd,[rn,rm]
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if((instruction & 0xf000) == 0x5000) {
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static string opcodes[] = {
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"str", "strh", "strb", "ldsb",
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"ldr", "ldrh", "ldrb", "ldsh",
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};
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uint3 opcode = instruction >> 9;
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uint3 rm = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(opcodes[opcode], " ", registers[rd], ",[", registers[rn], ",", registers[rm], "]");
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return output;
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}
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//move_word_immediate()
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//(ldr,str) rd,[rn,#offset]
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if((instruction & 0xf000) == 0x6000) {
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uint1 load = instruction >> 11;
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uint5 offset = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(load ? "ldr " : "str ", registers[rd], ",[", registers[rn], ",#0x", hex<2>(offset * 4), "]");
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return output;
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}
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//move_byte_immediate()
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//(ldr,str)b rd,[rn,#offset]
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if((instruction & 0xf000) == 0x7000) {
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uint1 load = instruction >> 11;
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uint5 offset = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(load ? "ldrb " : "strb ", registers[rd], ",[", registers[rn], ",#0x", hex<2>(offset), "]");
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return output;
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}
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//move_half_immediate()
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//(ldr,str)h rd,[rn,#offset]
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if((instruction & 0xf000) == 0x8000) {
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uint1 load = instruction >> 11;
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uint5 offset = instruction >> 6;
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uint3 rn = instruction >> 3;
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uint3 rd = instruction >> 0;
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output.append(load ? "ldrh " : "strh ", registers[rd], ",[", registers[rn], ",#0x", hex<2>(offset * 2), "]");
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return output;
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}
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//move_stack()
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//(ldr,str) rd,[sp,#relative]
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if((instruction & 0xf000) == 0x9000) {
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uint1 opcode = instruction >> 11;
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uint3 rd = instruction >> 8;
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int8 relative = instruction;
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output.append(opcode ? "ldr" : "str", " ", registers[rd], ",[sp,#0x", hex<3>(relative * 4), "]");
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return output;
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}
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//add_register_hi()
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//add rd,{pc,sp},#immediate
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if((instruction & 0xf000) == 0xa000) {
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uint1 sp = instruction >> 11;
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uint3 rd = instruction >> 8;
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uint8 immediate = instruction;
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output.append("add ", registers[rd], ",", sp ? "sp" : "pc", ",#0x", hex<2>(immediate));
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return output;
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}
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//adjust_stack()
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//(add,sub) sp,#immediate
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if((instruction & 0xff00) == 0xb000) {
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uint1 opcode = instruction >> 7;
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uint7 immediate = instruction;
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output.append(opcode == 0 ? "add" : "sub", " sp,#0x", hex<3>(immediate * 4));
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return output;
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}
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//stack_multiple()
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//push {r...{,lr}}
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//pop {r...{,pc}}
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if((instruction & 0xf600) == 0xb400) {
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uint1 load = instruction >> 11;
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uint1 branch = instruction >> 8;
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uint8 list = instruction;
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output.append(load == 0 ? "push" : "pop", " {");
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for(unsigned l = 0; l < 8; l++) {
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if(list & (1 << l)) output.append(registers[l], ",");
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}
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if(branch) output.append(load == 0 ? "lr," : "pc,");
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output.rtrim<1>(",");
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output.append("}");
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return output;
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}
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//move_multiple()
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//(ldmia,stmdb) rn,{r...}
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if((instruction & 0xf000) == 0xc000) {
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uint1 load = instruction >> 11;
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uint3 rn = instruction >> 8;
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uint8 list = instruction;
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output.append(load ? "ldmia " : "stmdb ", registers[rn], "!,{");
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for(unsigned l = 0; l < 8; l++) {
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if(list & (1 << l)) output.append(registers[l], ",");
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}
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output.rtrim<1>(",");
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output.append("}");
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return output;
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}
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//software_interrupt()
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//swi #immediate
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if((instruction & 0xff00) == 0xdf00) {
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uint8 immediate = instruction;
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output.append("swi #0x", hex<2>(immediate));
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return output;
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}
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//branch_conditional()
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//b{condition} address
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if((instruction & 0xf000) == 0xd000) {
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uint4 condition = instruction >> 8;
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int8 displacement = instruction;
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uint32 offset = pc + 4 + displacement * 2;
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output.append("b", conditions[condition], " 0x", hex<8>(offset));
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return output;
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}
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//branch_short()
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//b address
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if((instruction & 0xf800) == 0xe000) {
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int11 displacement = instruction;
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output.append("b 0x", hex<8>(pc + 4 + displacement * 2));
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return output;
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}
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//branch_long()
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//bl address
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if((instruction & 0xf800) == 0xf000) {
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uint11 offsethi = instruction;
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instruction = bus.read(pc + 2, Half);
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uint11 offsetlo = instruction;
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int22 displacement = (offsethi << 11) | (offsetlo << 0);
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output.append("bl 0x", hex<8>(pc + 4 + displacement * 2));
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output.append("\n", hex<8>(pc + 2), " ", hex<4>(instruction), " ...");
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return output;
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}
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output.append("???");
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return output;
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}
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@ -19,20 +19,81 @@ void ARM::thumb_step() {
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pipeline.fetch.instruction = bus.read(r(15), Half);
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step(1);
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//print(disassemble_registers(), "\n");
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print(disassemble_thumb_opcode(pipeline.execute.address), "\n");
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if((instruction() & 0xfc00) == 0x1800) { thumb_op_adjust_register(); return; }
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if((instruction() & 0xfc00) == 0x1c00) { thumb_op_adjust_immediate(); return; }
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if((instruction() & 0xe000) == 0x0000) { thumb_op_shift_immediate(); return; }
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if((instruction() & 0xe000) == 0x2000) { thumb_op_immediate(); return; }
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if((instruction() & 0xfc00) == 0x4000) { thumb_op_alu(); return; }
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if((instruction() & 0xff80) == 0x4700) { thumb_op_branch_exchange(); return; }
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if((instruction() & 0xfc00) == 0x4400) { thumb_op_alu_hi(); return; }
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if((instruction() & 0xf800) == 0x4800) { thumb_op_load_literal(); return; }
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if((instruction() & 0xf000) == 0x5000) { thumb_op_move_register_offset(); return; }
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if((instruction() & 0xf000) == 0x6000) { thumb_op_move_word_immediate(); return; }
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if((instruction() & 0xf000) == 0x7000) { thumb_op_move_byte_immediate(); return; }
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if((instruction() & 0xf000) == 0x8000) { thumb_op_move_half_immediate(); return; }
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if((instruction() & 0xf000) == 0x9000) { thumb_op_move_stack(); return; }
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if((instruction() & 0xf000) == 0xa000) { thumb_op_add_register_hi(); return; }
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if((instruction() & 0xff00) == 0xb000) { thumb_op_adjust_stack(); return; }
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if((instruction() & 0xf600) == 0xb400) { thumb_op_stack_multiple(); return; }
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if((instruction() & 0xf000) == 0xc000) { thumb_op_move_multiple(); return; }
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if((instruction() & 0xff00) == 0xdf00) { thumb_op_software_interrupt(); return; }
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if((instruction() & 0xf000) == 0xd000) { thumb_op_branch_conditional(); return; }
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if((instruction() & 0xf800) == 0xe000) { thumb_op_branch_short(); return; }
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if((instruction() & 0xf800) == 0xf000) { thumb_op_branch_long(); return; }
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exception = true;
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}
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void ARM::thumb_mov(GPR &source, uint32 modify) {
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bool ARM::thumb_condition(uint4 condition) {
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switch(condition) {
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case 0: return cpsr().z == 1; //EQ (equal)
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case 1: return cpsr().z == 0; //NE (not equal)
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case 2: return cpsr().c == 1; //CS (carry set)
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case 3: return cpsr().c == 0; //CC (carry clear)
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case 4: return cpsr().n == 1; //MI (negative)
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case 5: return cpsr().n == 0; //PL (positive)
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case 6: return cpsr().v == 1; //VS (overflow)
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case 7: return cpsr().v == 0; //VC (no overflow)
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case 8: return cpsr().c == 1 && cpsr().z == 0; //HI (unsigned higher)
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case 9: return cpsr().c == 0 || cpsr().z == 1; //LS (unsigned lower or same)
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case 10: return cpsr().n == cpsr().v; //GE (signed greater than or equal)
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case 11: return cpsr().n != cpsr().v; //LT (signed less than)
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case 12: return cpsr().z == 0 && cpsr().n == cpsr().v; //GT (signed greater than)
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case 13: return cpsr().z == 1 || cpsr().n != cpsr().v; //LE (signed less than or equal)
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}
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}
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void ARM::thumb_opcode(uint4 opcode, uint4 d, uint4 m) {
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switch(opcode) {
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case 0: r(d) = thumb_tst(r(d) & r(m)); break; //AND
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case 1: r(d) = thumb_tst(r(d) ^ r(m)); break; //EOR
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case 2: r(d) = thumb_lsl(r(d), r(m) & 0xff); break; //LSL
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case 3: r(d) = thumb_lsr(r(d), r(m) & 0xff); break; //LSR
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case 4: r(d) = thumb_asr(r(d), r(m) & 0xff); break; //ASR
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case 5: r(d) = thumb_add(r(d), r(m), cpsr().c); break; //ADC
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case 6: r(d) = thumb_sub(r(d), r(m), cpsr().c); break; //SBC
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case 7: r(d) = thumb_ror(r(d), r(m) & 0xff); break; //ROR
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case 8: thumb_tst(r(d) & r(m)); break; //TST
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case 9: r(d) = thumb_sub(0, r(m)); break; //NEG
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case 10: thumb_sub(r(d), r(m)); break; //CMP
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case 11: thumb_add(r(d), r(m)); break; //CMN
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case 12: r(d) = thumb_tst(r(d) | r(m)); break; //ORR
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case 13: r(d) = thumb_mul(r(d), r(m)); break; //MUL
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case 14: r(d) = thumb_tst(r(d) & ~r(m)); break; //BIC
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case 15: r(d) = thumb_tst(~r(m)); break; //MVN
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}
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}
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uint32 ARM::thumb_tst(uint32 modify) {
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cpsr().n = modify >> 31;
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cpsr().z = modify == 0;
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source = modify;
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return modify;
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}
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void ARM::thumb_cmp(GPR &source, uint32 modify) {
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void ARM::thumb_cmp(uint32 source, uint32 modify) {
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uint32 result = source - modify;
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uint32 overflow = ~(source ^ modify) & (source ^ result);
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cpsr().n = result >> 31;
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@ -41,24 +102,127 @@ void ARM::thumb_cmp(GPR &source, uint32 modify) {
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cpsr().v = (1u << 31) & (overflow);
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}
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void ARM::thumb_add(GPR &source, uint32 modify) {
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uint32 result = source + modify;
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uint32 ARM::thumb_add(uint32 source, uint32 modify, bool carry) {
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uint32 result = source + modify + carry;
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uint32 overflow = ~(source ^ modify) & (source ^ result);
|
||||
cpsr().n = result >> 31;
|
||||
cpsr().z = result == 0;
|
||||
cpsr().c = (1u << 31) & (overflow ^ source ^ modify ^ result);
|
||||
cpsr().v = (1u << 31) & (overflow);
|
||||
source = result;
|
||||
return result;
|
||||
}
|
||||
|
||||
void ARM::thumb_sub(GPR &source, uint32 modify) {
|
||||
uint32 result = source - modify;
|
||||
uint32 ARM::thumb_sub(uint32 source, uint32 modify, bool carry) {
|
||||
uint32 result = source - modify + carry;
|
||||
uint32 overflow = ~(source ^ modify) & (source ^ result);
|
||||
cpsr().n = result >> 31;
|
||||
cpsr().z = result == 0;
|
||||
cpsr().c = (1u << 31) & (overflow ^ source ^ modify ^ result);
|
||||
cpsr().v = (1u << 31) & (overflow);
|
||||
source = result;
|
||||
return result;
|
||||
}
|
||||
|
||||
uint32 ARM::thumb_lsl(uint32 source, uint32 modify) {
|
||||
while(modify--) {
|
||||
cpsr().c = source >> 31;
|
||||
source <<= 1;
|
||||
}
|
||||
cpsr().n = source >> 31;
|
||||
cpsr().z = source == 0;
|
||||
return source;
|
||||
}
|
||||
|
||||
uint32 ARM::thumb_lsr(uint32 source, uint32 modify) {
|
||||
while(modify--) {
|
||||
cpsr().c = source & 1;
|
||||
source >>= 1;
|
||||
}
|
||||
cpsr().n = source >> 31;
|
||||
cpsr().z = source == 0;
|
||||
return source;
|
||||
}
|
||||
|
||||
uint32 ARM::thumb_asr(uint32 source, uint32 modify) {
|
||||
while(modify--) {
|
||||
cpsr().c = source & 1;
|
||||
source = (int32)source >> 1;
|
||||
}
|
||||
cpsr().n = source >> 31;
|
||||
cpsr().z = source == 0;
|
||||
return source;
|
||||
}
|
||||
|
||||
uint32 ARM::thumb_ror(uint32 source, uint32 modify) {
|
||||
while(modify--) {
|
||||
cpsr().c = source & 1;
|
||||
source = (source << 31) | (source >> 1);
|
||||
}
|
||||
cpsr().n = source >> 31;
|
||||
cpsr().z = source == 0;
|
||||
return source;
|
||||
}
|
||||
|
||||
uint32 ARM::thumb_mul(uint32 source, uint32 modify) {
|
||||
source = source * modify;
|
||||
cpsr().n = source >> 31;
|
||||
cpsr().z = source == 0;
|
||||
cpsr().c = 0;
|
||||
return source;
|
||||
}
|
||||
|
||||
//(add,sub) rd,rn,rm
|
||||
//0001 10om mmnn nddd
|
||||
//o = opcode
|
||||
//m = rm
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_adjust_register() {
|
||||
uint1 opcode = instruction() >> 9;
|
||||
uint3 m = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
switch(opcode) {
|
||||
case 0: r(d) = thumb_add(r(n), r(m)); break;
|
||||
case 1: r(d) = thumb_sub(r(n), r(m)); break;
|
||||
}
|
||||
}
|
||||
|
||||
//(add,sub) rd,rn,#immediate
|
||||
//0001 11oi iinn nddd
|
||||
//o = opcode
|
||||
//i = immediate
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_adjust_immediate() {
|
||||
uint1 opcode = instruction() >> 9;
|
||||
uint3 immediate = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
switch(opcode) {
|
||||
case 0: r(d) = thumb_add(r(n), immediate); break;
|
||||
case 1: r(d) = thumb_sub(r(n), immediate); break;
|
||||
}
|
||||
}
|
||||
|
||||
//(lsl,lsr,asr) rd,rm,#immediate
|
||||
//000o oiii iimm mddd
|
||||
//o = opcode
|
||||
//i = immediate
|
||||
//m = rm
|
||||
//d = rd
|
||||
void ARM::thumb_op_shift_immediate() {
|
||||
uint2 opcode = instruction() >> 11;
|
||||
uint5 immediate = instruction() >> 6;
|
||||
uint3 m = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
switch(opcode) {
|
||||
case 0: r(d) = thumb_lsl(r(m), immediate); break;
|
||||
case 1: r(d) = thumb_lsr(r(m), immediate); break;
|
||||
case 2: r(d) = thumb_asr(r(m), immediate); break;
|
||||
}
|
||||
}
|
||||
|
||||
//(mov,cmp,add,sub) (rd,rn),#immediate
|
||||
|
|
@ -72,9 +236,291 @@ void ARM::thumb_op_immediate() {
|
|||
uint8 immediate = instruction();
|
||||
|
||||
switch(opcode) {
|
||||
case 0: thumb_mov(r(d), immediate); break;
|
||||
case 1: thumb_cmp(r(d), immediate); break;
|
||||
case 2: thumb_add(r(d), immediate); break;
|
||||
case 3: thumb_sub(r(d), immediate); break;
|
||||
case 0: r(d) = thumb_tst( immediate); break;
|
||||
case 1: thumb_cmp(r(d), immediate); break;
|
||||
case 2: r(d) = thumb_add(r(d), immediate); break;
|
||||
case 3: r(d) = thumb_sub(r(d), immediate); break;
|
||||
}
|
||||
}
|
||||
|
||||
//{opcode} rd,rm
|
||||
//0100 00oo oomm mddd
|
||||
//o = opcode
|
||||
//m = rm
|
||||
//d = rd
|
||||
void ARM::thumb_op_alu() {
|
||||
uint4 opcode = instruction() >> 6;
|
||||
uint3 m = instruction() >> 3;
|
||||
uint3 d = instruction();
|
||||
|
||||
thumb_opcode(opcode, d, m);
|
||||
}
|
||||
|
||||
//bx rm
|
||||
//0100 0111 0mmm m---
|
||||
//m = rm
|
||||
void ARM::thumb_op_branch_exchange() {
|
||||
uint4 m = instruction() >> 3;
|
||||
|
||||
r(15) = r(m);
|
||||
cpsr().t = r(m) & 1;
|
||||
}
|
||||
|
||||
//{opcode} rd,rm
|
||||
//0100 01oo DMmm mddd
|
||||
//o = opcode
|
||||
//M:m = rm
|
||||
//D:d = rd
|
||||
void ARM::thumb_op_alu_hi() {
|
||||
uint2 opcode = instruction() >> 8;
|
||||
uint4 m = instruction() >> 3;
|
||||
uint3 dl = instruction();
|
||||
uint1 dh = instruction() >> 7;
|
||||
|
||||
uint4 d = (dh << 3) + (dl << 0);
|
||||
switch(opcode) {
|
||||
case 0: r(d) = thumb_add(r(d), r(m)); break; //ADD
|
||||
case 1: thumb_sub(r(d), r(m)); break; //SUB
|
||||
case 2: r(d) = thumb_tst( r(m)); break; //MOV
|
||||
}
|
||||
}
|
||||
|
||||
//ldr rd,[pc,#+/-offset]
|
||||
//0100 1ddd oooo oooo
|
||||
//d = rd
|
||||
//o = offset
|
||||
void ARM::thumb_op_load_literal() {
|
||||
uint3 d = instruction() >> 8;
|
||||
uint8 displacement = instruction();
|
||||
|
||||
unsigned rm = (r(15) & ~3) + displacement * 4;
|
||||
r(d) = bus.read(rm, Word);
|
||||
}
|
||||
|
||||
//(ld(r,s),str){b,h} rd,[rn,rm]
|
||||
//0101 ooom mmnn nddd
|
||||
//o = opcode
|
||||
//m = rm
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_move_register_offset() {
|
||||
uint3 opcode = instruction() >> 9;
|
||||
uint3 m = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
switch(opcode) {
|
||||
case 0: bus.write(r(n) + r(m), Word, r(d)); break; //STR
|
||||
case 1: bus.write(r(n) + r(m), Half, r(d)); break; //STRH
|
||||
case 2: bus.write(r(n) + r(m), Byte, r(d)); break; //STRB
|
||||
case 3: r(d) = (int8)bus.read(r(n) + r(m), Byte); break; //LDSB
|
||||
case 4: r(d) = bus.read(r(n) + r(m), Word); break; //LDR
|
||||
case 5: r(d) = bus.read(r(n) + r(m), Half); break; //LDRH
|
||||
case 6: r(d) = bus.read(r(n) + r(m), Byte); break; //LDRB
|
||||
case 7: r(d) = (int16)bus.read(r(n) + r(m), Half); break; //LDSH
|
||||
}
|
||||
}
|
||||
|
||||
//(ldr,str) rd,[rn,#offset]
|
||||
//0110 looo oonn nddd
|
||||
//l = load
|
||||
//o = offset
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_move_word_immediate() {
|
||||
uint1 load = instruction() >> 11;
|
||||
uint5 offset = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
if(load == 1) r(d) = bus.read(r(n) + offset * 4, Word);
|
||||
if(load == 0) bus.write(r(d) + offset * 4, Word, r(n));
|
||||
}
|
||||
|
||||
//(ldr,str)b rd,[rn,#offset]
|
||||
//0111 looo oonn nddd
|
||||
//l = load
|
||||
//o = offset
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_move_byte_immediate() {
|
||||
uint1 load = instruction() >> 11;
|
||||
uint5 offset = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint4 d = instruction() >> 0;
|
||||
|
||||
if(load == 1) r(d) = bus.read(r(n) + offset, Byte);
|
||||
if(load == 0) bus.write(r(d) + offset, Byte, r(n));
|
||||
}
|
||||
|
||||
//(ldr,str)h rd,[rn,#offset]
|
||||
//1000 looo oonn nddd
|
||||
//l = load
|
||||
//o = offset
|
||||
//n = rn
|
||||
//d = rd
|
||||
void ARM::thumb_op_move_half_immediate() {
|
||||
uint1 load = instruction() >> 11;
|
||||
uint5 offset = instruction() >> 6;
|
||||
uint3 n = instruction() >> 3;
|
||||
uint3 d = instruction() >> 0;
|
||||
|
||||
if(load == 1) r(d) = bus.read(r(n) + offset * 2, Half);
|
||||
if(load == 0) bus.write(r(d) + offset * 2, Half, r(n));
|
||||
}
|
||||
|
||||
//(ldr,str) rd,[sp,#relative]
|
||||
//1001 oddd rrrr rrrr
|
||||
//o = opcode
|
||||
//d = rd
|
||||
//r = relative
|
||||
void ARM::thumb_op_move_stack() {
|
||||
uint1 opcode = instruction() >> 11;
|
||||
uint3 d = instruction() >> 8;
|
||||
int8 relative = instruction();
|
||||
|
||||
if(opcode == 0) bus.write(r(13) + relative * 4, Word, r(d));
|
||||
if(opcode == 1) r(d) = bus.read(r(13) + relative * 4, Word);
|
||||
}
|
||||
|
||||
//add rd,{pc,sp},#immediate
|
||||
//1010 sddd iiii iiii
|
||||
//s = sp (0 = pc)
|
||||
//d = rd
|
||||
//i = immediate
|
||||
void ARM::thumb_op_add_register_hi() {
|
||||
uint1 sp = instruction() >> 11;
|
||||
uint3 d = instruction() >> 8;
|
||||
uint8 immediate = instruction();
|
||||
|
||||
if(sp == 0) r(d) = (r(15) & ~2) + immediate;
|
||||
if(sp == 1) r(d) = r(13) + immediate;
|
||||
}
|
||||
|
||||
//(add,sub) sp,#immediate
|
||||
//1011 0000 oiii iiii
|
||||
//o = opcode
|
||||
//i = immediate
|
||||
void ARM::thumb_op_adjust_stack() {
|
||||
uint1 opcode = instruction() >> 7;
|
||||
uint7 immediate = instruction();
|
||||
|
||||
if(opcode == 0) r(13) += immediate * 4;
|
||||
if(opcode == 1) r(13) -= immediate * 4;
|
||||
}
|
||||
|
||||
//push {r...{,lr}}
|
||||
//pop {r...{,pc}}
|
||||
//1011 o10r llll llll
|
||||
//o = opcode (0 = push, 1 = pop)
|
||||
//r = push lr -or- pop pc
|
||||
//l = register list
|
||||
void ARM::thumb_op_stack_multiple() {
|
||||
uint1 load = instruction() >> 11;
|
||||
uint1 branch = instruction() >> 8;
|
||||
uint8 list = instruction();
|
||||
|
||||
if(load == 1) {
|
||||
for(unsigned l = 0; l < 8; l++) {
|
||||
if(list & (1 << l)) {
|
||||
r(l) = bus.read(r(13), Word);
|
||||
r(13) += 4;
|
||||
}
|
||||
}
|
||||
if(branch) {
|
||||
r(15) = bus.read(r(13), Word);
|
||||
r(13) += 4;
|
||||
}
|
||||
}
|
||||
|
||||
if(load == 0) {
|
||||
for(unsigned l = 0; l < 8; l++) {
|
||||
if(list & (1 << l)) {
|
||||
r(13) -= 4;
|
||||
bus.write(r(13), Word, r(l));
|
||||
}
|
||||
}
|
||||
if(branch) {
|
||||
r(13) -= 4;
|
||||
bus.write(r(13), Word, r(14));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//(ldmia,stmdb) rn!,{r...}
|
||||
//1100 lnnn llll llll
|
||||
//l = load (0 = save)
|
||||
//n = rn
|
||||
//l = register list
|
||||
void ARM::thumb_op_move_multiple() {
|
||||
uint1 load = instruction() >> 11;
|
||||
uint3 n = instruction() >> 8;
|
||||
uint8 list = instruction();
|
||||
|
||||
if(load == 1) {
|
||||
for(unsigned l = 0; l < 8; l++) {
|
||||
if(list & (1 << l)) {
|
||||
r(l) = bus.read(r(n), Word);
|
||||
r(n) += 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(load == 0) {
|
||||
for(unsigned l = 0; l < 8; l++) {
|
||||
if(list & (1 << l)) {
|
||||
r(n) -= 4;
|
||||
bus.write(r(n), Word, r(l));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//swi #immediate
|
||||
//1101 1111 iiii iiii
|
||||
//i = immediate
|
||||
void ARM::thumb_op_software_interrupt() {
|
||||
uint8 immediate = instruction();
|
||||
|
||||
auto psr = cpsr();
|
||||
processor.setMode(Processor::Mode::SVC);
|
||||
r(14) = r(15) - 2;
|
||||
spsr() = psr;
|
||||
cpsr().t = 0;
|
||||
cpsr().i = 1;
|
||||
r(15) = 0x00000008;
|
||||
}
|
||||
|
||||
//b{condition}
|
||||
//1101 cccc dddd dddd
|
||||
//c = condition
|
||||
//d = displacement
|
||||
void ARM::thumb_op_branch_conditional() {
|
||||
uint4 condition = instruction() >> 8;
|
||||
int8 displacement = instruction();
|
||||
|
||||
if(thumb_condition(condition) == false) return;
|
||||
r(15) = r(15) + displacement * 2;
|
||||
}
|
||||
|
||||
//b address
|
||||
//1110 0ooo oooo oooo
|
||||
//o = offset
|
||||
void ARM::thumb_op_branch_short() {
|
||||
int11 displacement = instruction();
|
||||
|
||||
r(15) += displacement * 2;
|
||||
}
|
||||
|
||||
//bl address
|
||||
//1111 0ooo oooo oooo
|
||||
//1111 1ooo oooo oooo
|
||||
//o = offset
|
||||
void ARM::thumb_op_branch_long() {
|
||||
uint11 offsethi = instruction();
|
||||
uint11 offsetlo = pipeline.decode.instruction;
|
||||
|
||||
int22 displacement = (offsethi << 11) | (offsetlo << 0);
|
||||
r(14) = (r(15) - 2) | 1;
|
||||
r(15) += displacement * 2;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,36 @@
|
|||
void thumb_step();
|
||||
|
||||
void thumb_mov(GPR &source, uint32 modify);
|
||||
void thumb_cmp(GPR &source, uint32 modify);
|
||||
void thumb_add(GPR &source, uint32 modify);
|
||||
void thumb_sub(GPR &source, uint32 modify);
|
||||
bool thumb_condition(uint4 condition);
|
||||
void thumb_opcode(uint4 opcode, uint4 d, uint4 s);
|
||||
|
||||
uint32 thumb_tst(uint32 modify);
|
||||
void thumb_cmp(uint32 source, uint32 modify);
|
||||
uint32 thumb_add(uint32 source, uint32 modify, bool carry = 0);
|
||||
uint32 thumb_sub(uint32 source, uint32 modify, bool carry = 1);
|
||||
uint32 thumb_lsl(uint32 source, uint32 modify);
|
||||
uint32 thumb_lsr(uint32 source, uint32 modify);
|
||||
uint32 thumb_asr(uint32 source, uint32 modify);
|
||||
uint32 thumb_ror(uint32 source, uint32 modify);
|
||||
uint32 thumb_mul(uint32 source, uint32 modify);
|
||||
|
||||
void thumb_op_adjust_register();
|
||||
void thumb_op_adjust_immediate();
|
||||
void thumb_op_shift_immediate();
|
||||
void thumb_op_immediate();
|
||||
void thumb_op_alu();
|
||||
void thumb_op_branch_exchange();
|
||||
void thumb_op_alu_hi();
|
||||
void thumb_op_load_literal();
|
||||
void thumb_op_move_register_offset();
|
||||
void thumb_op_move_word_immediate();
|
||||
void thumb_op_move_byte_immediate();
|
||||
void thumb_op_move_half_immediate();
|
||||
void thumb_op_move_stack();
|
||||
void thumb_op_add_register_hi();
|
||||
void thumb_op_adjust_stack();
|
||||
void thumb_op_stack_multiple();
|
||||
void thumb_op_move_multiple();
|
||||
void thumb_op_software_interrupt();
|
||||
void thumb_op_branch_conditional();
|
||||
void thumb_op_branch_short();
|
||||
void thumb_op_branch_long();
|
||||
|
|
|
|||
Loading…
Reference in New Issue