mirror of https://github.com/bsnes-emu/bsnes.git
Update to v073r06 release.
byuu says: Above WIP will automatically map in the ST-001x chips, no need for an XML file. F1 Race of Champions II (J) is fully playable, at least. It's forced to 15MHz like the ST-0011 for now. The core (snes/chip/necdsp/core) is somewhat unstable at the moment, some debugging hooks commented out and some hacks / ideas floating around in there. Disassembler can't handle long jumps yet.
This commit is contained in:
Tim Allen
parent
a7ffc31282
commit
73113da41e
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@ -146,10 +146,8 @@ SNESCartridge::SNESCartridge(const uint8_t *data, unsigned size) {
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xml << " <map mode='linear' address='80-ff:8000-ffff'/>\n";
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xml << " </rom>\n";
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xml << " <icd2 revision='1'>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </icd2>\n";
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} else if(type == TypeSuperGameBoy2Bios) {
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xml << " <rom>\n";
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@ -157,10 +155,8 @@ SNESCartridge::SNESCartridge(const uint8_t *data, unsigned size) {
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xml << " <map mode='linear' address='80-ff:8000-ffff'/>\n";
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xml << " </rom>\n";
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xml << " <icd2 revision='2'>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </icd2>\n";
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} else if(has_spc7110) {
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xml << " <rom>\n";
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@ -379,10 +375,8 @@ SNESCartridge::SNESCartridge(const uint8_t *data, unsigned size) {
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if(has_srtc) {
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xml << " <srtc>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:2800-2801'/>\n";
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xml << " <map address='80-bf:2800-2801'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:2800-2801'/>\n";
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xml << " <map address='80-bf:2800-2801'/>\n";
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xml << " </srtc>\n";
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}
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@ -400,10 +394,8 @@ SNESCartridge::SNESCartridge(const uint8_t *data, unsigned size) {
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if(has_cx4) {
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xml << " <cx4>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </cx4>\n";
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}
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@ -481,36 +473,29 @@ SNESCartridge::SNESCartridge(const uint8_t *data, unsigned size) {
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if(has_obc1) {
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xml << " <obc1>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:6000-7fff'/>\n";
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xml << " <map address='80-bf:6000-7fff'/>\n";
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xml << " </obc1>\n";
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}
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if(has_st010) {
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xml << " <upd96050 program='st0010.bin' sha256='55c697e864562445621cdf8a7bf6e84ae91361e393d382a3704e9aa55559041e'>\n";
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xml << " <map address='68-6f:0000-0fff'/>\n";
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xml << " <map address='e8-ef:0000-0fff'/>\n";
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xml << " <upd96050 program='st0010.bin' frequency='10000000' sha256='55c697e864562445621cdf8a7bf6e84ae91361e393d382a3704e9aa55559041e'>\n";
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xml << " <map address='60-6f:0000-0fff'/>\n";
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xml << " <map address='e0-ef:0000-0fff'/>\n";
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xml << " </upd96050>\n";
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}
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if(has_st011) {
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//ST-0011 addresses not verified; chip is unsupported
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xml << " <setadsp program='ST-0011'>\n";
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xml << " <mmio>\n";
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xml << " <map address='68-6f:0000-0fff'/>\n";
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xml << " <map address='e8-ef:0000-0fff'/>\n";
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xml << " </mmio>\n";
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xml << " </setadsp>\n";
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xml << " <upd96050 program='st0011.bin' frequency='15000000' sha256='448e0deb0f580833ea878f4894a56124da18453d2d78e821388b6545909ba00a'>\n";
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xml << " <map address='60-6f:0000-0fff'/>\n";
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xml << " <map address='e0-ef:0000-0fff'/>\n";
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xml << " </upd96050>\n";
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}
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if(has_st018) {
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xml << " <setarisc program='ST-0018'>\n";
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xml << " <mmio>\n";
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xml << " <map address='00-3f:3800-38ff'/>\n";
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xml << " <map address='80-bf:3800-38ff'/>\n";
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xml << " </mmio>\n";
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xml << " <map address='00-3f:3800-38ff'/>\n";
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xml << " <map address='80-bf:3800-38ff'/>\n";
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xml << " </setarisc>\n";
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}
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@ -43,7 +43,7 @@ void Cartridge::load(Mode cartridge_mode, const lstring &xml_list) {
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has_serial = false;
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parse_xml(xml_list);
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//foreach(xml_item, xml_list) print(xml_item, "\n\n");
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//print(xml_list[0], "\n\n");
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if(ram_size > 0) {
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memory::cartram.map(allocate<uint8_t>(ram_size, 0xff), ram_size);
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@ -107,16 +107,12 @@ void Cartridge::xml_parse_icd2(xml_element &root) {
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}
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foreach(node, root.element) {
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if(node.name == "mmio") {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m((Memory&)icd2);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map") {
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Mapping m((Memory&)icd2);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -330,7 +326,7 @@ void Cartridge::xml_parse_upd96050(xml_element &root) {
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for(unsigned n = 0; n < 16384; n++) {
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upd96050.programROM[n] = fp.readm(3);
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}
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for(unsigned n = 0; n < 1024; n++) {
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for(unsigned n = 0; n < 2048; n++) {
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upd96050.dataROM[n] = fp.readm(2);
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}
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@ -455,16 +451,12 @@ void Cartridge::xml_parse_srtc(xml_element &root) {
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has_srtc = true;
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foreach(node, root.element) {
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if(node.name == "mmio") {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m(srtc);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map") {
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Mapping m(srtc);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -569,16 +561,12 @@ void Cartridge::xml_parse_cx4(xml_element &root) {
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has_cx4 = true;
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foreach(node, root.element) {
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if(node.name == "mmio") {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m(cx4);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map") {
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Mapping m(cx4);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -587,16 +575,12 @@ void Cartridge::xml_parse_obc1(xml_element &root) {
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has_obc1 = true;
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foreach(node, root.element) {
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if(node.name == "mmio") {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m(obc1);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map") {
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Mapping m(obc1);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -619,16 +603,12 @@ void Cartridge::xml_parse_setadsp(xml_element &root) {
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Memory *map[3] = { 0, &st0010, 0 };
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foreach(node, root.element) {
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if(node.name == "mmio" && map[program]) {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m(*map[program]);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map" && map[program]) {
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Mapping m(*map[program]);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -648,16 +628,12 @@ void Cartridge::xml_parse_setarisc(xml_element &root) {
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MMIO *map[2] = { 0, &st0018 };
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foreach(node, root.element) {
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if(node.name == "mmio" && map[program]) {
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foreach(leaf, node.element) {
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if(leaf.name == "map") {
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Mapping m(*map[program]);
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foreach(attr, leaf.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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if(node.name == "map" && map[program]) {
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Mapping m(*map[program]);
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foreach(attr, node.attribute) {
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if(attr.name == "address") xml_parse_address(m, attr.content);
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}
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mapping.append(m);
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}
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}
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}
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@ -13,6 +13,7 @@ void ICD2::Enter() { icd2.enter(); }
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void ICD2::enter() {
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while(true) {
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if(scheduler.sync == Scheduler::SynchronizeMode::All) {
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GameBoy::system.runtosave();
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scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
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}
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@ -2,8 +2,6 @@
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void ICD2::serialize(serializer &s) {
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Processor::serialize(s);
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GameBoy::system.runtosave();
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GameBoy::system.serialize_all(s);
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for(unsigned n = 0; n < 64; n++) s.array(packet[n].data);
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@ -7,6 +7,12 @@ namespace SNES {
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#include "serialization.cpp"
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void uPDcore::exec() {
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//static uint16 lastpc = 0xffff;
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//if(lastpc != regs.pc) {
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// print("A:", hex<4>((uint16)regs.a), " B:", hex<4>((uint16)regs.b), " DR:", hex<4>(regs.dr), " SR:", hex<4>(regs.sr), " FA:", hex<2>(regs.flaga), " FB:", hex<2>(regs.flagb), "\n");
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// print(disassemble(lastpc = regs.pc), "\n");
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//}
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uint24 opcode = programROM[regs.pc];
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regs.pc = regs.pc + 1;
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switch(opcode >> 22) {
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@ -43,8 +49,8 @@ void uPDcore::exec_op(uint24 opcode) {
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case 8: regs.idb = regs.dr; regs.sr.rqm = 1; break;
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case 9: regs.idb = regs.dr; break;
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case 10: regs.idb = regs.sr; break;
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//case 11: regs.idb = regs.sim; break;
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//case 12: regs.idb = regs.sil; break;
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case 11: regs.idb = regs.si; break; //MSB
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case 12: regs.idb = regs.si; break; //LSB
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case 13: regs.idb = regs.k; break;
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case 14: regs.idb = regs.l; break;
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case 15: regs.idb = dataRAM[regs.dp]; break;
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@ -152,54 +158,113 @@ void uPDcore::exec_rt(uint24 opcode) {
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void uPDcore::exec_jp(uint24 opcode) {
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uint9 brch = opcode >> 13; //branch
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uint11 na = opcode >> 2; //next address
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uint2 bank = opcode >> 0; //bank address
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bool r = false;
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uint16 jps = (regs.pc & 0x3800) | (na << 0);
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uint16 jpl = (regs.pc & 0x2000) | (bank << 11) | (na << 0);
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bool lj = false;
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ljmp:
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switch(brch) {
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case 0x080: r = (regs.flaga.c == 0); break; //JNCA
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case 0x082: r = (regs.flaga.c == 1); break; //JCA
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case 0x084: r = (regs.flagb.c == 0); break; //JNCB
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case 0x086: r = (regs.flagb.c == 1); break; //JCB
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case 0x088: r = (regs.flaga.z == 0); break; //JNZA
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case 0x08a: r = (regs.flaga.z == 1); break; //JZA
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case 0x08c: r = (regs.flagb.z == 0); break; //JNZB
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case 0x08e: r = (regs.flagb.z == 1); break; //JZB
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case 0x090: r = (regs.flaga.ov0 == 0); break; //JNOVA0
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case 0x092: r = (regs.flaga.ov0 == 1); break; //JOVA0
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case 0x094: r = (regs.flagb.ov0 == 0); break; //JNOVB0
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case 0x096: r = (regs.flagb.ov0 == 1); break; //JOVB0
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case 0x098: r = (regs.flaga.ov1 == 0); break; //JNOVA1
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case 0x09a: r = (regs.flaga.ov1 == 1); break; //JOVA1
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case 0x09c: r = (regs.flagb.ov1 == 0); break; //JNOVB1
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case 0x09e: r = (regs.flagb.ov1 == 1); break; //JOVB1
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case 0x0a0: r = (regs.flaga.s0 == 0); break; //JNSA0
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case 0x0a2: r = (regs.flaga.s0 == 1); break; //JSA0
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case 0x0a4: r = (regs.flagb.s0 == 0); break; //JNSB0
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case 0x0a6: r = (regs.flagb.s0 == 1); break; //JSB0
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case 0x0a8: r = (regs.flaga.s1 == 0); break; //JNSA1
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case 0x0aa: r = (regs.flaga.s1 == 1); break; //JSA1
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case 0x0ac: r = (regs.flagb.s1 == 0); break; //JNSB1
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case 0x0ae: r = (regs.flagb.s1 == 1); break; //JSB1
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case 0x080: if(regs.flaga.c == 0) regs.pc = jps; return; //JNCA
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case 0x082: if(regs.flaga.c == 1) regs.pc = jps; return; //JCA
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case 0x084: if(regs.flagb.c == 0) regs.pc = jps; return; //JNCB
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case 0x086: if(regs.flagb.c == 1) regs.pc = jps; return; //JCB
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case 0x0b0: r = (regs.dp & 0x0f) == 0x00; break; //JDPL0
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case 0x0b1: r = (regs.dp & 0x0f) != 0x00; break; //JDPLN0
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case 0x0b2: r = (regs.dp & 0x0f) == 0x0f; break; //JDPLF
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case 0x0b3: r = (regs.dp & 0x0f) != 0x0f; break; //JDPLNF
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case 0x088: if(regs.flaga.z == 0) regs.pc = jps; return; //JNZA
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case 0x08a: if(regs.flaga.z == 1) regs.pc = jps; return; //JZA
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case 0x08c: if(regs.flagb.z == 0) regs.pc = jps; return; //JNZB
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case 0x08e: if(regs.flagb.z == 1) regs.pc = jps; return; //JZB
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case 0x0b4: r = (regs.siack == 0); break; //JNSIAK
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case 0x0b6: r = (regs.siack == 1); break; //JSIAK
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case 0x090: if(regs.flaga.ov0 == 0) regs.pc = jps; return; //JNOVA0
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case 0x092: if(regs.flaga.ov0 == 1) regs.pc = jps; return; //JOVA0
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case 0x094: if(regs.flagb.ov0 == 0) regs.pc = jps; return; //JNOVB0
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case 0x096: if(regs.flagb.ov0 == 1) regs.pc = jps; return; //JOVB0
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case 0x0b8: r = (regs.soack == 0); break; //JNSOAK
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case 0x0ba: r = (regs.soack == 1); break; //JSOAK
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case 0x098: if(regs.flaga.ov1 == 0) regs.pc = jps; return; //JNOVA1
|
||||
case 0x09a: if(regs.flaga.ov1 == 1) regs.pc = jps; return; //JOVA1
|
||||
case 0x09c: if(regs.flagb.ov1 == 0) regs.pc = jps; return; //JNOVB1
|
||||
case 0x09e: if(regs.flagb.ov1 == 1) regs.pc = jps; return; //JOVB1
|
||||
|
||||
case 0x0bc: r = (regs.sr.rqm == 0); break; //JNRQM
|
||||
case 0x0be: r = (regs.sr.rqm == 1); break; //JRQM
|
||||
case 0x0a0: if(regs.flaga.s0 == 0) regs.pc = jps; return; //JNSA0
|
||||
case 0x0a2: if(regs.flaga.s0 == 1) regs.pc = jps; return; //JSA0
|
||||
case 0x0a4: if(regs.flagb.s0 == 0) regs.pc = jps; return; //JNSB0
|
||||
case 0x0a6: if(regs.flagb.s0 == 1) regs.pc = jps; return; //JSB0
|
||||
|
||||
case 0x100: r = true; break; //JMP
|
||||
case 0x140: r = true; stack_push(); break; //CALL
|
||||
case 0x0a8: if(regs.flaga.s1 == 0) regs.pc = jps; return; //JNSA1
|
||||
case 0x0aa: if(regs.flaga.s1 == 1) regs.pc = jps; return; //JSA1
|
||||
case 0x0ac: if(regs.flagb.s1 == 0) regs.pc = jps; return; //JNSB1
|
||||
case 0x0ae: if(regs.flagb.s1 == 1) regs.pc = jps; return; //JSB1
|
||||
|
||||
case 0x0b0: if((regs.dp & 0x0f) == 0x00) regs.pc = jps; return; //JDPL0
|
||||
case 0x0b1: if((regs.dp & 0x0f) != 0x00) regs.pc = jps; return; //JDPLN0
|
||||
case 0x0b2: if((regs.dp & 0x0f) == 0x0f) regs.pc = jps; return; //JDPLF
|
||||
case 0x0b3: if((regs.dp & 0x0f) != 0x0f) regs.pc = jps; return; //JDPLNF
|
||||
|
||||
case 0x0bc: if(regs.sr.rqm == 0) regs.pc = jps; return; //JNRQM
|
||||
case 0x0be: if(regs.sr.rqm == 1) regs.pc = jps; return; //JRQM
|
||||
|
||||
case 0x100: regs.pc = jps; return; //JMP
|
||||
case 0x140: stack_push(); regs.pc = jps; return; //CALL
|
||||
}
|
||||
|
||||
if(r) regs.pc = na;
|
||||
if(brch == 0x000) {
|
||||
regs.pc = regs.so;
|
||||
return;
|
||||
}
|
||||
|
||||
if(lj == false) {
|
||||
lj = true;
|
||||
brch &= ~1;
|
||||
jps = jpl;
|
||||
goto ljmp;
|
||||
}
|
||||
|
||||
/*switch(brch) {
|
||||
case 0x081: if(regs.flaga.c == 0) regs.pc = jpl; return; //LJNCA
|
||||
|
||||
case 0x0bf: if(regs.sr.rqm == 1) regs.pc = jpl; return; //LJRQM
|
||||
}*/
|
||||
|
||||
print(hex<4>(regs.pc - 1), ": unknown jump ", hex<3>(brch), "\n");
|
||||
|
||||
/*bool r = false;
|
||||
switch(brch) {
|
||||
case 0x080: r = (regs.flaga.c == 0); break; //JNCA
|
||||
case 0x082: r = (regs.flaga.c == 1); break; //JCA
|
||||
case 0x084: r = (regs.flagb.c == 0); break; //JNCB
|
||||
case 0x086: r = (regs.flagb.c == 1); break; //JCB
|
||||
case 0x088: r = (regs.flaga.z == 0); break; //JNZA
|
||||
case 0x08a: r = (regs.flaga.z == 1); break; //JZA
|
||||
case 0x08c: r = (regs.flagb.z == 0); break; //JNZB
|
||||
case 0x08e: r = (regs.flagb.z == 1); break; //JZB
|
||||
case 0x090: r = (regs.flaga.ov0 == 0); break; //JNOVA0
|
||||
case 0x092: r = (regs.flaga.ov0 == 1); break; //JOVA0
|
||||
case 0x094: r = (regs.flagb.ov0 == 0); break; //JNOVB0
|
||||
case 0x096: r = (regs.flagb.ov0 == 1); break; //JOVB0
|
||||
case 0x098: r = (regs.flaga.ov1 == 0); break; //JNOVA1
|
||||
case 0x09a: r = (regs.flaga.ov1 == 1); break; //JOVA1
|
||||
case 0x09c: r = (regs.flagb.ov1 == 0); break; //JNOVB1
|
||||
case 0x09e: r = (regs.flagb.ov1 == 1); break; //JOVB1
|
||||
case 0x0a0: r = (regs.flaga.s0 == 0); break; //JNSA0
|
||||
case 0x0a2: r = (regs.flaga.s0 == 1); break; //JSA0
|
||||
case 0x0a4: r = (regs.flagb.s0 == 0); break; //JNSB0
|
||||
case 0x0a6: r = (regs.flagb.s0 == 1); break; //JSB0
|
||||
case 0x0a8: r = (regs.flaga.s1 == 0); break; //JNSA1
|
||||
case 0x0aa: r = (regs.flaga.s1 == 1); break; //JSA1
|
||||
case 0x0ac: r = (regs.flagb.s1 == 0); break; //JNSB1
|
||||
case 0x0ae: r = (regs.flagb.s1 == 1); break; //JSB1
|
||||
case 0x0b0: r = (regs.dp & 0x0f) == 0x00; break; //JDPL0
|
||||
case 0x0b1: r = (regs.dp & 0x0f) != 0x00; break; //JDPLN0
|
||||
case 0x0b2: r = (regs.dp & 0x0f) == 0x0f; break; //JDPLF
|
||||
case 0x0b3: r = (regs.dp & 0x0f) != 0x0f; break; //JDPLNF
|
||||
case 0x0bc: r = (regs.sr.rqm == 0); break; //JNRQM
|
||||
case 0x0be: r = (regs.sr.rqm == 1); break; //JRQM
|
||||
case 0x100: r = true; break; //JMP
|
||||
case 0x140: r = true; stack_push(); break; //CALL
|
||||
}
|
||||
if(r) regs.pc = na;*/
|
||||
}
|
||||
|
||||
void uPDcore::exec_ld(uint24 opcode) {
|
||||
|
|
@ -217,8 +282,8 @@ void uPDcore::exec_ld(uint24 opcode) {
|
|||
case 5: regs.rp = id; break;
|
||||
case 6: regs.dr = id; regs.sr.rqm = 1; break;
|
||||
case 7: regs.sr = (regs.sr & 0x907c) | (id & ~0x907c); break;
|
||||
//case 8: regs.sol = id; break;
|
||||
//case 9: regs.som = id; break;
|
||||
case 8: regs.so = id; break; //LSB
|
||||
case 9: regs.so = id; break; //MSB
|
||||
case 10: regs.k = id; break;
|
||||
case 11: regs.k = id; regs.l = dataROM[regs.rp]; break;
|
||||
case 12: regs.l = id; regs.k = dataRAM[regs.dp | 0x40]; break;
|
||||
|
|
@ -229,26 +294,14 @@ void uPDcore::exec_ld(uint24 opcode) {
|
|||
}
|
||||
|
||||
void uPDcore::stack_push() {
|
||||
regs.stack[7] = regs.stack[6];
|
||||
regs.stack[6] = regs.stack[5];
|
||||
regs.stack[5] = regs.stack[4];
|
||||
regs.stack[4] = regs.stack[3];
|
||||
regs.stack[3] = regs.stack[2];
|
||||
regs.stack[2] = regs.stack[1];
|
||||
regs.stack[1] = regs.stack[0];
|
||||
for(unsigned r = 63; r >= 1; r--) regs.stack[r] = regs.stack[r - 1];
|
||||
regs.stack[0] = regs.pc;
|
||||
}
|
||||
|
||||
void uPDcore::stack_pull() {
|
||||
regs.pc = regs.stack[0];
|
||||
regs.stack[0] = regs.stack[1];
|
||||
regs.stack[1] = regs.stack[2];
|
||||
regs.stack[2] = regs.stack[3];
|
||||
regs.stack[3] = regs.stack[4];
|
||||
regs.stack[4] = regs.stack[5];
|
||||
regs.stack[5] = regs.stack[6];
|
||||
regs.stack[6] = regs.stack[7];
|
||||
regs.stack[7] = 0x0000;
|
||||
for(unsigned r = 0; r <= 62; r++) regs.stack[r] = regs.stack[r + 1];
|
||||
regs.stack[63] = 0x0000;
|
||||
}
|
||||
|
||||
uPDcore::uPDcore(unsigned pcbits, unsigned rpbits, unsigned dpbits) {
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ public:
|
|||
void stack_push();
|
||||
void stack_pull();
|
||||
|
||||
string disassemble(uint11 ip);
|
||||
string disassemble(uint14 ip);
|
||||
|
||||
void serialize(serializer&);
|
||||
uPDcore(unsigned pcbits, unsigned rpbits, unsigned dpbits);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifdef UPDCORE_CPP
|
||||
|
||||
string uPDcore::disassemble(uint11 ip) {
|
||||
string uPDcore::disassemble(uint14 ip) {
|
||||
string output = { hex<3>(ip), " " };
|
||||
uint24 opcode = programROM[ip];
|
||||
uint2 type = opcode >> 22;
|
||||
|
|
@ -48,7 +48,7 @@ string uPDcore::disassemble(uint11 ip) {
|
|||
case 1: output << "b"; break;
|
||||
}
|
||||
|
||||
if(dst) {
|
||||
if(1||dst) {
|
||||
output << "\n mov ";
|
||||
|
||||
switch(src) {
|
||||
|
|
|
|||
|
|
@ -41,26 +41,24 @@ struct Status {
|
|||
}
|
||||
};
|
||||
|
||||
//11,11,10,8 and 14,14,11,11
|
||||
|
||||
struct Regs {
|
||||
Pointer pc; //program counter
|
||||
Pointer rp; //ROM pointer
|
||||
Pointer dp; //data pointer
|
||||
uint16 stack[8]; //LIFO
|
||||
Pointer pc; //program counter
|
||||
Pointer rp; //ROM pointer
|
||||
Pointer dp; //data pointer
|
||||
uint16 stack[64]; //LIFO
|
||||
int16 k;
|
||||
int16 l;
|
||||
int16 m;
|
||||
int16 n;
|
||||
int16 a; //accumulator
|
||||
int16 b; //accumulator
|
||||
int16 a; //accumulator
|
||||
int16 b; //accumulator
|
||||
Flag flaga;
|
||||
Flag flagb;
|
||||
uint16 tr; //temporary register
|
||||
uint16 trb; //temporary register
|
||||
Status sr; //status register
|
||||
uint16 dr; //data register
|
||||
bool siack;
|
||||
bool soack;
|
||||
uint16 tr; //temporary register
|
||||
uint16 trb; //temporary register
|
||||
Status sr; //status register
|
||||
uint16 dr; //data register
|
||||
uint16 si;
|
||||
uint16 so;
|
||||
uint16 idb;
|
||||
} regs;
|
||||
|
|
|
|||
|
|
@ -51,8 +51,6 @@ void uPDcore::serialize(serializer &s) {
|
|||
s.integer(regs.sr.p0);
|
||||
|
||||
s.integer(regs.dr);
|
||||
s.integer(regs.siack);
|
||||
s.integer(regs.soack);
|
||||
s.integer(regs.idb);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -86,8 +86,6 @@ void uPD7725::reset() {
|
|||
regs.flagb = 0x00;
|
||||
regs.sr = 0x0000;
|
||||
regs.rp = 0x3ff;
|
||||
regs.siack = 0;
|
||||
regs.soack = 0;
|
||||
}
|
||||
|
||||
void uPD7725::serialize(serializer &s) {
|
||||
|
|
@ -97,7 +95,6 @@ void uPD7725::serialize(serializer &s) {
|
|||
|
||||
uPD7725::uPD7725() : uPDcore(11, 10, 8) {
|
||||
//NEC uPD7725:
|
||||
//8.192 MIPS (8.192MHz / 1)
|
||||
//11-bit ProgramROM (2048 x 24-bit) w/4-level stack
|
||||
//10-bit DataROM (1024 x 16-bit)
|
||||
// 8-bit DataRAM ( 256 x 16-bit)
|
||||
|
|
|
|||
|
|
@ -14,36 +14,87 @@ void uPD96050::enter() {
|
|||
}
|
||||
|
||||
uPDcore::exec();
|
||||
step(2);
|
||||
step(1);
|
||||
synchronize_cpu();
|
||||
}
|
||||
}
|
||||
|
||||
uint8 uPD96050::read(unsigned addr) {
|
||||
cpu.synchronize_coprocessor();
|
||||
regs.sr.rqm = 0;
|
||||
addr &= 0x8ffff;
|
||||
|
||||
bool hi = addr & 1;
|
||||
addr = (addr >> 1) & 2047;
|
||||
|
||||
if(hi == false) {
|
||||
return dataRAM[addr] >> 0;
|
||||
} else {
|
||||
return dataRAM[addr] >> 8;
|
||||
if(addr == 0x00000) {
|
||||
if(regs.sr.drc == 0) {
|
||||
//16-bit
|
||||
if(regs.sr.drs == 0) {
|
||||
regs.sr.drs = 1;
|
||||
return regs.dr >> 0;
|
||||
} else {
|
||||
regs.sr.rqm = 0;
|
||||
regs.sr.drs = 0;
|
||||
return regs.dr >> 8;
|
||||
}
|
||||
} else {
|
||||
//8-bit
|
||||
regs.sr.rqm = 0;
|
||||
return regs.dr >> 0;
|
||||
}
|
||||
}
|
||||
|
||||
if(addr == 0x00001) {
|
||||
return regs.sr >> 8;
|
||||
}
|
||||
|
||||
if(addr & 0x80000) {
|
||||
bool hi = addr & 1;
|
||||
addr = (addr >> 1) & 2047;
|
||||
|
||||
if(hi == false) {
|
||||
return dataRAM[addr] >> 0;
|
||||
} else {
|
||||
return dataRAM[addr] >> 8;
|
||||
}
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void uPD96050::write(unsigned addr, uint8 data) {
|
||||
cpu.synchronize_coprocessor();
|
||||
regs.sr.rqm = 0;
|
||||
addr &= 0x8ffff;
|
||||
|
||||
bool hi = addr & 1;
|
||||
addr = (addr >> 1) & 2047;
|
||||
if(addr == 0x00000) {
|
||||
//print("DR = ", hex<2>(data), " @ ", hex<6>(cpu.regs.pc), "\n");
|
||||
if(regs.sr.drc == 0) {
|
||||
//16-bit
|
||||
if(regs.sr.drs == 0) {
|
||||
regs.sr.drs = 1;
|
||||
regs.dr = (regs.dr & 0xff00) | (data << 0);
|
||||
} else {
|
||||
regs.sr.rqm = 0;
|
||||
regs.sr.drs = 0;
|
||||
regs.dr = (data << 8) | (regs.dr & 0x00ff);
|
||||
}
|
||||
} else {
|
||||
//8-bit
|
||||
regs.sr.rqm = 0;
|
||||
regs.dr = (regs.dr & 0xff00) | (data << 0);
|
||||
}
|
||||
}
|
||||
|
||||
if(hi == false) {
|
||||
dataRAM[addr] = (dataRAM[addr] & 0xff00) | (data << 0);
|
||||
} else {
|
||||
dataRAM[addr] = (dataRAM[addr] & 0x00ff) | (data << 8);
|
||||
if(addr == 0x00001) {
|
||||
return;
|
||||
}
|
||||
|
||||
if(addr & 0x80000) {
|
||||
bool hi = addr & 1;
|
||||
addr = (addr >> 1) & 2047;
|
||||
|
||||
if(hi == false) {
|
||||
dataRAM[addr] = (dataRAM[addr] & 0xff00) | (data << 0);
|
||||
} else {
|
||||
dataRAM[addr] = (dataRAM[addr] & 0x00ff) | (data << 8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -59,7 +110,7 @@ void uPD96050::power() {
|
|||
}
|
||||
|
||||
void uPD96050::reset() {
|
||||
create(uPD96050::Enter, 20 * 1000 * 1000); //20MHz
|
||||
create(uPD96050::Enter, 15 * 1000 * 1000);
|
||||
|
||||
regs.pc = 0x0000;
|
||||
regs.stack[0] = 0x0000;
|
||||
|
|
@ -74,8 +125,6 @@ void uPD96050::reset() {
|
|||
regs.flagb = 0x00;
|
||||
regs.sr = 0x0000;
|
||||
regs.rp = 0x03ff;
|
||||
regs.siack = 0;
|
||||
regs.soack = 0;
|
||||
}
|
||||
|
||||
void uPD96050::serialize(serializer &s) {
|
||||
|
|
@ -85,7 +134,6 @@ void uPD96050::serialize(serializer &s) {
|
|||
|
||||
uPD96050::uPD96050() : uPDcore(14, 11, 11) {
|
||||
//NEC uPD96050:
|
||||
//10MIPS (20MHz / 2)
|
||||
//14-bit ProgramROM (16384 x 24-bit) w/8-level stack
|
||||
//11-bit DataROM ( 2048 x 16-bit)
|
||||
//11-bit DataRAM ( 2048 x 16-bit) w/battery backup
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
namespace SNES {
|
||||
namespace Info {
|
||||
static const char Name[] = "bsnes";
|
||||
static const char Version[] = "073.05";
|
||||
static const char Version[] = "073.06";
|
||||
static const unsigned SerializerVersion = 16;
|
||||
}
|
||||
}
|
||||
|
||||
//#define DEBUGGER
|
||||
#define DEBUGGER
|
||||
#define CHEAT_SYSTEM
|
||||
|
||||
#include <libco/libco.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue