mirror of https://github.com/bsnes-emu/bsnes.git
Update to v104r08 release.
byuu says:
Changelog:
- processor/upd96050: code cleanups
- processor/upd96050: improved emulation of S1/OV1 flags [thanks to
Cydrak, Lord Nightmare]
- tomoko/settings/audio: reduced the size of the frequency/latency
combo boxes to show longer device driver names
Errata: I need to clear regs.sr in uPD96050::power()
Note: the S1/OV1 emulation is likely not 100% correct yet, but it's a
step in the right direction. No SNES games actually use S1/OV1, so this
shouldn't result in any issues, I'd just like to have this part of the
chip emulated correctly.
This commit is contained in:
Tim Allen
parent
d8a8f06c35
commit
25bda4f159
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@ -12,7 +12,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "104.07";
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static const string Version = "104.08";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -31,7 +31,7 @@ auto uPD96050::execOP(uint24 opcode) -> void {
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case 4: idb = regs.dp; break;
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case 5: idb = regs.rp; break;
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case 6: idb = dataROM[regs.rp]; break;
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case 7: idb = 0x8000 - regs.flaga.s1; break;
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case 7: idb = 0x8000 - flags.a.s1; break;
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case 8: idb = regs.dr; regs.sr.rqm = 1; break;
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case 9: idb = regs.dr; break;
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case 10: idb = regs.sr; break;
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@ -45,7 +45,7 @@ auto uPD96050::execOP(uint24 opcode) -> void {
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if(alu) {
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uint16 p, q, r;
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Flag flag;
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bool c;
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boolean c;
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switch(pselect) {
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case 0: p = dataRAM[regs.dp]; break;
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@ -55,8 +55,8 @@ auto uPD96050::execOP(uint24 opcode) -> void {
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}
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switch(asl) {
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case 0: q = regs.a; flag = regs.flaga; c = regs.flagb.c; break;
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case 1: q = regs.b; flag = regs.flagb; c = regs.flaga.c; break;
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case 0: q = regs.a; flag = flags.a; c = flags.b.c; break;
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case 1: q = regs.b; flag = flags.b; c = flags.a.c; break;
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}
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switch(alu) {
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@ -70,46 +70,68 @@ auto uPD96050::execOP(uint24 opcode) -> void {
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case 8: r = q - 1; p = 1; break; //DEC
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case 9: r = q + 1; p = 1; break; //INC
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case 10: r = ~q; break; //CMP
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case 11: r = (q >> 1) | (q & 0x8000); break; //SHR1 (ASR)
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case 12: r = (q << 1) | c; break; //SHL1 (ROL)
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case 13: r = (q << 2) | 3; break; //SHL2
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case 14: r = (q << 4) | 15; break; //SHL4
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case 15: r = (q << 8) | (q >> 8); break; //XCHG
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case 11: r = q >> 1 | q & 0x8000; break; //SHR1 (ASR)
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case 12: r = q << 1 | c; break; //SHL1 (ROL)
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case 13: r = q << 2 | 3; break; //SHL2
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case 14: r = q << 4 | 15; break; //SHL4
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case 15: r = q << 8 | q >> 8; break; //XCHG
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}
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flag.s0 = (r & 0x8000);
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flag.z = (r == 0);
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flag.s0 = r & 0x8000;
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flag.z = r == 0;
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switch(alu) {
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case 1: case 2: case 3: case 10: case 13: case 14: case 15: {
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case 1: //OR
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case 2: //AND
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case 3: //XOR
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case 10: //CMP
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case 13: //SHL2
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case 14: //SHL4
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case 15: { //XCHG
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flag.c = 0;
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flag.ov0 = 0;
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flag.ov1 = 0;
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break;
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}
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case 4: case 5: case 6: case 7: case 8: case 9: {
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case 4: //SUB
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case 5: //ADD
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case 6: //SBB
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case 7: //ADC
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case 8: //DEC
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case 9: { //INC
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if(!flag.ov1) {
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flag.s1 = flag.s0;
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}
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if(alu & 1) {
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//addition
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flag.ov0 = (q ^ r) & ~(q ^ p) & 0x8000;
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flag.c = (r < q);
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flag.c = r < q;
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} else {
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//subtraction
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flag.ov0 = (q ^ r) & (q ^ p) & 0x8000;
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flag.c = (r > q);
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}
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if(flag.ov0) {
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flag.s1 = flag.ov1 ^ !(r & 0x8000);
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flag.ov1 = !flag.ov1;
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flag.c = r > q;
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}
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//ovh[] = last three overflow flags (0 = most recent result)
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flag.ovh[2] = flag.ovh[1];
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flag.ovh[1] = flag.ovh[0];
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flag.ovh[0] = flag.ov0;
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flag.ov1 = (
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(flag.ovh[0] ^ flag.ovh[1] ^ flag.ovh[2])
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);
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break;
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}
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case 11: {
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case 11: { //SHR1 (ASR)
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flag.c = q & 1;
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flag.ov0 = 0;
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flag.ov1 = 0;
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break;
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}
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case 12: {
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case 12: { //SHL1 (ROL)
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flag.c = q >> 15;
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flag.ov0 = 0;
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flag.ov1 = 0;
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@ -118,16 +140,16 @@ auto uPD96050::execOP(uint24 opcode) -> void {
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}
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switch(asl) {
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case 0: regs.a = r; regs.flaga = flag; break;
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case 1: regs.b = r; regs.flagb = flag; break;
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case 0: regs.a = r; flags.a = flag; break;
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case 1: regs.b = r; flags.b = flag; break;
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}
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}
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execLD((idb << 6) + dst);
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switch(dpl) {
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case 1: regs.dp = (regs.dp & 0xf0) + ((regs.dp + 1) & 0x0f); break; //DPINC
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case 2: regs.dp = (regs.dp & 0xf0) + ((regs.dp - 1) & 0x0f); break; //DPDEC
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case 1: regs.dp = (regs.dp & 0xf0) + (regs.dp + 1 & 0x0f); break; //DPINC
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case 2: regs.dp = (regs.dp & 0xf0) + (regs.dp - 1 & 0x0f); break; //DPDEC
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case 3: regs.dp = (regs.dp & 0xf0); break; //DPCLR
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}
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@ -146,46 +168,52 @@ auto uPD96050::execJP(uint24 opcode) -> void {
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uint11 na = opcode >> 2; //next address
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uint2 bank = opcode >> 0; //bank address
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uint14 jp = (regs.pc & 0x2000) | (bank << 11) | (na << 0);
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uint14 jp = regs.pc & 0x2000 | bank << 11 | na << 0;
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switch(brch) {
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case 0x000: regs.pc = regs.so; return; //JMPSO
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case 0x080: if(regs.flaga.c == 0) regs.pc = jp; return; //JNCA
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case 0x082: if(regs.flaga.c == 1) regs.pc = jp; return; //JCA
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case 0x084: if(regs.flagb.c == 0) regs.pc = jp; return; //JNCB
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case 0x086: if(regs.flagb.c == 1) regs.pc = jp; return; //JCB
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case 0x080: if(flags.a.c == 0) regs.pc = jp; return; //JNCA
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case 0x082: if(flags.a.c == 1) regs.pc = jp; return; //JCA
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case 0x084: if(flags.b.c == 0) regs.pc = jp; return; //JNCB
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case 0x086: if(flags.b.c == 1) regs.pc = jp; return; //JCB
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case 0x088: if(regs.flaga.z == 0) regs.pc = jp; return; //JNZA
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case 0x08a: if(regs.flaga.z == 1) regs.pc = jp; return; //JZA
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case 0x08c: if(regs.flagb.z == 0) regs.pc = jp; return; //JNZB
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case 0x08e: if(regs.flagb.z == 1) regs.pc = jp; return; //JZB
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case 0x088: if(flags.a.z == 0) regs.pc = jp; return; //JNZA
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case 0x08a: if(flags.a.z == 1) regs.pc = jp; return; //JZA
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case 0x08c: if(flags.b.z == 0) regs.pc = jp; return; //JNZB
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case 0x08e: if(flags.b.z == 1) regs.pc = jp; return; //JZB
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case 0x090: if(regs.flaga.ov0 == 0) regs.pc = jp; return; //JNOVA0
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case 0x092: if(regs.flaga.ov0 == 1) regs.pc = jp; return; //JOVA0
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case 0x094: if(regs.flagb.ov0 == 0) regs.pc = jp; return; //JNOVB0
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case 0x096: if(regs.flagb.ov0 == 1) regs.pc = jp; return; //JOVB0
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case 0x090: if(flags.a.ov0 == 0) regs.pc = jp; return; //JNOVA0
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case 0x092: if(flags.a.ov0 == 1) regs.pc = jp; return; //JOVA0
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case 0x094: if(flags.b.ov0 == 0) regs.pc = jp; return; //JNOVB0
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case 0x096: if(flags.b.ov0 == 1) regs.pc = jp; return; //JOVB0
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case 0x098: if(regs.flaga.ov1 == 0) regs.pc = jp; return; //JNOVA1
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case 0x09a: if(regs.flaga.ov1 == 1) regs.pc = jp; return; //JOVA1
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case 0x09c: if(regs.flagb.ov1 == 0) regs.pc = jp; return; //JNOVB1
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case 0x09e: if(regs.flagb.ov1 == 1) regs.pc = jp; return; //JOVB1
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case 0x098: if(flags.a.ov1 == 0) regs.pc = jp; return; //JNOVA1
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case 0x09a: if(flags.a.ov1 == 1) regs.pc = jp; return; //JOVA1
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case 0x09c: if(flags.b.ov1 == 0) regs.pc = jp; return; //JNOVB1
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case 0x09e: if(flags.b.ov1 == 1) regs.pc = jp; return; //JOVB1
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case 0x0a0: if(regs.flaga.s0 == 0) regs.pc = jp; return; //JNSA0
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case 0x0a2: if(regs.flaga.s0 == 1) regs.pc = jp; return; //JSA0
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case 0x0a4: if(regs.flagb.s0 == 0) regs.pc = jp; return; //JNSB0
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case 0x0a6: if(regs.flagb.s0 == 1) regs.pc = jp; return; //JSB0
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case 0x0a0: if(flags.a.s0 == 0) regs.pc = jp; return; //JNSA0
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case 0x0a2: if(flags.a.s0 == 1) regs.pc = jp; return; //JSA0
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case 0x0a4: if(flags.b.s0 == 0) regs.pc = jp; return; //JNSB0
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case 0x0a6: if(flags.b.s0 == 1) regs.pc = jp; return; //JSB0
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case 0x0a8: if(regs.flaga.s1 == 0) regs.pc = jp; return; //JNSA1
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case 0x0aa: if(regs.flaga.s1 == 1) regs.pc = jp; return; //JSA1
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case 0x0ac: if(regs.flagb.s1 == 0) regs.pc = jp; return; //JNSB1
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case 0x0ae: if(regs.flagb.s1 == 1) regs.pc = jp; return; //JSB1
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case 0x0a8: if(flags.a.s1 == 0) regs.pc = jp; return; //JNSA1
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case 0x0aa: if(flags.a.s1 == 1) regs.pc = jp; return; //JSA1
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case 0x0ac: if(flags.b.s1 == 0) regs.pc = jp; return; //JNSB1
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case 0x0ae: if(flags.b.s1 == 1) regs.pc = jp; return; //JSB1
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case 0x0b0: if((regs.dp & 0x0f) == 0x00) regs.pc = jp; return; //JDPL0
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case 0x0b1: if((regs.dp & 0x0f) != 0x00) regs.pc = jp; return; //JDPLN0
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case 0x0b2: if((regs.dp & 0x0f) == 0x0f) regs.pc = jp; return; //JDPLF
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case 0x0b3: if((regs.dp & 0x0f) != 0x0f) regs.pc = jp; return; //JDPLNF
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//serial input/output acknowledge not emulated
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case 0x0b4: if(0) regs.pc = jp; return; //JNSIAK
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case 0x0b6: if(0) regs.pc = jp; return; //JSIAK
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case 0x0b8: if(0) regs.pc = jp; return; //JNSOAK
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case 0x0ba: if(0) regs.pc = jp; return; //JSOAK
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case 0x0bc: if(regs.sr.rqm == 0) regs.pc = jp; return; //JNRQM
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case 0x0be: if(regs.sr.rqm == 1) regs.pc = jp; return; //JRQM
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@ -209,7 +237,7 @@ auto uPD96050::execLD(uint24 opcode) -> void {
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case 4: regs.dp = id; break;
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case 5: regs.rp = id; break;
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case 6: regs.dr = id; regs.sr.rqm = 1; break;
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case 7: regs.sr = (regs.sr & 0x907c) | (id & ~0x907c); break;
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case 7: regs.sr = regs.sr & 0x907c | id & ~0x907c; break;
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case 8: regs.so = id; break; //LSB
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case 9: regs.so = id; break; //MSB
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case 10: regs.k = id; break;
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@ -1,27 +1,50 @@
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auto uPD96050::serialize(serializer& s) -> void {
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s.array(dataRAM);
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s.array(regs.stack);
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s.integer(regs.pc);
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s.integer(regs.rp);
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s.integer(regs.dp);
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s.integer(regs.sp);
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s.integer(regs.k);
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s.integer(regs.l);
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s.integer(regs.m);
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s.integer(regs.n);
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s.integer(regs.a);
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s.integer(regs.b);
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s.integer(regs.flaga.data);
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s.integer(regs.flagb.data);
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s.integer(regs.tr);
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s.integer(regs.trb);
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s.integer(regs.sr.data);
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s.integer(regs.dr);
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s.integer(regs.si);
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s.integer(regs.so);
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regs.serialize(s);
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flags.a.serialize(s);
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flags.b.serialize(s);
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}
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auto uPD96050::Flag::serialize(serializer& s) -> void {
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s.boolean(ov0);
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s.boolean(ov1);
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s.boolean(z);
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s.boolean(c);
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s.boolean(s0);
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s.boolean(s1);
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s.array(ovh);
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}
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auto uPD96050::Status::serialize(serializer& s) -> void {
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s.boolean(p0);
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s.boolean(p1);
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s.boolean(ei);
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s.boolean(sic);
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s.boolean(soc);
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s.boolean(drc);
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s.boolean(dma);
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s.boolean(drs);
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s.boolean(uf0);
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s.boolean(uf1);
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s.boolean(rqm);
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}
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auto uPD96050::Registers::serialize(serializer& s) -> void {
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s.array(stack);
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s.integer(pc);
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s.integer(rp);
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s.integer(dp);
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s.integer(sp);
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s.integer(si);
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s.integer(so);
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s.integer(k);
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s.integer(l);
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s.integer(m);
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s.integer(n);
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s.integer(a);
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s.integer(b);
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s.integer(tr);
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s.integer(trb);
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s.integer(dr);
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sr.serialize(s);
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}
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@ -32,14 +32,14 @@ auto uPD96050::power() -> void {
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regs.n = 0x0000;
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regs.a = 0x0000;
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regs.b = 0x0000;
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regs.flaga = 0x00;
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regs.flagb = 0x00;
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regs.tr = 0x0000;
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regs.trb = 0x0000;
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regs.sr = 0x0000;
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regs.dr = 0x0000;
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regs.si = 0x0000;
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regs.so = 0x0000;
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flags.a = 0x0000;
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flags.b = 0x0000;
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}
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}
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@ -1,4 +1,3 @@
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//NEC uPD7720 (not supported)
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//NEC uPD7725
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//NEC uPD96050
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@ -33,62 +32,95 @@ struct uPD96050 {
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uint16 dataRAM[2048];
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struct Flag {
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union {
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uint8_t data = 0;
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BooleanBitField<uint8_t, 5> s1;
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BooleanBitField<uint8_t, 4> s0;
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BooleanBitField<uint8_t, 3> c;
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BooleanBitField<uint8_t, 2> z;
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BooleanBitField<uint8_t, 1> ov1;
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BooleanBitField<uint8_t, 0> ov0;
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};
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inline operator uint() const {
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return ov0 << 0 | ov1 << 1 | z << 2 | c << 3 | s0 << 4 | s1 << 5;
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}
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inline operator uint() const { return data & 0x3f; }
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inline auto& operator=(uint value) { return data = value, *this; }
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inline auto& operator=(const Flag& value) { return data = value.data, *this; }
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inline auto operator=(uint16 data) -> Flag& {
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ov0 = data.bit(0);
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ov1 = data.bit(1);
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z = data.bit(2);
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c = data.bit(3);
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s0 = data.bit(4);
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s1 = data.bit(5);
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return *this;
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}
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||||
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
boolean ov0; //overflow 0
|
||||
boolean ov1; //overflow 1
|
||||
boolean z; //zero
|
||||
boolean c; //carry
|
||||
boolean s0; //sign 0
|
||||
boolean s1; //sign 1
|
||||
|
||||
boolean ovh[3]; //overflow history (internal)
|
||||
};
|
||||
|
||||
struct Status {
|
||||
union {
|
||||
uint16_t data = 0;
|
||||
BooleanBitField<uint16_t, 15> rqm;
|
||||
BooleanBitField<uint16_t, 14> usf1;
|
||||
BooleanBitField<uint16_t, 13> usf0;
|
||||
BooleanBitField<uint16_t, 12> drs;
|
||||
BooleanBitField<uint16_t, 11> dma;
|
||||
BooleanBitField<uint16_t, 10> drc;
|
||||
BooleanBitField<uint16_t, 9> soc;
|
||||
BooleanBitField<uint16_t, 8> sic;
|
||||
BooleanBitField<uint16_t, 7> ei;
|
||||
BooleanBitField<uint16_t, 1> p1;
|
||||
BooleanBitField<uint16_t, 0> p0;
|
||||
inline operator uint() const {
|
||||
bool _drs = drs & !drc; //when DRC=1, DRS=0
|
||||
return p0 << 0 | p1 << 1 | ei << 7 | sic << 8 | soc << 9 | drc << 10
|
||||
| dma << 11 | _drs << 12 | uf0 << 13 | uf1 << 14 | rqm << 15;
|
||||
}
|
||||
|
||||
inline auto operator=(uint16 data) -> Status& {
|
||||
p0 = data.bit( 0);
|
||||
p1 = data.bit( 1);
|
||||
ei = data.bit( 7);
|
||||
sic = data.bit( 8);
|
||||
soc = data.bit( 9);
|
||||
drc = data.bit(10);
|
||||
dma = data.bit(11);
|
||||
drs = data.bit(12);
|
||||
uf0 = data.bit(13);
|
||||
uf1 = data.bit(14);
|
||||
rqm = data.bit(15);
|
||||
return *this;
|
||||
}
|
||||
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
boolean p0; //output port 0
|
||||
boolean p1; //output port 1
|
||||
boolean ei; //enable interrupts
|
||||
boolean sic; //serial input control (0 = 16-bit; 1 = 8-bit)
|
||||
boolean soc; //serial output control (0 = 16-bit; 1 = 8-bit)
|
||||
boolean drc; //data register size (0 = 16-bit; 1 = 8-bit)
|
||||
boolean dma; //data register DMA mode
|
||||
boolean drs; //data register status (1 = active; 0 = stopped)
|
||||
boolean uf0; //user flag 0
|
||||
boolean uf1; //user flag 1
|
||||
boolean rqm; //request mode (=1 on internal access; =0 on external access)
|
||||
};
|
||||
|
||||
inline operator uint() const { return data & 0xff83; }
|
||||
inline auto& operator=(uint value) { return data = value, *this; }
|
||||
};
|
||||
struct Registers {
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
struct Regs {
|
||||
uint16 stack[16]; //LIFO
|
||||
VariadicNatural pc; //program counter
|
||||
VariadicNatural rp; //ROM pointer
|
||||
VariadicNatural dp; //data pointer
|
||||
uint4 sp; //stack pointer
|
||||
uint16 si; //serial input
|
||||
uint16 so; //serial output
|
||||
int16 k;
|
||||
int16 l;
|
||||
int16 m;
|
||||
int16 n;
|
||||
int16 a; //accumulator
|
||||
int16 b; //accumulator
|
||||
Flag flaga;
|
||||
Flag flagb;
|
||||
uint16 tr; //temporary register
|
||||
uint16 trb; //temporary register
|
||||
Status sr; //status register
|
||||
uint16 dr; //data register
|
||||
uint16 si;
|
||||
uint16 so;
|
||||
Status sr; //status register
|
||||
} regs;
|
||||
|
||||
struct Flags {
|
||||
Flag a;
|
||||
Flag b;
|
||||
} flags;
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ AudioSettings::AudioSettings(TabFrame* parent) : TabFrameItem(parent) {
|
|||
auto AudioSettings::updateDevice() -> void {
|
||||
frequencyList.reset();
|
||||
for(auto& frequency : audio->availableFrequencies()) {
|
||||
frequencyList.append(ComboButtonItem().setText(frequency));
|
||||
frequencyList.append(ComboButtonItem().setText((uint)frequency));
|
||||
if(frequency == settings["Audio/Frequency"].real()) {
|
||||
frequencyList.item(frequencyList.itemCount() - 1).setSelected();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,9 +48,9 @@ struct AudioSettings : TabFrameItem {
|
|||
Label deviceLabel{&controlLayout, Size{0, 0}};
|
||||
ComboButton deviceList{&controlLayout, Size{~0, 0}};
|
||||
Label frequencyLabel{&controlLayout, Size{0, 0}};
|
||||
ComboButton frequencyList{&controlLayout, Size{~0, 0}};
|
||||
ComboButton frequencyList{&controlLayout, Size{80, 0}};
|
||||
Label latencyLabel{&controlLayout, Size{0, 0}};
|
||||
ComboButton latencyList{&controlLayout, Size{~0, 0}};
|
||||
ComboButton latencyList{&controlLayout, Size{80, 0}};
|
||||
CheckLabel exclusiveMode{&layout, Size{~0, 0}};
|
||||
Label effectsLabel{&layout, Size{~0, 0}, 2};
|
||||
HorizontalLayout volumeLayout{&layout, Size{~0, 0}};
|
||||
|
|
|
|||
Loading…
Reference in New Issue