Fix silly regression

This commit is contained in:
Lior Halphon 2020-05-06 01:10:46 +03:00
parent 730567dc60
commit 184743637e
1 changed files with 1 additions and 2 deletions

View File

@ -858,8 +858,7 @@ ENDC
call ClearVRAMViaHDMA call ClearVRAMViaHDMA
call _ClearVRAMViaHDMA call _ClearVRAMViaHDMA
call ClearVRAMViaHDMA ; A = $40, so it's bank 0 call ClearVRAMViaHDMA ; A = $40, so it's bank 0
cpl ld a, $ff
; A should be $FF
ldh [$00], a ldh [$00], a
; Final values for CGB mode ; Final values for CGB mode