mirror of https://github.com/bsnes-emu/bsnes.git
Update to v086r10 release.
byuu says: More ARM work. ARM core now begins to act upon initial 0xf1 command, but hangs.
This commit is contained in:
Tim Allen
parent
3ed42af8a1
commit
11d6f09359
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@ -1,7 +1,7 @@
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#ifndef BASE_HPP
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#define BASE_HPP
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const char Version[] = "086.09";
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const char Version[] = "086.10";
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#include <nall/platform.hpp>
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#include <nall/algorithm.hpp>
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@ -3,6 +3,8 @@
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#define ARMDSP_CPP
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namespace SNES {
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static bool trace = 0;
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#include "opcodes.cpp"
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#include "memory.cpp"
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#include "disassembler.cpp"
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@ -42,12 +44,17 @@ void ArmDSP::enter() {
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pipeline.prefetch.opcode = bus_read<4>(r[15]);
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r[15].step();
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//print("\n", disassemble_registers(), "\n");
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//print(disassemble_opcode(pipeline.instruction.address), "\n");
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//if(pipeline.instruction.address == 0x00000208) trace = 1;
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if(trace) {
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print("\n", disassemble_registers(), "\n");
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print(disassemble_opcode(pipeline.instruction.address), "\n");
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usleep(200000);
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}
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instruction = pipeline.instruction.opcode;
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if((instruction & 0x0fb000f0) == 0x01200000) { op_move_status_register_to_register(); continue; }
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if((instruction & 0x0e000010) == 0x00000000) { op_data_immediate_shift(); continue; }
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if((instruction & 0x0e000090) == 0x00000010) { op_data_register_shift(); continue; }
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if((instruction & 0x0e000000) == 0x02000000) { op_data_immediate(); continue; }
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if((instruction & 0x0e000000) == 0x04000000) { op_move_immediate_offset(); continue; }
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if((instruction & 0x0e000000) == 0x08000000) { op_move_multiple(); continue; }
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@ -58,21 +65,27 @@ void ArmDSP::enter() {
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}
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uint8 ArmDSP::mmio_read(unsigned addr) {
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addr &= 0xffff;
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if(addr == 0x3800) return armport[0];
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if(addr == 0x3802) return armport[1];
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if(addr == 0x3804) return armport[3];
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uint8 data = 0x00;
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switch(addr & 0xffff) {
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case 0x3800: data = w40000000; break;
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case 0x3802: data = r3802; break;
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case 0x3804: data = r3804; break;
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}
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print("* r", hex<4>(addr), "\n");
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return 0x00;
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print("* r", hex<6>(addr), " = ", hex<2>(data), "\n");
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usleep(200000);
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return data;
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}
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void ArmDSP::mmio_write(unsigned addr, uint8 data) {
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addr &= 0xffff;
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if(addr == 0x3802) cpuport[1] = data;
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if(addr == 0x3804) cpuport[0] = data;
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print("* w", hex<6>(addr), " = ", hex<2>(data), "\n");
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usleep(200000);
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print("* w", hex<4>(addr), "w = ", hex<2>(data), "\n");
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switch(addr & 0xffff) {
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case 0x3800: w3800 = data; break;
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case 0x3802: w3802 = data; trace = 0; cputoarm = true; break;
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case 0x3804: w3804 = data; break;
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}
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}
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void ArmDSP::init() {
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@ -96,6 +109,13 @@ void ArmDSP::reset() {
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pipeline.reload = true;
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r[15].write = [&] { pipeline.reload = true; };
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r3800=r3802=r3804=0;
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w3800=w3802=w3804=0;
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r40000000=r40000010=r40000020=r40000024=r40000028=r4000002c=0;
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w40000000=w40000010=w40000020=w40000024=w40000028=w4000002c=0;
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cputoarm=0;
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armtocpu=0;
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}
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}
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@ -6,8 +6,17 @@ struct ArmDSP : public Coprocessor {
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#include "registers.hpp"
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uint8 cpuport[4];
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uint8 armport[4];
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//CPU
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uint8 r3800, r3802, r3804;
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uint8 w3800, w3802, w3804;
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//ARM
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uint32 r40000000, r40000010, r40000020, r40000024, r40000028, r4000002c;
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uint32 w40000000, w40000010, w40000020, w40000024, w40000028, w4000002c;
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//Status
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bool cputoarm;
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bool armtocpu;
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static void Enter();
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void enter();
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@ -24,11 +33,11 @@ struct ArmDSP : public Coprocessor {
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//opcodes.cpp
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bool condition();
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void opcode(uint32 data);
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void flags(uint32 rd);
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void op_branch();
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void op_data_immediate();
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void op_data_immediate_shift();
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void op_data_register_shift();
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void op_move_immediate_offset();
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void op_move_status_register_to_register();
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void op_move_multiple();
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@ -6,6 +6,10 @@ string ArmDSP::disassemble_opcode(uint32 pc) {
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static string registers[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" };
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static string indices[] = { "da", "ia", "db", "ib" };
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static auto is_move = [](uint4 opcode) { return opcode == 13 || opcode == 15; };
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static auto is_comp = [](uint4 opcode) { return opcode >= 8 && opcode <= 11; };
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static auto is_math = [](uint4 opcode) { return opcode < 8 || opcode == 12 || opcode == 14; };
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string output{hex<8>(pc), " "};
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uint32 instruction = bus_read<4>(pc);
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@ -31,45 +35,65 @@ string ArmDSP::disassemble_opcode(uint32 pc) {
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}
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//data immediate shift
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//{opcode}{condition}{s} rd,rm {shift} #immediate
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//{opcode}{condition} rn,rm {shift} #immediate
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//{opcode}{condition}{s} rd,rn,rm {shift} #immediate
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if((instruction & 0x0e000000) == 0x00000000) {
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uint4 condition = instruction >> 28;
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uint4 opcode = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rd = instruction >> 16;
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uint4 rn = instruction >> 12;
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uint8 rm = instruction;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint5 shift = instruction >> 7;
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uint2 op = instruction >> 2;
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uint2 op = instruction >> 5;
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uint4 rm = instruction;
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output.append(opcodes[opcode], conditions[condition], save ? "s " : " ");
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output.append(registers[rd], ",");
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output.append(registers[rn], ",");
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output.append(registers[rm], " ");
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if(op == 0) output.append("lsl #", shift);
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if(op == 1) output.append("lsr #", 1 + shift);
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if(op == 2) output.append("asr #", 1 + shift);
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if(op == 3 && shift != 0) output.append("ror #", shift);
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if(op == 3 && shift == 0) output.append("rrx");
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output.append(opcodes[opcode], conditions[condition]);
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if(is_move(opcode)) output.append(save ? "s " : " ", registers[rd]);
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if(is_comp(opcode)) output.append(" ", registers[rn]);
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if(is_math(opcode)) output.append(save ? "s " : " ", registers[rd], ",", registers[rn]);
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output.append(",", registers[rm]);
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if(op == 0 && shift != 0) output.append(" lsl #", shift);
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if(op == 1) output.append(" lsr #", shift == 0 ? 32u : (unsigned)shift);
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if(op == 2) output.append(" asr #", shift == 0 ? 32u : (unsigned)shift);
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if(op == 3 && shift != 0) output.append(" ror #", shift);
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if(op == 3 && shift == 0) output.append(" rrx");
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return output;
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}
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//data immediate
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//{opcode}{condition}{s} rd,#immediate
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//{opcode}{condition} rn,#immediate
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//{opcode}{condition}{s} rd,rn,#immediate
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if((instruction & 0x0e000000) == 0x02000000) {
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uint5 rotate = 2 * (uint4)(instruction >> 8);
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uint32 immediate = (uint8)instruction;
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immediate = (immediate >> rotate) | (immediate << (32 - rotate));
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output.append(opcodes[opcode], " ", registers[rd], ",#0x", hex<8>(immediate));
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uint4 condition = instruction >> 28;
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uint4 opcode = instruction >> 21;
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uint1 save = instruction >> 20;
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uint4 rn = instruction >> 16;
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uint4 rd = instruction >> 12;
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uint4 rotate = instruction >> 8;
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uint8 immediate = instruction;
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uint32 shifter = (immediate >> (rotate << 1)) | (immediate << (32 - (rotate << 1)));
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output.append(opcodes[opcode], conditions[condition]);
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if(is_move(opcode)) output.append(save ? "s " : " ", registers[rd]);
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if(is_comp(opcode)) output.append(" ", registers[rn]);
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if(is_math(opcode)) output.append(save ? "s " : " ", registers[rd], ",", registers[rn]);
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output.append(",#0x", hex<8>(shifter));
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return output;
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}
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//move immediate offset
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//(ldr,str){condition}{b} rd,[rn{+offset}]
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//todo: support W flag
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if((instruction & 0x0e000000) == 0x04000000) {
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uint1 u = instruction >> 23;
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uint1 load = instruction >> 20;
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uint12 immediate = instruction;
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output.append(load ? "ldr" : "str", conditions[condition]);
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if(instruction & 0x00400000) output.append("b");
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output.append(" ", registers[rd], ",[", registers[rn]);
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if(immediate) output.append(u ? "+" : "-", "0x", hex<3>((uint12)instruction));
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output.append("]");
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@ -77,6 +101,7 @@ string ArmDSP::disassemble_opcode(uint32 pc) {
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}
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//move multiple
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//(ldm,stm){condition}{mode} rn{!},{r...}
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if((instruction & 0x0e000000) == 0x08000000) {
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output.append(instruction & 0x00100000 ? "ldm" : "stm", conditions[condition], indices[(uint2)(instruction >> 23)]);
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output.append(" ", registers[rn], instruction & 0x00200000 ? "!" : "", ",{");
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@ -87,6 +112,7 @@ string ArmDSP::disassemble_opcode(uint32 pc) {
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}
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//branch
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//b{l}{condition} address
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if((instruction & 0x0e000000) == 0x0a000000) {
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uint1 l = instruction >> 24;
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output.append("b", l ? "l" : "", conditions[condition]);
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@ -5,52 +5,70 @@ uint8 ArmDSP::bus_iread(uint32 addr) {
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return programROM[addr & 0x0001ffff];
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}
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if(addr >= 0x40000020 && addr <= 0x4000002f) {
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if(addr == 0x40000020) return cpuport[0];
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if(addr == 0x40000024) return cpuport[1];
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if(addr == 0x40000028) return cpuport[2];
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if(addr == 0x4000002c) return cpuport[3];
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(addr == 0x40000000) { return r40000000; }
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if(addr == 0x40000010) { return w3802; }
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if(addr == 0x40000020) { return (cputoarm << 3); }
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if(addr == 0x40000024) { return r40000024; }
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if(addr == 0x40000028) { return r40000028; }
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if(addr == 0x4000002c) { return r4000002c; }
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}
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if(addr >= 0xe0000000 && addr <= 0xe0003fff) {
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return programRAM[addr & 0x00003fff];
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}
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//print("* ARM r", hex<8>(addr), "\n");
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return 0x00;
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}
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void ArmDSP::bus_iwrite(uint32 addr, uint8 data) {
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if(addr >= 0x40000020 && addr <= 0x4000002f) {
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if(addr == 0x40000020) armport[0] = data;
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if(addr == 0x40000024) armport[1] = data;
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if(addr == 0x40000028) armport[2] = data;
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if(addr == 0x4000002c) armport[3] = data;
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if(data) print("* ARM w", hex<8>(addr), " = ", hex<2>(data), "\n");
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(addr == 0x40000000) { w40000000 = data; }
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if(addr == 0x40000020) { w40000020 = data; }
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if(addr == 0x40000024) { w40000024 = data; }
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if(addr == 0x40000028) { w40000028 = data; }
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if(addr == 0x4000002c) { w4000002c = data; if(data & 2) r3804 = 0x80; }
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}
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if(addr >= 0xe0000000 && addr <= 0xe0003fff) {
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programRAM[addr & 0x00003fff] = data;
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return;
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}
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//print("* ARM w", hex<8>(addr), " = ", hex<2>(data), "\n");
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}
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template<unsigned size>
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uint32 ArmDSP::bus_read(uint32 addr) {
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uint32 result = 0;
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result |= bus_iread(addr + 0) << 0;
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result |= bus_iread(addr + 1) << 8;
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result |= bus_iread(addr + 2) << 16;
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result |= bus_iread(addr + 3) << 24;
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if(size == 1) return result & 0xff;
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if(size == 2) return result & 0xffff;
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return result;
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uint32 data = 0;
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data |= bus_iread(addr + 0) << 0;
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data |= bus_iread(addr + 1) << 8;
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data |= bus_iread(addr + 2) << 16;
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data |= bus_iread(addr + 3) << 24;
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(data) {
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if(size == 1) print("* ARM r", hex<8>(addr), " = ", hex<2>(data), "\n");
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if(size == 2) print("* ARM r", hex<8>(addr), " = ", hex<4>(data), "\n");
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if(size == 4) print("* ARM r", hex<8>(addr), " = ", hex<8>(data), "\n");
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usleep(20000);
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}
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}
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if(size == 1) return data & 0xff;
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if(size == 2) return data & 0xffff;
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return data;
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}
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template<unsigned size>
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void ArmDSP::bus_write(uint32 addr, uint32 data) {
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(0||data) {
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if(size == 1) print("* ARM w", hex<8>(addr), " = ", hex<2>(data), "\n");
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if(size == 2) print("* ARM w", hex<8>(addr), " = ", hex<4>(data), "\n");
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if(size == 4) print("* ARM w", hex<8>(addr), " = ", hex<8>(data), "\n");
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usleep(20000);
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}
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}
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if(size == 1) data = (bus_read<1>(addr) & 0xffffff00) | (data & 0x000000ff);
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if(size == 2) data = (bus_read<2>(addr) & 0xffff0000) | (data & 0x0000ffff);
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bus_iwrite(addr + 0, data >> 0);
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@ -1,7 +1,7 @@
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#ifdef ARMDSP_CPP
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bool ArmDSP::condition() {
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switch((uint4)(instruction >> 28)) { default:
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switch((uint4)(instruction >> 28)) {
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case 0: return cpsr.z == 1; //EQ (equal)
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case 1: return cpsr.z == 0; //NE (not equal)
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case 2: return cpsr.c == 1; //CS (carry set)
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@ -53,15 +53,15 @@ void ArmDSP::opcode(uint32 rm) {
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switch(opcode) {
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case 0: rd = rn & rm; nz(rd); break; //AND (logical and)
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case 1: rd = rn ^ rm; nz(rd); break; //EOR (logical exclusive or)
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case 2: rd = rn +~rm; nzcv(rd); break; //SUB (subtract)
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case 3: rd = rm +~rn; nzcv(rd); break; //RSB (reverse subtract)
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case 2: rd = rn +~rm + 1; nzcv(rd); break; //SUB (subtract)
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case 3: rd = rm +~rn + 1; nzcv(rd); break; //RSB (reverse subtract)
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case 4: rd = rn + rm; nzcv(rd); break; //ADD (add)
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case 5: rd = rn + rm + cpsr.c; nzcv(rd); break; //ADC (add with carry)
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case 6: rd = rn +~rm + cpsr.c; nzcv(rd); break; //SBC (subtract with carry)
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case 7: rd = rm +~rn + cpsr.c; nzcv(rd); break; //RSC (reverse subtract with carry)
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case 8: ro = rn & rm; nz(ro); break; //TST (test)
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case 9: ro = rn ^ rm; nz(ro); break; //TEQ (test equivalence)
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case 10: ro = rn +~rm; nzcv(ro); break; //CMP (compare)
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case 10: ro = rn +~rm + 1; nzcv(ro); break; //CMP (compare)
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case 11: ro = rn + rm; nzcv(ro); break; //CMN (compare negated)
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case 12: rd = rn | rm; nz(rd); break; //ORR (logical inclusive or)
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case 13: rd = rm; nz(rd); break; //MOV (move)
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@ -70,11 +70,6 @@ void ArmDSP::opcode(uint32 rm) {
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}
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}
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void ArmDSP::flags(uint32 rd) {
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cpsr.n = rd & 0x80000000;
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cpsr.z = rd == 0;
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}
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//CCCC 101L DDDD DDDD DDDD DDDD DDDD DDDD
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//C = condition
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//L = link
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@ -89,6 +84,9 @@ void ArmDSP::op_branch() {
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r[15] += displacement * 4;
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}
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//{opcode}{condition}{s} rd,#immediate
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//{opcode}{condition} rn,#immediate
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//{opcode}{condition}{s} rd,rn,#immediate
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//CCCC 001O OOOS NNNN DDDD RRRR IIII IIII
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//C = condition
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//O = opcode
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@ -100,16 +98,18 @@ void ArmDSP::op_branch() {
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void ArmDSP::op_data_immediate() {
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if(!condition()) return;
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uint4 rotate = instruction >> 8;
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uint8 immediate = instruction >> 0;
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uint4 shift = instruction >> 8;
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uint8 immediate = instruction;
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opcode(
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(immediate >> (rotate << 1)) | (immediate << (32 - (rotate << 1)))
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);
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uint32 rs = shift << 1;
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uint32 rm = (immediate >> rs) | (immediate << (32 - rs));
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//todo: set carry for non-add/sub opcodes here
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opcode(rm);
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}
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//{opcode}{condition}{s} rd,rm {shift} #immediate
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//{opcode}{condition} rn,rm {shift} #immediate
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//{opcode}{condition}{s} rd,rn,rm {shift} #immediate
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//CCCC 000O OOOS NNNN DDDD LLLL LSS0 MMMM
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//C = condition
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//O = opcode
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@ -123,34 +123,66 @@ void ArmDSP::op_data_immediate_shift() {
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if(!condition()) return;
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uint5 shift = instruction >> 7;
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uint2 op = instruction >> 5;
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uint32 rm = r[(uint4)instruction];
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uint2 mode = instruction >> 5;
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uint4 m = instruction;
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if(op == 0) { //LSL (logical shift left)
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rm = rm << shift;
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}
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uint32 rs = shift;
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uint32 rm = r[m];
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if(op == 1) { //LSR (logical shift right)
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rm = rm >> (1 + shift);
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}
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switch(mode) {
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case 0: //LSL
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rm = rm << rs;
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break;
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if(op == 2) { //ASR (arithmetic shift right)
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rm = (int32)rm >> (1 + shift);
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}
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case 1: //LSR
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if(rs == 0) rs = 32;
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rm = rm >> rs;
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break;
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if(op == 3) { //ROR (rotate right)
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if(shift == 0) { //RRX (rorate right with extend)
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rm = (cpsr.c << 31) | (rm >> 1);
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} else {
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rm = (rm >> shift) + (rm << (32 - shift));
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}
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case 2: //ASR
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if(rs == 0) rs = 32;
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rm = (int32)rm >> rs;
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break;
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case 3: //ROR + RRX
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if(rs == 0) rm = (cpsr.c << 31) | (rm >> 1); //RRX
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if(rs != 0) rm = (rm >> rs) + (rm << (32 - rs)); //ROR
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break;
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||||
}
|
||||
|
||||
opcode(rm);
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||||
|
||||
//todo: set carry
|
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}
|
||||
|
||||
//cccc 000o ooos nnnn dddd ssss 0ss1 mmmm
|
||||
//c = condition
|
||||
//o = opcode
|
||||
//s = save flags
|
||||
//n = rn
|
||||
//d = rd
|
||||
//s = rs
|
||||
//s = shift
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||||
//m = rm
|
||||
void ArmDSP::op_data_register_shift() {
|
||||
if(!condition()) return;
|
||||
|
||||
uint4 s = instruction >> 8;
|
||||
uint2 mode = instruction >> 5;
|
||||
uint4 m = instruction >> 0;
|
||||
|
||||
uint32 rs = r[s];
|
||||
uint32 rm = r[m];
|
||||
|
||||
switch(mode) {
|
||||
case 0: rm = rm << rs; break; //LSL
|
||||
case 1: rm = rm >> rs; break; //LSR
|
||||
case 2: rm = (int32)rm >> rs; break; //ASR
|
||||
case 3: rm = (rm >> rs) + (rm << (32 - rs)); break; //ROR
|
||||
}
|
||||
|
||||
opcode(rm);
|
||||
}
|
||||
|
||||
//(ldr,str){condition}{b} rd,[rn{+offset}]
|
||||
//CCCC 010P UBWL NNNN DDDD IIII IIII IIII
|
||||
//C = condition
|
||||
//P = pre (0 = post-indexed addressing)
|
||||
|
|
@ -256,6 +288,8 @@ void ArmDSP::op_move_multiple() {
|
|||
if(u == 1) r[n] = r[n] + bit::count(list) * 4; //IA, IB
|
||||
if(u == 0) r[n] = r[n] - bit::count(list) * 4; //DA, DB
|
||||
}
|
||||
|
||||
//if(l)exception=true;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue