From 0f643e01b733b1e59f9a9eb17c7582a399b31a42 Mon Sep 17 00:00:00 2001 From: Lior Halphon Date: Fri, 8 Sep 2017 12:58:35 +0300 Subject: [PATCH] Removing the delayed interrupt mechanism, research is not complete enough for implementation --- Core/display.c | 11 ----------- Core/gb.h | 1 - Core/timing.c | 3 +-- Core/z80_cpu.c | 2 +- 4 files changed, 2 insertions(+), 15 deletions(-) diff --git a/Core/display.c b/Core/display.c index 4def6c89..ae0e77f3 100755 --- a/Core/display.c +++ b/Core/display.c @@ -300,7 +300,6 @@ static void update_display_state(GB_gameboy_t *gb, uint8_t cycles) uint8_t vram_blocking_rush = gb->is_cgb? 0 : 4; for (; cycles; cycles -= atomic_increase) { - gb->delayed_interrupts &= ~3; gb->display_cycles += atomic_increase; /* The very first line is 4 clocks shorter when the LCD turns on. Verified on SGB2, CGB in CGB mode and CGB in double speed mode. */ @@ -344,10 +343,6 @@ static void update_display_state(GB_gameboy_t *gb, uint8_t cycles) gb->io_registers[GB_IO_STAT] &= ~3; gb->io_registers[GB_IO_STAT] |= 1; gb->io_registers[GB_IO_IF] |= 1; - if (gb->is_cgb) { - /* See comment on STAT interrupt at the end of the loop */ - gb->delayed_interrupts |= 1; - } /* Entering VBlank state triggers the OAM interrupt. In CGB, it happens 4 cycles earlier */ if (gb->io_registers[GB_IO_STAT] & 0x20 && !gb->is_cgb) { @@ -563,12 +558,6 @@ static void update_display_state(GB_gameboy_t *gb, uint8_t cycles) if (gb->stat_interrupt_line && !previous_stat_interrupt_line) { gb->io_registers[GB_IO_IF] |= 2; - if (gb->is_cgb) { - /* On CGB, the STAT interrupt is not aligned to a T-Cycle, therefore it is only effective the next T-Cycle - Todo: verify on DMG mode CGB. This was only tested on LYC STAT interrupts, should be tested on others - as well. */ - gb->delayed_interrupts |= 2; - } } #if 0 diff --git a/Core/gb.h b/Core/gb.h index 773dccc1..c18bf304 100644 --- a/Core/gb.h +++ b/Core/gb.h @@ -332,7 +332,6 @@ struct GB_gameboy_internal_s { GB_PADDING(uint16_t, serial_cycles); uint16_t serial_cycles; /* This field changed its meaning in v0.10 */ uint16_t serial_length; - uint8_t delayed_interrupts; /* When an interrupt occurs while not aligned to a T-cycle, it must be "delayed" */ bool dont_delay_timer_interrupt; /* If the timer glitch causes a TIMA overflow, it causes the timer to overflow with different timing, so the triggered interrupt is not delayed. Todo: needs test ROM. */ diff --git a/Core/timing.c b/Core/timing.c index 626cb455..e5ac7882 100644 --- a/Core/timing.c +++ b/Core/timing.c @@ -82,14 +82,13 @@ static void GB_ir_run(GB_gameboy_t *gb) static void advance_tima_state_machine(GB_gameboy_t *gb) { - gb->delayed_interrupts &= ~4; if (gb->tima_reload_state == GB_TIMA_RELOADED) { gb->tima_reload_state = GB_TIMA_RUNNING; } else if (gb->tima_reload_state == GB_TIMA_RELOADING) { gb->io_registers[GB_IO_IF] |= 4; if (!gb->dont_delay_timer_interrupt) { - gb->delayed_interrupts |= 4; // Timer interrupt is not aligned to a T-cycle and therefore is effective only the next one. + // Todo } gb->tima_reload_state = GB_TIMA_RELOADED; } diff --git a/Core/z80_cpu.c b/Core/z80_cpu.c index b6dde8a5..ce30d551 100644 --- a/Core/z80_cpu.c +++ b/Core/z80_cpu.c @@ -1337,7 +1337,7 @@ static GB_opcode_t *opcodes[256] = { void GB_cpu_run(GB_gameboy_t *gb) { gb->vblank_just_occured = false; - uint8_t interrupt_queue = gb->interrupt_enable & gb->io_registers[GB_IO_IF] & 0x1F & ~gb->delayed_interrupts; + uint8_t interrupt_queue = gb->interrupt_enable & gb->io_registers[GB_IO_IF] & 0x1F; if (interrupt_queue) { gb->halted = false;