mirror of https://github.com/bsnes-emu/bsnes.git
Moved the fetcher state machine to another function
This commit is contained in:
Lior Halphon
parent
0461fb5b2a
commit
0751eae90b
233
Core/display.c
233
Core/display.c
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@ -399,6 +399,130 @@ static inline uint8_t fetcher_y(GB_gameboy_t *gb)
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return gb->current_line + (gb->in_window? - gb->io_registers[GB_IO_WY] - gb->wy_diff : gb->io_registers[GB_IO_SCY]);
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}
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static uint8_t advance_fetcher_state_machine(GB_gameboy_t *gb)
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{
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typedef enum {
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GB_FETCHER_GET_TILE,
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GB_FETCHER_GET_TILE_DATA_LOWER,
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GB_FETCHER_GET_TILE_DATA_HIGH,
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GB_FETCHER_PUSH,
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GB_FETCHER_SLEEP,
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} fetcher_step_t;
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fetcher_step_t fetcher_state_machine [8] = {
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GB_FETCHER_SLEEP,
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GB_FETCHER_GET_TILE,
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GB_FETCHER_SLEEP,
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GB_FETCHER_GET_TILE_DATA_LOWER,
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GB_FETCHER_SLEEP,
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GB_FETCHER_GET_TILE_DATA_HIGH,
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GB_FETCHER_SLEEP,
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GB_FETCHER_PUSH,
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};
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uint8_t delay = 0;
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switch (fetcher_state_machine[gb->fetcher_state]) {
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case GB_FETCHER_GET_TILE: {
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uint16_t map = 0x1800;
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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if (gb->io_registers[GB_IO_LCDC] & 0x08 && !gb->in_window) {
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map = 0x1C00;
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}
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else if (gb->io_registers[GB_IO_LCDC] & 0x40 && gb->in_window) {
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map = 0x1C00;
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}
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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uint8_t y = fetcher_y(gb);
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if (gb->is_cgb) {
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/* This value is cached on the CGB, so it cannot be used to mix tiles together */
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/* Todo: This is NOT true on CGB-B! This is likely the case for all CGBs prior to D.
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Currently, SameBoy is emulating CGB-E, but if other revisions are added in the future
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this should be taken care of*/
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gb->fetcher_y = y;
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}
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gb->current_tile = gb->vram[map + gb->fetcher_x + y / 8 * 32];
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if (gb->is_cgb) {
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/* The CGB actually accesses both the tile index AND the attributes in the same T-cycle.
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This probably means the CGB has a 16-bit data bus for the VRAM. */
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gb->current_tile_attributes = gb->vram[map + gb->fetcher_x + y / 8 * 32 + 0x2000];
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}
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gb->fetcher_x++;
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gb->fetcher_x &= 0x1f;
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}
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break;
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case GB_FETCHER_GET_TILE_DATA_LOWER: {
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uint8_t y_flip = 0;
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uint16_t tile_address = 0;
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uint8_t y = gb->is_cgb? gb->fetcher_y : fetcher_y(gb);
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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if (gb->io_registers[GB_IO_LCDC] & 0x10) {
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tile_address = gb->current_tile * 0x10;
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}
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else {
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tile_address = (int8_t)gb->current_tile * 0x10 + 0x1000;
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}
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if (gb->current_tile_attributes & 8) {
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tile_address += 0x2000;
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}
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if (gb->current_tile_attributes & 0x40) {
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y_flip = 0x7;
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}
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gb->current_tile_data[0] =
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gb->vram[tile_address + ((y & 7) ^ y_flip) * 2];
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}
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break;
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case GB_FETCHER_GET_TILE_DATA_HIGH: {
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong.
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Additionally, on the CGB mixing two tiles by changing the tileset bit
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mid-fetching causes a glitched mixing of the two, in comparison to the
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more logical DMG version. */
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uint16_t tile_address = 0;
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uint8_t y = gb->is_cgb? gb->fetcher_y : fetcher_y(gb);
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if (gb->io_registers[GB_IO_LCDC] & 0x10) {
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tile_address = gb->current_tile * 0x10;
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}
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else {
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tile_address = (int8_t)gb->current_tile * 0x10 + 0x1000;
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}
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if (gb->current_tile_attributes & 8) {
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tile_address += 0x2000;
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}
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uint8_t y_flip = 0;
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if (gb->current_tile_attributes & 0x40) {
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y_flip = 0x7;
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}
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gb->current_tile_data[1] =
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gb->vram[tile_address + ((y & 7) ^ y_flip) * 2 + 1];
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}
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break;
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case GB_FETCHER_PUSH: {
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fifo_push_bg_row(&gb->bg_fifo, gb->current_tile_data[0], gb->current_tile_data[1],
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gb->current_tile_attributes & 7, gb->current_tile_attributes & 0x80, gb->current_tile_attributes & 0x20);
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gb->bg_fifo_paused = false;
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gb->oam_fifo_paused = false;
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delay = gb->fetcher_stop_penalty;
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gb->fetcher_stop_penalty = 0;
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}
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break;
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case GB_FETCHER_SLEEP:
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break;
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}
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gb->fetcher_state++;
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gb->fetcher_state &= 7;
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return delay;
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}
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void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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{
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GB_object_t *objects = (GB_object_t *) &gb->oam;
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@ -567,8 +691,7 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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GB_SLEEP(gb, display, 10, 5);
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/* The actual rendering cycle */
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gb->fetcher_divisor = false;
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gb->fetcher_state = GB_FETCHER_GET_TILE;
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gb->fetcher_state = 0;
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gb->bg_fifo_paused = false;
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gb->oam_fifo_paused = false;
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gb->in_window = false;
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@ -589,7 +712,7 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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if (gb->fetcher_stop_penalty == 0) {
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/* TODO: figure out why the penalty works this way and actual access timings */
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/* Penalty for interrupting the fetcher */
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gb->fetcher_stop_penalty = (uint8_t[]){5, 4, 3, 2, 1, 0, 0, 0}[gb->fetcher_state * 2 + gb->fetcher_divisor];
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gb->fetcher_stop_penalty = (uint8_t[]){5, 4, 3, 2, 1, 0, 0, 0}[gb->fetcher_state];
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if (gb->obj_comperators[gb->n_visible_objs - 1] == 0) {
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gb->fetcher_stop_penalty += gb->extra_penalty_for_sprite_at_0;
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}
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@ -636,108 +759,14 @@ void GB_display_run(GB_gameboy_t *gb, uint8_t cycles)
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gb->bg_fifo_paused = true;
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gb->oam_fifo_paused = true;
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gb->fetcher_x = 0;
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gb->fetcher_state = GB_FETCHER_GET_TILE;
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gb->fetcher_state = 0;
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}
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if (gb->fetcher_divisor) {
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switch (gb->fetcher_state) {
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case GB_FETCHER_GET_TILE: {
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uint16_t map = 0x1800;
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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if (gb->io_registers[GB_IO_LCDC] & 0x08 && !gb->in_window) {
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map = 0x1C00;
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{
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uint8_t fetcher_delay = advance_fetcher_state_machine(gb);
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gb->cycles_for_line += fetcher_delay;
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GB_SLEEP(gb, display, 19, fetcher_delay);
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}
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else if (gb->io_registers[GB_IO_LCDC] & 0x40 && gb->in_window) {
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map = 0x1C00;
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}
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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uint8_t y = fetcher_y(gb);
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if (gb->is_cgb) {
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/* This value is cached on the CGB, so it cannot be used to mix tiles together */
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/* Todo: This is NOT true on CGB-B! This is likely the case for all CGBs prior to D.
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Currently, SameBoy is emulating CGB-E, but if other revisions are added in the future
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this should be taken care of*/
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gb->fetcher_y = y;
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}
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gb->current_tile = gb->vram[map + gb->fetcher_x + y / 8 * 32];
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if (gb->is_cgb) {
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/* The CGB actually accesses both the tile index AND the attributes in the same T-cycle.
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This probably means the CGB has a 16-bit data bus for the VRAM. */
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gb->current_tile_attributes = gb->vram[map + gb->fetcher_x + y / 8 * 32 + 0x2000];
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}
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gb->fetcher_x++;
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gb->fetcher_x &= 0x1f;
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}
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break;
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case GB_FETCHER_GET_TILE_DATA_LOWER: {
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uint8_t y_flip = 0;
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uint16_t tile_address = 0;
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uint8_t y = gb->is_cgb? gb->fetcher_y : fetcher_y(gb);
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong. */
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if (gb->io_registers[GB_IO_LCDC] & 0x10) {
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tile_address = gb->current_tile * 0x10;
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}
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else {
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tile_address = (int8_t)gb->current_tile * 0x10 + 0x1000;
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}
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if (gb->current_tile_attributes & 8) {
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tile_address += 0x2000;
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}
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if (gb->current_tile_attributes & 0x40) {
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y_flip = 0x7;
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}
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gb->current_tile_data[0] =
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gb->vram[tile_address + ((y & 7) ^ y_flip) * 2];
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}
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break;
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case GB_FETCHER_GET_TILE_DATA_HIGH: {
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/* Todo: Verified for DMG (Tested: SGB2), CGB timing is wrong.
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Additionally, on the CGB mixing two tiles by changing the tileset bit
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mid-fetching causes a glitched mixing of the two, in comparison to the
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more logical DMG version. */
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uint16_t tile_address = 0;
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uint8_t y = gb->is_cgb? gb->fetcher_y : fetcher_y(gb);
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if (gb->io_registers[GB_IO_LCDC] & 0x10) {
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tile_address = gb->current_tile * 0x10;
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}
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else {
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tile_address = (int8_t)gb->current_tile * 0x10 + 0x1000;
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}
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if (gb->current_tile_attributes & 8) {
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tile_address += 0x2000;
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}
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uint8_t y_flip = 0;
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if (gb->current_tile_attributes & 0x40) {
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y_flip = 0x7;
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}
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gb->current_tile_data[1] =
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gb->vram[tile_address + ((y & 7) ^ y_flip) * 2 + 1];
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}
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break;
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case GB_FETCHER_SLEEP: {
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gb->cycles_for_line += gb->fetcher_stop_penalty;
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GB_SLEEP(gb, display, 19, gb->fetcher_stop_penalty);
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gb->fetcher_stop_penalty = 0;
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fifo_push_bg_row(&gb->bg_fifo, gb->current_tile_data[0], gb->current_tile_data[1],
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gb->current_tile_attributes & 7, gb->current_tile_attributes & 0x80, gb->current_tile_attributes & 0x20);
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gb->bg_fifo_paused = false;
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gb->oam_fifo_paused = false;
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}
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break;
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}
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gb->fetcher_state++;
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gb->fetcher_state &= 3;
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}
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gb->fetcher_divisor ^= true;
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render_pixel_if_possible(gb);
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if (gb->position_in_line == 160) break;
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@ -411,14 +411,7 @@ struct GB_gameboy_internal_s {
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uint8_t current_tile;
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uint8_t current_tile_attributes;
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uint8_t current_tile_data[2];
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enum {
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GB_FETCHER_GET_TILE,
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GB_FETCHER_GET_TILE_DATA_LOWER,
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GB_FETCHER_GET_TILE_DATA_HIGH,
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GB_FETCHER_SLEEP,
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GB_FETCHER_MAX = GB_FETCHER_SLEEP,
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} fetcher_state:8;
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bool fetcher_divisor; // The fetcher runs at 2MHz
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uint8_t fetcher_state;
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bool bg_fifo_paused;
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bool oam_fifo_paused;
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bool in_window;
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