2017-01-13 23:59:38 +00:00
|
|
|
#define op(id, name, ...) case id: instruction_##name(__VA_ARGS__); return;
|
|
|
|
|
#define fp(name) &HuC6280::name
|
2017-01-13 01:15:45 +00:00
|
|
|
|
2017-01-16 21:02:56 +00:00
|
|
|
auto HuC6280::interrupt(uint16 vector) -> void {
|
|
|
|
|
io();
|
|
|
|
|
io();
|
|
|
|
|
push(PC >> 8);
|
|
|
|
|
push(PC >> 0);
|
|
|
|
|
push(P);
|
|
|
|
|
D = 0;
|
|
|
|
|
I = 1;
|
Update to v102 release.
byuu says (in the public announcement):
This release adds very preliminary emulation of the Sega Master System
(Mark III), Sega Game Gear, Sega Mega Drive (Genesis), and NEC PC Engine
(Turbografx-16). These cores do not yet offer sound emulation, save
states or cheat codes.
I'm always very hesitant to release a new emulation core in its alpha
stages, as in the past this has resulted in lasting bad impressions
of cores that have since improved greatly. For instance, the Game Boy
Advance emulation offered today is easily the second most accurate around,
yet it is still widely judged by its much older alpha implementation.
However, it's always been tradition with higan to not hold onto code
in secret. Rather than delay future releases for another year or two,
I'll put my faith in you all to understand that the emulation of these
systems will improve over time.
I hope that by releasing things as they are now, I might be able to
receive some much needed assistance in improving these cores, as the
documentation for these new systems is very much less than ideal.
byuu says (in the WIP forum):
Changelog:
- PCE: latch background scroll registers (fixes Neutopia scrolling)
- PCE: clip background attribute table scrolling (fixes Blazing Lazers
scrolling)
- PCE: support background/sprite enable/disable bits
- PCE: fix large sprite indexing (fixes Blazing Lazers title screen
sprites)
- HuC6280: wrap zeropage accesses to never go beyond $20xx
- HuC6280: fix alternating addresses for block move instructions
(fixes Neutopia II)
- HuC6280: block move instructions save and restore A,X,Y registers
- HuC6280: emulate BCD mode (may not be 100% correct, based on SNES
BCD) (fixes Blazing Lazers scoring)
2017-01-19 21:01:15 +00:00
|
|
|
PC.byte(0) = load16(vector + 0);
|
|
|
|
|
L PC.byte(1) = load16(vector + 1);
|
2017-01-16 21:02:56 +00:00
|
|
|
}
|
|
|
|
|
|
2017-01-13 01:15:45 +00:00
|
|
|
auto HuC6280::instruction() -> void {
|
2017-01-13 23:59:38 +00:00
|
|
|
auto code = opcode();
|
|
|
|
|
|
|
|
|
|
if(T) {
|
|
|
|
|
T = 0;
|
|
|
|
|
switch(code) {
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x09, memory, fp(ORA))
|
|
|
|
|
op(0x29, memory, fp(AND))
|
|
|
|
|
op(0x49, memory, fp(EOR))
|
|
|
|
|
op(0x69, memory, fp(ADC))
|
2017-01-13 23:59:38 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-15 00:58:47 +00:00
|
|
|
#define U
|
2017-01-13 23:59:38 +00:00
|
|
|
switch(code) {
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x00, BRK)
|
|
|
|
|
op(0x01, indirectLoad, fp(ORA), A, X)
|
|
|
|
|
op(0x02, swap, X, Y)
|
|
|
|
|
op(0x03, ST, 0)
|
|
|
|
|
op(0x04, zeropageModify, fp(TSB))
|
|
|
|
|
op(0x05, zeropageLoad, fp(ORA), A)
|
|
|
|
|
op(0x06, zeropageModify, fp(ASL))
|
|
|
|
|
op(0x07, RMB, 0)
|
|
|
|
|
op(0x08, push, P)
|
|
|
|
|
op(0x09, immediate, fp(ORA), A)
|
|
|
|
|
op(0x0a, implied, fp(ASL), A)
|
|
|
|
|
U op(0x0b, NOP)
|
|
|
|
|
op(0x0c, absoluteModify, fp(TSB))
|
|
|
|
|
op(0x0d, absoluteLoad, fp(ORA), A)
|
|
|
|
|
op(0x0e, absoluteModify, fp(ASL))
|
|
|
|
|
op(0x0f, BBR, 0)
|
|
|
|
|
op(0x10, branch, N == 0)
|
|
|
|
|
op(0x11, indirectYLoad, fp(ORA), A)
|
|
|
|
|
op(0x12, indirectLoad, fp(ORA), A)
|
Update to v102r03 release.
byuu says:
Changelog:
- PCE: split VCE from VDC
- HuC6280: changed bus from (uint21 addr) to (uint8 bank, uint13 addr)
- added SuperGrafx emulation (adds secondary VDC, plus new VPC)
The VDC now has no concept of the actual display raster timing, and
instead is driven by Vpulse (start of frame) and Hpulse (start of
scanline) signals from the VCE. One still can't render the start of the
next scanline onto the current scanline through overly aggressive
timings, but it shouldn't be too much more difficult to allow that to
occur now. This process incurs quite a major speed hit, so low-end
systems with Atom CPUs can't run things at 60fps anymore.
The timing needs a lot of work. The pixels end up very jagged if the VCE
doesn't output batches of 2-4 pixels at a time. But this should not be a
requirement at all, so I'm not sure what's going wrong there.
Yo, Bro and the 512-width mode of TV Sports Basketball is now broken as
a result of these changes, and I'm not sure why.
To load SuperGrafx games, you're going to have to change the .pce
extensions to .sg or .sgx. Or you can manually move the games from the
PC Engine folder to the SuperGrafx folder and change the game folder
extensions. I have no way to tell the games apart. Mednafen uses CRC32
comparisons, and I may consider that since there's only five games, but
I'm not sure yet.
The only SuperGrafx game that's playable right now is Aldynes. And the
priorities are all screwed up. I don't understand how the windows or the
priorities work at all from sgxtech.txt, so ... yeah. It's pretty
broken, but it's a start.
I could really use some help with this, as I'm very lost right now with
rendering :/
-----
Note that the SuperGrafx is technically its own system, it's not an
add-on.
As such, I'm giving it a separate .sys folder, and a separate library.
There's debate over how to name this thing. "SuperGrafx" appears more
popular than "Super Grafx". And you might also call it the "PC Engine
SuperGrafx", but I decided to leave off the prefix so it appears more
distinct.
2017-01-23 21:18:54 +00:00
|
|
|
op(0x13, ST, 1)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x14, zeropageModify, fp(TRB))
|
|
|
|
|
op(0x15, zeropageLoad, fp(ORA), A, X)
|
|
|
|
|
op(0x16, zeropageModify, fp(ASL), X)
|
|
|
|
|
op(0x17, RMB, 1)
|
|
|
|
|
op(0x18, clear, C)
|
|
|
|
|
op(0x19, absoluteLoad, fp(ORA), A, Y)
|
|
|
|
|
op(0x1a, implied, fp(INC), A)
|
|
|
|
|
U op(0x1b, NOP)
|
|
|
|
|
op(0x1c, absoluteModify, fp(TRB))
|
|
|
|
|
op(0x1d, absoluteLoad, fp(ORA), A, X)
|
|
|
|
|
op(0x1e, absoluteModify, fp(ASL), X)
|
|
|
|
|
op(0x1f, BBR, 1)
|
|
|
|
|
op(0x20, JSR)
|
|
|
|
|
op(0x21, indirectLoad, fp(AND), A, X)
|
|
|
|
|
op(0x22, swap, A, X)
|
Update to v102r03 release.
byuu says:
Changelog:
- PCE: split VCE from VDC
- HuC6280: changed bus from (uint21 addr) to (uint8 bank, uint13 addr)
- added SuperGrafx emulation (adds secondary VDC, plus new VPC)
The VDC now has no concept of the actual display raster timing, and
instead is driven by Vpulse (start of frame) and Hpulse (start of
scanline) signals from the VCE. One still can't render the start of the
next scanline onto the current scanline through overly aggressive
timings, but it shouldn't be too much more difficult to allow that to
occur now. This process incurs quite a major speed hit, so low-end
systems with Atom CPUs can't run things at 60fps anymore.
The timing needs a lot of work. The pixels end up very jagged if the VCE
doesn't output batches of 2-4 pixels at a time. But this should not be a
requirement at all, so I'm not sure what's going wrong there.
Yo, Bro and the 512-width mode of TV Sports Basketball is now broken as
a result of these changes, and I'm not sure why.
To load SuperGrafx games, you're going to have to change the .pce
extensions to .sg or .sgx. Or you can manually move the games from the
PC Engine folder to the SuperGrafx folder and change the game folder
extensions. I have no way to tell the games apart. Mednafen uses CRC32
comparisons, and I may consider that since there's only five games, but
I'm not sure yet.
The only SuperGrafx game that's playable right now is Aldynes. And the
priorities are all screwed up. I don't understand how the windows or the
priorities work at all from sgxtech.txt, so ... yeah. It's pretty
broken, but it's a start.
I could really use some help with this, as I'm very lost right now with
rendering :/
-----
Note that the SuperGrafx is technically its own system, it's not an
add-on.
As such, I'm giving it a separate .sys folder, and a separate library.
There's debate over how to name this thing. "SuperGrafx" appears more
popular than "Super Grafx". And you might also call it the "PC Engine
SuperGrafx", but I decided to leave off the prefix so it appears more
distinct.
2017-01-23 21:18:54 +00:00
|
|
|
op(0x23, ST, 2)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x24, zeropageLoad, fp(BIT), A)
|
|
|
|
|
op(0x25, zeropageLoad, fp(AND), A)
|
|
|
|
|
op(0x26, zeropageModify, fp(ROL))
|
|
|
|
|
op(0x27, RMB, 2)
|
Update to v102r04 release.
byuu says:
Changelog:
- Super Game Boy support is functional once again
- new GameBoy::SuperGameBoyInterface class
- system.(dmg,cgb,sgb) is now Model::(Super)GameBoy(Color) ala the PC
Engine
- merged WonderSwanInterface, WonderSwanColorInterface shared
functions to WonderSwan::Interface
- merged GameBoyInterface, GameBoyColorInterface shared functions to
GameBoy::Interface
- Interface::unload() now calls Interface::save() for Master System,
Game Gear, Mega Drive, PC Engine, SuperGrafx
- PCE: emulated PCE-CD backup RAM; stored per-game as save.ram (2KiB
file)
- this means you can now save your progress in games like Neutopia
- the PCE-CD I/O registers like BRAM write protect are not
emulated yet
- PCE: IRQ sources now hold the IRQ line state, instead of the CPU
holding it
- this fixes most SuperGrafx games, which were fighting over the
VDC IRQ line previously
- PCE: CPU I/O $14xx should return the pending IRQ bits even if IRQs
are disabled
- PCE: VCE and the VDCs now synchronize to each other; fixes pixel
widths in all games
- PCE: greatly increased the accuracy of the VPC priority selection
code (windows may be buggy still)
- HuC6280: PLA, PLX, PLY should set Z, N flags; fixes many game bugs
[Jonas Quinn]
The big thing I wanted to do was enslave the VDC(s) to the VCE. But
unfortunately, I forgot about the asynchronous DMA channels that each
VDC supports, so this isn't going to be possible I'm afraid.
In the most demanding case, Daimakaimura in-game, we're looking at 85fps
on my Xeon E3 1276v3. So ... not great, and we don't even have sound
connected yet.
We are going to have to profile and optimize this code once sound
emulation and save states are in.
Basically, think of it like this: the VCE, VDC0, and VDC1 all have the
same overhead, scheduling wise (which is the bulk of the performance
loss) as the dot-renderer for the SNES core. So it's like there's three
bsnes-accuracy PPU threads running just for video.
-----
Oh, just a fair warning ... the hooks for the SGB are a work in
progress.
If anyone is working on higan or a fork and want to do something similar
to it, don't use it as a template, at least not yet.
Right now, higan looks like this:
- Emulator::Video handles the platform→videoRefresh calls
- Emulator::Audio handles the platform→audioSample calls
- each core hard-codes the platform→inputPoll, inputRumble calls
- each core hard-codes calls to path, open, load to process files
- dipSettings and notify are specialty hacks, neither are even hooked
up right now to anything
With the SGB, it's an emulation core inside an emulation core, so
ideally you want to hook all of those functions. Emulator::Video and
Emulator::Audio aren't really abstractions over that, as the GB core
calls them and we have to special case not calling them in SGB mode.
The path, open, load can be implemented without hooks, thanks to the UI
only using one instance of Emulator::Platform for all cores. All we have
to do is override the folder path ID for the "Game Boy.sys" folder, so
that it picks "Super Game Boy.sfc/" and loads its boot ROM instead.
That's just a simple argument to GameBoy::System::load() and we're done.
dipSettings, notify and inputRumble don't matter. But we do also have to
hook inputPoll as well.
The nice idea would be for SuperFamicom::ICD2 to inherit from
Emulator::Platform and provide the desired functions that we need to
overload. After that, we'd just need the GB core to keep an abstraction
over the global Emulator::platform\* handle, to select between the UI
version and the SFC::ICD2 version.
However ... that doesn't work because of Emulator::Video and
Emulator::Audio. They would also have to gain an abstraction over
Emulator::platform\*, and even worse ... you'd have to constantly swap
between the two so that the SFC core uses the UI, and the GB core uses
the ICD2.
And so, for right now, I'm checking Model::SuperGameBoy() -> bool
everywhere, and choosing between the UI and ICD2 targets that way. And
as such, the ICD2 doesn't really need Emulator::Platform inheritance,
although it certainly could do that and just use the functions it needs.
But the SGB is even weirder, because we need additional new signals
beyond just Emulator::Platform, like joypWrite(), etc.
I'd also like to work on the Emulator::Stream for the SGB core. I don't
see why we can't have the GB core create its own stream, and let the
ICD2 just use that instead. We just have to be careful about the ICD2's
CPU soft reset function, to make sure the GB core's Stream object
remains valid. What I think that needs is a way to release an
Emulator::Stream individually, rather than calling
Emulator::Audio::reset() to do it. They are shared\_pointer objects, so
I think if I added a destructor function to remove it from
Emulator::Audio::streams, then that should work.
2017-01-26 01:06:06 +00:00
|
|
|
op(0x28, PLP)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x29, immediate, fp(AND), A)
|
|
|
|
|
op(0x2a, implied, fp(ROL), A)
|
|
|
|
|
U op(0x2b, NOP)
|
|
|
|
|
op(0x2c, absoluteLoad, fp(BIT), A)
|
|
|
|
|
op(0x2d, absoluteLoad, fp(AND), A)
|
|
|
|
|
op(0x2e, absoluteModify, fp(ROL))
|
|
|
|
|
op(0x2f, BBR, 2)
|
|
|
|
|
op(0x30, branch, N == 1)
|
|
|
|
|
op(0x31, indirectYLoad, fp(AND), A)
|
|
|
|
|
op(0x32, indirectLoad, fp(AND), A)
|
|
|
|
|
U op(0x33, NOP)
|
|
|
|
|
op(0x34, zeropageLoad, fp(BIT), A, X)
|
|
|
|
|
op(0x35, zeropageLoad, fp(AND), A, X)
|
|
|
|
|
op(0x36, zeropageModify, fp(ROL), X)
|
|
|
|
|
op(0x37, RMB, 3)
|
|
|
|
|
op(0x38, set, C)
|
|
|
|
|
op(0x39, absoluteLoad, fp(AND), A, Y)
|
|
|
|
|
op(0x3a, implied, fp(DEC), A)
|
|
|
|
|
U op(0x3b, NOP)
|
|
|
|
|
op(0x3c, absoluteLoad, fp(BIT), A, X)
|
|
|
|
|
op(0x3d, absoluteLoad, fp(AND), A, X)
|
|
|
|
|
op(0x3e, absoluteModify, fp(ROL), X)
|
|
|
|
|
op(0x3f, BBR, 3)
|
|
|
|
|
op(0x40, RTI)
|
|
|
|
|
op(0x41, indirectLoad, fp(EOR), A, X)
|
|
|
|
|
op(0x42, swap, A, Y)
|
2017-01-13 23:59:38 +00:00
|
|
|
op(0x43, TMA)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x44, BSR)
|
|
|
|
|
op(0x45, zeropageLoad, fp(EOR), A)
|
|
|
|
|
op(0x46, zeropageModify, fp(LSR))
|
|
|
|
|
op(0x47, RMB, 4)
|
|
|
|
|
op(0x48, push, A)
|
|
|
|
|
op(0x49, immediate, fp(EOR), A)
|
|
|
|
|
op(0x4a, implied, fp(LSR), A)
|
|
|
|
|
U op(0x4b, NOP)
|
|
|
|
|
op(0x4c, JMP_absolute)
|
|
|
|
|
op(0x4d, absoluteLoad, fp(EOR), A)
|
|
|
|
|
op(0x4e, absoluteModify, fp(LSR))
|
|
|
|
|
op(0x4f, BBR, 4)
|
|
|
|
|
op(0x50, branch, V == 0)
|
|
|
|
|
op(0x51, indirectYLoad, fp(EOR), A)
|
|
|
|
|
op(0x52, indirectLoad, fp(EOR), A)
|
2017-01-13 23:59:38 +00:00
|
|
|
op(0x53, TAM)
|
|
|
|
|
op(0x54, CSL)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0x55, zeropageLoad, fp(EOR), A, X)
|
|
|
|
|
op(0x56, zeropageModify, fp(LSR), X)
|
|
|
|
|
op(0x57, RMB, 5)
|
|
|
|
|
op(0x58, clear, I)
|
|
|
|
|
op(0x59, absoluteLoad, fp(EOR), A, Y)
|
|
|
|
|
op(0x5a, push, Y)
|
|
|
|
|
U op(0x5b, NOP)
|
|
|
|
|
U op(0x5c, NOP)
|
|
|
|
|
op(0x5d, absoluteLoad, fp(EOR), A, X)
|
|
|
|
|
op(0x5e, absoluteModify, fp(LSR), X)
|
|
|
|
|
op(0x5f, BBR, 5)
|
|
|
|
|
op(0x60, RTS)
|
|
|
|
|
op(0x61, indirectLoad, fp(ADC), A, X)
|
|
|
|
|
op(0x62, clear, A)
|
|
|
|
|
U op(0x63, NOP)
|
|
|
|
|
op(0x64, zeropageStore, 0)
|
|
|
|
|
op(0x65, zeropageLoad, fp(ADC), A)
|
|
|
|
|
op(0x66, zeropageModify, fp(ROR))
|
|
|
|
|
op(0x67, RMB, 6)
|
|
|
|
|
op(0x68, pull, A)
|
|
|
|
|
op(0x69, immediate, fp(ADC), A)
|
|
|
|
|
op(0x6a, implied, fp(ROR), A)
|
|
|
|
|
U op(0x6b, NOP)
|
|
|
|
|
op(0x6c, JMP_indirect)
|
|
|
|
|
op(0x6d, absoluteLoad, fp(ADC), A)
|
|
|
|
|
op(0x6e, absoluteModify, fp(ROR))
|
|
|
|
|
op(0x6f, BBR, 6)
|
|
|
|
|
op(0x70, branch, V == 1)
|
|
|
|
|
op(0x71, indirectYLoad, fp(ADC), A)
|
|
|
|
|
op(0x72, indirectLoad, fp(ADC), A)
|
|
|
|
|
op(0x73, blockmove, fp(TII))
|
|
|
|
|
op(0x74, zeropageStore, 0, X)
|
|
|
|
|
op(0x75, zeropageLoad, fp(ADC), A, X)
|
|
|
|
|
op(0x76, zeropageModify, fp(ROR), X)
|
|
|
|
|
op(0x77, RMB, 7)
|
|
|
|
|
op(0x78, set, I)
|
|
|
|
|
op(0x79, absoluteLoad, fp(ADC), A, Y)
|
|
|
|
|
op(0x7a, pull, Y)
|
|
|
|
|
U op(0x7b, NOP)
|
|
|
|
|
op(0x7c, JMP_indirect, X)
|
|
|
|
|
op(0x7d, absoluteLoad, fp(ADC), A, X)
|
|
|
|
|
op(0x7e, absoluteModify, fp(ROR), X)
|
|
|
|
|
op(0x7f, BBR, 7)
|
|
|
|
|
op(0x80, branch, 1)
|
|
|
|
|
op(0x81, indirectStore, A, X)
|
|
|
|
|
op(0x82, clear, X)
|
|
|
|
|
op(0x83, TST_zeropage)
|
|
|
|
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op(0x84, zeropageStore, Y)
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op(0x85, zeropageStore, A)
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op(0x86, zeropageStore, X)
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op(0x87, SMB, 0)
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op(0x88, implied, fp(DEC), Y)
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op(0x89, immediate, fp(BIT), A)
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op(0x8a, transfer, X, A)
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U op(0x8b, NOP)
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op(0x8c, absoluteStore, Y)
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op(0x8d, absoluteStore, A)
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op(0x8e, absoluteStore, X)
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op(0x8f, BBS, 0)
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op(0x90, branch, C == 0)
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op(0x91, indirectYStore, A)
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op(0x92, indirectStore, A)
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op(0x93, TST_absolute)
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op(0x94, zeropageStore, Y, X)
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op(0x95, zeropageStore, A, X)
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op(0x96, zeropageStore, X, Y)
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op(0x97, SMB, 1)
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op(0x98, transfer, Y, A)
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op(0x99, absoluteStore, A, Y)
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2017-01-13 23:59:38 +00:00
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op(0x9a, TXS)
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2017-01-15 00:58:47 +00:00
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U op(0x9b, NOP)
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op(0x9c, absoluteStore, 0)
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op(0x9d, absoluteStore, A, X)
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op(0x9e, absoluteStore, 0, X)
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op(0x9f, BBS, 1)
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op(0xa0, immediate, fp(LD), Y)
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op(0xa1, indirectLoad, fp(LD), A, X)
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op(0xa2, immediate, fp(LD), X)
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op(0xa3, TST_zeropage, X)
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op(0xa4, zeropageLoad, fp(LD), Y)
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op(0xa5, zeropageLoad, fp(LD), A)
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op(0xa6, zeropageLoad, fp(LD), X)
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op(0xa7, SMB, 2)
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op(0xa8, transfer, A, Y)
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op(0xa9, immediate, fp(LD), A)
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op(0xaa, transfer, A, X)
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U op(0xab, NOP)
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op(0xac, absoluteLoad, fp(LD), Y)
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op(0xad, absoluteLoad, fp(LD), A)
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op(0xae, absoluteLoad, fp(LD), X)
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op(0xaf, BBS, 2)
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op(0xb0, branch, C == 1)
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op(0xb1, indirectYLoad, fp(LD), A)
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op(0xb2, indirectLoad, fp(LD), A)
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op(0xb3, TST_absolute, X)
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op(0xb4, zeropageLoad, fp(LD), Y, X)
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op(0xb5, zeropageLoad, fp(LD), A, X)
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op(0xb6, zeropageLoad, fp(LD), X, Y)
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op(0xb7, SMB, 3)
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op(0xb8, clear, V)
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op(0xb9, absoluteLoad, fp(LD), A, Y)
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op(0xba, transfer, S, X)
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U op(0xbb, NOP)
|
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op(0xbc, absoluteLoad, fp(LD), Y, X)
|
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op(0xbd, absoluteLoad, fp(LD), A, X)
|
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op(0xbe, absoluteLoad, fp(LD), X, Y)
|
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|
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op(0xbf, BBS, 3)
|
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op(0xc0, immediate, fp(CPY), Y)
|
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op(0xc1, indirectLoad, fp(CMP), A, X)
|
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op(0xc2, clear, Y)
|
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|
|
|
op(0xc3, blockmove, fp(TDD))
|
|
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|
|
op(0xc4, zeropageLoad, fp(CPY), Y)
|
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|
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op(0xc5, zeropageLoad, fp(CMP), A)
|
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|
op(0xc6, zeropageModify, fp(DEC))
|
|
|
|
|
op(0xc7, SMB, 4)
|
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|
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|
op(0xc8, implied, fp(INC), Y)
|
|
|
|
|
op(0xc9, immediate, fp(CMP), A)
|
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|
|
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op(0xca, implied, fp(DEC), X)
|
|
|
|
|
U op(0xcb, NOP)
|
|
|
|
|
op(0xcc, absoluteLoad, fp(CPY), Y)
|
|
|
|
|
op(0xcd, absoluteLoad, fp(CMP), A)
|
|
|
|
|
op(0xce, absoluteModify, fp(DEC))
|
|
|
|
|
op(0xcf, BBS, 4)
|
|
|
|
|
op(0xd0, branch, Z == 0)
|
|
|
|
|
op(0xd1, indirectYLoad, fp(CMP), A)
|
|
|
|
|
op(0xd2, indirectLoad, fp(CMP), A)
|
|
|
|
|
op(0xd3, blockmove, fp(TIN))
|
2017-01-13 23:59:38 +00:00
|
|
|
op(0xd4, CSH)
|
2017-01-15 00:58:47 +00:00
|
|
|
op(0xd5, zeropageLoad, fp(CMP), A, X)
|
|
|
|
|
op(0xd6, zeropageModify, fp(DEC), X)
|
|
|
|
|
op(0xd7, SMB, 5)
|
|
|
|
|
op(0xd8, clear, D)
|
|
|
|
|
op(0xd9, absoluteLoad, fp(CMP), A, Y)
|
|
|
|
|
op(0xda, push, X)
|
|
|
|
|
U op(0xdb, NOP)
|
|
|
|
|
U op(0xdc, NOP)
|
|
|
|
|
op(0xdd, absoluteLoad, fp(CMP), A, X)
|
|
|
|
|
op(0xde, absoluteModify, fp(DEC), X)
|
|
|
|
|
op(0xdf, BBS, 5)
|
|
|
|
|
op(0xe0, immediate, fp(CPX), X)
|
|
|
|
|
op(0xe1, indirectLoad, fp(SBC), A, X)
|
|
|
|
|
U op(0xe2, NOP)
|
|
|
|
|
op(0xe3, blockmove, fp(TIA))
|
|
|
|
|
op(0xe4, zeropageLoad, fp(CPX), X)
|
|
|
|
|
op(0xe5, zeropageLoad, fp(SBC), A)
|
|
|
|
|
op(0xe6, zeropageModify, fp(INC))
|
|
|
|
|
op(0xe7, SMB, 6)
|
|
|
|
|
op(0xe8, implied, fp(INC), X)
|
|
|
|
|
op(0xe9, immediate, fp(SBC), A)
|
2017-01-13 01:15:45 +00:00
|
|
|
op(0xea, NOP)
|
2017-01-15 00:58:47 +00:00
|
|
|
U op(0xeb, NOP)
|
|
|
|
|
op(0xec, absoluteLoad, fp(CPX), X)
|
|
|
|
|
op(0xed, absoluteLoad, fp(SBC), A)
|
|
|
|
|
op(0xee, absoluteModify, fp(INC))
|
|
|
|
|
op(0xef, BBS, 6)
|
|
|
|
|
op(0xf0, branch, Z == 1)
|
|
|
|
|
op(0xf1, indirectYLoad, fp(SBC), A)
|
|
|
|
|
op(0xf2, indirectLoad, fp(SBC), A)
|
|
|
|
|
op(0xf3, blockmove, fp(TAI))
|
|
|
|
|
op(0xf4, set, T)
|
|
|
|
|
op(0xf5, zeropageLoad, fp(SBC), A, X)
|
|
|
|
|
op(0xf6, zeropageModify, fp(INC), X)
|
|
|
|
|
op(0xf7, SMB, 7)
|
|
|
|
|
op(0xf8, set, D)
|
|
|
|
|
op(0xf9, absoluteLoad, fp(SBC), A, Y)
|
|
|
|
|
op(0xfa, pull, X)
|
|
|
|
|
U op(0xfb, NOP)
|
|
|
|
|
U op(0xfc, NOP)
|
|
|
|
|
op(0xfd, absoluteLoad, fp(SBC), A, X)
|
|
|
|
|
op(0xfe, absoluteModify, fp(INC), X)
|
|
|
|
|
op(0xff, BBS, 7)
|
2017-01-13 01:15:45 +00:00
|
|
|
}
|
2017-01-15 00:58:47 +00:00
|
|
|
#undef U
|
2017-01-13 01:15:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef op
|
2017-01-13 23:59:38 +00:00
|
|
|
#undef fp
|