2011-11-04 11:57:54 +00:00
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struct VRC3 : Chip {
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2015-12-05 05:44:49 +00:00
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VRC3(Board& board) : Chip(board) {
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}
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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auto main() -> void {
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2016-02-09 11:51:12 +00:00
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if(irq_enable) {
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if(irq_mode == 0) { //16-bit
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if(++irq_counter.w == 0) {
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irq_line = 1;
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irq_enable = irq_acknowledge;
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irq_counter.w = irq_latch;
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2011-11-04 11:57:54 +00:00
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}
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2016-02-09 11:51:12 +00:00
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}
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if(irq_mode == 1) { //8-bit
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if(++irq_counter.l == 0) {
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irq_line = 1;
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irq_enable = irq_acknowledge;
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irq_counter.l = irq_latch;
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2011-11-04 11:57:54 +00:00
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}
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}
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}
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2016-02-09 11:51:12 +00:00
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Update to v099r04 release.
byuu says:
Changelog:
- lots of code cleanups to processor/r6502 (the switch.cpp file is only
halfway done ...)
- lots of code cleanups to fc/cpu
- removed fc/input
- implemented fc/controller
hex_usr, you may not like this, but I want to keep the controller port
and expansion port interface separate, like I do with the SNES. I realize
the NES' is used more for controllers, and the SNES' more for hardware
expansions, but ... they're not compatible pinouts and you can't really
connect one to the other.
Right now, I've only implemented the controller portion. I'll have to
get to the peripheral portion later.
Also, the gamepad implementation there now may be wrong. It's based off
the Super Famicom version obviously. I'm not sure if the Famicom has
different behavior with latching $4016 writes, or not. But, it works in
Mega Man II, so it's a start.
Everyone, be sure to remap your controls, and then set port 1 -> gamepad
after loading your first Famicom game with the new WIP.
2016-06-18 06:04:32 +00:00
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cpu.irqLine(irq_line);
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2016-02-09 11:51:12 +00:00
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tick();
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2015-12-05 05:44:49 +00:00
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}
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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auto prg_addr(uint addr) const -> uint {
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uint bank = (addr < 0xc000 ? (uint)prg_bank : 0x0f);
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return (bank * 0x4000) + (addr & 0x3fff);
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2011-11-04 11:57:54 +00:00
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}
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2015-12-05 05:44:49 +00:00
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auto reg_write(uint addr, uint8 data) -> void {
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switch(addr & 0xf000) {
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case 0x8000: irq_latch = (irq_latch & 0xfff0) | ((data & 0x0f) << 0); break;
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case 0x9000: irq_latch = (irq_latch & 0xff0f) | ((data & 0x0f) << 4); break;
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case 0xa000: irq_latch = (irq_latch & 0xf0ff) | ((data & 0x0f) << 8); break;
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case 0xb000: irq_latch = (irq_latch & 0x0fff) | ((data & 0x0f) << 12); break;
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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case 0xc000:
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irq_mode = data & 0x04;
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irq_enable = data & 0x02;
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irq_acknowledge = data & 0x01;
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if(irq_enable) irq_counter.w = irq_latch;
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break;
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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case 0xd000:
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irq_line = 0;
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irq_enable = irq_acknowledge;
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break;
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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case 0xf000:
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prg_bank = data & 0x0f;
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break;
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}
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2011-11-04 11:57:54 +00:00
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}
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2015-12-05 05:44:49 +00:00
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auto power() -> void {
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}
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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auto reset() -> void {
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prg_bank = 0;
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irq_mode = 0;
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irq_enable = 0;
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irq_acknowledge = 0;
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irq_latch = 0;
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irq_counter.w = 0;
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irq_line = 0;
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}
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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auto serialize(serializer& s) -> void {
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s.integer(prg_bank);
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s.integer(irq_mode);
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s.integer(irq_enable);
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s.integer(irq_acknowledge);
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s.integer(irq_latch);
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s.integer(irq_counter.w);
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s.integer(irq_line);
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}
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2011-11-04 11:57:54 +00:00
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2015-12-05 05:44:49 +00:00
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uint4 prg_bank;
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bool irq_mode;
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bool irq_enable;
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bool irq_acknowledge;
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uint16 irq_latch;
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struct {
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union {
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2016-02-16 09:27:55 +00:00
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uint16_t w;
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struct { uint8_t order_lsb2(l, h); };
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2015-12-05 05:44:49 +00:00
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};
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} irq_counter;
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bool irq_line;
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2011-11-04 11:57:54 +00:00
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};
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