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bsnes/higan/processor/wdc65816/instructions-pc.cpp

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Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionBranch(bool take) -> void {
if(!take) {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
L fetch();
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
} else {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint8 displacement = fetch();
uint16 absolute = PC + (int8)displacement;
idle6(absolute);
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
L idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
aa(PC) = absolute;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionBRL() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 displacement = fetch();
hi(displacement) = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
L idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
aa(PC) = PC + (int16)displacement;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJMPShort() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = fetch();
L hi(data) = fetch();
aa(PC) = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJMPLong() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 data = fetch();
hi(data) = fetch();
L db(data) = fetch();
PC = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJMPIndirect() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = fetch();
hi(absolute) = fetch();
uint16 data = read(uint16(absolute + 0));
L hi(data) = read(uint16(absolute + 1));
aa(PC) = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJMPIndexedIndirect() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = fetch();
hi(absolute) = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = read(db(PC) << 16 | uint16(absolute + X + 0));
L hi(data) = read(db(PC) << 16 | uint16(absolute + X + 1));
aa(PC) = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJMPIndirectLong() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = fetch();
hi(absolute) = fetch();
uint24 data = read(uint16(absolute + 0));
hi(data) = read(uint16(absolute + 1));
L db(data) = read(uint16(absolute + 2));
PC = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJSRShort() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = fetch();
hi(data) = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
aa(PC)--;
push(hi(PC));
L push(lo(PC));
aa(PC) = data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJSRLong() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 data = fetch();
hi(data) = fetch();
pushN(db(PC));
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
db(data) = fetch();
aa(PC)--;
pushN(hi(PC));
L pushN(lo(PC));
PC = data;
E hi(S) = 0x01;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionJSRIndexedIndirect() -> void {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = fetch();
pushN(hi(PC));
pushN(lo(PC));
hi(absolute) = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = read(db(PC) << 16 | uint16(absolute + X + 0));
L hi(data) = read(db(PC) << 16 | uint16(absolute + X + 1));
aa(PC) = data;
E hi(S) = 0x01;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionRTI() -> void {
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
P = pull();
E XF = 1, MF = 1;
if(XF) hi(X) = 0x00, hi(Y) = 0x00;
lo(PC) = pull();
if(EF) {
L hi(PC) = pull();
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
} else {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
hi(PC) = pull();
L db(PC) = pull();
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionRTS() -> void {
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = pull();
hi(data) = pull();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
L idle();
Update to v102r26 release. byuu says: Changelog: - md/ym2612: initialize DAC sample to center volume [Cydrak] - processor/arm: add accumulate mode extra cycle to mlal [Jonas Quinn] - processor/huc6280: split off algorithms, improve naming of functions - processor/mos6502: split off algorithms - processor/spc700: major revamp of entire core (~50% completed) - processor/wdc65816: fixed several bugs introduced by rewrite For the SPC700, this turns out to be very old code as well, with global object state variables, those annoying `{Boolean,Natural}BitField` types, `under_case` naming conventions, heavily abbreviated function names, etc. I'm working to get the code to be in the same design as the MOS6502, HuC6280, WDC65816 cores, since they're all extremely similar in terms of architectural design (the SPC700 is more of an off-label reimplementation of a 6502 core, but still.) The main thing left is that about 90% of the actual instructions still need to be adapted to not use the internal state (`aa`, `rd`, `dp`, `sp`, `bit` variables.) I wanted to finish this today, but ran out of time before work. I wouldn't suggest too much testing just yet. We should wait until the SPC700 core is finished for that. However, if some does want to and spots regressions, please let me know.
2017-06-16 00:06:17 +00:00
aa(PC) = data;
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
aa(PC)++;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::instructionRTL() -> void {
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 data = pullN();
hi(data) = pullN();
L db(data) = pullN();
PC = data;
aa(PC)++;
E hi(S) = 0x01;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}