2016-06-05 22:10:01 +00:00
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auto GSU::disassembleOpcode(char* output) -> void {
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2010-08-09 13:28:56 +00:00
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*output = 0;
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2016-06-05 22:10:01 +00:00
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switch(regs.sfr.alt2 << 1 | regs.sfr.alt1 << 0) {
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Update to v102r27 release.
byuu says:
Changelog:
- processor/gsu: minor code cleanup
- processor/hg51b: renamed reg(Read,Write) to register(Read,Write)
- processor/lr35902: minor code cleanup
- processor/spc700: completed code cleanup (sans disassembler)
- no longer uses internal global state inside instructions
- processor/spc700: will no longer hang the emulator if stuck in a WAI
(SLEEP) or STP (STOP) instruction
- processor/spc700: fixed bug in handling of OR1 and AND1 instructions
- processor/z80: minor code cleanup
- sfc/dsp: revert to initializing registers to 0x00; save for
ENDX=random(), FLG=0xe0 [Jonas Quinn]
Major testing of the SNES game library would be appreciated, now that
its CPU cores have all been revised.
We know the DSP registers read back as randomized data ... mostly, but
there are apparently internal latches, which we can't emulate with the
current DSP design. So until we know which registers have separate
internal state that actually *is* initialized, I'm going to play it safe
and not break more games.
Thanks again to Jonas Quinn for the continued research into this issue.
EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance
that the game will work. That seems pretty unlikely that the odds of it
working are that low, given hardware testing by others in the past :/ I
thought if worked if `PITCH != 0` before, which would have been way more
likely.
The two remaining CPU cores that need major cleanup efforts are the
LR35902 and ARM cores. Both are very large, complicated, annoying cores
that will probably be better off as full rewrites from scratch. I don't
think I want to delay v103 in trying to accomplish that, however.
So I think it'll be best to focus on allowing the Mega Drive core to not
lock when processors are frozen waiting on a response from other
processors during a save state operation. Then we should be good for a
new release.
2017-06-19 02:07:54 +00:00
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case 0: disassembleALT0(output); break;
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case 1: disassembleALT1(output); break;
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case 2: disassembleALT2(output); break;
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case 3: disassembleALT3(output); break;
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2010-08-09 13:28:56 +00:00
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}
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2016-06-05 22:10:01 +00:00
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uint length = strlen(output);
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2010-08-09 13:28:56 +00:00
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while(length++ < 20) strcat(output, " ");
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}
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#define case4(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3
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#define case6(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5
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#define case12(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11
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#define case15(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14
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#define case16(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
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#define op0 regs.pipeline
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2016-06-05 22:10:01 +00:00
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#define op1 read((regs.pbr << 16) + regs.r[15] + 0)
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#define op2 read((regs.pbr << 16) + regs.r[15] + 1)
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2010-08-09 13:28:56 +00:00
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|
Update to v102r27 release.
byuu says:
Changelog:
- processor/gsu: minor code cleanup
- processor/hg51b: renamed reg(Read,Write) to register(Read,Write)
- processor/lr35902: minor code cleanup
- processor/spc700: completed code cleanup (sans disassembler)
- no longer uses internal global state inside instructions
- processor/spc700: will no longer hang the emulator if stuck in a WAI
(SLEEP) or STP (STOP) instruction
- processor/spc700: fixed bug in handling of OR1 and AND1 instructions
- processor/z80: minor code cleanup
- sfc/dsp: revert to initializing registers to 0x00; save for
ENDX=random(), FLG=0xe0 [Jonas Quinn]
Major testing of the SNES game library would be appreciated, now that
its CPU cores have all been revised.
We know the DSP registers read back as randomized data ... mostly, but
there are apparently internal latches, which we can't emulate with the
current DSP design. So until we know which registers have separate
internal state that actually *is* initialized, I'm going to play it safe
and not break more games.
Thanks again to Jonas Quinn for the continued research into this issue.
EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance
that the game will work. That seems pretty unlikely that the odds of it
working are that low, given hardware testing by others in the past :/ I
thought if worked if `PITCH != 0` before, which would have been way more
likely.
The two remaining CPU cores that need major cleanup efforts are the
LR35902 and ARM cores. Both are very large, complicated, annoying cores
that will probably be better off as full rewrites from scratch. I don't
think I want to delay v103 in trying to accomplish that, however.
So I think it'll be best to focus on allowing the Mega Drive core to not
lock when processors are frozen waiting on a response from other
processors during a save state operation. Then we should be good for a
new release.
2017-06-19 02:07:54 +00:00
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auto GSU::disassembleALT0(char* output) -> void {
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2010-08-09 13:28:56 +00:00
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "plot"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "color"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "add r%u", op0 & 15); break;
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case16(0x60): sprintf(t, "sub r%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "and r%u", op0 & 15); break;
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case16(0x80): sprintf(t, "mult r%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "asr"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "fmult"); break;
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case16(0xa0): sprintf(t, "ibt r%u,#$%.2x", op0 & 15, op1); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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2013-12-10 12:12:54 +00:00
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case (0xc0): sprintf(t, "hib"); break;
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2010-08-09 13:28:56 +00:00
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case15(0xc1): sprintf(t, "or r%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "getc"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getb"); break;
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case16(0xf0): sprintf(t, "iwt r%u,#$%.2x%.2x", op0 & 15, op2, op1); break;
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}
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strcat(output, t);
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}
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|
Update to v102r27 release.
byuu says:
Changelog:
- processor/gsu: minor code cleanup
- processor/hg51b: renamed reg(Read,Write) to register(Read,Write)
- processor/lr35902: minor code cleanup
- processor/spc700: completed code cleanup (sans disassembler)
- no longer uses internal global state inside instructions
- processor/spc700: will no longer hang the emulator if stuck in a WAI
(SLEEP) or STP (STOP) instruction
- processor/spc700: fixed bug in handling of OR1 and AND1 instructions
- processor/z80: minor code cleanup
- sfc/dsp: revert to initializing registers to 0x00; save for
ENDX=random(), FLG=0xe0 [Jonas Quinn]
Major testing of the SNES game library would be appreciated, now that
its CPU cores have all been revised.
We know the DSP registers read back as randomized data ... mostly, but
there are apparently internal latches, which we can't emulate with the
current DSP design. So until we know which registers have separate
internal state that actually *is* initialized, I'm going to play it safe
and not break more games.
Thanks again to Jonas Quinn for the continued research into this issue.
EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance
that the game will work. That seems pretty unlikely that the odds of it
working are that low, given hardware testing by others in the past :/ I
thought if worked if `PITCH != 0` before, which would have been way more
likely.
The two remaining CPU cores that need major cleanup efforts are the
LR35902 and ARM cores. Both are very large, complicated, annoying cores
that will probably be better off as full rewrites from scratch. I don't
think I want to delay v103 in trying to accomplish that, however.
So I think it'll be best to focus on allowing the Mega Drive core to not
lock when processors are frozen waiting on a response from other
processors during a save state operation. Then we should be good for a
new release.
2017-06-19 02:07:54 +00:00
|
|
|
auto GSU::disassembleALT1(char* output) -> void {
|
2010-08-09 13:28:56 +00:00
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "rpix"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "cmode"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "adc r%u", op0 & 15); break;
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case16(0x60): sprintf(t, "sbc r%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "bic r%u", op0 & 15); break;
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case16(0x80): sprintf(t, "umult r%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "div2"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "lmult"); break;
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case16(0xa0): sprintf(t, "lms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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case (0xc0): sprintf(t, "hib"); break;
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case15(0xc1): sprintf(t, "xor r%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "getc"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getbh"); break;
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case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
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}
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|
|
|
|
strcat(output, t);
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|
|
|
|
}
|
|
|
|
|
|
Update to v102r27 release.
byuu says:
Changelog:
- processor/gsu: minor code cleanup
- processor/hg51b: renamed reg(Read,Write) to register(Read,Write)
- processor/lr35902: minor code cleanup
- processor/spc700: completed code cleanup (sans disassembler)
- no longer uses internal global state inside instructions
- processor/spc700: will no longer hang the emulator if stuck in a WAI
(SLEEP) or STP (STOP) instruction
- processor/spc700: fixed bug in handling of OR1 and AND1 instructions
- processor/z80: minor code cleanup
- sfc/dsp: revert to initializing registers to 0x00; save for
ENDX=random(), FLG=0xe0 [Jonas Quinn]
Major testing of the SNES game library would be appreciated, now that
its CPU cores have all been revised.
We know the DSP registers read back as randomized data ... mostly, but
there are apparently internal latches, which we can't emulate with the
current DSP design. So until we know which registers have separate
internal state that actually *is* initialized, I'm going to play it safe
and not break more games.
Thanks again to Jonas Quinn for the continued research into this issue.
EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance
that the game will work. That seems pretty unlikely that the odds of it
working are that low, given hardware testing by others in the past :/ I
thought if worked if `PITCH != 0` before, which would have been way more
likely.
The two remaining CPU cores that need major cleanup efforts are the
LR35902 and ARM cores. Both are very large, complicated, annoying cores
that will probably be better off as full rewrites from scratch. I don't
think I want to delay v103 in trying to accomplish that, however.
So I think it'll be best to focus on allowing the Mega Drive core to not
lock when processors are frozen waiting on a response from other
processors during a save state operation. Then we should be good for a
new release.
2017-06-19 02:07:54 +00:00
|
|
|
auto GSU::disassembleALT2(char* output) -> void {
|
2010-08-09 13:28:56 +00:00
|
|
|
char t[256] = "";
|
|
|
|
|
switch(op0) {
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|
|
|
|
case (0x00): sprintf(t, "stop"); break;
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|
case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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|
case (0x03): sprintf(t, "lsr"); break;
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|
case (0x04): sprintf(t, "rol"); break;
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|
case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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|
case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
|
|
|
|
|
case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
|
|
|
|
|
case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
|
|
|
|
|
case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
|
|
|
|
|
case (0x3c): sprintf(t, "loop"); break;
|
|
|
|
|
case (0x3d): sprintf(t, "alt1"); break;
|
|
|
|
|
case (0x3e): sprintf(t, "alt2"); break;
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|
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|
case (0x3f): sprintf(t, "alt3"); break;
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|
|
|
|
case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
|
|
|
|
|
case (0x4c): sprintf(t, "plot"); break;
|
|
|
|
|
case (0x4d): sprintf(t, "swap"); break;
|
|
|
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|
case (0x4e): sprintf(t, "color"); break;
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|
|
|
|
case (0x4f): sprintf(t, "not"); break;
|
|
|
|
|
case16(0x50): sprintf(t, "add #%u", op0 & 15); break;
|
|
|
|
|
case16(0x60): sprintf(t, "sub #%u", op0 & 15); break;
|
|
|
|
|
case (0x70): sprintf(t, "merge"); break;
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|
|
|
|
case15(0x71): sprintf(t, "and #%u", op0 & 15); break;
|
|
|
|
|
case16(0x80): sprintf(t, "mult #%u", op0 & 15); break;
|
|
|
|
|
case (0x90): sprintf(t, "sbk"); break;
|
|
|
|
|
case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
|
|
|
|
|
case (0x95): sprintf(t, "sex"); break;
|
|
|
|
|
case (0x96): sprintf(t, "asr"); break;
|
|
|
|
|
case (0x97): sprintf(t, "ror"); break;
|
|
|
|
|
case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
|
|
|
|
|
case (0x9e): sprintf(t, "lob"); break;
|
|
|
|
|
case (0x9f): sprintf(t, "fmult"); break;
|
|
|
|
|
case16(0xa0): sprintf(t, "sms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
|
|
|
|
|
case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
|
|
|
|
|
case (0xc0): sprintf(t, "hib"); break;
|
|
|
|
|
case15(0xc1): sprintf(t, "or #%u", op0 & 15); break;
|
|
|
|
|
case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
|
|
|
|
|
case (0xdf): sprintf(t, "ramb"); break;
|
|
|
|
|
case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
|
|
|
|
|
case (0xef): sprintf(t, "getbl"); break;
|
|
|
|
|
case16(0xf0): sprintf(t, "sm r%u", op0 & 15); break;
|
|
|
|
|
}
|
|
|
|
|
strcat(output, t);
|
|
|
|
|
}
|
|
|
|
|
|
Update to v102r27 release.
byuu says:
Changelog:
- processor/gsu: minor code cleanup
- processor/hg51b: renamed reg(Read,Write) to register(Read,Write)
- processor/lr35902: minor code cleanup
- processor/spc700: completed code cleanup (sans disassembler)
- no longer uses internal global state inside instructions
- processor/spc700: will no longer hang the emulator if stuck in a WAI
(SLEEP) or STP (STOP) instruction
- processor/spc700: fixed bug in handling of OR1 and AND1 instructions
- processor/z80: minor code cleanup
- sfc/dsp: revert to initializing registers to 0x00; save for
ENDX=random(), FLG=0xe0 [Jonas Quinn]
Major testing of the SNES game library would be appreciated, now that
its CPU cores have all been revised.
We know the DSP registers read back as randomized data ... mostly, but
there are apparently internal latches, which we can't emulate with the
current DSP design. So until we know which registers have separate
internal state that actually *is* initialized, I'm going to play it safe
and not break more games.
Thanks again to Jonas Quinn for the continued research into this issue.
EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance
that the game will work. That seems pretty unlikely that the odds of it
working are that low, given hardware testing by others in the past :/ I
thought if worked if `PITCH != 0` before, which would have been way more
likely.
The two remaining CPU cores that need major cleanup efforts are the
LR35902 and ARM cores. Both are very large, complicated, annoying cores
that will probably be better off as full rewrites from scratch. I don't
think I want to delay v103 in trying to accomplish that, however.
So I think it'll be best to focus on allowing the Mega Drive core to not
lock when processors are frozen waiting on a response from other
processors during a save state operation. Then we should be good for a
new release.
2017-06-19 02:07:54 +00:00
|
|
|
auto GSU::disassembleALT3(char* output) -> void {
|
2010-08-09 13:28:56 +00:00
|
|
|
char t[256] = "";
|
|
|
|
|
switch(op0) {
|
|
|
|
|
case (0x00): sprintf(t, "stop"); break;
|
|
|
|
|
case (0x01): sprintf(t, "nop"); break;
|
|
|
|
|
case (0x02): sprintf(t, "cache"); break;
|
|
|
|
|
case (0x03): sprintf(t, "lsr"); break;
|
|
|
|
|
case (0x04): sprintf(t, "rol"); break;
|
|
|
|
|
case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
|
|
|
|
|
case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
|
|
|
|
|
case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
|
|
|
|
|
case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
|
|
|
|
|
case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
|
|
|
|
|
case (0x3c): sprintf(t, "loop"); break;
|
|
|
|
|
case (0x3d): sprintf(t, "alt1"); break;
|
|
|
|
|
case (0x3e): sprintf(t, "alt2"); break;
|
|
|
|
|
case (0x3f): sprintf(t, "alt3"); break;
|
|
|
|
|
case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
|
|
|
|
|
case (0x4c): sprintf(t, "rpix"); break;
|
|
|
|
|
case (0x4d): sprintf(t, "swap"); break;
|
|
|
|
|
case (0x4e): sprintf(t, "cmode"); break;
|
|
|
|
|
case (0x4f): sprintf(t, "not"); break;
|
|
|
|
|
case16(0x50): sprintf(t, "adc #%u", op0 & 15); break;
|
|
|
|
|
case16(0x60): sprintf(t, "cmp r%u", op0 & 15); break;
|
|
|
|
|
case (0x70): sprintf(t, "merge"); break;
|
|
|
|
|
case15(0x71): sprintf(t, "bic #%u", op0 & 15); break;
|
|
|
|
|
case16(0x80): sprintf(t, "umult #%u", op0 & 15); break;
|
|
|
|
|
case (0x90): sprintf(t, "sbk"); break;
|
|
|
|
|
case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
|
|
|
|
|
case (0x95): sprintf(t, "sex"); break;
|
|
|
|
|
case (0x96): sprintf(t, "div2"); break;
|
|
|
|
|
case (0x97): sprintf(t, "ror"); break;
|
|
|
|
|
case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
|
|
|
|
|
case (0x9e): sprintf(t, "lob"); break;
|
|
|
|
|
case (0x9f): sprintf(t, "lmult"); break;
|
|
|
|
|
case16(0xa0): sprintf(t, "lms r%u", op0 & 15); break;
|
|
|
|
|
case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
|
|
|
|
|
case (0xc0): sprintf(t, "hib"); break;
|
|
|
|
|
case15(0xc1): sprintf(t, "xor #%u", op0 & 15); break;
|
|
|
|
|
case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
|
|
|
|
|
case (0xdf): sprintf(t, "romb"); break;
|
|
|
|
|
case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
|
|
|
|
|
case (0xef): sprintf(t, "getbs"); break;
|
|
|
|
|
case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
|
|
|
|
|
}
|
|
|
|
|
strcat(output, t);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef case4
|
|
|
|
|
#undef case6
|
|
|
|
|
#undef case12
|
|
|
|
|
#undef case15
|
|
|
|
|
#undef case16
|
|
|
|
|
#undef op0
|
|
|
|
|
#undef op1
|
|
|
|
|
#undef op2
|