Update to v101r14 release.
byuu says:
Changelog:
- rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY)
prefixes
- added Processor::Z80::Bus as a new type of abstraction
- all of the instructions implemented have their proper T-cycle counts
now
- added nall/certificates for my public keys
The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being
2-read + 2-wait states; operand+regular reads/writes being 3-read. For
now, this puts the cycle counts inside the CPU core. At the moment, I
can't think of any CPU core where this wouldn't be appropriate. But it's
certainly possible that such a case exists. So this may not be the
perfect solution.
The reason for having it be a subclass of Processor::Z80 instead of
virtual functions for the MasterSystem::CPU core to define is due to
naming conflicts. I wanted the core to say `in(addr)` and have it take
the four clocks. But I also wanted a version of the function that didn't
consume time when called. One way to do that would be for the core to
call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to
`MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::`
prefix on all of the opcodes. Very easy to forget it, and then end up not
consuming any time. Another is to use uglier names in the
`MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But,
yuck.
So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
|
|
|
-----BEGIN CERTIFICATE-----
|
2016-09-14 11:55:53 +00:00
|
|
|
MIIB6jCCAXCgAwIBAgIJAOrEeJHQ9mpoMAoGCCqGSM49BAMDMB4xDTALBgNVBAMM
|
|
|
|
|
BGJ5dXUxDTALBgNVBAoMBGJ5dXUwIBcNMTYwOTExMTM1MzU1WhgPMjA5MTA4MjQx
|
|
|
|
|
MzUzNTVaMCIxETAPBgNVBAMMCGJ5dXUub3JnMQ0wCwYDVQQKDARieXV1MHYwEAYH
|
|
|
|
|
KoZIzj0CAQYFK4EEACIDYgAEH+ny1an5De9P1TJ0vmpGlpmrZszuV1lKTPut28Vx
|
|
|
|
|
98ieuBdmSNG493sJ+ga+adXPtItkck5M0jITR1NxcWvVlZtJG8L6ctEuVF6smkoy
|
|
|
|
|
1dbxzEeTIs+xjRQqaLN4U67ho3QwcjAMBgNVHRMBAf8EAjAAMCIGA1UdEQEB/wQY
|
|
|
|
|
MBaCCGJ5dXUub3JnggoqLmJ5dXUub3JnMB0GA1UdDgQWBBRhhKSsc+qUaBUNiyJX
|
|
|
|
|
j17UDBFuuTAfBgNVHSMEGDAWgBSg+5hBev25rcTlErtORNImI0QqyTAKBggqhkjO
|
|
|
|
|
PQQDAwNoADBlAjEApEbI/wT/cU7DRFvBEmfFMtVDJCJCTz4UEo1lJI9SPOEtgX3x
|
|
|
|
|
gJZg4deqeoAEffVGAjB2RWI1UPi/jnpJwTsuw4sp5UqFhY48qfqddPiSO4qlmb8s
|
|
|
|
|
1aEdP6gHoji22pHrKbY=
|
Update to v101r14 release.
byuu says:
Changelog:
- rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY)
prefixes
- added Processor::Z80::Bus as a new type of abstraction
- all of the instructions implemented have their proper T-cycle counts
now
- added nall/certificates for my public keys
The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being
2-read + 2-wait states; operand+regular reads/writes being 3-read. For
now, this puts the cycle counts inside the CPU core. At the moment, I
can't think of any CPU core where this wouldn't be appropriate. But it's
certainly possible that such a case exists. So this may not be the
perfect solution.
The reason for having it be a subclass of Processor::Z80 instead of
virtual functions for the MasterSystem::CPU core to define is due to
naming conflicts. I wanted the core to say `in(addr)` and have it take
the four clocks. But I also wanted a version of the function that didn't
consume time when called. One way to do that would be for the core to
call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to
`MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::`
prefix on all of the opcodes. Very easy to forget it, and then end up not
consuming any time. Another is to use uglier names in the
`MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But,
yuck.
So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
|
|
|
-----END CERTIFICATE-----
|