bsnes/nall/inline-if.hpp

#pragma once
#warning "these defines break if statements with multiple parameters to templates"

#define if1(statement) if(statement)
#define if2(condition, false) ([&](auto&& value) -> decltype(condition) { \
  return (bool)value ? value : (decltype(condition))false; \
})(condition)
#define if3(condition, true, false) ((condition) ? (true) : (decltype(true))(false))
#define if4(type, condition, true, false) ((condition) ? (type)(true) : (type)(false))
#define if_(_1, _2, _3, _4, name, ...) name
#define if(...) if_(__VA_ARGS__, if4, if3, if2, if1)(__VA_ARGS__)
Update to v106r78 release. byuu says: I've implemented a lot more TLCS900H instructions. There are currently 20 missing spots, all of which are unique instructions (well, MINC and MDEC could be considered pairs of 3 each), from a map of 1024 slots. After that, I have to write the disassembler. Then the memory bus. Then I get to start the fun process of debugging this monstrosity. Also new is nall/inline-if.hpp. Note that this file is technically a war crime, so be careful when opening it. This replaces ternary() from the previous WIP. 2019-01-14 06:16:28 +00:00			`#pragma once`
Update to v106r83 release. byuu says: Changelog: - reverted nall/inline-if.hpp usage for now, since the nall/primitives.hpp math operators still cast to (u)int64_t - improved nall/primitives.hpp more; integer8 x = -128; print(-x) will now print 128 (unary operator+ and - cast to (u)int64_t) - renamed processor/lr35902 to processor/sm83; after the Sharp SM83 CPU core [gekkio discovered the name] - a few bugfixes to the TLCS900H CPU core - completed the disassembler for the TLCS900H core As a result of reverting most of the inline if stuff, I guess the testing priority has been reduced. Which is probably a good thing, considering I seem to have a smaller pool of testers these days. Indeed, the TLCS900H core has ended up at 131KiB compared to the M68000 core at 128KiB. So it's now the largest CPU core in all of higan. It's even more ridiculous because the M68000 core would ordinarily be quite a bit smaller, had I not gone overboard with the extreme templating to reduce instruction decoding overhead (you kind of have to do this for RISC CPUs, and the inverted design of the TLCS900H kind of makes it infeasible to do the same there.) This CPU core is bound to have dozens of extremely difficult CPU bugs, and there's no easy way for me to test them. I would greatly appreciate any help in looking over the core for bugs. A fresh pair of eyes to spot a mistake could save me up to several days of tedious debugging work. The core still isn't ready to actually be tested: I have to hook up cartridge loading, a memory bus, interrupts, timers, and the micro DMA controller before it's likely that anything happens at all. 2019-01-19 01:34:17 +00:00			`#warning "these defines break if statements with multiple parameters to templates"`
Update to v106r78 release. byuu says: I've implemented a lot more TLCS900H instructions. There are currently 20 missing spots, all of which are unique instructions (well, MINC and MDEC could be considered pairs of 3 each), from a map of 1024 slots. After that, I have to write the disassembler. Then the memory bus. Then I get to start the fun process of debugging this monstrosity. Also new is nall/inline-if.hpp. Note that this file is technically a war crime, so be careful when opening it. This replaces ternary() from the previous WIP. 2019-01-14 06:16:28 +00:00
			`#define if1(statement) if(statement)`
Update to v106r84 release. byuu says: Changelog: - fixed a few TLCS900H CPU and disassembler bugs - hooked up a basic Neo Geo Pocket emulator skeleton and memory map; can run a few instructions from the BIOS - emulated the flash memory used by Neo Geo Pocket games - added sourcery to the higan source archives - fixed ternary expressions in sfc/ppu-fast [hex_usr] 2019-01-21 05:27:24 +00:00			`#define if2(condition, false) ([&](auto&& value) -> decltype(condition) { \`
Update to v106r78 release. byuu says: I've implemented a lot more TLCS900H instructions. There are currently 20 missing spots, all of which are unique instructions (well, MINC and MDEC could be considered pairs of 3 each), from a map of 1024 slots. After that, I have to write the disassembler. Then the memory bus. Then I get to start the fun process of debugging this monstrosity. Also new is nall/inline-if.hpp. Note that this file is technically a war crime, so be careful when opening it. This replaces ternary() from the previous WIP. 2019-01-14 06:16:28 +00:00			`return (bool)value ? value : (decltype(condition))false; \`
			`})(condition)`
			`#define if3(condition, true, false) ((condition) ? (true) : (decltype(true))(false))`
			`#define if4(type, condition, true, false) ((condition) ? (type)(true) : (type)(false))`
			`#define if_(_1, _2, _3, _4, name, ...) name`
			`#define if(...) if_(__VA_ARGS__, if4, if3, if2, if1)(__VA_ARGS__)`