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bsnes/higan/processor/wdc65816/instructions-read.cpp

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Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionImmediateRead8(alu8 op) -> void {
L uint8 data = fetch();
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionImmediateRead16(alu16 op) -> void {
uint16 data = fetch();
L hi(data) = fetch();
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionBankRead8(alu8 op) -> void {
uint16 absolute = fetch();
hi(absolute) = fetch();
L uint8 data = readBank(absolute);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionBankRead16(alu16 op) -> void {
uint16 absolute = fetch();
hi(absolute) = fetch();
uint16 data = readBank(absolute + 0);
L hi(data) = readBank(absolute + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionBankRead8(alu8 op, uint16 index) -> void {
uint16 absolute = fetch();
hi(absolute) = fetch();
idle4(absolute, absolute + index);
L uint8 data = readBank(absolute + index);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionBankRead16(alu16 op, uint16 index) -> void {
uint16 absolute = fetch();
hi(absolute) = fetch();
idle4(absolute, absolute + index);
uint16 data = readBank(absolute + index + 0);
L hi(data) = readBank(absolute + index + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionLongRead8(alu8 op, uint16 index) -> void {
uint24 address = fetch();
hi(address) = fetch();
db(address) = fetch();
L uint8 data = read(address + index);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionLongRead16(alu16 op, uint16 index) -> void {
uint24 address = fetch();
hi(address) = fetch();
db(address) = fetch();
uint16 data = read(address + index + 0);
L hi(data) = read(address + index + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionDirectRead8(alu8 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
L uint8 data = readDirect(direct);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionDirectRead16(alu16 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = readDirect(direct + 0);
L hi(data) = readDirect(direct + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionDirectRead8(alu8 op, uint16 index) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
L uint8 data = readDirect(direct + index);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionDirectRead16(alu16 op, uint16 index) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = readDirect(direct + index + 0);
L hi(data) = readDirect(direct + index + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectRead8(alu8 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + 0);
hi(absolute) = readDirect(direct + 1);
L uint8 data = readBank(absolute);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectRead16(alu16 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + 0);
hi(absolute) = readDirect(direct + 1);
uint16 data = readBank(absolute + 0);
L hi(data) = readBank(absolute + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndexedIndirectRead8(alu8 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + X + 0);
hi(absolute) = readDirect(direct + X + 1);
L uint8 data = readBank(absolute);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndexedIndirectRead16(alu16 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + X + 0);
hi(absolute) = readDirect(direct + X + 1);
uint16 data = readBank(absolute + 0);
L hi(data) = readBank(absolute + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectIndexedRead8(alu8 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + 0);
hi(absolute) = readDirect(direct + 1);
idle4(absolute, absolute + Y);
L uint8 data = readBank(absolute + Y);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectIndexedRead16(alu16 op) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readDirect(direct + 0);
hi(absolute) = readDirect(direct + 1);
idle4(absolute, absolute + Y);
uint16 data = readBank(absolute + Y + 0);
L hi(data) = readBank(absolute + Y + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectLongRead8(alu8 op, uint16 index) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 address = readDirectN(direct + 0);
hi(address) = readDirectN(direct + 1);
db(address) = readDirectN(direct + 2);
L uint8 data = read(address + index);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectLongRead16(alu16 op, uint16 index) -> void {
uint8 direct = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle2();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 address = readDirectN(direct + 0);
hi(address) = readDirectN(direct + 1);
db(address) = readDirectN(direct + 2);
uint16 data = read(address + index + 0);
L hi(data) = read(address + index + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionStackRead8(alu8 op) -> void {
uint8 stack = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
L uint8 data = readStack(stack);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionStackRead16(alu16 op) -> void {
uint8 stack = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = readStack(stack + 0);
L hi(data) = readStack(stack + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectStackRead8(alu8 op) -> void {
uint8 stack = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readStack(stack + 0);
hi(absolute) = readStack(stack + 1);
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
L uint8 data = readBank(absolute + Y);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
auto WDC65816::instructionIndirectStackRead16(alu16 op) -> void {
uint8 stack = fetch();
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 absolute = readStack(stack + 0);
hi(absolute) = readStack(stack + 1);
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
idle();
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint16 data = readBank(absolute + Y + 0);
L hi(data) = readBank(absolute + Y + 1);
alu(data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}