bsnes/higan/processor/arm7tdmi/serialization.cpp

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auto ARM7TDMI::serialize(serializer& s) -> void {
processor.serialize(s);
pipeline.serialize(s);
s.boolean(carry);
s.boolean(irq);
}
auto ARM7TDMI::Processor::serialize(serializer& s) -> void {
s.integer(r0.data);
s.integer(r1.data);
s.integer(r2.data);
s.integer(r3.data);
s.integer(r4.data);
s.integer(r5.data);
s.integer(r6.data);
s.integer(r7.data);
s.integer(r8.data);
s.integer(r9.data);
s.integer(r10.data);
s.integer(r11.data);
s.integer(r12.data);
s.integer(r13.data);
s.integer(r14.data);
s.integer(r15.data);
cpsr.serialize(s);
s.integer(fiq.r8.data);
s.integer(fiq.r9.data);
s.integer(fiq.r10.data);
s.integer(fiq.r11.data);
s.integer(fiq.r12.data);
s.integer(fiq.r13.data);
s.integer(fiq.r14.data);
fiq.spsr.serialize(s);
s.integer(irq.r13.data);
s.integer(irq.r14.data);
irq.spsr.serialize(s);
s.integer(svc.r13.data);
s.integer(svc.r14.data);
svc.spsr.serialize(s);
s.integer(abt.r13.data);
s.integer(abt.r14.data);
abt.spsr.serialize(s);
s.integer(und.r13.data);
s.integer(und.r14.data);
und.spsr.serialize(s);
}
auto ARM7TDMI::PSR::serialize(serializer& s) -> void {
s.integer(m);
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
s.boolean(t);
s.boolean(f);
s.boolean(i);
s.boolean(v);
s.boolean(c);
s.boolean(z);
s.boolean(n);
}
auto ARM7TDMI::Pipeline::serialize(serializer& s) -> void {
s.integer(reload);
s.integer(nonsequential);
s.integer(fetch.address);
s.integer(fetch.instruction);
s.boolean(fetch.thumb);
s.integer(decode.address);
s.integer(decode.instruction);
s.boolean(decode.thumb);
s.integer(execute.address);
s.integer(execute.instruction);
s.boolean(execute.thumb);
}