bsnes/higan/processor/mos6502/mos6502.hpp

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//MOS Technologies MOS6502
#pragma once
namespace Processor {
struct MOS6502 {
virtual auto read(uint16 addr) -> uint8 = 0;
virtual auto write(uint16 addr, uint8 data) -> void = 0;
virtual auto lastCycle() -> void = 0;
virtual auto nmi(uint16& vector) -> void = 0;
virtual auto readDebugger(uint16 addr) -> uint8 { return 0; }
//mos6502.cpp
auto mdr() const -> uint8;
auto power() -> void;
//memory.cpp
auto idle() -> void;
auto idlePageCrossed(uint16, uint16) -> void;
auto idlePageAlways(uint16, uint16) -> void;
auto opcode() -> uint8;
auto operand() -> uint8;
auto load(uint8 addr) -> uint8;
auto store(uint8 addr, uint8 data) -> void;
auto push(uint8 data) -> void;
auto pull() -> uint8;
//instruction.cpp
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto interrupt() -> void;
auto instruction() -> void;
//instructions.cpp
using fp = auto (MOS6502::*)(uint8) -> uint8;
auto ADC(uint8) -> uint8;
auto AND(uint8) -> uint8;
auto ASL(uint8) -> uint8;
auto BIT(uint8) -> uint8;
auto CMP(uint8) -> uint8;
auto CPX(uint8) -> uint8;
auto CPY(uint8) -> uint8;
auto DEC(uint8) -> uint8;
auto EOR(uint8) -> uint8;
auto INC(uint8) -> uint8;
auto LD (uint8) -> uint8;
auto LSR(uint8) -> uint8;
auto ORA(uint8) -> uint8;
auto ROL(uint8) -> uint8;
auto ROR(uint8) -> uint8;
auto SBC(uint8) -> uint8;
auto instructionAbsoluteModify(fp alu) -> void;
auto instructionAbsoluteModify(fp alu, uint8 index) -> void;
auto instructionAbsoluteRead(fp alu, uint8& data) -> void;
auto instructionAbsoluteRead(fp alu, uint8& data, uint8 index) -> void;
auto instructionAbsoluteWrite(uint8& data) -> void;
auto instructionAbsoluteWrite(uint8& data, uint8 index) -> void;
auto instructionBranch(bool take) -> void;
auto instructionClear(bool& flag) -> void;
auto instructionImmediate(fp alu, uint8& data) -> void;
auto instructionImplied(fp alu, uint8& data) -> void;
auto instructionIndirectXRead(fp alu, uint8& data) -> void;
auto instructionIndirectXWrite(uint8& data) -> void;
auto instructionIndirectYRead(fp alu, uint8& data) -> void;
auto instructionIndirectYWrite(uint8& data) -> void;
auto instructionPull(uint8& data) -> void;
auto instructionPush(uint8& data) -> void;
auto instructionSet(bool& flag) -> void;
auto instructionTransfer(uint8& source, uint8& target, bool flag) -> void;
auto instructionZeroPageModify(fp alu) -> void;
auto instructionZeroPageModify(fp alu, uint8 index) -> void;
auto instructionZeroPageRead(fp alu, uint8& data) -> void;
auto instructionZeroPageRead(fp alu, uint8& data, uint8 index) -> void;
auto instructionZeroPageWrite(uint8& data) -> void;
auto instructionZeroPageWrite(uint8& data, uint8 index) -> void;
auto instructionBRK() -> void;
auto instructionJMPAbsolute() -> void;
auto instructionJMPIndirect() -> void;
auto instructionJSRAbsolute() -> void;
auto instructionNOP() -> void;
auto instructionPHP() -> void;
auto instructionPLP() -> void;
auto instructionRTI() -> void;
auto instructionRTS() -> void;
//serialization.cpp
auto serialize(serializer&) -> void;
//disassembler.cpp
auto disassemble(uint16 pc) -> string;
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//set to false to disable BCD mode in ADC, SBC instructions
bool BCD = true;
struct Flags {
bool c; //carry
bool z; //zero
bool i; //interrupt disable
bool d; //decimal mode
bool v; //overflow
bool n; //negative
inline operator uint() const {
return c << 0 | z << 1 | i << 2 | d << 3 | v << 6 | n << 7;
}
inline auto& operator=(uint8 data) {
c = data.bit(0);
z = data.bit(1);
i = data.bit(2);
d = data.bit(3);
v = data.bit(6);
n = data.bit(7);
return *this;
}
};
struct Registers {
uint8 a;
uint8 x;
uint8 y;
uint8 s;
uint16 pc;
Flags p;
uint8 mdr;
} r;
};
}