bsnes/higan/gba/apu/io.cpp

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Update to v099r13 release. byuu says: Changelog: - GB core code cleanup completed - GBA core code cleanup completed - some more cleanup on missed processor/arm functions/variables - fixed FC loading icarus bug - "Load ROM File" icarus functionality restored - minor code unification efforts all around (not perfect yet) - MMIO->IO - mmio.cpp->io.cpp - read,write->readIO,writeIO It's been a very long work in progress ... starting all the way back with v094r09, but the major part of the higan code cleanup is now completed! Of course, it's very important to note that this is only for the basic style: - under_score functions and variables are now camelCase - return-type function-name() are now auto function-name() -> return-type - Natural<T>/Integer<T> replace (u)intT_n types where possible - signed/unsigned are now int/uint - most of the x==true,x==false tests changed to x,!x A lot of spot improvements to consistency, simplicity and quality have gone in along the way, of course. But we'll probably never fully finishing beautifying every last line of code in the entire codebase. Still, this is a really great start. Going forward, WIP diffs should start being smaller and of higher quality once again. I know the joke is, "until my coding style changes again", but ... this was way too stressful, way too time consuming, and way too risky. I'm too old and tired now for extreme upheavel like this again. The only major change I'm slowly mulling over would be renaming the using Natural<T>/Integer<T> = (u)intT; shorthand to something that isn't as easily confused with the (u)int_t types ... but we'll see. I'll definitely continue to change small things all the time, but for the larger picture, I need to just accept the style I have and live with it.
2016-06-29 11:10:28 +00:00
auto APU::readIO(uint32 addr) -> uint8 {
switch(addr) {
//NR10
case 0x0400'0060: return square1.read(0);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
case 0x0400'0061: return 0x00;
//NR11, NR12
case 0x0400'0062: return square1.read(1);
case 0x0400'0063: return square1.read(2);
//NR13, NR14
case 0x0400'0064: return square1.read(3);
case 0x0400'0065: return square1.read(4);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'0066: return 0x00;
case 0x0400'0067: return 0x00;
//NR21, NR22
case 0x0400'0068: return square2.read(1);
case 0x0400'0069: return square2.read(2);
//NR23, NR24
case 0x0400'006c: return square2.read(3);
case 0x0400'006d: return square2.read(4);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'006e: return 0x00;
case 0x0400'006f: return 0x00;
//NR30
case 0x0400'0070: return wave.read(0);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
case 0x0400'0071: return 0x00;
//NR31, NR32
case 0x0400'0072: return wave.read(1);
case 0x0400'0073: return wave.read(2);
//NR33, NR34
case 0x0400'0074: return wave.read(3);
case 0x0400'0075: return wave.read(4);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'0076: return 0x00;
case 0x0400'0077: return 0x00;
//NR41, NR42
case 0x0400'0078: return noise.read(1);
case 0x0400'0079: return noise.read(2);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'007a: return 0x00;
case 0x0400'007b: return 0x00;
//NR43, NR44
case 0x0400'007c: return noise.read(3);
case 0x0400'007d: return noise.read(4);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'007e: return 0x00;
case 0x0400'007f: return 0x00;
//NR50, NR51
case 0x0400'0080: return sequencer.read(0);
case 0x0400'0081: return sequencer.read(1);
//SOUND_CNT_H
case 0x0400'0082: return (
sequencer.volume << 0
| fifo[0].volume << 2
| fifo[1].volume << 3
);
case 0x0400'0083: return (
fifo[0].renable << 0
| fifo[0].lenable << 1
| fifo[0].timer << 2
| fifo[1].renable << 4
| fifo[1].lenable << 5
| fifo[1].timer << 6
);
//NR52
case 0x0400'0084: return sequencer.read(2);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
case 0x0400'0085: return 0x00;
//zero
case 0x0400'0086: return 0x00;
case 0x0400'0087: return 0x00;
//SOUNDBIAS
case 0x0400'0088: return (
regs.bias.level.bits(0,7)
);
case 0x0400'0089: return (
regs.bias.level.bits(8,9) << 0
| regs.bias.amplitude << 6
);
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//zero
case 0x0400'008a: return 0x00;
case 0x0400'008b: return 0x00;
//WAVE_RAM0_L
case 0x0400'0090: return wave.readram( 0);
case 0x0400'0091: return wave.readram( 1);
//WAVE_RAM0_H
case 0x0400'0092: return wave.readram( 2);
case 0x0400'0093: return wave.readram( 3);
//WAVE_RAM1_L
case 0x0400'0094: return wave.readram( 4);
case 0x0400'0095: return wave.readram( 5);
//WAVE_RAM1_H
case 0x0400'0096: return wave.readram( 6);
case 0x0400'0097: return wave.readram( 7);
//WAVE_RAM2_L
case 0x0400'0098: return wave.readram( 8);
case 0x0400'0099: return wave.readram( 9);
//WAVE_RAM2_H
case 0x0400'009a: return wave.readram(10);
case 0x0400'009b: return wave.readram(11);
//WAVE_RAM3_L
case 0x0400'009c: return wave.readram(12);
case 0x0400'009d: return wave.readram(13);
//WAVE_RAM3_H
case 0x0400'009e: return wave.readram(14);
case 0x0400'009f: return wave.readram(15);
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
return cpu.pipeline.fetch.instruction.byte(addr & 1);
}
Update to v099r13 release. byuu says: Changelog: - GB core code cleanup completed - GBA core code cleanup completed - some more cleanup on missed processor/arm functions/variables - fixed FC loading icarus bug - "Load ROM File" icarus functionality restored - minor code unification efforts all around (not perfect yet) - MMIO->IO - mmio.cpp->io.cpp - read,write->readIO,writeIO It's been a very long work in progress ... starting all the way back with v094r09, but the major part of the higan code cleanup is now completed! Of course, it's very important to note that this is only for the basic style: - under_score functions and variables are now camelCase - return-type function-name() are now auto function-name() -> return-type - Natural<T>/Integer<T> replace (u)intT_n types where possible - signed/unsigned are now int/uint - most of the x==true,x==false tests changed to x,!x A lot of spot improvements to consistency, simplicity and quality have gone in along the way, of course. But we'll probably never fully finishing beautifying every last line of code in the entire codebase. Still, this is a really great start. Going forward, WIP diffs should start being smaller and of higher quality once again. I know the joke is, "until my coding style changes again", but ... this was way too stressful, way too time consuming, and way too risky. I'm too old and tired now for extreme upheavel like this again. The only major change I'm slowly mulling over would be renaming the using Natural<T>/Integer<T> = (u)intT; shorthand to something that isn't as easily confused with the (u)int_t types ... but we'll see. I'll definitely continue to change small things all the time, but for the larger picture, I need to just accept the style I have and live with it.
2016-06-29 11:10:28 +00:00
auto APU::writeIO(uint32 addr, uint8 data) -> void {
switch(addr) {
//NR10
case 0x0400'0060: return square1.write(0, data);
case 0x0400'0061: return;
//NR11, NR12
case 0x0400'0062: return square1.write(1, data);
case 0x0400'0063: return square1.write(2, data);
//NR13, NR14
case 0x0400'0064: return square1.write(3, data);
case 0x0400'0065: return square1.write(4, data);
//NR21, NR22
case 0x0400'0068: return square2.write(1, data);
case 0x0400'0069: return square2.write(2, data);
//NR23, NR24
case 0x0400'006c: return square2.write(3, data);
case 0x0400'006d: return square2.write(4, data);
//NR30
case 0x0400'0070: return wave.write(0, data);
case 0x0400'0071: return;
//NR31, NR32
case 0x0400'0072: return wave.write(1, data);
case 0x0400'0073: return wave.write(2, data);
//NR33, NR34
case 0x0400'0074: return wave.write(3, data);
case 0x0400'0075: return wave.write(4, data);
//NR41, NR42
case 0x0400'0078: return noise.write(1, data);
case 0x0400'0079: return noise.write(2, data);
//NR43, NR44
case 0x0400'007c: return noise.write(3, data);
case 0x0400'007d: return noise.write(4, data);
//NR50, NR51
case 0x0400'0080: return sequencer.write(0, data);
case 0x0400'0081: return sequencer.write(1, data);
//SOUND_CNT_H
case 0x0400'0082:
sequencer.volume = data.bits(0,1);
fifo[0].volume = data.bit (2);
fifo[1].volume = data.bit (3);
return;
case 0x0400'0083:
fifo[0].renable = data.bit(0);
fifo[0].lenable = data.bit(1);
fifo[0].timer = data.bit(2);
if(data.bit(3)) fifo[0].reset();
fifo[1].renable = data.bit(4);
fifo[1].lenable = data.bit(5);
fifo[1].timer = data.bit(6);
if(data.bit(7)) fifo[1].reset();
return;
//NR52
case 0x0400'0084: return sequencer.write(2, data);
case 0x0400'0085: return;
//SOUNDBIAS
case 0x0400'0088:
regs.bias.level.bits(0,7) = data;
return;
case 0x0400'0089:
regs.bias.level.bits(8,9) = data.bits(0,1);
regs.bias.amplitude = data.bits(6,7);
return;
//WAVE_RAM0_L
case 0x0400'0090: return wave.writeram( 0, data);
case 0x0400'0091: return wave.writeram( 1, data);
//WAVE_RAM0_H
case 0x0400'0092: return wave.writeram( 2, data);
case 0x0400'0093: return wave.writeram( 3, data);
//WAVE_RAM1_L
case 0x0400'0094: return wave.writeram( 4, data);
case 0x0400'0095: return wave.writeram( 5, data);
//WAVE_RAM1_H
case 0x0400'0096: return wave.writeram( 6, data);
case 0x0400'0097: return wave.writeram( 7, data);
//WAVE_RAM2_L
case 0x0400'0098: return wave.writeram( 8, data);
case 0x0400'0099: return wave.writeram( 9, data);
//WAVE_RAM2_H
case 0x0400'009a: return wave.writeram(10, data);
case 0x0400'009b: return wave.writeram(11, data);
//WAVE_RAM3_L
case 0x0400'009c: return wave.writeram(12, data);
case 0x0400'009d: return wave.writeram(13, data);
//WAVE_RAM3_H
case 0x0400'009e: return wave.writeram(14, data);
case 0x0400'009f: return wave.writeram(15, data);
//FIFO_A_L
//FIFO_A_H
case 0x0400'00a0: case 0x0400'00a1:
case 0x0400'00a2: case 0x0400'00a3:
return fifo[0].write(data);
//FIFO_B_L
//FIFO_B_H
case 0x0400'00a4: case 0x0400'00a5:
case 0x0400'00a6: case 0x0400'00a7:
return fifo[1].write(data);
}
}