2011-10-01 12:06:48 +00:00
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//BANDAI-FCG
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struct BandaiFCG : Board {
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uint8 chr_bank[8];
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uint8 prg_bank;
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uint2 mirror;
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bool irq_counter_enable;
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uint16 irq_counter;
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uint16 irq_latch;
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void main() {
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while(true) {
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if(scheduler.sync == Scheduler::SynchronizeMode::All) {
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scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
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}
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if(irq_counter_enable) {
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if(--irq_counter == 0xffff) {
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cpu.set_irq_line(1);
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irq_counter_enable = false;
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}
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}
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tick();
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}
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}
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unsigned ciram_addr(unsigned addr) const {
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switch(mirror) {
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case 0: return ((addr & 0x0400) >> 0) | (addr & 0x03ff);
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case 1: return ((addr & 0x0800) >> 1) | (addr & 0x03ff);
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case 2: return 0x0000 | (addr & 0x03ff);
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case 3: return 0x0400 | (addr & 0x03ff);
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}
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}
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uint8 prg_read(unsigned addr) {
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if(addr & 0x8000) {
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bool region = addr & 0x4000;
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unsigned bank = (region == 0 ? prg_bank : 0x0f);
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Update to v082r33 release.
byuu says:
Added MMC2, MMC4, VRC4, VRC7 (no audio.)
Split NES audio code up into individual modules.
Fixed libsnes to compile: Themaister, can you please test to make sure
it works? I don't have a libsnes client on my work PC to test it.
Added about / license information to bottom of advanced settings screen
for now (better than nothing, I guess.)
Blocked PPU reads/writes while rendering for now, easier than coming up
with a bus address locking thing :/
I can't seem to fix MMC5 graphics during the intro to Uchuu Keibitai.
Without that, trying to implement vertical-split screen mode doesn't
make sense.
So as far as special audio chips go ...
* VRC6 is completed
* Sunsoft 5B has everything the only game to use it uses, but there are
more unused channels I'd like to support anyway (they aren't
documented, though.)
* MMC5 audio unsupported for now
* VRC7 audio unsupported, probably for a long time (hardest audio driver
of all. More complex than core NES APU.)
* audio PCM games (Moero Pro Yakyuu!) I probably won't ever support
(they require external WAV packs.)
2011-10-12 12:03:58 +00:00
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return prgrom.read((bank << 14) | (addr & 0x3fff));
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2011-10-01 12:06:48 +00:00
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}
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return cpu.mdr();
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}
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void prg_write(unsigned addr, uint8 data) {
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if(addr >= 0x6000) {
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switch(addr & 15) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x04: case 0x05: case 0x06: case 0x07:
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chr_bank[addr & 7] = data;
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break;
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case 0x08:
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prg_bank = data & 0x0f;
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break;
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case 0x09:
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mirror = data & 0x03;
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break;
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case 0x0a:
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cpu.set_irq_line(0);
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irq_counter_enable = data & 0x01;
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irq_counter = irq_latch;
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break;
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case 0x0b:
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irq_latch = (irq_latch & 0xff00) | (data << 0);
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break;
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case 0x0c:
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irq_latch = (irq_latch & 0x00ff) | (data << 8);
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break;
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case 0x0d:
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//TODO: serial EEPROM support
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break;
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}
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}
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}
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uint8 chr_read(unsigned addr) {
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if(addr & 0x2000) return ppu.ciram_read(ciram_addr(addr));
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addr = (chr_bank[addr >> 10] << 10) | (addr & 0x03ff);
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return Board::chr_read(addr);
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}
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void chr_write(unsigned addr, uint8 data) {
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if(addr & 0x2000) return ppu.ciram_write(ciram_addr(addr), data);
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addr = (chr_bank[addr >> 10] << 10) | (addr & 0x03ff);
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return Board::chr_write(addr, data);
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}
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void power() {
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reset();
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}
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void reset() {
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for(auto &n : chr_bank) n = 0;
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prg_bank = 0;
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mirror = 0;
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irq_counter_enable = 0;
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irq_counter = 0;
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irq_latch = 0;
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}
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2013-05-05 09:21:30 +00:00
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void serialize(serializer& s) {
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2011-10-01 12:06:48 +00:00
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Board::serialize(s);
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s.array(chr_bank);
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s.integer(prg_bank);
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s.integer(mirror);
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s.integer(irq_counter_enable);
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s.integer(irq_counter);
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s.integer(irq_latch);
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}
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2013-05-05 09:21:30 +00:00
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BandaiFCG(Markup::Node& document) : Board(document) {
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2011-10-01 12:06:48 +00:00
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}
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};
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