2016-02-04 10:29:08 +00:00
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//80 grp1 memb,immb
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//81 grp1 memw,immw
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//82 grp1 memb,immbs
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//83 grp1 memw,immbs
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auto V30MZ::opGroup1MemImm(Size size, bool sign) {
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modRM();
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auto mem = getMem(size);
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2016-02-16 09:27:55 +00:00
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uint16 imm = 0;
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if(sign) imm = (int8)fetch();
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else if(size == Byte) imm = fetch();
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else imm = fetch(Word);
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2016-02-04 10:29:08 +00:00
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switch(modrm.reg) {
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case 0: setMem(size, alAdd(size, mem, imm)); break;
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case 1: setMem(size, alOr (size, mem, imm)); break;
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case 2: setMem(size, alAdc(size, mem, imm)); break;
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case 3: setMem(size, alSbb(size, mem, imm)); break;
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case 4: setMem(size, alAnd(size, mem, imm)); break;
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case 5: setMem(size, alSub(size, mem, imm)); break;
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case 6: setMem(size, alXor(size, mem, imm)); break;
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case 7: alSub(size, mem, imm); break;
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}
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}
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//c0 grp2 memb,imm8
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//c1 grp2 memw,imm8
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//d0 grp2 memb,1
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//d1 grp2 memw,1
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//d2 grp2 memb,cl
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//d3 grp2 memw,cl
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auto V30MZ::opGroup2MemImm(Size size, maybe<uint8> imm) {
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modRM();
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auto mem = getMem(size);
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if(!imm) {
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wait(2);
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imm = fetch();
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}
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switch(modrm.reg) {
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case 0: setMem(size, alRol(size, mem, *imm)); break;
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case 1: setMem(size, alRor(size, mem, *imm)); break;
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case 2: setMem(size, alRcl(size, mem, *imm)); break;
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case 3: setMem(size, alRcr(size, mem, *imm)); break;
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case 4: setMem(size, alShl(size, mem, *imm)); break;
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case 5: setMem(size, alShr(size, mem, *imm)); break;
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case 6: setMem(size, alSal(size, mem, *imm)); break;
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case 7: setMem(size, alSar(size, mem, *imm)); break;
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}
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}
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//f6 grp3 memb
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//f7 grp3 memw
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auto V30MZ::opGroup3MemImm(Size size) {
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modRM();
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auto mem = getMem(size);
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switch(modrm.reg) {
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case 0: alAnd(size, mem, fetch(size)); break;
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case 1: break;
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case 2: wait(2); setMem(size, alNot(size, mem)); break;
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case 3: wait(2); setMem(size, alNeg(size, mem)); break;
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case 4: wait(2); setAcc(size * 2, alMul(size, getAcc(size), mem)); break;
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case 5: wait(2); setAcc(size * 2, alMuli(size, getAcc(size), mem)); break; break;
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case 6: wait(size == Byte ? 15 : 23); setAcc(size * 2, alDiv(size, getAcc(size * 2), mem)); break;
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case 7: wait(size == Byte ? 17 : 24); setAcc(size * 2, alDivi(size, getAcc(size * 2), mem)); break;
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}
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}
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//fe grp4 memb
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//ff grp4 memw
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auto V30MZ::opGroup4MemImm(Size size) {
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modRM();
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auto mem = getMem(size);
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switch(modrm.reg) {
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case 0: wait(2); setMem(size, alInc(size, mem)); break;
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case 1: wait(2); setMem(size, alDec(size, mem)); break;
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case 2: break;
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case 3: break;
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case 4: break;
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case 5: break;
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case 6: break;
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case 7: break;
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}
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}
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