2015-11-21 07:36:48 +00:00
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auto CPU::op_io() -> void {
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2011-08-13 03:51:29 +00:00
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cycle_edge();
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2011-10-28 09:51:43 +00:00
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add_clocks(4);
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2010-12-28 06:03:02 +00:00
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}
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2015-11-21 07:36:48 +00:00
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auto CPU::op_read(uint16 addr) -> uint8 {
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2011-08-13 03:51:29 +00:00
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cycle_edge();
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2011-10-28 09:51:43 +00:00
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add_clocks(4);
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2013-12-20 11:40:39 +00:00
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if(oamdma.active && (addr < 0xff80 || addr == 0xffff)) return 0x00;
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2013-12-14 06:25:12 +00:00
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return bus.read(addr);
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2010-12-28 06:03:02 +00:00
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}
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2015-11-21 07:36:48 +00:00
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auto CPU::op_write(uint16 addr, uint8 data) -> void {
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2011-08-13 03:51:29 +00:00
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cycle_edge();
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2011-10-28 09:51:43 +00:00
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add_clocks(4);
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2013-12-20 11:40:39 +00:00
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if(oamdma.active && (addr < 0xff80 || addr == 0xffff)) return;
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bus.write(addr, data);
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2010-12-28 06:03:02 +00:00
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}
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2015-11-21 07:36:48 +00:00
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auto CPU::cycle_edge() -> void {
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2012-04-26 10:51:13 +00:00
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if(r.ei) {
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r.ei = false;
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r.ime = 1;
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2011-08-13 03:51:29 +00:00
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}
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}
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2013-12-10 12:12:54 +00:00
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//VRAM DMA source can only be ROM or RAM
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2015-11-21 07:36:48 +00:00
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auto CPU::dma_read(uint16 addr) -> uint8 {
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2013-12-10 12:12:54 +00:00
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if(addr < 0x8000) return bus.read(addr); //0000-7fff
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if(addr < 0xa000) return 0x00; //8000-9fff
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if(addr < 0xe000) return bus.read(addr); //a000-dfff
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return 0x00; //e000-ffff
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}
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//VRAM DMA target is always VRAM
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2015-11-21 07:36:48 +00:00
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auto CPU::dma_write(uint16 addr, uint8 data) -> void {
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2013-12-10 12:12:54 +00:00
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addr = 0x8000 | (addr & 0x1fff); //8000-9fff
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return bus.write(addr, data);
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}
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2015-11-21 07:36:48 +00:00
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auto CPU::debugger_read(uint16 addr) -> uint8 {
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2012-04-26 10:51:13 +00:00
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return bus.read(addr);
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}
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