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bsnes/higan/processor/upd96050/serialization.cpp

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Update to v095r08 release. byuu says: Changelog: - added preliminary WASAPI driver (it's really terrible, though. Patches most welcome.) - all of processor/ updated to auto fn() -> ret syntax - all of gb/ updated to auto fn() -> ret syntax If you want to test the WASAPI driver, then edit ui-tomoko/GNUmakefile, and replace audio.xaudio2 with audio.wasapi Note that the two drivers are incompatible and cannot co-exist (yet. We can probably make it work in the future.) All that's left for the auto fn() -> ret syntax is the NES core and the balanced/performance SNES components. This is kind of a big deal because this syntax change causes diffs between WIPs to go crazy. So the sooner we get this done and out of the way, the better. It's also nice from a consistency standpoint, of course.
2015-11-21 07:36:48 +00:00
auto uPD96050::serialize(serializer& s) -> void {
Update to v087r09 release. byuu says: Split apart necdsp: core is now in processor/upd96050 (wish I had a better name for it, but there's no family name that is maskable.) I would like to support the uPD7720 in the core as well, just for completeness' sake, but I'll have to modify the decoder to drop one bit from each mode. So ... I'll do that later. Worst part is even if I do, I won't be able to test it :( Added all of Cydrak's changes. I also simplified LDMIA/STMIA and PUSH/POP by merging the outer loops. Probably infinitesimally slower, but less code is nicer. Maybe GCC optimization will expand it, who knows.
2012-03-26 10:13:02 +00:00
s.array(dataRAM);
s.array(regs.stack);
s.integer(regs.pc);
s.integer(regs.rp);
s.integer(regs.dp);
s.integer(regs.sp);
s.integer(regs.k);
s.integer(regs.l);
s.integer(regs.m);
s.integer(regs.n);
s.integer(regs.a);
s.integer(regs.b);
Update to v098r19 release. byuu says: Changelog: - added nall/bit-field.hpp - updated all CPU cores (sans LR35902 due to some complexities) to use BitFields instead of bools - updated as many CPU cores as I could to use BitFields instead of union { struct { uint8_t ... }; }; pairs The speed changes are mostly a wash for this. In some instances, I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3% slowdown (eg Famicom emulation.) It's within the margin of error, so it's safe to say it has no impact. This does give us a lot of new useful things, however: - no more manual reconstruction of flag values from lots of left shifts and ORs - no more manual deconstruction of flag values from lots of ANDs - ability to get completely free aliases to flag groups (eg GSU can provide alt2, alt1 and also alt (which is alt2,alt1 combined) - removes the need for the nasty order_lsbN macro hack (eventually will make higan 100% endian independent) - saves us from insane compilers that try and do nasty things with alignment on union-structs - saves us from insane compilers that try to store bit-field bits in reverse order - will allow some really novel new use cases (I'm planning an instant-decode ARM opcode function, for instance.) - reduces code size (we can serialize flag registers in one line instead of one for each flag) However, I probably won't use it for super critical code that's constantly reading out register values (eg PPU MMIO registers.) I think there we would end up with a performance penalty.
2016-06-08 22:26:35 +00:00
s.integer(regs.flaga.data);
s.integer(regs.flagb.data);
Update to v087r09 release. byuu says: Split apart necdsp: core is now in processor/upd96050 (wish I had a better name for it, but there's no family name that is maskable.) I would like to support the uPD7720 in the core as well, just for completeness' sake, but I'll have to modify the decoder to drop one bit from each mode. So ... I'll do that later. Worst part is even if I do, I won't be able to test it :( Added all of Cydrak's changes. I also simplified LDMIA/STMIA and PUSH/POP by merging the outer loops. Probably infinitesimally slower, but less code is nicer. Maybe GCC optimization will expand it, who knows.
2012-03-26 10:13:02 +00:00
s.integer(regs.tr);
s.integer(regs.trb);
Update to v098r19 release. byuu says: Changelog: - added nall/bit-field.hpp - updated all CPU cores (sans LR35902 due to some complexities) to use BitFields instead of bools - updated as many CPU cores as I could to use BitFields instead of union { struct { uint8_t ... }; }; pairs The speed changes are mostly a wash for this. In some instances, I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3% slowdown (eg Famicom emulation.) It's within the margin of error, so it's safe to say it has no impact. This does give us a lot of new useful things, however: - no more manual reconstruction of flag values from lots of left shifts and ORs - no more manual deconstruction of flag values from lots of ANDs - ability to get completely free aliases to flag groups (eg GSU can provide alt2, alt1 and also alt (which is alt2,alt1 combined) - removes the need for the nasty order_lsbN macro hack (eventually will make higan 100% endian independent) - saves us from insane compilers that try and do nasty things with alignment on union-structs - saves us from insane compilers that try to store bit-field bits in reverse order - will allow some really novel new use cases (I'm planning an instant-decode ARM opcode function, for instance.) - reduces code size (we can serialize flag registers in one line instead of one for each flag) However, I probably won't use it for super critical code that's constantly reading out register values (eg PPU MMIO registers.) I think there we would end up with a performance penalty.
2016-06-08 22:26:35 +00:00
s.integer(regs.sr.data);
Update to v087r09 release. byuu says: Split apart necdsp: core is now in processor/upd96050 (wish I had a better name for it, but there's no family name that is maskable.) I would like to support the uPD7720 in the core as well, just for completeness' sake, but I'll have to modify the decoder to drop one bit from each mode. So ... I'll do that later. Worst part is even if I do, I won't be able to test it :( Added all of Cydrak's changes. I also simplified LDMIA/STMIA and PUSH/POP by merging the outer loops. Probably infinitesimally slower, but less code is nicer. Maybe GCC optimization will expand it, who knows.
2012-03-26 10:13:02 +00:00
s.integer(regs.dr);
s.integer(regs.si);
s.integer(regs.so);
}