2016-04-09 05:20:41 +00:00
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auto PPU::getVramAddress() -> uint16 {
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2016-06-14 10:51:54 +00:00
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uint16 address = r.vramAddress;
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switch(r.vramMapping) {
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2016-04-09 05:20:41 +00:00
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case 0: break; //direct mapping
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2016-06-14 10:51:54 +00:00
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case 1: address = (address & 0xff00) | ((address & 0x001f) << 3) | ((address >> 5) & 7); break;
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case 2: address = (address & 0xfe00) | ((address & 0x003f) << 3) | ((address >> 6) & 7); break;
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case 3: address = (address & 0xfc00) | ((address & 0x007f) << 3) | ((address >> 7) & 7); break;
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2016-04-09 05:20:41 +00:00
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}
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2016-06-14 10:51:54 +00:00
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return address << 1;
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2016-04-09 05:20:41 +00:00
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}
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auto PPU::vramRead(uint addr) -> uint8 {
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uint8 data = 0x00;
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2016-06-14 10:51:54 +00:00
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if(r.displayDisable || vcounter() >= vdisp()) {
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2016-06-15 11:32:17 +00:00
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data = vram[addr];
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2016-06-14 10:51:54 +00:00
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debugger.vramRead(addr, data);
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2016-04-09 05:20:41 +00:00
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}
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return data;
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}
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auto PPU::vramWrite(uint addr, uint8 data) -> void {
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2016-06-14 10:51:54 +00:00
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if(r.displayDisable || vcounter() >= vdisp()) {
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2016-06-15 11:32:17 +00:00
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vram[addr] = data;
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2016-06-14 10:51:54 +00:00
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debugger.vramWrite(addr, data);
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2016-04-09 05:20:41 +00:00
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}
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}
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auto PPU::oamRead(uint addr) -> uint8 {
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2016-06-15 11:32:17 +00:00
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uint8 data = oam[addr];
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2016-06-14 10:51:54 +00:00
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debugger.oamRead(addr, data);
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2016-04-09 05:20:41 +00:00
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return data;
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}
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auto PPU::oamWrite(uint addr, uint8 data) -> void {
|
2016-06-15 11:32:17 +00:00
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oam[addr] = data;
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|
|
obj.update(addr, data);
|
2016-06-14 10:51:54 +00:00
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|
|
debugger.oamWrite(addr, data);
|
2016-04-09 05:20:41 +00:00
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|
|
}
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|
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auto PPU::cgramRead(uint addr) -> uint8 {
|
2016-06-15 11:32:17 +00:00
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|
|
uint8 data = cgram[addr];
|
2016-06-14 10:51:54 +00:00
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|
|
debugger.cgramRead(addr, data);
|
2016-04-09 05:20:41 +00:00
|
|
|
return data;
|
|
|
|
}
|
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|
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|
|
auto PPU::cgramWrite(uint addr, uint8 data) -> void {
|
2016-06-15 11:32:17 +00:00
|
|
|
cgram[addr] = data;
|
2016-06-14 10:51:54 +00:00
|
|
|
debugger.cgramWrite(addr, data);
|
2016-04-09 05:20:41 +00:00
|
|
|
}
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