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bsnes/higan/processor/wdc65816/disassembler.cpp

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Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
enum : uint {
OPTYPE_DP = 0, //dp
OPTYPE_DPX, //dp,x
OPTYPE_DPY, //dp,y
OPTYPE_IDP, //(dp)
OPTYPE_IDPX, //(dp,x)
OPTYPE_IDPY, //(dp),y
OPTYPE_ILDP, //[dp]
OPTYPE_ILDPY, //[dp],y
OPTYPE_ADDR, //addr
OPTYPE_ADDRX, //addr,x
OPTYPE_ADDRY, //addr,y
OPTYPE_IADDRX, //(addr,x)
OPTYPE_ILADDR, //[addr]
OPTYPE_LONG, //long
OPTYPE_LONGX, //long, x
OPTYPE_SR, //sr,s
OPTYPE_ISRY, //(sr,s),y
OPTYPE_ADDR_PC, //pbr:addr
OPTYPE_IADDR_PC, //pbr:(addr)
OPTYPE_RELB, //relb
OPTYPE_RELW, //relw
};
auto WDC65816::dreadb(uint24 addr) -> uint8 {
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
if((addr & 0x40ffff) >= 0x2000 && (addr & 0x40ffff) <= 0x5fff) {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
//$00-3f|80-bf:2000-5fff
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
//do not read MMIO registers within debugger
return 0x00;
}
Update to v099r12 release. byuu says: Changelog: - fixed FC AxROM / VRC7 regression - BitField split to BooleanBitField/NaturalBitField (in preparation for IntegerBitField) - BitFieldReference removed - GB CPU cleaned up - GB Cartridge + Mappers cleaned up - SFC CGRAM is now emulated as uint15[256] instead of uint[512] - sfc/ppu/memory.cpp no longer needed; removed - purged SFC Debugger hooks for now (some of the operator[] calls were bypassing them anyway) Unfortunately, for reasons that defy all semblance of logic, the CGRAM change caused a slight speed hit. As have the last few changes. We're now down to around 129.5fps compared to 123.fps for v099 and 134.5fps at our peak (v099r01-r02). I really like the style I came up with for the Game Boy mappers to settle the purpose(ROM,RAM) vs (rom,ram)Purpose naming convention. If I ever get around to redoing the NES mappers, that's likely the approach I'll take.
2016-06-28 10:43:47 +00:00
return readDisassembler(addr);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::dreadw(uint24 addr) -> uint16 {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
uint16 data;
data.byte(0) = dreadb(addr++);
data.byte(1) = dreadb(addr++);
return data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::dreadl(uint24 addr) -> uint24 {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
uint24 data;
data.byte(0) = dreadb(addr++);
data.byte(1) = dreadb(addr++);
data.byte(2) = dreadb(addr++);
return data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::decode(uint8 mode, uint24 addr) -> uint24 {
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
uint24 a = 0;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
switch(mode) {
case OPTYPE_DP:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = (r.d + (addr & 0xffff)) & 0xffff;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_DPX:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = (r.d + r.x + (addr & 0xffff)) & 0xffff;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_DPY:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = (r.d + r.y + (addr & 0xffff)) & 0xffff;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_IDP:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.d + (addr & 0xffff)) & 0xffff;
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + dreadw(addr);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_IDPX:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.d + r.x + (addr & 0xffff)) & 0xffff;
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + dreadw(addr);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_IDPY:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.d + (addr & 0xffff)) & 0xffff;
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + dreadw(addr) + r.y;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ILDP:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.d + (addr & 0xffff)) & 0xffff;
a = dreadl(addr);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ILDPY:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.d + (addr & 0xffff)) & 0xffff;
a = dreadl(addr) + r.y;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ADDR:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + (addr & 0xffff);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ADDR_PC:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.pc & 0xff0000) + (addr & 0xffff);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ADDRX:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + (addr & 0xffff) + r.x;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ADDRY:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + (addr & 0xffff) + r.y;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_IADDR_PC:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.pc & 0xff0000) + (addr & 0xffff);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_IADDRX:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.pc & 0xff0000) + ((addr + r.x) & 0xffff);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ILADDR:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = addr;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_LONG:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = addr;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_LONGX:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = (addr + r.x);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_SR:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a = (r.s + (addr & 0xff)) & 0xffff;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_ISRY:
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
addr = (r.s + (addr & 0xff)) & 0xffff;
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.b << 16) + dreadw(addr) + r.y;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_RELB:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.pc & 0xff0000) + (((r.pc & 0xffff) + 2) & 0xffff);
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a += int8(addr);
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
case OPTYPE_RELW:
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
a = (r.pc & 0xff0000) + (((r.pc & 0xffff) + 3) & 0xffff);
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
a += (int16)addr;
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
break;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
return a;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::disassemble() -> string {
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
return disassemble(r.pc, r.e, r.p.m, r.p.x);
Update to v094r04 release. byuu says: Changelog: - target-ethos/ is now target-higan/ (will unfortunately screw up diffs pretty badly at this point.) - had a serious bug in nall::optional<T>::operator=, which is now fixed. - added tracer (no masking just yet, I need to write a nall::bitvector class because I don't want to hard-code those anymore.) - added usage logging (keep track of RWX/EP states for all bus addresses.) - added read/write to poke at memory (hex also works for reading, but this one can poke at MMIO regs and is for one address only.) - added both run.for (# of instructions) and run.to (program counter address.) - added read/write/execute breakpoints with counters for a given address, and with an optional compare byte (for read/write modes.) About the only major things left now for loki is support for trace masking, memory export, and VRAM/OAM/CGRAM access. For phoenix/Console, I really need to add a history to up+down arrows, and I should support left/right insert-at.
2014-02-02 21:02:18 +00:00
}
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
auto WDC65816::disassemble(uint24 addr, bool e, bool m, bool x) -> string {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
string s;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint24 pc = addr;
s = {hex(pc, 6), " "};
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
uint8 op = dreadb(pc); pc.bits(0,15)++;
uint8 op0 = dreadb(pc); pc.bits(0,15)++;
uint8 op1 = dreadb(pc); pc.bits(0,15)++;
uint8 op2 = dreadb(pc);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
#define op8 ((op0))
#define op16 ((op0) | (op1 << 8))
#define op24 ((op0) | (op1 << 8) | (op2 << 16))
Update to v094r04 release. byuu says: Changelog: - target-ethos/ is now target-higan/ (will unfortunately screw up diffs pretty badly at this point.) - had a serious bug in nall::optional<T>::operator=, which is now fixed. - added tracer (no masking just yet, I need to write a nall::bitvector class because I don't want to hard-code those anymore.) - added usage logging (keep track of RWX/EP states for all bus addresses.) - added read/write to poke at memory (hex also works for reading, but this one can poke at MMIO regs and is for one address only.) - added both run.for (# of instructions) and run.to (program counter address.) - added read/write/execute breakpoints with counters for a given address, and with an optional compare byte (for read/write modes.) About the only major things left now for loki is support for trace masking, memory export, and VRAM/OAM/CGRAM access. For phoenix/Console, I really need to add a history to up+down arrows, and I should support left/right insert-at.
2014-02-02 21:02:18 +00:00
#define a8 (e || m)
#define x8 (e || x)
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
char t[256];
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
switch(op) {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x00: sprintf(t, "brk #$%.2x ", op8); break;
case 0x01: sprintf(t, "ora ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0x02: sprintf(t, "cop #$%.2x ", op8); break;
case 0x03: sprintf(t, "ora $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0x04: sprintf(t, "tsb $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x05: sprintf(t, "ora $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x06: sprintf(t, "asl $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x07: sprintf(t, "ora [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0x08: sprintf(t, "php "); break;
case 0x09: if(a8)sprintf(t, "ora #$%.2x ", op8);
else sprintf(t, "ora #$%.4x ", op16); break;
case 0x0a: sprintf(t, "asl a "); break;
case 0x0b: sprintf(t, "phd "); break;
case 0x0c: sprintf(t, "tsb $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x0d: sprintf(t, "ora $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x0e: sprintf(t, "asl $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x0f: sprintf(t, "ora $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x10: sprintf(t, "bpl $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x11: sprintf(t, "ora ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0x12: sprintf(t, "ora ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0x13: sprintf(t, "ora ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0x14: sprintf(t, "trb $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x15: sprintf(t, "ora $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x16: sprintf(t, "asl $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x17: sprintf(t, "ora [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0x18: sprintf(t, "clc "); break;
case 0x19: sprintf(t, "ora $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0x1a: sprintf(t, "inc "); break;
case 0x1b: sprintf(t, "tcs "); break;
case 0x1c: sprintf(t, "trb $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x1d: sprintf(t, "ora $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x1e: sprintf(t, "asl $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x1f: sprintf(t, "ora $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0x20: sprintf(t, "jsr $%.4x [%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
case 0x21: sprintf(t, "and ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0x22: sprintf(t, "jsl $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
case 0x23: sprintf(t, "and $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0x24: sprintf(t, "bit $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x25: sprintf(t, "and $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x26: sprintf(t, "rol $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x27: sprintf(t, "and [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0x28: sprintf(t, "plp "); break;
case 0x29: if(a8)sprintf(t, "and #$%.2x ", op8);
else sprintf(t, "and #$%.4x ", op16); break;
case 0x2a: sprintf(t, "rol a "); break;
case 0x2b: sprintf(t, "pld "); break;
case 0x2c: sprintf(t, "bit $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x2d: sprintf(t, "and $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x2e: sprintf(t, "rol $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x2f: sprintf(t, "and $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x30: sprintf(t, "bmi $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x31: sprintf(t, "and ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0x32: sprintf(t, "and ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0x33: sprintf(t, "and ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0x34: sprintf(t, "bit $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x35: sprintf(t, "and $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x36: sprintf(t, "rol $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x37: sprintf(t, "and [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0x38: sprintf(t, "sec "); break;
case 0x39: sprintf(t, "and $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0x3a: sprintf(t, "dec "); break;
case 0x3b: sprintf(t, "tsc "); break;
case 0x3c: sprintf(t, "bit $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x3d: sprintf(t, "and $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x3e: sprintf(t, "rol $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x3f: sprintf(t, "and $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0x40: sprintf(t, "rti "); break;
case 0x41: sprintf(t, "eor ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0x42: sprintf(t, "wdm "); break;
case 0x43: sprintf(t, "eor $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0x44: sprintf(t, "mvp $%.2x,$%.2x ", op1, op8); break;
case 0x45: sprintf(t, "eor $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x46: sprintf(t, "lsr $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x47: sprintf(t, "eor [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0x48: sprintf(t, "pha "); break;
case 0x49: if(a8)sprintf(t, "eor #$%.2x ", op8);
else sprintf(t, "eor #$%.4x ", op16); break;
case 0x4a: sprintf(t, "lsr a "); break;
case 0x4b: sprintf(t, "phk "); break;
case 0x4c: sprintf(t, "jmp $%.4x [%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
case 0x4d: sprintf(t, "eor $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x4e: sprintf(t, "lsr $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x4f: sprintf(t, "eor $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x50: sprintf(t, "bvc $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x51: sprintf(t, "eor ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0x52: sprintf(t, "eor ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0x53: sprintf(t, "eor ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0x54: sprintf(t, "mvn $%.2x,$%.2x ", op1, op8); break;
case 0x55: sprintf(t, "eor $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x56: sprintf(t, "lsr $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x57: sprintf(t, "eor [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0x58: sprintf(t, "cli "); break;
case 0x59: sprintf(t, "eor $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0x5a: sprintf(t, "phy "); break;
case 0x5b: sprintf(t, "tcd "); break;
case 0x5c: sprintf(t, "jml $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
case 0x5d: sprintf(t, "eor $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x5e: sprintf(t, "lsr $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x5f: sprintf(t, "eor $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0x60: sprintf(t, "rts "); break;
case 0x61: sprintf(t, "adc ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0x62: sprintf(t, "per $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x63: sprintf(t, "adc $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0x64: sprintf(t, "stz $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x65: sprintf(t, "adc $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x66: sprintf(t, "ror $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x67: sprintf(t, "adc [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0x68: sprintf(t, "pla "); break;
case 0x69: if(a8)sprintf(t, "adc #$%.2x ", op8);
else sprintf(t, "adc #$%.4x ", op16); break;
case 0x6a: sprintf(t, "ror a "); break;
case 0x6b: sprintf(t, "rtl "); break;
case 0x6c: sprintf(t, "jmp ($%.4x) [%.6x]", op16, decode(OPTYPE_IADDR_PC, op16)); break;
case 0x6d: sprintf(t, "adc $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x6e: sprintf(t, "ror $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x6f: sprintf(t, "adc $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x70: sprintf(t, "bvs $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x71: sprintf(t, "adc ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0x72: sprintf(t, "adc ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0x73: sprintf(t, "adc ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0x74: sprintf(t, "stz $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x75: sprintf(t, "adc $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x76: sprintf(t, "ror $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x77: sprintf(t, "adc [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0x78: sprintf(t, "sei "); break;
case 0x79: sprintf(t, "adc $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0x7a: sprintf(t, "ply "); break;
case 0x7b: sprintf(t, "tdc "); break;
case 0x7c: sprintf(t, "jmp ($%.4x,x) [%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
case 0x7d: sprintf(t, "adc $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x7e: sprintf(t, "ror $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x7f: sprintf(t, "adc $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x80: sprintf(t, "bra $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x81: sprintf(t, "sta ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x82: sprintf(t, "brl $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELW, op16)), decode(OPTYPE_RELW, op16)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x83: sprintf(t, "sta $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0x84: sprintf(t, "sty $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x85: sprintf(t, "sta $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x86: sprintf(t, "stx $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0x87: sprintf(t, "sta [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0x88: sprintf(t, "dey "); break;
case 0x89: if(a8)sprintf(t, "bit #$%.2x ", op8);
else sprintf(t, "bit #$%.4x ", op16); break;
case 0x8a: sprintf(t, "txa "); break;
case 0x8b: sprintf(t, "phb "); break;
case 0x8c: sprintf(t, "sty $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x8d: sprintf(t, "sta $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x8e: sprintf(t, "stx $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x8f: sprintf(t, "sta $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0x90: sprintf(t, "bcc $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x91: sprintf(t, "sta ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0x92: sprintf(t, "sta ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0x93: sprintf(t, "sta ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0x94: sprintf(t, "sty $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x95: sprintf(t, "sta $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0x96: sprintf(t, "stx $%.2x,y [%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
case 0x97: sprintf(t, "sta [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0x98: sprintf(t, "tya "); break;
case 0x99: sprintf(t, "sta $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0x9a: sprintf(t, "txs "); break;
case 0x9b: sprintf(t, "txy "); break;
case 0x9c: sprintf(t, "stz $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0x9d: sprintf(t, "sta $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x9e: sprintf(t, "stz $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0x9f: sprintf(t, "sta $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0xa0: if(x8)sprintf(t, "ldy #$%.2x ", op8);
else sprintf(t, "ldy #$%.4x ", op16); break;
case 0xa1: sprintf(t, "lda ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0xa2: if(x8)sprintf(t, "ldx #$%.2x ", op8);
else sprintf(t, "ldx #$%.4x ", op16); break;
case 0xa3: sprintf(t, "lda $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0xa4: sprintf(t, "ldy $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xa5: sprintf(t, "lda $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xa6: sprintf(t, "ldx $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xa7: sprintf(t, "lda [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0xa8: sprintf(t, "tay "); break;
case 0xa9: if(a8)sprintf(t, "lda #$%.2x ", op8);
else sprintf(t, "lda #$%.4x ", op16); break;
case 0xaa: sprintf(t, "tax "); break;
case 0xab: sprintf(t, "plb "); break;
case 0xac: sprintf(t, "ldy $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xad: sprintf(t, "lda $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xae: sprintf(t, "ldx $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xaf: sprintf(t, "lda $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0xb0: sprintf(t, "bcs $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0xb1: sprintf(t, "lda ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0xb2: sprintf(t, "lda ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0xb3: sprintf(t, "lda ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0xb4: sprintf(t, "ldy $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xb5: sprintf(t, "lda $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xb6: sprintf(t, "ldx $%.2x,y [%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
case 0xb7: sprintf(t, "lda [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0xb8: sprintf(t, "clv "); break;
case 0xb9: sprintf(t, "lda $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0xba: sprintf(t, "tsx "); break;
case 0xbb: sprintf(t, "tyx "); break;
case 0xbc: sprintf(t, "ldy $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xbd: sprintf(t, "lda $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xbe: sprintf(t, "ldx $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0xbf: sprintf(t, "lda $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0xc0: if(x8)sprintf(t, "cpy #$%.2x ", op8);
else sprintf(t, "cpy #$%.4x ", op16); break;
case 0xc1: sprintf(t, "cmp ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0xc2: sprintf(t, "rep #$%.2x ", op8); break;
case 0xc3: sprintf(t, "cmp $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0xc4: sprintf(t, "cpy $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xc5: sprintf(t, "cmp $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xc6: sprintf(t, "dec $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xc7: sprintf(t, "cmp [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0xc8: sprintf(t, "iny "); break;
case 0xc9: if(a8)sprintf(t, "cmp #$%.2x ", op8);
else sprintf(t, "cmp #$%.4x ", op16); break;
case 0xca: sprintf(t, "dex "); break;
case 0xcb: sprintf(t, "wai "); break;
case 0xcc: sprintf(t, "cpy $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xcd: sprintf(t, "cmp $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xce: sprintf(t, "dec $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xcf: sprintf(t, "cmp $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0xd0: sprintf(t, "bne $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0xd1: sprintf(t, "cmp ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0xd2: sprintf(t, "cmp ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0xd3: sprintf(t, "cmp ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0xd4: sprintf(t, "pei ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0xd5: sprintf(t, "cmp $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xd6: sprintf(t, "dec $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xd7: sprintf(t, "cmp [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0xd8: sprintf(t, "cld "); break;
case 0xd9: sprintf(t, "cmp $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0xda: sprintf(t, "phx "); break;
case 0xdb: sprintf(t, "stp "); break;
case 0xdc: sprintf(t, "jmp [$%.4x] [%.6x]", op16, decode(OPTYPE_ILADDR, op16)); break;
case 0xdd: sprintf(t, "cmp $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xde: sprintf(t, "dec $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xdf: sprintf(t, "cmp $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
case 0xe0: if(x8)sprintf(t, "cpx #$%.2x ", op8);
else sprintf(t, "cpx #$%.4x ", op16); break;
case 0xe1: sprintf(t, "sbc ($%.2x,x) [%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
case 0xe2: sprintf(t, "sep #$%.2x ", op8); break;
case 0xe3: sprintf(t, "sbc $%.2x,s [%.6x]", op8, decode(OPTYPE_SR, op8)); break;
case 0xe4: sprintf(t, "cpx $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xe5: sprintf(t, "sbc $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xe6: sprintf(t, "inc $%.2x [%.6x]", op8, decode(OPTYPE_DP, op8)); break;
case 0xe7: sprintf(t, "sbc [$%.2x] [%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
case 0xe8: sprintf(t, "inx "); break;
case 0xe9: if(a8)sprintf(t, "sbc #$%.2x ", op8);
else sprintf(t, "sbc #$%.4x ", op16); break;
case 0xea: sprintf(t, "nop "); break;
case 0xeb: sprintf(t, "xba "); break;
case 0xec: sprintf(t, "cpx $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xed: sprintf(t, "sbc $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xee: sprintf(t, "inc $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xef: sprintf(t, "sbc $%.6x [%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
Update to v097r23 release. byuu says: Changelog: - emulated SuperDisc $21e1 basic interface (NEC 4-bit MCU); all hardware tests pass now (but they don't test much) - WS/V30MZ: fixed inc/dec reg flag calculation - WS/V30MZ: fixed lds/les instructions WS/C compatibility should be way up now. SuperDisc BIOS passes all tests now (but they only test for the presence of the interface, nothing more.)
2016-03-10 10:35:48 +00:00
case 0xf0: sprintf(t, "beq $%.4x [%.6x]", uint16_t(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0xf1: sprintf(t, "sbc ($%.2x),y [%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
case 0xf2: sprintf(t, "sbc ($%.2x) [%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
case 0xf3: sprintf(t, "sbc ($%.2x,s),y [%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
case 0xf4: sprintf(t, "pea $%.4x [%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
case 0xf5: sprintf(t, "sbc $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xf6: sprintf(t, "inc $%.2x,x [%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
case 0xf7: sprintf(t, "sbc [$%.2x],y [%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
case 0xf8: sprintf(t, "sed "); break;
case 0xf9: sprintf(t, "sbc $%.4x,y [%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
case 0xfa: sprintf(t, "plx "); break;
case 0xfb: sprintf(t, "xce "); break;
case 0xfc: sprintf(t, "jsr ($%.4x,x) [%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
case 0xfd: sprintf(t, "sbc $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xfe: sprintf(t, "inc $%.4x,x [%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
case 0xff: sprintf(t, "sbc $%.6x,x [%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
#undef op8
#undef op16
#undef op24
#undef a8
#undef x8
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
s.append(t, " A:{0} X:{1} Y:{2} S:{3} D:{4} B:{5} ", string_format{
Update to v102r25 release. byuu says: Changelog: - processor/arm: corrected MUL instruction timings [Jonas Quinn] - processor/wdc65816: finished phase two of the rewrite I'm really pleased with the visual results of the wdc65816 core rewrite. I was able to eliminate all of the weird `{Boolean,Natural}BitRange` templates, as well as the need to use unions/structs. Registers are now just simple `uint24` or `uint16` types (technically they're `Natural<T>` types, but then all of higan uses those), flags are now just bool types. I also eliminated all of the implicit object state inside of the core (aa, rd, dp, sp) and instead do all computations on the stack frame with local variables. Through using macros to reference the registers and individual parts of them, I was able to reduce the visual tensity of all of the instructions. And by using normal types without implicit states, I was able to eliminate about 15% of the instructions necessary, instead reusing existing ones. The final third phase of the rewrite will be to recode the disassembler. That code is probably the oldest code in all of higan right now, still using sprintf to generate the output. So it is very long overdue for a cleanup. And now for the bad news ... as with any large code cleanup, regression errors have seeped in. Currently, no games are running at all. I've left the old disassembler in for this reason: we can compare trace logs of v102r23 against trace logs of v102r25. The second there's any difference, we've spotted a buggy instruction and can correct it. With any luck, this will be the last time I ever rewrite the wdc65816 core. My style has changed wildly over the ~10 years since I wrote this core, but it's really solidifed in recent years.
2017-06-14 15:55:55 +00:00
hex(r.a, 4), hex(r.x, 4), hex(r.y, 4),
hex(r.s, 4), hex(r.d, 4), hex(r.b, 2)
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
});
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
if(r.e) {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
s.append(
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
r.p.n ? 'N' : 'n', r.p.v ? 'V' : 'v',
r.p.m ? '1' : '0', r.p.x ? 'B' : 'b',
r.p.d ? 'D' : 'd', r.p.i ? 'I' : 'i',
r.p.z ? 'Z' : 'z', r.p.c ? 'C' : 'c'
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
} else {
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
s.append(
Update to v098r11 release. byuu says: Changelog: - fixed nall/path.hpp compilation issue - fixed ruby/audio/xaudio header declaration compilation issue (again) - cleaned up xaudio2.hpp file to match my coding syntax (12.5% of the file was whitespace overkill) - added null terminator entry to nall/windows/utf8.hpp argc[] array - nall/windows/guid.hpp uses the Windows API for generating the GUID - this should stop all the bug reports where two nall users were generating GUIDs at the exact same second - fixed hiro/cocoa compilation issue with uint# types - fixed major higan/sfc Super Game Boy audio latency issue - fixed higan/sfc CPU core bug with pei, [dp], [dp]+y instructions - major cleanups to higan/processor/r65816 core - merged emulation/native-mode opcodes - use camel-case naming on memory.hpp functions - simplify address masking code for memory.hpp functions - simplify a few opcodes themselves (avoid redundant copies, etc) - rename regs.* to r.* to match modern convention of other CPU cores - removed device.order<> concept from Emulator::Interface - cores will now do the translation to make the job of the UI easier - fixed plurality naming of arrays in Emulator::Interface - example: emulator.ports[p].devices[d].inputs[i] - example: vector<Medium> media - probably more surprises Major show-stoppers to the next official release: - we need to work on GB core improvements: LY=153/0 case, multiple STAT IRQs case, GBC audio output regs, etc. - we need to re-add software cursors for light guns (Super Scope, Justifier) - after the above, we need to fix the turbo button for the Super Scope I really have no idea how I want to implement the light guns. Ideally, we'd want it in higan/video, so we can support the NES Zapper with the same code. But this isn't going to be easy, because only the SNES knows when its output is interlaced, and its resolutions can vary as {256,512}x{224,240,448,480} which requires pixel doubling that was hard-coded to the SNES-specific behavior, but isn't appropriate to be exposed in higan/video.
2016-05-25 11:13:02 +00:00
r.p.n ? 'N' : 'n', r.p.v ? 'V' : 'v',
r.p.m ? 'M' : 'm', r.p.x ? 'X' : 'x',
r.p.d ? 'D' : 'd', r.p.i ? 'I' : 'i',
r.p.z ? 'Z' : 'z', r.p.c ? 'C' : 'c'
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v097r29 release. byuu says: Changelog: - fixed DAS instruction (Judgment Silversword score) - fixed [VH]TMR_FREQ writes (Judgement Silversword audio after area 20) - fixed initialization of SP (fixes seven games that were hanging on startup) - added SER_STATUS and SER_DATA stubs (fixes four games that were hanging on startup) - initialized IEEP data (fixes Super Robot Taisen Compact 2 series) - note: you'll need to delete your internal.com in WonderSwan (Color).sys folders - fixed CMPS and SCAS termination condition (fixes serious bugs in four games) - set read/writeCompleted flags for EEPROM status (fixes Tetsujin 28 Gou) - major code cleanups to SFC/R65816 and SFC/CPU - mostly refactored disassembler to output strings instead of using char* buffer - unrolled all the subfolders on sfc/cpu to a single directory - corrected casing for all of sfc/cpu and a large portion of processor/r65816 I kind of went overboard on the code cleanup with this WIP. Hopefully nothing broke. Any testing one can do with the SFC accuracy core would be greatly appreciated. There's still an absolutely huge amount of work left to go, but I do want to eventually refresh the entire codebase to my current coding style, which is extremely different from stuff that's been in higan mostly untouched since ~2006 or so. It's dangerous and fickle work, but if I don't do it, then the code will be a jumbled mess of several different styles.
2016-03-26 01:56:15 +00:00
return s;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}