diff --git a/Core/gb.h b/Core/gb.h index 45deae9..fcae405 100644 --- a/Core/gb.h +++ b/Core/gb.h @@ -227,11 +227,13 @@ enum { GB_IO_PSWX = 0x72, // X position of the palette switching window GB_IO_PSWY = 0x73, // Y position of the palette switching window GB_IO_PSW = 0x74, // Key combo to trigger the palette switching window - GB_IO_UNKNOWN5 = 0x75, // (8Fh) - Bit 4-6 (Read/Write) - GB_IO_PCM12 = 0x76, // Channels 1 and 2 amplitudes - GB_IO_PCM34 = 0x77, // Channels 3 and 4 amplitudes + GB_IO_PGB = 0x75, // Bits 0-2 control PHI, A15 and ¬CS, respectively. Bits 4-6 control the I/O directions of bits 0-2 (0 is R, 1 is W) + GB_IO_PCM12 = 0x76, // Channels 1 and 2 amplitudes + GB_IO_PCM34 = 0x77, // Channels 3 and 4 amplitudes }; +static const typeof(GB_IO_PGB) __attribute__((deprecated("Use GB_IO_PGB instead"))) GB_IO_UNKNOWN5 = GB_IO_PGB; + typedef enum { GB_LOG_BOLD = 1, GB_LOG_DASHED_UNDERLINE = 2, diff --git a/Core/memory.c b/Core/memory.c index 7702423..e1b30da 100644 --- a/Core/memory.c +++ b/Core/memory.c @@ -735,7 +735,7 @@ static uint8_t read_high_memory(GB_gameboy_t *gb, uint16_t addr) return GB_is_cgb(gb)? gb->io_registers[addr & 0xFF] : 0xFF; case GB_IO_PSW: return gb->cgb_mode? gb->io_registers[addr & 0xFF] : 0xFF; - case GB_IO_UNKNOWN5: + case GB_IO_PGB: return GB_is_cgb(gb)? gb->io_registers[addr & 0xFF] | 0x8F : 0xFF; default: if ((addr & 0xFF) >= GB_IO_NR10 && (addr & 0xFF) <= GB_IO_WAV_END) { @@ -1415,7 +1415,7 @@ static void write_high_memory(GB_gameboy_t *gb, uint16_t addr, uint8_t value) case GB_IO_PSWX: case GB_IO_PSWY: case GB_IO_PSW: - case GB_IO_UNKNOWN5: + case GB_IO_PGB: gb->io_registers[addr & 0xFF] = value; return; case GB_IO_OPRI: diff --git a/Misc/registers.sym b/Misc/registers.sym index ef027d0..1da8871 100644 --- a/Misc/registers.sym +++ b/Misc/registers.sym @@ -61,7 +61,7 @@ 00:FF72 rPSWX 00:FF73 rPSWY 00:FF74 rPSW -00:FF75 rUNKNOWN5 +00:FF75 rPGB 00:FF76 rPCM12 00:FF77 rPCM34 00:FFFF rIE