(WIIU) shaders: use bitfields for GPU register values.
This commit is contained in:
aliaspider
parent
ec4b0f9089
commit
f6fdd421c6
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@ -71,18 +71,91 @@ typedef struct GX2VertexShader
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{
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{
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struct
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struct
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{
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{
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uint32_t sq_pgm_resources_vs;
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struct
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uint32_t vgt_primitiveid_en;
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{
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uint32_t spi_vs_out_config;
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unsigned :2;
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bool prime_cache_on_const :1;
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bool prime_cache_enable :1;
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bool uncached_first_inst :1;
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unsigned fetch_cache_lines :3;
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bool prime_cache_on_draw :1;
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bool prime_cache_pgm_en :1;
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bool dx10_clamp :1;
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unsigned :5;
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unsigned stack_size :8;
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unsigned num_gprs :8;
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}sq_pgm_resources_vs;
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bool vgt_primitiveid_en;
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struct
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{
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unsigned :18;
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unsigned vs_out_fog_vec_addr : 5;
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bool vs_exports_fog : 1;
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unsigned :2;
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unsigned vs_export_count :5;
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bool vs_per_component : 1;
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}spi_vs_out_config;
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uint32_t num_spi_vs_out_id;
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uint32_t num_spi_vs_out_id;
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uint32_t spi_vs_out_id[10];
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struct
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uint32_t pa_cl_vs_out_cntl;
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{
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uint8_t semantic_3;
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uint8_t semantic_2;
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uint8_t semantic_1;
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uint8_t semantic_0;
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}spi_vs_out_id[10];
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struct
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{
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bool clip_dist_ena_7 :1;
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bool clip_dist_ena_6 :1;
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bool clip_dist_ena_5 :1;
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bool clip_dist_ena_4 :1;
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bool clip_dist_ena_3 :1;
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bool clip_dist_ena_2 :1;
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bool clip_dist_ena_1 :1;
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bool clip_dist_ena_0 :1;
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bool cull_dist_ena_7 :1;
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bool cull_dist_ena_6 :1;
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bool cull_dist_ena_5 :1;
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bool cull_dist_ena_0 :1;
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bool cull_dist_ena_4 :1;
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bool cull_dist_ena_3 :1;
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bool cull_dist_ena_2 :1;
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bool cull_dist_ena_1 :1;
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bool vs_out_misc_side_bus_ena :1;
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bool vs_out_ccdist1_vec_ena :1;
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bool vs_out_ccdist0_vec_ena :1;
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bool vs_out_misc_vec_ena :1;
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bool use_vtx_kill_flag :1;
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bool use_vtx_viewport_indx :1;
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bool use_vtx_render_target_indx :1;
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bool use_vtx_edge_flag :1;
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unsigned :6;
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bool use_vtx_point_size :1;
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bool use_vtx_gs_cut_flag :1;
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}pa_cl_vs_out_cntl;
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uint32_t sq_vtx_semantic_clear;
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uint32_t sq_vtx_semantic_clear;
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uint32_t num_sq_vtx_semantic;
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uint32_t num_sq_vtx_semantic;
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uint32_t sq_vtx_semantic[32];
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uint32_t sq_vtx_semantic[32]; /* 8 bit */
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uint32_t vgt_strmout_buffer_en;
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struct
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uint32_t vgt_vertex_reuse_block_cntl;
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{
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uint32_t vgt_hos_reuse_depth;
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bool buffer_3_en :1;
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bool buffer_2_en :1;
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bool buffer_1_en :1;
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bool buffer_0_en :1;
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}vgt_strmout_buffer_en;
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struct
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{
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unsigned :24;
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uint8_t vtx_reuse_depth;
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}vgt_vertex_reuse_block_cntl;
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struct
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{
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unsigned :24;
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uint8_t reuse_depth;
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}vgt_hos_reuse_depth;
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} regs;
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} regs;
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uint32_t size;
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uint32_t size;
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@ -115,20 +188,129 @@ typedef struct GX2VertexShader
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GX2RBuffer gx2rBuffer;
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GX2RBuffer gx2rBuffer;
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} GX2VertexShader;
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} GX2VertexShader;
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typedef enum {
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spi_baryc_cntl_centroids_only = 0,
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spi_baryc_cntl_centers_only = 1,
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spi_baryc_cntl_centroids_and_centers = 2,
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}spi_baryc_cntl;
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typedef enum {
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db_z_order_late_z = 0,
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db_z_order_early_z_then_late_z = 1,
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db_z_order_re_z = 2,
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db_z_order_early_z_then_re_z = 3,
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}db_z_order;
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typedef struct GX2PixelShader
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typedef struct GX2PixelShader
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{
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{
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struct
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struct
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{
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{
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uint32_t sq_pgm_resources_ps;
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struct
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uint32_t sq_pgm_exports_ps;
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{
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uint32_t spi_ps_in_control_0;
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unsigned :2;
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uint32_t spi_ps_in_control_1;
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bool prime_cache_on_const :1;
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bool prime_cache_enable :1;
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bool uncached_first_inst :1;
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unsigned fetch_cache_lines :3;
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bool prime_cache_on_draw :1;
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bool prime_cache_pgm_en :1;
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bool dx10_clamp :1;
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unsigned :5;
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unsigned stack_size :8;
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unsigned num_gprs :8;
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}sq_pgm_resources_ps;
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struct
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{
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unsigned :24;
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unsigned export_mode :5;
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}sq_pgm_exports_ps;
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struct
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{
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bool baryc_at_sample_ena :1;
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bool position_sample :1;
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bool linear_gradient_ena :1;
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bool persp_gradient_ena :1;
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spi_baryc_cntl baryc_sample_cntl :2;
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unsigned param_gen_addr : 7;
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unsigned param_gen :4;
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unsigned position_addr :5;
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bool position_centroid :1;
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bool position_ena :1;
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unsigned :2;
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unsigned num_interp :6;
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}spi_ps_in_control_0;
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struct
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{
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unsigned :1;
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bool position_ulc :1;
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unsigned fixed_pt_position_addr :5;
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bool fixed_pt_position_ena :1;
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unsigned fog_addr :7;
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unsigned front_face_addr :5;
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bool front_face_all_bits :1;
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unsigned front_face_chan :2;
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bool front_face_ena :1;
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unsigned gen_index_pix_addr :7;
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bool gen_index_pix :1;
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}spi_ps_in_control_1;
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uint32_t num_spi_ps_input_cntl;
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uint32_t num_spi_ps_input_cntl;
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uint32_t spi_ps_input_cntls[32];
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uint32_t cb_shader_mask;
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struct
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uint32_t cb_shader_control;
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{
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uint32_t db_shader_control;
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unsigned :13;
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uint32_t spi_input_z;
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bool sel_sample :1;
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bool pt_sprite_tex :1;
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unsigned cyl_wrap :4;
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bool sel_linear :1;
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bool sel_centroid :1;
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bool flat_shade :1;
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unsigned default_val :2;
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unsigned semantic :8;
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}spi_ps_input_cntls[32];
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struct
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{
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unsigned output7_enable :4;
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unsigned output6_enable :4;
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unsigned output5_enable :4;
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unsigned output4_enable :4;
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unsigned output3_enable :4;
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unsigned output2_enable :4;
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unsigned output1_enable :4;
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unsigned output0_enable :4;
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}cb_shader_mask;
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struct {
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unsigned :24;
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bool rt7_enable :1;
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bool rt6_enable :1;
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bool rt5_enable :1;
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bool rt4_enable :1;
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bool rt3_enable :1;
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bool rt2_enable :1;
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bool rt1_enable :1;
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bool rt0_enable :1;
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}cb_shader_control;
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struct
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{
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unsigned :19;
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bool alpha_to_mask_disable :1;
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bool exec_on_noop :1;
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bool exec_on_hier_fail :1;
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bool dual_export_enable :1;
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bool mask_export_enable :1;
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bool coverage_to_mask_enable :1;
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bool kill_enable :1;
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db_z_order z_order :2;
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unsigned :2;
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bool z_export_enable :1;
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bool stencil_ref_export_enable :1;
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} db_shader_control;
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bool spi_input_z;
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} regs;
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} regs;
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uint32_t size;
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uint32_t size;
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@ -133,67 +133,64 @@ tex_shader_t tex_shader =
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{
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{
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{
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{
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{
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{
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0x00000103, 0x00000000, 0x00000000, 0x00000001, /* sq_pgm_resources_vs, vgt_primitiveid_en, spi_vs_out_config, num_spi_vs_out_id */
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.sq_pgm_resources_vs.num_gprs = 3,
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{ 0xffffff00, _x9(0xffffffff) }, /* spi_vs_out_id @10 */
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.sq_pgm_resources_vs.stack_size = 1,
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0x00000000, 0xfffffffc, 0x00000002, /* pa_cl_vs_out_cntl, sq_vtx_semantic_clear, num_sq_vtx_semantic */
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.num_spi_vs_out_id = 1,
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{
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{
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0x00000000, 0x00000001, _x30(0x000000ff) /* sq_vtx_semantic @32 */
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{.semantic_0 = 0x00, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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{.semantic_0 = 0xFF, .semantic_1 = 0xFF, .semantic_2 = 0xFF, .semantic_3 = 0xFF},
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},
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},
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0x00000000, 0x0000000e, 0x00000010 /* vgt_strmout_buffer_en, vgt_vertex_reuse_block_cntl, vgt_hos_reuse_depth */
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.sq_vtx_semantic_clear = ~0x3,
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}, /* regs */
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.num_sq_vtx_semantic = 2,
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sizeof(vs_program), /* size */
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{
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(uint8_t*)&vs_program, /* program */
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0, 1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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GX2_SHADER_MODE_UNIFORM_REGISTER, /* mode */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0, /* uniformBlockCount */
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},
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NULL, /* uniformBlocks */
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.vgt_vertex_reuse_block_cntl.vtx_reuse_depth = 0xE,
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0, /* uniformVarCount */
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.vgt_hos_reuse_depth.reuse_depth = 0x10,
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NULL, /* uniformVars */
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}, /* regs */
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0, /* initialValueCount */
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.size = sizeof(vs_program),
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NULL, /* initialValues */
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.program = (uint8_t*)&vs_program,
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0, /* loopVarCount */
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.mode = GX2_SHADER_MODE_UNIFORM_REGISTER,
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NULL, /* loopVars */
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.attribVarCount = sizeof(tex_shader.attributes) / sizeof(GX2AttribVar), (GX2AttribVar*) &tex_shader.attributes,
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0, /* samplerVarCount */
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NULL, /* samplerVars */
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sizeof(tex_shader.attributes) / sizeof(GX2AttribVar), /* attribVarCount */
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(GX2AttribVar*) &tex_shader.attributes, /* attribVars */
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0, /* ringItemsize */
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FALSE, /* hasStreamOut */
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{0}, /* streamOutStride @4 */
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{} /* gx2rBuffer */
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},
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},
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{
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{
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{
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{
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0x00000001, 0x00000002, 0x14000001, 0x00000000, /* sq_pgm_resources_ps, sq_pgm_exports_ps, spi_ps_in_control_0, spi_ps_in_control_1 */
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.sq_pgm_resources_ps.num_gprs = 1,
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0x00000001, /* num_spi_ps_input_cntl */
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.sq_pgm_exports_ps.export_mode = 0x2,
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{ 0x00000100, _x30(0x00000000)}, /* spi_ps_input_cntls @ 32*/
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.spi_ps_in_control_0.num_interp = 1,
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0x0000000f, 0x00000001, 0x00000010, 0x00000000 /* cb_shader_mask, cb_shader_control, db_shader_control, spi_input_z */
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.spi_ps_in_control_0.persp_gradient_ena = 1,
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}, /* regs */
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.spi_ps_in_control_0.baryc_sample_cntl = spi_baryc_cntl_centers_only,
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sizeof(ps_program), /* size */
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.num_spi_ps_input_cntl = 1, {{.default_val = 1},},
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(uint8_t*)&ps_program, /* program */
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.cb_shader_mask.output0_enable = 0xF,
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GX2_SHADER_MODE_UNIFORM_REGISTER, /* mode */
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.cb_shader_control.rt0_enable = TRUE,
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0, /* uniformBlockCount */
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.db_shader_control.z_order = db_z_order_early_z_then_late_z,
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NULL, /* uniformBlocks */
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}, /* regs */
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0, /* uniformVarCount */
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.size = sizeof(ps_program),
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NULL, /* uniformVars */
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.program = (uint8_t*)&ps_program,
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0, /* initialValueCount */
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.mode = GX2_SHADER_MODE_UNIFORM_REGISTER,
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NULL, /* initialValues */
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.samplerVarCount = 1,
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0, /* loopVarCount */
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.samplerVars = (GX2SamplerVar*) &tex_shader.sampler,
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NULL, /* loopVars */
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1, /* samplerVarCount */
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(GX2SamplerVar*) &tex_shader.sampler, /* samplerVars */
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{} /* gx2rBuffer */
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},
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},
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{ "s", GX2_SAMPLER_VAR_TYPE_SAMPLER_2D, 0 },
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.sampler = { "s", GX2_SAMPLER_VAR_TYPE_SAMPLER_2D, 0 },
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{
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.attributes = {
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{ "position", GX2_SHADER_VAR_TYPE_FLOAT2, 0, 0},
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.position = { "position", GX2_SHADER_VAR_TYPE_FLOAT2, 0, 0},
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{ "tex_coord_in", GX2_SHADER_VAR_TYPE_FLOAT2, 0, 1}
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.tex_coord = { "tex_coord_in", GX2_SHADER_VAR_TYPE_FLOAT2, 0, 1}
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},
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},
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{
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.attribute_stream = {
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{
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.position = {
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0, 0, 0, GX2_ATTRIB_FORMAT_FLOAT_32_32,
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0, 0, 0, GX2_ATTRIB_FORMAT_FLOAT_32_32,
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GX2_ATTRIB_INDEX_PER_VERTEX, 0, GX2_COMP_SEL(_X, _Y, _0, _1), GX2_ENDIAN_SWAP_DEFAULT
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GX2_ATTRIB_INDEX_PER_VERTEX, 0, GX2_COMP_SEL(_X, _Y, _0, _1), GX2_ENDIAN_SWAP_DEFAULT
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},
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},
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{
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.tex_coord = {
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1, 1, 0, GX2_ATTRIB_FORMAT_FLOAT_32_32,
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1, 1, 0, GX2_ATTRIB_FORMAT_FLOAT_32_32,
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GX2_ATTRIB_INDEX_PER_VERTEX, 0, GX2_COMP_SEL(_X, _Y, _0, _1), GX2_ENDIAN_SWAP_DEFAULT
|
GX2_ATTRIB_INDEX_PER_VERTEX, 0, GX2_COMP_SEL(_X, _Y, _0, _1), GX2_ENDIAN_SWAP_DEFAULT
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue