diff --git a/performance.c b/performance.c
index 6d0de4f461..f6984787d7 100644
--- a/performance.c
+++ b/performance.c
@@ -146,18 +146,35 @@ void rarch_get_cpu_features(struct rarch_cpu_features *cpu)
       return;
 
    x86_cpuid(1, flags);
-   cpu->sse  = flags[3] & (1 << 25);
-   cpu->sse2 = flags[3] & (1 << 26);
+
+   if(flags[3] & (1 << 25))
+      cpu->simd |= RARCH_SIMD_SSE;
+
+   if(flags[3] & (1 << 26))
+      cpu->simd |= RARCH_SIMD_SSE2;
 
    int avx_flags = (1 << 27) | (1 << 28);
-   cpu->avx = (flags[2] & avx_flags) == avx_flags; // Is this enough?
 
-   RARCH_LOG("[CPUID]: SSE:  %d\n", cpu->sse);
-   RARCH_LOG("[CPUID]: SSE2: %d\n", cpu->sse2);
-   RARCH_LOG("[CPUID]: AVX:  %d\n", cpu->avx);
+   if((flags[2] & avx_flags) == avx_flags)
+      cpu->simd |= RARCH_SIMD_AVX;
+
+   RARCH_LOG("[CPUID]: SSE:  %d\n", (cpu->simd & RARCH_SIMD_SSE) == RARCH_SIMD_SSE);
+   RARCH_LOG("[CPUID]: SSE2: %d\n", (cpu->simd & RARCH_SIMD_SSE2) == RARCH_SIMD_SSE2);
+   RARCH_LOG("[CPUID]: AVX:  %d\n", (cpu->simd & RARCH_SIMD_AVX) == RARCH_SIMD_AVX);
 #elif defined(ANDROID) && defined(ANDROID_ARM)
    uint64_t cpu_flags = android_getCpuFeatures();
-   cpu->neon = (cpu_flags & ANDROID_CPU_ARM_FEATURE_NEON);
-   RARCH_LOG("[CPUID]: NEON: %d\n", cpu->neon);
+
+   if(cpu_flags & ANDROID_CPU_ARM_FEATURE_NEON)
+      cpu->simd |= RARCH_SIMD_NEON;
+
+   RARCH_LOG("[CPUID]: NEON: %d\n", (cpu->simd & RARCH_SIMD_NEON) == RARCH_SIMD_NEON);
+#elif defined(__CELLOS_LV2__)
+   cpu->simd |= RARCH_SIMD_VMX;
+
+   RARCH_LOG("[CPUID]: VMX: %d\n", (cpu->simd & RARCH_SIMD_VMX) == RARCH_SIMD_VMX);
+#elif defined(XBOX360)
+   cpu->simd |= RARCH_SIMD_VMX128;
+
+   RARCH_LOG("[CPUID]: VMX128: %d\n", (cpu->simd & RARCH_SIMD_VMX128) == RARCH_SIMD_VMX128);
 #endif
 }
diff --git a/performance.h b/performance.h
index a712061546..cdc3487e30 100644
--- a/performance.h
+++ b/performance.h
@@ -42,13 +42,17 @@ void rarch_perf_log(void);
 
 struct rarch_cpu_features
 {
-   bool sse;
-   bool sse2;
-   bool vmx;
-   bool avx;
-   bool neon;
+   uint32_t simd;
 };
 
+// Id values for SIMD CPU features
+#define RARCH_SIMD_SSE      (1 << 0)
+#define RARCH_SIMD_SSE2     (1 << 1)
+#define RARCH_SIMD_VMX      (1 << 2)
+#define RARCH_SIMD_VMX128   (1 << 3)
+#define RARCH_SIMD_AVX      (1 << 4)
+#define RARCH_SIMD_NEON     (1 << 5)
+
 void rarch_get_cpu_features(struct rarch_cpu_features *cpu);
 
 #ifdef PERF_TEST
diff --git a/retroarch.c b/retroarch.c
index 656c3774b8..70d61d9530 100644
--- a/retroarch.c
+++ b/retroarch.c
@@ -2594,15 +2594,15 @@ static void validate_cpu_features(void)
 } while(0)
 
 #ifdef __SSE__
-   if (!cpu.sse)
+   if ((cpu.simd & RARCH_SIMD_SSE) != RARCH_SIMD_SSE)
       FAIL_CPU("SSE");
 #endif
 #ifdef __SSE2__
-   if (!cpu.sse2)
+   if ((cpu.simd & RARCH_SIMD_SSE2) != RARCH_SIMD_SSE2)
       FAIL_CPU("SSE2");
 #endif
 #ifdef __AVX__
-   if (!cpu.avx)
+   if ((cpu.simd & RARCH_SIMD_AVX) != RARCH_SIMD_AVX)
       FAIL_CPU("AVX");
 #endif
 }