mirror of https://github.com/InoriRus/Kyty.git
PS5 graphics (#42)
This commit is contained in:
InoriRus
parent
96b0202858
commit
e110bd0f63
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@ -1,4 +1,4 @@
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version: 0.1.10.build-{build}
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version: 0.1.11.build-{build}
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image: Visual Studio 2019
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environment:
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matrix:
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@ -82,7 +82,7 @@ if (KYTY_LINKER STREQUAL LD)
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set(KYTY_LD_OPTIONS "-Wl,--image-base=0x100000000000")
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endif()
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project(Kyty${KYTY_PROJECT_NAME}${CMAKE_BUILD_TYPE}${KYTY_COMPILER} VERSION 0.1.10)
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project(Kyty${KYTY_PROJECT_NAME}${CMAKE_BUILD_TYPE}${KYTY_COMPILER} VERSION 0.1.11)
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include(src_script.cmake)
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@ -29,15 +29,21 @@ struct ColorView
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{
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uint32_t base_array_slice_index = 0;
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uint32_t last_array_slice_index = 0;
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uint32_t current_mip_level = 0;
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};
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struct ColorInfo
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{
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bool fmask_compression_enable = false;
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uint32_t fmask_compression_mode = 0;
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// uint32_t fmask_compression_mode = 0;
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bool fmask_data_compression_disable = false;
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bool fmask_one_frag_mode = false;
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bool cmask_fast_clear_enable = false;
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bool dcc_compression_enable = false;
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bool neo_mode = false;
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bool blend_clamp = false;
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bool blend_bypass = false;
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bool round_mode = false;
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uint32_t cmask_tile_mode = 0;
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uint32_t cmask_tile_mode_neo = 0;
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uint32_t format = 0;
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@ -54,14 +60,33 @@ struct ColorAttrib
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uint32_t num_fragments = 0;
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};
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struct ColorDcc
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struct ColorAttrib2
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{
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uint32_t height = 0;
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uint32_t width = 0;
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uint32_t num_mip_levels = 0;
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};
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struct ColorAttrib3
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{
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uint32_t depth = 0;
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uint32_t tile_mode = 0;
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uint32_t dimension = 0;
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bool cmask_pipe_aligned = false;
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bool dcc_pipe_aligned = false;
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};
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struct ColorDccControl
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{
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uint32_t max_uncompressed_block_size = 0;
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uint32_t max_compressed_block_size = 0;
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uint32_t min_compressed_block_size = 0;
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uint32_t color_transform = 0;
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bool enable_overwrite_combiner = false;
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bool force_independent_blocks = false;
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bool dcc_clear_key_enable = false;
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bool overwrite_combiner_disable = false;
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bool independent_64b_blocks = false;
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bool independent_128b_blocks = false;
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bool data_write_on_dcc_clear_to_reg = false;
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};
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struct ColorCmask
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@ -113,7 +138,9 @@ struct RenderTarget
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ColorView view;
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ColorInfo info;
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ColorAttrib attrib;
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ColorDcc dcc;
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ColorAttrib2 attrib2;
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ColorAttrib3 attrib3;
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ColorDccControl dcc;
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ColorCmask cmask;
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ColorCmaskSlice cmask_slice;
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ColorFmask fmask;
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@ -124,23 +151,29 @@ struct RenderTarget
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ColorSize size;
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};
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struct DepthRenderTargetZInfo
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struct DepthZInfo
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{
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t num_samples = 0;
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uint32_t zrange_precision = 0;
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bool tile_surface_enable = false;
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bool expclear_enabled = false;
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uint32_t zrange_precision = 0;
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bool embedded_sample_locations = false;
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bool partially_resident = false;
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uint8_t num_mip_levels = 0;
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uint8_t plane_compression = 0;
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};
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struct DepthRenderTargetStencilInfo
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struct DepthStencilInfo
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{
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t tile_split = 0;
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bool expclear_enabled = false;
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bool tile_stencil_disable = false;
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bool texture_compatible_stencil = false;
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bool partially_resident = false;
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};
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struct DepthRenderTargetDepthInfo
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@ -154,10 +187,19 @@ struct DepthRenderTargetDepthInfo
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uint32_t num_banks = 0;
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};
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struct DepthRenderTargetDepthView
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struct DepthDepthView
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{
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uint32_t slice_start = 0;
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uint32_t slice_max = 0;
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uint8_t current_mip_level = 0;
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bool depth_write_disable = false;
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bool stencil_write_disable = false;
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};
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struct DepthDepthSizeXY
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{
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uint16_t x_max = 0;
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uint16_t y_max = 0;
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};
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struct DepthRenderTargetHTileSurface
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@ -173,10 +215,11 @@ struct DepthRenderTargetHTileSurface
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struct DepthRenderTarget
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{
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DepthRenderTargetZInfo z_info;
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DepthRenderTargetStencilInfo stencil_info;
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DepthZInfo z_info;
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DepthStencilInfo stencil_info;
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DepthDepthView depth_view;
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DepthDepthSizeXY size;
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DepthRenderTargetDepthInfo depth_info;
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DepthRenderTargetDepthView depth_view;
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DepthRenderTargetHTileSurface htile_surface;
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uint64_t z_read_base_addr = 0;
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@ -228,6 +271,8 @@ struct DepthControl
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bool backface_enable = false;
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uint8_t stencilfunc = 0;
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uint8_t stencilfunc_bf = 0;
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bool color_writes_on_depth_fail_enable = false;
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bool color_writes_on_depth_pass_disable = false;
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};
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struct StencilControl
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@ -374,29 +419,66 @@ struct ScreenViewport
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float guard_band_vert_discard = 0.0f;
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};
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struct VsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool ieee_mode = false;
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uint8_t vgpr_component_count = 0;
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bool cu_group_enable = false;
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bool require_forward_progress = false;
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bool fp16_overflow = false;
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};
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struct VsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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bool offchip_lds = false;
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bool streamout_enabled = false;
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uint8_t shared_vgprs = 0;
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};
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struct VsStageRegisters
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{
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uint32_t m_spiShaderPgmLoVs = 0;
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uint32_t m_spiShaderPgmHiVs = 0;
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uint32_t m_spiShaderPgmRsrc1Vs = 0;
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uint32_t m_spiShaderPgmRsrc2Vs = 0;
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uint64_t data_addr = 0;
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VsShaderResource1 rsrc1;
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VsShaderResource2 rsrc2;
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};
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[[nodiscard]] uint64_t GetGpuAddress() const;
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[[nodiscard]] bool GetStreamoutEnabled() const;
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[[nodiscard]] uint32_t GetSgprCount() const;
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[[nodiscard]] uint32_t GetInputComponentsCount() const;
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[[nodiscard]] uint32_t GetUnknown1() const;
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[[nodiscard]] uint32_t GetUnknown2() const;
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struct PsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool debug_mode = false;
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bool ieee_mode = false;
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bool cu_group_disable = false;
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bool require_forward_progress = false;
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bool fp16_overflow = false;
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};
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struct PsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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bool wave_cnt_en = false;
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uint8_t extra_lds_size = 0;
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bool raster_ordered_shading = false;
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uint8_t shared_vgprs = 0;
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};
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struct PsStageRegisters
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{
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uint64_t data_addr = 0;
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t scratch_en = 0;
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uint8_t user_sgpr = 0;
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uint8_t wave_cnt_en = 0;
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PsShaderResource1 rsrc1;
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PsShaderResource2 rsrc2;
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uint64_t chksum = 0;
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};
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struct CsStageRegisters
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@ -419,6 +501,45 @@ struct CsStageRegisters
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uint8_t lds_size = 0;
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};
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struct EsStageRegisters
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{
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uint64_t data_addr = 0;
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};
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struct GsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool debug_mode = false;
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bool ieee_mode = false;
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bool cu_group_enable = false;
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bool require_forward_progress = false;
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bool lds_configuration = false;
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uint8_t gs_vgpr_component_count = 0;
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bool fp16_overflow = false;
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};
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struct GsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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uint8_t es_vgpr_component_count = 0;
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bool offchip_lds = false;
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uint8_t lds_size = 0;
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uint8_t shared_vgprs = 0;
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};
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struct GsStageRegisters
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{
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uint64_t data_addr = 0;
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GsShaderResource1 rsrc1;
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GsShaderResource2 rsrc2;
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uint64_t chksum = 0;
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};
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struct ShaderRegisters
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{
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uint32_t m_spiVsOutConfig = 0;
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@ -472,9 +593,12 @@ struct UserSgprInfo
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struct VertexShaderInfo
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{
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VsStageRegisters vs_regs;
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EsStageRegisters es_regs;
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GsStageRegisters gs_regs;
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uint32_t vs_shader_modifier = 0;
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uint32_t vs_embedded_id = 0;
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UserSgprInfo vs_user_sgpr;
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UserSgprInfo gs_user_sgpr;
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bool vs_embedded = false;
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};
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@ -493,6 +617,19 @@ struct ComputeShaderInfo
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UserSgprInfo cs_user_sgpr;
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};
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struct GeControl
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{
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uint16_t primitive_group_size = 0;
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uint16_t vertex_group_size = 0;
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};
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struct GeUserVgprEn
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{
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bool vgpr1 = false;
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bool vgpr2 = false;
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bool vgpr3 = false;
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};
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class Context
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{
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public:
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@ -509,7 +646,9 @@ public:
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void SetColorView(uint32_t slot, const ColorView& view) { m_render_targets[slot].view = view; }
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void SetColorInfo(uint32_t slot, const ColorInfo& info) { m_render_targets[slot].info = info; }
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void SetColorAttrib(uint32_t slot, const ColorAttrib& attrib) { m_render_targets[slot].attrib = attrib; }
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void SetColorDcc(uint32_t slot, const ColorDcc& dcc) { m_render_targets[slot].dcc = dcc; }
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void SetColorAttrib2(uint32_t slot, const ColorAttrib2& attrib2) { m_render_targets[slot].attrib2 = attrib2; }
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void SetColorAttrib3(uint32_t slot, const ColorAttrib3& attrib3) { m_render_targets[slot].attrib3 = attrib3; }
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void SetColorDccControl(uint32_t slot, const ColorDccControl& dcc) { m_render_targets[slot].dcc = dcc; }
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void SetColorCmask(uint32_t slot, const ColorCmask& cmask) { m_render_targets[slot].cmask = cmask; }
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void SetColorCmaskSlice(uint32_t slot, const ColorCmaskSlice& cmask_slice) { m_render_targets[slot].cmask_slice = cmask_slice; }
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void SetColorFmask(uint32_t slot, const ColorFmask& fmask) { m_render_targets[slot].fmask = fmask; }
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@ -531,16 +670,27 @@ public:
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void SetDepthRenderTarget(const DepthRenderTarget& target) { m_depth_render_target = target; }
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[[nodiscard]] const DepthRenderTarget& GetDepthRenderTarget() const { return m_depth_render_target; }
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void SetDepthRenderTargetZInfo(const DepthRenderTargetZInfo& info) { m_depth_render_target.z_info = info; }
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[[nodiscard]] const DepthRenderTargetZInfo& GetDepthRenderTargetZInfo() const { return m_depth_render_target.z_info; }
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void SetDepthRenderTargetStencilInfo(const DepthRenderTargetStencilInfo& info) { m_depth_render_target.stencil_info = info; }
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[[nodiscard]] const DepthRenderTargetStencilInfo& GetDepthRenderTargetStencilInfo() const { return m_depth_render_target.stencil_info; }
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void SetDepthZInfo(const DepthZInfo& info) { m_depth_render_target.z_info = info; }
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[[nodiscard]] const DepthZInfo& GetDepthZInfo() const { return m_depth_render_target.z_info; }
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void SetDepthStencilInfo(const DepthStencilInfo& info) { m_depth_render_target.stencil_info = info; }
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[[nodiscard]] const DepthStencilInfo& GetDepthStencilInfo() const { return m_depth_render_target.stencil_info; }
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void SetDepthZReadBase(uint64_t addr) { m_depth_render_target.z_read_base_addr = addr; }
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void SetDepthStencilReadBase(uint64_t addr) { m_depth_render_target.stencil_read_base_addr = addr; }
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void SetDepthZWriteBase(uint64_t addr) { m_depth_render_target.z_write_base_addr = addr; }
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void SetDepthStencilWriteBase(uint64_t addr) { m_depth_render_target.stencil_write_base_addr = addr; }
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void SetDepthHTileDataBase(uint64_t addr) { m_depth_render_target.htile_data_base_addr = addr; }
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void SetDepthDepthView(const DepthDepthView& view) { m_depth_render_target.depth_view = view; }
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[[nodiscard]] const DepthDepthView& GetDepthDepthView() const { return m_depth_render_target.depth_view; }
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void SetDepthDepthSizeXY(const DepthDepthSizeXY& size) { m_depth_render_target.size = size; }
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[[nodiscard]] const DepthDepthSizeXY& GetDepthDepthSizeXY() const { return m_depth_render_target.size; }
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void SetViewportZ(uint32_t viewport_id, float zmin, float zmax)
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{
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m_screen_viewport.viewports[viewport_id].zmin = zmin;
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m_screen_viewport.viewports[viewport_id].zmax = zmax;
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}
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void SetViewportZMin(uint32_t viewport_id, float zmin) { m_screen_viewport.viewports[viewport_id].zmin = zmin; }
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void SetViewportZMax(uint32_t viewport_id, float zmax) { m_screen_viewport.viewports[viewport_id].zmax = zmax; }
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void SetViewportScaleOffset(uint32_t viewport_id, float xscale, float xoffset, float yscale, float yoffset, float zscale, float zoffset)
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{
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m_screen_viewport.viewports[viewport_id].xscale = xscale;
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@ -550,6 +700,31 @@ public:
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m_screen_viewport.viewports[viewport_id].zscale = zscale;
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m_screen_viewport.viewports[viewport_id].zoffset = zoffset;
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}
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void SetViewportXScale(uint32_t viewport_id, float xscale) { m_screen_viewport.viewports[viewport_id].xscale = xscale; }
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void SetViewportXOffset(uint32_t viewport_id, float xoffset) { m_screen_viewport.viewports[viewport_id].xoffset = xoffset; }
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void SetViewportYScale(uint32_t viewport_id, float yscale) { m_screen_viewport.viewports[viewport_id].yscale = yscale; }
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void SetViewportYOffset(uint32_t viewport_id, float yoffset) { m_screen_viewport.viewports[viewport_id].yoffset = yoffset; }
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void SetViewportZScale(uint32_t viewport_id, float zscale) { m_screen_viewport.viewports[viewport_id].zscale = zscale; }
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void SetViewportZOffset(uint32_t viewport_id, float zoffset) { m_screen_viewport.viewports[viewport_id].zoffset = zoffset; }
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void SetViewportScissor(uint32_t viewport_id, int left, int top, int right, int bottom, bool window_offset_enable)
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{
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m_screen_viewport.viewports[viewport_id].viewport_scissor_left = left;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_top = top;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_right = right;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_bottom = bottom;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_window_offset_enable = window_offset_enable;
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}
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void SetViewportScissorTL(uint32_t viewport_id, int left, int top, bool window_offset_enable)
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{
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m_screen_viewport.viewports[viewport_id].viewport_scissor_left = left;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_top = top;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_window_offset_enable = window_offset_enable;
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}
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void SetViewportScissorBR(uint32_t viewport_id, int right, int bottom)
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{
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m_screen_viewport.viewports[viewport_id].viewport_scissor_right = right;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_bottom = bottom;
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}
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void SetViewportTransformControl(uint32_t control) { m_screen_viewport.transform_control = control; }
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void SetScreenScissor(int left, int top, int right, int bottom)
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{
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@ -688,8 +863,16 @@ public:
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void SetPrimitiveType(uint32_t prim_type) { m_prim_type = prim_type; }
|
||||
[[nodiscard]] uint32_t GetPrimType() const { return m_prim_type; }
|
||||
|
||||
[[nodiscard]] const GeControl& GetGeControl() const { return m_ge_cntl; }
|
||||
void SetGeControl(const GeControl& control) { m_ge_cntl = control; }
|
||||
[[nodiscard]] const GeUserVgprEn& GetGeUserVgprEn() const { return m_ge_user_vgpr_en; }
|
||||
void SetGeUserVgprEn(const GeUserVgprEn& en) { m_ge_user_vgpr_en = en; }
|
||||
|
||||
private:
|
||||
uint32_t m_prim_type = 0;
|
||||
|
||||
GeControl m_ge_cntl;
|
||||
GeUserVgprEn m_ge_user_vgpr_en;
|
||||
};
|
||||
|
||||
class Shader
|
||||
|
|
@ -702,42 +885,63 @@ public:
|
|||
|
||||
void Reset() { *this = Shader(); }
|
||||
|
||||
void SetVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
void SetVsShaderModifier(uint32_t shader_modifier) { m_vs.vs_shader_modifier = shader_modifier; }
|
||||
void SetVsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_vs.vs_regs = vs_regs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_regs.data_addr = addr;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsShaderResource1(const VsShaderResource1& rsrc1)
|
||||
{
|
||||
m_vs.vs_regs.rsrc1 = rsrc1;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsShaderResource2(const VsShaderResource2& rsrc2)
|
||||
{
|
||||
m_vs.vs_regs.rsrc2 = rsrc2;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
|
||||
void UpdateVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_regs.m_spiShaderPgmLoVs = vs_regs.m_spiShaderPgmLoVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmHiVs = vs_regs.m_spiShaderPgmHiVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc1Vs = vs_regs.m_spiShaderPgmRsrc1Vs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc2Vs = vs_regs.m_spiShaderPgmRsrc2Vs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsEmbedded(uint32_t id, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_embedded_id = id;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = true;
|
||||
}
|
||||
|
||||
void SetPsShader(const PsStageRegisters& ps_regs)
|
||||
void SetEsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_ps.ps_regs = ps_regs;
|
||||
m_vs.es_regs.data_addr = addr;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetGsShaderResource1(const GsShaderResource1& rsrc1)
|
||||
{
|
||||
m_vs.gs_regs.rsrc1 = rsrc1;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetGsShaderResource2(const GsShaderResource2& rsrc2)
|
||||
{
|
||||
m_vs.gs_regs.rsrc2 = rsrc2;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetGsShaderChksum(uint32_t value)
|
||||
{
|
||||
m_vs.gs_regs.chksum <<= 32u;
|
||||
m_vs.gs_regs.chksum |= value;
|
||||
}
|
||||
|
||||
void SetPsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_ps.ps_regs.data_addr = addr;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void UpdatePsShader(const PsStageRegisters& ps_regs)
|
||||
void SetPsShaderResource1(const PsShaderResource1& rsrc1)
|
||||
{
|
||||
m_ps.ps_regs.data_addr = ps_regs.data_addr;
|
||||
m_ps.ps_regs.vgprs = ps_regs.vgprs;
|
||||
m_ps.ps_regs.sgprs = ps_regs.sgprs;
|
||||
m_ps.ps_regs.scratch_en = ps_regs.scratch_en;
|
||||
m_ps.ps_regs.user_sgpr = ps_regs.user_sgpr;
|
||||
m_ps.ps_regs.wave_cnt_en = ps_regs.wave_cnt_en;
|
||||
m_ps.ps_regs.rsrc1 = rsrc1;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsShaderResource2(const PsShaderResource2& rsrc2)
|
||||
{
|
||||
m_ps.ps_regs.rsrc2 = rsrc2;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsEmbedded(uint32_t id)
|
||||
|
|
@ -745,6 +949,11 @@ public:
|
|||
m_ps.ps_embedded_id = id;
|
||||
m_ps.ps_embedded = true;
|
||||
}
|
||||
void SetPsShaderChksum(uint32_t value)
|
||||
{
|
||||
m_ps.ps_regs.chksum <<= 32u;
|
||||
m_ps.ps_regs.chksum |= value;
|
||||
}
|
||||
|
||||
void SetCsShader(const CsStageRegisters& cs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
|
|
@ -770,6 +979,12 @@ public:
|
|||
m_cs.cs_user_sgpr.type[id] = type;
|
||||
m_cs.cs_user_sgpr.count = ((id + 1) > m_cs.cs_user_sgpr.count ? (id + 1) : m_cs.cs_user_sgpr.count);
|
||||
}
|
||||
void SetGsUserSgpr(uint32_t id, uint32_t value, UserSgprType type)
|
||||
{
|
||||
m_vs.gs_user_sgpr.value[id] = value;
|
||||
m_vs.gs_user_sgpr.type[id] = type;
|
||||
m_vs.gs_user_sgpr.count = ((id + 1) > m_vs.gs_user_sgpr.count ? (id + 1) : m_vs.gs_user_sgpr.count);
|
||||
}
|
||||
|
||||
[[nodiscard]] const PixelShaderInfo& GetPs() const { return m_ps; }
|
||||
[[nodiscard]] const VertexShaderInfo& GetVs() const { return m_vs; }
|
||||
|
|
@ -781,36 +996,6 @@ private:
|
|||
ComputeShaderInfo m_cs;
|
||||
};
|
||||
|
||||
inline uint64_t VsStageRegisters::GetGpuAddress() const
|
||||
{
|
||||
return (static_cast<uint64_t>(m_spiShaderPgmLoVs) << 8u) | (static_cast<uint64_t>(m_spiShaderPgmHiVs) << 40u);
|
||||
}
|
||||
|
||||
inline bool VsStageRegisters::GetStreamoutEnabled() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc2Vs & 0x00001000u) != 0u;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetSgprCount() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc1Vs >> 6u) & 0xfu;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetInputComponentsCount() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc1Vs >> 24u) & 0x3u;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetUnknown1() const
|
||||
{
|
||||
return m_spiShaderPgmRsrc1Vs & 0xfcfffc3fu;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetUnknown2() const
|
||||
{
|
||||
return m_spiShaderPgmRsrc2Vs & 0xFFFFEFFFu;
|
||||
}
|
||||
|
||||
} // namespace Kyty::Libs::Graphics::HW
|
||||
|
||||
#endif // KYTY_EMU_ENABLED
|
||||
|
|
|
|||
|
|
@ -18,14 +18,16 @@ public:
|
|||
static constexpr int PARAM_HEIGHT = 2;
|
||||
static constexpr int PARAM_HTILE = 3;
|
||||
static constexpr int PARAM_NEO = 4;
|
||||
static constexpr int PARAM_USAGE = 5;
|
||||
|
||||
DepthStencilBufferObject(uint64_t vk_format, uint32_t width, uint32_t height, bool htile, bool neo)
|
||||
DepthStencilBufferObject(uint64_t vk_format, uint32_t width, uint32_t height, bool htile, bool neo, bool sampled)
|
||||
{
|
||||
params[PARAM_FORMAT] = vk_format;
|
||||
params[PARAM_WIDTH] = width;
|
||||
params[PARAM_HEIGHT] = height;
|
||||
params[PARAM_HTILE] = htile ? 1 : 0;
|
||||
params[PARAM_NEO] = neo ? 1 : 0;
|
||||
params[PARAM_USAGE] = sampled ? 1 : 0;
|
||||
check_hash = false;
|
||||
type = Graphics::GpuMemoryObjectType::DepthStencilBuffer;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -123,14 +123,30 @@ constexpr uint32_t DB_COUNT_CONTROL = 0x1;
|
|||
constexpr uint32_t DB_DEPTH_VIEW = 0x2;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_SHIFT = 11;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_MASK = 0x3;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_SHIFT = 24;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_SHIFT = 25;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_MIPID_SHIFT = 26;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_MIPID_MASK = 0xF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_SHIFT = 30;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_MASK = 0x3;
|
||||
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE = 0x3;
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE2 = 0x4;
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
|
||||
constexpr uint32_t PS_SHADER_SAMPLE_EXCLUSION_MASK = 0x6;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_MASK = 0x3FFF;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_SHIFT = 16;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_MASK = 0x3FFF;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
|
||||
|
||||
|
|
@ -177,8 +193,18 @@ constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT = 0;
|
|||
constexpr uint32_t DB_Z_INFO_FORMAT_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_SHIFT = 2;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_SHIFT = 11;
|
||||
constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
|
||||
constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_MAXMIP_SHIFT = 16;
|
||||
constexpr uint32_t DB_Z_INFO_MAXMIP_MASK = 0xF;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_SHIFT = 20;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_SHIFT = 23;
|
||||
constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_MASK = 0xF;
|
||||
constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
|
||||
constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_SHIFT = 31;
|
||||
|
|
@ -187,8 +213,16 @@ constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_MASK = 0x1;
|
|||
constexpr uint32_t DB_STENCIL_INFO = 0x11;
|
||||
constexpr uint32_t DB_STENCIL_INFO_FORMAT_SHIFT = 0;
|
||||
constexpr uint32_t DB_STENCIL_INFO_FORMAT_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_SHIFT = 11;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
|
||||
constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_SHIFT = 13;
|
||||
constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_MASK = 0x7;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_SHIFT = 20;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_MASK = 0x1;
|
||||
|
||||
|
|
@ -246,9 +280,25 @@ constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_SHIFT = 16;
|
|||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_MASK = 0x7FFF;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_SHIFT = 31;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_MASK = 0x7FFF;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_15_TL = 0xB2;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_15_BR = 0xB3;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_15 = 0xD2;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_15 = 0xD3;
|
||||
constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
|
||||
constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
|
||||
constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
|
||||
|
|
@ -301,6 +351,12 @@ constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
|
|||
constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE_15 = 0x169;
|
||||
constexpr uint32_t PA_CL_VPORT_XOFFSET_15 = 0x16A;
|
||||
constexpr uint32_t PA_CL_VPORT_YSCALE_15 = 0x16B;
|
||||
constexpr uint32_t PA_CL_VPORT_YOFFSET_15 = 0x16C;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE_15 = 0x16D;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET_15 = 0x16E;
|
||||
constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
|
||||
constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
|
||||
constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
|
||||
|
|
@ -356,6 +412,10 @@ constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT = 8;
|
|||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT = 20;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_SHIFT = 30;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_SHIFT = 31;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t DB_EQAA = 0x201;
|
||||
constexpr uint32_t DB_EQAA_MAX_ANCHOR_SAMPLES_SHIFT = 0;
|
||||
|
|
@ -539,21 +599,124 @@ constexpr uint32_t PA_SC_BINNER_CNTL_1 = 0x312;
|
|||
constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
|
||||
constexpr uint32_t PA_SC_NGG_MODE_CNTL = 0x314;
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_SHIFT = 8;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_SHIFT = 11;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_SHIFT = 16;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_SHIFT = 18;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_SHIFT = 27;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_SHIFT = 29;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_SHIFT = 31;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_SHIFT = 12;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_SHIFT = 17;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_SHIFT = 1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_SHIFT = 4;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_SHIFT = 7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_SHIFT = 9;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_SHIFT = 20;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR7_BASE = 0x381;
|
||||
constexpr uint32_t CB_COLOR7_VIEW = 0x384;
|
||||
constexpr uint32_t CB_COLOR7_INFO = 0x385;
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB = 0x386;
|
||||
constexpr uint32_t CB_COLOR7_DCC_CONTROL = 0x387;
|
||||
constexpr uint32_t CB_COLOR7_CMASK = 0x388;
|
||||
constexpr uint32_t CB_COLOR7_FMASK = 0x38A;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD0 = 0x38C;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD1 = 0x38D;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE = 0x38E;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR7_BASE_EXT = 0x397;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR7_CMASK_BASE_EXT = 0x39F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR7_FMASK_BASE_EXT = 0x3A7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE_EXT = 0x3AF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB2 = 0x3B7;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_SHIFT = 24;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_SHIFT = 30;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB3 = 0x3BF;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
|
|
@ -577,6 +740,22 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
|||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0;
|
||||
|
|
@ -584,11 +763,58 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1;
|
|||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_SHIFT = 8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_VS = 0x48;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_VS = 0x49;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS = 0x4A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS = 0x4B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS = 0x80;
|
||||
|
|
@ -598,9 +824,51 @@ constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
|
|||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS = 0x87;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_GS = 0x88;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_GS = 0x89;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_SHIFT = 16;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_SHIFT = 18;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_SHIFT = 19;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_15 = 0x9B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9;
|
||||
|
|
@ -671,17 +939,34 @@ constexpr uint32_t SH_NUM = 0x2FF + 1;
|
|||
/* User config registers */
|
||||
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_SHIFT = 0;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_MASK = 0x3F;
|
||||
|
||||
constexpr uint32_t VGT_OBJECT_ID = 0x248;
|
||||
constexpr uint32_t GE_INDX_OFFSET = 0x24A;
|
||||
constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
|
||||
constexpr uint32_t VGT_HS_OFFCHIP_PARAM = 0x24F;
|
||||
constexpr uint32_t VGT_TF_MEMORY_BASE = 0x250;
|
||||
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_SHIFT = 0;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_MASK = 0x1FF;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_SHIFT = 9;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_SHIFT = 0;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_SHIFT = 1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_SHIFT = 2;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
|
|
|
|||
|
|
@ -823,6 +823,7 @@ Vector<uint32_t> ShaderRecompileVS(const ShaderCode& code, const ShaderVertexInp
|
|||
Vector<uint32_t> ShaderRecompilePS(const ShaderCode& code, const ShaderPixelInputInfo* input_info);
|
||||
Vector<uint32_t> ShaderRecompileCS(const ShaderCode& code, const ShaderComputeInputInfo* input_info);
|
||||
bool ShaderIsDisabled(uint64_t addr);
|
||||
bool ShaderIsDisabled2(uint64_t addr, uint64_t chksum);
|
||||
void ShaderDisable(uint64_t id);
|
||||
void ShaderInjectDebugPrintf(uint64_t id, const ShaderDebugPrintf& cmd);
|
||||
|
||||
|
|
|
|||
|
|
@ -1556,13 +1556,34 @@ int KYTY_SYSV_ABI GraphicsCreateShader(Shader** dst, void* header, const volatil
|
|||
|
||||
h->code = code;
|
||||
|
||||
dbg_dump_shader(h);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(h->file_header != 0x34333231);
|
||||
EXIT_NOT_IMPLEMENTED(h->version != 0x00000018);
|
||||
|
||||
auto base = reinterpret_cast<uint64_t>(code);
|
||||
|
||||
if (h->type == 2 && h->num_sh_registers >= 2 && h->sh_registers[0].offset == Pm4::SPI_SHADER_PGM_LO_ES &&
|
||||
h->sh_registers[1].offset == Pm4::SPI_SHADER_PGM_HI_ES)
|
||||
{
|
||||
h->sh_registers[0].offset = Pm4::SPI_SHADER_PGM_LO_ES;
|
||||
h->sh_registers[0].value = ((base >> 8u) & 0xffffffffu);
|
||||
h->sh_registers[1].offset = Pm4::SPI_SHADER_PGM_HI_ES;
|
||||
h->sh_registers[1].value = ((base >> 40u) & 0x000000ffu);
|
||||
} else if (h->type == 1 && h->num_sh_registers >= 2 && h->sh_registers[0].offset == Pm4::SPI_SHADER_PGM_LO_PS &&
|
||||
h->sh_registers[1].offset == Pm4::SPI_SHADER_PGM_HI_PS)
|
||||
{
|
||||
h->sh_registers[0].offset = Pm4::SPI_SHADER_PGM_LO_PS;
|
||||
h->sh_registers[0].value = ((base >> 8u) & 0xffffffffu);
|
||||
h->sh_registers[1].offset = Pm4::SPI_SHADER_PGM_HI_PS;
|
||||
h->sh_registers[1].value = ((base >> 40u) & 0x000000ffu);
|
||||
} else
|
||||
{
|
||||
EXIT("invalid shader\n");
|
||||
}
|
||||
|
||||
*dst = h;
|
||||
|
||||
dbg_dump_shader(h);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -1774,6 +1795,10 @@ uint32_t* KYTY_SYSV_ABI GraphicsCbSetShRegisterRangeDirect(CommandBuffer* buf, u
|
|||
|
||||
buf->DbgDump();
|
||||
|
||||
auto* marker = buf->AllocateDW(2);
|
||||
marker[0] = KYTY_PM4(2, Pm4::IT_NOP, Pm4::R_ZERO);
|
||||
marker[1] = 0x6875000d;
|
||||
|
||||
auto* cmd = buf->AllocateDW(num_values + 2);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd == nullptr);
|
||||
|
|
@ -1815,23 +1840,22 @@ uint32_t* KYTY_SYSV_ABI GraphicsCbReleaseMem(CommandBuffer* buf, uint8_t action,
|
|||
EXIT_NOT_IMPLEMENTED(data_sel != 2);
|
||||
EXIT_NOT_IMPLEMENTED(gds_offset != 0);
|
||||
EXIT_NOT_IMPLEMENTED(gds_size != 1);
|
||||
EXIT_NOT_IMPLEMENTED(interrupt != 0);
|
||||
EXIT_NOT_IMPLEMENTED(interrupt_ctx_id != 0);
|
||||
|
||||
buf->DbgDump();
|
||||
|
||||
auto* cmd = buf->AllocateDW(10);
|
||||
auto* cmd = buf->AllocateDW(7);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd == nullptr);
|
||||
|
||||
cmd[0] = KYTY_PM4(10, Pm4::IT_NOP, Pm4::R_RELEASE_MEM);
|
||||
cmd[1] = action;
|
||||
cmd[0] = KYTY_PM4(7, Pm4::IT_NOP, Pm4::R_RELEASE_MEM);
|
||||
cmd[1] = action | (static_cast<uint32_t>(cache_policy) << 8u);
|
||||
cmd[2] = gcr_cntl;
|
||||
cmd[3] = cache_policy;
|
||||
cmd[4] = static_cast<uint32_t>(reinterpret_cast<uint64_t>(address) & 0xffffffffu);
|
||||
cmd[5] = static_cast<uint32_t>((reinterpret_cast<uint64_t>(address) >> 32u) & 0xffffffffu);
|
||||
cmd[6] = static_cast<uint32_t>(data & 0xffffffffu);
|
||||
cmd[7] = static_cast<uint32_t>((data >> 32u) & 0xffffffffu);
|
||||
cmd[8] = interrupt;
|
||||
cmd[9] = interrupt_ctx_id;
|
||||
cmd[3] = static_cast<uint32_t>(reinterpret_cast<uint64_t>(address) & 0xffffffffu);
|
||||
cmd[4] = static_cast<uint32_t>((reinterpret_cast<uint64_t>(address) >> 32u) & 0xffffffffu);
|
||||
cmd[5] = static_cast<uint32_t>(data & 0xffffffffu);
|
||||
cmd[6] = static_cast<uint32_t>((data >> 32u) & 0xffffffffu);
|
||||
|
||||
return cmd;
|
||||
}
|
||||
|
|
@ -2086,26 +2110,23 @@ uint32_t* KYTY_SYSV_ABI GraphicsDcbWriteData(CommandBuffer* buf, uint8_t dst, ui
|
|||
printf("\t write_confirm = 0x%02" PRIx8 "\n", write_confirm);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(buf == nullptr);
|
||||
EXIT_NOT_IMPLEMENTED((8 + num_dwords - 2u) > 0x3fffu);
|
||||
EXIT_NOT_IMPLEMENTED((4 + num_dwords - 2u) > 0x3fffu);
|
||||
EXIT_NOT_IMPLEMENTED(data == nullptr);
|
||||
EXIT_NOT_IMPLEMENTED(address_or_offset == 0);
|
||||
|
||||
buf->DbgDump();
|
||||
|
||||
auto* cmd = buf->AllocateDW(8 + num_dwords);
|
||||
auto* cmd = buf->AllocateDW(4 + num_dwords);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd == nullptr);
|
||||
|
||||
cmd[0] = KYTY_PM4(8 + num_dwords, Pm4::IT_NOP, Pm4::R_WRITE_DATA);
|
||||
cmd[1] = dst;
|
||||
cmd[2] = cache_policy;
|
||||
cmd[3] = address_or_offset & 0xffffffffu;
|
||||
cmd[4] = (address_or_offset >> 32u) & 0xffffffffu;
|
||||
cmd[5] = num_dwords;
|
||||
cmd[6] = increment;
|
||||
cmd[7] = write_confirm;
|
||||
cmd[0] = KYTY_PM4(4 + num_dwords, Pm4::IT_NOP, Pm4::R_WRITE_DATA);
|
||||
cmd[1] = dst | (static_cast<uint32_t>(cache_policy) << 8u) | (static_cast<uint32_t>(increment) << 16u) |
|
||||
(static_cast<uint32_t>(write_confirm) << 24u);
|
||||
cmd[2] = address_or_offset & 0xffffffffu;
|
||||
cmd[3] = (address_or_offset >> 32u) & 0xffffffffu;
|
||||
|
||||
memcpy(cmd + 8, data, static_cast<size_t>(num_dwords) * 4);
|
||||
memcpy(cmd + 4, data, static_cast<size_t>(num_dwords) * 4);
|
||||
|
||||
return cmd;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -466,10 +466,27 @@ static void uc_print(const char* func, const HW::UserConfig& uc)
|
|||
{
|
||||
printf("%s\n", func);
|
||||
|
||||
const auto& ge_cntl = uc.GetGeControl();
|
||||
const auto& user_en = uc.GetGeUserVgprEn();
|
||||
|
||||
printf("\t GetPrimType() = 0x%08" PRIx32 "\n", uc.GetPrimType());
|
||||
printf("\t primitive_group_size = 0x%04" PRIx16 "\n", ge_cntl.primitive_group_size);
|
||||
printf("\t en_user_vgpr1 = %s\n", user_en.vgpr1 ? "true" : "false");
|
||||
printf("\t en_user_vgpr2 = %s\n", user_en.vgpr2 ? "true" : "false");
|
||||
printf("\t en_user_vgpr3 = %s\n", user_en.vgpr3 ? "true" : "false");
|
||||
}
|
||||
|
||||
static void uc_check(const HW::UserConfig& /*uc*/) {}
|
||||
static void uc_check(const HW::UserConfig& uc)
|
||||
{
|
||||
const auto& ge_cntl = uc.GetGeControl();
|
||||
const auto& user_en = uc.GetGeUserVgprEn();
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(ge_cntl.primitive_group_size != 0x0000);
|
||||
EXIT_NOT_IMPLEMENTED(ge_cntl.vertex_group_size != 0x0000);
|
||||
EXIT_NOT_IMPLEMENTED(user_en.vgpr1 != false);
|
||||
EXIT_NOT_IMPLEMENTED(user_en.vgpr2 != false);
|
||||
EXIT_NOT_IMPLEMENTED(user_en.vgpr3 != false);
|
||||
}
|
||||
|
||||
static void sh_print(const char* func, const HW::Shader& /*uc*/)
|
||||
{
|
||||
|
|
@ -490,8 +507,13 @@ static Core::StringList rt_print(const char* func, const HW::RenderTarget& rt)
|
|||
dst.Add(String::FromPrintf("\t slice.slice_div64_minus1 = 0x%08" PRIx32 "\n", rt.slice.slice_div64_minus1));
|
||||
dst.Add(String::FromPrintf("\t view.base_array_slice_index = 0x%08" PRIx32 "\n", rt.view.base_array_slice_index));
|
||||
dst.Add(String::FromPrintf("\t view.last_array_slice_index = 0x%08" PRIx32 "\n", rt.view.last_array_slice_index));
|
||||
dst.Add(String::FromPrintf("\t view.current_mip_level = 0x%08" PRIx32 "\n", rt.view.current_mip_level));
|
||||
dst.Add(String::FromPrintf("\t info.fmask_compression_enable = %s\n", rt.info.fmask_compression_enable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.fmask_compression_mode = 0x%08" PRIx32 "\n", rt.info.fmask_compression_mode));
|
||||
|
||||
// dst.Add(String::FromPrintf("\t info.fmask_compression_mode = 0x%08" PRIx32 "\n", rt.info.fmask_compression_mode));
|
||||
dst.Add(String::FromPrintf("\t info.fmask_data_compression_disable = %s\n", rt.info.fmask_data_compression_disable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.fmask_one_frag_mode = %s\n", rt.info.fmask_one_frag_mode ? "true" : "false"));
|
||||
|
||||
dst.Add(String::FromPrintf("\t info.cmask_fast_clear_enable = %s\n", rt.info.cmask_fast_clear_enable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.dcc_compression_enable = %s\n", rt.info.dcc_compression_enable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.neo_mode = %s\n", rt.info.neo_mode ? "true" : "false"));
|
||||
|
|
@ -500,17 +522,31 @@ static Core::StringList rt_print(const char* func, const HW::RenderTarget& rt)
|
|||
dst.Add(String::FromPrintf("\t info.format = 0x%08" PRIx32 "\n", rt.info.format));
|
||||
dst.Add(String::FromPrintf("\t info.channel_type = 0x%08" PRIx32 "\n", rt.info.channel_type));
|
||||
dst.Add(String::FromPrintf("\t info.channel_order = 0x%08" PRIx32 "\n", rt.info.channel_order));
|
||||
dst.Add(String::FromPrintf("\t info.blend_bypa = %s\n", rt.info.blend_bypass ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.blend_clamp = %s\n", rt.info.blend_clamp ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t info.round_mode = %s\n", rt.info.round_mode ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t attrib.force_dest_alpha_to_one = %s\n", rt.attrib.force_dest_alpha_to_one ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t attrib.tile_mode = 0x%08" PRIx32 "\n", rt.attrib.tile_mode));
|
||||
dst.Add(String::FromPrintf("\t attrib.fmask_tile_mode = 0x%08" PRIx32 "\n", rt.attrib.fmask_tile_mode));
|
||||
dst.Add(String::FromPrintf("\t attrib.num_samples = 0x%08" PRIx32 "\n", rt.attrib.num_samples));
|
||||
dst.Add(String::FromPrintf("\t attrib.num_fragments = 0x%08" PRIx32 "\n", rt.attrib.num_fragments));
|
||||
dst.Add(String::FromPrintf("\t attrib2.width = 0x%08" PRIx32 "\n", rt.attrib2.width));
|
||||
dst.Add(String::FromPrintf("\t attrib2.height = 0x%08" PRIx32 "\n", rt.attrib2.height));
|
||||
dst.Add(String::FromPrintf("\t attrib2.num_mip_levels = 0x%08" PRIx32 "\n", rt.attrib2.num_mip_levels));
|
||||
dst.Add(String::FromPrintf("\t attrib3.depth = 0x%08" PRIx32 "\n", rt.attrib3.depth));
|
||||
dst.Add(String::FromPrintf("\t attrib3.tile_mode = 0x%08" PRIx32 "\n", rt.attrib3.tile_mode));
|
||||
dst.Add(String::FromPrintf("\t attrib3.dimension = 0x%08" PRIx32 "\n", rt.attrib3.dimension));
|
||||
dst.Add(String::FromPrintf("\t attrib3.cmask_pipe_aligned = %s\n", rt.attrib3.cmask_pipe_aligned ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t attrib3.dcc_pipe_aligned = %s\n", rt.attrib3.dcc_pipe_aligned ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.max_uncompressed_block_size = 0x%08" PRIx32 "\n", rt.dcc.max_uncompressed_block_size));
|
||||
dst.Add(String::FromPrintf("\t dcc.max_compressed_block_size = 0x%08" PRIx32 "\n", rt.dcc.max_compressed_block_size));
|
||||
dst.Add(String::FromPrintf("\t dcc.min_compressed_block_size = 0x%08" PRIx32 "\n", rt.dcc.min_compressed_block_size));
|
||||
dst.Add(String::FromPrintf("\t dcc.color_transform = 0x%08" PRIx32 "\n", rt.dcc.color_transform));
|
||||
dst.Add(String::FromPrintf("\t dcc.enable_overwrite_combiner = %s\n", rt.dcc.enable_overwrite_combiner ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.force_independent_blocks = %s\n", rt.dcc.force_independent_blocks ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.overwrite_combiner_disable = %s\n", rt.dcc.overwrite_combiner_disable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.independent_64b_blocks = %s\n", rt.dcc.independent_64b_blocks ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.independent_128b_blocks = %s\n", rt.dcc.independent_128b_blocks ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t data_write_on_dcc_clear_to_reg = %s\n", rt.dcc.data_write_on_dcc_clear_to_reg ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t dcc.dcc_clear_key_enable = %s\n", rt.dcc.dcc_clear_key_enable ? "true" : "false"));
|
||||
dst.Add(String::FromPrintf("\t cmask.addr = 0x%016" PRIx64 "\n", rt.cmask.addr));
|
||||
dst.Add(String::FromPrintf("\t cmask_slice.slice_minus1 = 0x%08" PRIx32 "\n", rt.cmask_slice.slice_minus1));
|
||||
dst.Add(String::FromPrintf("\t fmask.addr = 0x%016" PRIx64 "\n", rt.fmask.addr));
|
||||
|
|
@ -536,13 +572,21 @@ static void rt_check(const HW::RenderTarget& rt)
|
|||
// EXIT_NOT_IMPLEMENTED(rt.slice_div64_minus1 != 0x000086ff);
|
||||
EXIT_NOT_IMPLEMENTED(rt.view.base_array_slice_index != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.view.last_array_slice_index != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.view.current_mip_level != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.fmask_compression_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.fmask_compression_mode != 0x00000000);
|
||||
|
||||
// EXIT_NOT_IMPLEMENTED(rt.info.fmask_compression_mode != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.fmask_data_compression_disable != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.fmask_one_frag_mode != false);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.cmask_fast_clear_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.dcc_compression_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(!render_to_texture && rt.info.neo_mode != Config::IsNeo());
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.cmask_tile_mode != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.cmask_tile_mode_neo != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.blend_bypass != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.info.blend_clamp != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.info.round_mode != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.format != 0x0000000a);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.channel_type != 0x00000006);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.channel_order != 0x00000001);
|
||||
|
|
@ -551,12 +595,23 @@ static void rt_check(const HW::RenderTarget& rt)
|
|||
// EXIT_NOT_IMPLEMENTED(rt.fmask_tile_mode != 0x0000000a);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib.num_samples != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib.num_fragments != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib2.width != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib2.height != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib2.num_mip_levels != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib3.depth != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib3.tile_mode != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib3.dimension != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib3.cmask_pipe_aligned != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.attrib3.dcc_pipe_aligned != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc_max_uncompressed_block_size != 0x00000002);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc.max_compressed_block_size != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.dcc.min_compressed_block_size != 0x00000000);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc.color_transform != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.dcc.enable_overwrite_combiner != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.dcc.overwrite_combiner_disable != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc.force_independent_blocks != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc.independent_128b_blocks != false);
|
||||
// EXIT_NOT_IMPLEMENTED(rt.dcc.data_write_on_dcc_clear_to_reg != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.dcc.dcc_clear_key_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(rt.cmask.addr != 0x0000000000000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.cmask_slice.slice_minus1 != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(rt.fmask.addr != 0x0000000000000000);
|
||||
|
|
@ -579,11 +634,17 @@ static void z_print(const char* func, const HW::DepthRenderTarget& z)
|
|||
printf("\t z_info.tile_surface_enable = %s\n", z.z_info.tile_surface_enable ? "true" : "false");
|
||||
printf("\t z_info.expclear_enabled = %s\n", z.z_info.expclear_enabled ? "true" : "false");
|
||||
printf("\t z_info.zrange_precision = 0x%08" PRIx32 "\n", z.z_info.zrange_precision);
|
||||
printf("\t z_info.embedded_sample_locations = %s\n", z.z_info.embedded_sample_locations ? "true" : "false");
|
||||
printf("\t z_info.partially_resident = %s\n", z.z_info.partially_resident ? "true" : "false");
|
||||
printf("\t z_info.num_mip_levels = 0x%02" PRIx8 "\n", z.z_info.num_mip_levels);
|
||||
printf("\t z_info.plane_compression = 0x%02" PRIx8 "\n", z.z_info.plane_compression);
|
||||
printf("\t stencil_info.format = 0x%08" PRIx32 "\n", z.stencil_info.format);
|
||||
printf("\t stencil_info.tile_stencil_disable = %s\n", z.stencil_info.tile_stencil_disable ? "true" : "false");
|
||||
printf("\t stencil_info.expclear_enabled = %s\n", z.stencil_info.expclear_enabled ? "true" : "false");
|
||||
printf("\t stencil_info.tile_mode_index = 0x%08" PRIx32 "\n", z.stencil_info.tile_mode_index);
|
||||
printf("\t stencil_info.tile_split = 0x%08" PRIx32 "\n", z.stencil_info.tile_split);
|
||||
printf("\t stencil_info.texture_compatible_stencil = %s\n", z.stencil_info.texture_compatible_stencil ? "true" : "false");
|
||||
printf("\t stencil_info.partially_resident = %s\n", z.stencil_info.partially_resident ? "true" : "false");
|
||||
printf("\t depth_info.addr5_swizzle_mask = 0x%08" PRIx32 "\n", z.depth_info.addr5_swizzle_mask);
|
||||
printf("\t depth_info.array_mode = 0x%08" PRIx32 "\n", z.depth_info.array_mode);
|
||||
printf("\t depth_info.pipe_config = 0x%08" PRIx32 "\n", z.depth_info.pipe_config);
|
||||
|
|
@ -593,6 +654,9 @@ static void z_print(const char* func, const HW::DepthRenderTarget& z)
|
|||
printf("\t depth_info.num_banks = 0x%08" PRIx32 "\n", z.depth_info.num_banks);
|
||||
printf("\t depth_view.slice_start = 0x%08" PRIx32 "\n", z.depth_view.slice_start);
|
||||
printf("\t depth_view.slice_max = 0x%08" PRIx32 "\n", z.depth_view.slice_max);
|
||||
printf("\t depth_view.current_mip_level = 0x%02" PRIx8 "\n", z.depth_view.current_mip_level);
|
||||
printf("\t depth_view.depth_write_disable = %s\n", z.depth_view.depth_write_disable ? "true" : "false");
|
||||
printf("\t depth_view.stencil_write_disable = %s\n", z.depth_view.stencil_write_disable ? "true" : "false");
|
||||
printf("\t htile_surface.linear = 0x%08" PRIx32 "\n", z.htile_surface.linear);
|
||||
printf("\t htile_surface.full_cache = 0x%08" PRIx32 "\n", z.htile_surface.full_cache);
|
||||
printf("\t htile_surface.htile_uses_preload_win = 0x%08" PRIx32 "\n", z.htile_surface.htile_uses_preload_win);
|
||||
|
|
@ -610,6 +674,8 @@ static void z_print(const char* func, const HW::DepthRenderTarget& z)
|
|||
printf("\t htile_data_base_addr = 0x%016" PRIx64 "\n", z.htile_data_base_addr);
|
||||
printf("\t width = 0x%08" PRIx32 "\n", z.width);
|
||||
printf("\t height = 0x%08" PRIx32 "\n", z.height);
|
||||
printf("\t size.x_max = 0x%04" PRIx16 "\n", z.size.x_max);
|
||||
printf("\t size.y_max = 0x%04" PRIx16 "\n", z.size.y_max);
|
||||
}
|
||||
|
||||
// NOLINTNEXTLINE(readability-function-cognitive-complexity)
|
||||
|
|
@ -623,6 +689,10 @@ static void z_check(const HW::DepthRenderTarget& z)
|
|||
EXIT_NOT_IMPLEMENTED(z.z_info.tile_surface_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.expclear_enabled != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.zrange_precision != 0);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.embedded_sample_locations != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.partially_resident != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.num_mip_levels != 0);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.plane_compression != 0);
|
||||
} else
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.format != 0x00000003);
|
||||
|
|
@ -631,22 +701,30 @@ static void z_check(const HW::DepthRenderTarget& z)
|
|||
// EXIT_NOT_IMPLEMENTED(z.z_info.tile_surface_enable != true);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.expclear_enabled != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.zrange_precision != 0x00000001);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.embedded_sample_locations != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.partially_resident != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.num_mip_levels != 0);
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.plane_compression != 0);
|
||||
}
|
||||
|
||||
if (z.stencil_info.format == 0)
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.format != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.format != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_stencil_disable != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.expclear_enabled != false);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_mode_index != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_split != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.texture_compatible_stencil != true);
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.partially_resident != false);
|
||||
} else
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.format != 0x00000001);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.format != 0x00000001);
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_stencil_disable != true);
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.expclear_enabled != false);
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_mode_index != (Config::IsNeo() ? 0x00000002 : 0));
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.tile_split != (Config::IsNeo() ? 0x00000002 : 0));
|
||||
// EXIT_NOT_IMPLEMENTED(z.stencil_info.texture_compatible_stencil != true);
|
||||
EXIT_NOT_IMPLEMENTED(z.stencil_info.partially_resident != false);
|
||||
}
|
||||
|
||||
if (z.z_info.format != 0 || z.stencil_info.format != 0)
|
||||
|
|
@ -660,6 +738,9 @@ static void z_check(const HW::DepthRenderTarget& z)
|
|||
// EXIT_NOT_IMPLEMENTED(z.depth_info.num_banks != (Config::IsNeo() ? 0x00000002 : 3));
|
||||
EXIT_NOT_IMPLEMENTED(z.depth_view.slice_start != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(z.depth_view.slice_max != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(z.depth_view.current_mip_level != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(z.depth_view.depth_write_disable != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.depth_view.stencil_write_disable != false);
|
||||
EXIT_NOT_IMPLEMENTED(z.htile_surface.linear != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(z.htile_surface.full_cache != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(z.htile_surface.htile_uses_preload_win != 0x00000000);
|
||||
|
|
@ -677,6 +758,8 @@ static void z_check(const HW::DepthRenderTarget& z)
|
|||
// EXIT_NOT_IMPLEMENTED(z.htile_data_base_addr == 0);
|
||||
// EXIT_NOT_IMPLEMENTED(z.width != 0x00000780);
|
||||
// EXIT_NOT_IMPLEMENTED(z.height != 0x00000438);
|
||||
EXIT_NOT_IMPLEMENTED(z.size.x_max != 0);
|
||||
EXIT_NOT_IMPLEMENTED(z.size.y_max != 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -820,6 +903,8 @@ static void d_print(const char* func, const HW::DepthControl& c, const HW::Stenc
|
|||
printf("\t backface_enable = %s\n", c.backface_enable ? "true" : "false");
|
||||
printf("\t stencilfunc = %" PRIu8 "\n", c.stencilfunc);
|
||||
printf("\t stencilfunc_bf = %" PRIu8 "\n", c.stencilfunc_bf);
|
||||
printf("\t color_writes_on_depth_fail_enable = %s\n", c.color_writes_on_depth_fail_enable ? "true" : "false");
|
||||
printf("\t color_writes_on_depth_pass_disable = %s\n", c.color_writes_on_depth_pass_disable ? "true" : "false");
|
||||
printf("\t stencil_fail = %" PRIu8 "\n", s.stencil_fail);
|
||||
printf("\t stencil_zpass = %" PRIu8 "\n", s.stencil_zpass);
|
||||
printf("\t stencil_zfail = %" PRIu8 "\n", s.stencil_zfail);
|
||||
|
|
@ -846,6 +931,8 @@ static void d_check(const HW::DepthControl& c, const HW::StencilControl& s, cons
|
|||
EXIT_NOT_IMPLEMENTED(c.backface_enable != false);
|
||||
// EXIT_NOT_IMPLEMENTED(c.stencilfunc != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(c.stencilfunc_bf != 0);
|
||||
EXIT_NOT_IMPLEMENTED(c.color_writes_on_depth_fail_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(c.color_writes_on_depth_pass_disable != false);
|
||||
// EXIT_NOT_IMPLEMENTED(s.stencil_fail != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(s.stencil_zpass != 0);
|
||||
// EXIT_NOT_IMPLEMENTED(s.stencil_zfail != 0);
|
||||
|
|
@ -3736,7 +3823,9 @@ static void FindRenderDepthInfo(uint64_t submit_id, CommandBuffer* /*buffer*/, c
|
|||
|
||||
if (r->format != VK_FORMAT_UNDEFINED)
|
||||
{
|
||||
DepthStencilBufferObject vulkan_buffer_info(r->format, r->width, r->height, htile, neo);
|
||||
bool sampled = ((z.stencil_info.format == 0 && z.z_info.tile_mode_index != 0) || z.stencil_info.texture_compatible_stencil);
|
||||
|
||||
DepthStencilBufferObject vulkan_buffer_info(r->format, r->width, r->height, htile, neo, sampled);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(z.z_info.tile_mode_index != 0 && r->depth_tile_swizzle != 0);
|
||||
EXIT_NOT_IMPLEMENTED(r->stencil_tile_swizzle != 0);
|
||||
|
|
@ -4321,6 +4410,26 @@ static void SetDynamicParams(VkCommandBuffer vk_buffer, VulkanPipeline* pipeline
|
|||
}
|
||||
}
|
||||
|
||||
static bool shader_is_disabled(HW::Shader* sh_ctx)
|
||||
{
|
||||
if (const auto& vs = sh_ctx->GetVs();
|
||||
!vs.vs_embedded && ((vs.vs_regs.data_addr != 0 && ShaderIsDisabled(vs.vs_regs.data_addr)) ||
|
||||
(vs.vs_regs.data_addr == 0 && vs.gs_regs.data_addr == 0 && vs.es_regs.data_addr != 0 &&
|
||||
vs.gs_regs.chksum != 0 && ShaderIsDisabled2(vs.es_regs.data_addr, vs.gs_regs.chksum))))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
if (const auto& ps = sh_ctx->GetPs();
|
||||
!ps.ps_embedded && ((ps.ps_regs.chksum == 0 && ShaderIsDisabled(ps.ps_regs.data_addr)) ||
|
||||
(ps.ps_regs.chksum != 0 && ShaderIsDisabled2(ps.ps_regs.data_addr, ps.ps_regs.chksum))))
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void GraphicsRenderDrawIndex(uint64_t submit_id, CommandBuffer* buffer, HW::Context* ctx, HW::UserConfig* ucfg, HW::Shader* sh_ctx,
|
||||
uint32_t index_type_and_size, uint32_t index_count, const void* index_addr, uint32_t flags, uint32_t type)
|
||||
{
|
||||
|
|
@ -4334,12 +4443,7 @@ void GraphicsRenderDrawIndex(uint64_t submit_id, CommandBuffer* buffer, HW::Cont
|
|||
|
||||
Core::LockGuard lock(g_render_ctx->GetMutex());
|
||||
|
||||
if (const auto& vs = sh_ctx->GetVs(); !vs.vs_embedded && ShaderIsDisabled(vs.vs_regs.GetGpuAddress()))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (const auto& ps = sh_ctx->GetPs(); !ps.ps_embedded && ShaderIsDisabled(ps.ps_regs.data_addr))
|
||||
if (shader_is_disabled(sh_ctx))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -4482,12 +4586,7 @@ void GraphicsRenderDrawIndexAuto(uint64_t submit_id, CommandBuffer* buffer, HW::
|
|||
|
||||
Core::LockGuard lock(g_render_ctx->GetMutex());
|
||||
|
||||
if (const auto& vs = sh_ctx->GetVs(); !vs.vs_embedded && ShaderIsDisabled(vs.vs_regs.GetGpuAddress()))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (const auto& ps = sh_ctx->GetPs(); !ps.ps_embedded && ShaderIsDisabled(ps.ps_regs.data_addr))
|
||||
if (shader_is_disabled(sh_ctx))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -31,7 +31,8 @@ static void* create_func(GraphicContext* ctx, const uint64_t* params, const uint
|
|||
auto pixel_format = static_cast<VkFormat>(params[DepthStencilBufferObject::PARAM_FORMAT]);
|
||||
auto width = params[DepthStencilBufferObject::PARAM_WIDTH];
|
||||
auto height = params[DepthStencilBufferObject::PARAM_HEIGHT];
|
||||
bool htile = params[DepthStencilBufferObject::PARAM_HTILE] != 1;
|
||||
bool htile = params[DepthStencilBufferObject::PARAM_HTILE] != 0;
|
||||
bool sampled = params[DepthStencilBufferObject::PARAM_USAGE] == 1;
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(pixel_format == VK_FORMAT_UNDEFINED);
|
||||
EXIT_NOT_IMPLEMENTED(width == 0);
|
||||
|
|
@ -50,7 +51,7 @@ static void* create_func(GraphicContext* ctx, const uint64_t* params, const uint
|
|||
view = nullptr;
|
||||
}
|
||||
|
||||
vk_obj->compressed = htile;
|
||||
vk_obj->compressed = !htile;
|
||||
|
||||
VkImageCreateInfo image_info {};
|
||||
image_info.sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO;
|
||||
|
|
@ -66,7 +67,7 @@ static void* create_func(GraphicContext* ctx, const uint64_t* params, const uint
|
|||
image_info.tiling = VK_IMAGE_TILING_OPTIMAL;
|
||||
image_info.initialLayout = vk_obj->layout;
|
||||
image_info.usage = static_cast<VkImageUsageFlags>(VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) |
|
||||
static_cast<VkImageUsageFlags>(VK_IMAGE_USAGE_SAMPLED_BIT);
|
||||
(sampled ? static_cast<VkImageUsageFlags>(VK_IMAGE_USAGE_SAMPLED_BIT) : static_cast<VkImageUsageFlags>(0));
|
||||
image_info.sharingMode = VK_SHARING_MODE_EXCLUSIVE;
|
||||
image_info.samples = VK_SAMPLE_COUNT_1_BIT;
|
||||
|
||||
|
|
@ -160,15 +161,10 @@ static void delete_func(GraphicContext* ctx, void* obj, VulkanMemory* mem)
|
|||
bool DepthStencilBufferObject::Equal(const uint64_t* other) const
|
||||
{
|
||||
return (params[PARAM_FORMAT] == other[PARAM_FORMAT] && params[PARAM_WIDTH] == other[PARAM_WIDTH] &&
|
||||
params[PARAM_HEIGHT] == other[PARAM_HEIGHT] && params[PARAM_HTILE] == other[PARAM_HTILE]);
|
||||
params[PARAM_HEIGHT] == other[PARAM_HEIGHT] && params[PARAM_HTILE] == other[PARAM_HTILE] &&
|
||||
params[PARAM_NEO] == other[PARAM_NEO] && params[PARAM_USAGE] == other[PARAM_USAGE]);
|
||||
}
|
||||
|
||||
// bool DepthStencilBufferObject::Reuse(const uint64_t* other) const
|
||||
//{
|
||||
// return (params[PARAM_FORMAT] == other[PARAM_FORMAT] && params[PARAM_WIDTH] <= other[PARAM_WIDTH] &&
|
||||
// params[PARAM_HEIGHT] <= other[PARAM_HEIGHT] && params[PARAM_HTILE] == other[PARAM_HTILE]);
|
||||
//}
|
||||
|
||||
GpuObject::create_func_t DepthStencilBufferObject::GetCreateFunc() const
|
||||
{
|
||||
return create_func;
|
||||
|
|
|
|||
|
|
@ -2088,20 +2088,59 @@ KYTY_SHADER_PARSER(shader_parse)
|
|||
return ptr - src;
|
||||
}
|
||||
|
||||
static void vs_print(const char* func, const HW::VsStageRegisters& vs, const HW::ShaderRegisters& sh)
|
||||
static void vs_print(const char* func, const HW::VertexShaderInfo& vs, const HW::ShaderRegisters& sh)
|
||||
{
|
||||
printf("%s\n", func);
|
||||
|
||||
printf("\t GetGpuAddress() = 0x%016" PRIx64 "\n", vs.GetGpuAddress());
|
||||
printf("\t GetStreamoutEnabled() = %s\n", vs.GetStreamoutEnabled() ? "true" : "false");
|
||||
printf("\t GetSgprCount() = 0x%08" PRIx32 "\n", vs.GetSgprCount());
|
||||
printf("\t GetInputComponentsCount() = 0x%08" PRIx32 "\n", vs.GetInputComponentsCount());
|
||||
printf("\t GetUnknown1() = 0x%08" PRIx32 "\n", vs.GetUnknown1());
|
||||
printf("\t GetUnknown2() = 0x%08" PRIx32 "\n", vs.GetUnknown2());
|
||||
printf("\t vs.data_addr = 0x%016" PRIx64 "\n", vs.vs_regs.data_addr);
|
||||
printf("\t es.data_addr = 0x%016" PRIx64 "\n", vs.es_regs.data_addr);
|
||||
printf("\t gs.data_addr = 0x%016" PRIx64 "\n", vs.gs_regs.data_addr);
|
||||
|
||||
if (vs.vs_regs.data_addr != 0)
|
||||
{
|
||||
printf("\t vs.vgprs = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc1.vgprs);
|
||||
printf("\t vs.sgprs = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc1.sgprs);
|
||||
printf("\t vs.priority = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc1.priority);
|
||||
printf("\t vs.float_mode = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc1.float_mode);
|
||||
printf("\t vs.dx10_clamp = %s\n", vs.vs_regs.rsrc1.dx10_clamp ? "true" : "false");
|
||||
printf("\t vs.ieee_mode = %s\n", vs.vs_regs.rsrc1.ieee_mode ? "true" : "false");
|
||||
printf("\t vs.vgpr_component_count = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc1.vgpr_component_count);
|
||||
printf("\t vs.cu_group_enable = %s\n", vs.vs_regs.rsrc1.cu_group_enable ? "true" : "false");
|
||||
printf("\t vs.require_forward_progress = %s\n", vs.vs_regs.rsrc1.require_forward_progress ? "true" : "false");
|
||||
printf("\t vs.fp16_overflow = %s\n", vs.vs_regs.rsrc1.fp16_overflow ? "true" : "false");
|
||||
printf("\t vs.scratch_en = %s\n", vs.vs_regs.rsrc2.scratch_en ? "true" : "false");
|
||||
printf("\t vs.user_sgpr = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc2.user_sgpr);
|
||||
printf("\t vs.offchip_lds = %s\n", vs.vs_regs.rsrc2.offchip_lds ? "true" : "false");
|
||||
printf("\t vs.streamout_enabled = %s\n", vs.vs_regs.rsrc2.streamout_enabled ? "true" : "false");
|
||||
printf("\t vs.shared_vgprs = 0x%02" PRIx8 "\n", vs.vs_regs.rsrc2.shared_vgprs);
|
||||
}
|
||||
|
||||
if (vs.gs_regs.data_addr != 0 || vs.es_regs.data_addr != 0)
|
||||
{
|
||||
printf("\t chksum = 0x%016" PRIx64 "\n", vs.gs_regs.chksum);
|
||||
printf("\t gs.vgprs = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc1.vgprs);
|
||||
printf("\t gs.sgprs = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc1.sgprs);
|
||||
printf("\t gs.priority = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc1.priority);
|
||||
printf("\t gs.float_mode = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc1.float_mode);
|
||||
printf("\t gs.dx10_clamp = %s\n", vs.gs_regs.rsrc1.dx10_clamp ? "true" : "false");
|
||||
printf("\t gs.ieee_mode = %s\n", vs.gs_regs.rsrc1.ieee_mode ? "true" : "false");
|
||||
printf("\t gs.debug_mode = %s\n", vs.gs_regs.rsrc1.debug_mode ? "true" : "false");
|
||||
printf("\t gs.lds_configuration = %s\n", vs.gs_regs.rsrc1.lds_configuration ? "true" : "false");
|
||||
printf("\t gs.cu_group_enable = %s\n", vs.gs_regs.rsrc1.cu_group_enable ? "true" : "false");
|
||||
printf("\t gs.require_forward_progress = %s\n", vs.gs_regs.rsrc1.require_forward_progress ? "true" : "false");
|
||||
printf("\t gs.fp16_overflow = %s\n", vs.gs_regs.rsrc1.fp16_overflow ? "true" : "false");
|
||||
printf("\t gs.gs_vgpr_component_count = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc1.gs_vgpr_component_count);
|
||||
printf("\t gs.scratch_en = %s\n", vs.gs_regs.rsrc2.scratch_en ? "true" : "false");
|
||||
printf("\t gs.user_sgpr = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc2.user_sgpr);
|
||||
printf("\t gs.offchip_lds = %s\n", vs.gs_regs.rsrc2.offchip_lds ? "true" : "false");
|
||||
printf("\t gs.shared_vgprs = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc2.shared_vgprs);
|
||||
printf("\t gs.es_vgpr_component_count = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc2.es_vgpr_component_count);
|
||||
printf("\t gs.lds_size = 0x%02" PRIx8 "\n", vs.gs_regs.rsrc2.lds_size);
|
||||
}
|
||||
|
||||
printf("\t m_spiVsOutConfig = 0x%08" PRIx32 "\n", sh.m_spiVsOutConfig);
|
||||
printf("\t m_spiShaderPosFormat = 0x%08" PRIx32 "\n", sh.m_spiShaderPosFormat);
|
||||
printf("\t m_paClVsOutCntl = 0x%08" PRIx32 "\n", sh.m_paClVsOutCntl);
|
||||
|
||||
printf("\t m_spiShaderIdxFormat = 0x%08" PRIx32 "\n", sh.m_spiShaderIdxFormat);
|
||||
printf("\t m_geNggSubgrpCntl = 0x%08" PRIx32 "\n", sh.m_geNggSubgrpCntl);
|
||||
printf("\t m_vgtGsInstanceCnt = 0x%08" PRIx32 "\n", sh.m_vgtGsInstanceCnt);
|
||||
|
|
@ -2118,21 +2157,30 @@ static void ps_print(const char* func, const HW::PsStageRegisters& ps, const HW:
|
|||
{
|
||||
printf("%s\n", func);
|
||||
|
||||
// printf("\t GetGpuAddress() = 0x%016" PRIx64 "\n", ps.GetGpuAddress());
|
||||
// printf("\t m_spiShaderPgmRsrc1Ps = 0x%08" PRIx32 "\n", ps.m_spiShaderPgmRsrc1Ps);
|
||||
// printf("\t m_spiShaderPgmRsrc2Ps = 0x%08" PRIx32 "\n", ps.m_spiShaderPgmRsrc2Ps);
|
||||
// printf("\t GetTargetOutputMode(0) = 0x%08" PRIx32 "\n", ps.GetTargetOutputMode(0));
|
||||
printf("\t data_addr = 0x%016" PRIx64 "\n", ps.data_addr);
|
||||
printf("\t chksum = 0x%016" PRIx64 "\n", ps.chksum);
|
||||
printf("\t conservative_z_export_value = 0x%08" PRIx32 "\n", sh.db_shader_control.conservative_z_export_value);
|
||||
printf("\t shader_z_behavior = 0x%08" PRIx32 "\n", sh.db_shader_control.shader_z_behavior);
|
||||
printf("\t shader_kill_enable = %s\n", sh.db_shader_control.shader_kill_enable ? "true" : "false");
|
||||
printf("\t shader_z_export_enable = %s\n", sh.db_shader_control.shader_z_export_enable ? "true" : "false");
|
||||
printf("\t shader_execute_on_noop = %s\n", sh.db_shader_control.shader_execute_on_noop ? "true" : "false");
|
||||
printf("\t vgprs = 0x%02" PRIx8 "\n", ps.vgprs);
|
||||
printf("\t sgprs = 0x%02" PRIx8 "\n", ps.sgprs);
|
||||
printf("\t scratch_en = 0x%02" PRIx8 "\n", ps.scratch_en);
|
||||
printf("\t user_sgpr = 0x%02" PRIx8 "\n", ps.user_sgpr);
|
||||
printf("\t wave_cnt_en = 0x%02" PRIx8 "\n", ps.wave_cnt_en);
|
||||
printf("\t vgprs = 0x%02" PRIx8 "\n", ps.rsrc1.vgprs);
|
||||
printf("\t sgprs = 0x%02" PRIx8 "\n", ps.rsrc1.sgprs);
|
||||
printf("\t priority = 0x%02" PRIx8 "\n", ps.rsrc1.priority);
|
||||
printf("\t float_mode = 0x%02" PRIx8 "\n", ps.rsrc1.float_mode);
|
||||
printf("\t dx10_clamp = %s\n", ps.rsrc1.dx10_clamp ? "true" : "false");
|
||||
printf("\t debug_mode = %s\n", ps.rsrc1.debug_mode ? "true" : "false");
|
||||
printf("\t ieee_mode = %s\n", ps.rsrc1.ieee_mode ? "true" : "false");
|
||||
printf("\t cu_group_disable = %s\n", ps.rsrc1.cu_group_disable ? "true" : "false");
|
||||
printf("\t require_forward_progress = %s\n", ps.rsrc1.require_forward_progress ? "true" : "false");
|
||||
printf("\t fp16_overflow = %s\n", ps.rsrc1.fp16_overflow ? "true" : "false");
|
||||
printf("\t scratch_en = %s\n", ps.rsrc2.scratch_en ? "true" : "false");
|
||||
printf("\t user_sgpr = 0x%02" PRIx8 "\n", ps.rsrc2.user_sgpr);
|
||||
printf("\t wave_cnt_en = %s\n", ps.rsrc2.wave_cnt_en ? "true" : "false");
|
||||
printf("\t extra_lds_size = 0x%02" PRIx8 "\n", ps.rsrc2.extra_lds_size);
|
||||
printf("\t raster_ordered_shading = %s\n", ps.rsrc2.raster_ordered_shading ? "true" : "false");
|
||||
printf("\t shared_vgprs = 0x%02" PRIx8 "\n", ps.rsrc2.shared_vgprs);
|
||||
|
||||
printf("\t shader_z_format = 0x%08" PRIx32 "\n", sh.shader_z_format);
|
||||
printf("\t target_output_mode[0] = 0x%02" PRIx8 "\n", sh.target_output_mode[0]);
|
||||
printf("\t ps_input_ena = 0x%08" PRIx32 "\n", sh.ps_input_ena);
|
||||
|
|
@ -2196,14 +2244,43 @@ static void bi_print(const char* func, const ShaderBinaryInfo& bi)
|
|||
printf("\t crc32 = 0x%08" PRIx32 "\n", bi.crc32);
|
||||
}
|
||||
|
||||
static void vs_check(const HW::VsStageRegisters& vs, const HW::ShaderRegisters& sh)
|
||||
// NOLINTNEXTLINE(readability-function-cognitive-complexity)
|
||||
static void vs_check(const HW::VertexShaderInfo& vs, const HW::ShaderRegisters& sh)
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(vs.GetStreamoutEnabled() != false);
|
||||
// EXIT_NOT_IMPLEMENTED(vs.GetSgprCount() != 0x00000000);
|
||||
// EXIT_NOT_IMPLEMENTED(vs.GetInputComponentsCount() != 0x00000003);
|
||||
// EXIT_NOT_IMPLEMENTED(vs.GetUnknown1() != 0x002c0000);
|
||||
// EXIT_NOT_IMPLEMENTED(vs.GetUnknown2() != 0x00000000);
|
||||
// EXIT_NOT_IMPLEMENTED(vs.m_spiVsOutConfig != 0x00000000);
|
||||
if (vs.vs_regs.data_addr != 0)
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.priority != 0);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.float_mode != 192);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.dx10_clamp != true);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.ieee_mode != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.cu_group_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.require_forward_progress != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc1.fp16_overflow != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc2.scratch_en != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc2.offchip_lds != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc2.streamout_enabled != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.vs_regs.rsrc2.shared_vgprs != 0);
|
||||
}
|
||||
|
||||
if (vs.es_regs.data_addr != 0 || vs.gs_regs.data_addr != 0)
|
||||
{
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.priority != 0);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.float_mode != 192);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.dx10_clamp != true);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.debug_mode != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.ieee_mode != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.cu_group_enable != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.require_forward_progress != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.lds_configuration != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.gs_vgpr_component_count != 0);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.fp16_overflow != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.scratch_en != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.offchip_lds != false);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.es_vgpr_component_count != 0);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.lds_size != 0);
|
||||
EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.shared_vgprs != 0);
|
||||
}
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(sh.m_spiShaderPosFormat != 0x00000004);
|
||||
EXIT_NOT_IMPLEMENTED(sh.m_paClVsOutCntl != 0x00000000);
|
||||
|
||||
|
|
@ -2231,9 +2308,21 @@ static void ps_check(const HW::PsStageRegisters& ps, const HW::ShaderRegisters&
|
|||
// EXIT_NOT_IMPLEMENTED(ps.m_spiShaderPgmRsrc2Ps != 0x00000000);
|
||||
// EXIT_NOT_IMPLEMENTED(ps.vgprs != 0x00 && ps.vgprs != 0x01);
|
||||
// EXIT_NOT_IMPLEMENTED(ps.sgprs != 0x00 && ps.sgprs != 0x01);
|
||||
EXIT_NOT_IMPLEMENTED(ps.scratch_en != 0);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.priority != 0);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.float_mode != 192);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.dx10_clamp != true);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.debug_mode != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.ieee_mode != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.cu_group_disable != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.require_forward_progress != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc1.fp16_overflow != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc2.scratch_en != false);
|
||||
// EXIT_NOT_IMPLEMENTED(ps.user_sgpr != 0 && ps.user_sgpr != 4 && ps.user_sgpr != 12);
|
||||
EXIT_NOT_IMPLEMENTED(ps.wave_cnt_en != 0);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc2.wave_cnt_en != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc2.extra_lds_size != 0);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc2.raster_ordered_shading != false);
|
||||
EXIT_NOT_IMPLEMENTED(ps.rsrc2.shared_vgprs != 0);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(sh.shader_z_format != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(sh.ps_input_ena != 0x00000002 && sh.ps_input_ena != 0x00000302);
|
||||
EXIT_NOT_IMPLEMENTED(sh.ps_input_addr != 0x00000002 && sh.ps_input_addr != 0x00000302);
|
||||
|
|
@ -2756,7 +2845,7 @@ void ShaderGetInputInfoVS(const HW::VertexShaderInfo* regs, const HW::ShaderRegi
|
|||
return;
|
||||
}
|
||||
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.GetGpuAddress());
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.data_addr);
|
||||
|
||||
auto usages = GetUsageSlots(src);
|
||||
|
||||
|
|
@ -3400,12 +3489,14 @@ ShaderCode ShaderParseVS(const HW::VertexShaderInfo* regs, const HW::ShaderRegis
|
|||
code.SetVsEmbeddedId(regs->vs_embedded_id);
|
||||
} else
|
||||
{
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.GetGpuAddress());
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.data_addr);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(src == nullptr);
|
||||
|
||||
vs_print("ShaderParseVS()", regs->vs_regs, *sh);
|
||||
vs_check(regs->vs_regs, *sh);
|
||||
vs_print("ShaderParseVS()", *regs, *sh);
|
||||
vs_check(*regs, *sh);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(regs->vs_regs.rsrc2.user_sgpr > regs->vs_user_sgpr.count);
|
||||
|
||||
const auto* header = GetBinaryInfo(src);
|
||||
|
||||
|
|
@ -3489,7 +3580,7 @@ ShaderCode ShaderParsePS(const HW::PixelShaderInfo* regs, const HW::ShaderRegist
|
|||
ps_print("ShaderParsePS()", regs->ps_regs, *sh);
|
||||
ps_check(regs->ps_regs, *sh);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(regs->ps_regs.user_sgpr > regs->ps_user_sgpr.count);
|
||||
EXIT_NOT_IMPLEMENTED(regs->ps_regs.rsrc2.user_sgpr > regs->ps_user_sgpr.count);
|
||||
|
||||
const auto* header = GetBinaryInfo(src);
|
||||
|
||||
|
|
@ -3853,7 +3944,7 @@ ShaderId ShaderGetIdVS(const HW::VertexShaderInfo* regs, const ShaderVertexInput
|
|||
return ret;
|
||||
}
|
||||
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.GetGpuAddress());
|
||||
const auto* src = reinterpret_cast<const uint32_t*>(regs->vs_regs.data_addr);
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(src == nullptr);
|
||||
|
||||
|
|
@ -3999,6 +4090,15 @@ bool ShaderIsDisabled(uint64_t addr)
|
|||
return disabled;
|
||||
}
|
||||
|
||||
bool ShaderIsDisabled2(uint64_t addr, uint64_t chksum)
|
||||
{
|
||||
bool disabled = (g_disabled_shaders != nullptr && g_disabled_shaders->Contains(chksum));
|
||||
|
||||
printf("Shader 0x%016" PRIx64 ": id = 0x%016" PRIx64 " - %s\n", addr, chksum, (disabled ? "disabled" : "enabled"));
|
||||
|
||||
return disabled;
|
||||
}
|
||||
|
||||
void ShaderDisable(uint64_t id)
|
||||
{
|
||||
if (g_disabled_shaders == nullptr)
|
||||
|
|
|
|||
Loading…
Reference in New Issue