mirror of https://github.com/red-prig/fpPS4.git
573 lines
14 KiB
Plaintext
573 lines
14 KiB
Plaintext
unit emit_SOP2;
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{$mode objfpc}{$H+}
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interface
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uses
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sysutils,
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spirv,
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ps4_pssl,
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srType,
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srReg,
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srConst,
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emit_fetch;
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type
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TEmit_SOP2=class(TEmitFetch)
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procedure emit_SOP2;
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procedure emit_S_ADD_I32;
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procedure emit_S_ADD_U32;
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procedure emit_S_SUB_I32;
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procedure emit_S_SUB_U32;
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procedure emit_S_ADDC_U32;
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procedure emit_S_MMX(OpId:DWORD;rtype:TsrDataType);
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procedure emit_S_MUL_I32;
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procedure OpISccNotZero(src:TsrRegNode);
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procedure OpISccNotZero2(src0,src1:TsrRegNode);
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procedure emit_S_SH(OpId:DWORD;rtype:TsrDataType);
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procedure emit_S_AND_B32;
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procedure emit_S_AND_B64;
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procedure emit_S_ANDN2_B64;
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procedure emit_S_OR_B32;
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procedure emit_S_OR_B64;
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procedure emit_S_XOR_B32;
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procedure emit_S_XOR_B64;
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procedure emit_S_ORN2_B64;
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procedure emit_S_NAND_B64;
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procedure emit_S_NOR_B64;
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procedure emit_S_CSELECT_B32;
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procedure emit_S_CSELECT_B64;
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procedure emit_S_BFE_U32;
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procedure emit_S_BFM_B32;
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end;
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implementation
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procedure TEmit_SOP2.emit_S_ADD_I32;
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Var
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dst,car:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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x,y,d:TsrRegNode;
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a,b:TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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car:=get_scc;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtInt32);
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//Force type
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src[0]:=BitcastList.FetchRead(dtInt32,src[0]);
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src[1]:=BitcastList.FetchRead(dtInt32,src[1]);
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OpIAdd(dst,src[0],src[1]);
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//scc = sign(x) == sign(y) && sign(d) != sign(x);
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x:=OpIsSSignTo(src[0]);
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y:=OpIsSSignTo(src[1]);
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d:=OpIsSSignTo(dst^.current);
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a:=OpEqualTo(x,y);
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b:=OpNotEqualTo(d,x);
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OpLogicalAnd(car,a,b);
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end;
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procedure TEmit_SOP2.emit_S_ADD_U32;
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Var
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dst,car:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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car:=get_scc;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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OpIAddExt(dst,car,src[0],src[1],dtUInt32);
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end;
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procedure TEmit_SOP2.emit_S_SUB_I32;
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Var
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dst,bor:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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x,y,d:TsrRegNode;
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a,b:TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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bor:=get_scc;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtInt32);
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//Force type
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src[0]:=BitcastList.FetchRead(dtInt32,src[0]);
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src[1]:=BitcastList.FetchRead(dtInt32,src[1]);
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OpISub(dst,src[0],src[1]);
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//scc = sign(x) != sign(y) && sign(d) != sign(x);
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x:=OpIsSSignTo(src[0]);
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y:=OpIsSSignTo(src[1]);
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d:=OpIsSSignTo(dst^.current);
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a:=OpNotEqualTo(x,y);
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b:=OpNotEqualTo(d,x);
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OpLogicalAnd(bor,a,b);
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end;
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procedure TEmit_SOP2.emit_S_SUB_U32;
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Var
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dst,bor:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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bor:=get_scc;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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OpISubExt(dst,bor,src[0],src[1],dtUInt32);
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end;
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procedure TEmit_SOP2.emit_S_ADDC_U32;
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Var
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dst,car:PsrRegSlot;
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src:array[0..2] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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car:=get_scc;
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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src[2]:=MakeRead(car,dtUInt32);
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OpIAddExt(dst,car,src[0],src[1],dtUInt32); //src0+src1
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src[0]:=MakeRead(dst,dtUInt32);
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src[1]:=MakeRead(car,dtUInt32); //save car1
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OpIAddExt(dst,car,src[0],src[2],dtUInt32); //(src0+src1)+SCC
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src[0]:=MakeRead(car,dtUInt32);
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OpBitwiseOr(car,src[1],src[0]); //SCC1 or SCC2
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end;
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procedure TEmit_SOP2.emit_S_MMX(OpId:DWORD;rtype:TsrDataType);
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,rtype);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,rtype);
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OpGlsl2(OpId,rtype,dst,src[0],src[1]);
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end;
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procedure TEmit_SOP2.emit_S_MUL_I32;
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtInt32);
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OpIMul(dst,src[0],src[1]);
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end;
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procedure TEmit_SOP2.OpISccNotZero(src:TsrRegNode); //SCC = (sdst.u != 0)
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begin
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if src.is_const then
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begin
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//early optimization
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SetConst_b(get_scc,src.AsConst.AsBool);
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end else
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begin
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MakeCopy(get_scc,src);
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get_scc^.current.dtype:=dtBool; //implict cast (int != 0)
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end;
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end;
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procedure TEmit_SOP2.OpISccNotZero2(src0,src1:TsrRegNode);
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begin
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if src0.is_const and
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src1.is_const then
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begin
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//early optimization
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SetConst_b(get_scc,src0.AsConst.AsBool or src1.AsConst.AsBool);
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end else
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begin
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//force type
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src0:=BitcastList.FetchRead(dtBool,src0);
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src1:=BitcastList.FetchRead(dtBool,src1);
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OpLogicalOr(get_scc,src0,src1); //implict cast (int != 0)
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end;
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end;
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procedure TEmit_SOP2.emit_S_SH(OpId:DWORD;rtype:TsrDataType);
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,rtype);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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src[1]:=OpAndTo(src[1],31);
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src[1].PrepType(ord(dtUInt32));
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Op2(OpId,src[0].dtype,dst,src[0],src[1]);
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OpISccNotZero(dst^.current); //SCC = (sdst.u != 0)
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end;
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procedure TEmit_SOP2.emit_S_AND_B32; //sdst = (ssrc0 & ssrc1); SCC = (sdst != 0)
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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OpBitwiseAnd(dst,src[0],src[1]);
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OpISccNotZero(dst^.current); //SCC = (sdst.u != 0)
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end;
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procedure TEmit_SOP2.emit_S_AND_B64; //sdst[2] = (ssrc0[2] & ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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OpBitwiseAnd(dst[0],src0[0],src1[0]);
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OpBitwiseAnd(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_ANDN2_B64; //sdst[2] = (ssrc0[2] & ~ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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src1[0]:=OpNotTo(src1[0]);
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src1[1]:=OpNotTo(src1[1]);
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OpBitwiseAnd(dst[0],src0[0],src1[0]);
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OpBitwiseAnd(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_OR_B32;
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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OpBitwiseOr(dst,src[0],src[1]);
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OpISccNotZero(dst^.current); //SCC = (sdst.u != 0)
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end;
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procedure TEmit_SOP2.emit_S_OR_B64; //sdst[2] = (ssrc0[2] | ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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OpBitwiseOr(dst[0],src0[0],src1[0]);
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OpBitwiseOr(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_XOR_B32;
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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OpBitwiseXor(dst,src[0],src[1]);
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OpISccNotZero(dst^.current); //SCC = (sdst.u != 0)
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end;
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procedure TEmit_SOP2.emit_S_XOR_B64; //sdst[2] = (ssrc0[2] ^ ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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OpBitwiseXor(dst[0],src0[0],src1[0]);
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OpBitwiseXor(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_ORN2_B64; //sdst[2] = (ssrc0[2] | ~ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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src1[0]:=OpNotTo(src1[0]);
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src1[1]:=OpNotTo(src1[1]);
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OpBitwiseOr(dst[0],src0[0],src1[0]);
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OpBitwiseOr(dst[1],src0[1],src1[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_NAND_B64; //sdst[2] = ~(ssrc0[2] & ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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src2[0]:=OpAndTo(src0[0],src1[0]);
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src2[1]:=OpAndTo(src0[1],src1[1]);
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OpNot(dst[0],src2[0]);
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OpNot(dst[1],src2[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_NOR_B64; //sdst[2] = ~(ssrc0[2] | ssrc1[2]); SCC = (sdst[2] != 0)
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1,src2:array[0..1] of TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUInt32) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUInt32) then Assert(False);
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src2[0]:=OpOrTo(src0[0],src1[0]);
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src2[1]:=OpOrTo(src0[1],src1[1]);
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OpNot(dst[0],src2[0]);
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OpNot(dst[1],src2[1]);
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src2[0]:=dst[0]^.current;
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src2[1]:=dst[1]^.current;
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OpISccNotZero2(src2[0],src2[1]); //implict cast (int != 0)
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end;
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procedure TEmit_SOP2.emit_S_CSELECT_B32; //sdst = SCC ? ssrc0 : ssrc1
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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scc:TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUnknow);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUnknow);
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scc:=MakeRead(get_scc,dtBool);
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//dst,cond,src_true,src_false
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OpSelect(dst,scc,src[0],src[1]);
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end;
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procedure TEmit_SOP2.emit_S_CSELECT_B64; //sdst[2] = SCC ? ssrc0[2] : ssrc1[2]
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Var
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dst:array[0..1] of PsrRegSlot;
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src0,src1:array[0..1] of TsrRegNode;
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scc:TsrRegNode;
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begin
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if not get_sdst7_pair(FSPI.SOP2.SDST,@dst) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC0,@src0,dtUnknow) then Assert(False);
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if not fetch_ssrc9_pair(FSPI.SOP2.SSRC1,@src1,dtUnknow) then Assert(False);
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scc:=MakeRead(get_scc,dtBool);
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//dst,cond,src_true,src_false
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OpSelect(dst[0],scc,src0[0],src1[0]);
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OpSelect(dst[1],scc,src0[1],src1[1]);
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end;
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//offset = ssrc1[4:0].u and 31
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//width = ssrc1[22:16].u shr 16
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procedure TEmit_SOP2.emit_S_BFE_U32; //sdst.u = bitFieldExtract(ssrc0); SCC = (sdst.u != 0)
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Var
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dst:PsrRegSlot;
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src:array[0..1] of TsrRegNode;
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pImm:TsrConst;
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offset,count:TsrRegNode;
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begin
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dst:=get_sdst7(FSPI.SOP2.SDST);
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src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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|
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//early optimization
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pImm:=src[1].pWriter.specialize AsType<ntConst>;
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|
|
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if (pImm<>nil) then
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begin
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offset:=NewImm_i(dtUInt32,pImm.AsUint32 and 31);
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count :=NewImm_i(dtUInt32,pImm.AsUint32 shr 16);
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end else
|
|
begin
|
|
offset:=OpAndTo(src[1],31);
|
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count :=OpShrTo(src[1],16);
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|
end;
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|
|
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Op3(Op.OpBitFieldUExtract,dtUInt32,dst,src[0],offset,count);
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|
|
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OpISccNotZero(dst^.current); //SCC = (sdst.u != 0)
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|
end;
|
|
|
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procedure TEmit_SOP2.emit_S_BFM_B32; //sdst.u = ((1 << ssrc0.u[4:0])-1) << ssrc1[4:0]
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Var
|
|
dst:PsrRegSlot;
|
|
src:array[0..1] of TsrRegNode;
|
|
one:TsrRegNode;
|
|
begin
|
|
dst:=get_sdst7(FSPI.SOP2.SDST);
|
|
|
|
src[0]:=fetch_ssrc9(FSPI.SOP2.SSRC0,dtUInt32);
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src[1]:=fetch_ssrc9(FSPI.SOP2.SSRC1,dtUInt32);
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|
|
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src[0]:=OpAndTo(src[0],31);
|
|
src[1]:=OpAndTo(src[1],31);
|
|
|
|
src[0].PrepType(ord(dtUInt32));
|
|
src[1].PrepType(ord(dtUInt32));
|
|
|
|
one:=NewImm_q(dtUInt32,1);
|
|
|
|
src[0]:=OpShrTo(one,src[0]); //(1 << src0)
|
|
src[0]:=OpISubTo(src[0],1); //-1
|
|
|
|
Op2(Op.OpShiftRightLogical,dtUInt32,dst,src[0],src[1]);
|
|
end;
|
|
|
|
procedure TEmit_SOP2.emit_SOP2;
|
|
begin
|
|
|
|
Case FSPI.SOP2.OP of
|
|
|
|
S_ADD_U32: emit_S_ADD_U32;
|
|
S_ADD_I32: emit_S_ADD_I32;
|
|
|
|
S_SUB_U32: emit_S_SUB_U32;
|
|
S_SUB_I32: emit_S_SUB_I32;
|
|
|
|
S_ADDC_U32: emit_S_ADDC_U32;
|
|
|
|
S_MIN_I32: emit_S_MMX(GlslOp.SMin,dtInt32);
|
|
S_MAX_I32: emit_S_MMX(GlslOp.SMax,dtInt32);
|
|
|
|
S_MIN_U32: emit_S_MMX(GlslOp.UMin,dtUint32);
|
|
S_MAX_U32: emit_S_MMX(GlslOp.UMax,dtUint32);
|
|
|
|
S_MUL_I32: emit_S_MUL_I32;
|
|
|
|
S_LSHL_B32: emit_S_SH(Op.OpShiftLeftLogical ,dtUInt32);
|
|
S_LSHR_B32: emit_S_SH(Op.OpShiftRightLogical ,dtUInt32);
|
|
S_ASHR_I32: emit_S_SH(Op.OpShiftRightArithmetic,dtInt32);
|
|
|
|
S_AND_B32: emit_S_AND_B32;
|
|
S_AND_B64: emit_S_AND_B64;
|
|
|
|
S_ANDN2_B64: emit_S_ANDN2_B64;
|
|
|
|
S_OR_B32: emit_S_OR_B32;
|
|
S_OR_B64: emit_S_OR_B64;
|
|
|
|
S_XOR_B32: emit_S_XOR_B32;
|
|
S_XOR_B64: emit_S_XOR_B64;
|
|
|
|
S_ORN2_B64: emit_S_ORN2_B64;
|
|
|
|
S_NAND_B64: emit_S_NAND_B64;
|
|
|
|
S_NOR_B64: emit_S_NOR_B64;
|
|
|
|
S_CSELECT_B32: emit_S_CSELECT_B32;
|
|
S_CSELECT_B64: emit_S_CSELECT_B64;
|
|
|
|
S_BFE_U32: emit_S_BFE_U32;
|
|
S_BFM_B32: emit_S_BFM_B32;
|
|
|
|
else
|
|
Assert(False,'SOP2?'+IntToStr(FSPI.SOP2.OP)+' '+get_str_spi(FSPI));
|
|
end;
|
|
|
|
end;
|
|
|
|
end.
|
|
|