From f434e066780af07abd355e88476f9888bbffab2c Mon Sep 17 00:00:00 2001
From: Pavel <68122101+red-prig@users.noreply.github.com>
Date: Fri, 23 May 2025 15:42:13 +0300
Subject: [PATCH] +

---
 chip/pm4_me.pas       | 26 ++++++++++++++++++++------
 chip/pm4_pfp.pas      |  7 ++++++-
 vulkan/vCmdBuffer.pas | 26 ++++++++++++++++++++++++++
 3 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/chip/pm4_me.pas b/chip/pm4_me.pas
index 3a18654c..b8658061 100644
--- a/chip/pm4_me.pas
+++ b/chip/pm4_me.pas
@@ -1242,6 +1242,17 @@ begin
 
 end;
 
+Function get_bind_str(FBind:TvPointer):RawByteString;
+begin
+ if (FBind.FMemory=nil) then
+ begin
+  Result:='(nil)';
+ end else
+ begin
+  Result:='0x'+HexStr(FBind.FMemory.FHandle,16);
+ end;
+end;
+
 procedure Bind_Uniforms(var ctx:t_me_render_context;
                         BindPoint:TVkPipelineBindPoint;
                         var UniformBuilder:TvUniformBuilder);
@@ -1433,8 +1444,8 @@ begin
 
    range:=size;
 
-   Writeln('BindBuffer:->[',i,']'#13#10,
-           ' 0x',HexStr(buf.FHandle,16),':',buf.FName,'->[',diff_a,'..',range,']');
+   Writeln('BindBuffer:->[',i,':',bind,']',' 0x',HexStr(QWORD(addr),10),' ',get_bind_str(buf.FBind),#13#10,
+           ' 0x',HexStr(buf.FHandle,16),':',buf.FName,'->[',diff_a,'..',diff_a+range,']');
 
    DescriptorGroup.BindBuffer(fset,bind,
                               buf.FHandle,
@@ -2348,6 +2359,8 @@ begin
  pm4_InitStream(ctx);
  //
 
+ //if not ctx.WaitConfirmOrSwitch then Exit;
+
  StartFrameCapture;
 
  ctx.BeginCmdBuffer;
@@ -2838,11 +2851,12 @@ end;
 procedure pm4_EventWrite(var ctx:t_me_render_context;node:p_pm4_node_EventWrite);
 begin
  Case node^.eventType of
+  CS_PARTIAL_FLUSH,            //CS
   CACHE_FLUSH_AND_INV_EVENT,   //CB,DB
-  FLUSH_AND_INV_CB_PIXEL_DATA, //CB
-  //FLUSH_AND_INV_DB_DATA_TS   :Writeln(' eventType=FLUSH_AND_INV_DB_DATA_TS');
-  FLUSH_AND_INV_DB_META, //HTILE
-  FLUSH_AND_INV_CB_META: //CMASK
+  DB_CACHE_FLUSH_AND_INV,      //DB
+  FLUSH_AND_INV_DB_META,       //HTILE
+  FLUSH_AND_INV_CB_META,       //CMASK
+  FLUSH_AND_INV_CB_PIXEL_DATA: //CB
    begin
     if (ctx.Cmd<>nil) and ctx.Cmd.IsAllocated then
     begin
diff --git a/chip/pm4_pfp.pas b/chip/pm4_pfp.pas
index d7d2ea27..5d1b134a 100644
--- a/chip/pm4_pfp.pas
+++ b/chip/pm4_pfp.pas
@@ -1076,13 +1076,18 @@ begin
 
  if p_print_gpu_ops then
  Case Body^.eventType of
+  CS_PARTIAL_FLUSH           :Writeln(' eventType=CS_PARTIAL_FLUSH');
   CACHE_FLUSH_AND_INV_EVENT  :Writeln(' eventType=FLUSH_AND_INV_EVENT');
-  FLUSH_AND_INV_CB_PIXEL_DATA:Writeln(' eventType=FLUSH_AND_INV_CB_PIXEL_DATA');
+  DB_CACHE_FLUSH_AND_INV     :Writeln(' eventType=DB_CACHE_FLUSH_AND_INV');
   FLUSH_AND_INV_DB_DATA_TS   :Writeln(' eventType=FLUSH_AND_INV_DB_DATA_TS');
   FLUSH_AND_INV_DB_META      :Writeln(' eventType=FLUSH_AND_INV_DB_META');
   FLUSH_AND_INV_CB_DATA_TS   :Writeln(' eventType=FLUSH_AND_INV_CB_DATA_TS');
   FLUSH_AND_INV_CB_META      :Writeln(' eventType=FLUSH_AND_INV_CB_META');
+  FLUSH_AND_INV_CB_PIXEL_DATA:Writeln(' eventType=FLUSH_AND_INV_CB_PIXEL_DATA');
   THREAD_TRACE_MARKER        :Writeln(' eventType=THREAD_TRACE_MARKER');
+  PIXEL_PIPE_STAT_CONTROL    :Writeln(' eventType=PIXEL_PIPE_STAT_CONTROL');
+  PIXEL_PIPE_STAT_DUMP       :Writeln(' eventType=PIXEL_PIPE_STAT_DUMP');
+  PIXEL_PIPE_STAT_RESET      :Writeln(' eventType=PIXEL_PIPE_STAT_RESET');
   PIPELINESTAT_STOP          :Writeln(' eventType=PIPELINESTAT_STOP');
   PERFCOUNTER_START          :Writeln(' eventType=PERFCOUNTER_START');
   PERFCOUNTER_STOP           :Writeln(' eventType=PERFCOUNTER_STOP');
diff --git a/vulkan/vCmdBuffer.pas b/vulkan/vCmdBuffer.pas
index 9cee22b2..680dc25f 100644
--- a/vulkan/vCmdBuffer.pas
+++ b/vulkan/vCmdBuffer.pas
@@ -1426,6 +1426,32 @@ begin
  if (not BeginCmdBuffer) then Exit;
 
  Case eventType of
+  CS_PARTIAL_FLUSH:
+    begin
+     Inc(cmd_count);
+
+     DebugReport.CmdInsertLabel(FCmdbuf,'CS_PARTIAL_FLUSH');
+
+     vkMemoryBarrier(FCmdbuf,
+                     VK_ACCESS_CS,                              //srcAccessMask
+                     VK_ACCESS_ANY,                             //dstAccessMask
+     	             ord(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT), //srcStageMask
+     	             ord(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT));  //dstStageMask
+    end;
+  DB_CACHE_FLUSH_AND_INV: //DB
+   begin
+    Inc(cmd_count);
+
+    DebugReport.CmdInsertLabel(FCmdbuf,'DB_CACHE_FLUSH_AND_INV');
+
+    vkMemoryBarrier(FCmdbuf,
+                    VK_ACCESS_DB,                             //srcAccessMask
+                    VK_ACCESS_ANY,                            //dstAccessMask
+                    VK_STAGE_DB,                              //srcStageMask
+                    ord(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)); //dstStageMask
+
+   end;
+
   FLUSH_AND_INV_DB_META: //HTILE
    begin
     Inc(cmd_count);