From efd1a3a3c6f99a9f2ad58ce3aa469d2d6b1d000f Mon Sep 17 00:00:00 2001 From: Pavel <68122101+red-prig@users.noreply.github.com> Date: Mon, 27 Jan 2025 15:55:21 +0300 Subject: [PATCH] re generation of source code --- chip/si_ci_vi_merged_groups.pas | 6298 +++- chip/si_ci_vi_merged_offset.pas | 16840 +++++++-- chip/si_ci_vi_merged_registers.pas | 53896 ++++++++++++++++++++++++++- tools/gfx6_chip/chip.lpr | 443 +- 4 files changed, 72468 insertions(+), 5009 deletions(-) diff --git a/chip/si_ci_vi_merged_groups.pas b/chip/si_ci_vi_merged_groups.pas index 11ad4182..ac312cce 100644 --- a/chip/si_ci_vi_merged_groups.pas +++ b/chip/si_ci_vi_merged_groups.pas @@ -210,7 +210,13 @@ type REG_A018_A01F :array[0..7] of DWORD; // 0xA018 TA_BC_BASE_ADDR :TTA_BC_BASE_ADDR; // 0xA020 TA_BC_BASE_ADDR_HI :TTA_BC_BASE_ADDR_HI; // 0xA021 - REG_A022_A07F :array[0..93] of DWORD; // 0xA022 + REG_A022_A079 :array[0..87] of DWORD; // 0xA022 + COHER_DEST_BASE_HI_0 :TCOHER_DEST_BASE_HI_0; // 0xA07A + COHER_DEST_BASE_HI_1 :TCOHER_DEST_BASE_HI_1; // 0xA07B + COHER_DEST_BASE_HI_2 :TCOHER_DEST_BASE_HI_2; // 0xA07C + COHER_DEST_BASE_HI_3 :TCOHER_DEST_BASE_HI_3; // 0xA07D + COHER_DEST_BASE_2 :TCOHER_DEST_BASE_2; // 0xA07E + COHER_DEST_BASE_3 :TCOHER_DEST_BASE_3; // 0xA07F PA_SC_WINDOW_OFFSET :TPA_SC_WINDOW_OFFSET; // 0xA080 PA_SC_WINDOW_SCISSOR_TL :TPA_SC_WINDOW_SCISSOR_TL; // 0xA081 PA_SC_WINDOW_SCISSOR_BR :TPA_SC_WINDOW_SCISSOR_BR; // 0xA082 @@ -228,7 +234,8 @@ type CB_TARGET_MASK :TCB_TARGET_MASK; // 0xA08E CB_SHADER_MASK :TCB_SHADER_MASK; // 0xA08F PA_SC_GENERIC_SCISSOR :TVPORT_SCISSOR; // 0xA090 - REG_A092_A093 :array[0..1] of DWORD; // 0xA092 + COHER_DEST_BASE_0 :TCOHER_DEST_BASE_0; // 0xA092 + COHER_DEST_BASE_1 :TCOHER_DEST_BASE_1; // 0xA093 PA_SC_VPORT_SCISSOR :array[0..15] of TVPORT_SCISSOR; // 0xA094 PA_SC_VPORT_ZMIN_MAX :array[0..15] of TVPORT_ZMIN_MAX; // 0xA0B4 PA_SC_RASTER_CONFIG :TPA_SC_RASTER_CONFIG; // 0xA0D4 @@ -304,7 +311,9 @@ type SX_MRT6_BLEND_OPT :TSX_MRT6_BLEND_OPT; // 0xA1DE SX_MRT7_BLEND_OPT :TSX_MRT7_BLEND_OPT; // 0xA1DF CB_BLEND_CONTROL :array[0..7] of TCB_BLEND0_CONTROL; // 0xA1E0 - REG_A1E8_A1F4 :array[0..12] of DWORD; // 0xA1E8 + REG_A1E8_A1F2 :array[0..10] of DWORD; // 0xA1E8 + CS_COPY_STATE :TCS_COPY_STATE; // 0xA1F3 + GFX_COPY_STATE :TGFX_COPY_STATE; // 0xA1F4 PA_CL_POINT_X_RAD :TPA_CL_POINT_X_RAD; // 0xA1F5 PA_CL_POINT_Y_RAD :TPA_CL_POINT_Y_RAD; // 0xA1F6 PA_CL_POINT_SIZE :TPA_CL_POINT_SIZE; // 0xA1F7 @@ -454,770 +463,5491 @@ type end; TCONFIG_SPACE_GROUP=bitpacked record - GRBM_CNTL :TGRBM_CNTL; // 0x2000 - GRBM_SKEW_CNTL :TGRBM_SKEW_CNTL; // 0x2001 - GRBM_STATUS2 :TGRBM_STATUS2; // 0x2002 - GRBM_PWR_CNTL :TGRBM_PWR_CNTL; // 0x2003 - GRBM_STATUS :TGRBM_STATUS; // 0x2004 - GRBM_STATUS_SE0 :TGRBM_STATUS_SE0; // 0x2005 - GRBM_STATUS_SE1 :TGRBM_STATUS_SE1; // 0x2006 - REG_2007 :DWORD; // 0x2007 - GRBM_SOFT_RESET :TGRBM_SOFT_RESET; // 0x2008 - GRBM_DEBUG_CNTL :TGRBM_DEBUG_CNTL; // 0x2009 - GRBM_DEBUG_DATA :TGRBM_DEBUG_DATA; // 0x200A - REG_200B :DWORD; // 0x200B - GRBM_GFX_CLKEN_CNTL :TGRBM_GFX_CLKEN_CNTL; // 0x200C - GRBM_WAIT_IDLE_CLOCKS :TGRBM_WAIT_IDLE_CLOCKS; // 0x200D - GRBM_STATUS_SE2 :TGRBM_STATUS_SE2; // 0x200E - GRBM_STATUS_SE3 :TGRBM_STATUS_SE3; // 0x200F - REG_2010_2013 :array[0..3] of DWORD; // 0x2010 - GRBM_DEBUG :TGRBM_DEBUG; // 0x2014 - GRBM_DEBUG_SNAPSHOT :TGRBM_DEBUG_SNAPSHOT; // 0x2015 - GRBM_READ_ERROR :TGRBM_READ_ERROR; // 0x2016 - GRBM_READ_ERROR2 :TGRBM_READ_ERROR2; // 0x2017 - GRBM_INT_CNTL :TGRBM_INT_CNTL; // 0x2018 - GRBM_TRAP_OP :TGRBM_TRAP_OP; // 0x2019 - GRBM_TRAP_ADDR :TGRBM_TRAP_ADDR; // 0x201A - GRBM_TRAP_ADDR_MSK :TGRBM_TRAP_ADDR_MSK; // 0x201B - GRBM_TRAP_WD :TGRBM_TRAP_WD; // 0x201C - GRBM_TRAP_WD_MSK :TGRBM_TRAP_WD_MSK; // 0x201D - GRBM_DSM_BYPASS :TGRBM_DSM_BYPASS; // 0x201E - GRBM_WRITE_ERROR :TGRBM_WRITE_ERROR; // 0x201F - REG_2020_203E :array[0..30] of DWORD; // 0x2020 - GRBM_NOWHERE :TGRBM_NOWHERE; // 0x203F - GRBM_SCRATCH_REG0 :TGRBM_SCRATCH_REG0; // 0x2040 - GRBM_SCRATCH_REG1 :TGRBM_SCRATCH_REG1; // 0x2041 - GRBM_SCRATCH_REG2 :TGRBM_SCRATCH_REG2; // 0x2042 - GRBM_SCRATCH_REG3 :TGRBM_SCRATCH_REG3; // 0x2043 - GRBM_SCRATCH_REG4 :TGRBM_SCRATCH_REG4; // 0x2044 - GRBM_SCRATCH_REG5 :TGRBM_SCRATCH_REG5; // 0x2045 - GRBM_SCRATCH_REG6 :TGRBM_SCRATCH_REG6; // 0x2046 - GRBM_SCRATCH_REG7 :TGRBM_SCRATCH_REG7; // 0x2047 - REG_2048_2083 :array[0..59] of DWORD; // 0x2048 - CP_CPC_STATUS :TCP_CPC_STATUS; // 0x2084 - CP_CPC_BUSY_STAT :TCP_CPC_BUSY_STAT; // 0x2085 - CP_CPC_STALLED_STAT1 :TCP_CPC_STALLED_STAT1; // 0x2086 - CP_CPF_STATUS :TCP_CPF_STATUS; // 0x2087 - CP_CPF_BUSY_STAT :TCP_CPF_BUSY_STAT; // 0x2088 - CP_CPF_STALLED_STAT1 :TCP_CPF_STALLED_STAT1; // 0x2089 - REG_208A :DWORD; // 0x208A - CP_CPC_GRBM_FREE_COUNT :TCP_CPC_GRBM_FREE_COUNT; // 0x208B - REG_208C :DWORD; // 0x208C - CP_MEC_CNTL :TCP_MEC_CNTL; // 0x208D - CP_MEC_ME1_HEADER_DUMP :TCP_MEC_ME1_HEADER_DUMP; // 0x208E - CP_MEC_ME2_HEADER_DUMP :TCP_MEC_ME2_HEADER_DUMP; // 0x208F - CP_CPC_SCRATCH_INDEX :TCP_CPC_SCRATCH_INDEX; // 0x2090 - CP_CPC_SCRATCH_DATA :TCP_CPC_SCRATCH_DATA; // 0x2091 - REG_2092_20A6 :array[0..20] of DWORD; // 0x2092 - CP_CPC_HALT_HYST_COUNT :TCP_CPC_HALT_HYST_COUNT; // 0x20A7 - REG_20A8_20AC :array[0..4] of DWORD; // 0x20A8 - CP_PRT_LOD_STATS_CNTL0 :TCP_PRT_LOD_STATS_CNTL0; // 0x20AD - CP_PRT_LOD_STATS_CNTL1 :TCP_PRT_LOD_STATS_CNTL1; // 0x20AE - CP_PRT_LOD_STATS_CNTL2 :TCP_PRT_LOD_STATS_CNTL2; // 0x20AF - REG_20B0_20BF :array[0..15] of DWORD; // 0x20B0 - CP_CE_COMPARE_COUNT :TCP_CE_COMPARE_COUNT; // 0x20C0 - CP_CE_DE_COUNT :TCP_CE_DE_COUNT; // 0x20C1 - CP_DE_CE_COUNT :TCP_DE_CE_COUNT; // 0x20C2 - CP_DE_LAST_INVAL_COUNT :TCP_DE_LAST_INVAL_COUNT; // 0x20C3 - CP_DE_DE_COUNT :TCP_DE_DE_COUNT; // 0x20C4 - REG_20C5_219B :array[0..214] of DWORD; // 0x20C5 - CP_STALLED_STAT3 :TCP_STALLED_STAT3; // 0x219C - CP_STALLED_STAT1 :TCP_STALLED_STAT1; // 0x219D - CP_STALLED_STAT2 :TCP_STALLED_STAT2; // 0x219E - CP_BUSY_STAT :TCP_BUSY_STAT; // 0x219F - CP_STAT :TCP_STAT; // 0x21A0 - REG_21A1 :DWORD; // 0x21A1 - CP_PFP_HEADER_DUMP :TCP_PFP_HEADER_DUMP; // 0x21A2 - CP_GRBM_FREE_COUNT :TCP_GRBM_FREE_COUNT; // 0x21A3 - CP_CE_HEADER_DUMP :TCP_CE_HEADER_DUMP; // 0x21A4 - REG_21A5_21B3 :array[0..14] of DWORD; // 0x21A5 - CP_CSF_STAT :TCP_CSF_STAT; // 0x21B4 - CP_CSF_CNTL :TCP_CSF_CNTL; // 0x21B5 - REG_21B6_21B7 :array[0..1] of DWORD; // 0x21B6 - CP_CNTX_STAT :TCP_CNTX_STAT; // 0x21B8 - REG_21B9_21BB :array[0..2] of DWORD; // 0x21B9 - CP_ROQ_THRESHOLDS :TCP_ROQ_THRESHOLDS; // 0x21BC - CP_MEQ_STQ_THRESHOLD :TCP_MEQ_STQ_THRESHOLD; // 0x21BD - CP_RB2_RPTR :TCP_RB2_RPTR; // 0x21BE - CP_RB1_RPTR :TCP_RB1_RPTR; // 0x21BF - CP_RB0_RPTR :TCP_RB0_RPTR; // 0x21C0 - REG_21C1_21D4 :array[0..19] of DWORD; // 0x21C1 - CP_ROQ1_THRESHOLDS :TCP_ROQ1_THRESHOLDS; // 0x21D5 - CP_ROQ2_THRESHOLDS :TCP_ROQ2_THRESHOLDS; // 0x21D6 - CP_STQ_THRESHOLDS :TCP_STQ_THRESHOLDS; // 0x21D7 - CP_QUEUE_THRESHOLDS :TCP_QUEUE_THRESHOLDS; // 0x21D8 - CP_MEQ_THRESHOLDS :TCP_MEQ_THRESHOLDS; // 0x21D9 - CP_ROQ_AVAIL :TCP_ROQ_AVAIL; // 0x21DA - CP_STQ_AVAIL :TCP_STQ_AVAIL; // 0x21DB - CP_ROQ2_AVAIL :TCP_ROQ2_AVAIL; // 0x21DC - CP_MEQ_AVAIL :TCP_MEQ_AVAIL; // 0x21DD - CP_CMD_INDEX :TCP_CMD_INDEX; // 0x21DE - CP_CMD_DATA :TCP_CMD_DATA; // 0x21DF - CP_ROQ_RB_STAT :TCP_ROQ_RB_STAT; // 0x21E0 - CP_ROQ_IB1_STAT :TCP_ROQ_IB1_STAT; // 0x21E1 - CP_ROQ_IB2_STAT :TCP_ROQ_IB2_STAT; // 0x21E2 - CP_STQ_STAT :TCP_STQ_STAT; // 0x21E3 - CP_STQ_WR_STAT :TCP_STQ_WR_STAT; // 0x21E4 - CP_MEQ_STAT :TCP_MEQ_STAT; // 0x21E5 - CP_CEQ1_AVAIL :TCP_CEQ1_AVAIL; // 0x21E6 - CP_CEQ2_AVAIL :TCP_CEQ2_AVAIL; // 0x21E7 - CP_CE_ROQ_RB_STAT :TCP_CE_ROQ_RB_STAT; // 0x21E8 - CP_CE_ROQ_IB1_STAT :TCP_CE_ROQ_IB1_STAT; // 0x21E9 - CP_CE_ROQ_IB2_STAT :TCP_CE_ROQ_IB2_STAT; // 0x21EA - REG_21EB_21F6 :array[0..11] of DWORD; // 0x21EB - CP_INT_STAT_DEBUG :TCP_INT_STAT_DEBUG; // 0x21F7 - REG_21F8_222B :array[0..51] of DWORD; // 0x21F8 - VGT_VTX_VECT_EJECT_REG :TVGT_VTX_VECT_EJECT_REG; // 0x222C - VGT_DMA_DATA_FIFO_DEPTH :TVGT_DMA_DATA_FIFO_DEPTH; // 0x222D - VGT_DMA_REQ_FIFO_DEPTH :TVGT_DMA_REQ_FIFO_DEPTH; // 0x222E - VGT_DRAW_INIT_FIFO_DEPTH :TVGT_DRAW_INIT_FIFO_DEPTH; // 0x222F - VGT_LAST_COPY_STATE :TVGT_LAST_COPY_STATE; // 0x2230 - VGT_CACHE_INVALIDATION :TVGT_CACHE_INVALIDATION; // 0x2231 - VGT_RESET_DEBUG :TVGT_RESET_DEBUG; // 0x2232 - VGT_STRMOUT_DELAY :TVGT_STRMOUT_DELAY; // 0x2233 - VGT_FIFO_DEPTHS :TVGT_FIFO_DEPTHS; // 0x2234 - VGT_GS_VERTEX_REUSE :TVGT_GS_VERTEX_REUSE; // 0x2235 - VGT_MC_LAT_CNTL :TVGT_MC_LAT_CNTL; // 0x2236 - IA_CNTL_STATUS :TIA_CNTL_STATUS; // 0x2237 - VGT_DEBUG_CNTL :TVGT_DEBUG_CNTL; // 0x2238 - VGT_DEBUG_DATA :TVGT_DEBUG_DATA; // 0x2239 - IA_DEBUG_CNTL :TIA_DEBUG_CNTL; // 0x223A - IA_DEBUG_DATA :TIA_DEBUG_DATA; // 0x223B - VGT_CNTL_STATUS :TVGT_CNTL_STATUS; // 0x223C - WD_DEBUG_CNTL :TWD_DEBUG_CNTL; // 0x223D - WD_DEBUG_DATA :TWD_DEBUG_DATA; // 0x223E - WD_CNTL_STATUS :TWD_CNTL_STATUS; // 0x223F - REG_2240_2241 :array[0..1] of DWORD; // 0x2240 - WD_QOS :TWD_QOS; // 0x2242 - REG_2243_2262 :array[0..31] of DWORD; // 0x2243 - VGT_SYS_CONFIG :TVGT_SYS_CONFIG; // 0x2263 - REG_2264_2267 :array[0..3] of DWORD; // 0x2264 - VGT_VS_MAX_WAVE_ID :TVGT_VS_MAX_WAVE_ID; // 0x2268 - REG_2269_2270 :array[0..7] of DWORD; // 0x2269 - VGT_DMA_PRIMITIVE_TYPE :TVGT_DMA_PRIMITIVE_TYPE; // 0x2271 - VGT_DMA_CONTROL :TVGT_DMA_CONTROL; // 0x2272 - VGT_DMA_LS_HS_CONFIG :TVGT_DMA_LS_HS_CONFIG; // 0x2273 - REG_2274_227F :array[0..11] of DWORD; // 0x2274 - PA_SU_DEBUG_CNTL :TPA_SU_DEBUG_CNTL; // 0x2280 - PA_SU_DEBUG_DATA :TPA_SU_DEBUG_DATA; // 0x2281 - REG_2282_2283 :array[0..1] of DWORD; // 0x2282 - PA_CL_CNTL_STATUS :TPA_CL_CNTL_STATUS; // 0x2284 - PA_CL_ENHANCE :TPA_CL_ENHANCE; // 0x2285 - PA_CL_RESET_DEBUG :TPA_CL_RESET_DEBUG; // 0x2286 - REG_2287_2293 :array[0..12] of DWORD; // 0x2287 - PA_SU_CNTL_STATUS :TPA_SU_CNTL_STATUS; // 0x2294 - PA_SC_FIFO_DEPTH_CNTL :TPA_SC_FIFO_DEPTH_CNTL; // 0x2295 - REG_2296_22BF :array[0..41] of DWORD; // 0x2296 - PA_SC_P3D_TRAP_SCREEN_HV_LOCK :TPA_SC_P3D_TRAP_SCREEN_HV_LOCK; // 0x22C0 - PA_SC_HP3D_TRAP_SCREEN_HV_LOCK:TPA_SC_HP3D_TRAP_SCREEN_HV_LOCK; // 0x22C1 - PA_SC_TRAP_SCREEN_HV_LOCK :TPA_SC_TRAP_SCREEN_HV_LOCK; // 0x22C2 - REG_22C3_22C8 :array[0..5] of DWORD; // 0x22C3 - PA_SC_FORCE_EOV_MAX_CNTS :TPA_SC_FORCE_EOV_MAX_CNTS; // 0x22C9 - REG_22CA_22F2 :array[0..40] of DWORD; // 0x22CA - PA_SC_FIFO_SIZE :TPA_SC_FIFO_SIZE; // 0x22F3 - REG_22F4 :DWORD; // 0x22F4 - PA_SC_IF_FIFO_SIZE :TPA_SC_IF_FIFO_SIZE; // 0x22F5 - PA_SC_DEBUG_CNTL :TPA_SC_DEBUG_CNTL; // 0x22F6 - PA_SC_DEBUG_DATA :TPA_SC_DEBUG_DATA; // 0x22F7 - REG_22F8_22FB :array[0..3] of DWORD; // 0x22F8 - PA_SC_ENHANCE :TPA_SC_ENHANCE; // 0x22FC - REG_22FD_238F :array[0..146] of DWORD; // 0x22FD - SQ_THREAD_TRACE_CNTR :TSQ_THREAD_TRACE_CNTR; // 0x2390 - REG_2391_23BF :array[0..46] of DWORD; // 0x2391 - SQ_BUF_RSRC_WORD0 :TSQ_BUF_RSRC_WORD0; // 0x23C0 - SQ_BUF_RSRC_WORD1 :TSQ_BUF_RSRC_WORD1; // 0x23C1 - SQ_BUF_RSRC_WORD2 :TSQ_BUF_RSRC_WORD2; // 0x23C2 - SQ_BUF_RSRC_WORD3 :TSQ_BUF_RSRC_WORD3; // 0x23C3 - SQ_IMG_RSRC_WORD0 :TSQ_IMG_RSRC_WORD0; // 0x23C4 - SQ_IMG_RSRC_WORD1 :TSQ_IMG_RSRC_WORD1; // 0x23C5 - SQ_IMG_RSRC_WORD2 :TSQ_IMG_RSRC_WORD2; // 0x23C6 - SQ_IMG_RSRC_WORD3 :TSQ_IMG_RSRC_WORD3; // 0x23C7 - SQ_IMG_RSRC_WORD4 :TSQ_IMG_RSRC_WORD4; // 0x23C8 - SQ_IMG_RSRC_WORD5 :TSQ_IMG_RSRC_WORD5; // 0x23C9 - SQ_IMG_RSRC_WORD6 :TSQ_IMG_RSRC_WORD6; // 0x23CA - SQ_IMG_RSRC_WORD7 :TSQ_IMG_RSRC_WORD7; // 0x23CB - SQ_IMG_SAMP_WORD0 :TSQ_IMG_SAMP_WORD0; // 0x23CC - SQ_IMG_SAMP_WORD1 :TSQ_IMG_SAMP_WORD1; // 0x23CD - SQ_IMG_SAMP_WORD2 :TSQ_IMG_SAMP_WORD2; // 0x23CE - SQ_IMG_SAMP_WORD3 :TSQ_IMG_SAMP_WORD3; // 0x23CF - REG_23D0_2413 :array[0..67] of DWORD; // 0x23D0 - SX_DEBUG_BUSY :TSX_DEBUG_BUSY; // 0x2414 - SX_DEBUG_BUSY_2 :TSX_DEBUG_BUSY_2; // 0x2415 - SX_DEBUG_BUSY_3 :TSX_DEBUG_BUSY_3; // 0x2416 - SX_DEBUG_BUSY_4 :TSX_DEBUG_BUSY_4; // 0x2417 - SX_DEBUG_1 :TSX_DEBUG_1; // 0x2418 - REG_2419_2439 :array[0..32] of DWORD; // 0x2419 - SPI_PS_MAX_WAVE_ID :TSPI_PS_MAX_WAVE_ID; // 0x243A - SPI_START_PHASE :TSPI_START_PHASE; // 0x243B - SPI_GFX_CNTL :TSPI_GFX_CNTL; // 0x243C - REG_243D_243F :array[0..2] of DWORD; // 0x243D - SPI_CONFIG_CNTL :TSPI_CONFIG_CNTL; // 0x2440 - SPI_DEBUG_CNTL :TSPI_DEBUG_CNTL; // 0x2441 - SPI_DEBUG_READ :TSPI_DEBUG_READ; // 0x2442 - SPI_DSM_CNTL :TSPI_DSM_CNTL; // 0x2443 - SPI_EDC_CNT :TSPI_EDC_CNT; // 0x2444 - REG_2445_244E :array[0..9] of DWORD; // 0x2445 - SPI_CONFIG_CNTL_1 :TSPI_CONFIG_CNTL_1; // 0x244F - SPI_DEBUG_BUSY :TSPI_DEBUG_BUSY; // 0x2450 - SPI_CONFIG_CNTL_2 :TSPI_CONFIG_CNTL_2; // 0x2451 - REG_2452_24A9 :array[0..87] of DWORD; // 0x2452 - SPI_WF_LIFETIME_CNTL :TSPI_WF_LIFETIME_CNTL; // 0x24AA - SPI_WF_LIFETIME_LIMIT_0 :TSPI_WF_LIFETIME_LIMIT_0; // 0x24AB - SPI_WF_LIFETIME_LIMIT_1 :TSPI_WF_LIFETIME_LIMIT_1; // 0x24AC - SPI_WF_LIFETIME_LIMIT_2 :TSPI_WF_LIFETIME_LIMIT_2; // 0x24AD - SPI_WF_LIFETIME_LIMIT_3 :TSPI_WF_LIFETIME_LIMIT_3; // 0x24AE - SPI_WF_LIFETIME_LIMIT_4 :TSPI_WF_LIFETIME_LIMIT_4; // 0x24AF - SPI_WF_LIFETIME_LIMIT_5 :TSPI_WF_LIFETIME_LIMIT_5; // 0x24B0 - SPI_WF_LIFETIME_LIMIT_6 :TSPI_WF_LIFETIME_LIMIT_6; // 0x24B1 - SPI_WF_LIFETIME_LIMIT_7 :TSPI_WF_LIFETIME_LIMIT_7; // 0x24B2 - SPI_WF_LIFETIME_LIMIT_8 :TSPI_WF_LIFETIME_LIMIT_8; // 0x24B3 - SPI_WF_LIFETIME_LIMIT_9 :TSPI_WF_LIFETIME_LIMIT_9; // 0x24B4 - SPI_WF_LIFETIME_STATUS_0 :TSPI_WF_LIFETIME_STATUS_0; // 0x24B5 - SPI_WF_LIFETIME_STATUS_1 :TSPI_WF_LIFETIME_STATUS_1; // 0x24B6 - SPI_WF_LIFETIME_STATUS_2 :TSPI_WF_LIFETIME_STATUS_2; // 0x24B7 - SPI_WF_LIFETIME_STATUS_3 :TSPI_WF_LIFETIME_STATUS_3; // 0x24B8 - SPI_WF_LIFETIME_STATUS_4 :TSPI_WF_LIFETIME_STATUS_4; // 0x24B9 - SPI_WF_LIFETIME_STATUS_5 :TSPI_WF_LIFETIME_STATUS_5; // 0x24BA - SPI_WF_LIFETIME_STATUS_6 :TSPI_WF_LIFETIME_STATUS_6; // 0x24BB - SPI_WF_LIFETIME_STATUS_7 :TSPI_WF_LIFETIME_STATUS_7; // 0x24BC - SPI_WF_LIFETIME_STATUS_8 :TSPI_WF_LIFETIME_STATUS_8; // 0x24BD - SPI_WF_LIFETIME_STATUS_9 :TSPI_WF_LIFETIME_STATUS_9; // 0x24BE - SPI_WF_LIFETIME_STATUS_10 :TSPI_WF_LIFETIME_STATUS_10; // 0x24BF - SPI_WF_LIFETIME_STATUS_11 :TSPI_WF_LIFETIME_STATUS_11; // 0x24C0 - SPI_WF_LIFETIME_STATUS_12 :TSPI_WF_LIFETIME_STATUS_12; // 0x24C1 - SPI_WF_LIFETIME_STATUS_13 :TSPI_WF_LIFETIME_STATUS_13; // 0x24C2 - SPI_WF_LIFETIME_STATUS_14 :TSPI_WF_LIFETIME_STATUS_14; // 0x24C3 - SPI_WF_LIFETIME_STATUS_15 :TSPI_WF_LIFETIME_STATUS_15; // 0x24C4 - SPI_WF_LIFETIME_STATUS_16 :TSPI_WF_LIFETIME_STATUS_16; // 0x24C5 - SPI_WF_LIFETIME_STATUS_17 :TSPI_WF_LIFETIME_STATUS_17; // 0x24C6 - SPI_WF_LIFETIME_STATUS_18 :TSPI_WF_LIFETIME_STATUS_18; // 0x24C7 - SPI_WF_LIFETIME_STATUS_19 :TSPI_WF_LIFETIME_STATUS_19; // 0x24C8 - SPI_WF_LIFETIME_STATUS_20 :TSPI_WF_LIFETIME_STATUS_20; // 0x24C9 - SPI_WF_LIFETIME_DEBUG :TSPI_WF_LIFETIME_DEBUG; // 0x24CA - REG_24CB_24D2 :array[0..7] of DWORD; // 0x24CB - SPI_SLAVE_DEBUG_BUSY :TSPI_SLAVE_DEBUG_BUSY; // 0x24D3 - SPI_LB_CTR_CTRL :TSPI_LB_CTR_CTRL; // 0x24D4 - SPI_LB_CU_MASK :TSPI_LB_CU_MASK; // 0x24D5 - SPI_LB_DATA_REG :TSPI_LB_DATA_REG; // 0x24D6 - SPI_PG_ENABLE_STATIC_CU_MASK :TSPI_PG_ENABLE_STATIC_CU_MASK; // 0x24D7 - SPI_GDS_CREDITS :TSPI_GDS_CREDITS; // 0x24D8 - SPI_SX_EXPORT_BUFFER_SIZES :TSPI_SX_EXPORT_BUFFER_SIZES; // 0x24D9 - SPI_SX_SCOREBOARD_BUFFER_SIZES:TSPI_SX_SCOREBOARD_BUFFER_SIZES; // 0x24DA - SPI_CSQ_WF_ACTIVE_STATUS :TSPI_CSQ_WF_ACTIVE_STATUS; // 0x24DB - SPI_CSQ_WF_ACTIVE_COUNT_0 :TSPI_CSQ_WF_ACTIVE_COUNT_0; // 0x24DC - SPI_CSQ_WF_ACTIVE_COUNT_1 :TSPI_CSQ_WF_ACTIVE_COUNT_1; // 0x24DD - SPI_CSQ_WF_ACTIVE_COUNT_2 :TSPI_CSQ_WF_ACTIVE_COUNT_2; // 0x24DE - SPI_CSQ_WF_ACTIVE_COUNT_3 :TSPI_CSQ_WF_ACTIVE_COUNT_3; // 0x24DF - SPI_CSQ_WF_ACTIVE_COUNT_4 :TSPI_CSQ_WF_ACTIVE_COUNT_4; // 0x24E0 - SPI_CSQ_WF_ACTIVE_COUNT_5 :TSPI_CSQ_WF_ACTIVE_COUNT_5; // 0x24E1 - SPI_CSQ_WF_ACTIVE_COUNT_6 :TSPI_CSQ_WF_ACTIVE_COUNT_6; // 0x24E2 - SPI_CSQ_WF_ACTIVE_COUNT_7 :TSPI_CSQ_WF_ACTIVE_COUNT_7; // 0x24E3 - REG_24E4_24EB :array[0..7] of DWORD; // 0x24E4 - SPI_P0_TRAP_SCREEN_PSBA_LO :TSPI_P0_TRAP_SCREEN_PSBA_LO; // 0x24EC - SPI_P0_TRAP_SCREEN_PSBA_HI :TSPI_P0_TRAP_SCREEN_PSBA_HI; // 0x24ED - SPI_P0_TRAP_SCREEN_PSMA_LO :TSPI_P0_TRAP_SCREEN_PSMA_LO; // 0x24EE - SPI_P0_TRAP_SCREEN_PSMA_HI :TSPI_P0_TRAP_SCREEN_PSMA_HI; // 0x24EF - SPI_P0_TRAP_SCREEN_GPR_MIN :TSPI_P0_TRAP_SCREEN_GPR_MIN; // 0x24F0 - SPI_P1_TRAP_SCREEN_PSBA_LO :TSPI_P1_TRAP_SCREEN_PSBA_LO; // 0x24F1 - SPI_P1_TRAP_SCREEN_PSBA_HI :TSPI_P1_TRAP_SCREEN_PSBA_HI; // 0x24F2 - SPI_P1_TRAP_SCREEN_PSMA_LO :TSPI_P1_TRAP_SCREEN_PSMA_LO; // 0x24F3 - SPI_P1_TRAP_SCREEN_PSMA_HI :TSPI_P1_TRAP_SCREEN_PSMA_HI; // 0x24F4 - SPI_P1_TRAP_SCREEN_GPR_MIN :TSPI_P1_TRAP_SCREEN_GPR_MIN; // 0x24F5 - REG_24F6_2524 :array[0..46] of DWORD; // 0x24F6 - TD_CNTL :TTD_CNTL; // 0x2525 - TD_STATUS :TTD_STATUS; // 0x2526 - REG_2527 :DWORD; // 0x2527 - TD_DEBUG_INDEX :TTD_DEBUG_INDEX; // 0x2528 - TD_DEBUG_DATA :TTD_DEBUG_DATA; // 0x2529 - REG_252A_252E :array[0..4] of DWORD; // 0x252A - TD_DSM_CNTL :TTD_DSM_CNTL; // 0x252F - REG_2530_2532 :array[0..2] of DWORD; // 0x2530 - TD_SCRATCH :TTD_SCRATCH; // 0x2533 - REG_2534_2540 :array[0..12] of DWORD; // 0x2534 - TA_CNTL :TTA_CNTL; // 0x2541 - TA_CNTL_AUX :TTA_CNTL_AUX; // 0x2542 - TA_RESERVED_010C :TTA_RESERVED_010C; // 0x2543 - REG_2544_2547 :array[0..3] of DWORD; // 0x2544 - TA_STATUS :TTA_STATUS; // 0x2548 - REG_2549_254B :array[0..2] of DWORD; // 0x2549 - TA_DEBUG_INDEX :TTA_DEBUG_INDEX; // 0x254C - TA_DEBUG_DATA :TTA_DEBUG_DATA; // 0x254D - REG_254E_2563 :array[0..21] of DWORD; // 0x254E - TA_SCRATCH :TTA_SCRATCH; // 0x2564 - REG_2565_25BF :array[0..90] of DWORD; // 0x2565 - GDS_CONFIG :TGDS_CONFIG; // 0x25C0 - GDS_CNTL_STATUS :TGDS_CNTL_STATUS; // 0x25C1 - GDS_ENHANCE2 :TGDS_ENHANCE2; // 0x25C2 - GDS_PROTECTION_FAULT :TGDS_PROTECTION_FAULT; // 0x25C3 - GDS_VM_PROTECTION_FAULT :TGDS_VM_PROTECTION_FAULT; // 0x25C4 - GDS_EDC_CNT :TGDS_EDC_CNT; // 0x25C5 - GDS_EDC_GRBM_CNT :TGDS_EDC_GRBM_CNT; // 0x25C6 - GDS_EDC_OA_DED :TGDS_EDC_OA_DED; // 0x25C7 - GDS_DEBUG_CNTL :TGDS_DEBUG_CNTL; // 0x25C8 - GDS_DEBUG_DATA :TGDS_DEBUG_DATA; // 0x25C9 - GDS_DSM_CNTL :TGDS_DSM_CNTL; // 0x25CA - REG_25CB_260B :array[0..64] of DWORD; // 0x25CB - DB_DEBUG :TDB_DEBUG; // 0x260C - DB_DEBUG2 :TDB_DEBUG2; // 0x260D - DB_DEBUG3 :TDB_DEBUG3; // 0x260E - DB_DEBUG4 :TDB_DEBUG4; // 0x260F - REG_2610_2613 :array[0..3] of DWORD; // 0x2610 - DB_CREDIT_LIMIT :TDB_CREDIT_LIMIT; // 0x2614 - DB_WATERMARKS :TDB_WATERMARKS; // 0x2615 - DB_SUBTILE_CONTROL :TDB_SUBTILE_CONTROL; // 0x2616 - DB_FREE_CACHELINES :TDB_FREE_CACHELINES; // 0x2617 - DB_FIFO_DEPTH1 :TDB_FIFO_DEPTH1; // 0x2618 - DB_FIFO_DEPTH2 :TDB_FIFO_DEPTH2; // 0x2619 - REG_261A :DWORD; // 0x261A - DB_RING_CONTROL :TDB_RING_CONTROL; // 0x261B - REG_261C_261F :array[0..3] of DWORD; // 0x261C - DB_READ_DEBUG_0 :TDB_READ_DEBUG_0; // 0x2620 - DB_READ_DEBUG_1 :TDB_READ_DEBUG_1; // 0x2621 - DB_READ_DEBUG_2 :TDB_READ_DEBUG_2; // 0x2622 - DB_READ_DEBUG_3 :TDB_READ_DEBUG_3; // 0x2623 - DB_READ_DEBUG_4 :TDB_READ_DEBUG_4; // 0x2624 - DB_READ_DEBUG_5 :TDB_READ_DEBUG_5; // 0x2625 - DB_READ_DEBUG_6 :TDB_READ_DEBUG_6; // 0x2626 - DB_READ_DEBUG_7 :TDB_READ_DEBUG_7; // 0x2627 - DB_READ_DEBUG_8 :TDB_READ_DEBUG_8; // 0x2628 - DB_READ_DEBUG_9 :TDB_READ_DEBUG_9; // 0x2629 - DB_READ_DEBUG_A :TDB_READ_DEBUG_A; // 0x262A - DB_READ_DEBUG_B :TDB_READ_DEBUG_B; // 0x262B - DB_READ_DEBUG_C :TDB_READ_DEBUG_C; // 0x262C - DB_READ_DEBUG_D :TDB_READ_DEBUG_D; // 0x262D - DB_READ_DEBUG_E :TDB_READ_DEBUG_E; // 0x262E - DB_READ_DEBUG_F :TDB_READ_DEBUG_F; // 0x262F - REG_2630_2682 :array[0..82] of DWORD; // 0x2630 - CB_HW_CONTROL_3 :TCB_HW_CONTROL_3; // 0x2683 - CB_HW_CONTROL :TCB_HW_CONTROL; // 0x2684 - CB_HW_CONTROL_1 :TCB_HW_CONTROL_1; // 0x2685 - CB_HW_CONTROL_2 :TCB_HW_CONTROL_2; // 0x2686 - CB_DCC_CONFIG :TCB_DCC_CONFIG; // 0x2687 - REG_2688_2698 :array[0..16] of DWORD; // 0x2688 - CB_DEBUG_BUS_1 :TCB_DEBUG_BUS_1; // 0x2699 - CB_DEBUG_BUS_2 :TCB_DEBUG_BUS_2; // 0x269A - REG_269B_26A4 :array[0..9] of DWORD; // 0x269B - CB_DEBUG_BUS_13 :TCB_DEBUG_BUS_13; // 0x26A5 - CB_DEBUG_BUS_14 :TCB_DEBUG_BUS_14; // 0x26A6 - CB_DEBUG_BUS_15 :TCB_DEBUG_BUS_15; // 0x26A7 - CB_DEBUG_BUS_16 :TCB_DEBUG_BUS_16; // 0x26A8 - CB_DEBUG_BUS_17 :TCB_DEBUG_BUS_17; // 0x26A9 - CB_DEBUG_BUS_18 :TCB_DEBUG_BUS_18; // 0x26AA - CB_DEBUG_BUS_19 :TCB_DEBUG_BUS_19; // 0x26AB - CB_DEBUG_BUS_20 :TCB_DEBUG_BUS_20; // 0x26AC - CB_DEBUG_BUS_21 :TCB_DEBUG_BUS_21; // 0x26AD - CB_DEBUG_BUS_22 :TCB_DEBUG_BUS_22; // 0x26AE - REG_26AF_2AFF :array[0..1104] of DWORD; // 0x26AF - TCP_INVALIDATE :TTCP_INVALIDATE; // 0x2B00 - TCP_STATUS :TTCP_STATUS; // 0x2B01 - TCP_CNTL :TTCP_CNTL; // 0x2B02 - TCP_CHAN_STEER_LO :TTCP_CHAN_STEER_LO; // 0x2B03 - TCP_CHAN_STEER_HI :TTCP_CHAN_STEER_HI; // 0x2B04 - TCP_ADDR_CONFIG :TTCP_ADDR_CONFIG; // 0x2B05 - TCP_CREDIT :TTCP_CREDIT; // 0x2B06 - REG_2B07_2B15 :array[0..14] of DWORD; // 0x2B07 - TCP_BUFFER_ADDR_HASH_CNTL :TTCP_BUFFER_ADDR_HASH_CNTL; // 0x2B16 - TCP_EDC_CNT :TTCP_EDC_CNT; // 0x2B17 - REG_2B18_2B7F :array[0..103] of DWORD; // 0x2B18 - TCC_CTRL :TTCC_CTRL; // 0x2B80 - REG_2B81 :DWORD; // 0x2B81 - TCC_EDC_CNT :TTCC_EDC_CNT; // 0x2B82 - TCC_REDUNDANCY :TTCC_REDUNDANCY; // 0x2B83 - TCC_EXE_DISABLE :TTCC_EXE_DISABLE; // 0x2B84 - TCC_DSM_CNTL :TTCC_DSM_CNTL; // 0x2B85 - REG_2B86_2BBF :array[0..57] of DWORD; // 0x2B86 - TCA_CTRL :TTCA_CTRL; // 0x2BC0 - REG_2BC1_301F :array[0..1118] of DWORD; // 0x2BC1 - CP_DFY_CNTL :TCP_DFY_CNTL; // 0x3020 - CP_DFY_STAT :TCP_DFY_STAT; // 0x3021 - CP_DFY_ADDR_HI :TCP_DFY_ADDR_HI; // 0x3022 - CP_DFY_ADDR_LO :TCP_DFY_ADDR_LO; // 0x3023 - CP_DFY_DATA_0 :TCP_DFY_DATA_0; // 0x3024 - CP_DFY_DATA_1 :TCP_DFY_DATA_1; // 0x3025 - CP_DFY_DATA_2 :TCP_DFY_DATA_2; // 0x3026 - CP_DFY_DATA_3 :TCP_DFY_DATA_3; // 0x3027 - CP_DFY_DATA_4 :TCP_DFY_DATA_4; // 0x3028 - CP_DFY_DATA_5 :TCP_DFY_DATA_5; // 0x3029 - CP_DFY_DATA_6 :TCP_DFY_DATA_6; // 0x302A - CP_DFY_DATA_7 :TCP_DFY_DATA_7; // 0x302B - CP_DFY_DATA_8 :TCP_DFY_DATA_8; // 0x302C - CP_DFY_DATA_9 :TCP_DFY_DATA_9; // 0x302D - CP_DFY_DATA_10 :TCP_DFY_DATA_10; // 0x302E - CP_DFY_DATA_11 :TCP_DFY_DATA_11; // 0x302F - CP_DFY_DATA_12 :TCP_DFY_DATA_12; // 0x3030 - CP_DFY_DATA_13 :TCP_DFY_DATA_13; // 0x3031 - CP_DFY_DATA_14 :TCP_DFY_DATA_14; // 0x3032 - CP_DFY_DATA_15 :TCP_DFY_DATA_15; // 0x3033 - CP_DFY_CMD :TCP_DFY_CMD; // 0x3034 - REG_3035 :DWORD; // 0x3035 - CP_CPC_MGCG_SYNC_CNTL :TCP_CPC_MGCG_SYNC_CNTL; // 0x3036 - REG_3037 :DWORD; // 0x3037 - CP_VIRT_STATUS :TCP_VIRT_STATUS; // 0x3038 - REG_3039_303F :array[0..6] of DWORD; // 0x3039 - CP_RB0_BASE :TCP_RB0_BASE; // 0x3040 - CP_RB0_CNTL :TCP_RB0_CNTL; // 0x3041 - REG_3042 :DWORD; // 0x3042 - CP_RB0_RPTR_ADDR :TCP_RB0_RPTR_ADDR; // 0x3043 - CP_RB0_RPTR_ADDR_HI :TCP_RB0_RPTR_ADDR_HI; // 0x3044 - CP_RB0_WPTR :TCP_RB0_WPTR; // 0x3045 - REG_3046_3048 :array[0..2] of DWORD; // 0x3046 - CP_INT_CNTL :TCP_INT_CNTL; // 0x3049 - CP_INT_STATUS :TCP_INT_STATUS; // 0x304A - CP_DEVICE_ID :TCP_DEVICE_ID; // 0x304B - CP_ME0_PIPE_PRIORITY_CNTS :TCP_ME0_PIPE_PRIORITY_CNTS; // 0x304C - CP_ME0_PIPE0_PRIORITY :TCP_ME0_PIPE0_PRIORITY; // 0x304D - CP_ME0_PIPE1_PRIORITY :TCP_ME0_PIPE1_PRIORITY; // 0x304E - CP_ME0_PIPE2_PRIORITY :TCP_ME0_PIPE2_PRIORITY; // 0x304F - CP_ENDIAN_SWAP :TCP_ENDIAN_SWAP; // 0x3050 - REG_3051 :DWORD; // 0x3051 - CP_ME0_PIPE0_VMID :TCP_ME0_PIPE0_VMID; // 0x3052 - CP_ME0_PIPE1_VMID :TCP_ME0_PIPE1_VMID; // 0x3053 - REG_3054_305B :array[0..7] of DWORD; // 0x3054 - CP_MEC_DOORBELL_RANGE_LOWER :TCP_MEC_DOORBELL_RANGE_LOWER; // 0x305C - CP_MEC_DOORBELL_RANGE_UPPER :TCP_MEC_DOORBELL_RANGE_UPPER; // 0x305D - REG_305E_305F :array[0..1] of DWORD; // 0x305E - CP_RB1_BASE :TCP_RB1_BASE; // 0x3060 - CP_RB1_CNTL :TCP_RB1_CNTL; // 0x3061 - CP_RB1_RPTR_ADDR :TCP_RB1_RPTR_ADDR; // 0x3062 - CP_RB1_RPTR_ADDR_HI :TCP_RB1_RPTR_ADDR_HI; // 0x3063 - CP_RB1_WPTR :TCP_RB1_WPTR; // 0x3064 - CP_RB2_BASE :TCP_RB2_BASE; // 0x3065 - CP_RB2_CNTL :TCP_RB2_CNTL; // 0x3066 - CP_RB2_RPTR_ADDR :TCP_RB2_RPTR_ADDR; // 0x3067 - CP_RB2_RPTR_ADDR_HI :TCP_RB2_RPTR_ADDR_HI; // 0x3068 - CP_RB2_WPTR :TCP_RB2_WPTR; // 0x3069 - CP_INT_CNTL_RING0 :TCP_INT_CNTL_RING0; // 0x306A - CP_INT_CNTL_RING1 :TCP_INT_CNTL_RING1; // 0x306B - CP_INT_CNTL_RING2 :TCP_INT_CNTL_RING2; // 0x306C - CP_INT_STATUS_RING0 :TCP_INT_STATUS_RING0; // 0x306D - CP_INT_STATUS_RING1 :TCP_INT_STATUS_RING1; // 0x306E - CP_INT_STATUS_RING2 :TCP_INT_STATUS_RING2; // 0x306F - REG_3070_3077 :array[0..7] of DWORD; // 0x3070 - CP_PWR_CNTL :TCP_PWR_CNTL; // 0x3078 - CP_MEM_SLP_CNTL :TCP_MEM_SLP_CNTL; // 0x3079 - CP_ECC_FIRSTOCCURRENCE :TCP_ECC_FIRSTOCCURRENCE; // 0x307A - CP_ECC_FIRSTOCCURRENCE_RING0 :TCP_ECC_FIRSTOCCURRENCE_RING0; // 0x307B - CP_ECC_FIRSTOCCURRENCE_RING1 :TCP_ECC_FIRSTOCCURRENCE_RING1; // 0x307C - CP_ECC_FIRSTOCCURRENCE_RING2 :TCP_ECC_FIRSTOCCURRENCE_RING2; // 0x307D - REG_307E :DWORD; // 0x307E - CP_DEBUG :TCP_DEBUG; // 0x307F - REG_3080_3082 :array[0..2] of DWORD; // 0x3080 - CP_PQ_WPTR_POLL_CNTL :TCP_PQ_WPTR_POLL_CNTL; // 0x3083 - CP_PQ_WPTR_POLL_CNTL1 :TCP_PQ_WPTR_POLL_CNTL1; // 0x3084 - CP_ME1_PIPE0_INT_CNTL :TCP_ME1_PIPE0_INT_CNTL; // 0x3085 - CP_ME1_PIPE1_INT_CNTL :TCP_ME1_PIPE1_INT_CNTL; // 0x3086 - CP_ME1_PIPE2_INT_CNTL :TCP_ME1_PIPE2_INT_CNTL; // 0x3087 - CP_ME1_PIPE3_INT_CNTL :TCP_ME1_PIPE3_INT_CNTL; // 0x3088 - CP_ME2_PIPE0_INT_CNTL :TCP_ME2_PIPE0_INT_CNTL; // 0x3089 - CP_ME2_PIPE1_INT_CNTL :TCP_ME2_PIPE1_INT_CNTL; // 0x308A - CP_ME2_PIPE2_INT_CNTL :TCP_ME2_PIPE2_INT_CNTL; // 0x308B - CP_ME2_PIPE3_INT_CNTL :TCP_ME2_PIPE3_INT_CNTL; // 0x308C - CP_ME1_PIPE0_INT_STATUS :TCP_ME1_PIPE0_INT_STATUS; // 0x308D - CP_ME1_PIPE1_INT_STATUS :TCP_ME1_PIPE1_INT_STATUS; // 0x308E - CP_ME1_PIPE2_INT_STATUS :TCP_ME1_PIPE2_INT_STATUS; // 0x308F - CP_ME1_PIPE3_INT_STATUS :TCP_ME1_PIPE3_INT_STATUS; // 0x3090 - CP_ME2_PIPE0_INT_STATUS :TCP_ME2_PIPE0_INT_STATUS; // 0x3091 - CP_ME2_PIPE1_INT_STATUS :TCP_ME2_PIPE1_INT_STATUS; // 0x3092 - CP_ME2_PIPE2_INT_STATUS :TCP_ME2_PIPE2_INT_STATUS; // 0x3093 - CP_ME2_PIPE3_INT_STATUS :TCP_ME2_PIPE3_INT_STATUS; // 0x3094 - CP_ME1_INT_STAT_DEBUG :TCP_ME1_INT_STAT_DEBUG; // 0x3095 - CP_ME2_INT_STAT_DEBUG :TCP_ME2_INT_STAT_DEBUG; // 0x3096 - REG_3097_3098 :array[0..1] of DWORD; // 0x3097 - CP_ME1_PIPE_PRIORITY_CNTS :TCP_ME1_PIPE_PRIORITY_CNTS; // 0x3099 - CP_ME1_PIPE0_PRIORITY :TCP_ME1_PIPE0_PRIORITY; // 0x309A - CP_ME1_PIPE1_PRIORITY :TCP_ME1_PIPE1_PRIORITY; // 0x309B - CP_ME1_PIPE2_PRIORITY :TCP_ME1_PIPE2_PRIORITY; // 0x309C - CP_ME1_PIPE3_PRIORITY :TCP_ME1_PIPE3_PRIORITY; // 0x309D - CP_ME2_PIPE_PRIORITY_CNTS :TCP_ME2_PIPE_PRIORITY_CNTS; // 0x309E - CP_ME2_PIPE0_PRIORITY :TCP_ME2_PIPE0_PRIORITY; // 0x309F - CP_ME2_PIPE1_PRIORITY :TCP_ME2_PIPE1_PRIORITY; // 0x30A0 - CP_ME2_PIPE2_PRIORITY :TCP_ME2_PIPE2_PRIORITY; // 0x30A1 - CP_ME2_PIPE3_PRIORITY :TCP_ME2_PIPE3_PRIORITY; // 0x30A2 - CP_CE_PRGRM_CNTR_START :TCP_CE_PRGRM_CNTR_START; // 0x30A3 - CP_PFP_PRGRM_CNTR_START :TCP_PFP_PRGRM_CNTR_START; // 0x30A4 - REG_30A5 :DWORD; // 0x30A5 - CP_MEC1_PRGRM_CNTR_START :TCP_MEC1_PRGRM_CNTR_START; // 0x30A6 - CP_MEC2_PRGRM_CNTR_START :TCP_MEC2_PRGRM_CNTR_START; // 0x30A7 - CP_CE_INTR_ROUTINE_START :TCP_CE_INTR_ROUTINE_START; // 0x30A8 - CP_PFP_INTR_ROUTINE_START :TCP_PFP_INTR_ROUTINE_START; // 0x30A9 - REG_30AA :DWORD; // 0x30AA - CP_MEC1_INTR_ROUTINE_START :TCP_MEC1_INTR_ROUTINE_START; // 0x30AB - CP_MEC2_INTR_ROUTINE_START :TCP_MEC2_INTR_ROUTINE_START; // 0x30AC - CP_CONTEXT_CNTL :TCP_CONTEXT_CNTL; // 0x30AD - CP_MAX_CONTEXT :TCP_MAX_CONTEXT; // 0x30AE - CP_IQ_WAIT_TIME1 :TCP_IQ_WAIT_TIME1; // 0x30AF - CP_IQ_WAIT_TIME2 :TCP_IQ_WAIT_TIME2; // 0x30B0 - CP_RB0_BASE_HI :TCP_RB0_BASE_HI; // 0x30B1 - CP_RB1_BASE_HI :TCP_RB1_BASE_HI; // 0x30B2 - CP_VMID_RESET :TCP_VMID_RESET; // 0x30B3 - CPC_INT_CNTL :TCPC_INT_CNTL; // 0x30B4 - CPC_INT_STATUS :TCPC_INT_STATUS; // 0x30B5 - CP_VMID_PREEMPT :TCP_VMID_PREEMPT; // 0x30B6 - CPC_INT_CNTX_ID :TCPC_INT_CNTX_ID; // 0x30B7 - CP_PQ_STATUS :TCP_PQ_STATUS; // 0x30B8 - CP_CPC_IC_BASE_LO :TCP_CPC_IC_BASE_LO; // 0x30B9 - CP_CPC_IC_BASE_HI :TCP_CPC_IC_BASE_HI; // 0x30BA - CP_CPC_IC_BASE_CNTL :TCP_CPC_IC_BASE_CNTL; // 0x30BB - CP_CPC_IC_OP_CNTL :TCP_CPC_IC_OP_CNTL; // 0x30BC - CP_MEC1_F32_INT_DIS :TCP_MEC1_F32_INT_DIS; // 0x30BD - CP_MEC2_F32_INT_DIS :TCP_MEC2_F32_INT_DIS; // 0x30BE - CP_VMID_STATUS :TCP_VMID_STATUS; // 0x30BF - REG_30C0_31BF :array[0..255] of DWORD; // 0x30C0 - SPI_ARB_PRIORITY :TSPI_ARB_PRIORITY; // 0x31C0 - SPI_ARB_CYCLES_0 :TSPI_ARB_CYCLES_0; // 0x31C1 - SPI_ARB_CYCLES_1 :TSPI_ARB_CYCLES_1; // 0x31C2 - SPI_CDBG_SYS_GFX :TSPI_CDBG_SYS_GFX; // 0x31C3 - SPI_CDBG_SYS_HP3D :TSPI_CDBG_SYS_HP3D; // 0x31C4 - SPI_CDBG_SYS_CS0 :TSPI_CDBG_SYS_CS0; // 0x31C5 - SPI_CDBG_SYS_CS1 :TSPI_CDBG_SYS_CS1; // 0x31C6 - SPI_WCL_PIPE_PERCENT_GFX :TSPI_WCL_PIPE_PERCENT_GFX; // 0x31C7 - SPI_WCL_PIPE_PERCENT_HP3D :TSPI_WCL_PIPE_PERCENT_HP3D; // 0x31C8 - SPI_WCL_PIPE_PERCENT_CS0 :TSPI_WCL_PIPE_PERCENT_CS0; // 0x31C9 - SPI_WCL_PIPE_PERCENT_CS1 :TSPI_WCL_PIPE_PERCENT_CS1; // 0x31CA - SPI_WCL_PIPE_PERCENT_CS2 :TSPI_WCL_PIPE_PERCENT_CS2; // 0x31CB - SPI_WCL_PIPE_PERCENT_CS3 :TSPI_WCL_PIPE_PERCENT_CS3; // 0x31CC - SPI_WCL_PIPE_PERCENT_CS4 :TSPI_WCL_PIPE_PERCENT_CS4; // 0x31CD - SPI_WCL_PIPE_PERCENT_CS5 :TSPI_WCL_PIPE_PERCENT_CS5; // 0x31CE - SPI_WCL_PIPE_PERCENT_CS6 :TSPI_WCL_PIPE_PERCENT_CS6; // 0x31CF - SPI_WCL_PIPE_PERCENT_CS7 :TSPI_WCL_PIPE_PERCENT_CS7; // 0x31D0 - SPI_GDBG_WAVE_CNTL :TSPI_GDBG_WAVE_CNTL; // 0x31D1 - SPI_GDBG_TRAP_CONFIG :TSPI_GDBG_TRAP_CONFIG; // 0x31D2 - SPI_GDBG_TRAP_MASK :TSPI_GDBG_TRAP_MASK; // 0x31D3 - SPI_GDBG_TBA_LO :TSPI_GDBG_TBA_LO; // 0x31D4 - SPI_GDBG_TBA_HI :TSPI_GDBG_TBA_HI; // 0x31D5 - SPI_GDBG_TMA_LO :TSPI_GDBG_TMA_LO; // 0x31D6 - SPI_GDBG_TMA_HI :TSPI_GDBG_TMA_HI; // 0x31D7 - SPI_GDBG_TRAP_DATA0 :TSPI_GDBG_TRAP_DATA0; // 0x31D8 - SPI_GDBG_TRAP_DATA1 :TSPI_GDBG_TRAP_DATA1; // 0x31D9 - SPI_RESET_DEBUG :TSPI_RESET_DEBUG; // 0x31DA - SPI_COMPUTE_QUEUE_RESET :TSPI_COMPUTE_QUEUE_RESET; // 0x31DB - SPI_RESOURCE_RESERVE_CU_0 :TSPI_RESOURCE_RESERVE_CU_0; // 0x31DC - SPI_RESOURCE_RESERVE_CU_1 :TSPI_RESOURCE_RESERVE_CU_1; // 0x31DD - SPI_RESOURCE_RESERVE_CU_2 :TSPI_RESOURCE_RESERVE_CU_2; // 0x31DE - SPI_RESOURCE_RESERVE_CU_3 :TSPI_RESOURCE_RESERVE_CU_3; // 0x31DF - SPI_RESOURCE_RESERVE_CU_4 :TSPI_RESOURCE_RESERVE_CU_4; // 0x31E0 - SPI_RESOURCE_RESERVE_CU_5 :TSPI_RESOURCE_RESERVE_CU_5; // 0x31E1 - SPI_RESOURCE_RESERVE_CU_6 :TSPI_RESOURCE_RESERVE_CU_6; // 0x31E2 - SPI_RESOURCE_RESERVE_CU_7 :TSPI_RESOURCE_RESERVE_CU_7; // 0x31E3 - SPI_RESOURCE_RESERVE_CU_8 :TSPI_RESOURCE_RESERVE_CU_8; // 0x31E4 - SPI_RESOURCE_RESERVE_CU_9 :TSPI_RESOURCE_RESERVE_CU_9; // 0x31E5 - SPI_RESOURCE_RESERVE_EN_CU_0 :TSPI_RESOURCE_RESERVE_EN_CU_0; // 0x31E6 - SPI_RESOURCE_RESERVE_EN_CU_1 :TSPI_RESOURCE_RESERVE_EN_CU_1; // 0x31E7 - SPI_RESOURCE_RESERVE_EN_CU_2 :TSPI_RESOURCE_RESERVE_EN_CU_2; // 0x31E8 - SPI_RESOURCE_RESERVE_EN_CU_3 :TSPI_RESOURCE_RESERVE_EN_CU_3; // 0x31E9 - SPI_RESOURCE_RESERVE_EN_CU_4 :TSPI_RESOURCE_RESERVE_EN_CU_4; // 0x31EA - SPI_RESOURCE_RESERVE_EN_CU_5 :TSPI_RESOURCE_RESERVE_EN_CU_5; // 0x31EB - SPI_RESOURCE_RESERVE_EN_CU_6 :TSPI_RESOURCE_RESERVE_EN_CU_6; // 0x31EC - SPI_RESOURCE_RESERVE_EN_CU_7 :TSPI_RESOURCE_RESERVE_EN_CU_7; // 0x31ED - SPI_RESOURCE_RESERVE_EN_CU_8 :TSPI_RESOURCE_RESERVE_EN_CU_8; // 0x31EE - SPI_RESOURCE_RESERVE_EN_CU_9 :TSPI_RESOURCE_RESERVE_EN_CU_9; // 0x31EF - SPI_RESOURCE_RESERVE_CU_10 :TSPI_RESOURCE_RESERVE_CU_10; // 0x31F0 - SPI_RESOURCE_RESERVE_CU_11 :TSPI_RESOURCE_RESERVE_CU_11; // 0x31F1 - SPI_RESOURCE_RESERVE_EN_CU_10 :TSPI_RESOURCE_RESERVE_EN_CU_10; // 0x31F2 - SPI_RESOURCE_RESERVE_EN_CU_11 :TSPI_RESOURCE_RESERVE_EN_CU_11; // 0x31F3 - SPI_RESOURCE_RESERVE_CU_12 :TSPI_RESOURCE_RESERVE_CU_12; // 0x31F4 - SPI_RESOURCE_RESERVE_CU_13 :TSPI_RESOURCE_RESERVE_CU_13; // 0x31F5 - SPI_RESOURCE_RESERVE_CU_14 :TSPI_RESOURCE_RESERVE_CU_14; // 0x31F6 - SPI_RESOURCE_RESERVE_CU_15 :TSPI_RESOURCE_RESERVE_CU_15; // 0x31F7 - SPI_RESOURCE_RESERVE_EN_CU_12 :TSPI_RESOURCE_RESERVE_EN_CU_12; // 0x31F8 - SPI_RESOURCE_RESERVE_EN_CU_13 :TSPI_RESOURCE_RESERVE_EN_CU_13; // 0x31F9 - SPI_RESOURCE_RESERVE_EN_CU_14 :TSPI_RESOURCE_RESERVE_EN_CU_14; // 0x31FA - SPI_RESOURCE_RESERVE_EN_CU_15 :TSPI_RESOURCE_RESERVE_EN_CU_15; // 0x31FB - SPI_COMPUTE_WF_CTX_SAVE :TSPI_COMPUTE_WF_CTX_SAVE; // 0x31FC - REG_31FD_323F :array[0..66] of DWORD; // 0x31FD - CP_HPD_ROQ_OFFSETS :TCP_HPD_ROQ_OFFSETS; // 0x3240 - CP_HPD_STATUS0 :TCP_HPD_STATUS0; // 0x3241 - REG_3242_3244 :array[0..2] of DWORD; // 0x3242 - CP_MQD_BASE_ADDR :TCP_MQD_BASE_ADDR; // 0x3245 - CP_MQD_BASE_ADDR_HI :TCP_MQD_BASE_ADDR_HI; // 0x3246 - CP_HQD_ACTIVE :TCP_HQD_ACTIVE; // 0x3247 - CP_HQD_VMID :TCP_HQD_VMID; // 0x3248 - CP_HQD_PERSISTENT_STATE :TCP_HQD_PERSISTENT_STATE; // 0x3249 - CP_HQD_PIPE_PRIORITY :TCP_HQD_PIPE_PRIORITY; // 0x324A - CP_HQD_QUEUE_PRIORITY :TCP_HQD_QUEUE_PRIORITY; // 0x324B - CP_HQD_QUANTUM :TCP_HQD_QUANTUM; // 0x324C - CP_HQD_PQ_BASE :TCP_HQD_PQ_BASE; // 0x324D - CP_HQD_PQ_BASE_HI :TCP_HQD_PQ_BASE_HI; // 0x324E - CP_HQD_PQ_RPTR :TCP_HQD_PQ_RPTR; // 0x324F - CP_HQD_PQ_RPTR_REPORT_ADDR :TCP_HQD_PQ_RPTR_REPORT_ADDR; // 0x3250 - CP_HQD_PQ_RPTR_REPORT_ADDR_HI :TCP_HQD_PQ_RPTR_REPORT_ADDR_HI; // 0x3251 - CP_HQD_PQ_WPTR_POLL_ADDR :TCP_HQD_PQ_WPTR_POLL_ADDR; // 0x3252 - CP_HQD_PQ_WPTR_POLL_ADDR_HI :TCP_HQD_PQ_WPTR_POLL_ADDR_HI; // 0x3253 - CP_HQD_PQ_DOORBELL_CONTROL :TCP_HQD_PQ_DOORBELL_CONTROL; // 0x3254 - CP_HQD_PQ_WPTR :TCP_HQD_PQ_WPTR; // 0x3255 - CP_HQD_PQ_CONTROL :TCP_HQD_PQ_CONTROL; // 0x3256 - CP_HQD_IB_BASE_ADDR :TCP_HQD_IB_BASE_ADDR; // 0x3257 - CP_HQD_IB_BASE_ADDR_HI :TCP_HQD_IB_BASE_ADDR_HI; // 0x3258 - CP_HQD_IB_RPTR :TCP_HQD_IB_RPTR; // 0x3259 - CP_HQD_IB_CONTROL :TCP_HQD_IB_CONTROL; // 0x325A - CP_HQD_IQ_TIMER :TCP_HQD_IQ_TIMER; // 0x325B - CP_HQD_IQ_RPTR :TCP_HQD_IQ_RPTR; // 0x325C - CP_HQD_DEQUEUE_REQUEST :TCP_HQD_DEQUEUE_REQUEST; // 0x325D - CP_HQD_OFFLOAD :TCP_HQD_OFFLOAD; // 0x325E - CP_HQD_SEMA_CMD :TCP_HQD_SEMA_CMD; // 0x325F - CP_HQD_MSG_TYPE :TCP_HQD_MSG_TYPE; // 0x3260 - CP_HQD_ATOMIC0_PREOP_LO :TCP_HQD_ATOMIC0_PREOP_LO; // 0x3261 - CP_HQD_ATOMIC0_PREOP_HI :TCP_HQD_ATOMIC0_PREOP_HI; // 0x3262 - CP_HQD_ATOMIC1_PREOP_LO :TCP_HQD_ATOMIC1_PREOP_LO; // 0x3263 - CP_HQD_ATOMIC1_PREOP_HI :TCP_HQD_ATOMIC1_PREOP_HI; // 0x3264 - CP_HQD_HQ_STATUS0 :TCP_HQD_HQ_STATUS0; // 0x3265 - CP_HQD_HQ_CONTROL0 :TCP_HQD_HQ_CONTROL0; // 0x3266 - CP_MQD_CONTROL :TCP_MQD_CONTROL; // 0x3267 - CP_HQD_HQ_STATUS1 :TCP_HQD_HQ_STATUS1; // 0x3268 - CP_HQD_HQ_CONTROL1 :TCP_HQD_HQ_CONTROL1; // 0x3269 - CP_HQD_EOP_BASE_ADDR :TCP_HQD_EOP_BASE_ADDR; // 0x326A - CP_HQD_EOP_BASE_ADDR_HI :TCP_HQD_EOP_BASE_ADDR_HI; // 0x326B - CP_HQD_EOP_CONTROL :TCP_HQD_EOP_CONTROL; // 0x326C - CP_HQD_EOP_RPTR :TCP_HQD_EOP_RPTR; // 0x326D - CP_HQD_EOP_WPTR :TCP_HQD_EOP_WPTR; // 0x326E - CP_HQD_EOP_EVENTS :TCP_HQD_EOP_EVENTS; // 0x326F - CP_HQD_CTX_SAVE_BASE_ADDR_LO :TCP_HQD_CTX_SAVE_BASE_ADDR_LO; // 0x3270 - CP_HQD_CTX_SAVE_BASE_ADDR_HI :TCP_HQD_CTX_SAVE_BASE_ADDR_HI; // 0x3271 - CP_HQD_CTX_SAVE_CONTROL :TCP_HQD_CTX_SAVE_CONTROL; // 0x3272 - CP_HQD_CNTL_STACK_OFFSET :TCP_HQD_CNTL_STACK_OFFSET; // 0x3273 - CP_HQD_CNTL_STACK_SIZE :TCP_HQD_CNTL_STACK_SIZE; // 0x3274 - CP_HQD_WG_STATE_OFFSET :TCP_HQD_WG_STATE_OFFSET; // 0x3275 - CP_HQD_CTX_SAVE_SIZE :TCP_HQD_CTX_SAVE_SIZE; // 0x3276 - CP_HQD_GDS_RESOURCE_STATE :TCP_HQD_GDS_RESOURCE_STATE; // 0x3277 - CP_HQD_ERROR :TCP_HQD_ERROR; // 0x3278 - CP_HQD_EOP_WPTR_MEM :TCP_HQD_EOP_WPTR_MEM; // 0x3279 - CP_HQD_EOP_DONES :TCP_HQD_EOP_DONES; // 0x327A - REG_327B_329F :array[0..36] of DWORD; // 0x327B - TCP_WATCH0_ADDR_H :TTCP_WATCH0_ADDR_H; // 0x32A0 - TCP_WATCH0_ADDR_L :TTCP_WATCH0_ADDR_L; // 0x32A1 - TCP_WATCH0_CNTL :TTCP_WATCH0_CNTL; // 0x32A2 - TCP_WATCH1_ADDR_H :TTCP_WATCH1_ADDR_H; // 0x32A3 - TCP_WATCH1_ADDR_L :TTCP_WATCH1_ADDR_L; // 0x32A4 - TCP_WATCH1_CNTL :TTCP_WATCH1_CNTL; // 0x32A5 - TCP_WATCH2_ADDR_H :TTCP_WATCH2_ADDR_H; // 0x32A6 - TCP_WATCH2_ADDR_L :TTCP_WATCH2_ADDR_L; // 0x32A7 - TCP_WATCH2_CNTL :TTCP_WATCH2_CNTL; // 0x32A8 - TCP_WATCH3_ADDR_H :TTCP_WATCH3_ADDR_H; // 0x32A9 - TCP_WATCH3_ADDR_L :TTCP_WATCH3_ADDR_L; // 0x32AA - TCP_WATCH3_CNTL :TTCP_WATCH3_CNTL; // 0x32AB - REG_32AC_32AF :array[0..3] of DWORD; // 0x32AC - TCP_GATCL1_CNTL :TTCP_GATCL1_CNTL; // 0x32B0 - TCP_ATC_EDC_GATCL1_CNT :TTCP_ATC_EDC_GATCL1_CNT; // 0x32B1 - TCP_GATCL1_DSM_CNTL :TTCP_GATCL1_DSM_CNTL; // 0x32B2 - TCP_DSM_CNTL :TTCP_DSM_CNTL; // 0x32B3 - TCP_CNTL2 :TTCP_CNTL2; // 0x32B4 - REG_32B5_32FF :array[0..74] of DWORD; // 0x32B5 - GDS_VMID0_BASE :TGDS_VMID0_BASE; // 0x3300 - GDS_VMID0_SIZE :TGDS_VMID0_SIZE; // 0x3301 - GDS_VMID1_BASE :TGDS_VMID1_BASE; // 0x3302 - GDS_VMID1_SIZE :TGDS_VMID1_SIZE; // 0x3303 - GDS_VMID2_BASE :TGDS_VMID2_BASE; // 0x3304 - GDS_VMID2_SIZE :TGDS_VMID2_SIZE; // 0x3305 - GDS_VMID3_BASE :TGDS_VMID3_BASE; // 0x3306 - GDS_VMID3_SIZE :TGDS_VMID3_SIZE; // 0x3307 - GDS_VMID4_BASE :TGDS_VMID4_BASE; // 0x3308 - GDS_VMID4_SIZE :TGDS_VMID4_SIZE; // 0x3309 - GDS_VMID5_BASE :TGDS_VMID5_BASE; // 0x330A - GDS_VMID5_SIZE :TGDS_VMID5_SIZE; // 0x330B - GDS_VMID6_BASE :TGDS_VMID6_BASE; // 0x330C - GDS_VMID6_SIZE :TGDS_VMID6_SIZE; // 0x330D - GDS_VMID7_BASE :TGDS_VMID7_BASE; // 0x330E - GDS_VMID7_SIZE :TGDS_VMID7_SIZE; // 0x330F - GDS_VMID8_BASE :TGDS_VMID8_BASE; // 0x3310 - GDS_VMID8_SIZE :TGDS_VMID8_SIZE; // 0x3311 - GDS_VMID9_BASE :TGDS_VMID9_BASE; // 0x3312 - GDS_VMID9_SIZE :TGDS_VMID9_SIZE; // 0x3313 - GDS_VMID10_BASE :TGDS_VMID10_BASE; // 0x3314 - GDS_VMID10_SIZE :TGDS_VMID10_SIZE; // 0x3315 - GDS_VMID11_BASE :TGDS_VMID11_BASE; // 0x3316 - GDS_VMID11_SIZE :TGDS_VMID11_SIZE; // 0x3317 - GDS_VMID12_BASE :TGDS_VMID12_BASE; // 0x3318 - GDS_VMID12_SIZE :TGDS_VMID12_SIZE; // 0x3319 - GDS_VMID13_BASE :TGDS_VMID13_BASE; // 0x331A - GDS_VMID13_SIZE :TGDS_VMID13_SIZE; // 0x331B - GDS_VMID14_BASE :TGDS_VMID14_BASE; // 0x331C - GDS_VMID14_SIZE :TGDS_VMID14_SIZE; // 0x331D - GDS_VMID15_BASE :TGDS_VMID15_BASE; // 0x331E - GDS_VMID15_SIZE :TGDS_VMID15_SIZE; // 0x331F - GDS_GWS_VMID0 :TGDS_GWS_VMID0; // 0x3320 - GDS_GWS_VMID1 :TGDS_GWS_VMID1; // 0x3321 - GDS_GWS_VMID2 :TGDS_GWS_VMID2; // 0x3322 - GDS_GWS_VMID3 :TGDS_GWS_VMID3; // 0x3323 - GDS_GWS_VMID4 :TGDS_GWS_VMID4; // 0x3324 - GDS_GWS_VMID5 :TGDS_GWS_VMID5; // 0x3325 - GDS_GWS_VMID6 :TGDS_GWS_VMID6; // 0x3326 - GDS_GWS_VMID7 :TGDS_GWS_VMID7; // 0x3327 - GDS_GWS_VMID8 :TGDS_GWS_VMID8; // 0x3328 - GDS_GWS_VMID9 :TGDS_GWS_VMID9; // 0x3329 - GDS_GWS_VMID10 :TGDS_GWS_VMID10; // 0x332A - GDS_GWS_VMID11 :TGDS_GWS_VMID11; // 0x332B - GDS_GWS_VMID12 :TGDS_GWS_VMID12; // 0x332C - GDS_GWS_VMID13 :TGDS_GWS_VMID13; // 0x332D - GDS_GWS_VMID14 :TGDS_GWS_VMID14; // 0x332E - GDS_GWS_VMID15 :TGDS_GWS_VMID15; // 0x332F - GDS_OA_VMID0 :TGDS_OA_VMID0; // 0x3330 - GDS_OA_VMID1 :TGDS_OA_VMID1; // 0x3331 - GDS_OA_VMID2 :TGDS_OA_VMID2; // 0x3332 - GDS_OA_VMID3 :TGDS_OA_VMID3; // 0x3333 - GDS_OA_VMID4 :TGDS_OA_VMID4; // 0x3334 - GDS_OA_VMID5 :TGDS_OA_VMID5; // 0x3335 - GDS_OA_VMID6 :TGDS_OA_VMID6; // 0x3336 - GDS_OA_VMID7 :TGDS_OA_VMID7; // 0x3337 - GDS_OA_VMID8 :TGDS_OA_VMID8; // 0x3338 - GDS_OA_VMID9 :TGDS_OA_VMID9; // 0x3339 - GDS_OA_VMID10 :TGDS_OA_VMID10; // 0x333A - GDS_OA_VMID11 :TGDS_OA_VMID11; // 0x333B - GDS_OA_VMID12 :TGDS_OA_VMID12; // 0x333C - GDS_OA_VMID13 :TGDS_OA_VMID13; // 0x333D - GDS_OA_VMID14 :TGDS_OA_VMID14; // 0x333E - GDS_OA_VMID15 :TGDS_OA_VMID15; // 0x333F - REG_3340_3343 :array[0..3] of DWORD; // 0x3340 - GDS_GWS_RESET0 :TGDS_GWS_RESET0; // 0x3344 - GDS_GWS_RESET1 :TGDS_GWS_RESET1; // 0x3345 - GDS_GWS_RESOURCE_RESET :TGDS_GWS_RESOURCE_RESET; // 0x3346 - REG_3347 :DWORD; // 0x3347 - GDS_COMPUTE_MAX_WAVE_ID :TGDS_COMPUTE_MAX_WAVE_ID; // 0x3348 - GDS_OA_RESET_MASK :TGDS_OA_RESET_MASK; // 0x3349 - GDS_OA_RESET :TGDS_OA_RESET; // 0x334A - GDS_ENHANCE :TGDS_ENHANCE; // 0x334B - GDS_OA_CGPG_RESTORE :TGDS_OA_CGPG_RESTORE; // 0x334C - GDS_CS_CTXSW_STATUS :TGDS_CS_CTXSW_STATUS; // 0x334D - GDS_CS_CTXSW_CNT0 :TGDS_CS_CTXSW_CNT0; // 0x334E - GDS_CS_CTXSW_CNT1 :TGDS_CS_CTXSW_CNT1; // 0x334F - GDS_CS_CTXSW_CNT2 :TGDS_CS_CTXSW_CNT2; // 0x3350 - GDS_CS_CTXSW_CNT3 :TGDS_CS_CTXSW_CNT3; // 0x3351 - GDS_GFX_CTXSW_STATUS :TGDS_GFX_CTXSW_STATUS; // 0x3352 - GDS_VS_CTXSW_CNT0 :TGDS_VS_CTXSW_CNT0; // 0x3353 - GDS_VS_CTXSW_CNT1 :TGDS_VS_CTXSW_CNT1; // 0x3354 - GDS_VS_CTXSW_CNT2 :TGDS_VS_CTXSW_CNT2; // 0x3355 - GDS_VS_CTXSW_CNT3 :TGDS_VS_CTXSW_CNT3; // 0x3356 - GDS_PS0_CTXSW_CNT0 :TGDS_PS0_CTXSW_CNT0; // 0x3357 - GDS_PS0_CTXSW_CNT1 :TGDS_PS0_CTXSW_CNT1; // 0x3358 - GDS_PS0_CTXSW_CNT2 :TGDS_PS0_CTXSW_CNT2; // 0x3359 - GDS_PS0_CTXSW_CNT3 :TGDS_PS0_CTXSW_CNT3; // 0x335A - GDS_PS1_CTXSW_CNT0 :TGDS_PS1_CTXSW_CNT0; // 0x335B - GDS_PS1_CTXSW_CNT1 :TGDS_PS1_CTXSW_CNT1; // 0x335C - GDS_PS1_CTXSW_CNT2 :TGDS_PS1_CTXSW_CNT2; // 0x335D - GDS_PS1_CTXSW_CNT3 :TGDS_PS1_CTXSW_CNT3; // 0x335E - GDS_PS2_CTXSW_CNT0 :TGDS_PS2_CTXSW_CNT0; // 0x335F - GDS_PS2_CTXSW_CNT1 :TGDS_PS2_CTXSW_CNT1; // 0x3360 - GDS_PS2_CTXSW_CNT2 :TGDS_PS2_CTXSW_CNT2; // 0x3361 - GDS_PS2_CTXSW_CNT3 :TGDS_PS2_CTXSW_CNT3; // 0x3362 - GDS_PS3_CTXSW_CNT0 :TGDS_PS3_CTXSW_CNT0; // 0x3363 - GDS_PS3_CTXSW_CNT1 :TGDS_PS3_CTXSW_CNT1; // 0x3364 - GDS_PS3_CTXSW_CNT2 :TGDS_PS3_CTXSW_CNT2; // 0x3365 - GDS_PS3_CTXSW_CNT3 :TGDS_PS3_CTXSW_CNT3; // 0x3366 - GDS_PS4_CTXSW_CNT0 :TGDS_PS4_CTXSW_CNT0; // 0x3367 - GDS_PS4_CTXSW_CNT1 :TGDS_PS4_CTXSW_CNT1; // 0x3368 - GDS_PS4_CTXSW_CNT2 :TGDS_PS4_CTXSW_CNT2; // 0x3369 - GDS_PS4_CTXSW_CNT3 :TGDS_PS4_CTXSW_CNT3; // 0x336A - GDS_PS5_CTXSW_CNT0 :TGDS_PS5_CTXSW_CNT0; // 0x336B - GDS_PS5_CTXSW_CNT1 :TGDS_PS5_CTXSW_CNT1; // 0x336C - GDS_PS5_CTXSW_CNT2 :TGDS_PS5_CTXSW_CNT2; // 0x336D - GDS_PS5_CTXSW_CNT3 :TGDS_PS5_CTXSW_CNT3; // 0x336E - GDS_PS6_CTXSW_CNT0 :TGDS_PS6_CTXSW_CNT0; // 0x336F - GDS_PS6_CTXSW_CNT1 :TGDS_PS6_CTXSW_CNT1; // 0x3370 - GDS_PS6_CTXSW_CNT2 :TGDS_PS6_CTXSW_CNT2; // 0x3371 - GDS_PS6_CTXSW_CNT3 :TGDS_PS6_CTXSW_CNT3; // 0x3372 - GDS_PS7_CTXSW_CNT0 :TGDS_PS7_CTXSW_CNT0; // 0x3373 - GDS_PS7_CTXSW_CNT1 :TGDS_PS7_CTXSW_CNT1; // 0x3374 - GDS_PS7_CTXSW_CNT2 :TGDS_PS7_CTXSW_CNT2; // 0x3375 - GDS_PS7_CTXSW_CNT3 :TGDS_PS7_CTXSW_CNT3; // 0x3376 + GRBM_CNTL :TGRBM_CNTL; // 0x2000 + GRBM_SKEW_CNTL :TGRBM_SKEW_CNTL; // 0x2001 + GRBM_STATUS2 :TGRBM_STATUS2; // 0x2002 + GRBM_PWR_CNTL :TGRBM_PWR_CNTL; // 0x2003 + GRBM_STATUS :TGRBM_STATUS; // 0x2004 + GRBM_STATUS_SE0 :TGRBM_STATUS_SE0; // 0x2005 + GRBM_STATUS_SE1 :TGRBM_STATUS_SE1; // 0x2006 + REG_2007 :DWORD; // 0x2007 + GRBM_SOFT_RESET :TGRBM_SOFT_RESET; // 0x2008 + GRBM_DEBUG_CNTL :TGRBM_DEBUG_CNTL; // 0x2009 + GRBM_DEBUG_DATA :TGRBM_DEBUG_DATA; // 0x200A + REG_200B :DWORD; // 0x200B + GRBM_GFX_CLKEN_CNTL :TGRBM_GFX_CLKEN_CNTL; // 0x200C + GRBM_WAIT_IDLE_CLOCKS :TGRBM_WAIT_IDLE_CLOCKS; // 0x200D + GRBM_STATUS_SE2 :TGRBM_STATUS_SE2; // 0x200E + GRBM_STATUS_SE3 :TGRBM_STATUS_SE3; // 0x200F + REG_2010_2013 :array[0..3] of DWORD; // 0x2010 + GRBM_DEBUG :TGRBM_DEBUG; // 0x2014 + GRBM_DEBUG_SNAPSHOT :TGRBM_DEBUG_SNAPSHOT; // 0x2015 + GRBM_READ_ERROR :TGRBM_READ_ERROR; // 0x2016 + GRBM_READ_ERROR2 :TGRBM_READ_ERROR2; // 0x2017 + GRBM_INT_CNTL :TGRBM_INT_CNTL; // 0x2018 + GRBM_TRAP_OP :TGRBM_TRAP_OP; // 0x2019 + GRBM_TRAP_ADDR :TGRBM_TRAP_ADDR; // 0x201A + GRBM_TRAP_ADDR_MSK :TGRBM_TRAP_ADDR_MSK; // 0x201B + GRBM_TRAP_WD :TGRBM_TRAP_WD; // 0x201C + GRBM_TRAP_WD_MSK :TGRBM_TRAP_WD_MSK; // 0x201D + GRBM_DSM_BYPASS :TGRBM_DSM_BYPASS; // 0x201E + GRBM_WRITE_ERROR :TGRBM_WRITE_ERROR; // 0x201F + REG_2020_203B :array[0..27] of DWORD; // 0x2020 + DEBUG_INDEX :TDEBUG_INDEX; // 0x203C + DEBUG_DATA :TDEBUG_DATA; // 0x203D + REG_203E :DWORD; // 0x203E + GRBM_NOWHERE :TGRBM_NOWHERE; // 0x203F + GRBM_SCRATCH_REG0 :TGRBM_SCRATCH_REG0; // 0x2040 + GRBM_SCRATCH_REG1 :TGRBM_SCRATCH_REG1; // 0x2041 + GRBM_SCRATCH_REG2 :TGRBM_SCRATCH_REG2; // 0x2042 + GRBM_SCRATCH_REG3 :TGRBM_SCRATCH_REG3; // 0x2043 + GRBM_SCRATCH_REG4 :TGRBM_SCRATCH_REG4; // 0x2044 + GRBM_SCRATCH_REG5 :TGRBM_SCRATCH_REG5; // 0x2045 + GRBM_SCRATCH_REG6 :TGRBM_SCRATCH_REG6; // 0x2046 + GRBM_SCRATCH_REG7 :TGRBM_SCRATCH_REG7; // 0x2047 + REG_2048_2083 :array[0..59] of DWORD; // 0x2048 + CP_CPC_STATUS :TCP_CPC_STATUS; // 0x2084 + CP_CPC_BUSY_STAT :TCP_CPC_BUSY_STAT; // 0x2085 + CP_CPC_STALLED_STAT1 :TCP_CPC_STALLED_STAT1; // 0x2086 + CP_CPF_STATUS :TCP_CPF_STATUS; // 0x2087 + CP_CPF_BUSY_STAT :TCP_CPF_BUSY_STAT; // 0x2088 + CP_CPF_STALLED_STAT1 :TCP_CPF_STALLED_STAT1; // 0x2089 + REG_208A :DWORD; // 0x208A + CP_CPC_GRBM_FREE_COUNT :TCP_CPC_GRBM_FREE_COUNT; // 0x208B + REG_208C :DWORD; // 0x208C + CP_MEC_CNTL :TCP_MEC_CNTL; // 0x208D + CP_MEC_ME1_HEADER_DUMP :TCP_MEC_ME1_HEADER_DUMP; // 0x208E + CP_MEC_ME2_HEADER_DUMP :TCP_MEC_ME2_HEADER_DUMP; // 0x208F + CP_CPC_SCRATCH_INDEX :TCP_CPC_SCRATCH_INDEX; // 0x2090 + CP_CPC_SCRATCH_DATA :TCP_CPC_SCRATCH_DATA; // 0x2091 + REG_2092_20A6 :array[0..20] of DWORD; // 0x2092 + CP_CPC_HALT_HYST_COUNT :TCP_CPC_HALT_HYST_COUNT; // 0x20A7 + REG_20A8_20AC :array[0..4] of DWORD; // 0x20A8 + CP_PRT_LOD_STATS_CNTL0 :TCP_PRT_LOD_STATS_CNTL0; // 0x20AD + CP_PRT_LOD_STATS_CNTL1 :TCP_PRT_LOD_STATS_CNTL1; // 0x20AE + CP_PRT_LOD_STATS_CNTL2 :TCP_PRT_LOD_STATS_CNTL2; // 0x20AF + REG_20B0_20BF :array[0..15] of DWORD; // 0x20B0 + CP_CE_COMPARE_COUNT :TCP_CE_COMPARE_COUNT; // 0x20C0 + CP_CE_DE_COUNT :TCP_CE_DE_COUNT; // 0x20C1 + CP_DE_CE_COUNT :TCP_DE_CE_COUNT; // 0x20C2 + CP_DE_LAST_INVAL_COUNT :TCP_DE_LAST_INVAL_COUNT; // 0x20C3 + CP_DE_DE_COUNT :TCP_DE_DE_COUNT; // 0x20C4 + REG_20C5_219B :array[0..214] of DWORD; // 0x20C5 + CP_STALLED_STAT3 :TCP_STALLED_STAT3; // 0x219C + CP_STALLED_STAT1 :TCP_STALLED_STAT1; // 0x219D + CP_STALLED_STAT2 :TCP_STALLED_STAT2; // 0x219E + CP_BUSY_STAT :TCP_BUSY_STAT; // 0x219F + CP_STAT :TCP_STAT; // 0x21A0 + CP_ME_HEADER_DUMP :TCP_ME_HEADER_DUMP; // 0x21A1 + CP_PFP_HEADER_DUMP :TCP_PFP_HEADER_DUMP; // 0x21A2 + CP_GRBM_FREE_COUNT :TCP_GRBM_FREE_COUNT; // 0x21A3 + CP_CE_HEADER_DUMP :TCP_CE_HEADER_DUMP; // 0x21A4 + REG_21A5_21B3 :array[0..14] of DWORD; // 0x21A5 + CP_CSF_STAT :TCP_CSF_STAT; // 0x21B4 + CP_CSF_CNTL :TCP_CSF_CNTL; // 0x21B5 + CP_ME_CNTL :TCP_ME_CNTL; // 0x21B6 + REG_21B7 :DWORD; // 0x21B7 + CP_CNTX_STAT :TCP_CNTX_STAT; // 0x21B8 + CP_ME_PREEMPTION :TCP_ME_PREEMPTION; // 0x21B9 + REG_21BA_21BB :array[0..1] of DWORD; // 0x21BA + CP_ROQ_THRESHOLDS :TCP_ROQ_THRESHOLDS; // 0x21BC + CP_MEQ_STQ_THRESHOLD :TCP_MEQ_STQ_THRESHOLD; // 0x21BD + CP_RB2_RPTR :TCP_RB2_RPTR; // 0x21BE + CP_RB1_RPTR :TCP_RB1_RPTR; // 0x21BF + CP_RB0_RPTR :TCP_RB0_RPTR; // 0x21C0 + CP_RB_WPTR_DELAY :TCP_RB_WPTR_DELAY; // 0x21C1 + CP_RB_WPTR_POLL_CNTL :TCP_RB_WPTR_POLL_CNTL; // 0x21C2 + REG_21C3_21D4 :array[0..17] of DWORD; // 0x21C3 + CP_ROQ1_THRESHOLDS :TCP_ROQ1_THRESHOLDS; // 0x21D5 + CP_ROQ2_THRESHOLDS :TCP_ROQ2_THRESHOLDS; // 0x21D6 + CP_STQ_THRESHOLDS :TCP_STQ_THRESHOLDS; // 0x21D7 + CP_QUEUE_THRESHOLDS :TCP_QUEUE_THRESHOLDS; // 0x21D8 + CP_MEQ_THRESHOLDS :TCP_MEQ_THRESHOLDS; // 0x21D9 + CP_ROQ_AVAIL :TCP_ROQ_AVAIL; // 0x21DA + CP_STQ_AVAIL :TCP_STQ_AVAIL; // 0x21DB + CP_ROQ2_AVAIL :TCP_ROQ2_AVAIL; // 0x21DC + CP_MEQ_AVAIL :TCP_MEQ_AVAIL; // 0x21DD + CP_CMD_INDEX :TCP_CMD_INDEX; // 0x21DE + CP_CMD_DATA :TCP_CMD_DATA; // 0x21DF + CP_ROQ_RB_STAT :TCP_ROQ_RB_STAT; // 0x21E0 + CP_ROQ_IB1_STAT :TCP_ROQ_IB1_STAT; // 0x21E1 + CP_ROQ_IB2_STAT :TCP_ROQ_IB2_STAT; // 0x21E2 + CP_STQ_STAT :TCP_STQ_STAT; // 0x21E3 + CP_STQ_WR_STAT :TCP_STQ_WR_STAT; // 0x21E4 + CP_MEQ_STAT :TCP_MEQ_STAT; // 0x21E5 + CP_CEQ1_AVAIL :TCP_CEQ1_AVAIL; // 0x21E6 + CP_CEQ2_AVAIL :TCP_CEQ2_AVAIL; // 0x21E7 + CP_CE_ROQ_RB_STAT :TCP_CE_ROQ_RB_STAT; // 0x21E8 + CP_CE_ROQ_IB1_STAT :TCP_CE_ROQ_IB1_STAT; // 0x21E9 + CP_CE_ROQ_IB2_STAT :TCP_CE_ROQ_IB2_STAT; // 0x21EA + REG_21EB_21F6 :array[0..11] of DWORD; // 0x21EB + CP_INT_STAT_DEBUG :TCP_INT_STAT_DEBUG; // 0x21F7 + REG_21F8_21FB :array[0..3] of DWORD; // 0x21F8 + CP_PERFCOUNTER_SELECT :TCP_PERFCOUNTER_SELECT; // 0x21FC + CP_PERFCOUNTER_LO :TCP_PERFCOUNTER_LO; // 0x21FD + CP_PERFCOUNTER_HI :TCP_PERFCOUNTER_HI; // 0x21FE + REG_21FF_222B :array[0..44] of DWORD; // 0x21FF + VGT_VTX_VECT_EJECT_REG :TVGT_VTX_VECT_EJECT_REG; // 0x222C + VGT_DMA_DATA_FIFO_DEPTH :TVGT_DMA_DATA_FIFO_DEPTH; // 0x222D + VGT_DMA_REQ_FIFO_DEPTH :TVGT_DMA_REQ_FIFO_DEPTH; // 0x222E + VGT_DRAW_INIT_FIFO_DEPTH :TVGT_DRAW_INIT_FIFO_DEPTH; // 0x222F + VGT_LAST_COPY_STATE :TVGT_LAST_COPY_STATE; // 0x2230 + VGT_CACHE_INVALIDATION :TVGT_CACHE_INVALIDATION; // 0x2231 + VGT_RESET_DEBUG :TVGT_RESET_DEBUG; // 0x2232 + VGT_STRMOUT_DELAY :TVGT_STRMOUT_DELAY; // 0x2233 + VGT_FIFO_DEPTHS :TVGT_FIFO_DEPTHS; // 0x2234 + VGT_GS_VERTEX_REUSE :TVGT_GS_VERTEX_REUSE; // 0x2235 + VGT_MC_LAT_CNTL :TVGT_MC_LAT_CNTL; // 0x2236 + IA_CNTL_STATUS :TIA_CNTL_STATUS; // 0x2237 + VGT_DEBUG_CNTL :TVGT_DEBUG_CNTL; // 0x2238 + VGT_DEBUG_DATA :TVGT_DEBUG_DATA; // 0x2239 + IA_DEBUG_CNTL :TIA_DEBUG_CNTL; // 0x223A + IA_DEBUG_DATA :TIA_DEBUG_DATA; // 0x223B + VGT_CNTL_STATUS :TVGT_CNTL_STATUS; // 0x223C + WD_DEBUG_CNTL :TWD_DEBUG_CNTL; // 0x223D + WD_DEBUG_DATA :TWD_DEBUG_DATA; // 0x223E + WD_CNTL_STATUS :TWD_CNTL_STATUS; // 0x223F + CC_GC_PRIM_CONFIG :TCC_GC_PRIM_CONFIG; // 0x2240 + GC_USER_PRIM_CONFIG :TGC_USER_PRIM_CONFIG; // 0x2241 + WD_QOS :TWD_QOS; // 0x2242 + REG_2243_225E :array[0..27] of DWORD; // 0x2243 + CGTT_VGT_CLK_CTRL :TCGTT_VGT_CLK_CTRL; // 0x225F + REG_2260 :DWORD; // 0x2260 + CGTT_IA_CLK_CTRL :TCGTT_IA_CLK_CTRL; // 0x2261 + REG_2262 :DWORD; // 0x2262 + VGT_SYS_CONFIG :TVGT_SYS_CONFIG; // 0x2263 + REG_2264_2267 :array[0..3] of DWORD; // 0x2264 + VGT_VS_MAX_WAVE_ID :TVGT_VS_MAX_WAVE_ID; // 0x2268 + REG_2269_226C :array[0..3] of DWORD; // 0x2269 + GFX_PIPE_CONTROL :TGFX_PIPE_CONTROL; // 0x226D + REG_226E :DWORD; // 0x226E + CC_GC_SHADER_ARRAY_CONFIG :TCC_GC_SHADER_ARRAY_CONFIG; // 0x226F + GC_USER_SHADER_ARRAY_CONFIG :TGC_USER_SHADER_ARRAY_CONFIG; // 0x2270 + VGT_DMA_PRIMITIVE_TYPE :TVGT_DMA_PRIMITIVE_TYPE; // 0x2271 + VGT_DMA_CONTROL :TVGT_DMA_CONTROL; // 0x2272 + VGT_DMA_LS_HS_CONFIG :TVGT_DMA_LS_HS_CONFIG; // 0x2273 + REG_2274_227F :array[0..11] of DWORD; // 0x2274 + PA_SU_DEBUG_CNTL :TPA_SU_DEBUG_CNTL; // 0x2280 + PA_SU_DEBUG_DATA :TPA_SU_DEBUG_DATA; // 0x2281 + REG_2282_2283 :array[0..1] of DWORD; // 0x2282 + PA_CL_CNTL_STATUS :TPA_CL_CNTL_STATUS; // 0x2284 + PA_CL_ENHANCE :TPA_CL_ENHANCE; // 0x2285 + PA_CL_RESET_DEBUG :TPA_CL_RESET_DEBUG; // 0x2286 + REG_2287_2293 :array[0..12] of DWORD; // 0x2287 + PA_SU_CNTL_STATUS :TPA_SU_CNTL_STATUS; // 0x2294 + PA_SC_FIFO_DEPTH_CNTL :TPA_SC_FIFO_DEPTH_CNTL; // 0x2295 + REG_2296_22BF :array[0..41] of DWORD; // 0x2296 + PA_SC_P3D_TRAP_SCREEN_HV_LOCK :TPA_SC_P3D_TRAP_SCREEN_HV_LOCK; // 0x22C0 + PA_SC_HP3D_TRAP_SCREEN_HV_LOCK :TPA_SC_HP3D_TRAP_SCREEN_HV_LOCK; // 0x22C1 + PA_SC_TRAP_SCREEN_HV_LOCK :TPA_SC_TRAP_SCREEN_HV_LOCK; // 0x22C2 + REG_22C3_22C8 :array[0..5] of DWORD; // 0x22C3 + PA_SC_FORCE_EOV_MAX_CNTS :TPA_SC_FORCE_EOV_MAX_CNTS; // 0x22C9 + CGTT_SC_CLK_CTRL :TCGTT_SC_CLK_CTRL; // 0x22CA + REG_22CB_22F2 :array[0..39] of DWORD; // 0x22CB + PA_SC_FIFO_SIZE :TPA_SC_FIFO_SIZE; // 0x22F3 + REG_22F4 :DWORD; // 0x22F4 + PA_SC_IF_FIFO_SIZE :TPA_SC_IF_FIFO_SIZE; // 0x22F5 + PA_SC_DEBUG_CNTL :TPA_SC_DEBUG_CNTL; // 0x22F6 + PA_SC_DEBUG_DATA :TPA_SC_DEBUG_DATA; // 0x22F7 + REG_22F8_22FB :array[0..3] of DWORD; // 0x22F8 + PA_SC_ENHANCE :TPA_SC_ENHANCE; // 0x22FC + REG_22FD_22FF :array[0..2] of DWORD; // 0x22FD + SQ_CONFIG :TSQ_CONFIG; // 0x2300 + SQC_CONFIG :TSQC_CONFIG; // 0x2301 + REG_2302 :DWORD; // 0x2302 + SQ_RANDOM_WAVE_PRI :TSQ_RANDOM_WAVE_PRI; // 0x2303 + SQ_REG_CREDITS :TSQ_REG_CREDITS; // 0x2304 + SQ_FIFO_SIZES :TSQ_FIFO_SIZES; // 0x2305 + SQ_DSM_CNTL :TSQ_DSM_CNTL; // 0x2306 + CC_SQC_BANK_DISABLE :TCC_SQC_BANK_DISABLE; // 0x2307 + USER_SQC_BANK_DISABLE :TUSER_SQC_BANK_DISABLE; // 0x2308 + SQ_DEBUG_STS_GLOBAL :TSQ_DEBUG_STS_GLOBAL; // 0x2309 + SH_MEM_BASES :TSH_MEM_BASES; // 0x230A + SH_MEM_APE1_BASE :TSH_MEM_APE1_BASE; // 0x230B + SH_MEM_APE1_LIMIT :TSH_MEM_APE1_LIMIT; // 0x230C + SH_MEM_CONFIG :TSH_MEM_CONFIG; // 0x230D + REG_230E :DWORD; // 0x230E + SQC_DSM_CNTL :TSQC_DSM_CNTL; // 0x230F + SQ_DEBUG_STS_GLOBAL2 :TSQ_DEBUG_STS_GLOBAL2; // 0x2310 + SQ_DEBUG_STS_GLOBAL3 :TSQ_DEBUG_STS_GLOBAL3; // 0x2311 + CC_GC_SHADER_RATE_CONFIG :TCC_GC_SHADER_RATE_CONFIG; // 0x2312 + GC_USER_SHADER_RATE_CONFIG :TGC_USER_SHADER_RATE_CONFIG; // 0x2313 + SQ_INTERRUPT_AUTO_MASK :TSQ_INTERRUPT_AUTO_MASK; // 0x2314 + SQ_INTERRUPT_MSG_CTRL :TSQ_INTERRUPT_MSG_CTRL; // 0x2315 + REG_2316_235F :array[0..73] of DWORD; // 0x2316 + SQ_ALU_CLK_CTRL :TSQ_ALU_CLK_CTRL; // 0x2360 + SQ_TEX_CLK_CTRL :TSQ_TEX_CLK_CTRL; // 0x2361 + CGTT_SQ_CLK_CTRL :TCGTT_SQ_CLK_CTRL; // 0x2362 + CGTT_SQG_CLK_CTRL :TCGTT_SQG_CLK_CTRL; // 0x2363 + REG_2364_2373 :array[0..15] of DWORD; // 0x2364 + SQ_REG_TIMESTAMP :TSQ_REG_TIMESTAMP; // 0x2374 + SQ_CMD_TIMESTAMP :TSQ_CMD_TIMESTAMP; // 0x2375 + REG_2376_2377 :array[0..1] of DWORD; // 0x2376 + SQ_IND_INDEX :TSQ_IND_INDEX; // 0x2378 + SQ_IND_DATA :TSQ_IND_DATA; // 0x2379 + REG_237A :DWORD; // 0x237A + SQ_CMD :TSQ_CMD; // 0x237B + SQ_TIME_HI :TSQ_TIME_HI; // 0x237C + SQ_TIME_LO :TSQ_TIME_LO; // 0x237D + REG_237E :DWORD; // 0x237E + SQ_DS_0 :TSQ_DS_0; // 0x237F + REG_2380_238F :array[0..15] of DWORD; // 0x2380 + SQ_THREAD_TRACE_CNTR :TSQ_THREAD_TRACE_CNTR; // 0x2390 + REG_2391_2395 :array[0..4] of DWORD; // 0x2391 + SQ_POWER_THROTTLE :TSQ_POWER_THROTTLE; // 0x2396 + SQ_POWER_THROTTLE2 :TSQ_POWER_THROTTLE2; // 0x2397 + SQ_LB_CTR_CTRL :TSQ_LB_CTR_CTRL; // 0x2398 + SQ_LB_DATA_ALU_CYCLES :TSQ_LB_DATA_ALU_CYCLES; // 0x2399 + SQ_LB_DATA_TEX_CYCLES :TSQ_LB_DATA_TEX_CYCLES; // 0x239A + SQ_LB_DATA_ALU_STALLS :TSQ_LB_DATA_ALU_STALLS; // 0x239B + SQ_LB_DATA_TEX_STALLS :TSQ_LB_DATA_TEX_STALLS; // 0x239C + REG_239D_239F :array[0..2] of DWORD; // 0x239D + SQC_EDC_CNT :TSQC_EDC_CNT; // 0x23A0 + SQ_EDC_SEC_CNT :TSQ_EDC_SEC_CNT; // 0x23A1 + SQ_EDC_DED_CNT :TSQ_EDC_DED_CNT; // 0x23A2 + SQ_EDC_INFO :TSQ_EDC_INFO; // 0x23A3 + REG_23A4_23AF :array[0..11] of DWORD; // 0x23A4 + SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 :TSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2; // 0x23B0 + SQ_WREXEC_EXEC_HI :TSQ_WREXEC_EXEC_HI; // 0x23B1 + SQC_GATCL1_CNTL :TSQC_GATCL1_CNTL; // 0x23B2 + SQC_ATC_EDC_GATCL1_CNT :TSQC_ATC_EDC_GATCL1_CNT; // 0x23B3 + REG_23B4_23BF :array[0..11] of DWORD; // 0x23B4 + SQ_BUF_RSRC_WORD0 :TSQ_BUF_RSRC_WORD0; // 0x23C0 + SQ_BUF_RSRC_WORD1 :TSQ_BUF_RSRC_WORD1; // 0x23C1 + SQ_BUF_RSRC_WORD2 :TSQ_BUF_RSRC_WORD2; // 0x23C2 + SQ_BUF_RSRC_WORD3 :TSQ_BUF_RSRC_WORD3; // 0x23C3 + SQ_IMG_RSRC_WORD0 :TSQ_IMG_RSRC_WORD0; // 0x23C4 + SQ_IMG_RSRC_WORD1 :TSQ_IMG_RSRC_WORD1; // 0x23C5 + SQ_IMG_RSRC_WORD2 :TSQ_IMG_RSRC_WORD2; // 0x23C6 + SQ_IMG_RSRC_WORD3 :TSQ_IMG_RSRC_WORD3; // 0x23C7 + SQ_IMG_RSRC_WORD4 :TSQ_IMG_RSRC_WORD4; // 0x23C8 + SQ_IMG_RSRC_WORD5 :TSQ_IMG_RSRC_WORD5; // 0x23C9 + SQ_IMG_RSRC_WORD6 :TSQ_IMG_RSRC_WORD6; // 0x23CA + SQ_IMG_RSRC_WORD7 :TSQ_IMG_RSRC_WORD7; // 0x23CB + SQ_IMG_SAMP_WORD0 :TSQ_IMG_SAMP_WORD0; // 0x23CC + SQ_IMG_SAMP_WORD1 :TSQ_IMG_SAMP_WORD1; // 0x23CD + SQ_IMG_SAMP_WORD2 :TSQ_IMG_SAMP_WORD2; // 0x23CE + SQ_IMG_SAMP_WORD3 :TSQ_IMG_SAMP_WORD3; // 0x23CF + SQ_FLAT_SCRATCH_WORD0 :TSQ_FLAT_SCRATCH_WORD0; // 0x23D0 + SQ_FLAT_SCRATCH_WORD1 :TSQ_FLAT_SCRATCH_WORD1; // 0x23D1 + SQ_M0_GPR_IDX_WORD :TSQ_M0_GPR_IDX_WORD; // 0x23D2 + REG_23D3_240B :array[0..56] of DWORD; // 0x23D3 + CGTT_SX_CLK_CTRL0 :TCGTT_SX_CLK_CTRL0; // 0x240C + CGTT_SX_CLK_CTRL1 :TCGTT_SX_CLK_CTRL1; // 0x240D + CGTT_SX_CLK_CTRL2 :TCGTT_SX_CLK_CTRL2; // 0x240E + CGTT_SX_CLK_CTRL3 :TCGTT_SX_CLK_CTRL3; // 0x240F + CGTT_SX_CLK_CTRL4 :TCGTT_SX_CLK_CTRL4; // 0x2410 + REG_2411_2413 :array[0..2] of DWORD; // 0x2411 + SX_DEBUG_BUSY :TSX_DEBUG_BUSY; // 0x2414 + SX_DEBUG_BUSY_2 :TSX_DEBUG_BUSY_2; // 0x2415 + SX_DEBUG_BUSY_3 :TSX_DEBUG_BUSY_3; // 0x2416 + SX_DEBUG_BUSY_4 :TSX_DEBUG_BUSY_4; // 0x2417 + SX_DEBUG_1 :TSX_DEBUG_1; // 0x2418 + REG_2419_2439 :array[0..32] of DWORD; // 0x2419 + SPI_PS_MAX_WAVE_ID :TSPI_PS_MAX_WAVE_ID; // 0x243A + SPI_START_PHASE :TSPI_START_PHASE; // 0x243B + SPI_GFX_CNTL :TSPI_GFX_CNTL; // 0x243C + REG_243D_243F :array[0..2] of DWORD; // 0x243D + SPI_CONFIG_CNTL :TSPI_CONFIG_CNTL; // 0x2440 + SPI_DEBUG_CNTL :TSPI_DEBUG_CNTL; // 0x2441 + SPI_DEBUG_READ :TSPI_DEBUG_READ; // 0x2442 + SPI_DSM_CNTL :TSPI_DSM_CNTL; // 0x2443 + SPI_EDC_CNT :TSPI_EDC_CNT; // 0x2444 + REG_2445_244E :array[0..9] of DWORD; // 0x2445 + SPI_CONFIG_CNTL_1 :TSPI_CONFIG_CNTL_1; // 0x244F + SPI_DEBUG_BUSY :TSPI_DEBUG_BUSY; // 0x2450 + SPI_CONFIG_CNTL_2 :TSPI_CONFIG_CNTL_2; // 0x2451 + CGTS_TCC_DISABLE :TCGTS_TCC_DISABLE; // 0x2452 + CGTS_USER_TCC_DISABLE :TCGTS_USER_TCC_DISABLE; // 0x2453 + CGTS_SM_CTRL_REG :TCGTS_SM_CTRL_REG; // 0x2454 + CGTS_RD_CTRL_REG :TCGTS_RD_CTRL_REG; // 0x2455 + CGTS_RD_REG :TCGTS_RD_REG; // 0x2456 + REG_2457_24A7 :array[0..80] of DWORD; // 0x2457 + CGTT_PC_CLK_CTRL :TCGTT_PC_CLK_CTRL; // 0x24A8 + CGTT_BCI_CLK_CTRL :TCGTT_BCI_CLK_CTRL; // 0x24A9 + SPI_WF_LIFETIME_CNTL :TSPI_WF_LIFETIME_CNTL; // 0x24AA + SPI_WF_LIFETIME_LIMIT_0 :TSPI_WF_LIFETIME_LIMIT_0; // 0x24AB + SPI_WF_LIFETIME_LIMIT_1 :TSPI_WF_LIFETIME_LIMIT_1; // 0x24AC + SPI_WF_LIFETIME_LIMIT_2 :TSPI_WF_LIFETIME_LIMIT_2; // 0x24AD + SPI_WF_LIFETIME_LIMIT_3 :TSPI_WF_LIFETIME_LIMIT_3; // 0x24AE + SPI_WF_LIFETIME_LIMIT_4 :TSPI_WF_LIFETIME_LIMIT_4; // 0x24AF + SPI_WF_LIFETIME_LIMIT_5 :TSPI_WF_LIFETIME_LIMIT_5; // 0x24B0 + SPI_WF_LIFETIME_LIMIT_6 :TSPI_WF_LIFETIME_LIMIT_6; // 0x24B1 + SPI_WF_LIFETIME_LIMIT_7 :TSPI_WF_LIFETIME_LIMIT_7; // 0x24B2 + SPI_WF_LIFETIME_LIMIT_8 :TSPI_WF_LIFETIME_LIMIT_8; // 0x24B3 + SPI_WF_LIFETIME_LIMIT_9 :TSPI_WF_LIFETIME_LIMIT_9; // 0x24B4 + SPI_WF_LIFETIME_STATUS_0 :TSPI_WF_LIFETIME_STATUS_0; // 0x24B5 + SPI_WF_LIFETIME_STATUS_1 :TSPI_WF_LIFETIME_STATUS_1; // 0x24B6 + SPI_WF_LIFETIME_STATUS_2 :TSPI_WF_LIFETIME_STATUS_2; // 0x24B7 + SPI_WF_LIFETIME_STATUS_3 :TSPI_WF_LIFETIME_STATUS_3; // 0x24B8 + SPI_WF_LIFETIME_STATUS_4 :TSPI_WF_LIFETIME_STATUS_4; // 0x24B9 + SPI_WF_LIFETIME_STATUS_5 :TSPI_WF_LIFETIME_STATUS_5; // 0x24BA + SPI_WF_LIFETIME_STATUS_6 :TSPI_WF_LIFETIME_STATUS_6; // 0x24BB + SPI_WF_LIFETIME_STATUS_7 :TSPI_WF_LIFETIME_STATUS_7; // 0x24BC + SPI_WF_LIFETIME_STATUS_8 :TSPI_WF_LIFETIME_STATUS_8; // 0x24BD + SPI_WF_LIFETIME_STATUS_9 :TSPI_WF_LIFETIME_STATUS_9; // 0x24BE + SPI_WF_LIFETIME_STATUS_10 :TSPI_WF_LIFETIME_STATUS_10; // 0x24BF + SPI_WF_LIFETIME_STATUS_11 :TSPI_WF_LIFETIME_STATUS_11; // 0x24C0 + SPI_WF_LIFETIME_STATUS_12 :TSPI_WF_LIFETIME_STATUS_12; // 0x24C1 + SPI_WF_LIFETIME_STATUS_13 :TSPI_WF_LIFETIME_STATUS_13; // 0x24C2 + SPI_WF_LIFETIME_STATUS_14 :TSPI_WF_LIFETIME_STATUS_14; // 0x24C3 + SPI_WF_LIFETIME_STATUS_15 :TSPI_WF_LIFETIME_STATUS_15; // 0x24C4 + SPI_WF_LIFETIME_STATUS_16 :TSPI_WF_LIFETIME_STATUS_16; // 0x24C5 + SPI_WF_LIFETIME_STATUS_17 :TSPI_WF_LIFETIME_STATUS_17; // 0x24C6 + SPI_WF_LIFETIME_STATUS_18 :TSPI_WF_LIFETIME_STATUS_18; // 0x24C7 + SPI_WF_LIFETIME_STATUS_19 :TSPI_WF_LIFETIME_STATUS_19; // 0x24C8 + SPI_WF_LIFETIME_STATUS_20 :TSPI_WF_LIFETIME_STATUS_20; // 0x24C9 + SPI_WF_LIFETIME_DEBUG :TSPI_WF_LIFETIME_DEBUG; // 0x24CA + REG_24CB_24D2 :array[0..7] of DWORD; // 0x24CB + SPI_SLAVE_DEBUG_BUSY :TSPI_SLAVE_DEBUG_BUSY; // 0x24D3 + SPI_LB_CTR_CTRL :TSPI_LB_CTR_CTRL; // 0x24D4 + SPI_LB_CU_MASK :TSPI_LB_CU_MASK; // 0x24D5 + SPI_LB_DATA_REG :TSPI_LB_DATA_REG; // 0x24D6 + SPI_PG_ENABLE_STATIC_CU_MASK :TSPI_PG_ENABLE_STATIC_CU_MASK; // 0x24D7 + SPI_GDS_CREDITS :TSPI_GDS_CREDITS; // 0x24D8 + SPI_SX_EXPORT_BUFFER_SIZES :TSPI_SX_EXPORT_BUFFER_SIZES; // 0x24D9 + SPI_SX_SCOREBOARD_BUFFER_SIZES :TSPI_SX_SCOREBOARD_BUFFER_SIZES; // 0x24DA + SPI_CSQ_WF_ACTIVE_STATUS :TSPI_CSQ_WF_ACTIVE_STATUS; // 0x24DB + SPI_CSQ_WF_ACTIVE_COUNT_0 :TSPI_CSQ_WF_ACTIVE_COUNT_0; // 0x24DC + SPI_CSQ_WF_ACTIVE_COUNT_1 :TSPI_CSQ_WF_ACTIVE_COUNT_1; // 0x24DD + SPI_CSQ_WF_ACTIVE_COUNT_2 :TSPI_CSQ_WF_ACTIVE_COUNT_2; // 0x24DE + SPI_CSQ_WF_ACTIVE_COUNT_3 :TSPI_CSQ_WF_ACTIVE_COUNT_3; // 0x24DF + SPI_CSQ_WF_ACTIVE_COUNT_4 :TSPI_CSQ_WF_ACTIVE_COUNT_4; // 0x24E0 + SPI_CSQ_WF_ACTIVE_COUNT_5 :TSPI_CSQ_WF_ACTIVE_COUNT_5; // 0x24E1 + SPI_CSQ_WF_ACTIVE_COUNT_6 :TSPI_CSQ_WF_ACTIVE_COUNT_6; // 0x24E2 + SPI_CSQ_WF_ACTIVE_COUNT_7 :TSPI_CSQ_WF_ACTIVE_COUNT_7; // 0x24E3 + REG_24E4_24EA :array[0..6] of DWORD; // 0x24E4 + BCI_DEBUG_READ :TBCI_DEBUG_READ; // 0x24EB + SPI_P0_TRAP_SCREEN_PSBA_LO :TSPI_P0_TRAP_SCREEN_PSBA_LO; // 0x24EC + SPI_P0_TRAP_SCREEN_PSBA_HI :TSPI_P0_TRAP_SCREEN_PSBA_HI; // 0x24ED + SPI_P0_TRAP_SCREEN_PSMA_LO :TSPI_P0_TRAP_SCREEN_PSMA_LO; // 0x24EE + SPI_P0_TRAP_SCREEN_PSMA_HI :TSPI_P0_TRAP_SCREEN_PSMA_HI; // 0x24EF + SPI_P0_TRAP_SCREEN_GPR_MIN :TSPI_P0_TRAP_SCREEN_GPR_MIN; // 0x24F0 + SPI_P1_TRAP_SCREEN_PSBA_LO :TSPI_P1_TRAP_SCREEN_PSBA_LO; // 0x24F1 + SPI_P1_TRAP_SCREEN_PSBA_HI :TSPI_P1_TRAP_SCREEN_PSBA_HI; // 0x24F2 + SPI_P1_TRAP_SCREEN_PSMA_LO :TSPI_P1_TRAP_SCREEN_PSMA_LO; // 0x24F3 + SPI_P1_TRAP_SCREEN_PSMA_HI :TSPI_P1_TRAP_SCREEN_PSMA_HI; // 0x24F4 + SPI_P1_TRAP_SCREEN_GPR_MIN :TSPI_P1_TRAP_SCREEN_GPR_MIN; // 0x24F5 + REG_24F6_2524 :array[0..46] of DWORD; // 0x24F6 + TD_CNTL :TTD_CNTL; // 0x2525 + TD_STATUS :TTD_STATUS; // 0x2526 + TD_CGTT_CTRL :TTD_CGTT_CTRL; // 0x2527 + TD_DEBUG_INDEX :TTD_DEBUG_INDEX; // 0x2528 + TD_DEBUG_DATA :TTD_DEBUG_DATA; // 0x2529 + REG_252A_252E :array[0..4] of DWORD; // 0x252A + TD_DSM_CNTL :TTD_DSM_CNTL; // 0x252F + REG_2530_2532 :array[0..2] of DWORD; // 0x2530 + TD_SCRATCH :TTD_SCRATCH; // 0x2533 + REG_2534_2540 :array[0..12] of DWORD; // 0x2534 + TA_CNTL :TTA_CNTL; // 0x2541 + TA_CNTL_AUX :TTA_CNTL_AUX; // 0x2542 + TA_RESERVED_010C :TTA_RESERVED_010C; // 0x2543 + TA_CGTT_CTRL :TTA_CGTT_CTRL; // 0x2544 + REG_2545_2547 :array[0..2] of DWORD; // 0x2545 + TA_STATUS :TTA_STATUS; // 0x2548 + REG_2549_254B :array[0..2] of DWORD; // 0x2549 + TA_DEBUG_INDEX :TTA_DEBUG_INDEX; // 0x254C + TA_DEBUG_DATA :TTA_DEBUG_DATA; // 0x254D + REG_254E_2563 :array[0..21] of DWORD; // 0x254E + TA_SCRATCH :TTA_SCRATCH; // 0x2564 + REG_2565_257F :array[0..26] of DWORD; // 0x2565 + SH_HIDDEN_PRIVATE_BASE_VMID :TSH_HIDDEN_PRIVATE_BASE_VMID; // 0x2580 + SH_STATIC_MEM_CONFIG :TSH_STATIC_MEM_CONFIG; // 0x2581 + REG_2582_25BF :array[0..61] of DWORD; // 0x2582 + GDS_CONFIG :TGDS_CONFIG; // 0x25C0 + GDS_CNTL_STATUS :TGDS_CNTL_STATUS; // 0x25C1 + GDS_ENHANCE2 :TGDS_ENHANCE2; // 0x25C2 + GDS_PROTECTION_FAULT :TGDS_PROTECTION_FAULT; // 0x25C3 + GDS_VM_PROTECTION_FAULT :TGDS_VM_PROTECTION_FAULT; // 0x25C4 + GDS_EDC_CNT :TGDS_EDC_CNT; // 0x25C5 + GDS_EDC_GRBM_CNT :TGDS_EDC_GRBM_CNT; // 0x25C6 + GDS_EDC_OA_DED :TGDS_EDC_OA_DED; // 0x25C7 + GDS_DEBUG_CNTL :TGDS_DEBUG_CNTL; // 0x25C8 + GDS_DEBUG_DATA :TGDS_DEBUG_DATA; // 0x25C9 + GDS_DSM_CNTL :TGDS_DSM_CNTL; // 0x25CA + REG_25CB_25DC :array[0..17] of DWORD; // 0x25CB + CGTT_GDS_CLK_CTRL :TCGTT_GDS_CLK_CTRL; // 0x25DD + REG_25DE_25E1 :array[0..3] of DWORD; // 0x25DE + GDS_SECDED_CNT :TGDS_SECDED_CNT; // 0x25E2 + GDS_GRBM_SECDED_CNT :TGDS_GRBM_SECDED_CNT; // 0x25E3 + GDS_OA_DED :TGDS_OA_DED; // 0x25E4 + REG_25E5_260B :array[0..38] of DWORD; // 0x25E5 + DB_DEBUG :TDB_DEBUG; // 0x260C + DB_DEBUG2 :TDB_DEBUG2; // 0x260D + DB_DEBUG3 :TDB_DEBUG3; // 0x260E + DB_DEBUG4 :TDB_DEBUG4; // 0x260F + REG_2610_2613 :array[0..3] of DWORD; // 0x2610 + DB_CREDIT_LIMIT :TDB_CREDIT_LIMIT; // 0x2614 + DB_WATERMARKS :TDB_WATERMARKS; // 0x2615 + DB_SUBTILE_CONTROL :TDB_SUBTILE_CONTROL; // 0x2616 + DB_FREE_CACHELINES :TDB_FREE_CACHELINES; // 0x2617 + DB_FIFO_DEPTH1 :TDB_FIFO_DEPTH1; // 0x2618 + DB_FIFO_DEPTH2 :TDB_FIFO_DEPTH2; // 0x2619 + DB_CGTT_CLK_CTRL_0 :TDB_CGTT_CLK_CTRL_0; // 0x261A + DB_RING_CONTROL :TDB_RING_CONTROL; // 0x261B + REG_261C_261F :array[0..3] of DWORD; // 0x261C + DB_READ_DEBUG_0 :TDB_READ_DEBUG_0; // 0x2620 + DB_READ_DEBUG_1 :TDB_READ_DEBUG_1; // 0x2621 + DB_READ_DEBUG_2 :TDB_READ_DEBUG_2; // 0x2622 + DB_READ_DEBUG_3 :TDB_READ_DEBUG_3; // 0x2623 + DB_READ_DEBUG_4 :TDB_READ_DEBUG_4; // 0x2624 + DB_READ_DEBUG_5 :TDB_READ_DEBUG_5; // 0x2625 + DB_READ_DEBUG_6 :TDB_READ_DEBUG_6; // 0x2626 + DB_READ_DEBUG_7 :TDB_READ_DEBUG_7; // 0x2627 + DB_READ_DEBUG_8 :TDB_READ_DEBUG_8; // 0x2628 + DB_READ_DEBUG_9 :TDB_READ_DEBUG_9; // 0x2629 + DB_READ_DEBUG_A :TDB_READ_DEBUG_A; // 0x262A + DB_READ_DEBUG_B :TDB_READ_DEBUG_B; // 0x262B + DB_READ_DEBUG_C :TDB_READ_DEBUG_C; // 0x262C + DB_READ_DEBUG_D :TDB_READ_DEBUG_D; // 0x262D + DB_READ_DEBUG_E :TDB_READ_DEBUG_E; // 0x262E + DB_READ_DEBUG_F :TDB_READ_DEBUG_F; // 0x262F + REG_2630_263B :array[0..11] of DWORD; // 0x2630 + CC_RB_REDUNDANCY :TCC_RB_REDUNDANCY; // 0x263C + CC_RB_BACKEND_DISABLE :TCC_RB_BACKEND_DISABLE; // 0x263D + GB_ADDR_CONFIG :TGB_ADDR_CONFIG; // 0x263E + GB_BACKEND_MAP :TGB_BACKEND_MAP; // 0x263F + GB_GPU_ID :TGB_GPU_ID; // 0x2640 + CC_RB_DAISY_CHAIN :TCC_RB_DAISY_CHAIN; // 0x2641 + REG_2642_2643 :array[0..1] of DWORD; // 0x2642 + GB_TILE_MODE0 :TGB_TILE_MODE0; // 0x2644 + GB_TILE_MODE1 :TGB_TILE_MODE1; // 0x2645 + GB_TILE_MODE2 :TGB_TILE_MODE2; // 0x2646 + GB_TILE_MODE3 :TGB_TILE_MODE3; // 0x2647 + GB_TILE_MODE4 :TGB_TILE_MODE4; // 0x2648 + GB_TILE_MODE5 :TGB_TILE_MODE5; // 0x2649 + GB_TILE_MODE6 :TGB_TILE_MODE6; // 0x264A + GB_TILE_MODE7 :TGB_TILE_MODE7; // 0x264B + GB_TILE_MODE8 :TGB_TILE_MODE8; // 0x264C + GB_TILE_MODE9 :TGB_TILE_MODE9; // 0x264D + GB_TILE_MODE10 :TGB_TILE_MODE10; // 0x264E + GB_TILE_MODE11 :TGB_TILE_MODE11; // 0x264F + GB_TILE_MODE12 :TGB_TILE_MODE12; // 0x2650 + GB_TILE_MODE13 :TGB_TILE_MODE13; // 0x2651 + GB_TILE_MODE14 :TGB_TILE_MODE14; // 0x2652 + GB_TILE_MODE15 :TGB_TILE_MODE15; // 0x2653 + GB_TILE_MODE16 :TGB_TILE_MODE16; // 0x2654 + GB_TILE_MODE17 :TGB_TILE_MODE17; // 0x2655 + GB_TILE_MODE18 :TGB_TILE_MODE18; // 0x2656 + GB_TILE_MODE19 :TGB_TILE_MODE19; // 0x2657 + GB_TILE_MODE20 :TGB_TILE_MODE20; // 0x2658 + GB_TILE_MODE21 :TGB_TILE_MODE21; // 0x2659 + GB_TILE_MODE22 :TGB_TILE_MODE22; // 0x265A + GB_TILE_MODE23 :TGB_TILE_MODE23; // 0x265B + GB_TILE_MODE24 :TGB_TILE_MODE24; // 0x265C + GB_TILE_MODE25 :TGB_TILE_MODE25; // 0x265D + GB_TILE_MODE26 :TGB_TILE_MODE26; // 0x265E + GB_TILE_MODE27 :TGB_TILE_MODE27; // 0x265F + GB_TILE_MODE28 :TGB_TILE_MODE28; // 0x2660 + GB_TILE_MODE29 :TGB_TILE_MODE29; // 0x2661 + GB_TILE_MODE30 :TGB_TILE_MODE30; // 0x2662 + GB_TILE_MODE31 :TGB_TILE_MODE31; // 0x2663 + GB_MACROTILE_MODE0 :TGB_MACROTILE_MODE0; // 0x2664 + GB_MACROTILE_MODE1 :TGB_MACROTILE_MODE1; // 0x2665 + GB_MACROTILE_MODE2 :TGB_MACROTILE_MODE2; // 0x2666 + GB_MACROTILE_MODE3 :TGB_MACROTILE_MODE3; // 0x2667 + GB_MACROTILE_MODE4 :TGB_MACROTILE_MODE4; // 0x2668 + GB_MACROTILE_MODE5 :TGB_MACROTILE_MODE5; // 0x2669 + GB_MACROTILE_MODE6 :TGB_MACROTILE_MODE6; // 0x266A + GB_MACROTILE_MODE7 :TGB_MACROTILE_MODE7; // 0x266B + GB_MACROTILE_MODE8 :TGB_MACROTILE_MODE8; // 0x266C + GB_MACROTILE_MODE9 :TGB_MACROTILE_MODE9; // 0x266D + GB_MACROTILE_MODE10 :TGB_MACROTILE_MODE10; // 0x266E + GB_MACROTILE_MODE11 :TGB_MACROTILE_MODE11; // 0x266F + GB_MACROTILE_MODE12 :TGB_MACROTILE_MODE12; // 0x2670 + GB_MACROTILE_MODE13 :TGB_MACROTILE_MODE13; // 0x2671 + GB_MACROTILE_MODE14 :TGB_MACROTILE_MODE14; // 0x2672 + GB_MACROTILE_MODE15 :TGB_MACROTILE_MODE15; // 0x2673 + REG_2674_2682 :array[0..14] of DWORD; // 0x2674 + CB_HW_CONTROL_3 :TCB_HW_CONTROL_3; // 0x2683 + CB_HW_CONTROL :TCB_HW_CONTROL; // 0x2684 + CB_HW_CONTROL_1 :TCB_HW_CONTROL_1; // 0x2685 + CB_HW_CONTROL_2 :TCB_HW_CONTROL_2; // 0x2686 + CB_DCC_CONFIG :TCB_DCC_CONFIG; // 0x2687 + CB_PERFCOUNTER0_SELECT0 :TCB_PERFCOUNTER0_SELECT0; // 0x2688 + REG_2689 :DWORD; // 0x2689 + CB_PERFCOUNTER1_SELECT0 :TCB_PERFCOUNTER1_SELECT0; // 0x268A + CB_PERFCOUNTER1_SELECT1 :TCB_PERFCOUNTER1_SELECT1; // 0x268B + CB_PERFCOUNTER2_SELECT0 :TCB_PERFCOUNTER2_SELECT0; // 0x268C + CB_PERFCOUNTER2_SELECT1 :TCB_PERFCOUNTER2_SELECT1; // 0x268D + CB_PERFCOUNTER3_SELECT0 :TCB_PERFCOUNTER3_SELECT0; // 0x268E + CB_PERFCOUNTER3_SELECT1 :TCB_PERFCOUNTER3_SELECT1; // 0x268F + REG_2690_2697 :array[0..7] of DWORD; // 0x2690 + CB_CGTT_SCLK_CTRL :TCB_CGTT_SCLK_CTRL; // 0x2698 + CB_DEBUG_BUS_1 :TCB_DEBUG_BUS_1; // 0x2699 + CB_DEBUG_BUS_2 :TCB_DEBUG_BUS_2; // 0x269A + REG_269B_26A4 :array[0..9] of DWORD; // 0x269B + CB_DEBUG_BUS_13 :TCB_DEBUG_BUS_13; // 0x26A5 + CB_DEBUG_BUS_14 :TCB_DEBUG_BUS_14; // 0x26A6 + CB_DEBUG_BUS_15 :TCB_DEBUG_BUS_15; // 0x26A7 + CB_DEBUG_BUS_16 :TCB_DEBUG_BUS_16; // 0x26A8 + CB_DEBUG_BUS_17 :TCB_DEBUG_BUS_17; // 0x26A9 + CB_DEBUG_BUS_18 :TCB_DEBUG_BUS_18; // 0x26AA + CB_DEBUG_BUS_19 :TCB_DEBUG_BUS_19; // 0x26AB + CB_DEBUG_BUS_20 :TCB_DEBUG_BUS_20; // 0x26AC + CB_DEBUG_BUS_21 :TCB_DEBUG_BUS_21; // 0x26AD + CB_DEBUG_BUS_22 :TCB_DEBUG_BUS_22; // 0x26AE + REG_26AF_26DD :array[0..46] of DWORD; // 0x26AF + GC_USER_RB_REDUNDANCY :TGC_USER_RB_REDUNDANCY; // 0x26DE + GC_USER_RB_BACKEND_DISABLE :TGC_USER_RB_BACKEND_DISABLE; // 0x26DF + REG_26E0_2AFF :array[0..1055] of DWORD; // 0x26E0 + TCP_INVALIDATE :TTCP_INVALIDATE; // 0x2B00 + TCP_STATUS :TTCP_STATUS; // 0x2B01 + TCP_CNTL :TTCP_CNTL; // 0x2B02 + TCP_CHAN_STEER_LO :TTCP_CHAN_STEER_LO; // 0x2B03 + TCP_CHAN_STEER_HI :TTCP_CHAN_STEER_HI; // 0x2B04 + TCP_ADDR_CONFIG :TTCP_ADDR_CONFIG; // 0x2B05 + TCP_CREDIT :TTCP_CREDIT; // 0x2B06 + REG_2B07_2B14 :array[0..13] of DWORD; // 0x2B07 + CGTT_TCP_CLK_CTRL :TCGTT_TCP_CLK_CTRL; // 0x2B15 + TCP_BUFFER_ADDR_HASH_CNTL :TTCP_BUFFER_ADDR_HASH_CNTL; // 0x2B16 + TCP_EDC_CNT :TTCP_EDC_CNT; // 0x2B17 + REG_2B18_2B19 :array[0..1] of DWORD; // 0x2B18 + TC_CFG_L1_LOAD_POLICY0 :TTC_CFG_L1_LOAD_POLICY0; // 0x2B1A + TC_CFG_L1_LOAD_POLICY1 :TTC_CFG_L1_LOAD_POLICY1; // 0x2B1B + TC_CFG_L1_STORE_POLICY :TTC_CFG_L1_STORE_POLICY; // 0x2B1C + TC_CFG_L2_LOAD_POLICY0 :TTC_CFG_L2_LOAD_POLICY0; // 0x2B1D + TC_CFG_L2_LOAD_POLICY1 :TTC_CFG_L2_LOAD_POLICY1; // 0x2B1E + TC_CFG_L2_STORE_POLICY0 :TTC_CFG_L2_STORE_POLICY0; // 0x2B1F + TC_CFG_L2_STORE_POLICY1 :TTC_CFG_L2_STORE_POLICY1; // 0x2B20 + TC_CFG_L2_ATOMIC_POLICY :TTC_CFG_L2_ATOMIC_POLICY; // 0x2B21 + TC_CFG_L1_VOLATILE :TTC_CFG_L1_VOLATILE; // 0x2B22 + TC_CFG_L2_VOLATILE :TTC_CFG_L2_VOLATILE; // 0x2B23 + REG_2B24_2B5F :array[0..59] of DWORD; // 0x2B24 + CGTT_TCI_CLK_CTRL :TCGTT_TCI_CLK_CTRL; // 0x2B60 + TCI_STATUS :TTCI_STATUS; // 0x2B61 + TCI_CNTL_1 :TTCI_CNTL_1; // 0x2B62 + TCI_CNTL_2 :TTCI_CNTL_2; // 0x2B63 + REG_2B64_2B7F :array[0..27] of DWORD; // 0x2B64 + TCC_CTRL :TTCC_CTRL; // 0x2B80 + TCC_CGTT_SCLK_CTRL :TTCC_CGTT_SCLK_CTRL; // 0x2B81 + TCC_EDC_CNT :TTCC_EDC_CNT; // 0x2B82 + TCC_REDUNDANCY :TTCC_REDUNDANCY; // 0x2B83 + TCC_EXE_DISABLE :TTCC_EXE_DISABLE; // 0x2B84 + TCC_DSM_CNTL :TTCC_DSM_CNTL; // 0x2B85 + REG_2B86_2BBF :array[0..57] of DWORD; // 0x2B86 + TCA_CTRL :TTCA_CTRL; // 0x2BC0 + TCA_CGTT_SCLK_CTRL :TTCA_CGTT_SCLK_CTRL; // 0x2BC1 + REG_2BC2_301F :array[0..1117] of DWORD; // 0x2BC2 + CP_DFY_CNTL :TCP_DFY_CNTL; // 0x3020 + CP_DFY_STAT :TCP_DFY_STAT; // 0x3021 + CP_DFY_ADDR_HI :TCP_DFY_ADDR_HI; // 0x3022 + CP_DFY_ADDR_LO :TCP_DFY_ADDR_LO; // 0x3023 + CP_DFY_DATA_0 :TCP_DFY_DATA_0; // 0x3024 + CP_DFY_DATA_1 :TCP_DFY_DATA_1; // 0x3025 + CP_DFY_DATA_2 :TCP_DFY_DATA_2; // 0x3026 + CP_DFY_DATA_3 :TCP_DFY_DATA_3; // 0x3027 + CP_DFY_DATA_4 :TCP_DFY_DATA_4; // 0x3028 + CP_DFY_DATA_5 :TCP_DFY_DATA_5; // 0x3029 + CP_DFY_DATA_6 :TCP_DFY_DATA_6; // 0x302A + CP_DFY_DATA_7 :TCP_DFY_DATA_7; // 0x302B + CP_DFY_DATA_8 :TCP_DFY_DATA_8; // 0x302C + CP_DFY_DATA_9 :TCP_DFY_DATA_9; // 0x302D + CP_DFY_DATA_10 :TCP_DFY_DATA_10; // 0x302E + CP_DFY_DATA_11 :TCP_DFY_DATA_11; // 0x302F + CP_DFY_DATA_12 :TCP_DFY_DATA_12; // 0x3030 + CP_DFY_DATA_13 :TCP_DFY_DATA_13; // 0x3031 + CP_DFY_DATA_14 :TCP_DFY_DATA_14; // 0x3032 + CP_DFY_DATA_15 :TCP_DFY_DATA_15; // 0x3033 + CP_DFY_CMD :TCP_DFY_CMD; // 0x3034 + REG_3035 :DWORD; // 0x3035 + CP_CPC_MGCG_SYNC_CNTL :TCP_CPC_MGCG_SYNC_CNTL; // 0x3036 + REG_3037 :DWORD; // 0x3037 + CP_VIRT_STATUS :TCP_VIRT_STATUS; // 0x3038 + REG_3039_303F :array[0..6] of DWORD; // 0x3039 + CP_RB0_BASE :TCP_RB0_BASE; // 0x3040 + CP_RB0_CNTL :TCP_RB0_CNTL; // 0x3041 + CP_RB_RPTR_WR :TCP_RB_RPTR_WR; // 0x3042 + CP_RB0_RPTR_ADDR :TCP_RB0_RPTR_ADDR; // 0x3043 + CP_RB0_RPTR_ADDR_HI :TCP_RB0_RPTR_ADDR_HI; // 0x3044 + CP_RB0_WPTR :TCP_RB0_WPTR; // 0x3045 + CP_RB_WPTR_POLL_ADDR_LO :TCP_RB_WPTR_POLL_ADDR_LO; // 0x3046 + CP_RB_WPTR_POLL_ADDR_HI :TCP_RB_WPTR_POLL_ADDR_HI; // 0x3047 + REG_3048 :DWORD; // 0x3048 + CP_INT_CNTL :TCP_INT_CNTL; // 0x3049 + CP_INT_STATUS :TCP_INT_STATUS; // 0x304A + CP_DEVICE_ID :TCP_DEVICE_ID; // 0x304B + CP_ME0_PIPE_PRIORITY_CNTS :TCP_ME0_PIPE_PRIORITY_CNTS; // 0x304C + CP_ME0_PIPE0_PRIORITY :TCP_ME0_PIPE0_PRIORITY; // 0x304D + CP_ME0_PIPE1_PRIORITY :TCP_ME0_PIPE1_PRIORITY; // 0x304E + CP_ME0_PIPE2_PRIORITY :TCP_ME0_PIPE2_PRIORITY; // 0x304F + CP_ENDIAN_SWAP :TCP_ENDIAN_SWAP; // 0x3050 + CP_RB_VMID :TCP_RB_VMID; // 0x3051 + CP_ME0_PIPE0_VMID :TCP_ME0_PIPE0_VMID; // 0x3052 + CP_ME0_PIPE1_VMID :TCP_ME0_PIPE1_VMID; // 0x3053 + REG_3054_3058 :array[0..4] of DWORD; // 0x3054 + CP_RB_DOORBELL_CONTROL :TCP_RB_DOORBELL_CONTROL; // 0x3059 + CP_RB_DOORBELL_RANGE_LOWER :TCP_RB_DOORBELL_RANGE_LOWER; // 0x305A + CP_RB_DOORBELL_RANGE_UPPER :TCP_RB_DOORBELL_RANGE_UPPER; // 0x305B + CP_MEC_DOORBELL_RANGE_LOWER :TCP_MEC_DOORBELL_RANGE_LOWER; // 0x305C + CP_MEC_DOORBELL_RANGE_UPPER :TCP_MEC_DOORBELL_RANGE_UPPER; // 0x305D + REG_305E_305F :array[0..1] of DWORD; // 0x305E + CP_RB1_BASE :TCP_RB1_BASE; // 0x3060 + CP_RB1_CNTL :TCP_RB1_CNTL; // 0x3061 + CP_RB1_RPTR_ADDR :TCP_RB1_RPTR_ADDR; // 0x3062 + CP_RB1_RPTR_ADDR_HI :TCP_RB1_RPTR_ADDR_HI; // 0x3063 + CP_RB1_WPTR :TCP_RB1_WPTR; // 0x3064 + CP_RB2_BASE :TCP_RB2_BASE; // 0x3065 + CP_RB2_CNTL :TCP_RB2_CNTL; // 0x3066 + CP_RB2_RPTR_ADDR :TCP_RB2_RPTR_ADDR; // 0x3067 + CP_RB2_RPTR_ADDR_HI :TCP_RB2_RPTR_ADDR_HI; // 0x3068 + CP_RB2_WPTR :TCP_RB2_WPTR; // 0x3069 + CP_INT_CNTL_RING0 :TCP_INT_CNTL_RING0; // 0x306A + CP_INT_CNTL_RING1 :TCP_INT_CNTL_RING1; // 0x306B + CP_INT_CNTL_RING2 :TCP_INT_CNTL_RING2; // 0x306C + CP_INT_STATUS_RING0 :TCP_INT_STATUS_RING0; // 0x306D + CP_INT_STATUS_RING1 :TCP_INT_STATUS_RING1; // 0x306E + CP_INT_STATUS_RING2 :TCP_INT_STATUS_RING2; // 0x306F + REG_3070_3077 :array[0..7] of DWORD; // 0x3070 + CP_PWR_CNTL :TCP_PWR_CNTL; // 0x3078 + CP_MEM_SLP_CNTL :TCP_MEM_SLP_CNTL; // 0x3079 + CP_ECC_FIRSTOCCURRENCE :TCP_ECC_FIRSTOCCURRENCE; // 0x307A + CP_ECC_FIRSTOCCURRENCE_RING0 :TCP_ECC_FIRSTOCCURRENCE_RING0; // 0x307B + CP_ECC_FIRSTOCCURRENCE_RING1 :TCP_ECC_FIRSTOCCURRENCE_RING1; // 0x307C + CP_ECC_FIRSTOCCURRENCE_RING2 :TCP_ECC_FIRSTOCCURRENCE_RING2; // 0x307D + GB_EDC_MODE :TGB_EDC_MODE; // 0x307E + CP_DEBUG :TCP_DEBUG; // 0x307F + REG_3080_3082 :array[0..2] of DWORD; // 0x3080 + CP_PQ_WPTR_POLL_CNTL :TCP_PQ_WPTR_POLL_CNTL; // 0x3083 + CP_PQ_WPTR_POLL_CNTL1 :TCP_PQ_WPTR_POLL_CNTL1; // 0x3084 + CP_ME1_PIPE0_INT_CNTL :TCP_ME1_PIPE0_INT_CNTL; // 0x3085 + CP_ME1_PIPE1_INT_CNTL :TCP_ME1_PIPE1_INT_CNTL; // 0x3086 + CP_ME1_PIPE2_INT_CNTL :TCP_ME1_PIPE2_INT_CNTL; // 0x3087 + CP_ME1_PIPE3_INT_CNTL :TCP_ME1_PIPE3_INT_CNTL; // 0x3088 + CP_ME2_PIPE0_INT_CNTL :TCP_ME2_PIPE0_INT_CNTL; // 0x3089 + CP_ME2_PIPE1_INT_CNTL :TCP_ME2_PIPE1_INT_CNTL; // 0x308A + CP_ME2_PIPE2_INT_CNTL :TCP_ME2_PIPE2_INT_CNTL; // 0x308B + CP_ME2_PIPE3_INT_CNTL :TCP_ME2_PIPE3_INT_CNTL; // 0x308C + CP_ME1_PIPE0_INT_STATUS :TCP_ME1_PIPE0_INT_STATUS; // 0x308D + CP_ME1_PIPE1_INT_STATUS :TCP_ME1_PIPE1_INT_STATUS; // 0x308E + CP_ME1_PIPE2_INT_STATUS :TCP_ME1_PIPE2_INT_STATUS; // 0x308F + CP_ME1_PIPE3_INT_STATUS :TCP_ME1_PIPE3_INT_STATUS; // 0x3090 + CP_ME2_PIPE0_INT_STATUS :TCP_ME2_PIPE0_INT_STATUS; // 0x3091 + CP_ME2_PIPE1_INT_STATUS :TCP_ME2_PIPE1_INT_STATUS; // 0x3092 + CP_ME2_PIPE2_INT_STATUS :TCP_ME2_PIPE2_INT_STATUS; // 0x3093 + CP_ME2_PIPE3_INT_STATUS :TCP_ME2_PIPE3_INT_STATUS; // 0x3094 + CP_ME1_INT_STAT_DEBUG :TCP_ME1_INT_STAT_DEBUG; // 0x3095 + CP_ME2_INT_STAT_DEBUG :TCP_ME2_INT_STAT_DEBUG; // 0x3096 + REG_3097 :DWORD; // 0x3097 + CC_GC_EDC_CONFIG :TCC_GC_EDC_CONFIG; // 0x3098 + CP_ME1_PIPE_PRIORITY_CNTS :TCP_ME1_PIPE_PRIORITY_CNTS; // 0x3099 + CP_ME1_PIPE0_PRIORITY :TCP_ME1_PIPE0_PRIORITY; // 0x309A + CP_ME1_PIPE1_PRIORITY :TCP_ME1_PIPE1_PRIORITY; // 0x309B + CP_ME1_PIPE2_PRIORITY :TCP_ME1_PIPE2_PRIORITY; // 0x309C + CP_ME1_PIPE3_PRIORITY :TCP_ME1_PIPE3_PRIORITY; // 0x309D + CP_ME2_PIPE_PRIORITY_CNTS :TCP_ME2_PIPE_PRIORITY_CNTS; // 0x309E + CP_ME2_PIPE0_PRIORITY :TCP_ME2_PIPE0_PRIORITY; // 0x309F + CP_ME2_PIPE1_PRIORITY :TCP_ME2_PIPE1_PRIORITY; // 0x30A0 + CP_ME2_PIPE2_PRIORITY :TCP_ME2_PIPE2_PRIORITY; // 0x30A1 + CP_ME2_PIPE3_PRIORITY :TCP_ME2_PIPE3_PRIORITY; // 0x30A2 + CP_CE_PRGRM_CNTR_START :TCP_CE_PRGRM_CNTR_START; // 0x30A3 + CP_PFP_PRGRM_CNTR_START :TCP_PFP_PRGRM_CNTR_START; // 0x30A4 + CP_ME_PRGRM_CNTR_START :TCP_ME_PRGRM_CNTR_START; // 0x30A5 + CP_MEC1_PRGRM_CNTR_START :TCP_MEC1_PRGRM_CNTR_START; // 0x30A6 + CP_MEC2_PRGRM_CNTR_START :TCP_MEC2_PRGRM_CNTR_START; // 0x30A7 + CP_CE_INTR_ROUTINE_START :TCP_CE_INTR_ROUTINE_START; // 0x30A8 + CP_PFP_INTR_ROUTINE_START :TCP_PFP_INTR_ROUTINE_START; // 0x30A9 + CP_ME_INTR_ROUTINE_START :TCP_ME_INTR_ROUTINE_START; // 0x30AA + CP_MEC1_INTR_ROUTINE_START :TCP_MEC1_INTR_ROUTINE_START; // 0x30AB + CP_MEC2_INTR_ROUTINE_START :TCP_MEC2_INTR_ROUTINE_START; // 0x30AC + CP_CONTEXT_CNTL :TCP_CONTEXT_CNTL; // 0x30AD + CP_MAX_CONTEXT :TCP_MAX_CONTEXT; // 0x30AE + CP_IQ_WAIT_TIME1 :TCP_IQ_WAIT_TIME1; // 0x30AF + CP_IQ_WAIT_TIME2 :TCP_IQ_WAIT_TIME2; // 0x30B0 + CP_RB0_BASE_HI :TCP_RB0_BASE_HI; // 0x30B1 + CP_RB1_BASE_HI :TCP_RB1_BASE_HI; // 0x30B2 + CP_VMID_RESET :TCP_VMID_RESET; // 0x30B3 + CPC_INT_CNTL :TCPC_INT_CNTL; // 0x30B4 + CPC_INT_STATUS :TCPC_INT_STATUS; // 0x30B5 + CP_VMID_PREEMPT :TCP_VMID_PREEMPT; // 0x30B6 + CPC_INT_CNTX_ID :TCPC_INT_CNTX_ID; // 0x30B7 + CP_PQ_STATUS :TCP_PQ_STATUS; // 0x30B8 + CP_CPC_IC_BASE_LO :TCP_CPC_IC_BASE_LO; // 0x30B9 + CP_CPC_IC_BASE_HI :TCP_CPC_IC_BASE_HI; // 0x30BA + CP_CPC_IC_BASE_CNTL :TCP_CPC_IC_BASE_CNTL; // 0x30BB + CP_CPC_IC_OP_CNTL :TCP_CPC_IC_OP_CNTL; // 0x30BC + CP_MEC1_F32_INT_DIS :TCP_MEC1_F32_INT_DIS; // 0x30BD + CP_MEC2_F32_INT_DIS :TCP_MEC2_F32_INT_DIS; // 0x30BE + CP_VMID_STATUS :TCP_VMID_STATUS; // 0x30BF + REG_30C0_30C2 :array[0..2] of DWORD; // 0x30C0 + RLC_LB_CNTL :TRLC_LB_CNTL; // 0x30C3 + RLC_SAVE_AND_RESTORE_BASE :TRLC_SAVE_AND_RESTORE_BASE; // 0x30C4 + RLC_LB_CNTR_MAX :TRLC_LB_CNTR_MAX; // 0x30C5 + RLC_LB_CNTR_INIT :TRLC_LB_CNTR_INIT; // 0x30C6 + RLC_DRIVER_CPDMA_STATUS :TRLC_DRIVER_CPDMA_STATUS; // 0x30C7 + REG_30C8 :DWORD; // 0x30C8 + RLC_DEBUG_SELECT :TRLC_DEBUG_SELECT; // 0x30C9 + RLC_DEBUG :TRLC_DEBUG; // 0x30CA + REG_30CB_30CD :array[0..2] of DWORD; // 0x30CB + RLC_GPU_CLOCK_COUNT_LSB :TRLC_GPU_CLOCK_COUNT_LSB; // 0x30CE + RLC_GPU_CLOCK_COUNT_MSB :TRLC_GPU_CLOCK_COUNT_MSB; // 0x30CF + RLC_CAPTURE_GPU_CLOCK_COUNT :TRLC_CAPTURE_GPU_CLOCK_COUNT; // 0x30D0 + RLC_MC_CNTL :TRLC_MC_CNTL; // 0x30D1 + RLC_UCODE_CNTL :TRLC_UCODE_CNTL; // 0x30D2 + RLC_STAT :TRLC_STAT; // 0x30D3 + RLC_GPU_CLOCK_32_RES_SEL :TRLC_GPU_CLOCK_32_RES_SEL; // 0x30D4 + RLC_GPU_CLOCK_32 :TRLC_GPU_CLOCK_32; // 0x30D5 + RLC_SOFT_RESET_GPU :TRLC_SOFT_RESET_GPU; // 0x30D6 + RLC_PG_CNTL :TRLC_PG_CNTL; // 0x30D7 + RLC_MEM_SLP_CNTL :TRLC_MEM_SLP_CNTL; // 0x30D8 + RLC_PERFMON_CNTL :TRLC_PERFMON_CNTL; // 0x30D9 + RLC_PERFCOUNTER0_SELECT :TRLC_PERFCOUNTER0_SELECT; // 0x30DA + REG_30DB_30DC :array[0..1] of DWORD; // 0x30DB + RLC_PERFCOUNTER1_SELECT :TRLC_PERFCOUNTER1_SELECT; // 0x30DD + REG_30DE_30DF :array[0..1] of DWORD; // 0x30DE + CGTT_RLC_CLK_CTRL :TCGTT_RLC_CLK_CTRL; // 0x30E0 + REG_30E1_30F5 :array[0..20] of DWORD; // 0x30E1 + RLC_LOAD_BALANCE_CNTR :TRLC_LOAD_BALANCE_CNTR; // 0x30F6 + REG_30F7_30FF :array[0..8] of DWORD; // 0x30F7 + RLC_CGTT_MGCG_OVERRIDE :TRLC_CGTT_MGCG_OVERRIDE; // 0x3100 + RLC_CGCG_CGLS_CTRL :TRLC_CGCG_CGLS_CTRL; // 0x3101 + RLC_CGCG_RAMP_CTRL :TRLC_CGCG_RAMP_CTRL; // 0x3102 + RLC_DYN_PG_STATUS :TRLC_DYN_PG_STATUS; // 0x3103 + RLC_DYN_PG_REQUEST :TRLC_DYN_PG_REQUEST; // 0x3104 + REG_3105 :DWORD; // 0x3105 + RLC_CU_STATUS :TRLC_CU_STATUS; // 0x3106 + RLC_LB_INIT_CU_MASK :TRLC_LB_INIT_CU_MASK; // 0x3107 + RLC_LB_ALWAYS_ACTIVE_CU_MASK :TRLC_LB_ALWAYS_ACTIVE_CU_MASK; // 0x3108 + RLC_LB_PARAMS :TRLC_LB_PARAMS; // 0x3109 + RLC_THREAD1_DELAY :TRLC_THREAD1_DELAY; // 0x310A + RLC_PG_ALWAYS_ON_CU_MASK :TRLC_PG_ALWAYS_ON_CU_MASK; // 0x310B + RLC_MAX_PG_CU :TRLC_MAX_PG_CU; // 0x310C + RLC_AUTO_PG_CTRL :TRLC_AUTO_PG_CTRL; // 0x310D + RLC_SMU_GRBM_REG_SAVE_CTRL :TRLC_SMU_GRBM_REG_SAVE_CTRL; // 0x310E + RLC_SMU_PG_CTRL :TRLC_SMU_PG_CTRL; // 0x310F + RLC_SMU_PG_WAKE_UP_CTRL :TRLC_SMU_PG_WAKE_UP_CTRL; // 0x3110 + RLC_SERDES_RD_MASTER_INDEX :TRLC_SERDES_RD_MASTER_INDEX; // 0x3111 + RLC_SERDES_RD_DATA_0 :TRLC_SERDES_RD_DATA_0; // 0x3112 + RLC_SERDES_RD_DATA_1 :TRLC_SERDES_RD_DATA_1; // 0x3113 + RLC_SERDES_RD_DATA_2 :TRLC_SERDES_RD_DATA_2; // 0x3114 + REG_3115_3116 :array[0..1] of DWORD; // 0x3115 + RLC_SERDES_WR_CTRL :TRLC_SERDES_WR_CTRL; // 0x3117 + RLC_SERDES_WR_DATA :TRLC_SERDES_WR_DATA; // 0x3118 + REG_3119_31BF :array[0..166] of DWORD; // 0x3119 + SPI_ARB_PRIORITY :TSPI_ARB_PRIORITY; // 0x31C0 + SPI_ARB_CYCLES_0 :TSPI_ARB_CYCLES_0; // 0x31C1 + SPI_ARB_CYCLES_1 :TSPI_ARB_CYCLES_1; // 0x31C2 + SPI_CDBG_SYS_GFX :TSPI_CDBG_SYS_GFX; // 0x31C3 + SPI_CDBG_SYS_HP3D :TSPI_CDBG_SYS_HP3D; // 0x31C4 + SPI_CDBG_SYS_CS0 :TSPI_CDBG_SYS_CS0; // 0x31C5 + SPI_CDBG_SYS_CS1 :TSPI_CDBG_SYS_CS1; // 0x31C6 + SPI_WCL_PIPE_PERCENT_GFX :TSPI_WCL_PIPE_PERCENT_GFX; // 0x31C7 + SPI_WCL_PIPE_PERCENT_HP3D :TSPI_WCL_PIPE_PERCENT_HP3D; // 0x31C8 + SPI_WCL_PIPE_PERCENT_CS0 :TSPI_WCL_PIPE_PERCENT_CS0; // 0x31C9 + SPI_WCL_PIPE_PERCENT_CS1 :TSPI_WCL_PIPE_PERCENT_CS1; // 0x31CA + SPI_WCL_PIPE_PERCENT_CS2 :TSPI_WCL_PIPE_PERCENT_CS2; // 0x31CB + SPI_WCL_PIPE_PERCENT_CS3 :TSPI_WCL_PIPE_PERCENT_CS3; // 0x31CC + SPI_WCL_PIPE_PERCENT_CS4 :TSPI_WCL_PIPE_PERCENT_CS4; // 0x31CD + SPI_WCL_PIPE_PERCENT_CS5 :TSPI_WCL_PIPE_PERCENT_CS5; // 0x31CE + SPI_WCL_PIPE_PERCENT_CS6 :TSPI_WCL_PIPE_PERCENT_CS6; // 0x31CF + SPI_WCL_PIPE_PERCENT_CS7 :TSPI_WCL_PIPE_PERCENT_CS7; // 0x31D0 + SPI_GDBG_WAVE_CNTL :TSPI_GDBG_WAVE_CNTL; // 0x31D1 + SPI_GDBG_TRAP_CONFIG :TSPI_GDBG_TRAP_CONFIG; // 0x31D2 + SPI_GDBG_TRAP_MASK :TSPI_GDBG_TRAP_MASK; // 0x31D3 + SPI_GDBG_TBA_LO :TSPI_GDBG_TBA_LO; // 0x31D4 + SPI_GDBG_TBA_HI :TSPI_GDBG_TBA_HI; // 0x31D5 + SPI_GDBG_TMA_LO :TSPI_GDBG_TMA_LO; // 0x31D6 + SPI_GDBG_TMA_HI :TSPI_GDBG_TMA_HI; // 0x31D7 + SPI_GDBG_TRAP_DATA0 :TSPI_GDBG_TRAP_DATA0; // 0x31D8 + SPI_GDBG_TRAP_DATA1 :TSPI_GDBG_TRAP_DATA1; // 0x31D9 + SPI_RESET_DEBUG :TSPI_RESET_DEBUG; // 0x31DA + SPI_COMPUTE_QUEUE_RESET :TSPI_COMPUTE_QUEUE_RESET; // 0x31DB + SPI_RESOURCE_RESERVE_CU_0 :TSPI_RESOURCE_RESERVE_CU_0; // 0x31DC + SPI_RESOURCE_RESERVE_CU_1 :TSPI_RESOURCE_RESERVE_CU_1; // 0x31DD + SPI_RESOURCE_RESERVE_CU_2 :TSPI_RESOURCE_RESERVE_CU_2; // 0x31DE + SPI_RESOURCE_RESERVE_CU_3 :TSPI_RESOURCE_RESERVE_CU_3; // 0x31DF + SPI_RESOURCE_RESERVE_CU_4 :TSPI_RESOURCE_RESERVE_CU_4; // 0x31E0 + SPI_RESOURCE_RESERVE_CU_5 :TSPI_RESOURCE_RESERVE_CU_5; // 0x31E1 + SPI_RESOURCE_RESERVE_CU_6 :TSPI_RESOURCE_RESERVE_CU_6; // 0x31E2 + SPI_RESOURCE_RESERVE_CU_7 :TSPI_RESOURCE_RESERVE_CU_7; // 0x31E3 + SPI_RESOURCE_RESERVE_CU_8 :TSPI_RESOURCE_RESERVE_CU_8; // 0x31E4 + SPI_RESOURCE_RESERVE_CU_9 :TSPI_RESOURCE_RESERVE_CU_9; // 0x31E5 + SPI_RESOURCE_RESERVE_EN_CU_0 :TSPI_RESOURCE_RESERVE_EN_CU_0; // 0x31E6 + SPI_RESOURCE_RESERVE_EN_CU_1 :TSPI_RESOURCE_RESERVE_EN_CU_1; // 0x31E7 + SPI_RESOURCE_RESERVE_EN_CU_2 :TSPI_RESOURCE_RESERVE_EN_CU_2; // 0x31E8 + SPI_RESOURCE_RESERVE_EN_CU_3 :TSPI_RESOURCE_RESERVE_EN_CU_3; // 0x31E9 + SPI_RESOURCE_RESERVE_EN_CU_4 :TSPI_RESOURCE_RESERVE_EN_CU_4; // 0x31EA + SPI_RESOURCE_RESERVE_EN_CU_5 :TSPI_RESOURCE_RESERVE_EN_CU_5; // 0x31EB + SPI_RESOURCE_RESERVE_EN_CU_6 :TSPI_RESOURCE_RESERVE_EN_CU_6; // 0x31EC + SPI_RESOURCE_RESERVE_EN_CU_7 :TSPI_RESOURCE_RESERVE_EN_CU_7; // 0x31ED + SPI_RESOURCE_RESERVE_EN_CU_8 :TSPI_RESOURCE_RESERVE_EN_CU_8; // 0x31EE + SPI_RESOURCE_RESERVE_EN_CU_9 :TSPI_RESOURCE_RESERVE_EN_CU_9; // 0x31EF + SPI_RESOURCE_RESERVE_CU_10 :TSPI_RESOURCE_RESERVE_CU_10; // 0x31F0 + SPI_RESOURCE_RESERVE_CU_11 :TSPI_RESOURCE_RESERVE_CU_11; // 0x31F1 + SPI_RESOURCE_RESERVE_EN_CU_10 :TSPI_RESOURCE_RESERVE_EN_CU_10; // 0x31F2 + SPI_RESOURCE_RESERVE_EN_CU_11 :TSPI_RESOURCE_RESERVE_EN_CU_11; // 0x31F3 + SPI_RESOURCE_RESERVE_CU_12 :TSPI_RESOURCE_RESERVE_CU_12; // 0x31F4 + SPI_RESOURCE_RESERVE_CU_13 :TSPI_RESOURCE_RESERVE_CU_13; // 0x31F5 + SPI_RESOURCE_RESERVE_CU_14 :TSPI_RESOURCE_RESERVE_CU_14; // 0x31F6 + SPI_RESOURCE_RESERVE_CU_15 :TSPI_RESOURCE_RESERVE_CU_15; // 0x31F7 + SPI_RESOURCE_RESERVE_EN_CU_12 :TSPI_RESOURCE_RESERVE_EN_CU_12; // 0x31F8 + SPI_RESOURCE_RESERVE_EN_CU_13 :TSPI_RESOURCE_RESERVE_EN_CU_13; // 0x31F9 + SPI_RESOURCE_RESERVE_EN_CU_14 :TSPI_RESOURCE_RESERVE_EN_CU_14; // 0x31FA + SPI_RESOURCE_RESERVE_EN_CU_15 :TSPI_RESOURCE_RESERVE_EN_CU_15; // 0x31FB + SPI_COMPUTE_WF_CTX_SAVE :TSPI_COMPUTE_WF_CTX_SAVE; // 0x31FC + REG_31FD_323F :array[0..66] of DWORD; // 0x31FD + CP_HPD_ROQ_OFFSETS :TCP_HPD_ROQ_OFFSETS; // 0x3240 + CP_HPD_STATUS0 :TCP_HPD_STATUS0; // 0x3241 + REG_3242_3244 :array[0..2] of DWORD; // 0x3242 + CP_MQD_BASE_ADDR :TCP_MQD_BASE_ADDR; // 0x3245 + CP_MQD_BASE_ADDR_HI :TCP_MQD_BASE_ADDR_HI; // 0x3246 + CP_HQD_ACTIVE :TCP_HQD_ACTIVE; // 0x3247 + CP_HQD_VMID :TCP_HQD_VMID; // 0x3248 + CP_HQD_PERSISTENT_STATE :TCP_HQD_PERSISTENT_STATE; // 0x3249 + CP_HQD_PIPE_PRIORITY :TCP_HQD_PIPE_PRIORITY; // 0x324A + CP_HQD_QUEUE_PRIORITY :TCP_HQD_QUEUE_PRIORITY; // 0x324B + CP_HQD_QUANTUM :TCP_HQD_QUANTUM; // 0x324C + CP_HQD_PQ_BASE :TCP_HQD_PQ_BASE; // 0x324D + CP_HQD_PQ_BASE_HI :TCP_HQD_PQ_BASE_HI; // 0x324E + CP_HQD_PQ_RPTR :TCP_HQD_PQ_RPTR; // 0x324F + CP_HQD_PQ_RPTR_REPORT_ADDR :TCP_HQD_PQ_RPTR_REPORT_ADDR; // 0x3250 + CP_HQD_PQ_RPTR_REPORT_ADDR_HI :TCP_HQD_PQ_RPTR_REPORT_ADDR_HI; // 0x3251 + CP_HQD_PQ_WPTR_POLL_ADDR :TCP_HQD_PQ_WPTR_POLL_ADDR; // 0x3252 + CP_HQD_PQ_WPTR_POLL_ADDR_HI :TCP_HQD_PQ_WPTR_POLL_ADDR_HI; // 0x3253 + CP_HQD_PQ_DOORBELL_CONTROL :TCP_HQD_PQ_DOORBELL_CONTROL; // 0x3254 + CP_HQD_PQ_WPTR :TCP_HQD_PQ_WPTR; // 0x3255 + CP_HQD_PQ_CONTROL :TCP_HQD_PQ_CONTROL; // 0x3256 + CP_HQD_IB_BASE_ADDR :TCP_HQD_IB_BASE_ADDR; // 0x3257 + CP_HQD_IB_BASE_ADDR_HI :TCP_HQD_IB_BASE_ADDR_HI; // 0x3258 + CP_HQD_IB_RPTR :TCP_HQD_IB_RPTR; // 0x3259 + CP_HQD_IB_CONTROL :TCP_HQD_IB_CONTROL; // 0x325A + CP_HQD_IQ_TIMER :TCP_HQD_IQ_TIMER; // 0x325B + CP_HQD_IQ_RPTR :TCP_HQD_IQ_RPTR; // 0x325C + CP_HQD_DEQUEUE_REQUEST :TCP_HQD_DEQUEUE_REQUEST; // 0x325D + CP_HQD_DMA_OFFLOAD :TCP_HQD_DMA_OFFLOAD; // 0x325E + CP_HQD_SEMA_CMD :TCP_HQD_SEMA_CMD; // 0x325F + CP_HQD_MSG_TYPE :TCP_HQD_MSG_TYPE; // 0x3260 + CP_HQD_ATOMIC0_PREOP_LO :TCP_HQD_ATOMIC0_PREOP_LO; // 0x3261 + CP_HQD_ATOMIC0_PREOP_HI :TCP_HQD_ATOMIC0_PREOP_HI; // 0x3262 + CP_HQD_ATOMIC1_PREOP_LO :TCP_HQD_ATOMIC1_PREOP_LO; // 0x3263 + CP_HQD_ATOMIC1_PREOP_HI :TCP_HQD_ATOMIC1_PREOP_HI; // 0x3264 + CP_HQD_HQ_SCHEDULER0 :TCP_HQD_HQ_SCHEDULER0; // 0x3265 + CP_HQD_HQ_SCHEDULER1 :TCP_HQD_HQ_SCHEDULER1; // 0x3266 + CP_MQD_CONTROL :TCP_MQD_CONTROL; // 0x3267 + CP_HQD_HQ_STATUS1 :TCP_HQD_HQ_STATUS1; // 0x3268 + CP_HQD_HQ_CONTROL1 :TCP_HQD_HQ_CONTROL1; // 0x3269 + CP_HQD_EOP_BASE_ADDR :TCP_HQD_EOP_BASE_ADDR; // 0x326A + CP_HQD_EOP_BASE_ADDR_HI :TCP_HQD_EOP_BASE_ADDR_HI; // 0x326B + CP_HQD_EOP_CONTROL :TCP_HQD_EOP_CONTROL; // 0x326C + CP_HQD_EOP_RPTR :TCP_HQD_EOP_RPTR; // 0x326D + CP_HQD_EOP_WPTR :TCP_HQD_EOP_WPTR; // 0x326E + CP_HQD_EOP_EVENTS :TCP_HQD_EOP_EVENTS; // 0x326F + CP_HQD_CTX_SAVE_BASE_ADDR_LO :TCP_HQD_CTX_SAVE_BASE_ADDR_LO; // 0x3270 + CP_HQD_CTX_SAVE_BASE_ADDR_HI :TCP_HQD_CTX_SAVE_BASE_ADDR_HI; // 0x3271 + CP_HQD_CTX_SAVE_CONTROL :TCP_HQD_CTX_SAVE_CONTROL; // 0x3272 + CP_HQD_CNTL_STACK_OFFSET :TCP_HQD_CNTL_STACK_OFFSET; // 0x3273 + CP_HQD_CNTL_STACK_SIZE :TCP_HQD_CNTL_STACK_SIZE; // 0x3274 + CP_HQD_WG_STATE_OFFSET :TCP_HQD_WG_STATE_OFFSET; // 0x3275 + CP_HQD_CTX_SAVE_SIZE :TCP_HQD_CTX_SAVE_SIZE; // 0x3276 + CP_HQD_GDS_RESOURCE_STATE :TCP_HQD_GDS_RESOURCE_STATE; // 0x3277 + CP_HQD_ERROR :TCP_HQD_ERROR; // 0x3278 + CP_HQD_EOP_WPTR_MEM :TCP_HQD_EOP_WPTR_MEM; // 0x3279 + CP_HQD_EOP_DONES :TCP_HQD_EOP_DONES; // 0x327A + REG_327B_327F :array[0..4] of DWORD; // 0x327B + DIDT_IND_INDEX :TDIDT_IND_INDEX; // 0x3280 + DIDT_IND_DATA :TDIDT_IND_DATA; // 0x3281 + REG_3282_3291 :array[0..15] of DWORD; // 0x3282 + GC_CAC_CGTT_CLK_CTRL :TGC_CAC_CGTT_CLK_CTRL; // 0x3292 + SE_CAC_CGTT_CLK_CTRL :TSE_CAC_CGTT_CLK_CTRL; // 0x3293 + REG_3294_3295 :array[0..1] of DWORD; // 0x3294 + GC_CAC_LKG_AGGR_LOWER :TGC_CAC_LKG_AGGR_LOWER; // 0x3296 + GC_CAC_LKG_AGGR_UPPER :TGC_CAC_LKG_AGGR_UPPER; // 0x3297 + REG_3298_329F :array[0..7] of DWORD; // 0x3298 + TCP_WATCH0_ADDR_H :TTCP_WATCH0_ADDR_H; // 0x32A0 + TCP_WATCH0_ADDR_L :TTCP_WATCH0_ADDR_L; // 0x32A1 + TCP_WATCH0_CNTL :TTCP_WATCH0_CNTL; // 0x32A2 + TCP_WATCH1_ADDR_H :TTCP_WATCH1_ADDR_H; // 0x32A3 + TCP_WATCH1_ADDR_L :TTCP_WATCH1_ADDR_L; // 0x32A4 + TCP_WATCH1_CNTL :TTCP_WATCH1_CNTL; // 0x32A5 + TCP_WATCH2_ADDR_H :TTCP_WATCH2_ADDR_H; // 0x32A6 + TCP_WATCH2_ADDR_L :TTCP_WATCH2_ADDR_L; // 0x32A7 + TCP_WATCH2_CNTL :TTCP_WATCH2_CNTL; // 0x32A8 + TCP_WATCH3_ADDR_H :TTCP_WATCH3_ADDR_H; // 0x32A9 + TCP_WATCH3_ADDR_L :TTCP_WATCH3_ADDR_L; // 0x32AA + TCP_WATCH3_CNTL :TTCP_WATCH3_CNTL; // 0x32AB + REG_32AC_32AF :array[0..3] of DWORD; // 0x32AC + TCP_GATCL1_CNTL :TTCP_GATCL1_CNTL; // 0x32B0 + TCP_ATC_EDC_GATCL1_CNT :TTCP_ATC_EDC_GATCL1_CNT; // 0x32B1 + TCP_GATCL1_DSM_CNTL :TTCP_GATCL1_DSM_CNTL; // 0x32B2 + TCP_DSM_CNTL :TTCP_DSM_CNTL; // 0x32B3 + TCP_CNTL2 :TTCP_CNTL2; // 0x32B4 + REG_32B5_32FF :array[0..74] of DWORD; // 0x32B5 + GDS_VMID0_BASE :TGDS_VMID0_BASE; // 0x3300 + GDS_VMID0_SIZE :TGDS_VMID0_SIZE; // 0x3301 + GDS_VMID1_BASE :TGDS_VMID1_BASE; // 0x3302 + GDS_VMID1_SIZE :TGDS_VMID1_SIZE; // 0x3303 + GDS_VMID2_BASE :TGDS_VMID2_BASE; // 0x3304 + GDS_VMID2_SIZE :TGDS_VMID2_SIZE; // 0x3305 + GDS_VMID3_BASE :TGDS_VMID3_BASE; // 0x3306 + GDS_VMID3_SIZE :TGDS_VMID3_SIZE; // 0x3307 + GDS_VMID4_BASE :TGDS_VMID4_BASE; // 0x3308 + GDS_VMID4_SIZE :TGDS_VMID4_SIZE; // 0x3309 + GDS_VMID5_BASE :TGDS_VMID5_BASE; // 0x330A + GDS_VMID5_SIZE :TGDS_VMID5_SIZE; // 0x330B + GDS_VMID6_BASE :TGDS_VMID6_BASE; // 0x330C + GDS_VMID6_SIZE :TGDS_VMID6_SIZE; // 0x330D + GDS_VMID7_BASE :TGDS_VMID7_BASE; // 0x330E + GDS_VMID7_SIZE :TGDS_VMID7_SIZE; // 0x330F + GDS_VMID8_BASE :TGDS_VMID8_BASE; // 0x3310 + GDS_VMID8_SIZE :TGDS_VMID8_SIZE; // 0x3311 + GDS_VMID9_BASE :TGDS_VMID9_BASE; // 0x3312 + GDS_VMID9_SIZE :TGDS_VMID9_SIZE; // 0x3313 + GDS_VMID10_BASE :TGDS_VMID10_BASE; // 0x3314 + GDS_VMID10_SIZE :TGDS_VMID10_SIZE; // 0x3315 + GDS_VMID11_BASE :TGDS_VMID11_BASE; // 0x3316 + GDS_VMID11_SIZE :TGDS_VMID11_SIZE; // 0x3317 + GDS_VMID12_BASE :TGDS_VMID12_BASE; // 0x3318 + GDS_VMID12_SIZE :TGDS_VMID12_SIZE; // 0x3319 + GDS_VMID13_BASE :TGDS_VMID13_BASE; // 0x331A + GDS_VMID13_SIZE :TGDS_VMID13_SIZE; // 0x331B + GDS_VMID14_BASE :TGDS_VMID14_BASE; // 0x331C + GDS_VMID14_SIZE :TGDS_VMID14_SIZE; // 0x331D + GDS_VMID15_BASE :TGDS_VMID15_BASE; // 0x331E + GDS_VMID15_SIZE :TGDS_VMID15_SIZE; // 0x331F + GDS_GWS_VMID0 :TGDS_GWS_VMID0; // 0x3320 + GDS_GWS_VMID1 :TGDS_GWS_VMID1; // 0x3321 + GDS_GWS_VMID2 :TGDS_GWS_VMID2; // 0x3322 + GDS_GWS_VMID3 :TGDS_GWS_VMID3; // 0x3323 + GDS_GWS_VMID4 :TGDS_GWS_VMID4; // 0x3324 + GDS_GWS_VMID5 :TGDS_GWS_VMID5; // 0x3325 + GDS_GWS_VMID6 :TGDS_GWS_VMID6; // 0x3326 + GDS_GWS_VMID7 :TGDS_GWS_VMID7; // 0x3327 + GDS_GWS_VMID8 :TGDS_GWS_VMID8; // 0x3328 + GDS_GWS_VMID9 :TGDS_GWS_VMID9; // 0x3329 + GDS_GWS_VMID10 :TGDS_GWS_VMID10; // 0x332A + GDS_GWS_VMID11 :TGDS_GWS_VMID11; // 0x332B + GDS_GWS_VMID12 :TGDS_GWS_VMID12; // 0x332C + GDS_GWS_VMID13 :TGDS_GWS_VMID13; // 0x332D + GDS_GWS_VMID14 :TGDS_GWS_VMID14; // 0x332E + GDS_GWS_VMID15 :TGDS_GWS_VMID15; // 0x332F + GDS_OA_VMID0 :TGDS_OA_VMID0; // 0x3330 + GDS_OA_VMID1 :TGDS_OA_VMID1; // 0x3331 + GDS_OA_VMID2 :TGDS_OA_VMID2; // 0x3332 + GDS_OA_VMID3 :TGDS_OA_VMID3; // 0x3333 + GDS_OA_VMID4 :TGDS_OA_VMID4; // 0x3334 + GDS_OA_VMID5 :TGDS_OA_VMID5; // 0x3335 + GDS_OA_VMID6 :TGDS_OA_VMID6; // 0x3336 + GDS_OA_VMID7 :TGDS_OA_VMID7; // 0x3337 + GDS_OA_VMID8 :TGDS_OA_VMID8; // 0x3338 + GDS_OA_VMID9 :TGDS_OA_VMID9; // 0x3339 + GDS_OA_VMID10 :TGDS_OA_VMID10; // 0x333A + GDS_OA_VMID11 :TGDS_OA_VMID11; // 0x333B + GDS_OA_VMID12 :TGDS_OA_VMID12; // 0x333C + GDS_OA_VMID13 :TGDS_OA_VMID13; // 0x333D + GDS_OA_VMID14 :TGDS_OA_VMID14; // 0x333E + GDS_OA_VMID15 :TGDS_OA_VMID15; // 0x333F + REG_3340_3343 :array[0..3] of DWORD; // 0x3340 + GDS_GWS_RESET0 :TGDS_GWS_RESET0; // 0x3344 + GDS_GWS_RESET1 :TGDS_GWS_RESET1; // 0x3345 + GDS_GWS_RESOURCE_RESET :TGDS_GWS_RESOURCE_RESET; // 0x3346 + REG_3347 :DWORD; // 0x3347 + GDS_COMPUTE_MAX_WAVE_ID :TGDS_COMPUTE_MAX_WAVE_ID; // 0x3348 + GDS_OA_RESET_MASK :TGDS_OA_RESET_MASK; // 0x3349 + GDS_OA_RESET :TGDS_OA_RESET; // 0x334A + GDS_ENHANCE :TGDS_ENHANCE; // 0x334B + GDS_OA_CGPG_RESTORE :TGDS_OA_CGPG_RESTORE; // 0x334C + GDS_CS_CTXSW_STATUS :TGDS_CS_CTXSW_STATUS; // 0x334D + GDS_CS_CTXSW_CNT0 :TGDS_CS_CTXSW_CNT0; // 0x334E + GDS_CS_CTXSW_CNT1 :TGDS_CS_CTXSW_CNT1; // 0x334F + GDS_CS_CTXSW_CNT2 :TGDS_CS_CTXSW_CNT2; // 0x3350 + GDS_CS_CTXSW_CNT3 :TGDS_CS_CTXSW_CNT3; // 0x3351 + GDS_GFX_CTXSW_STATUS :TGDS_GFX_CTXSW_STATUS; // 0x3352 + GDS_VS_CTXSW_CNT0 :TGDS_VS_CTXSW_CNT0; // 0x3353 + GDS_VS_CTXSW_CNT1 :TGDS_VS_CTXSW_CNT1; // 0x3354 + GDS_VS_CTXSW_CNT2 :TGDS_VS_CTXSW_CNT2; // 0x3355 + GDS_VS_CTXSW_CNT3 :TGDS_VS_CTXSW_CNT3; // 0x3356 + GDS_PS0_CTXSW_CNT0 :TGDS_PS0_CTXSW_CNT0; // 0x3357 + GDS_PS0_CTXSW_CNT1 :TGDS_PS0_CTXSW_CNT1; // 0x3358 + GDS_PS0_CTXSW_CNT2 :TGDS_PS0_CTXSW_CNT2; // 0x3359 + GDS_PS0_CTXSW_CNT3 :TGDS_PS0_CTXSW_CNT3; // 0x335A + GDS_PS1_CTXSW_CNT0 :TGDS_PS1_CTXSW_CNT0; // 0x335B + GDS_PS1_CTXSW_CNT1 :TGDS_PS1_CTXSW_CNT1; // 0x335C + GDS_PS1_CTXSW_CNT2 :TGDS_PS1_CTXSW_CNT2; // 0x335D + GDS_PS1_CTXSW_CNT3 :TGDS_PS1_CTXSW_CNT3; // 0x335E + GDS_PS2_CTXSW_CNT0 :TGDS_PS2_CTXSW_CNT0; // 0x335F + GDS_PS2_CTXSW_CNT1 :TGDS_PS2_CTXSW_CNT1; // 0x3360 + GDS_PS2_CTXSW_CNT2 :TGDS_PS2_CTXSW_CNT2; // 0x3361 + GDS_PS2_CTXSW_CNT3 :TGDS_PS2_CTXSW_CNT3; // 0x3362 + GDS_PS3_CTXSW_CNT0 :TGDS_PS3_CTXSW_CNT0; // 0x3363 + GDS_PS3_CTXSW_CNT1 :TGDS_PS3_CTXSW_CNT1; // 0x3364 + GDS_PS3_CTXSW_CNT2 :TGDS_PS3_CTXSW_CNT2; // 0x3365 + GDS_PS3_CTXSW_CNT3 :TGDS_PS3_CTXSW_CNT3; // 0x3366 + GDS_PS4_CTXSW_CNT0 :TGDS_PS4_CTXSW_CNT0; // 0x3367 + GDS_PS4_CTXSW_CNT1 :TGDS_PS4_CTXSW_CNT1; // 0x3368 + GDS_PS4_CTXSW_CNT2 :TGDS_PS4_CTXSW_CNT2; // 0x3369 + GDS_PS4_CTXSW_CNT3 :TGDS_PS4_CTXSW_CNT3; // 0x336A + GDS_PS5_CTXSW_CNT0 :TGDS_PS5_CTXSW_CNT0; // 0x336B + GDS_PS5_CTXSW_CNT1 :TGDS_PS5_CTXSW_CNT1; // 0x336C + GDS_PS5_CTXSW_CNT2 :TGDS_PS5_CTXSW_CNT2; // 0x336D + GDS_PS5_CTXSW_CNT3 :TGDS_PS5_CTXSW_CNT3; // 0x336E + GDS_PS6_CTXSW_CNT0 :TGDS_PS6_CTXSW_CNT0; // 0x336F + GDS_PS6_CTXSW_CNT1 :TGDS_PS6_CTXSW_CNT1; // 0x3370 + GDS_PS6_CTXSW_CNT2 :TGDS_PS6_CTXSW_CNT2; // 0x3371 + GDS_PS6_CTXSW_CNT3 :TGDS_PS6_CTXSW_CNT3; // 0x3372 + GDS_PS7_CTXSW_CNT0 :TGDS_PS7_CTXSW_CNT0; // 0x3373 + GDS_PS7_CTXSW_CNT1 :TGDS_PS7_CTXSW_CNT1; // 0x3374 + GDS_PS7_CTXSW_CNT2 :TGDS_PS7_CTXSW_CNT2; // 0x3375 + GDS_PS7_CTXSW_CNT3 :TGDS_PS7_CTXSW_CNT3; // 0x3376 + REG_3377_337F :array[0..8] of DWORD; // 0x3377 + RAS_SIGNATURE_CONTROL :TRAS_SIGNATURE_CONTROL; // 0x3380 + RAS_SIGNATURE_MASK :TRAS_SIGNATURE_MASK; // 0x3381 + RAS_SX_SIGNATURE0 :TRAS_SX_SIGNATURE0; // 0x3382 + RAS_SX_SIGNATURE1 :TRAS_SX_SIGNATURE1; // 0x3383 + RAS_SX_SIGNATURE2 :TRAS_SX_SIGNATURE2; // 0x3384 + RAS_SX_SIGNATURE3 :TRAS_SX_SIGNATURE3; // 0x3385 + REG_3386_338A :array[0..4] of DWORD; // 0x3386 + RAS_DB_SIGNATURE0 :TRAS_DB_SIGNATURE0; // 0x338B + RAS_PA_SIGNATURE0 :TRAS_PA_SIGNATURE0; // 0x338C + RAS_VGT_SIGNATURE0 :TRAS_VGT_SIGNATURE0; // 0x338D + RAS_SQ_SIGNATURE0 :TRAS_SQ_SIGNATURE0; // 0x338E + RAS_SC_SIGNATURE0 :TRAS_SC_SIGNATURE0; // 0x338F + RAS_SC_SIGNATURE1 :TRAS_SC_SIGNATURE1; // 0x3390 + RAS_SC_SIGNATURE2 :TRAS_SC_SIGNATURE2; // 0x3391 + RAS_SC_SIGNATURE3 :TRAS_SC_SIGNATURE3; // 0x3392 + RAS_SC_SIGNATURE4 :TRAS_SC_SIGNATURE4; // 0x3393 + RAS_SC_SIGNATURE5 :TRAS_SC_SIGNATURE5; // 0x3394 + RAS_SC_SIGNATURE6 :TRAS_SC_SIGNATURE6; // 0x3395 + RAS_SC_SIGNATURE7 :TRAS_SC_SIGNATURE7; // 0x3396 + RAS_IA_SIGNATURE0 :TRAS_IA_SIGNATURE0; // 0x3397 + RAS_IA_SIGNATURE1 :TRAS_IA_SIGNATURE1; // 0x3398 + RAS_SPI_SIGNATURE0 :TRAS_SPI_SIGNATURE0; // 0x3399 + RAS_SPI_SIGNATURE1 :TRAS_SPI_SIGNATURE1; // 0x339A + RAS_TA_SIGNATURE0 :TRAS_TA_SIGNATURE0; // 0x339B + RAS_TD_SIGNATURE0 :TRAS_TD_SIGNATURE0; // 0x339C + RAS_CB_SIGNATURE0 :TRAS_CB_SIGNATURE0; // 0x339D + RAS_BCI_SIGNATURE0 :TRAS_BCI_SIGNATURE0; // 0x339E + RAS_BCI_SIGNATURE1 :TRAS_BCI_SIGNATURE1; // 0x339F + RAS_TA_SIGNATURE1 :TRAS_TA_SIGNATURE1; // 0x33A0 + REG_33A1_33FF :array[0..94] of DWORD; // 0x33A1 + SDMA0_UCODE_ADDR :TSDMA0_UCODE_ADDR; // 0x3400 + SDMA0_UCODE_DATA :TSDMA0_UCODE_DATA; // 0x3401 + SDMA0_POWER_CNTL :TSDMA0_POWER_CNTL; // 0x3402 + SDMA0_CLK_CTRL :TSDMA0_CLK_CTRL; // 0x3403 + SDMA0_CNTL :TSDMA0_CNTL; // 0x3404 + SDMA0_CHICKEN_BITS :TSDMA0_CHICKEN_BITS; // 0x3405 + SDMA0_TILING_CONFIG :TSDMA0_TILING_CONFIG; // 0x3406 + SDMA0_HASH :TSDMA0_HASH; // 0x3407 + REG_3408 :DWORD; // 0x3408 + SDMA0_SEM_WAIT_FAIL_TIMER_CNTL :TSDMA0_SEM_WAIT_FAIL_TIMER_CNTL; // 0x3409 + SDMA0_RB_RPTR_FETCH :TSDMA0_RB_RPTR_FETCH; // 0x340A + SDMA0_IB_OFFSET_FETCH :TSDMA0_IB_OFFSET_FETCH; // 0x340B + SDMA0_PROGRAM :TSDMA0_PROGRAM; // 0x340C + SDMA0_STATUS_REG :TSDMA0_STATUS_REG; // 0x340D + SDMA0_STATUS1_REG :TSDMA0_STATUS1_REG; // 0x340E + SDMA0_RD_BURST_CNTL :TSDMA0_RD_BURST_CNTL; // 0x340F + REG_3410_3411 :array[0..1] of DWORD; // 0x3410 + SDMA0_F32_CNTL :TSDMA0_F32_CNTL; // 0x3412 + SDMA0_FREEZE :TSDMA0_FREEZE; // 0x3413 + SDMA0_PHASE0_QUANTUM :TSDMA0_PHASE0_QUANTUM; // 0x3414 + SDMA0_PHASE1_QUANTUM :TSDMA0_PHASE1_QUANTUM; // 0x3415 + SDMA_POWER_GATING :TSDMA_POWER_GATING; // 0x3416 + SDMA_PGFSM_CONFIG :TSDMA_PGFSM_CONFIG; // 0x3417 + SDMA_PGFSM_WRITE :TSDMA_PGFSM_WRITE; // 0x3418 + SDMA_PGFSM_READ :TSDMA_PGFSM_READ; // 0x3419 + SDMA0_EDC_CONFIG :TSDMA0_EDC_CONFIG; // 0x341A + SDMA0_VM_CNTL :TSDMA0_VM_CNTL; // 0x341B + SDMA0_VM_CTX_LO :TSDMA0_VM_CTX_LO; // 0x341C + SDMA0_VM_CTX_HI :TSDMA0_VM_CTX_HI; // 0x341D + SDMA0_STATUS2_REG :TSDMA0_STATUS2_REG; // 0x341E + SDMA0_ACTIVE_FCN_ID :TSDMA0_ACTIVE_FCN_ID; // 0x341F + SDMA0_VM_CTX_CNTL :TSDMA0_VM_CTX_CNTL; // 0x3420 + SDMA0_VIRT_RESET_REQ :TSDMA0_VIRT_RESET_REQ; // 0x3421 + REG_3422_3429 :array[0..7] of DWORD; // 0x3422 + SDMA0_VF_ENABLE :TSDMA0_VF_ENABLE; // 0x342A + SDMA0_BA_THRESHOLD :TSDMA0_BA_THRESHOLD; // 0x342B + SDMA0_ID :TSDMA0_ID; // 0x342C + SDMA0_VERSION :TSDMA0_VERSION; // 0x342D + SDMA0_ATOMIC_CNTL :TSDMA0_ATOMIC_CNTL; // 0x342E + SDMA0_ATOMIC_PREOP_LO :TSDMA0_ATOMIC_PREOP_LO; // 0x342F + SDMA0_ATOMIC_PREOP_HI :TSDMA0_ATOMIC_PREOP_HI; // 0x3430 + REG_3431_3476 :array[0..69] of DWORD; // 0x3431 + SDMA0_PERF_REG_TYPE0 :TSDMA0_PERF_REG_TYPE0; // 0x3477 + SDMA0_CONTEXT_REG_TYPE0 :TSDMA0_CONTEXT_REG_TYPE0; // 0x3478 + SDMA0_CONTEXT_REG_TYPE1 :TSDMA0_CONTEXT_REG_TYPE1; // 0x3479 + SDMA0_CONTEXT_REG_TYPE2 :TSDMA0_CONTEXT_REG_TYPE2; // 0x347A + REG_347B :DWORD; // 0x347B + SDMA0_PUB_REG_TYPE0 :TSDMA0_PUB_REG_TYPE0; // 0x347C + SDMA0_PUB_REG_TYPE1 :TSDMA0_PUB_REG_TYPE1; // 0x347D + REG_347E_347F :array[0..1] of DWORD; // 0x347E + SDMA0_GFX_RB_CNTL :TSDMA0_GFX_RB_CNTL; // 0x3480 + SDMA0_GFX_RB_BASE :TSDMA0_GFX_RB_BASE; // 0x3481 + SDMA0_GFX_RB_BASE_HI :TSDMA0_GFX_RB_BASE_HI; // 0x3482 + SDMA0_GFX_RB_RPTR :TSDMA0_GFX_RB_RPTR; // 0x3483 + SDMA0_GFX_RB_WPTR :TSDMA0_GFX_RB_WPTR; // 0x3484 + SDMA0_GFX_RB_WPTR_POLL_CNTL :TSDMA0_GFX_RB_WPTR_POLL_CNTL; // 0x3485 + SDMA0_GFX_RB_WPTR_POLL_ADDR_HI :TSDMA0_GFX_RB_WPTR_POLL_ADDR_HI; // 0x3486 + SDMA0_GFX_RB_WPTR_POLL_ADDR_LO :TSDMA0_GFX_RB_WPTR_POLL_ADDR_LO; // 0x3487 + SDMA0_GFX_RB_RPTR_ADDR_HI :TSDMA0_GFX_RB_RPTR_ADDR_HI; // 0x3488 + SDMA0_GFX_RB_RPTR_ADDR_LO :TSDMA0_GFX_RB_RPTR_ADDR_LO; // 0x3489 + SDMA0_GFX_IB_CNTL :TSDMA0_GFX_IB_CNTL; // 0x348A + SDMA0_GFX_IB_RPTR :TSDMA0_GFX_IB_RPTR; // 0x348B + SDMA0_GFX_IB_OFFSET :TSDMA0_GFX_IB_OFFSET; // 0x348C + SDMA0_GFX_IB_BASE_LO :TSDMA0_GFX_IB_BASE_LO; // 0x348D + SDMA0_GFX_IB_BASE_HI :TSDMA0_GFX_IB_BASE_HI; // 0x348E + SDMA0_GFX_IB_SIZE :TSDMA0_GFX_IB_SIZE; // 0x348F + SDMA0_GFX_SKIP_CNTL :TSDMA0_GFX_SKIP_CNTL; // 0x3490 + SDMA0_GFX_CONTEXT_STATUS :TSDMA0_GFX_CONTEXT_STATUS; // 0x3491 + SDMA0_GFX_DOORBELL :TSDMA0_GFX_DOORBELL; // 0x3492 + SDMA0_GFX_CONTEXT_CNTL :TSDMA0_GFX_CONTEXT_CNTL; // 0x3493 + REG_3494_34A6 :array[0..18] of DWORD; // 0x3494 + SDMA0_GFX_VIRTUAL_ADDR :TSDMA0_GFX_VIRTUAL_ADDR; // 0x34A7 + SDMA0_GFX_APE1_CNTL :TSDMA0_GFX_APE1_CNTL; // 0x34A8 + SDMA0_GFX_DOORBELL_LOG :TSDMA0_GFX_DOORBELL_LOG; // 0x34A9 + SDMA0_GFX_WATERMARK :TSDMA0_GFX_WATERMARK; // 0x34AA + REG_34AB :DWORD; // 0x34AB + SDMA0_GFX_CSA_ADDR_LO :TSDMA0_GFX_CSA_ADDR_LO; // 0x34AC + SDMA0_GFX_CSA_ADDR_HI :TSDMA0_GFX_CSA_ADDR_HI; // 0x34AD + REG_34AE :DWORD; // 0x34AE + SDMA0_GFX_IB_SUB_REMAIN :TSDMA0_GFX_IB_SUB_REMAIN; // 0x34AF + SDMA0_GFX_PREEMPT :TSDMA0_GFX_PREEMPT; // 0x34B0 + SDMA0_GFX_DUMMY_REG :TSDMA0_GFX_DUMMY_REG; // 0x34B1 + REG_34B2_34C0 :array[0..14] of DWORD; // 0x34B2 + SDMA0_GFX_MIDCMD_DATA0 :TSDMA0_GFX_MIDCMD_DATA0; // 0x34C1 + SDMA0_GFX_MIDCMD_DATA1 :TSDMA0_GFX_MIDCMD_DATA1; // 0x34C2 + SDMA0_GFX_MIDCMD_DATA2 :TSDMA0_GFX_MIDCMD_DATA2; // 0x34C3 + SDMA0_GFX_MIDCMD_DATA3 :TSDMA0_GFX_MIDCMD_DATA3; // 0x34C4 + SDMA0_GFX_MIDCMD_DATA4 :TSDMA0_GFX_MIDCMD_DATA4; // 0x34C5 + SDMA0_GFX_MIDCMD_DATA5 :TSDMA0_GFX_MIDCMD_DATA5; // 0x34C6 + SDMA0_GFX_MIDCMD_CNTL :TSDMA0_GFX_MIDCMD_CNTL; // 0x34C7 + REG_34C8_34FF :array[0..55] of DWORD; // 0x34C8 + SDMA0_RLC0_RB_CNTL :TSDMA0_RLC0_RB_CNTL; // 0x3500 + SDMA0_RLC0_RB_BASE :TSDMA0_RLC0_RB_BASE; // 0x3501 + SDMA0_RLC0_RB_BASE_HI :TSDMA0_RLC0_RB_BASE_HI; // 0x3502 + SDMA0_RLC0_RB_RPTR :TSDMA0_RLC0_RB_RPTR; // 0x3503 + SDMA0_RLC0_RB_WPTR :TSDMA0_RLC0_RB_WPTR; // 0x3504 + SDMA0_RLC0_RB_WPTR_POLL_CNTL :TSDMA0_RLC0_RB_WPTR_POLL_CNTL; // 0x3505 + SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI :TSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI; // 0x3506 + SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO :TSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO; // 0x3507 + SDMA0_RLC0_RB_RPTR_ADDR_HI :TSDMA0_RLC0_RB_RPTR_ADDR_HI; // 0x3508 + SDMA0_RLC0_RB_RPTR_ADDR_LO :TSDMA0_RLC0_RB_RPTR_ADDR_LO; // 0x3509 + SDMA0_RLC0_IB_CNTL :TSDMA0_RLC0_IB_CNTL; // 0x350A + SDMA0_RLC0_IB_RPTR :TSDMA0_RLC0_IB_RPTR; // 0x350B + SDMA0_RLC0_IB_OFFSET :TSDMA0_RLC0_IB_OFFSET; // 0x350C + SDMA0_RLC0_IB_BASE_LO :TSDMA0_RLC0_IB_BASE_LO; // 0x350D + SDMA0_RLC0_IB_BASE_HI :TSDMA0_RLC0_IB_BASE_HI; // 0x350E + SDMA0_RLC0_IB_SIZE :TSDMA0_RLC0_IB_SIZE; // 0x350F + SDMA0_RLC0_SKIP_CNTL :TSDMA0_RLC0_SKIP_CNTL; // 0x3510 + SDMA0_RLC0_CONTEXT_STATUS :TSDMA0_RLC0_CONTEXT_STATUS; // 0x3511 + SDMA0_RLC0_DOORBELL :TSDMA0_RLC0_DOORBELL; // 0x3512 + REG_3513_3526 :array[0..19] of DWORD; // 0x3513 + SDMA0_RLC0_VIRTUAL_ADDR :TSDMA0_RLC0_VIRTUAL_ADDR; // 0x3527 + SDMA0_RLC0_APE1_CNTL :TSDMA0_RLC0_APE1_CNTL; // 0x3528 + SDMA0_RLC0_DOORBELL_LOG :TSDMA0_RLC0_DOORBELL_LOG; // 0x3529 + SDMA0_RLC0_WATERMARK :TSDMA0_RLC0_WATERMARK; // 0x352A + REG_352B :DWORD; // 0x352B + SDMA0_RLC0_CSA_ADDR_LO :TSDMA0_RLC0_CSA_ADDR_LO; // 0x352C + SDMA0_RLC0_CSA_ADDR_HI :TSDMA0_RLC0_CSA_ADDR_HI; // 0x352D + REG_352E :DWORD; // 0x352E + SDMA0_RLC0_IB_SUB_REMAIN :TSDMA0_RLC0_IB_SUB_REMAIN; // 0x352F + SDMA0_RLC0_PREEMPT :TSDMA0_RLC0_PREEMPT; // 0x3530 + SDMA0_RLC0_DUMMY_REG :TSDMA0_RLC0_DUMMY_REG; // 0x3531 + REG_3532_3540 :array[0..14] of DWORD; // 0x3532 + SDMA0_RLC0_MIDCMD_DATA0 :TSDMA0_RLC0_MIDCMD_DATA0; // 0x3541 + SDMA0_RLC0_MIDCMD_DATA1 :TSDMA0_RLC0_MIDCMD_DATA1; // 0x3542 + SDMA0_RLC0_MIDCMD_DATA2 :TSDMA0_RLC0_MIDCMD_DATA2; // 0x3543 + SDMA0_RLC0_MIDCMD_DATA3 :TSDMA0_RLC0_MIDCMD_DATA3; // 0x3544 + SDMA0_RLC0_MIDCMD_DATA4 :TSDMA0_RLC0_MIDCMD_DATA4; // 0x3545 + SDMA0_RLC0_MIDCMD_DATA5 :TSDMA0_RLC0_MIDCMD_DATA5; // 0x3546 + SDMA0_RLC0_MIDCMD_CNTL :TSDMA0_RLC0_MIDCMD_CNTL; // 0x3547 + REG_3548_357F :array[0..55] of DWORD; // 0x3548 + SDMA0_RLC1_RB_CNTL :TSDMA0_RLC1_RB_CNTL; // 0x3580 + SDMA0_RLC1_RB_BASE :TSDMA0_RLC1_RB_BASE; // 0x3581 + SDMA0_RLC1_RB_BASE_HI :TSDMA0_RLC1_RB_BASE_HI; // 0x3582 + SDMA0_RLC1_RB_RPTR :TSDMA0_RLC1_RB_RPTR; // 0x3583 + SDMA0_RLC1_RB_WPTR :TSDMA0_RLC1_RB_WPTR; // 0x3584 + SDMA0_RLC1_RB_WPTR_POLL_CNTL :TSDMA0_RLC1_RB_WPTR_POLL_CNTL; // 0x3585 + SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI :TSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI; // 0x3586 + SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO :TSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO; // 0x3587 + SDMA0_RLC1_RB_RPTR_ADDR_HI :TSDMA0_RLC1_RB_RPTR_ADDR_HI; // 0x3588 + SDMA0_RLC1_RB_RPTR_ADDR_LO :TSDMA0_RLC1_RB_RPTR_ADDR_LO; // 0x3589 + SDMA0_RLC1_IB_CNTL :TSDMA0_RLC1_IB_CNTL; // 0x358A + SDMA0_RLC1_IB_RPTR :TSDMA0_RLC1_IB_RPTR; // 0x358B + SDMA0_RLC1_IB_OFFSET :TSDMA0_RLC1_IB_OFFSET; // 0x358C + SDMA0_RLC1_IB_BASE_LO :TSDMA0_RLC1_IB_BASE_LO; // 0x358D + SDMA0_RLC1_IB_BASE_HI :TSDMA0_RLC1_IB_BASE_HI; // 0x358E + SDMA0_RLC1_IB_SIZE :TSDMA0_RLC1_IB_SIZE; // 0x358F + SDMA0_RLC1_SKIP_CNTL :TSDMA0_RLC1_SKIP_CNTL; // 0x3590 + SDMA0_RLC1_CONTEXT_STATUS :TSDMA0_RLC1_CONTEXT_STATUS; // 0x3591 + SDMA0_RLC1_DOORBELL :TSDMA0_RLC1_DOORBELL; // 0x3592 + REG_3593_35A6 :array[0..19] of DWORD; // 0x3593 + SDMA0_RLC1_VIRTUAL_ADDR :TSDMA0_RLC1_VIRTUAL_ADDR; // 0x35A7 + SDMA0_RLC1_APE1_CNTL :TSDMA0_RLC1_APE1_CNTL; // 0x35A8 + SDMA0_RLC1_DOORBELL_LOG :TSDMA0_RLC1_DOORBELL_LOG; // 0x35A9 + SDMA0_RLC1_WATERMARK :TSDMA0_RLC1_WATERMARK; // 0x35AA + REG_35AB :DWORD; // 0x35AB + SDMA0_RLC1_CSA_ADDR_LO :TSDMA0_RLC1_CSA_ADDR_LO; // 0x35AC + SDMA0_RLC1_CSA_ADDR_HI :TSDMA0_RLC1_CSA_ADDR_HI; // 0x35AD + REG_35AE :DWORD; // 0x35AE + SDMA0_RLC1_IB_SUB_REMAIN :TSDMA0_RLC1_IB_SUB_REMAIN; // 0x35AF + SDMA0_RLC1_PREEMPT :TSDMA0_RLC1_PREEMPT; // 0x35B0 + SDMA0_RLC1_DUMMY_REG :TSDMA0_RLC1_DUMMY_REG; // 0x35B1 + REG_35B2_35C0 :array[0..14] of DWORD; // 0x35B2 + SDMA0_RLC1_MIDCMD_DATA0 :TSDMA0_RLC1_MIDCMD_DATA0; // 0x35C1 + SDMA0_RLC1_MIDCMD_DATA1 :TSDMA0_RLC1_MIDCMD_DATA1; // 0x35C2 + SDMA0_RLC1_MIDCMD_DATA2 :TSDMA0_RLC1_MIDCMD_DATA2; // 0x35C3 + SDMA0_RLC1_MIDCMD_DATA3 :TSDMA0_RLC1_MIDCMD_DATA3; // 0x35C4 + SDMA0_RLC1_MIDCMD_DATA4 :TSDMA0_RLC1_MIDCMD_DATA4; // 0x35C5 + SDMA0_RLC1_MIDCMD_DATA5 :TSDMA0_RLC1_MIDCMD_DATA5; // 0x35C6 + SDMA0_RLC1_MIDCMD_CNTL :TSDMA0_RLC1_MIDCMD_CNTL; // 0x35C7 + REG_35C8_35FF :array[0..55] of DWORD; // 0x35C8 + SDMA1_UCODE_ADDR :TSDMA1_UCODE_ADDR; // 0x3600 + SDMA1_UCODE_DATA :TSDMA1_UCODE_DATA; // 0x3601 + SDMA1_POWER_CNTL :TSDMA1_POWER_CNTL; // 0x3602 + SDMA1_CLK_CTRL :TSDMA1_CLK_CTRL; // 0x3603 + SDMA1_CNTL :TSDMA1_CNTL; // 0x3604 + SDMA1_CHICKEN_BITS :TSDMA1_CHICKEN_BITS; // 0x3605 + SDMA1_TILING_CONFIG :TSDMA1_TILING_CONFIG; // 0x3606 + SDMA1_HASH :TSDMA1_HASH; // 0x3607 + REG_3608 :DWORD; // 0x3608 + SDMA1_SEM_WAIT_FAIL_TIMER_CNTL :TSDMA1_SEM_WAIT_FAIL_TIMER_CNTL; // 0x3609 + SDMA1_RB_RPTR_FETCH :TSDMA1_RB_RPTR_FETCH; // 0x360A + SDMA1_IB_OFFSET_FETCH :TSDMA1_IB_OFFSET_FETCH; // 0x360B + SDMA1_PROGRAM :TSDMA1_PROGRAM; // 0x360C + SDMA1_STATUS_REG :TSDMA1_STATUS_REG; // 0x360D + SDMA1_STATUS1_REG :TSDMA1_STATUS1_REG; // 0x360E + SDMA1_RD_BURST_CNTL :TSDMA1_RD_BURST_CNTL; // 0x360F + REG_3610_3611 :array[0..1] of DWORD; // 0x3610 + SDMA1_F32_CNTL :TSDMA1_F32_CNTL; // 0x3612 + SDMA1_FREEZE :TSDMA1_FREEZE; // 0x3613 + SDMA1_PHASE0_QUANTUM :TSDMA1_PHASE0_QUANTUM; // 0x3614 + SDMA1_PHASE1_QUANTUM :TSDMA1_PHASE1_QUANTUM; // 0x3615 + REG_3616_3619 :array[0..3] of DWORD; // 0x3616 + SDMA1_EDC_CONFIG :TSDMA1_EDC_CONFIG; // 0x361A + SDMA1_VM_CNTL :TSDMA1_VM_CNTL; // 0x361B + SDMA1_VM_CTX_LO :TSDMA1_VM_CTX_LO; // 0x361C + SDMA1_VM_CTX_HI :TSDMA1_VM_CTX_HI; // 0x361D + SDMA1_STATUS2_REG :TSDMA1_STATUS2_REG; // 0x361E + SDMA1_ACTIVE_FCN_ID :TSDMA1_ACTIVE_FCN_ID; // 0x361F + SDMA1_VM_CTX_CNTL :TSDMA1_VM_CTX_CNTL; // 0x3620 + SDMA1_VIRT_RESET_REQ :TSDMA1_VIRT_RESET_REQ; // 0x3621 + REG_3622_3629 :array[0..7] of DWORD; // 0x3622 + SDMA1_VF_ENABLE :TSDMA1_VF_ENABLE; // 0x362A + SDMA1_BA_THRESHOLD :TSDMA1_BA_THRESHOLD; // 0x362B + SDMA1_ID :TSDMA1_ID; // 0x362C + SDMA1_VERSION :TSDMA1_VERSION; // 0x362D + SDMA1_ATOMIC_CNTL :TSDMA1_ATOMIC_CNTL; // 0x362E + SDMA1_ATOMIC_PREOP_LO :TSDMA1_ATOMIC_PREOP_LO; // 0x362F + SDMA1_ATOMIC_PREOP_HI :TSDMA1_ATOMIC_PREOP_HI; // 0x3630 + REG_3631_3676 :array[0..69] of DWORD; // 0x3631 + SDMA1_PERF_REG_TYPE0 :TSDMA1_PERF_REG_TYPE0; // 0x3677 + SDMA1_CONTEXT_REG_TYPE0 :TSDMA1_CONTEXT_REG_TYPE0; // 0x3678 + SDMA1_CONTEXT_REG_TYPE1 :TSDMA1_CONTEXT_REG_TYPE1; // 0x3679 + SDMA1_CONTEXT_REG_TYPE2 :TSDMA1_CONTEXT_REG_TYPE2; // 0x367A + REG_367B :DWORD; // 0x367B + SDMA1_PUB_REG_TYPE0 :TSDMA1_PUB_REG_TYPE0; // 0x367C + SDMA1_PUB_REG_TYPE1 :TSDMA1_PUB_REG_TYPE1; // 0x367D + REG_367E_367F :array[0..1] of DWORD; // 0x367E + SDMA1_GFX_RB_CNTL :TSDMA1_GFX_RB_CNTL; // 0x3680 + SDMA1_GFX_RB_BASE :TSDMA1_GFX_RB_BASE; // 0x3681 + SDMA1_GFX_RB_BASE_HI :TSDMA1_GFX_RB_BASE_HI; // 0x3682 + SDMA1_GFX_RB_RPTR :TSDMA1_GFX_RB_RPTR; // 0x3683 + SDMA1_GFX_RB_WPTR :TSDMA1_GFX_RB_WPTR; // 0x3684 + SDMA1_GFX_RB_WPTR_POLL_CNTL :TSDMA1_GFX_RB_WPTR_POLL_CNTL; // 0x3685 + SDMA1_GFX_RB_WPTR_POLL_ADDR_HI :TSDMA1_GFX_RB_WPTR_POLL_ADDR_HI; // 0x3686 + SDMA1_GFX_RB_WPTR_POLL_ADDR_LO :TSDMA1_GFX_RB_WPTR_POLL_ADDR_LO; // 0x3687 + SDMA1_GFX_RB_RPTR_ADDR_HI :TSDMA1_GFX_RB_RPTR_ADDR_HI; // 0x3688 + SDMA1_GFX_RB_RPTR_ADDR_LO :TSDMA1_GFX_RB_RPTR_ADDR_LO; // 0x3689 + SDMA1_GFX_IB_CNTL :TSDMA1_GFX_IB_CNTL; // 0x368A + SDMA1_GFX_IB_RPTR :TSDMA1_GFX_IB_RPTR; // 0x368B + SDMA1_GFX_IB_OFFSET :TSDMA1_GFX_IB_OFFSET; // 0x368C + SDMA1_GFX_IB_BASE_LO :TSDMA1_GFX_IB_BASE_LO; // 0x368D + SDMA1_GFX_IB_BASE_HI :TSDMA1_GFX_IB_BASE_HI; // 0x368E + SDMA1_GFX_IB_SIZE :TSDMA1_GFX_IB_SIZE; // 0x368F + SDMA1_GFX_SKIP_CNTL :TSDMA1_GFX_SKIP_CNTL; // 0x3690 + SDMA1_GFX_CONTEXT_STATUS :TSDMA1_GFX_CONTEXT_STATUS; // 0x3691 + SDMA1_GFX_DOORBELL :TSDMA1_GFX_DOORBELL; // 0x3692 + SDMA1_GFX_CONTEXT_CNTL :TSDMA1_GFX_CONTEXT_CNTL; // 0x3693 + REG_3694_36A6 :array[0..18] of DWORD; // 0x3694 + SDMA1_GFX_VIRTUAL_ADDR :TSDMA1_GFX_VIRTUAL_ADDR; // 0x36A7 + SDMA1_GFX_APE1_CNTL :TSDMA1_GFX_APE1_CNTL; // 0x36A8 + SDMA1_GFX_DOORBELL_LOG :TSDMA1_GFX_DOORBELL_LOG; // 0x36A9 + SDMA1_GFX_WATERMARK :TSDMA1_GFX_WATERMARK; // 0x36AA + REG_36AB :DWORD; // 0x36AB + SDMA1_GFX_CSA_ADDR_LO :TSDMA1_GFX_CSA_ADDR_LO; // 0x36AC + SDMA1_GFX_CSA_ADDR_HI :TSDMA1_GFX_CSA_ADDR_HI; // 0x36AD + REG_36AE :DWORD; // 0x36AE + SDMA1_GFX_IB_SUB_REMAIN :TSDMA1_GFX_IB_SUB_REMAIN; // 0x36AF + SDMA1_GFX_PREEMPT :TSDMA1_GFX_PREEMPT; // 0x36B0 + SDMA1_GFX_DUMMY_REG :TSDMA1_GFX_DUMMY_REG; // 0x36B1 + REG_36B2_36C0 :array[0..14] of DWORD; // 0x36B2 + SDMA1_GFX_MIDCMD_DATA0 :TSDMA1_GFX_MIDCMD_DATA0; // 0x36C1 + SDMA1_GFX_MIDCMD_DATA1 :TSDMA1_GFX_MIDCMD_DATA1; // 0x36C2 + SDMA1_GFX_MIDCMD_DATA2 :TSDMA1_GFX_MIDCMD_DATA2; // 0x36C3 + SDMA1_GFX_MIDCMD_DATA3 :TSDMA1_GFX_MIDCMD_DATA3; // 0x36C4 + SDMA1_GFX_MIDCMD_DATA4 :TSDMA1_GFX_MIDCMD_DATA4; // 0x36C5 + SDMA1_GFX_MIDCMD_DATA5 :TSDMA1_GFX_MIDCMD_DATA5; // 0x36C6 + SDMA1_GFX_MIDCMD_CNTL :TSDMA1_GFX_MIDCMD_CNTL; // 0x36C7 + REG_36C8_36FF :array[0..55] of DWORD; // 0x36C8 + SDMA1_RLC0_RB_CNTL :TSDMA1_RLC0_RB_CNTL; // 0x3700 + SDMA1_RLC0_RB_BASE :TSDMA1_RLC0_RB_BASE; // 0x3701 + SDMA1_RLC0_RB_BASE_HI :TSDMA1_RLC0_RB_BASE_HI; // 0x3702 + SDMA1_RLC0_RB_RPTR :TSDMA1_RLC0_RB_RPTR; // 0x3703 + SDMA1_RLC0_RB_WPTR :TSDMA1_RLC0_RB_WPTR; // 0x3704 + SDMA1_RLC0_RB_WPTR_POLL_CNTL :TSDMA1_RLC0_RB_WPTR_POLL_CNTL; // 0x3705 + SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI :TSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI; // 0x3706 + SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO :TSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO; // 0x3707 + SDMA1_RLC0_RB_RPTR_ADDR_HI :TSDMA1_RLC0_RB_RPTR_ADDR_HI; // 0x3708 + SDMA1_RLC0_RB_RPTR_ADDR_LO :TSDMA1_RLC0_RB_RPTR_ADDR_LO; // 0x3709 + SDMA1_RLC0_IB_CNTL :TSDMA1_RLC0_IB_CNTL; // 0x370A + SDMA1_RLC0_IB_RPTR :TSDMA1_RLC0_IB_RPTR; // 0x370B + SDMA1_RLC0_IB_OFFSET :TSDMA1_RLC0_IB_OFFSET; // 0x370C + SDMA1_RLC0_IB_BASE_LO :TSDMA1_RLC0_IB_BASE_LO; // 0x370D + SDMA1_RLC0_IB_BASE_HI :TSDMA1_RLC0_IB_BASE_HI; // 0x370E + SDMA1_RLC0_IB_SIZE :TSDMA1_RLC0_IB_SIZE; // 0x370F + SDMA1_RLC0_SKIP_CNTL :TSDMA1_RLC0_SKIP_CNTL; // 0x3710 + SDMA1_RLC0_CONTEXT_STATUS :TSDMA1_RLC0_CONTEXT_STATUS; // 0x3711 + SDMA1_RLC0_DOORBELL :TSDMA1_RLC0_DOORBELL; // 0x3712 + REG_3713_3726 :array[0..19] of DWORD; // 0x3713 + SDMA1_RLC0_VIRTUAL_ADDR :TSDMA1_RLC0_VIRTUAL_ADDR; // 0x3727 + SDMA1_RLC0_APE1_CNTL :TSDMA1_RLC0_APE1_CNTL; // 0x3728 + SDMA1_RLC0_DOORBELL_LOG :TSDMA1_RLC0_DOORBELL_LOG; // 0x3729 + SDMA1_RLC0_WATERMARK :TSDMA1_RLC0_WATERMARK; // 0x372A + REG_372B :DWORD; // 0x372B + SDMA1_RLC0_CSA_ADDR_LO :TSDMA1_RLC0_CSA_ADDR_LO; // 0x372C + SDMA1_RLC0_CSA_ADDR_HI :TSDMA1_RLC0_CSA_ADDR_HI; // 0x372D + REG_372E :DWORD; // 0x372E + SDMA1_RLC0_IB_SUB_REMAIN :TSDMA1_RLC0_IB_SUB_REMAIN; // 0x372F + SDMA1_RLC0_PREEMPT :TSDMA1_RLC0_PREEMPT; // 0x3730 + SDMA1_RLC0_DUMMY_REG :TSDMA1_RLC0_DUMMY_REG; // 0x3731 + REG_3732_3740 :array[0..14] of DWORD; // 0x3732 + SDMA1_RLC0_MIDCMD_DATA0 :TSDMA1_RLC0_MIDCMD_DATA0; // 0x3741 + SDMA1_RLC0_MIDCMD_DATA1 :TSDMA1_RLC0_MIDCMD_DATA1; // 0x3742 + SDMA1_RLC0_MIDCMD_DATA2 :TSDMA1_RLC0_MIDCMD_DATA2; // 0x3743 + SDMA1_RLC0_MIDCMD_DATA3 :TSDMA1_RLC0_MIDCMD_DATA3; // 0x3744 + SDMA1_RLC0_MIDCMD_DATA4 :TSDMA1_RLC0_MIDCMD_DATA4; // 0x3745 + SDMA1_RLC0_MIDCMD_DATA5 :TSDMA1_RLC0_MIDCMD_DATA5; // 0x3746 + SDMA1_RLC0_MIDCMD_CNTL :TSDMA1_RLC0_MIDCMD_CNTL; // 0x3747 + REG_3748_377F :array[0..55] of DWORD; // 0x3748 + SDMA1_RLC1_RB_CNTL :TSDMA1_RLC1_RB_CNTL; // 0x3780 + SDMA1_RLC1_RB_BASE :TSDMA1_RLC1_RB_BASE; // 0x3781 + SDMA1_RLC1_RB_BASE_HI :TSDMA1_RLC1_RB_BASE_HI; // 0x3782 + SDMA1_RLC1_RB_RPTR :TSDMA1_RLC1_RB_RPTR; // 0x3783 + SDMA1_RLC1_RB_WPTR :TSDMA1_RLC1_RB_WPTR; // 0x3784 + SDMA1_RLC1_RB_WPTR_POLL_CNTL :TSDMA1_RLC1_RB_WPTR_POLL_CNTL; // 0x3785 + SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI :TSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI; // 0x3786 + SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO :TSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO; // 0x3787 + SDMA1_RLC1_RB_RPTR_ADDR_HI :TSDMA1_RLC1_RB_RPTR_ADDR_HI; // 0x3788 + SDMA1_RLC1_RB_RPTR_ADDR_LO :TSDMA1_RLC1_RB_RPTR_ADDR_LO; // 0x3789 + SDMA1_RLC1_IB_CNTL :TSDMA1_RLC1_IB_CNTL; // 0x378A + SDMA1_RLC1_IB_RPTR :TSDMA1_RLC1_IB_RPTR; // 0x378B + SDMA1_RLC1_IB_OFFSET :TSDMA1_RLC1_IB_OFFSET; // 0x378C + SDMA1_RLC1_IB_BASE_LO :TSDMA1_RLC1_IB_BASE_LO; // 0x378D + SDMA1_RLC1_IB_BASE_HI :TSDMA1_RLC1_IB_BASE_HI; // 0x378E + SDMA1_RLC1_IB_SIZE :TSDMA1_RLC1_IB_SIZE; // 0x378F + SDMA1_RLC1_SKIP_CNTL :TSDMA1_RLC1_SKIP_CNTL; // 0x3790 + SDMA1_RLC1_CONTEXT_STATUS :TSDMA1_RLC1_CONTEXT_STATUS; // 0x3791 + SDMA1_RLC1_DOORBELL :TSDMA1_RLC1_DOORBELL; // 0x3792 + REG_3793_37A6 :array[0..19] of DWORD; // 0x3793 + SDMA1_RLC1_VIRTUAL_ADDR :TSDMA1_RLC1_VIRTUAL_ADDR; // 0x37A7 + SDMA1_RLC1_APE1_CNTL :TSDMA1_RLC1_APE1_CNTL; // 0x37A8 + SDMA1_RLC1_DOORBELL_LOG :TSDMA1_RLC1_DOORBELL_LOG; // 0x37A9 + SDMA1_RLC1_WATERMARK :TSDMA1_RLC1_WATERMARK; // 0x37AA + REG_37AB :DWORD; // 0x37AB + SDMA1_RLC1_CSA_ADDR_LO :TSDMA1_RLC1_CSA_ADDR_LO; // 0x37AC + SDMA1_RLC1_CSA_ADDR_HI :TSDMA1_RLC1_CSA_ADDR_HI; // 0x37AD + REG_37AE :DWORD; // 0x37AE + SDMA1_RLC1_IB_SUB_REMAIN :TSDMA1_RLC1_IB_SUB_REMAIN; // 0x37AF + SDMA1_RLC1_PREEMPT :TSDMA1_RLC1_PREEMPT; // 0x37B0 + SDMA1_RLC1_DUMMY_REG :TSDMA1_RLC1_DUMMY_REG; // 0x37B1 + REG_37B2_37C0 :array[0..14] of DWORD; // 0x37B2 + SDMA1_RLC1_MIDCMD_DATA0 :TSDMA1_RLC1_MIDCMD_DATA0; // 0x37C1 + SDMA1_RLC1_MIDCMD_DATA1 :TSDMA1_RLC1_MIDCMD_DATA1; // 0x37C2 + SDMA1_RLC1_MIDCMD_DATA2 :TSDMA1_RLC1_MIDCMD_DATA2; // 0x37C3 + SDMA1_RLC1_MIDCMD_DATA3 :TSDMA1_RLC1_MIDCMD_DATA3; // 0x37C4 + SDMA1_RLC1_MIDCMD_DATA4 :TSDMA1_RLC1_MIDCMD_DATA4; // 0x37C5 + SDMA1_RLC1_MIDCMD_DATA5 :TSDMA1_RLC1_MIDCMD_DATA5; // 0x37C6 + SDMA1_RLC1_MIDCMD_CNTL :TSDMA1_RLC1_MIDCMD_CNTL; // 0x37C7 + REG_37C8_38BF :array[0..247] of DWORD; // 0x37C8 + UVD_PGFSM_CONFIG :TUVD_PGFSM_CONFIG; // 0x38C0 + REG_38C1 :DWORD; // 0x38C1 + UVD_PGFSM_READ_TILE1 :TUVD_PGFSM_READ_TILE1; // 0x38C2 + UVD_PGFSM_READ_TILE2 :TUVD_PGFSM_READ_TILE2; // 0x38C3 + UVD_POWER_STATUS :TUVD_POWER_STATUS; // 0x38C4 + UVD_PGFSM_READ_TILE3 :TUVD_PGFSM_READ_TILE3; // 0x38C5 + UVD_PGFSM_READ_TILE4 :TUVD_PGFSM_READ_TILE4; // 0x38C6 + REG_38C7 :DWORD; // 0x38C7 + UVD_PGFSM_READ_TILE5 :TUVD_PGFSM_READ_TILE5; // 0x38C8 + REG_38C9_38ED :array[0..36] of DWORD; // 0x38C9 + UVD_PGFSM_READ_TILE6 :TUVD_PGFSM_READ_TILE6; // 0x38EE + UVD_PGFSM_READ_TILE7 :TUVD_PGFSM_READ_TILE7; // 0x38EF + REG_38F0_3991 :array[0..161] of DWORD; // 0x38F0 + UVD_MIF_CURR_ADDR_CONFIG :TUVD_MIF_CURR_ADDR_CONFIG; // 0x3992 + UVD_MIF_REF_ADDR_CONFIG :TUVD_MIF_REF_ADDR_CONFIG; // 0x3993 + REG_3994_39C4 :array[0..48] of DWORD; // 0x3994 + UVD_MIF_RECON1_ADDR_CONFIG :TUVD_MIF_RECON1_ADDR_CONFIG; // 0x39C5 + REG_39C6_3A1E :array[0..88] of DWORD; // 0x39C6 + UVD_JPEG_ADDR_CONFIG :TUVD_JPEG_ADDR_CONFIG; // 0x3A1F + REG_3A20_3BBF :array[0..415] of DWORD; // 0x3A20 + UVD_SEMA_ADDR_LOW :TUVD_SEMA_ADDR_LOW; // 0x3BC0 + UVD_SEMA_ADDR_HIGH :TUVD_SEMA_ADDR_HIGH; // 0x3BC1 + UVD_SEMA_CMD :TUVD_SEMA_CMD; // 0x3BC2 + UVD_GPCOM_VCPU_CMD :TUVD_GPCOM_VCPU_CMD; // 0x3BC3 + UVD_GPCOM_VCPU_DATA0 :TUVD_GPCOM_VCPU_DATA0; // 0x3BC4 + UVD_GPCOM_VCPU_DATA1 :TUVD_GPCOM_VCPU_DATA1; // 0x3BC5 + UVD_ENGINE_CNTL :TUVD_ENGINE_CNTL; // 0x3BC6 + REG_3BC7_3BD2 :array[0..11] of DWORD; // 0x3BC7 + UVD_UDEC_ADDR_CONFIG :TUVD_UDEC_ADDR_CONFIG; // 0x3BD3 + UVD_UDEC_DB_ADDR_CONFIG :TUVD_UDEC_DB_ADDR_CONFIG; // 0x3BD4 + UVD_UDEC_DBW_ADDR_CONFIG :TUVD_UDEC_DBW_ADDR_CONFIG; // 0x3BD5 + REG_3BD6_3BE3 :array[0..13] of DWORD; // 0x3BD6 + UVD_SUVD_CGC_GATE :TUVD_SUVD_CGC_GATE; // 0x3BE4 + UVD_SUVD_CGC_STATUS :TUVD_SUVD_CGC_STATUS; // 0x3BE5 + UVD_SUVD_CGC_CTRL :TUVD_SUVD_CGC_CTRL; // 0x3BE6 + REG_3BE7_3C5D :array[0..118] of DWORD; // 0x3BE7 + UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH :TUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH; // 0x3C5E + UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW :TUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW; // 0x3C5F + REG_3C60_3C65 :array[0..5] of DWORD; // 0x3C60 + UVD_LMI_RBC_IB_64BIT_BAR_HIGH :TUVD_LMI_RBC_IB_64BIT_BAR_HIGH; // 0x3C66 + UVD_LMI_RBC_IB_64BIT_BAR_LOW :TUVD_LMI_RBC_IB_64BIT_BAR_LOW; // 0x3C67 + UVD_LMI_RBC_RB_64BIT_BAR_HIGH :TUVD_LMI_RBC_RB_64BIT_BAR_HIGH; // 0x3C68 + UVD_LMI_RBC_RB_64BIT_BAR_LOW :TUVD_LMI_RBC_RB_64BIT_BAR_LOW; // 0x3C69 + REG_3C6A_3CFF :array[0..149] of DWORD; // 0x3C6A + UVD_SEMA_CNTL :TUVD_SEMA_CNTL; // 0x3D00 + REG_3D01_3D25 :array[0..36] of DWORD; // 0x3D01 + UVD_LMI_EXT40_ADDR :TUVD_LMI_EXT40_ADDR; // 0x3D26 + REG_3D27 :DWORD; // 0x3D27 + UVD_CTX_INDEX :TUVD_CTX_INDEX; // 0x3D28 + UVD_CTX_DATA :TUVD_CTX_DATA; // 0x3D29 + UVD_CGC_GATE :TUVD_CGC_GATE; // 0x3D2A + UVD_CGC_STATUS :TUVD_CGC_STATUS; // 0x3D2B + UVD_CGC_CTRL :TUVD_CGC_CTRL; // 0x3D2C + UVD_CGC_UDEC_STATUS :TUVD_CGC_UDEC_STATUS; // 0x3D2D + REG_3D2E_3D3C :array[0..14] of DWORD; // 0x3D2E + UVD_LMI_CTRL2 :TUVD_LMI_CTRL2; // 0x3D3D + REG_3D3E_3D3F :array[0..1] of DWORD; // 0x3D3E + UVD_MASTINT_EN :TUVD_MASTINT_EN; // 0x3D40 + REG_3D41_3D64 :array[0..35] of DWORD; // 0x3D41 + UVD_LMI_ADDR_EXT :TUVD_LMI_ADDR_EXT; // 0x3D65 + UVD_LMI_CTRL :TUVD_LMI_CTRL; // 0x3D66 + UVD_LMI_STATUS :TUVD_LMI_STATUS; // 0x3D67 + REG_3D68_3D6C :array[0..4] of DWORD; // 0x3D68 + UVD_LMI_SWAP_CNTL :TUVD_LMI_SWAP_CNTL; // 0x3D6D + REG_3D6E :DWORD; // 0x3D6E + UVD_MP_SWAP_CNTL :TUVD_MP_SWAP_CNTL; // 0x3D6F + REG_3D70_3D76 :array[0..6] of DWORD; // 0x3D70 + UVD_MPC_CNTL :TUVD_MPC_CNTL; // 0x3D77 + REG_3D78 :DWORD; // 0x3D78 + UVD_MPC_SET_MUXA0 :TUVD_MPC_SET_MUXA0; // 0x3D79 + UVD_MPC_SET_MUXA1 :TUVD_MPC_SET_MUXA1; // 0x3D7A + UVD_MPC_SET_MUXB0 :TUVD_MPC_SET_MUXB0; // 0x3D7B + UVD_MPC_SET_MUXB1 :TUVD_MPC_SET_MUXB1; // 0x3D7C + UVD_MPC_SET_MUX :TUVD_MPC_SET_MUX; // 0x3D7D + UVD_MPC_SET_ALU :TUVD_MPC_SET_ALU; // 0x3D7E + REG_3D7F_3D81 :array[0..2] of DWORD; // 0x3D7F + UVD_VCPU_CACHE_OFFSET0 :TUVD_VCPU_CACHE_OFFSET0; // 0x3D82 + UVD_VCPU_CACHE_SIZE0 :TUVD_VCPU_CACHE_SIZE0; // 0x3D83 + UVD_VCPU_CACHE_OFFSET1 :TUVD_VCPU_CACHE_OFFSET1; // 0x3D84 + UVD_VCPU_CACHE_SIZE1 :TUVD_VCPU_CACHE_SIZE1; // 0x3D85 + UVD_VCPU_CACHE_OFFSET2 :TUVD_VCPU_CACHE_OFFSET2; // 0x3D86 + UVD_VCPU_CACHE_SIZE2 :TUVD_VCPU_CACHE_SIZE2; // 0x3D87 + REG_3D88_3D97 :array[0..15] of DWORD; // 0x3D88 + UVD_VCPU_CNTL :TUVD_VCPU_CNTL; // 0x3D98 + REG_3D99_3D9F :array[0..6] of DWORD; // 0x3D99 + UVD_SOFT_RESET :TUVD_SOFT_RESET; // 0x3DA0 + UVD_LMI_RBC_IB_VMID :TUVD_LMI_RBC_IB_VMID; // 0x3DA1 + UVD_RBC_IB_SIZE :TUVD_RBC_IB_SIZE; // 0x3DA2 + UVD_LMI_RBC_RB_VMID :TUVD_LMI_RBC_RB_VMID; // 0x3DA3 + UVD_RBC_RB_RPTR :TUVD_RBC_RB_RPTR; // 0x3DA4 + UVD_RBC_RB_WPTR :TUVD_RBC_RB_WPTR; // 0x3DA5 + REG_3DA6_3DA8 :array[0..2] of DWORD; // 0x3DA6 + UVD_RBC_RB_CNTL :TUVD_RBC_RB_CNTL; // 0x3DA9 + UVD_RBC_RB_RPTR_ADDR :TUVD_RBC_RB_RPTR_ADDR; // 0x3DAA + REG_3DAB_3DAE :array[0..3] of DWORD; // 0x3DAB + UVD_STATUS :TUVD_STATUS; // 0x3DAF + UVD_SEMA_TIMEOUT_STATUS :TUVD_SEMA_TIMEOUT_STATUS; // 0x3DB0 + UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL :TUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL; // 0x3DB1 + UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL :TUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL; // 0x3DB2 + UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL :TUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL; // 0x3DB3 + REG_3DB4_3DBC :array[0..8] of DWORD; // 0x3DB4 + UVD_CONTEXT_ID :TUVD_CONTEXT_ID; // 0x3DBD + REG_3DBE_3FFF :array[0..577] of DWORD; // 0x3DBE + DCP3_GRPH_ENABLE :DWORD; // 0x4000 + DCP3_GRPH_CONTROL :DWORD; // 0x4001 + DCP3_GRPH_LUT_10BIT_BYPASS :DWORD; // 0x4002 + DCP3_GRPH_SWAP_CNTL :DWORD; // 0x4003 + DCP3_GRPH_PRIMARY_SURFACE_ADDRESS :DWORD; // 0x4004 + DCP3_GRPH_SECONDARY_SURFACE_ADDRESS :DWORD; // 0x4005 + DCP3_GRPH_PITCH :DWORD; // 0x4006 + DCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4007 + DCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4008 + DCP3_GRPH_SURFACE_OFFSET_X :DWORD; // 0x4009 + DCP3_GRPH_SURFACE_OFFSET_Y :DWORD; // 0x400A + DCP3_GRPH_X_START :DWORD; // 0x400B + DCP3_GRPH_Y_START :DWORD; // 0x400C + DCP3_GRPH_X_END :DWORD; // 0x400D + DCP3_GRPH_Y_END :DWORD; // 0x400E + REG_400F :DWORD; // 0x400F + DCP3_INPUT_GAMMA_CONTROL :DWORD; // 0x4010 + DCP3_GRPH_UPDATE :DWORD; // 0x4011 + DCP3_GRPH_FLIP_CONTROL :DWORD; // 0x4012 + DCP3_GRPH_SURFACE_ADDRESS_INUSE :DWORD; // 0x4013 + DCP3_GRPH_DFQ_CONTROL :DWORD; // 0x4014 + DCP3_GRPH_DFQ_STATUS :DWORD; // 0x4015 + DCP3_GRPH_INTERRUPT_STATUS :DWORD; // 0x4016 + DCP3_GRPH_INTERRUPT_CONTROL :DWORD; // 0x4017 + DCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE :DWORD; // 0x4018 + DCP3_GRPH_COMPRESS_SURFACE_ADDRESS :DWORD; // 0x4019 + DCP3_GRPH_COMPRESS_PITCH :DWORD; // 0x401A + DCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH :DWORD; // 0x401B + DCP3_OVL_ENABLE :DWORD; // 0x401C + DCP3_OVL_CONTROL1 :DWORD; // 0x401D + DCP3_OVL_CONTROL2 :DWORD; // 0x401E + DCP3_OVL_SWAP_CNTL :DWORD; // 0x401F + DCP3_OVL_SURFACE_ADDRESS :DWORD; // 0x4020 + DCP3_OVL_PITCH :DWORD; // 0x4021 + DCP3_OVL_SURFACE_ADDRESS_HIGH :DWORD; // 0x4022 + DCP3_OVL_SURFACE_OFFSET_X :DWORD; // 0x4023 + DCP3_OVL_SURFACE_OFFSET_Y :DWORD; // 0x4024 + DCP3_OVL_START :DWORD; // 0x4025 + DCP3_OVL_END :DWORD; // 0x4026 + DCP3_OVL_UPDATE :DWORD; // 0x4027 + DCP3_OVL_SURFACE_ADDRESS_INUSE :DWORD; // 0x4028 + DCP3_OVL_DFQ_CONTROL :DWORD; // 0x4029 + DCP3_OVL_DFQ_STATUS :DWORD; // 0x402A + DCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE :DWORD; // 0x402B + DCP3_OVLSCL_EDGE_PIXEL_CNTL :DWORD; // 0x402C + DCP3_PRESCALE_GRPH_CONTROL :DWORD; // 0x402D + DCP3_PRESCALE_VALUES_GRPH_R :DWORD; // 0x402E + DCP3_PRESCALE_VALUES_GRPH_G :DWORD; // 0x402F + DCP3_PRESCALE_VALUES_GRPH_B :DWORD; // 0x4030 + DCP3_PRESCALE_OVL_CONTROL :DWORD; // 0x4031 + DCP3_PRESCALE_VALUES_OVL_CB :DWORD; // 0x4032 + DCP3_PRESCALE_VALUES_OVL_Y :DWORD; // 0x4033 + DCP3_PRESCALE_VALUES_OVL_CR :DWORD; // 0x4034 + DCP3_INPUT_CSC_CONTROL :DWORD; // 0x4035 + DCP3_INPUT_CSC_C11_C12 :DWORD; // 0x4036 + DCP3_INPUT_CSC_C13_C14 :DWORD; // 0x4037 + DCP3_INPUT_CSC_C21_C22 :DWORD; // 0x4038 + DCP3_INPUT_CSC_C23_C24 :DWORD; // 0x4039 + DCP3_INPUT_CSC_C31_C32 :DWORD; // 0x403A + DCP3_INPUT_CSC_C33_C34 :DWORD; // 0x403B + DCP3_OUTPUT_CSC_CONTROL :DWORD; // 0x403C + DCP3_OUTPUT_CSC_C11_C12 :DWORD; // 0x403D + DCP3_OUTPUT_CSC_C13_C14 :DWORD; // 0x403E + DCP3_OUTPUT_CSC_C21_C22 :DWORD; // 0x403F + DCP3_OUTPUT_CSC_C23_C24 :DWORD; // 0x4040 + DCP3_OUTPUT_CSC_C31_C32 :DWORD; // 0x4041 + DCP3_OUTPUT_CSC_C33_C34 :DWORD; // 0x4042 + DCP3_COMM_MATRIXA_TRANS_C11_C12 :DWORD; // 0x4043 + DCP3_COMM_MATRIXA_TRANS_C13_C14 :DWORD; // 0x4044 + DCP3_COMM_MATRIXA_TRANS_C21_C22 :DWORD; // 0x4045 + DCP3_COMM_MATRIXA_TRANS_C23_C24 :DWORD; // 0x4046 + DCP3_COMM_MATRIXA_TRANS_C31_C32 :DWORD; // 0x4047 + DCP3_COMM_MATRIXA_TRANS_C33_C34 :DWORD; // 0x4048 + DCP3_COMM_MATRIXB_TRANS_C11_C12 :DWORD; // 0x4049 + DCP3_COMM_MATRIXB_TRANS_C13_C14 :DWORD; // 0x404A + DCP3_COMM_MATRIXB_TRANS_C21_C22 :DWORD; // 0x404B + DCP3_COMM_MATRIXB_TRANS_C23_C24 :DWORD; // 0x404C + DCP3_COMM_MATRIXB_TRANS_C31_C32 :DWORD; // 0x404D + DCP3_COMM_MATRIXB_TRANS_C33_C34 :DWORD; // 0x404E + REG_404F :DWORD; // 0x404F + DCP3_DENORM_CONTROL :DWORD; // 0x4050 + DCP3_OUT_ROUND_CONTROL :DWORD; // 0x4051 + DCP3_OUT_CLAMP_CONTROL_R_CR :DWORD; // 0x4052 + DCP3_KEY_CONTROL :DWORD; // 0x4053 + DCP3_KEY_RANGE_ALPHA :DWORD; // 0x4054 + DCP3_KEY_RANGE_RED :DWORD; // 0x4055 + DCP3_KEY_RANGE_GREEN :DWORD; // 0x4056 + DCP3_KEY_RANGE_BLUE :DWORD; // 0x4057 + DCP3_DEGAMMA_CONTROL :DWORD; // 0x4058 + DCP3_GAMUT_REMAP_CONTROL :DWORD; // 0x4059 + DCP3_GAMUT_REMAP_C11_C12 :DWORD; // 0x405A + DCP3_GAMUT_REMAP_C13_C14 :DWORD; // 0x405B + DCP3_GAMUT_REMAP_C21_C22 :DWORD; // 0x405C + DCP3_GAMUT_REMAP_C23_C24 :DWORD; // 0x405D + DCP3_GAMUT_REMAP_C31_C32 :DWORD; // 0x405E + DCP3_GAMUT_REMAP_C33_C34 :DWORD; // 0x405F + DCP3_DCP_SPATIAL_DITHER_CNTL :DWORD; // 0x4060 + DCP3_DCP_RANDOM_SEEDS :DWORD; // 0x4061 + REG_4062_4064 :array[0..2] of DWORD; // 0x4062 + DCP3_DCP_FP_CONVERTED_FIELD :DWORD; // 0x4065 + DCP3_CUR_CONTROL :DWORD; // 0x4066 + DCP3_CUR_SURFACE_ADDRESS :DWORD; // 0x4067 + DCP3_CUR_SIZE :DWORD; // 0x4068 + DCP3_CUR_SURFACE_ADDRESS_HIGH :DWORD; // 0x4069 + DCP3_CUR_POSITION :DWORD; // 0x406A + DCP3_CUR_HOT_SPOT :DWORD; // 0x406B + DCP3_CUR_COLOR1 :DWORD; // 0x406C + DCP3_CUR_COLOR2 :DWORD; // 0x406D + DCP3_CUR_UPDATE :DWORD; // 0x406E + DCP3_CUR2_CONTROL :DWORD; // 0x406F + DCP3_CUR2_SURFACE_ADDRESS :DWORD; // 0x4070 + DCP3_CUR2_SIZE :DWORD; // 0x4071 + DCP3_CUR2_SURFACE_ADDRESS_HIGH :DWORD; // 0x4072 + DCP3_CUR2_POSITION :DWORD; // 0x4073 + DCP3_CUR2_HOT_SPOT :DWORD; // 0x4074 + DCP3_CUR2_COLOR1 :DWORD; // 0x4075 + DCP3_CUR2_COLOR2 :DWORD; // 0x4076 + DCP3_CUR2_UPDATE :DWORD; // 0x4077 + DCP3_DC_LUT_RW_MODE :DWORD; // 0x4078 + DCP3_DC_LUT_RW_INDEX :DWORD; // 0x4079 + DCP3_DC_LUT_SEQ_COLOR :DWORD; // 0x407A + DCP3_DC_LUT_PWL_DATA :DWORD; // 0x407B + DCP3_DC_LUT_30_COLOR :DWORD; // 0x407C + DCP3_DC_LUT_VGA_ACCESS_ENABLE :DWORD; // 0x407D + DCP3_DC_LUT_WRITE_EN_MASK :DWORD; // 0x407E + DCP3_DC_LUT_AUTOFILL :DWORD; // 0x407F + DCP3_DC_LUT_CONTROL :DWORD; // 0x4080 + DCP3_DC_LUT_BLACK_OFFSET_BLUE :DWORD; // 0x4081 + DCP3_DC_LUT_BLACK_OFFSET_GREEN :DWORD; // 0x4082 + DCP3_DC_LUT_BLACK_OFFSET_RED :DWORD; // 0x4083 + DCP3_DC_LUT_WHITE_OFFSET_BLUE :DWORD; // 0x4084 + DCP3_DC_LUT_WHITE_OFFSET_GREEN :DWORD; // 0x4085 + DCP3_DC_LUT_WHITE_OFFSET_RED :DWORD; // 0x4086 + DCP3_DCP_CRC_CONTROL :DWORD; // 0x4087 + DCP3_DCP_CRC_MASK :DWORD; // 0x4088 + DCP3_DCP_CRC_CURRENT :DWORD; // 0x4089 + REG_408A :DWORD; // 0x408A + DCP3_DCP_CRC_LAST :DWORD; // 0x408B + REG_408C :DWORD; // 0x408C + DCP3_DCP_DEBUG :DWORD; // 0x408D + DCP3_GRPH_FLIP_RATE_CNTL :DWORD; // 0x408E + REG_408F :DWORD; // 0x408F + DCP3_DCP_GSL_CONTROL :DWORD; // 0x4090 + DCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK :DWORD; // 0x4091 + DCP3_OVL_SECONDARY_SURFACE_ADDRESS :DWORD; // 0x4092 + DCP3_OVL_STEREOSYNC_FLIP :DWORD; // 0x4093 + DCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4094 + DCP3_DCP_TEST_DEBUG_INDEX :DWORD; // 0x4095 + DCP3_DCP_TEST_DEBUG_DATA :DWORD; // 0x4096 + DCP3_GRPH_STEREOSYNC_FLIP :DWORD; // 0x4097 + DCP3_DCP_DEBUG2 :DWORD; // 0x4098 + DCP3_CUR_REQUEST_FILTER_CNTL :DWORD; // 0x4099 + DCP3_CUR_STEREO_CONTROL :DWORD; // 0x409A + DCP3_CUR2_STEREO_CONTROL :DWORD; // 0x409B + DCP3_OUT_CLAMP_CONTROL_G_Y :DWORD; // 0x409C + DCP3_OUT_CLAMP_CONTROL_B_CB :DWORD; // 0x409D + DCP3_HW_ROTATION :DWORD; // 0x409E + DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :DWORD; // 0x409F + DCP3_REGAMMA_CONTROL :DWORD; // 0x40A0 + DCP3_REGAMMA_LUT_INDEX :DWORD; // 0x40A1 + DCP3_REGAMMA_LUT_DATA :DWORD; // 0x40A2 + DCP3_REGAMMA_LUT_WRITE_EN_MASK :DWORD; // 0x40A3 + DCP3_REGAMMA_CNTLA_START_CNTL :DWORD; // 0x40A4 + DCP3_REGAMMA_CNTLA_SLOPE_CNTL :DWORD; // 0x40A5 + DCP3_REGAMMA_CNTLA_END_CNTL1 :DWORD; // 0x40A6 + DCP3_REGAMMA_CNTLA_END_CNTL2 :DWORD; // 0x40A7 + DCP3_REGAMMA_CNTLA_REGION_0_1 :DWORD; // 0x40A8 + DCP3_REGAMMA_CNTLA_REGION_2_3 :DWORD; // 0x40A9 + DCP3_REGAMMA_CNTLA_REGION_4_5 :DWORD; // 0x40AA + DCP3_REGAMMA_CNTLA_REGION_6_7 :DWORD; // 0x40AB + DCP3_REGAMMA_CNTLA_REGION_8_9 :DWORD; // 0x40AC + DCP3_REGAMMA_CNTLA_REGION_10_11 :DWORD; // 0x40AD + DCP3_REGAMMA_CNTLA_REGION_12_13 :DWORD; // 0x40AE + DCP3_REGAMMA_CNTLA_REGION_14_15 :DWORD; // 0x40AF + DCP3_REGAMMA_CNTLB_START_CNTL :DWORD; // 0x40B0 + DCP3_REGAMMA_CNTLB_SLOPE_CNTL :DWORD; // 0x40B1 + DCP3_REGAMMA_CNTLB_END_CNTL1 :DWORD; // 0x40B2 + DCP3_REGAMMA_CNTLB_END_CNTL2 :DWORD; // 0x40B3 + DCP3_REGAMMA_CNTLB_REGION_0_1 :DWORD; // 0x40B4 + DCP3_REGAMMA_CNTLB_REGION_2_3 :DWORD; // 0x40B5 + DCP3_REGAMMA_CNTLB_REGION_4_5 :DWORD; // 0x40B6 + DCP3_REGAMMA_CNTLB_REGION_6_7 :DWORD; // 0x40B7 + DCP3_REGAMMA_CNTLB_REGION_8_9 :DWORD; // 0x40B8 + DCP3_REGAMMA_CNTLB_REGION_10_11 :DWORD; // 0x40B9 + DCP3_REGAMMA_CNTLB_REGION_12_13 :DWORD; // 0x40BA + DCP3_REGAMMA_CNTLB_REGION_14_15 :DWORD; // 0x40BB + DCP3_ALPHA_CONTROL :DWORD; // 0x40BC + DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :DWORD; // 0x40BD + DCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :DWORD; // 0x40BE + DCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :DWORD; // 0x40BF + LB3_LB_DATA_FORMAT :DWORD; // 0x40C0 + LB3_LB_MEMORY_CTRL :DWORD; // 0x40C1 + LB3_LB_MEMORY_SIZE_STATUS :DWORD; // 0x40C2 + LB3_LB_DESKTOP_HEIGHT :DWORD; // 0x40C3 + LB3_LB_VLINE_START_END :DWORD; // 0x40C4 + LB3_LB_VLINE2_START_END :DWORD; // 0x40C5 + LB3_LB_V_COUNTER :DWORD; // 0x40C6 + LB3_LB_SNAPSHOT_V_COUNTER :DWORD; // 0x40C7 + LB3_LB_INTERRUPT_MASK :DWORD; // 0x40C8 + LB3_LB_VLINE_STATUS :DWORD; // 0x40C9 + LB3_LB_VLINE2_STATUS :DWORD; // 0x40CA + LB3_LB_VBLANK_STATUS :DWORD; // 0x40CB + LB3_LB_SYNC_RESET_SEL :DWORD; // 0x40CC + LB3_LB_BLACK_KEYER_R_CR :DWORD; // 0x40CD + LB3_LB_BLACK_KEYER_G_Y :DWORD; // 0x40CE + LB3_LB_BLACK_KEYER_B_CB :DWORD; // 0x40CF + LB3_LB_KEYER_COLOR_CTRL :DWORD; // 0x40D0 + LB3_LB_KEYER_COLOR_R_CR :DWORD; // 0x40D1 + LB3_LB_KEYER_COLOR_G_Y :DWORD; // 0x40D2 + LB3_LB_KEYER_COLOR_B_CB :DWORD; // 0x40D3 + LB3_LB_KEYER_COLOR_REP_R_CR :DWORD; // 0x40D4 + LB3_LB_KEYER_COLOR_REP_G_Y :DWORD; // 0x40D5 + LB3_LB_KEYER_COLOR_REP_B_CB :DWORD; // 0x40D6 + LB3_LB_BUFFER_LEVEL_STATUS :DWORD; // 0x40D7 + LB3_LB_BUFFER_URGENCY_CTRL :DWORD; // 0x40D8 + LB3_LB_BUFFER_URGENCY_STATUS :DWORD; // 0x40D9 + LB3_LB_BUFFER_STATUS :DWORD; // 0x40DA + LB2_DC_MVP_LB_CONTROL :DWORD; // 0x40DB + LB3_LB_NO_OUTSTANDING_REQ_STATUS :DWORD; // 0x40DC + REG_40DD_40DF :array[0..2] of DWORD; // 0x40DD + LB3_MVP_AFR_FLIP_MODE :DWORD; // 0x40E0 + LB3_MVP_AFR_FLIP_FIFO_CNTL :DWORD; // 0x40E1 + LB3_MVP_FLIP_LINE_NUM_INSERT :DWORD; // 0x40E2 + LB3_DC_MVP_LB_CONTROL :DWORD; // 0x40E3 + LB3_LB_DEBUG :DWORD; // 0x40E4 + LB3_LB_DEBUG2 :DWORD; // 0x40E5 + LB3_LB_DEBUG3 :DWORD; // 0x40E6 + REG_40E7_40FB :array[0..20] of DWORD; // 0x40E7 + LB2_LB_DEBUG :DWORD; // 0x40FC + REG_40FD :DWORD; // 0x40FD + LB3_LB_TEST_DEBUG_INDEX :DWORD; // 0x40FE + LB3_LB_TEST_DEBUG_DATA :DWORD; // 0x40FF + DCFE3_DCFE_CLOCK_CONTROL :DWORD; // 0x4100 + DCFE3_DCFE_SOFT_RESET :DWORD; // 0x4101 + DCFE3_DCFE_DBG_CONFIG :DWORD; // 0x4102 + REG_4103_4123 :array[0..32] of DWORD; // 0x4103 + DC_PERFMON6_PERFCOUNTER_CNTL :DWORD; // 0x4124 + DC_PERFMON6_PERFCOUNTER_STATE :DWORD; // 0x4125 + DC_PERFMON6_PERFMON_CVALUE_INT_MISC :DWORD; // 0x4126 + DC_PERFMON6_PERFMON_CNTL :DWORD; // 0x4127 + DC_PERFMON6_PERFMON_CVALUE_LOW :DWORD; // 0x4128 + DC_PERFMON6_PERFMON_HI :DWORD; // 0x4129 + DC_PERFMON6_PERFMON_LOW :DWORD; // 0x412A + DC_PERFMON6_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x412B + DC_PERFMON6_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x412C + REG_412D :DWORD; // 0x412D + DC_PERFMON6_PERFMON_CNTL2 :DWORD; // 0x412E + REG_412F :DWORD; // 0x412F + DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 :DWORD; // 0x4130 + DMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 :DWORD; // 0x4131 + DMIF_PG3_DPG_WATERMARK_MASK_CONTROL :DWORD; // 0x4132 + DMIF_PG3_DPG_PIPE_URGENCY_CONTROL :DWORD; // 0x4133 + DMIF_PG3_DPG_PIPE_DPM_CONTROL :DWORD; // 0x4134 + DMIF_PG3_DPG_PIPE_STUTTER_CONTROL :DWORD; // 0x4135 + DMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :DWORD; // 0x4136 + DMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :DWORD; // 0x4137 + DMIF_PG3_DPG_TEST_DEBUG_INDEX :DWORD; // 0x4138 + DMIF_PG3_DPG_TEST_DEBUG_DATA :DWORD; // 0x4139 + DMIF_PG3_DPG_REPEATER_PROGRAM :DWORD; // 0x413A + DMIF_PG3_DPG_HW_DEBUG_A :DWORD; // 0x413B + DMIF_PG3_DPG_HW_DEBUG_B :DWORD; // 0x413C + DMIF_PG3_DPG_HW_DEBUG_11 :DWORD; // 0x413D + REG_413E_413F :array[0..1] of DWORD; // 0x413E + SCL3_SCL_COEF_RAM_SELECT :DWORD; // 0x4140 + SCL3_SCL_COEF_RAM_TAP_DATA :DWORD; // 0x4141 + SCL3_SCL_MODE :DWORD; // 0x4142 + SCL3_SCL_TAP_CONTROL :DWORD; // 0x4143 + SCL3_SCL_CONTROL :DWORD; // 0x4144 + SCL3_SCL_BYPASS_CONTROL :DWORD; // 0x4145 + SCL3_SCL_MANUAL_REPLICATE_CONTROL :DWORD; // 0x4146 + SCL3_SCL_AUTOMATIC_MODE_CONTROL :DWORD; // 0x4147 + SCL3_SCL_HORZ_FILTER_CONTROL :DWORD; // 0x4148 + SCL3_SCL_HORZ_FILTER_SCALE_RATIO :DWORD; // 0x4149 + SCL3_SCL_HORZ_FILTER_INIT :DWORD; // 0x414A + SCL3_SCL_VERT_FILTER_CONTROL :DWORD; // 0x414B + SCL3_SCL_VERT_FILTER_SCALE_RATIO :DWORD; // 0x414C + SCL3_SCL_VERT_FILTER_INIT :DWORD; // 0x414D + SCL3_SCL_VERT_FILTER_INIT_BOT :DWORD; // 0x414E + SCL3_SCL_ROUND_OFFSET :DWORD; // 0x414F + SCL2_SCL_VERT_FILTER_INIT :DWORD; // 0x4150 + SCL3_SCL_UPDATE :DWORD; // 0x4151 + REG_4152 :DWORD; // 0x4152 + SCL3_SCL_F_SHARP_CONTROL :DWORD; // 0x4153 + SCL3_SCL_ALU_CONTROL :DWORD; // 0x4154 + SCL3_SCL_COEF_RAM_CONFLICT_STATUS :DWORD; // 0x4155 + REG_4156 :DWORD; // 0x4156 + SCL2_SCL_VERT_FILTER_INIT_BOT :DWORD; // 0x4157 + REG_4158_415A :array[0..2] of DWORD; // 0x4158 + SCL3_VIEWPORT_START_SECONDARY :DWORD; // 0x415B + SCL3_VIEWPORT_START :DWORD; // 0x415C + SCL3_VIEWPORT_SIZE :DWORD; // 0x415D + SCL3_EXT_OVERSCAN_LEFT_RIGHT :DWORD; // 0x415E + SCL3_EXT_OVERSCAN_TOP_BOTTOM :DWORD; // 0x415F + SCL3_SCL_MODE_CHANGE_DET1 :DWORD; // 0x4160 + SCL3_SCL_MODE_CHANGE_DET2 :DWORD; // 0x4161 + SCL3_SCL_MODE_CHANGE_DET3 :DWORD; // 0x4162 + SCL3_SCL_MODE_CHANGE_MASK :DWORD; // 0x4163 + REG_4164_4168 :array[0..4] of DWORD; // 0x4164 + SCL3_SCL_DEBUG2 :DWORD; // 0x4169 + SCL3_SCL_DEBUG :DWORD; // 0x416A + SCL3_SCL_TEST_DEBUG_INDEX :DWORD; // 0x416B + SCL3_SCL_TEST_DEBUG_DATA :DWORD; // 0x416C + BLND3_BLND_CONTROL :DWORD; // 0x416D + BLND3_SM_CONTROL2 :DWORD; // 0x416E + BLND3_BLND_CONTROL2 :DWORD; // 0x416F + BLND3_BLND_UPDATE :DWORD; // 0x4170 + BLND3_BLND_UNDERFLOW_INTERRUPT :DWORD; // 0x4171 + REG_4172 :DWORD; // 0x4172 + BLND3_BLND_V_UPDATE_LOCK :DWORD; // 0x4173 + BLND3_BLND_DEBUG :DWORD; // 0x4174 + BLND3_BLND_TEST_DEBUG_INDEX :DWORD; // 0x4175 + BLND3_BLND_TEST_DEBUG_DATA :DWORD; // 0x4176 + BLND3_BLND_REG_UPDATE_STATUS :DWORD; // 0x4177 + CRTC3_CRTC_3D_STRUCTURE_CONTROL :DWORD; // 0x4178 + CRTC3_CRTC_GSL_VSYNC_GAP :DWORD; // 0x4179 + CRTC3_CRTC_GSL_WINDOW :DWORD; // 0x417A + CRTC3_CRTC_GSL_CONTROL :DWORD; // 0x417B + CRTC3_CRTC_DCFE_CLOCK_CONTROL :DWORD; // 0x417C + CRTC3_CRTC_H_BLANK_EARLY_NUM :DWORD; // 0x417D + CRTC3_DCFE_DBG_SEL :DWORD; // 0x417E + CRTC3_DCFE_MEM_PWR_CTRL :DWORD; // 0x417F + CRTC3_CRTC_H_TOTAL :DWORD; // 0x4180 + CRTC3_CRTC_H_BLANK_START_END :DWORD; // 0x4181 + CRTC3_CRTC_H_SYNC_A :DWORD; // 0x4182 + CRTC3_CRTC_H_SYNC_A_CNTL :DWORD; // 0x4183 + CRTC3_CRTC_H_SYNC_B :DWORD; // 0x4184 + CRTC3_CRTC_H_SYNC_B_CNTL :DWORD; // 0x4185 + CRTC3_CRTC_VBI_END :DWORD; // 0x4186 + CRTC3_CRTC_V_TOTAL :DWORD; // 0x4187 + CRTC3_CRTC_V_TOTAL_MIN :DWORD; // 0x4188 + CRTC3_CRTC_V_TOTAL_MAX :DWORD; // 0x4189 + CRTC3_CRTC_V_TOTAL_CONTROL :DWORD; // 0x418A + CRTC3_CRTC_V_TOTAL_INT_STATUS :DWORD; // 0x418B + CRTC3_CRTC_VSYNC_NOM_INT_STATUS :DWORD; // 0x418C + CRTC3_CRTC_V_BLANK_START_END :DWORD; // 0x418D + CRTC3_CRTC_V_SYNC_A :DWORD; // 0x418E + CRTC3_CRTC_V_SYNC_A_CNTL :DWORD; // 0x418F + CRTC3_CRTC_V_SYNC_B :DWORD; // 0x4190 + CRTC3_CRTC_V_SYNC_B_CNTL :DWORD; // 0x4191 + CRTC3_CRTC_DTMTEST_CNTL :DWORD; // 0x4192 + CRTC3_CRTC_DTMTEST_STATUS_POSITION :DWORD; // 0x4193 + CRTC3_CRTC_TRIGA_CNTL :DWORD; // 0x4194 + CRTC3_CRTC_TRIGA_MANUAL_TRIG :DWORD; // 0x4195 + CRTC3_CRTC_TRIGB_CNTL :DWORD; // 0x4196 + CRTC3_CRTC_TRIGB_MANUAL_TRIG :DWORD; // 0x4197 + CRTC3_CRTC_FORCE_COUNT_NOW_CNTL :DWORD; // 0x4198 + CRTC3_CRTC_FLOW_CONTROL :DWORD; // 0x4199 + CRTC3_CRTC_STEREO_FORCE_NEXT_EYE :DWORD; // 0x419A + CRTC3_CRTC_AVSYNC_COUNTER :DWORD; // 0x419B + CRTC3_CRTC_CONTROL :DWORD; // 0x419C + CRTC3_CRTC_BLANK_CONTROL :DWORD; // 0x419D + CRTC3_CRTC_INTERLACE_CONTROL :DWORD; // 0x419E + CRTC3_CRTC_INTERLACE_STATUS :DWORD; // 0x419F + CRTC3_CRTC_FIELD_INDICATION_CONTROL :DWORD; // 0x41A0 + CRTC3_CRTC_PIXEL_DATA_READBACK0 :DWORD; // 0x41A1 + CRTC3_CRTC_PIXEL_DATA_READBACK1 :DWORD; // 0x41A2 + CRTC3_CRTC_STATUS :DWORD; // 0x41A3 + CRTC3_CRTC_STATUS_POSITION :DWORD; // 0x41A4 + CRTC3_CRTC_NOM_VERT_POSITION :DWORD; // 0x41A5 + CRTC3_CRTC_STATUS_FRAME_COUNT :DWORD; // 0x41A6 + CRTC3_CRTC_STATUS_VF_COUNT :DWORD; // 0x41A7 + CRTC3_CRTC_STATUS_HV_COUNT :DWORD; // 0x41A8 + CRTC3_CRTC_COUNT_CONTROL :DWORD; // 0x41A9 + CRTC3_CRTC_COUNT_RESET :DWORD; // 0x41AA + CRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :DWORD; // 0x41AB + CRTC3_CRTC_VERT_SYNC_CONTROL :DWORD; // 0x41AC + CRTC3_CRTC_STEREO_STATUS :DWORD; // 0x41AD + CRTC3_CRTC_STEREO_CONTROL :DWORD; // 0x41AE + CRTC3_CRTC_SNAPSHOT_STATUS :DWORD; // 0x41AF + CRTC3_CRTC_SNAPSHOT_CONTROL :DWORD; // 0x41B0 + CRTC3_CRTC_SNAPSHOT_POSITION :DWORD; // 0x41B1 + CRTC3_CRTC_SNAPSHOT_FRAME :DWORD; // 0x41B2 + CRTC3_CRTC_START_LINE_CONTROL :DWORD; // 0x41B3 + CRTC3_CRTC_INTERRUPT_CONTROL :DWORD; // 0x41B4 + CRTC3_CRTC_UPDATE_LOCK :DWORD; // 0x41B5 + CRTC3_CRTC_DOUBLE_BUFFER_CONTROL :DWORD; // 0x41B6 + CRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE :DWORD; // 0x41B7 + CRTC3_DCFE_MEM_PWR_CTRL2 :DWORD; // 0x41B8 + CRTC3_DCFE_MEM_PWR_STATUS :DWORD; // 0x41B9 + CRTC3_CRTC_TEST_PATTERN_CONTROL :DWORD; // 0x41BA + CRTC3_CRTC_TEST_PATTERN_PARAMETERS :DWORD; // 0x41BB + CRTC3_CRTC_TEST_PATTERN_COLOR :DWORD; // 0x41BC + CRTC3_MASTER_UPDATE_LOCK :DWORD; // 0x41BD + CRTC3_MASTER_UPDATE_MODE :DWORD; // 0x41BE + CRTC3_CRTC_MVP_INBAND_CNTL_INSERT :DWORD; // 0x41BF + CRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :DWORD; // 0x41C0 + CRTC3_CRTC_MVP_STATUS :DWORD; // 0x41C1 + CRTC3_CRTC_MASTER_EN :DWORD; // 0x41C2 + CRTC3_CRTC_ALLOW_STOP_OFF_V_CNT :DWORD; // 0x41C3 + CRTC3_CRTC_V_UPDATE_INT_STATUS :DWORD; // 0x41C4 + REG_41C5 :DWORD; // 0x41C5 + CRTC3_CRTC_TEST_DEBUG_INDEX :DWORD; // 0x41C6 + CRTC3_CRTC_TEST_DEBUG_DATA :DWORD; // 0x41C7 + CRTC3_CRTC_OVERSCAN_COLOR :DWORD; // 0x41C8 + CRTC3_CRTC_OVERSCAN_COLOR_EXT :DWORD; // 0x41C9 + CRTC3_CRTC_BLANK_DATA_COLOR :DWORD; // 0x41CA + CRTC3_CRTC_BLANK_DATA_COLOR_EXT :DWORD; // 0x41CB + CRTC3_CRTC_BLACK_COLOR :DWORD; // 0x41CC + CRTC3_CRTC_BLACK_COLOR_EXT :DWORD; // 0x41CD + CRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION :DWORD; // 0x41CE + CRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL :DWORD; // 0x41CF + CRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION :DWORD; // 0x41D0 + CRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL :DWORD; // 0x41D1 + CRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION :DWORD; // 0x41D2 + CRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL :DWORD; // 0x41D3 + CRTC3_CRTC_CRC_CNTL :DWORD; // 0x41D4 + CRTC3_CRTC_CRC0_WINDOWA_X_CONTROL :DWORD; // 0x41D5 + CRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL :DWORD; // 0x41D6 + CRTC3_CRTC_CRC0_WINDOWB_X_CONTROL :DWORD; // 0x41D7 + CRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL :DWORD; // 0x41D8 + CRTC3_CRTC_CRC0_DATA_RG :DWORD; // 0x41D9 + CRTC3_CRTC_CRC0_DATA_B :DWORD; // 0x41DA + CRTC3_CRTC_CRC1_WINDOWA_X_CONTROL :DWORD; // 0x41DB + CRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL :DWORD; // 0x41DC + CRTC3_CRTC_CRC1_WINDOWB_X_CONTROL :DWORD; // 0x41DD + CRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL :DWORD; // 0x41DE + CRTC3_CRTC_CRC1_DATA_RG :DWORD; // 0x41DF + CRTC3_CRTC_CRC1_DATA_B :DWORD; // 0x41E0 + CRTC3_CRTC_EXT_TIMING_SYNC_CONTROL :DWORD; // 0x41E1 + CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START :DWORD; // 0x41E2 + CRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END :DWORD; // 0x41E3 + CRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :DWORD; // 0x41E4 + CRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :DWORD; // 0x41E5 + CRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :DWORD; // 0x41E6 + CRTC3_CRTC_STATIC_SCREEN_CONTROL :DWORD; // 0x41E7 + FMT3_FMT_CLAMP_COMPONENT_R :DWORD; // 0x41E8 + FMT3_FMT_CLAMP_COMPONENT_G :DWORD; // 0x41E9 + FMT3_FMT_CLAMP_COMPONENT_B :DWORD; // 0x41EA + FMT3_FMT_TEST_DEBUG_INDEX :DWORD; // 0x41EB + FMT3_FMT_TEST_DEBUG_DATA :DWORD; // 0x41EC + FMT3_FMT_DYNAMIC_EXP_CNTL :DWORD; // 0x41ED + FMT3_FMT_CONTROL :DWORD; // 0x41EE + FMT3_FMT_FORCE_OUTPUT_CNTL :DWORD; // 0x41EF + FMT3_FMT_FORCE_DATA_0_1 :DWORD; // 0x41F0 + FMT3_FMT_FORCE_DATA_2_3 :DWORD; // 0x41F1 + FMT3_FMT_BIT_DEPTH_CONTROL :DWORD; // 0x41F2 + FMT3_FMT_DITHER_RAND_R_SEED :DWORD; // 0x41F3 + FMT3_FMT_DITHER_RAND_G_SEED :DWORD; // 0x41F4 + FMT3_FMT_DITHER_RAND_B_SEED :DWORD; // 0x41F5 + FMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :DWORD; // 0x41F6 + FMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD; // 0x41F7 + FMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD; // 0x41F8 + FMT3_FMT_CLAMP_CNTL :DWORD; // 0x41F9 + FMT3_FMT_CRC_CNTL :DWORD; // 0x41FA + FMT3_FMT_CRC_SIG_RED_GREEN_MASK :DWORD; // 0x41FB + FMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK :DWORD; // 0x41FC + FMT3_FMT_CRC_SIG_RED_GREEN :DWORD; // 0x41FD + FMT3_FMT_CRC_SIG_BLUE_CONTROL :DWORD; // 0x41FE + FMT3_FMT_DEBUG_CNTL :DWORD; // 0x41FF + DCP4_GRPH_ENABLE :DWORD; // 0x4200 + DCP4_GRPH_CONTROL :DWORD; // 0x4201 + REG_4202_4203 :array[0..1] of DWORD; // 0x4202 + DCP4_GRPH_PRIMARY_SURFACE_ADDRESS :DWORD; // 0x4204 + REG_4205 :DWORD; // 0x4205 + DCP4_GRPH_PITCH :DWORD; // 0x4206 + DCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4207 + DCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4208 + DCP4_GRPH_SURFACE_OFFSET_X :DWORD; // 0x4209 + DCP4_GRPH_SURFACE_OFFSET_Y :DWORD; // 0x420A + DCP4_GRPH_X_START :DWORD; // 0x420B + REG_420C_420F :array[0..3] of DWORD; // 0x420C + DCP4_INPUT_GAMMA_CONTROL :DWORD; // 0x4210 + DCP4_GRPH_UPDATE :DWORD; // 0x4211 + DCP4_GRPH_FLIP_CONTROL :DWORD; // 0x4212 + DCP4_GRPH_SURFACE_ADDRESS_INUSE :DWORD; // 0x4213 + DCP4_GRPH_DFQ_CONTROL :DWORD; // 0x4214 + DCP4_GRPH_DFQ_STATUS :DWORD; // 0x4215 + REG_4216_421F :array[0..9] of DWORD; // 0x4216 + DCP4_OVL_SURFACE_ADDRESS :DWORD; // 0x4220 + REG_4221_4226 :array[0..5] of DWORD; // 0x4221 + DCP4_OVL_UPDATE :DWORD; // 0x4227 + DCP4_OVL_SURFACE_ADDRESS_INUSE :DWORD; // 0x4228 + DCP4_OVL_DFQ_CONTROL :DWORD; // 0x4229 + DCP4_OVL_DFQ_STATUS :DWORD; // 0x422A + DCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE :DWORD; // 0x422B + DCP4_OVLSCL_EDGE_PIXEL_CNTL :DWORD; // 0x422C + DCP4_PRESCALE_GRPH_CONTROL :DWORD; // 0x422D + DCP4_PRESCALE_VALUES_GRPH_R :DWORD; // 0x422E + DCP4_PRESCALE_VALUES_GRPH_G :DWORD; // 0x422F + DCP4_PRESCALE_VALUES_GRPH_B :DWORD; // 0x4230 + DCP4_PRESCALE_OVL_CONTROL :DWORD; // 0x4231 + DCP4_PRESCALE_VALUES_OVL_CB :DWORD; // 0x4232 + DCP4_PRESCALE_VALUES_OVL_Y :DWORD; // 0x4233 + DCP4_PRESCALE_VALUES_OVL_CR :DWORD; // 0x4234 + DCP4_INPUT_CSC_CONTROL :DWORD; // 0x4235 + DCP4_INPUT_CSC_C11_C12 :DWORD; // 0x4236 + DCP4_INPUT_CSC_C13_C14 :DWORD; // 0x4237 + DCP4_INPUT_CSC_C21_C22 :DWORD; // 0x4238 + DCP4_INPUT_CSC_C23_C24 :DWORD; // 0x4239 + DCP4_INPUT_CSC_C31_C32 :DWORD; // 0x423A + DCP4_INPUT_CSC_C33_C34 :DWORD; // 0x423B + DCP4_OUTPUT_CSC_CONTROL :DWORD; // 0x423C + DCP4_OUTPUT_CSC_C11_C12 :DWORD; // 0x423D + DCP4_OUTPUT_CSC_C13_C14 :DWORD; // 0x423E + DCP4_OUTPUT_CSC_C21_C22 :DWORD; // 0x423F + DCP4_OUTPUT_CSC_C23_C24 :DWORD; // 0x4240 + DCP4_OUTPUT_CSC_C31_C32 :DWORD; // 0x4241 + DCP4_OUTPUT_CSC_C33_C34 :DWORD; // 0x4242 + DCP4_COMM_MATRIXA_TRANS_C11_C12 :DWORD; // 0x4243 + DCP4_COMM_MATRIXA_TRANS_C13_C14 :DWORD; // 0x4244 + DCP4_COMM_MATRIXA_TRANS_C21_C22 :DWORD; // 0x4245 + DCP4_COMM_MATRIXA_TRANS_C23_C24 :DWORD; // 0x4246 + DCP4_COMM_MATRIXA_TRANS_C31_C32 :DWORD; // 0x4247 + DCP4_COMM_MATRIXA_TRANS_C33_C34 :DWORD; // 0x4248 + DCP4_COMM_MATRIXB_TRANS_C11_C12 :DWORD; // 0x4249 + DCP4_COMM_MATRIXB_TRANS_C13_C14 :DWORD; // 0x424A + DCP4_COMM_MATRIXB_TRANS_C21_C22 :DWORD; // 0x424B + DCP4_COMM_MATRIXB_TRANS_C23_C24 :DWORD; // 0x424C + DCP4_COMM_MATRIXB_TRANS_C31_C32 :DWORD; // 0x424D + DCP4_COMM_MATRIXB_TRANS_C33_C34 :DWORD; // 0x424E + REG_424F :DWORD; // 0x424F + DCP4_DENORM_CONTROL :DWORD; // 0x4250 + DCP4_OUT_ROUND_CONTROL :DWORD; // 0x4251 + DCP4_OUT_CLAMP_CONTROL_R_CR :DWORD; // 0x4252 + DCP4_KEY_CONTROL :DWORD; // 0x4253 + DCP4_KEY_RANGE_ALPHA :DWORD; // 0x4254 + DCP4_KEY_RANGE_RED :DWORD; // 0x4255 + DCP4_KEY_RANGE_GREEN :DWORD; // 0x4256 + DCP4_KEY_RANGE_BLUE :DWORD; // 0x4257 + DCP4_DEGAMMA_CONTROL :DWORD; // 0x4258 + DCP4_GAMUT_REMAP_CONTROL :DWORD; // 0x4259 + DCP4_GAMUT_REMAP_C11_C12 :DWORD; // 0x425A + DCP4_GAMUT_REMAP_C13_C14 :DWORD; // 0x425B + DCP4_GAMUT_REMAP_C21_C22 :DWORD; // 0x425C + DCP4_GAMUT_REMAP_C23_C24 :DWORD; // 0x425D + DCP4_GAMUT_REMAP_C31_C32 :DWORD; // 0x425E + DCP4_GAMUT_REMAP_C33_C34 :DWORD; // 0x425F + DCP4_DCP_SPATIAL_DITHER_CNTL :DWORD; // 0x4260 + DCP4_DCP_RANDOM_SEEDS :DWORD; // 0x4261 + REG_4262_4264 :array[0..2] of DWORD; // 0x4262 + DCP4_DCP_FP_CONVERTED_FIELD :DWORD; // 0x4265 + DCP4_CUR_CONTROL :DWORD; // 0x4266 + DCP4_CUR_SURFACE_ADDRESS :DWORD; // 0x4267 + DCP4_CUR_SIZE :DWORD; // 0x4268 + DCP4_CUR_SURFACE_ADDRESS_HIGH :DWORD; // 0x4269 + DCP4_CUR_POSITION :DWORD; // 0x426A + DCP4_CUR_HOT_SPOT :DWORD; // 0x426B + DCP4_CUR_COLOR1 :DWORD; // 0x426C + DCP4_CUR_COLOR2 :DWORD; // 0x426D + DCP4_CUR_UPDATE :DWORD; // 0x426E + DCP4_CUR2_CONTROL :DWORD; // 0x426F + DCP4_CUR2_SURFACE_ADDRESS :DWORD; // 0x4270 + DCP4_CUR2_SIZE :DWORD; // 0x4271 + DCP4_CUR2_SURFACE_ADDRESS_HIGH :DWORD; // 0x4272 + DCP4_CUR2_POSITION :DWORD; // 0x4273 + DCP4_CUR2_HOT_SPOT :DWORD; // 0x4274 + DCP4_CUR2_COLOR1 :DWORD; // 0x4275 + DCP4_CUR2_COLOR2 :DWORD; // 0x4276 + DCP4_CUR2_UPDATE :DWORD; // 0x4277 + DCP4_DC_LUT_RW_MODE :DWORD; // 0x4278 + DCP4_DC_LUT_RW_INDEX :DWORD; // 0x4279 + DCP4_DC_LUT_SEQ_COLOR :DWORD; // 0x427A + DCP4_DC_LUT_PWL_DATA :DWORD; // 0x427B + REG_427C :DWORD; // 0x427C + DCP4_DC_LUT_VGA_ACCESS_ENABLE :DWORD; // 0x427D + REG_427E_4284 :array[0..6] of DWORD; // 0x427E + DCP4_DC_LUT_WHITE_OFFSET_GREEN :DWORD; // 0x4285 + REG_4286_4287 :array[0..1] of DWORD; // 0x4286 + DCP4_DCP_CRC_MASK :DWORD; // 0x4288 + DCP4_DCP_CRC_CURRENT :DWORD; // 0x4289 + REG_428A :DWORD; // 0x428A + DCP4_DCP_CRC_LAST :DWORD; // 0x428B + REG_428C :DWORD; // 0x428C + DCP4_DCP_DEBUG :DWORD; // 0x428D + DCP4_GRPH_FLIP_RATE_CNTL :DWORD; // 0x428E + REG_428F :DWORD; // 0x428F + DCP4_DCP_GSL_CONTROL :DWORD; // 0x4290 + DCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK :DWORD; // 0x4291 + DCP4_OVL_SECONDARY_SURFACE_ADDRESS :DWORD; // 0x4292 + DCP4_OVL_STEREOSYNC_FLIP :DWORD; // 0x4293 + DCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4294 + DCP4_DCP_TEST_DEBUG_INDEX :DWORD; // 0x4295 + DCP4_DCP_TEST_DEBUG_DATA :DWORD; // 0x4296 + DCP4_GRPH_STEREOSYNC_FLIP :DWORD; // 0x4297 + DCP4_DCP_DEBUG2 :DWORD; // 0x4298 + DCP4_CUR_REQUEST_FILTER_CNTL :DWORD; // 0x4299 + DCP4_CUR_STEREO_CONTROL :DWORD; // 0x429A + DCP4_CUR2_STEREO_CONTROL :DWORD; // 0x429B + DCP4_OUT_CLAMP_CONTROL_G_Y :DWORD; // 0x429C + DCP4_OUT_CLAMP_CONTROL_B_CB :DWORD; // 0x429D + DCP4_HW_ROTATION :DWORD; // 0x429E + DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :DWORD; // 0x429F + DCP4_REGAMMA_CONTROL :DWORD; // 0x42A0 + DCP4_REGAMMA_LUT_INDEX :DWORD; // 0x42A1 + DCP4_REGAMMA_LUT_DATA :DWORD; // 0x42A2 + DCP4_REGAMMA_LUT_WRITE_EN_MASK :DWORD; // 0x42A3 + DCP4_REGAMMA_CNTLA_START_CNTL :DWORD; // 0x42A4 + DCP4_REGAMMA_CNTLA_SLOPE_CNTL :DWORD; // 0x42A5 + DCP4_REGAMMA_CNTLA_END_CNTL1 :DWORD; // 0x42A6 + DCP4_REGAMMA_CNTLA_END_CNTL2 :DWORD; // 0x42A7 + DCP4_REGAMMA_CNTLA_REGION_0_1 :DWORD; // 0x42A8 + DCP4_REGAMMA_CNTLA_REGION_2_3 :DWORD; // 0x42A9 + DCP4_REGAMMA_CNTLA_REGION_4_5 :DWORD; // 0x42AA + DCP4_REGAMMA_CNTLA_REGION_6_7 :DWORD; // 0x42AB + DCP4_REGAMMA_CNTLA_REGION_8_9 :DWORD; // 0x42AC + DCP4_REGAMMA_CNTLA_REGION_10_11 :DWORD; // 0x42AD + DCP4_REGAMMA_CNTLA_REGION_12_13 :DWORD; // 0x42AE + DCP4_REGAMMA_CNTLA_REGION_14_15 :DWORD; // 0x42AF + DCP4_REGAMMA_CNTLB_START_CNTL :DWORD; // 0x42B0 + DCP4_REGAMMA_CNTLB_SLOPE_CNTL :DWORD; // 0x42B1 + DCP4_REGAMMA_CNTLB_END_CNTL1 :DWORD; // 0x42B2 + DCP4_REGAMMA_CNTLB_END_CNTL2 :DWORD; // 0x42B3 + DCP4_REGAMMA_CNTLB_REGION_0_1 :DWORD; // 0x42B4 + DCP4_REGAMMA_CNTLB_REGION_2_3 :DWORD; // 0x42B5 + DCP4_REGAMMA_CNTLB_REGION_4_5 :DWORD; // 0x42B6 + DCP4_REGAMMA_CNTLB_REGION_6_7 :DWORD; // 0x42B7 + DCP4_REGAMMA_CNTLB_REGION_8_9 :DWORD; // 0x42B8 + DCP4_REGAMMA_CNTLB_REGION_10_11 :DWORD; // 0x42B9 + DCP4_REGAMMA_CNTLB_REGION_12_13 :DWORD; // 0x42BA + DCP4_REGAMMA_CNTLB_REGION_14_15 :DWORD; // 0x42BB + DCP4_ALPHA_CONTROL :DWORD; // 0x42BC + DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :DWORD; // 0x42BD + DCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :DWORD; // 0x42BE + DCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :DWORD; // 0x42BF + LB4_LB_DATA_FORMAT :DWORD; // 0x42C0 + LB4_LB_MEMORY_CTRL :DWORD; // 0x42C1 + LB4_LB_MEMORY_SIZE_STATUS :DWORD; // 0x42C2 + LB4_LB_DESKTOP_HEIGHT :DWORD; // 0x42C3 + LB4_LB_VLINE_START_END :DWORD; // 0x42C4 + LB4_LB_VLINE2_START_END :DWORD; // 0x42C5 + LB4_LB_V_COUNTER :DWORD; // 0x42C6 + LB4_LB_SNAPSHOT_V_COUNTER :DWORD; // 0x42C7 + LB4_LB_INTERRUPT_MASK :DWORD; // 0x42C8 + LB4_LB_VLINE_STATUS :DWORD; // 0x42C9 + LB4_LB_VLINE2_STATUS :DWORD; // 0x42CA + LB4_LB_VBLANK_STATUS :DWORD; // 0x42CB + LB4_LB_SYNC_RESET_SEL :DWORD; // 0x42CC + LB4_LB_BLACK_KEYER_R_CR :DWORD; // 0x42CD + LB4_LB_BLACK_KEYER_G_Y :DWORD; // 0x42CE + LB4_LB_BLACK_KEYER_B_CB :DWORD; // 0x42CF + LB4_LB_KEYER_COLOR_CTRL :DWORD; // 0x42D0 + LB4_LB_KEYER_COLOR_R_CR :DWORD; // 0x42D1 + LB4_LB_KEYER_COLOR_G_Y :DWORD; // 0x42D2 + LB4_LB_KEYER_COLOR_B_CB :DWORD; // 0x42D3 + LB4_LB_KEYER_COLOR_REP_R_CR :DWORD; // 0x42D4 + LB4_LB_KEYER_COLOR_REP_G_Y :DWORD; // 0x42D5 + LB4_LB_KEYER_COLOR_REP_B_CB :DWORD; // 0x42D6 + LB4_LB_BUFFER_LEVEL_STATUS :DWORD; // 0x42D7 + LB4_LB_BUFFER_URGENCY_CTRL :DWORD; // 0x42D8 + LB4_LB_BUFFER_URGENCY_STATUS :DWORD; // 0x42D9 + LB4_LB_BUFFER_STATUS :DWORD; // 0x42DA + REG_42DB :DWORD; // 0x42DB + LB4_LB_NO_OUTSTANDING_REQ_STATUS :DWORD; // 0x42DC + REG_42DD_42DF :array[0..2] of DWORD; // 0x42DD + LB4_MVP_AFR_FLIP_MODE :DWORD; // 0x42E0 + LB4_MVP_AFR_FLIP_FIFO_CNTL :DWORD; // 0x42E1 + LB4_MVP_FLIP_LINE_NUM_INSERT :DWORD; // 0x42E2 + LB4_DC_MVP_LB_CONTROL :DWORD; // 0x42E3 + LB4_LB_DEBUG :DWORD; // 0x42E4 + LB4_LB_DEBUG2 :DWORD; // 0x42E5 + LB4_LB_DEBUG3 :DWORD; // 0x42E6 + REG_42E7_42FD :array[0..22] of DWORD; // 0x42E7 + LB4_LB_TEST_DEBUG_INDEX :DWORD; // 0x42FE + LB4_LB_TEST_DEBUG_DATA :DWORD; // 0x42FF + DCFE4_DCFE_CLOCK_CONTROL :DWORD; // 0x4300 + DCFE4_DCFE_SOFT_RESET :DWORD; // 0x4301 + DCFE4_DCFE_DBG_CONFIG :DWORD; // 0x4302 + REG_4303_4323 :array[0..32] of DWORD; // 0x4303 + DC_PERFMON7_PERFCOUNTER_CNTL :DWORD; // 0x4324 + DC_PERFMON7_PERFCOUNTER_STATE :DWORD; // 0x4325 + DC_PERFMON7_PERFMON_CVALUE_INT_MISC :DWORD; // 0x4326 + DC_PERFMON7_PERFMON_CNTL :DWORD; // 0x4327 + DC_PERFMON7_PERFMON_CVALUE_LOW :DWORD; // 0x4328 + DC_PERFMON7_PERFMON_HI :DWORD; // 0x4329 + DC_PERFMON7_PERFMON_LOW :DWORD; // 0x432A + DC_PERFMON7_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x432B + DC_PERFMON7_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x432C + REG_432D :DWORD; // 0x432D + DC_PERFMON7_PERFMON_CNTL2 :DWORD; // 0x432E + REG_432F :DWORD; // 0x432F + DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 :DWORD; // 0x4330 + DMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 :DWORD; // 0x4331 + DMIF_PG4_DPG_WATERMARK_MASK_CONTROL :DWORD; // 0x4332 + DMIF_PG4_DPG_PIPE_URGENCY_CONTROL :DWORD; // 0x4333 + DMIF_PG4_DPG_PIPE_DPM_CONTROL :DWORD; // 0x4334 + DMIF_PG4_DPG_PIPE_STUTTER_CONTROL :DWORD; // 0x4335 + DMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :DWORD; // 0x4336 + DMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :DWORD; // 0x4337 + DMIF_PG4_DPG_TEST_DEBUG_INDEX :DWORD; // 0x4338 + DMIF_PG4_DPG_TEST_DEBUG_DATA :DWORD; // 0x4339 + DMIF_PG4_DPG_REPEATER_PROGRAM :DWORD; // 0x433A + DMIF_PG4_DPG_HW_DEBUG_A :DWORD; // 0x433B + DMIF_PG4_DPG_HW_DEBUG_B :DWORD; // 0x433C + DMIF_PG4_DPG_HW_DEBUG_11 :DWORD; // 0x433D + REG_433E_433F :array[0..1] of DWORD; // 0x433E + SCL4_SCL_COEF_RAM_SELECT :DWORD; // 0x4340 + SCL4_SCL_COEF_RAM_TAP_DATA :DWORD; // 0x4341 + SCL4_SCL_MODE :DWORD; // 0x4342 + SCL4_SCL_TAP_CONTROL :DWORD; // 0x4343 + SCL4_SCL_CONTROL :DWORD; // 0x4344 + SCL4_SCL_BYPASS_CONTROL :DWORD; // 0x4345 + SCL4_SCL_MANUAL_REPLICATE_CONTROL :DWORD; // 0x4346 + SCL4_SCL_AUTOMATIC_MODE_CONTROL :DWORD; // 0x4347 + SCL4_SCL_HORZ_FILTER_CONTROL :DWORD; // 0x4348 + SCL4_SCL_HORZ_FILTER_SCALE_RATIO :DWORD; // 0x4349 + SCL4_SCL_HORZ_FILTER_INIT :DWORD; // 0x434A + SCL4_SCL_VERT_FILTER_CONTROL :DWORD; // 0x434B + SCL4_SCL_VERT_FILTER_SCALE_RATIO :DWORD; // 0x434C + SCL4_SCL_VERT_FILTER_INIT :DWORD; // 0x434D + SCL4_SCL_VERT_FILTER_INIT_BOT :DWORD; // 0x434E + SCL4_SCL_ROUND_OFFSET :DWORD; // 0x434F + REG_4350 :DWORD; // 0x4350 + SCL4_SCL_UPDATE :DWORD; // 0x4351 + REG_4352 :DWORD; // 0x4352 + SCL4_SCL_F_SHARP_CONTROL :DWORD; // 0x4353 + SCL4_SCL_ALU_CONTROL :DWORD; // 0x4354 + SCL4_SCL_COEF_RAM_CONFLICT_STATUS :DWORD; // 0x4355 + REG_4356_435A :array[0..4] of DWORD; // 0x4356 + SCL4_VIEWPORT_START_SECONDARY :DWORD; // 0x435B + SCL4_VIEWPORT_START :DWORD; // 0x435C + SCL4_VIEWPORT_SIZE :DWORD; // 0x435D + SCL4_EXT_OVERSCAN_LEFT_RIGHT :DWORD; // 0x435E + SCL4_EXT_OVERSCAN_TOP_BOTTOM :DWORD; // 0x435F + SCL4_SCL_MODE_CHANGE_DET1 :DWORD; // 0x4360 + SCL4_SCL_MODE_CHANGE_DET2 :DWORD; // 0x4361 + SCL4_SCL_MODE_CHANGE_DET3 :DWORD; // 0x4362 + SCL4_SCL_MODE_CHANGE_MASK :DWORD; // 0x4363 + REG_4364_4368 :array[0..4] of DWORD; // 0x4364 + SCL4_SCL_DEBUG2 :DWORD; // 0x4369 + SCL4_SCL_DEBUG :DWORD; // 0x436A + SCL4_SCL_TEST_DEBUG_INDEX :DWORD; // 0x436B + SCL4_SCL_TEST_DEBUG_DATA :DWORD; // 0x436C + BLND4_BLND_CONTROL :DWORD; // 0x436D + BLND4_SM_CONTROL2 :DWORD; // 0x436E + BLND4_BLND_CONTROL2 :DWORD; // 0x436F + BLND4_BLND_UPDATE :DWORD; // 0x4370 + BLND4_BLND_UNDERFLOW_INTERRUPT :DWORD; // 0x4371 + REG_4372 :DWORD; // 0x4372 + BLND4_BLND_V_UPDATE_LOCK :DWORD; // 0x4373 + BLND4_BLND_DEBUG :DWORD; // 0x4374 + BLND4_BLND_TEST_DEBUG_INDEX :DWORD; // 0x4375 + BLND4_BLND_TEST_DEBUG_DATA :DWORD; // 0x4376 + BLND4_BLND_REG_UPDATE_STATUS :DWORD; // 0x4377 + CRTC4_CRTC_3D_STRUCTURE_CONTROL :DWORD; // 0x4378 + CRTC4_CRTC_GSL_VSYNC_GAP :DWORD; // 0x4379 + CRTC4_CRTC_GSL_WINDOW :DWORD; // 0x437A + CRTC4_CRTC_GSL_CONTROL :DWORD; // 0x437B + CRTC4_CRTC_DCFE_CLOCK_CONTROL :DWORD; // 0x437C + CRTC4_CRTC_H_BLANK_EARLY_NUM :DWORD; // 0x437D + CRTC4_DCFE_DBG_SEL :DWORD; // 0x437E + CRTC4_DCFE_MEM_PWR_CTRL :DWORD; // 0x437F + REG_4380_4389 :array[0..9] of DWORD; // 0x4380 + CRTC4_CRTC_V_TOTAL_CONTROL :DWORD; // 0x438A + REG_438B :DWORD; // 0x438B + CRTC4_CRTC_VSYNC_NOM_INT_STATUS :DWORD; // 0x438C + REG_438D :DWORD; // 0x438D + CRTC4_CRTC_V_SYNC_A :DWORD; // 0x438E + CRTC4_CRTC_V_SYNC_A_CNTL :DWORD; // 0x438F + CRTC4_CRTC_V_SYNC_B :DWORD; // 0x4390 + REG_4391 :DWORD; // 0x4391 + CRTC4_CRTC_DTMTEST_CNTL :DWORD; // 0x4392 + CRTC4_CRTC_DTMTEST_STATUS_POSITION :DWORD; // 0x4393 + CRTC4_CRTC_TRIGA_CNTL :DWORD; // 0x4394 + REG_4395_4396 :array[0..1] of DWORD; // 0x4395 + CRTC4_CRTC_TRIGB_MANUAL_TRIG :DWORD; // 0x4397 + CRTC4_CRTC_FORCE_COUNT_NOW_CNTL :DWORD; // 0x4398 + CRTC4_CRTC_FLOW_CONTROL :DWORD; // 0x4399 + CRTC4_CRTC_STEREO_FORCE_NEXT_EYE :DWORD; // 0x439A + CRTC4_CRTC_AVSYNC_COUNTER :DWORD; // 0x439B + CRTC4_CRTC_CONTROL :DWORD; // 0x439C + CRTC4_CRTC_BLANK_CONTROL :DWORD; // 0x439D + CRTC4_CRTC_INTERLACE_CONTROL :DWORD; // 0x439E + CRTC4_CRTC_INTERLACE_STATUS :DWORD; // 0x439F + CRTC4_CRTC_FIELD_INDICATION_CONTROL :DWORD; // 0x43A0 + CRTC4_CRTC_PIXEL_DATA_READBACK0 :DWORD; // 0x43A1 + CRTC4_CRTC_PIXEL_DATA_READBACK1 :DWORD; // 0x43A2 + CRTC4_CRTC_STATUS :DWORD; // 0x43A3 + CRTC4_CRTC_STATUS_POSITION :DWORD; // 0x43A4 + CRTC4_CRTC_NOM_VERT_POSITION :DWORD; // 0x43A5 + CRTC4_CRTC_STATUS_FRAME_COUNT :DWORD; // 0x43A6 + CRTC4_CRTC_STATUS_VF_COUNT :DWORD; // 0x43A7 + CRTC4_CRTC_STATUS_HV_COUNT :DWORD; // 0x43A8 + CRTC4_CRTC_COUNT_CONTROL :DWORD; // 0x43A9 + CRTC4_CRTC_COUNT_RESET :DWORD; // 0x43AA + CRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :DWORD; // 0x43AB + CRTC4_CRTC_VERT_SYNC_CONTROL :DWORD; // 0x43AC + CRTC4_CRTC_STEREO_STATUS :DWORD; // 0x43AD + CRTC4_CRTC_STEREO_CONTROL :DWORD; // 0x43AE + CRTC4_CRTC_SNAPSHOT_STATUS :DWORD; // 0x43AF + CRTC4_CRTC_SNAPSHOT_CONTROL :DWORD; // 0x43B0 + CRTC4_CRTC_SNAPSHOT_POSITION :DWORD; // 0x43B1 + CRTC4_CRTC_SNAPSHOT_FRAME :DWORD; // 0x43B2 + CRTC4_CRTC_START_LINE_CONTROL :DWORD; // 0x43B3 + CRTC4_CRTC_INTERRUPT_CONTROL :DWORD; // 0x43B4 + CRTC4_CRTC_UPDATE_LOCK :DWORD; // 0x43B5 + CRTC4_CRTC_DOUBLE_BUFFER_CONTROL :DWORD; // 0x43B6 + CRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE :DWORD; // 0x43B7 + CRTC4_DCFE_MEM_PWR_CTRL2 :DWORD; // 0x43B8 + CRTC4_DCFE_MEM_PWR_STATUS :DWORD; // 0x43B9 + CRTC4_CRTC_TEST_PATTERN_CONTROL :DWORD; // 0x43BA + CRTC4_CRTC_TEST_PATTERN_PARAMETERS :DWORD; // 0x43BB + CRTC4_CRTC_TEST_PATTERN_COLOR :DWORD; // 0x43BC + CRTC4_MASTER_UPDATE_LOCK :DWORD; // 0x43BD + CRTC4_MASTER_UPDATE_MODE :DWORD; // 0x43BE + CRTC4_CRTC_MVP_INBAND_CNTL_INSERT :DWORD; // 0x43BF + CRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :DWORD; // 0x43C0 + CRTC4_CRTC_MVP_STATUS :DWORD; // 0x43C1 + CRTC4_CRTC_MASTER_EN :DWORD; // 0x43C2 + CRTC4_CRTC_ALLOW_STOP_OFF_V_CNT :DWORD; // 0x43C3 + CRTC4_CRTC_V_UPDATE_INT_STATUS :DWORD; // 0x43C4 + REG_43C5 :DWORD; // 0x43C5 + CRTC4_CRTC_TEST_DEBUG_INDEX :DWORD; // 0x43C6 + CRTC4_CRTC_TEST_DEBUG_DATA :DWORD; // 0x43C7 + CRTC4_CRTC_OVERSCAN_COLOR :DWORD; // 0x43C8 + CRTC4_CRTC_OVERSCAN_COLOR_EXT :DWORD; // 0x43C9 + REG_43CA :DWORD; // 0x43CA + CRTC4_CRTC_BLANK_DATA_COLOR_EXT :DWORD; // 0x43CB + CRTC4_CRTC_BLACK_COLOR :DWORD; // 0x43CC + CRTC4_CRTC_BLACK_COLOR_EXT :DWORD; // 0x43CD + CRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION :DWORD; // 0x43CE + CRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL :DWORD; // 0x43CF + CRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION :DWORD; // 0x43D0 + CRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL :DWORD; // 0x43D1 + CRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION :DWORD; // 0x43D2 + CRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL :DWORD; // 0x43D3 + CRTC4_CRTC_CRC_CNTL :DWORD; // 0x43D4 + CRTC4_CRTC_CRC0_WINDOWA_X_CONTROL :DWORD; // 0x43D5 + CRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL :DWORD; // 0x43D6 + CRTC4_CRTC_CRC0_WINDOWB_X_CONTROL :DWORD; // 0x43D7 + CRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL :DWORD; // 0x43D8 + CRTC4_CRTC_CRC0_DATA_RG :DWORD; // 0x43D9 + CRTC4_CRTC_CRC0_DATA_B :DWORD; // 0x43DA + CRTC4_CRTC_CRC1_WINDOWA_X_CONTROL :DWORD; // 0x43DB + CRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL :DWORD; // 0x43DC + CRTC4_CRTC_CRC1_WINDOWB_X_CONTROL :DWORD; // 0x43DD + CRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL :DWORD; // 0x43DE + CRTC4_CRTC_CRC1_DATA_RG :DWORD; // 0x43DF + CRTC4_CRTC_CRC1_DATA_B :DWORD; // 0x43E0 + CRTC4_CRTC_EXT_TIMING_SYNC_CONTROL :DWORD; // 0x43E1 + CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START :DWORD; // 0x43E2 + CRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END :DWORD; // 0x43E3 + CRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :DWORD; // 0x43E4 + CRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :DWORD; // 0x43E5 + CRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :DWORD; // 0x43E6 + CRTC4_CRTC_STATIC_SCREEN_CONTROL :DWORD; // 0x43E7 + FMT4_FMT_CLAMP_COMPONENT_R :DWORD; // 0x43E8 + FMT4_FMT_CLAMP_COMPONENT_G :DWORD; // 0x43E9 + FMT4_FMT_CLAMP_COMPONENT_B :DWORD; // 0x43EA + FMT4_FMT_TEST_DEBUG_INDEX :DWORD; // 0x43EB + FMT4_FMT_TEST_DEBUG_DATA :DWORD; // 0x43EC + FMT4_FMT_DYNAMIC_EXP_CNTL :DWORD; // 0x43ED + FMT4_FMT_CONTROL :DWORD; // 0x43EE + FMT4_FMT_FORCE_OUTPUT_CNTL :DWORD; // 0x43EF + FMT4_FMT_FORCE_DATA_0_1 :DWORD; // 0x43F0 + FMT4_FMT_FORCE_DATA_2_3 :DWORD; // 0x43F1 + FMT4_FMT_BIT_DEPTH_CONTROL :DWORD; // 0x43F2 + FMT4_FMT_DITHER_RAND_R_SEED :DWORD; // 0x43F3 + FMT4_FMT_DITHER_RAND_G_SEED :DWORD; // 0x43F4 + FMT4_FMT_DITHER_RAND_B_SEED :DWORD; // 0x43F5 + FMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :DWORD; // 0x43F6 + FMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD; // 0x43F7 + FMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD; // 0x43F8 + FMT4_FMT_CLAMP_CNTL :DWORD; // 0x43F9 + FMT4_FMT_CRC_CNTL :DWORD; // 0x43FA + FMT4_FMT_CRC_SIG_RED_GREEN_MASK :DWORD; // 0x43FB + REG_43FC :DWORD; // 0x43FC + FMT4_FMT_CRC_SIG_RED_GREEN :DWORD; // 0x43FD + REG_43FE_43FF :array[0..1] of DWORD; // 0x43FE + DCP5_GRPH_ENABLE :DWORD; // 0x4400 + DCP5_GRPH_CONTROL :DWORD; // 0x4401 + DCP5_GRPH_LUT_10BIT_BYPASS :DWORD; // 0x4402 + DCP5_GRPH_SWAP_CNTL :DWORD; // 0x4403 + DCP5_GRPH_PRIMARY_SURFACE_ADDRESS :DWORD; // 0x4404 + DCP5_GRPH_SECONDARY_SURFACE_ADDRESS :DWORD; // 0x4405 + DCP5_GRPH_PITCH :DWORD; // 0x4406 + DCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4407 + DCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4408 + DCP5_GRPH_SURFACE_OFFSET_X :DWORD; // 0x4409 + DCP5_GRPH_SURFACE_OFFSET_Y :DWORD; // 0x440A + DCP5_GRPH_X_START :DWORD; // 0x440B + DCP5_GRPH_Y_START :DWORD; // 0x440C + DCP5_GRPH_X_END :DWORD; // 0x440D + DCP5_GRPH_Y_END :DWORD; // 0x440E + REG_440F :DWORD; // 0x440F + DCP5_INPUT_GAMMA_CONTROL :DWORD; // 0x4410 + DCP5_GRPH_UPDATE :DWORD; // 0x4411 + DCP5_GRPH_FLIP_CONTROL :DWORD; // 0x4412 + DCP5_GRPH_SURFACE_ADDRESS_INUSE :DWORD; // 0x4413 + DCP5_GRPH_DFQ_CONTROL :DWORD; // 0x4414 + DCP5_GRPH_DFQ_STATUS :DWORD; // 0x4415 + DCP5_GRPH_INTERRUPT_STATUS :DWORD; // 0x4416 + DCP5_GRPH_INTERRUPT_CONTROL :DWORD; // 0x4417 + DCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE :DWORD; // 0x4418 + DCP5_GRPH_COMPRESS_SURFACE_ADDRESS :DWORD; // 0x4419 + DCP5_GRPH_COMPRESS_PITCH :DWORD; // 0x441A + DCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH :DWORD; // 0x441B + DCP5_OVL_ENABLE :DWORD; // 0x441C + DCP5_OVL_CONTROL1 :DWORD; // 0x441D + DCP5_OVL_CONTROL2 :DWORD; // 0x441E + DCP5_OVL_SWAP_CNTL :DWORD; // 0x441F + DCP5_OVL_SURFACE_ADDRESS :DWORD; // 0x4420 + DCP5_OVL_PITCH :DWORD; // 0x4421 + DCP5_OVL_SURFACE_ADDRESS_HIGH :DWORD; // 0x4422 + DCP5_OVL_SURFACE_OFFSET_X :DWORD; // 0x4423 + DCP5_OVL_SURFACE_OFFSET_Y :DWORD; // 0x4424 + DCP5_OVL_START :DWORD; // 0x4425 + DCP5_OVL_END :DWORD; // 0x4426 + DCP5_OVL_UPDATE :DWORD; // 0x4427 + DCP5_OVL_SURFACE_ADDRESS_INUSE :DWORD; // 0x4428 + DCP5_OVL_DFQ_CONTROL :DWORD; // 0x4429 + DCP5_OVL_DFQ_STATUS :DWORD; // 0x442A + DCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE :DWORD; // 0x442B + DCP5_OVLSCL_EDGE_PIXEL_CNTL :DWORD; // 0x442C + DCP5_PRESCALE_GRPH_CONTROL :DWORD; // 0x442D + DCP5_PRESCALE_VALUES_GRPH_R :DWORD; // 0x442E + DCP5_PRESCALE_VALUES_GRPH_G :DWORD; // 0x442F + DCP5_PRESCALE_VALUES_GRPH_B :DWORD; // 0x4430 + DCP5_PRESCALE_OVL_CONTROL :DWORD; // 0x4431 + DCP5_PRESCALE_VALUES_OVL_CB :DWORD; // 0x4432 + DCP5_PRESCALE_VALUES_OVL_Y :DWORD; // 0x4433 + DCP5_PRESCALE_VALUES_OVL_CR :DWORD; // 0x4434 + DCP5_INPUT_CSC_CONTROL :DWORD; // 0x4435 + DCP5_INPUT_CSC_C11_C12 :DWORD; // 0x4436 + DCP5_INPUT_CSC_C13_C14 :DWORD; // 0x4437 + DCP5_INPUT_CSC_C21_C22 :DWORD; // 0x4438 + DCP5_INPUT_CSC_C23_C24 :DWORD; // 0x4439 + DCP5_INPUT_CSC_C31_C32 :DWORD; // 0x443A + DCP5_INPUT_CSC_C33_C34 :DWORD; // 0x443B + DCP5_OUTPUT_CSC_CONTROL :DWORD; // 0x443C + DCP5_OUTPUT_CSC_C11_C12 :DWORD; // 0x443D + DCP5_OUTPUT_CSC_C13_C14 :DWORD; // 0x443E + DCP5_OUTPUT_CSC_C21_C22 :DWORD; // 0x443F + DCP5_OUTPUT_CSC_C23_C24 :DWORD; // 0x4440 + DCP5_OUTPUT_CSC_C31_C32 :DWORD; // 0x4441 + DCP5_OUTPUT_CSC_C33_C34 :DWORD; // 0x4442 + DCP5_COMM_MATRIXA_TRANS_C11_C12 :DWORD; // 0x4443 + DCP5_COMM_MATRIXA_TRANS_C13_C14 :DWORD; // 0x4444 + DCP5_COMM_MATRIXA_TRANS_C21_C22 :DWORD; // 0x4445 + DCP5_COMM_MATRIXA_TRANS_C23_C24 :DWORD; // 0x4446 + DCP5_COMM_MATRIXA_TRANS_C31_C32 :DWORD; // 0x4447 + DCP5_COMM_MATRIXA_TRANS_C33_C34 :DWORD; // 0x4448 + DCP5_COMM_MATRIXB_TRANS_C11_C12 :DWORD; // 0x4449 + DCP5_COMM_MATRIXB_TRANS_C13_C14 :DWORD; // 0x444A + DCP5_COMM_MATRIXB_TRANS_C21_C22 :DWORD; // 0x444B + DCP5_COMM_MATRIXB_TRANS_C23_C24 :DWORD; // 0x444C + DCP5_COMM_MATRIXB_TRANS_C31_C32 :DWORD; // 0x444D + DCP5_COMM_MATRIXB_TRANS_C33_C34 :DWORD; // 0x444E + REG_444F :DWORD; // 0x444F + DCP5_DENORM_CONTROL :DWORD; // 0x4450 + DCP5_OUT_ROUND_CONTROL :DWORD; // 0x4451 + DCP5_OUT_CLAMP_CONTROL_R_CR :DWORD; // 0x4452 + DCP5_KEY_CONTROL :DWORD; // 0x4453 + DCP5_KEY_RANGE_ALPHA :DWORD; // 0x4454 + DCP5_KEY_RANGE_RED :DWORD; // 0x4455 + DCP5_KEY_RANGE_GREEN :DWORD; // 0x4456 + DCP5_KEY_RANGE_BLUE :DWORD; // 0x4457 + DCP5_DEGAMMA_CONTROL :DWORD; // 0x4458 + DCP5_GAMUT_REMAP_CONTROL :DWORD; // 0x4459 + DCP5_GAMUT_REMAP_C11_C12 :DWORD; // 0x445A + DCP5_GAMUT_REMAP_C13_C14 :DWORD; // 0x445B + DCP5_GAMUT_REMAP_C21_C22 :DWORD; // 0x445C + DCP5_GAMUT_REMAP_C23_C24 :DWORD; // 0x445D + DCP5_GAMUT_REMAP_C31_C32 :DWORD; // 0x445E + DCP5_GAMUT_REMAP_C33_C34 :DWORD; // 0x445F + DCP5_DCP_SPATIAL_DITHER_CNTL :DWORD; // 0x4460 + DCP5_DCP_RANDOM_SEEDS :DWORD; // 0x4461 + REG_4462_4464 :array[0..2] of DWORD; // 0x4462 + DCP5_DCP_FP_CONVERTED_FIELD :DWORD; // 0x4465 + DCP5_CUR_CONTROL :DWORD; // 0x4466 + DCP5_CUR_SURFACE_ADDRESS :DWORD; // 0x4467 + DCP5_CUR_SIZE :DWORD; // 0x4468 + DCP5_CUR_SURFACE_ADDRESS_HIGH :DWORD; // 0x4469 + DCP5_CUR_POSITION :DWORD; // 0x446A + DCP5_CUR_HOT_SPOT :DWORD; // 0x446B + DCP5_CUR_COLOR1 :DWORD; // 0x446C + DCP5_CUR_COLOR2 :DWORD; // 0x446D + DCP5_CUR_UPDATE :DWORD; // 0x446E + DCP5_CUR2_CONTROL :DWORD; // 0x446F + DCP5_CUR2_SURFACE_ADDRESS :DWORD; // 0x4470 + DCP5_CUR2_SIZE :DWORD; // 0x4471 + DCP5_CUR2_SURFACE_ADDRESS_HIGH :DWORD; // 0x4472 + DCP5_CUR2_POSITION :DWORD; // 0x4473 + DCP5_CUR2_HOT_SPOT :DWORD; // 0x4474 + DCP5_CUR2_COLOR1 :DWORD; // 0x4475 + DCP5_CUR2_COLOR2 :DWORD; // 0x4476 + DCP5_CUR2_UPDATE :DWORD; // 0x4477 + DCP5_DC_LUT_RW_MODE :DWORD; // 0x4478 + DCP5_DC_LUT_RW_INDEX :DWORD; // 0x4479 + DCP5_DC_LUT_SEQ_COLOR :DWORD; // 0x447A + DCP5_DC_LUT_PWL_DATA :DWORD; // 0x447B + DCP5_DC_LUT_30_COLOR :DWORD; // 0x447C + DCP5_DC_LUT_VGA_ACCESS_ENABLE :DWORD; // 0x447D + DCP5_DC_LUT_WRITE_EN_MASK :DWORD; // 0x447E + DCP5_DC_LUT_AUTOFILL :DWORD; // 0x447F + DCP5_DC_LUT_CONTROL :DWORD; // 0x4480 + DCP5_DC_LUT_BLACK_OFFSET_BLUE :DWORD; // 0x4481 + DCP5_DC_LUT_BLACK_OFFSET_GREEN :DWORD; // 0x4482 + DCP5_DC_LUT_BLACK_OFFSET_RED :DWORD; // 0x4483 + DCP5_DC_LUT_WHITE_OFFSET_BLUE :DWORD; // 0x4484 + DCP5_DC_LUT_WHITE_OFFSET_GREEN :DWORD; // 0x4485 + DCP5_DC_LUT_WHITE_OFFSET_RED :DWORD; // 0x4486 + DCP5_DCP_CRC_CONTROL :DWORD; // 0x4487 + DCP5_DCP_CRC_MASK :DWORD; // 0x4488 + DCP5_DCP_CRC_CURRENT :DWORD; // 0x4489 + REG_448A :DWORD; // 0x448A + DCP5_DCP_CRC_LAST :DWORD; // 0x448B + REG_448C :DWORD; // 0x448C + DCP5_DCP_DEBUG :DWORD; // 0x448D + DCP5_GRPH_FLIP_RATE_CNTL :DWORD; // 0x448E + REG_448F :DWORD; // 0x448F + DCP5_DCP_GSL_CONTROL :DWORD; // 0x4490 + DCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK :DWORD; // 0x4491 + DCP5_OVL_SECONDARY_SURFACE_ADDRESS :DWORD; // 0x4492 + DCP5_OVL_STEREOSYNC_FLIP :DWORD; // 0x4493 + DCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :DWORD; // 0x4494 + DCP5_DCP_TEST_DEBUG_INDEX :DWORD; // 0x4495 + DCP5_DCP_TEST_DEBUG_DATA :DWORD; // 0x4496 + DCP5_GRPH_STEREOSYNC_FLIP :DWORD; // 0x4497 + DCP5_DCP_DEBUG2 :DWORD; // 0x4498 + DCP5_CUR_REQUEST_FILTER_CNTL :DWORD; // 0x4499 + DCP5_CUR_STEREO_CONTROL :DWORD; // 0x449A + DCP5_CUR2_STEREO_CONTROL :DWORD; // 0x449B + DCP5_OUT_CLAMP_CONTROL_G_Y :DWORD; // 0x449C + DCP5_OUT_CLAMP_CONTROL_B_CB :DWORD; // 0x449D + DCP5_HW_ROTATION :DWORD; // 0x449E + DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :DWORD; // 0x449F + DCP5_REGAMMA_CONTROL :DWORD; // 0x44A0 + DCP5_REGAMMA_LUT_INDEX :DWORD; // 0x44A1 + DCP5_REGAMMA_LUT_DATA :DWORD; // 0x44A2 + DCP5_REGAMMA_LUT_WRITE_EN_MASK :DWORD; // 0x44A3 + DCP5_REGAMMA_CNTLA_START_CNTL :DWORD; // 0x44A4 + DCP5_REGAMMA_CNTLA_SLOPE_CNTL :DWORD; // 0x44A5 + DCP5_REGAMMA_CNTLA_END_CNTL1 :DWORD; // 0x44A6 + DCP5_REGAMMA_CNTLA_END_CNTL2 :DWORD; // 0x44A7 + DCP5_REGAMMA_CNTLA_REGION_0_1 :DWORD; // 0x44A8 + DCP5_REGAMMA_CNTLA_REGION_2_3 :DWORD; // 0x44A9 + DCP5_REGAMMA_CNTLA_REGION_4_5 :DWORD; // 0x44AA + DCP5_REGAMMA_CNTLA_REGION_6_7 :DWORD; // 0x44AB + DCP5_REGAMMA_CNTLA_REGION_8_9 :DWORD; // 0x44AC + DCP5_REGAMMA_CNTLA_REGION_10_11 :DWORD; // 0x44AD + DCP5_REGAMMA_CNTLA_REGION_12_13 :DWORD; // 0x44AE + DCP5_REGAMMA_CNTLA_REGION_14_15 :DWORD; // 0x44AF + DCP5_REGAMMA_CNTLB_START_CNTL :DWORD; // 0x44B0 + DCP5_REGAMMA_CNTLB_SLOPE_CNTL :DWORD; // 0x44B1 + DCP5_REGAMMA_CNTLB_END_CNTL1 :DWORD; // 0x44B2 + DCP5_REGAMMA_CNTLB_END_CNTL2 :DWORD; // 0x44B3 + DCP5_REGAMMA_CNTLB_REGION_0_1 :DWORD; // 0x44B4 + DCP5_REGAMMA_CNTLB_REGION_2_3 :DWORD; // 0x44B5 + DCP5_REGAMMA_CNTLB_REGION_4_5 :DWORD; // 0x44B6 + DCP5_REGAMMA_CNTLB_REGION_6_7 :DWORD; // 0x44B7 + DCP5_REGAMMA_CNTLB_REGION_8_9 :DWORD; // 0x44B8 + DCP5_REGAMMA_CNTLB_REGION_10_11 :DWORD; // 0x44B9 + DCP5_REGAMMA_CNTLB_REGION_12_13 :DWORD; // 0x44BA + DCP5_REGAMMA_CNTLB_REGION_14_15 :DWORD; // 0x44BB + DCP5_ALPHA_CONTROL :DWORD; // 0x44BC + DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :DWORD; // 0x44BD + DCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :DWORD; // 0x44BE + DCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :DWORD; // 0x44BF + LB5_LB_DATA_FORMAT :DWORD; // 0x44C0 + LB5_LB_MEMORY_CTRL :DWORD; // 0x44C1 + LB5_LB_MEMORY_SIZE_STATUS :DWORD; // 0x44C2 + LB5_LB_DESKTOP_HEIGHT :DWORD; // 0x44C3 + LB5_LB_VLINE_START_END :DWORD; // 0x44C4 + LB5_LB_VLINE2_START_END :DWORD; // 0x44C5 + LB5_LB_V_COUNTER :DWORD; // 0x44C6 + LB5_LB_SNAPSHOT_V_COUNTER :DWORD; // 0x44C7 + LB5_LB_INTERRUPT_MASK :DWORD; // 0x44C8 + LB5_LB_VLINE_STATUS :DWORD; // 0x44C9 + LB5_LB_VLINE2_STATUS :DWORD; // 0x44CA + LB5_LB_VBLANK_STATUS :DWORD; // 0x44CB + LB5_LB_SYNC_RESET_SEL :DWORD; // 0x44CC + LB5_LB_BLACK_KEYER_R_CR :DWORD; // 0x44CD + LB5_LB_BLACK_KEYER_G_Y :DWORD; // 0x44CE + LB5_LB_BLACK_KEYER_B_CB :DWORD; // 0x44CF + LB5_LB_KEYER_COLOR_CTRL :DWORD; // 0x44D0 + LB5_LB_KEYER_COLOR_R_CR :DWORD; // 0x44D1 + LB5_LB_KEYER_COLOR_G_Y :DWORD; // 0x44D2 + LB5_LB_KEYER_COLOR_B_CB :DWORD; // 0x44D3 + LB5_LB_KEYER_COLOR_REP_R_CR :DWORD; // 0x44D4 + LB5_LB_KEYER_COLOR_REP_G_Y :DWORD; // 0x44D5 + LB5_LB_KEYER_COLOR_REP_B_CB :DWORD; // 0x44D6 + LB5_LB_BUFFER_LEVEL_STATUS :DWORD; // 0x44D7 + LB5_LB_BUFFER_URGENCY_CTRL :DWORD; // 0x44D8 + LB5_LB_BUFFER_URGENCY_STATUS :DWORD; // 0x44D9 + LB5_LB_BUFFER_STATUS :DWORD; // 0x44DA + REG_44DB :DWORD; // 0x44DB + LB5_LB_NO_OUTSTANDING_REQ_STATUS :DWORD; // 0x44DC + REG_44DD_44DF :array[0..2] of DWORD; // 0x44DD + LB5_MVP_AFR_FLIP_MODE :DWORD; // 0x44E0 + LB5_MVP_AFR_FLIP_FIFO_CNTL :DWORD; // 0x44E1 + LB5_MVP_FLIP_LINE_NUM_INSERT :DWORD; // 0x44E2 + LB5_DC_MVP_LB_CONTROL :DWORD; // 0x44E3 + LB5_LB_DEBUG :DWORD; // 0x44E4 + LB5_LB_DEBUG2 :DWORD; // 0x44E5 + LB5_LB_DEBUG3 :DWORD; // 0x44E6 + REG_44E7_44FD :array[0..22] of DWORD; // 0x44E7 + LB5_LB_TEST_DEBUG_INDEX :DWORD; // 0x44FE + LB5_LB_TEST_DEBUG_DATA :DWORD; // 0x44FF + DCFE5_DCFE_CLOCK_CONTROL :DWORD; // 0x4500 + DCFE5_DCFE_SOFT_RESET :DWORD; // 0x4501 + DCFE5_DCFE_DBG_CONFIG :DWORD; // 0x4502 + REG_4503_4512 :array[0..15] of DWORD; // 0x4503 + DIG3_HDMI_GENERIC_PACKET_CONTROL :DWORD; // 0x4513 + REG_4514_4523 :array[0..15] of DWORD; // 0x4514 + DC_PERFMON8_PERFCOUNTER_CNTL :DWORD; // 0x4524 + DC_PERFMON8_PERFCOUNTER_STATE :DWORD; // 0x4525 + DC_PERFMON8_PERFMON_CVALUE_INT_MISC :DWORD; // 0x4526 + DC_PERFMON8_PERFMON_CNTL :DWORD; // 0x4527 + DC_PERFMON8_PERFMON_CVALUE_LOW :DWORD; // 0x4528 + DC_PERFMON8_PERFMON_HI :DWORD; // 0x4529 + DC_PERFMON8_PERFMON_LOW :DWORD; // 0x452A + DC_PERFMON8_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x452B + DC_PERFMON8_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x452C + REG_452D :DWORD; // 0x452D + DC_PERFMON8_PERFMON_CNTL2 :DWORD; // 0x452E + REG_452F :DWORD; // 0x452F + DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 :DWORD; // 0x4530 + DMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 :DWORD; // 0x4531 + DMIF_PG5_DPG_WATERMARK_MASK_CONTROL :DWORD; // 0x4532 + DMIF_PG5_DPG_PIPE_URGENCY_CONTROL :DWORD; // 0x4533 + DMIF_PG5_DPG_PIPE_DPM_CONTROL :DWORD; // 0x4534 + DMIF_PG5_DPG_PIPE_STUTTER_CONTROL :DWORD; // 0x4535 + DMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :DWORD; // 0x4536 + DMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :DWORD; // 0x4537 + DMIF_PG5_DPG_TEST_DEBUG_INDEX :DWORD; // 0x4538 + DMIF_PG5_DPG_TEST_DEBUG_DATA :DWORD; // 0x4539 + DMIF_PG5_DPG_REPEATER_PROGRAM :DWORD; // 0x453A + DMIF_PG5_DPG_HW_DEBUG_A :DWORD; // 0x453B + DMIF_PG5_DPG_HW_DEBUG_B :DWORD; // 0x453C + DMIF_PG5_DPG_HW_DEBUG_11 :DWORD; // 0x453D + REG_453E_453F :array[0..1] of DWORD; // 0x453E + SCL5_SCL_COEF_RAM_SELECT :DWORD; // 0x4540 + SCL5_SCL_COEF_RAM_TAP_DATA :DWORD; // 0x4541 + SCL5_SCL_MODE :DWORD; // 0x4542 + SCL5_SCL_TAP_CONTROL :DWORD; // 0x4543 + SCL5_SCL_CONTROL :DWORD; // 0x4544 + SCL5_SCL_BYPASS_CONTROL :DWORD; // 0x4545 + SCL5_SCL_MANUAL_REPLICATE_CONTROL :DWORD; // 0x4546 + SCL5_SCL_AUTOMATIC_MODE_CONTROL :DWORD; // 0x4547 + SCL5_SCL_HORZ_FILTER_CONTROL :DWORD; // 0x4548 + SCL5_SCL_HORZ_FILTER_SCALE_RATIO :DWORD; // 0x4549 + SCL5_SCL_HORZ_FILTER_INIT :DWORD; // 0x454A + SCL5_SCL_VERT_FILTER_CONTROL :DWORD; // 0x454B + SCL5_SCL_VERT_FILTER_SCALE_RATIO :DWORD; // 0x454C + SCL5_SCL_VERT_FILTER_INIT :DWORD; // 0x454D + SCL5_SCL_VERT_FILTER_INIT_BOT :DWORD; // 0x454E + SCL5_SCL_ROUND_OFFSET :DWORD; // 0x454F + REG_4550 :DWORD; // 0x4550 + SCL5_SCL_UPDATE :DWORD; // 0x4551 + REG_4552 :DWORD; // 0x4552 + SCL5_SCL_F_SHARP_CONTROL :DWORD; // 0x4553 + SCL5_SCL_ALU_CONTROL :DWORD; // 0x4554 + SCL5_SCL_COEF_RAM_CONFLICT_STATUS :DWORD; // 0x4555 + REG_4556_455A :array[0..4] of DWORD; // 0x4556 + SCL5_VIEWPORT_START_SECONDARY :DWORD; // 0x455B + SCL5_VIEWPORT_START :DWORD; // 0x455C + SCL5_VIEWPORT_SIZE :DWORD; // 0x455D + SCL5_EXT_OVERSCAN_LEFT_RIGHT :DWORD; // 0x455E + SCL5_EXT_OVERSCAN_TOP_BOTTOM :DWORD; // 0x455F + SCL5_SCL_MODE_CHANGE_DET1 :DWORD; // 0x4560 + SCL5_SCL_MODE_CHANGE_DET2 :DWORD; // 0x4561 + SCL5_SCL_MODE_CHANGE_DET3 :DWORD; // 0x4562 + SCL5_SCL_MODE_CHANGE_MASK :DWORD; // 0x4563 + REG_4564_4568 :array[0..4] of DWORD; // 0x4564 + SCL5_SCL_DEBUG2 :DWORD; // 0x4569 + SCL5_SCL_DEBUG :DWORD; // 0x456A + SCL5_SCL_TEST_DEBUG_INDEX :DWORD; // 0x456B + SCL5_SCL_TEST_DEBUG_DATA :DWORD; // 0x456C + BLND5_BLND_CONTROL :DWORD; // 0x456D + BLND5_SM_CONTROL2 :DWORD; // 0x456E + BLND5_BLND_CONTROL2 :DWORD; // 0x456F + BLND5_BLND_UPDATE :DWORD; // 0x4570 + BLND5_BLND_UNDERFLOW_INTERRUPT :DWORD; // 0x4571 + REG_4572 :DWORD; // 0x4572 + BLND5_BLND_V_UPDATE_LOCK :DWORD; // 0x4573 + BLND5_BLND_DEBUG :DWORD; // 0x4574 + BLND5_BLND_TEST_DEBUG_INDEX :DWORD; // 0x4575 + BLND5_BLND_TEST_DEBUG_DATA :DWORD; // 0x4576 + BLND5_BLND_REG_UPDATE_STATUS :DWORD; // 0x4577 + CRTC5_CRTC_3D_STRUCTURE_CONTROL :DWORD; // 0x4578 + CRTC5_CRTC_GSL_VSYNC_GAP :DWORD; // 0x4579 + CRTC5_CRTC_GSL_WINDOW :DWORD; // 0x457A + CRTC5_CRTC_GSL_CONTROL :DWORD; // 0x457B + CRTC5_CRTC_DCFE_CLOCK_CONTROL :DWORD; // 0x457C + CRTC5_CRTC_H_BLANK_EARLY_NUM :DWORD; // 0x457D + CRTC5_DCFE_DBG_SEL :DWORD; // 0x457E + CRTC5_DCFE_MEM_PWR_CTRL :DWORD; // 0x457F + REG_4580_4584 :array[0..4] of DWORD; // 0x4580 + CRTC5_CRTC_H_SYNC_B_CNTL :DWORD; // 0x4585 + REG_4586_4587 :array[0..1] of DWORD; // 0x4586 + CRTC5_CRTC_V_TOTAL_MIN :DWORD; // 0x4588 + CRTC5_CRTC_V_TOTAL_MAX :DWORD; // 0x4589 + CRTC5_CRTC_V_TOTAL_CONTROL :DWORD; // 0x458A + CRTC5_CRTC_V_TOTAL_INT_STATUS :DWORD; // 0x458B + REG_458C :DWORD; // 0x458C + CRTC5_CRTC_V_BLANK_START_END :DWORD; // 0x458D + CRTC5_CRTC_V_SYNC_A :DWORD; // 0x458E + CRTC5_CRTC_V_SYNC_A_CNTL :DWORD; // 0x458F + CRTC5_CRTC_V_SYNC_B :DWORD; // 0x4590 + CRTC5_CRTC_V_SYNC_B_CNTL :DWORD; // 0x4591 + CRTC5_CRTC_DTMTEST_CNTL :DWORD; // 0x4592 + CRTC5_CRTC_DTMTEST_STATUS_POSITION :DWORD; // 0x4593 + CRTC5_CRTC_TRIGA_CNTL :DWORD; // 0x4594 + CRTC5_CRTC_TRIGA_MANUAL_TRIG :DWORD; // 0x4595 + CRTC5_CRTC_TRIGB_CNTL :DWORD; // 0x4596 + CRTC5_CRTC_TRIGB_MANUAL_TRIG :DWORD; // 0x4597 + CRTC5_CRTC_FORCE_COUNT_NOW_CNTL :DWORD; // 0x4598 + CRTC5_CRTC_FLOW_CONTROL :DWORD; // 0x4599 + CRTC5_CRTC_STEREO_FORCE_NEXT_EYE :DWORD; // 0x459A + CRTC5_CRTC_AVSYNC_COUNTER :DWORD; // 0x459B + CRTC5_CRTC_CONTROL :DWORD; // 0x459C + CRTC5_CRTC_BLANK_CONTROL :DWORD; // 0x459D + CRTC5_CRTC_INTERLACE_CONTROL :DWORD; // 0x459E + CRTC5_CRTC_INTERLACE_STATUS :DWORD; // 0x459F + CRTC5_CRTC_FIELD_INDICATION_CONTROL :DWORD; // 0x45A0 + CRTC5_CRTC_PIXEL_DATA_READBACK0 :DWORD; // 0x45A1 + CRTC5_CRTC_PIXEL_DATA_READBACK1 :DWORD; // 0x45A2 + CRTC5_CRTC_STATUS :DWORD; // 0x45A3 + CRTC5_CRTC_STATUS_POSITION :DWORD; // 0x45A4 + REG_45A5_45AA :array[0..5] of DWORD; // 0x45A5 + CRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :DWORD; // 0x45AB + CRTC5_CRTC_VERT_SYNC_CONTROL :DWORD; // 0x45AC + CRTC5_CRTC_STEREO_STATUS :DWORD; // 0x45AD + CRTC5_CRTC_STEREO_CONTROL :DWORD; // 0x45AE + CRTC5_CRTC_SNAPSHOT_STATUS :DWORD; // 0x45AF + CRTC5_CRTC_SNAPSHOT_CONTROL :DWORD; // 0x45B0 + CRTC5_CRTC_SNAPSHOT_POSITION :DWORD; // 0x45B1 + CRTC5_CRTC_SNAPSHOT_FRAME :DWORD; // 0x45B2 + CRTC5_CRTC_START_LINE_CONTROL :DWORD; // 0x45B3 + CRTC5_CRTC_INTERRUPT_CONTROL :DWORD; // 0x45B4 + CRTC5_CRTC_UPDATE_LOCK :DWORD; // 0x45B5 + CRTC5_CRTC_DOUBLE_BUFFER_CONTROL :DWORD; // 0x45B6 + CRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE :DWORD; // 0x45B7 + CRTC5_DCFE_MEM_PWR_CTRL2 :DWORD; // 0x45B8 + CRTC5_DCFE_MEM_PWR_STATUS :DWORD; // 0x45B9 + CRTC5_CRTC_TEST_PATTERN_CONTROL :DWORD; // 0x45BA + CRTC5_CRTC_TEST_PATTERN_PARAMETERS :DWORD; // 0x45BB + CRTC5_CRTC_TEST_PATTERN_COLOR :DWORD; // 0x45BC + CRTC5_MASTER_UPDATE_LOCK :DWORD; // 0x45BD + CRTC5_MASTER_UPDATE_MODE :DWORD; // 0x45BE + CRTC5_CRTC_MVP_INBAND_CNTL_INSERT :DWORD; // 0x45BF + REG_45C0_45C5 :array[0..5] of DWORD; // 0x45C0 + CRTC5_CRTC_TEST_DEBUG_INDEX :DWORD; // 0x45C6 + CRTC5_CRTC_TEST_DEBUG_DATA :DWORD; // 0x45C7 + CRTC5_CRTC_OVERSCAN_COLOR :DWORD; // 0x45C8 + CRTC5_CRTC_OVERSCAN_COLOR_EXT :DWORD; // 0x45C9 + REG_45CA :DWORD; // 0x45CA + CRTC5_CRTC_BLANK_DATA_COLOR_EXT :DWORD; // 0x45CB + CRTC5_CRTC_BLACK_COLOR :DWORD; // 0x45CC + CRTC5_CRTC_BLACK_COLOR_EXT :DWORD; // 0x45CD + CRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION :DWORD; // 0x45CE + CRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL :DWORD; // 0x45CF + CRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION :DWORD; // 0x45D0 + CRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL :DWORD; // 0x45D1 + CRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION :DWORD; // 0x45D2 + CRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL :DWORD; // 0x45D3 + CRTC5_CRTC_CRC_CNTL :DWORD; // 0x45D4 + CRTC5_CRTC_CRC0_WINDOWA_X_CONTROL :DWORD; // 0x45D5 + CRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL :DWORD; // 0x45D6 + CRTC5_CRTC_CRC0_WINDOWB_X_CONTROL :DWORD; // 0x45D7 + CRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL :DWORD; // 0x45D8 + CRTC5_CRTC_CRC0_DATA_RG :DWORD; // 0x45D9 + CRTC5_CRTC_CRC0_DATA_B :DWORD; // 0x45DA + CRTC5_CRTC_CRC1_WINDOWA_X_CONTROL :DWORD; // 0x45DB + CRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL :DWORD; // 0x45DC + CRTC5_CRTC_CRC1_WINDOWB_X_CONTROL :DWORD; // 0x45DD + CRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL :DWORD; // 0x45DE + CRTC5_CRTC_CRC1_DATA_RG :DWORD; // 0x45DF + CRTC5_CRTC_CRC1_DATA_B :DWORD; // 0x45E0 + CRTC5_CRTC_EXT_TIMING_SYNC_CONTROL :DWORD; // 0x45E1 + CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START :DWORD; // 0x45E2 + CRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END :DWORD; // 0x45E3 + CRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :DWORD; // 0x45E4 + CRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :DWORD; // 0x45E5 + CRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :DWORD; // 0x45E6 + CRTC5_CRTC_STATIC_SCREEN_CONTROL :DWORD; // 0x45E7 + FMT5_FMT_CLAMP_COMPONENT_R :DWORD; // 0x45E8 + FMT5_FMT_CLAMP_COMPONENT_G :DWORD; // 0x45E9 + FMT5_FMT_CLAMP_COMPONENT_B :DWORD; // 0x45EA + FMT5_FMT_TEST_DEBUG_INDEX :DWORD; // 0x45EB + FMT5_FMT_TEST_DEBUG_DATA :DWORD; // 0x45EC + FMT5_FMT_DYNAMIC_EXP_CNTL :DWORD; // 0x45ED + FMT5_FMT_CONTROL :DWORD; // 0x45EE + FMT5_FMT_FORCE_OUTPUT_CNTL :DWORD; // 0x45EF + FMT5_FMT_FORCE_DATA_0_1 :DWORD; // 0x45F0 + FMT5_FMT_FORCE_DATA_2_3 :DWORD; // 0x45F1 + FMT5_FMT_BIT_DEPTH_CONTROL :DWORD; // 0x45F2 + FMT5_FMT_DITHER_RAND_R_SEED :DWORD; // 0x45F3 + FMT5_FMT_DITHER_RAND_G_SEED :DWORD; // 0x45F4 + FMT5_FMT_DITHER_RAND_B_SEED :DWORD; // 0x45F5 + FMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :DWORD; // 0x45F6 + FMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :DWORD; // 0x45F7 + FMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :DWORD; // 0x45F8 + FMT5_FMT_CLAMP_CNTL :DWORD; // 0x45F9 + FMT5_FMT_CRC_CNTL :DWORD; // 0x45FA + FMT5_FMT_CRC_SIG_RED_GREEN_MASK :DWORD; // 0x45FB + FMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK :DWORD; // 0x45FC + FMT5_FMT_CRC_SIG_RED_GREEN :DWORD; // 0x45FD + FMT5_FMT_CRC_SIG_BLUE_CONTROL :DWORD; // 0x45FE + FMT5_FMT_DEBUG_CNTL :DWORD; // 0x45FF + UNP_GRPH_ENABLE :TUNP_GRPH_ENABLE; // 0x4600 + UNP_GRPH_CONTROL :TUNP_GRPH_CONTROL; // 0x4601 + REG_4602 :DWORD; // 0x4602 + UNP_GRPH_CONTROL_EXP :TUNP_GRPH_CONTROL_EXP; // 0x4603 + REG_4604 :DWORD; // 0x4604 + UNP_GRPH_SWAP_CNTL :TUNP_GRPH_SWAP_CNTL; // 0x4605 + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L; // 0x4606 + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C; // 0x4607 + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L; // 0x4608 + UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C :TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C; // 0x4609 + UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L; // 0x460A + UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C; // 0x460B + UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L; // 0x460C + UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C :TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C; // 0x460D + UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L; // 0x460E + UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C; // 0x460F + UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L; // 0x4610 + UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C :TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C; // 0x4611 + UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L; // 0x4612 + UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C; // 0x4613 + UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L; // 0x4614 + UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C :TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C; // 0x4615 + UNP_GRPH_PITCH_L :TUNP_GRPH_PITCH_L; // 0x4616 + UNP_GRPH_PITCH_C :TUNP_GRPH_PITCH_C; // 0x4617 + UNP_GRPH_SURFACE_OFFSET_X_L :TUNP_GRPH_SURFACE_OFFSET_X_L; // 0x4618 + UNP_GRPH_SURFACE_OFFSET_X_C :TUNP_GRPH_SURFACE_OFFSET_X_C; // 0x4619 + UNP_GRPH_SURFACE_OFFSET_Y_L :TUNP_GRPH_SURFACE_OFFSET_Y_L; // 0x461A + UNP_GRPH_SURFACE_OFFSET_Y_C :TUNP_GRPH_SURFACE_OFFSET_Y_C; // 0x461B + UNP_GRPH_X_START_L :TUNP_GRPH_X_START_L; // 0x461C + UNP_GRPH_X_START_C :TUNP_GRPH_X_START_C; // 0x461D + UNP_GRPH_Y_START_L :TUNP_GRPH_Y_START_L; // 0x461E + UNP_GRPH_Y_START_C :TUNP_GRPH_Y_START_C; // 0x461F + UNP_GRPH_X_END_L :TUNP_GRPH_X_END_L; // 0x4620 + UNP_GRPH_X_END_C :TUNP_GRPH_X_END_C; // 0x4621 + UNP_GRPH_Y_END_L :TUNP_GRPH_Y_END_L; // 0x4622 + UNP_GRPH_Y_END_C :TUNP_GRPH_Y_END_C; // 0x4623 + UNP_GRPH_UPDATE :TUNP_GRPH_UPDATE; // 0x4624 + UNP_GRPH_SURFACE_ADDRESS_INUSE_L :TUNP_GRPH_SURFACE_ADDRESS_INUSE_L; // 0x4625 + UNP_GRPH_SURFACE_ADDRESS_INUSE_C :TUNP_GRPH_SURFACE_ADDRESS_INUSE_C; // 0x4626 + UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L :TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L; // 0x4627 + UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C :TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C; // 0x4628 + UNP_GRPH_DFQ_CONTROL :TUNP_GRPH_DFQ_CONTROL; // 0x4629 + UNP_GRPH_DFQ_STATUS :TUNP_GRPH_DFQ_STATUS; // 0x462A + UNP_GRPH_INTERRUPT_STATUS :TUNP_GRPH_INTERRUPT_STATUS; // 0x462B + UNP_GRPH_INTERRUPT_CONTROL :TUNP_GRPH_INTERRUPT_CONTROL; // 0x462C + REG_462D :DWORD; // 0x462D + UNP_GRPH_STEREOSYNC_FLIP :TUNP_GRPH_STEREOSYNC_FLIP; // 0x462E + UNP_GRPH_FLIP_RATE_CNTL :TUNP_GRPH_FLIP_RATE_CNTL; // 0x462F + UNP_CRC_CONTROL :TUNP_CRC_CONTROL; // 0x4630 + UNP_CRC_MASK :TUNP_CRC_MASK; // 0x4631 + UNP_CRC_CURRENT :TUNP_CRC_CURRENT; // 0x4632 + UNP_CRC_LAST :TUNP_CRC_LAST; // 0x4633 + UNP_LB_DATA_GAP_BETWEEN_CHUNK :TUNP_LB_DATA_GAP_BETWEEN_CHUNK; // 0x4634 + UNP_HW_ROTATION :TUNP_HW_ROTATION; // 0x4635 + UNP_DEBUG :TUNP_DEBUG; // 0x4636 + UNP_DEBUG2 :TUNP_DEBUG2; // 0x4637 + UNP_TEST_DEBUG_INDEX :TUNP_TEST_DEBUG_INDEX; // 0x4638 + UNP_TEST_DEBUG_DATA :TUNP_TEST_DEBUG_DATA; // 0x4639 + REG_463A_463B :array[0..1] of DWORD; // 0x463A + LBV_DATA_FORMAT :TLBV_DATA_FORMAT; // 0x463C + LBV_MEMORY_CTRL :TLBV_MEMORY_CTRL; // 0x463D + LBV_MEMORY_SIZE_STATUS :TLBV_MEMORY_SIZE_STATUS; // 0x463E + LBV_DESKTOP_HEIGHT :TLBV_DESKTOP_HEIGHT; // 0x463F + LBV_VLINE_START_END :TLBV_VLINE_START_END; // 0x4640 + LBV_VLINE2_START_END :TLBV_VLINE2_START_END; // 0x4641 + LBV_V_COUNTER :TLBV_V_COUNTER; // 0x4642 + LBV_SNAPSHOT_V_COUNTER :TLBV_SNAPSHOT_V_COUNTER; // 0x4643 + LBV_V_COUNTER_CHROMA :TLBV_V_COUNTER_CHROMA; // 0x4644 + LBV_SNAPSHOT_V_COUNTER_CHROMA :TLBV_SNAPSHOT_V_COUNTER_CHROMA; // 0x4645 + LBV_INTERRUPT_MASK :TLBV_INTERRUPT_MASK; // 0x4646 + LBV_VLINE_STATUS :TLBV_VLINE_STATUS; // 0x4647 + LBV_VLINE2_STATUS :TLBV_VLINE2_STATUS; // 0x4648 + LBV_VBLANK_STATUS :TLBV_VBLANK_STATUS; // 0x4649 + LBV_SYNC_RESET_SEL :TLBV_SYNC_RESET_SEL; // 0x464A + LBV_BLACK_KEYER_R_CR :TLBV_BLACK_KEYER_R_CR; // 0x464B + LBV_BLACK_KEYER_G_Y :TLBV_BLACK_KEYER_G_Y; // 0x464C + LBV_BLACK_KEYER_B_CB :TLBV_BLACK_KEYER_B_CB; // 0x464D + LBV_KEYER_COLOR_CTRL :TLBV_KEYER_COLOR_CTRL; // 0x464E + LBV_KEYER_COLOR_R_CR :TLBV_KEYER_COLOR_R_CR; // 0x464F + LBV_KEYER_COLOR_G_Y :TLBV_KEYER_COLOR_G_Y; // 0x4650 + LBV_KEYER_COLOR_B_CB :TLBV_KEYER_COLOR_B_CB; // 0x4651 + LBV_KEYER_COLOR_REP_R_CR :TLBV_KEYER_COLOR_REP_R_CR; // 0x4652 + LBV_KEYER_COLOR_REP_G_Y :TLBV_KEYER_COLOR_REP_G_Y; // 0x4653 + LBV_KEYER_COLOR_REP_B_CB :TLBV_KEYER_COLOR_REP_B_CB; // 0x4654 + LBV_BUFFER_LEVEL_STATUS :TLBV_BUFFER_LEVEL_STATUS; // 0x4655 + LBV_BUFFER_URGENCY_CTRL :TLBV_BUFFER_URGENCY_CTRL; // 0x4656 + LBV_BUFFER_URGENCY_STATUS :TLBV_BUFFER_URGENCY_STATUS; // 0x4657 + LBV_BUFFER_STATUS :TLBV_BUFFER_STATUS; // 0x4658 + LBV_NO_OUTSTANDING_REQ_STATUS :TLBV_NO_OUTSTANDING_REQ_STATUS; // 0x4659 + LBV_DEBUG :TLBV_DEBUG; // 0x465A + LBV_DEBUG2 :TLBV_DEBUG2; // 0x465B + LBV_DEBUG3 :TLBV_DEBUG3; // 0x465C + REG_465D_4665 :array[0..8] of DWORD; // 0x465D + LBV_TEST_DEBUG_INDEX :TLBV_TEST_DEBUG_INDEX; // 0x4666 + LBV_TEST_DEBUG_DATA :TLBV_TEST_DEBUG_DATA; // 0x4667 + REG_4668_466F :array[0..7] of DWORD; // 0x4668 + SCLV_COEF_RAM_SELECT :TSCLV_COEF_RAM_SELECT; // 0x4670 + SCLV_COEF_RAM_TAP_DATA :TSCLV_COEF_RAM_TAP_DATA; // 0x4671 + SCLV_MODE :TSCLV_MODE; // 0x4672 + SCLV_TAP_CONTROL :TSCLV_TAP_CONTROL; // 0x4673 + SCLV_CONTROL :TSCLV_CONTROL; // 0x4674 + SCLV_MANUAL_REPLICATE_CONTROL :TSCLV_MANUAL_REPLICATE_CONTROL; // 0x4675 + SCLV_AUTOMATIC_MODE_CONTROL :TSCLV_AUTOMATIC_MODE_CONTROL; // 0x4676 + SCLV_HORZ_FILTER_CONTROL :TSCLV_HORZ_FILTER_CONTROL; // 0x4677 + SCLV_HORZ_FILTER_SCALE_RATIO :TSCLV_HORZ_FILTER_SCALE_RATIO; // 0x4678 + SCLV_HORZ_FILTER_INIT :TSCLV_HORZ_FILTER_INIT; // 0x4679 + SCLV_HORZ_FILTER_SCALE_RATIO_C :TSCLV_HORZ_FILTER_SCALE_RATIO_C; // 0x467A + SCLV_HORZ_FILTER_INIT_C :TSCLV_HORZ_FILTER_INIT_C; // 0x467B + SCLV_VERT_FILTER_CONTROL :TSCLV_VERT_FILTER_CONTROL; // 0x467C + SCLV_VERT_FILTER_SCALE_RATIO :TSCLV_VERT_FILTER_SCALE_RATIO; // 0x467D + SCLV_VERT_FILTER_INIT :TSCLV_VERT_FILTER_INIT; // 0x467E + SCLV_VERT_FILTER_INIT_BOT :TSCLV_VERT_FILTER_INIT_BOT; // 0x467F + SCLV_VERT_FILTER_SCALE_RATIO_C :TSCLV_VERT_FILTER_SCALE_RATIO_C; // 0x4680 + SCLV_VERT_FILTER_INIT_C :TSCLV_VERT_FILTER_INIT_C; // 0x4681 + SCLV_VERT_FILTER_INIT_BOT_C :TSCLV_VERT_FILTER_INIT_BOT_C; // 0x4682 + SCLV_ROUND_OFFSET :TSCLV_ROUND_OFFSET; // 0x4683 + SCLV_UPDATE :TSCLV_UPDATE; // 0x4684 + SCLV_ALU_CONTROL :TSCLV_ALU_CONTROL; // 0x4685 + SCLV_VIEWPORT_START :TSCLV_VIEWPORT_START; // 0x4686 + SCLV_VIEWPORT_START_SECONDARY :TSCLV_VIEWPORT_START_SECONDARY; // 0x4687 + SCLV_VIEWPORT_SIZE :TSCLV_VIEWPORT_SIZE; // 0x4688 + SCLV_VIEWPORT_START_C :TSCLV_VIEWPORT_START_C; // 0x4689 + SCLV_VIEWPORT_START_SECONDARY_C :TSCLV_VIEWPORT_START_SECONDARY_C; // 0x468A + SCLV_VIEWPORT_SIZE_C :TSCLV_VIEWPORT_SIZE_C; // 0x468B + SCLV_EXT_OVERSCAN_LEFT_RIGHT :TSCLV_EXT_OVERSCAN_LEFT_RIGHT; // 0x468C + SCLV_EXT_OVERSCAN_TOP_BOTTOM :TSCLV_EXT_OVERSCAN_TOP_BOTTOM; // 0x468D + SCLV_MODE_CHANGE_DET1 :TSCLV_MODE_CHANGE_DET1; // 0x468E + SCLV_MODE_CHANGE_DET2 :TSCLV_MODE_CHANGE_DET2; // 0x468F + SCLV_MODE_CHANGE_DET3 :TSCLV_MODE_CHANGE_DET3; // 0x4690 + SCLV_MODE_CHANGE_MASK :TSCLV_MODE_CHANGE_MASK; // 0x4691 + SCLV_DEBUG2 :TSCLV_DEBUG2; // 0x4692 + SCLV_DEBUG :TSCLV_DEBUG; // 0x4693 + SCLV_TEST_DEBUG_INDEX :TSCLV_TEST_DEBUG_INDEX; // 0x4694 + SCLV_TEST_DEBUG_DATA :TSCLV_TEST_DEBUG_DATA; // 0x4695 + REG_4696_46A3 :array[0..13] of DWORD; // 0x4696 + COL_MAN_UPDATE :TCOL_MAN_UPDATE; // 0x46A4 + COL_MAN_INPUT_CSC_CONTROL :TCOL_MAN_INPUT_CSC_CONTROL; // 0x46A5 + INPUT_CSC_C11_C12_A :TINPUT_CSC_C11_C12_A; // 0x46A6 + INPUT_CSC_C13_C14_A :TINPUT_CSC_C13_C14_A; // 0x46A7 + INPUT_CSC_C21_C22_A :TINPUT_CSC_C21_C22_A; // 0x46A8 + INPUT_CSC_C23_C24_A :TINPUT_CSC_C23_C24_A; // 0x46A9 + INPUT_CSC_C31_C32_A :TINPUT_CSC_C31_C32_A; // 0x46AA + INPUT_CSC_C33_C34_A :TINPUT_CSC_C33_C34_A; // 0x46AB + INPUT_CSC_C11_C12_B :TINPUT_CSC_C11_C12_B; // 0x46AC + INPUT_CSC_C13_C14_B :TINPUT_CSC_C13_C14_B; // 0x46AD + INPUT_CSC_C21_C22_B :TINPUT_CSC_C21_C22_B; // 0x46AE + INPUT_CSC_C23_C24_B :TINPUT_CSC_C23_C24_B; // 0x46AF + INPUT_CSC_C31_C32_B :TINPUT_CSC_C31_C32_B; // 0x46B0 + INPUT_CSC_C33_C34_B :TINPUT_CSC_C33_C34_B; // 0x46B1 + PRESCALE_CONTROL :TPRESCALE_CONTROL; // 0x46B2 + PRESCALE_VALUES_R :TPRESCALE_VALUES_R; // 0x46B3 + PRESCALE_VALUES_G :TPRESCALE_VALUES_G; // 0x46B4 + PRESCALE_VALUES_B :TPRESCALE_VALUES_B; // 0x46B5 + COL_MAN_OUTPUT_CSC_CONTROL :TCOL_MAN_OUTPUT_CSC_CONTROL; // 0x46B6 + OUTPUT_CSC_C11_C12_A :TOUTPUT_CSC_C11_C12_A; // 0x46B7 + OUTPUT_CSC_C13_C14_A :TOUTPUT_CSC_C13_C14_A; // 0x46B8 + OUTPUT_CSC_C21_C22_A :TOUTPUT_CSC_C21_C22_A; // 0x46B9 + OUTPUT_CSC_C23_C24_A :TOUTPUT_CSC_C23_C24_A; // 0x46BA + OUTPUT_CSC_C31_C32_A :TOUTPUT_CSC_C31_C32_A; // 0x46BB + OUTPUT_CSC_C33_C34_A :TOUTPUT_CSC_C33_C34_A; // 0x46BC + OUTPUT_CSC_C11_C12_B :TOUTPUT_CSC_C11_C12_B; // 0x46BD + OUTPUT_CSC_C13_C14_B :TOUTPUT_CSC_C13_C14_B; // 0x46BE + OUTPUT_CSC_C21_C22_B :TOUTPUT_CSC_C21_C22_B; // 0x46BF + OUTPUT_CSC_C23_C24_B :TOUTPUT_CSC_C23_C24_B; // 0x46C0 + OUTPUT_CSC_C31_C32_B :TOUTPUT_CSC_C31_C32_B; // 0x46C1 + OUTPUT_CSC_C33_C34_B :TOUTPUT_CSC_C33_C34_B; // 0x46C2 + DENORM_CLAMP_CONTROL :TDENORM_CLAMP_CONTROL; // 0x46C3 + DENORM_CLAMP_RANGE_R_CR :TDENORM_CLAMP_RANGE_R_CR; // 0x46C4 + DENORM_CLAMP_RANGE_G_Y :TDENORM_CLAMP_RANGE_G_Y; // 0x46C5 + DENORM_CLAMP_RANGE_B_CB :TDENORM_CLAMP_RANGE_B_CB; // 0x46C6 + COL_MAN_FP_CONVERTED_FIELD :TCOL_MAN_FP_CONVERTED_FIELD; // 0x46C7 + GAMMA_CORR_CONTROL :TGAMMA_CORR_CONTROL; // 0x46C8 + GAMMA_CORR_LUT_INDEX :TGAMMA_CORR_LUT_INDEX; // 0x46C9 + GAMMA_CORR_LUT_DATA :TGAMMA_CORR_LUT_DATA; // 0x46CA + GAMMA_CORR_LUT_WRITE_EN_MASK :TGAMMA_CORR_LUT_WRITE_EN_MASK; // 0x46CB + GAMMA_CORR_CNTLA_START_CNTL :TGAMMA_CORR_CNTLA_START_CNTL; // 0x46CC + GAMMA_CORR_CNTLA_SLOPE_CNTL :TGAMMA_CORR_CNTLA_SLOPE_CNTL; // 0x46CD + GAMMA_CORR_CNTLA_END_CNTL1 :TGAMMA_CORR_CNTLA_END_CNTL1; // 0x46CE + GAMMA_CORR_CNTLA_END_CNTL2 :TGAMMA_CORR_CNTLA_END_CNTL2; // 0x46CF + GAMMA_CORR_CNTLA_REGION_0_1 :TGAMMA_CORR_CNTLA_REGION_0_1; // 0x46D0 + GAMMA_CORR_CNTLA_REGION_2_3 :TGAMMA_CORR_CNTLA_REGION_2_3; // 0x46D1 + GAMMA_CORR_CNTLA_REGION_4_5 :TGAMMA_CORR_CNTLA_REGION_4_5; // 0x46D2 + GAMMA_CORR_CNTLA_REGION_6_7 :TGAMMA_CORR_CNTLA_REGION_6_7; // 0x46D3 + GAMMA_CORR_CNTLA_REGION_8_9 :TGAMMA_CORR_CNTLA_REGION_8_9; // 0x46D4 + GAMMA_CORR_CNTLA_REGION_10_11 :TGAMMA_CORR_CNTLA_REGION_10_11; // 0x46D5 + GAMMA_CORR_CNTLA_REGION_12_13 :TGAMMA_CORR_CNTLA_REGION_12_13; // 0x46D6 + GAMMA_CORR_CNTLA_REGION_14_15 :TGAMMA_CORR_CNTLA_REGION_14_15; // 0x46D7 + GAMMA_CORR_CNTLB_START_CNTL :TGAMMA_CORR_CNTLB_START_CNTL; // 0x46D8 + GAMMA_CORR_CNTLB_SLOPE_CNTL :TGAMMA_CORR_CNTLB_SLOPE_CNTL; // 0x46D9 + GAMMA_CORR_CNTLB_END_CNTL1 :TGAMMA_CORR_CNTLB_END_CNTL1; // 0x46DA + GAMMA_CORR_CNTLB_END_CNTL2 :TGAMMA_CORR_CNTLB_END_CNTL2; // 0x46DB + GAMMA_CORR_CNTLB_REGION_0_1 :TGAMMA_CORR_CNTLB_REGION_0_1; // 0x46DC + GAMMA_CORR_CNTLB_REGION_2_3 :TGAMMA_CORR_CNTLB_REGION_2_3; // 0x46DD + GAMMA_CORR_CNTLB_REGION_4_5 :TGAMMA_CORR_CNTLB_REGION_4_5; // 0x46DE + GAMMA_CORR_CNTLB_REGION_6_7 :TGAMMA_CORR_CNTLB_REGION_6_7; // 0x46DF + GAMMA_CORR_CNTLB_REGION_8_9 :TGAMMA_CORR_CNTLB_REGION_8_9; // 0x46E0 + GAMMA_CORR_CNTLB_REGION_10_11 :TGAMMA_CORR_CNTLB_REGION_10_11; // 0x46E1 + GAMMA_CORR_CNTLB_REGION_12_13 :TGAMMA_CORR_CNTLB_REGION_12_13; // 0x46E2 + GAMMA_CORR_CNTLB_REGION_14_15 :TGAMMA_CORR_CNTLB_REGION_14_15; // 0x46E3 + COL_MAN_TEST_DEBUG_INDEX :TCOL_MAN_TEST_DEBUG_INDEX; // 0x46E4 + COL_MAN_TEST_DEBUG_DATA :TCOL_MAN_TEST_DEBUG_DATA; // 0x46E5 + COL_MAN_DEBUG_CONTROL :TCOL_MAN_DEBUG_CONTROL; // 0x46E6 + REG_46E7_46F3 :array[0..12] of DWORD; // 0x46E7 + DCFEV_CLOCK_CONTROL :TDCFEV_CLOCK_CONTROL; // 0x46F4 + DCFEV_SOFT_RESET :TDCFEV_SOFT_RESET; // 0x46F5 + DCFEV_DMIFV_CLOCK_CONTROL :TDCFEV_DMIFV_CLOCK_CONTROL; // 0x46F6 + DCFEV_DBG_CONFIG :TDCFEV_DBG_CONFIG; // 0x46F7 + DCFEV_DMIFV_MEM_PWR_CTRL :TDCFEV_DMIFV_MEM_PWR_CTRL; // 0x46F8 + DCFEV_DMIFV_MEM_PWR_STATUS :TDCFEV_DMIFV_MEM_PWR_STATUS; // 0x46F9 + REG_46FA_4723 :array[0..41] of DWORD; // 0x46FA + DC_PERFMON11_PERFCOUNTER_CNTL :DWORD; // 0x4724 + DC_PERFMON11_PERFCOUNTER_STATE :DWORD; // 0x4725 + DC_PERFMON11_PERFMON_CVALUE_INT_MISC :DWORD; // 0x4726 + DC_PERFMON11_PERFMON_CNTL :DWORD; // 0x4727 + DC_PERFMON11_PERFMON_CVALUE_LOW :DWORD; // 0x4728 + DC_PERFMON11_PERFMON_HI :DWORD; // 0x4729 + DC_PERFMON11_PERFMON_LOW :DWORD; // 0x472A + DC_PERFMON11_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x472B + DC_PERFMON11_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x472C + REG_472D :DWORD; // 0x472D + DC_PERFMON11_PERFMON_CNTL2 :DWORD; // 0x472E + REG_472F :DWORD; // 0x472F + DMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 :DWORD; // 0x4730 + DMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 :DWORD; // 0x4731 + DMIF_PG6_DPG_WATERMARK_MASK_CONTROL :DWORD; // 0x4732 + DMIF_PG6_DPG_PIPE_URGENCY_CONTROL :DWORD; // 0x4733 + DMIF_PG6_DPG_PIPE_DPM_CONTROL :DWORD; // 0x4734 + DMIF_PG6_DPG_PIPE_STUTTER_CONTROL :DWORD; // 0x4735 + DMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :DWORD; // 0x4736 + DMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :DWORD; // 0x4737 + DMIF_PG6_DPG_TEST_DEBUG_INDEX :DWORD; // 0x4738 + DMIF_PG6_DPG_TEST_DEBUG_DATA :DWORD; // 0x4739 + DMIF_PG6_DPG_REPEATER_PROGRAM :DWORD; // 0x473A + DMIF_PG6_DPG_HW_DEBUG_A :DWORD; // 0x473B + DMIF_PG6_DPG_HW_DEBUG_B :DWORD; // 0x473C + DMIF_PG6_DPG_HW_DEBUG_11 :DWORD; // 0x473D + REG_473E_476C :array[0..46] of DWORD; // 0x473E + BLND6_BLND_CONTROL :DWORD; // 0x476D + BLND6_SM_CONTROL2 :DWORD; // 0x476E + BLND6_BLND_CONTROL2 :DWORD; // 0x476F + BLND6_BLND_UPDATE :DWORD; // 0x4770 + BLND6_BLND_UNDERFLOW_INTERRUPT :DWORD; // 0x4771 + REG_4772 :DWORD; // 0x4772 + BLND6_BLND_V_UPDATE_LOCK :DWORD; // 0x4773 + BLND6_BLND_DEBUG :DWORD; // 0x4774 + BLND6_BLND_TEST_DEBUG_INDEX :DWORD; // 0x4775 + BLND6_BLND_TEST_DEBUG_DATA :DWORD; // 0x4776 + BLND6_BLND_REG_UPDATE_STATUS :DWORD; // 0x4777 + CRTC6_CRTC_3D_STRUCTURE_CONTROL :DWORD; // 0x4778 + CRTC6_CRTC_GSL_VSYNC_GAP :DWORD; // 0x4779 + CRTC6_CRTC_GSL_WINDOW :DWORD; // 0x477A + CRTC6_CRTC_GSL_CONTROL :DWORD; // 0x477B + CRTC6_CRTC_DCFE_CLOCK_CONTROL :DWORD; // 0x477C + CRTC6_CRTC_H_BLANK_EARLY_NUM :DWORD; // 0x477D + CRTC6_DCFE_DBG_SEL :DWORD; // 0x477E + CRTC6_DCFE_MEM_PWR_CTRL :DWORD; // 0x477F + CRTC6_CRTC_H_TOTAL :DWORD; // 0x4780 + CRTC6_CRTC_H_BLANK_START_END :DWORD; // 0x4781 + CRTC6_CRTC_H_SYNC_A :DWORD; // 0x4782 + CRTC6_CRTC_H_SYNC_A_CNTL :DWORD; // 0x4783 + CRTC6_CRTC_H_SYNC_B :DWORD; // 0x4784 + CRTC6_CRTC_H_SYNC_B_CNTL :DWORD; // 0x4785 + CRTC6_CRTC_VBI_END :DWORD; // 0x4786 + CRTC6_CRTC_V_TOTAL :DWORD; // 0x4787 + CRTC6_CRTC_V_TOTAL_MIN :DWORD; // 0x4788 + CRTC6_CRTC_V_TOTAL_MAX :DWORD; // 0x4789 + CRTC6_CRTC_V_TOTAL_CONTROL :DWORD; // 0x478A + CRTC6_CRTC_V_TOTAL_INT_STATUS :DWORD; // 0x478B + CRTC6_CRTC_VSYNC_NOM_INT_STATUS :DWORD; // 0x478C + CRTC6_CRTC_V_BLANK_START_END :DWORD; // 0x478D + CRTC6_CRTC_V_SYNC_A :DWORD; // 0x478E + CRTC6_CRTC_V_SYNC_A_CNTL :DWORD; // 0x478F + CRTC6_CRTC_V_SYNC_B :DWORD; // 0x4790 + CRTC6_CRTC_V_SYNC_B_CNTL :DWORD; // 0x4791 + CRTC6_CRTC_DTMTEST_CNTL :DWORD; // 0x4792 + CRTC6_CRTC_DTMTEST_STATUS_POSITION :DWORD; // 0x4793 + CRTC6_CRTC_TRIGA_CNTL :DWORD; // 0x4794 + CRTC6_CRTC_TRIGA_MANUAL_TRIG :DWORD; // 0x4795 + CRTC6_CRTC_TRIGB_CNTL :DWORD; // 0x4796 + CRTC6_CRTC_TRIGB_MANUAL_TRIG :DWORD; // 0x4797 + CRTC6_CRTC_FORCE_COUNT_NOW_CNTL :DWORD; // 0x4798 + CRTC6_CRTC_FLOW_CONTROL :DWORD; // 0x4799 + CRTC6_CRTC_STEREO_FORCE_NEXT_EYE :DWORD; // 0x479A + CRTC6_CRTC_AVSYNC_COUNTER :DWORD; // 0x479B + CRTC6_CRTC_CONTROL :DWORD; // 0x479C + CRTC6_CRTC_BLANK_CONTROL :DWORD; // 0x479D + CRTC6_CRTC_INTERLACE_CONTROL :DWORD; // 0x479E + CRTC6_CRTC_INTERLACE_STATUS :DWORD; // 0x479F + CRTC6_CRTC_FIELD_INDICATION_CONTROL :DWORD; // 0x47A0 + CRTC6_CRTC_PIXEL_DATA_READBACK0 :DWORD; // 0x47A1 + CRTC6_CRTC_PIXEL_DATA_READBACK1 :DWORD; // 0x47A2 + CRTC6_CRTC_STATUS :DWORD; // 0x47A3 + CRTC6_CRTC_STATUS_POSITION :DWORD; // 0x47A4 + CRTC6_CRTC_NOM_VERT_POSITION :DWORD; // 0x47A5 + CRTC6_CRTC_STATUS_FRAME_COUNT :DWORD; // 0x47A6 + CRTC6_CRTC_STATUS_VF_COUNT :DWORD; // 0x47A7 + CRTC6_CRTC_STATUS_HV_COUNT :DWORD; // 0x47A8 + CRTC6_CRTC_COUNT_CONTROL :DWORD; // 0x47A9 + CRTC6_CRTC_COUNT_RESET :DWORD; // 0x47AA + CRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :DWORD; // 0x47AB + CRTC6_CRTC_VERT_SYNC_CONTROL :DWORD; // 0x47AC + CRTC6_CRTC_STEREO_STATUS :DWORD; // 0x47AD + CRTC6_CRTC_STEREO_CONTROL :DWORD; // 0x47AE + CRTC6_CRTC_SNAPSHOT_STATUS :DWORD; // 0x47AF + CRTC6_CRTC_SNAPSHOT_CONTROL :DWORD; // 0x47B0 + CRTC6_CRTC_SNAPSHOT_POSITION :DWORD; // 0x47B1 + CRTC6_CRTC_SNAPSHOT_FRAME :DWORD; // 0x47B2 + CRTC6_CRTC_START_LINE_CONTROL :DWORD; // 0x47B3 + CRTC6_CRTC_INTERRUPT_CONTROL :DWORD; // 0x47B4 + CRTC6_CRTC_UPDATE_LOCK :DWORD; // 0x47B5 + CRTC6_CRTC_DOUBLE_BUFFER_CONTROL :DWORD; // 0x47B6 + CRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE :DWORD; // 0x47B7 + CRTC6_DCFE_MEM_PWR_CTRL2 :DWORD; // 0x47B8 + CRTC6_DCFE_MEM_PWR_STATUS :DWORD; // 0x47B9 + CRTC6_CRTC_TEST_PATTERN_CONTROL :DWORD; // 0x47BA + CRTC6_CRTC_TEST_PATTERN_PARAMETERS :DWORD; // 0x47BB + CRTC6_CRTC_TEST_PATTERN_COLOR :DWORD; // 0x47BC + CRTC6_MASTER_UPDATE_LOCK :DWORD; // 0x47BD + CRTC6_MASTER_UPDATE_MODE :DWORD; // 0x47BE + CRTC6_CRTC_MVP_INBAND_CNTL_INSERT :DWORD; // 0x47BF + CRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :DWORD; // 0x47C0 + CRTC6_CRTC_MVP_STATUS :DWORD; // 0x47C1 + CRTC6_CRTC_MASTER_EN :DWORD; // 0x47C2 + CRTC6_CRTC_ALLOW_STOP_OFF_V_CNT :DWORD; // 0x47C3 + CRTC6_CRTC_V_UPDATE_INT_STATUS :DWORD; // 0x47C4 + REG_47C5 :DWORD; // 0x47C5 + CRTC6_CRTC_TEST_DEBUG_INDEX :DWORD; // 0x47C6 + CRTC6_CRTC_TEST_DEBUG_DATA :DWORD; // 0x47C7 + CRTC6_CRTC_OVERSCAN_COLOR :DWORD; // 0x47C8 + CRTC6_CRTC_OVERSCAN_COLOR_EXT :DWORD; // 0x47C9 + CRTC6_CRTC_BLANK_DATA_COLOR :DWORD; // 0x47CA + CRTC6_CRTC_BLANK_DATA_COLOR_EXT :DWORD; // 0x47CB + CRTC6_CRTC_BLACK_COLOR :DWORD; // 0x47CC + CRTC6_CRTC_BLACK_COLOR_EXT :DWORD; // 0x47CD + CRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION :DWORD; // 0x47CE + CRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL :DWORD; // 0x47CF + CRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION :DWORD; // 0x47D0 + CRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL :DWORD; // 0x47D1 + CRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION :DWORD; // 0x47D2 + CRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL :DWORD; // 0x47D3 + CRTC6_CRTC_CRC_CNTL :DWORD; // 0x47D4 + CRTC6_CRTC_CRC0_WINDOWA_X_CONTROL :DWORD; // 0x47D5 + CRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL :DWORD; // 0x47D6 + CRTC6_CRTC_CRC0_WINDOWB_X_CONTROL :DWORD; // 0x47D7 + CRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL :DWORD; // 0x47D8 + CRTC6_CRTC_CRC0_DATA_RG :DWORD; // 0x47D9 + CRTC6_CRTC_CRC0_DATA_B :DWORD; // 0x47DA + CRTC6_CRTC_CRC1_WINDOWA_X_CONTROL :DWORD; // 0x47DB + CRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL :DWORD; // 0x47DC + CRTC6_CRTC_CRC1_WINDOWB_X_CONTROL :DWORD; // 0x47DD + CRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL :DWORD; // 0x47DE + CRTC6_CRTC_CRC1_DATA_RG :DWORD; // 0x47DF + CRTC6_CRTC_CRC1_DATA_B :DWORD; // 0x47E0 + CRTC6_CRTC_EXT_TIMING_SYNC_CONTROL :DWORD; // 0x47E1 + CRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START :DWORD; // 0x47E2 + CRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END :DWORD; // 0x47E3 + CRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :DWORD; // 0x47E4 + CRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :DWORD; // 0x47E5 + CRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :DWORD; // 0x47E6 + CRTC6_CRTC_STATIC_SCREEN_CONTROL :DWORD; // 0x47E7 + REG_47E8_47FF :array[0..23] of DWORD; // 0x47E8 + DC_GENERICA :TDC_GENERICA; // 0x4800 + DC_GENERICB :TDC_GENERICB; // 0x4801 + DC_PAD_EXTERN_SIG :TDC_PAD_EXTERN_SIG; // 0x4802 + DC_REF_CLK_CNTL :TDC_REF_CLK_CNTL; // 0x4803 + DC_GPIO_DEBUG :TDC_GPIO_DEBUG; // 0x4804 + UNIPHYA_LINK_CNTL :TUNIPHYA_LINK_CNTL; // 0x4805 + UNIPHYA_CHANNEL_XBAR_CNTL :TUNIPHYA_CHANNEL_XBAR_CNTL; // 0x4806 + UNIPHYB_LINK_CNTL :TUNIPHYB_LINK_CNTL; // 0x4807 + UNIPHYB_CHANNEL_XBAR_CNTL :TUNIPHYB_CHANNEL_XBAR_CNTL; // 0x4808 + UNIPHYC_LINK_CNTL :TUNIPHYC_LINK_CNTL; // 0x4809 + UNIPHYC_CHANNEL_XBAR_CNTL :TUNIPHYC_CHANNEL_XBAR_CNTL; // 0x480A + UNIPHYD_LINK_CNTL :TUNIPHYD_LINK_CNTL; // 0x480B + UNIPHYD_CHANNEL_XBAR_CNTL :TUNIPHYD_CHANNEL_XBAR_CNTL; // 0x480C + UNIPHYE_LINK_CNTL :TUNIPHYE_LINK_CNTL; // 0x480D + UNIPHYE_CHANNEL_XBAR_CNTL :TUNIPHYE_CHANNEL_XBAR_CNTL; // 0x480E + UNIPHYF_LINK_CNTL :TUNIPHYF_LINK_CNTL; // 0x480F + UNIPHYF_CHANNEL_XBAR_CNTL :TUNIPHYF_CHANNEL_XBAR_CNTL; // 0x4810 + UNIPHYG_LINK_CNTL :TUNIPHYG_LINK_CNTL; // 0x4811 + UNIPHYG_CHANNEL_XBAR_CNTL :TUNIPHYG_CHANNEL_XBAR_CNTL; // 0x4812 + DIG4_HDMI_GENERIC_PACKET_CONTROL :DWORD; // 0x4813 + REG_4814_4815 :array[0..1] of DWORD; // 0x4814 + DCIO_WRCMD_DELAY :TDCIO_WRCMD_DELAY; // 0x4816 + REG_4817 :DWORD; // 0x4817 + DC_PINSTRAPS :TDC_PINSTRAPS; // 0x4818 + REG_4819 :DWORD; // 0x4819 + DC_DVODATA_CONFIG :TDC_DVODATA_CONFIG; // 0x481A + LVTMA_PWRSEQ_CNTL :TLVTMA_PWRSEQ_CNTL; // 0x481B + LVTMA_PWRSEQ_STATE :TLVTMA_PWRSEQ_STATE; // 0x481C + LVTMA_PWRSEQ_REF_DIV :TLVTMA_PWRSEQ_REF_DIV; // 0x481D + LVTMA_PWRSEQ_DELAY1 :TLVTMA_PWRSEQ_DELAY1; // 0x481E + LVTMA_PWRSEQ_DELAY2 :TLVTMA_PWRSEQ_DELAY2; // 0x481F + BL_PWM_CNTL :TBL_PWM_CNTL; // 0x4820 + BL_PWM_CNTL2 :TBL_PWM_CNTL2; // 0x4821 + BL_PWM_PERIOD_CNTL :TBL_PWM_PERIOD_CNTL; // 0x4822 + BL_PWM_GRP1_REG_LOCK :TBL_PWM_GRP1_REG_LOCK; // 0x4823 + DCIO_GSL_GENLK_PAD_CNTL :TDCIO_GSL_GENLK_PAD_CNTL; // 0x4824 + DCIO_GSL_SWAPLOCK_PAD_CNTL :TDCIO_GSL_SWAPLOCK_PAD_CNTL; // 0x4825 + DCIO_GSL0_CNTL :TDCIO_GSL0_CNTL; // 0x4826 + DCIO_GSL1_CNTL :TDCIO_GSL1_CNTL; // 0x4827 + DCIO_GSL2_CNTL :TDCIO_GSL2_CNTL; // 0x4828 + DC_GPU_TIMER_START_POSITION_V_UPDATE :TDC_GPU_TIMER_START_POSITION_V_UPDATE; // 0x4829 + DC_GPU_TIMER_START_POSITION_P_FLIP :TDC_GPU_TIMER_START_POSITION_P_FLIP; // 0x482A + DC_GPU_TIMER_READ :TDC_GPU_TIMER_READ; // 0x482B + DC_GPU_TIMER_READ_CNTL :TDC_GPU_TIMER_READ_CNTL; // 0x482C + DCIO_CLOCK_CNTL :TDCIO_CLOCK_CNTL; // 0x482D + REG_482E :DWORD; // 0x482E + DCIO_DEBUG :TDCIO_DEBUG; // 0x482F + DCO_DCFE_EXT_VSYNC_CNTL :TDCO_DCFE_EXT_VSYNC_CNTL; // 0x4830 + DCIO_TEST_DEBUG_INDEX :TDCIO_TEST_DEBUG_INDEX; // 0x4831 + DCIO_TEST_DEBUG_DATA :TDCIO_TEST_DEBUG_DATA; // 0x4832 + REG_4833 :DWORD; // 0x4833 + DBG_OUT_CNTL :TDBG_OUT_CNTL; // 0x4834 + DCIO_DEBUG_CONFIG :TDCIO_DEBUG_CONFIG; // 0x4835 + DCIO_SOFT_RESET :TDCIO_SOFT_RESET; // 0x4836 + DCIO_DPHY_SEL :TDCIO_DPHY_SEL; // 0x4837 + UNIPHY_IMPCAL_LINKA :TUNIPHY_IMPCAL_LINKA; // 0x4838 + UNIPHY_IMPCAL_LINKB :TUNIPHY_IMPCAL_LINKB; // 0x4839 + UNIPHY_IMPCAL_PERIOD :TUNIPHY_IMPCAL_PERIOD; // 0x483A + AUXP_IMPCAL :TAUXP_IMPCAL; // 0x483B + AUXN_IMPCAL :TAUXN_IMPCAL; // 0x483C + DCIO_IMPCAL_CNTL :TDCIO_IMPCAL_CNTL; // 0x483D + UNIPHY_IMPCAL_PSW_AB :TUNIPHY_IMPCAL_PSW_AB; // 0x483E + UNIPHY_IMPCAL_LINKC :TUNIPHY_IMPCAL_LINKC; // 0x483F + UNIPHY_IMPCAL_LINKD :TUNIPHY_IMPCAL_LINKD; // 0x4840 + DCIO_IMPCAL_CNTL_CD :TDCIO_IMPCAL_CNTL_CD; // 0x4841 + UNIPHY_IMPCAL_PSW_CD :TUNIPHY_IMPCAL_PSW_CD; // 0x4842 + UNIPHY_IMPCAL_LINKE :TUNIPHY_IMPCAL_LINKE; // 0x4843 + UNIPHY_IMPCAL_LINKF :TUNIPHY_IMPCAL_LINKF; // 0x4844 + DCIO_IMPCAL_CNTL_EF :TDCIO_IMPCAL_CNTL_EF; // 0x4845 + UNIPHY_IMPCAL_PSW_EF :TUNIPHY_IMPCAL_PSW_EF; // 0x4846 + REG_4847_485F :array[0..24] of DWORD; // 0x4847 + DC_GPIO_GENERIC_MASK :TDC_GPIO_GENERIC_MASK; // 0x4860 + DC_GPIO_GENERIC_A :TDC_GPIO_GENERIC_A; // 0x4861 + DC_GPIO_GENERIC_EN :TDC_GPIO_GENERIC_EN; // 0x4862 + DC_GPIO_GENERIC_Y :TDC_GPIO_GENERIC_Y; // 0x4863 + DC_GPIO_DVODATA_MASK :TDC_GPIO_DVODATA_MASK; // 0x4864 + DC_GPIO_DVODATA_A :TDC_GPIO_DVODATA_A; // 0x4865 + DC_GPIO_DVODATA_EN :TDC_GPIO_DVODATA_EN; // 0x4866 + DC_GPIO_DVODATA_Y :TDC_GPIO_DVODATA_Y; // 0x4867 + DC_GPIO_DDC1_MASK :TDC_GPIO_DDC1_MASK; // 0x4868 + DC_GPIO_DDC1_A :TDC_GPIO_DDC1_A; // 0x4869 + DC_GPIO_DDC1_EN :TDC_GPIO_DDC1_EN; // 0x486A + DC_GPIO_DDC1_Y :TDC_GPIO_DDC1_Y; // 0x486B + DC_GPIO_DDC2_MASK :TDC_GPIO_DDC2_MASK; // 0x486C + DC_GPIO_DDC2_A :TDC_GPIO_DDC2_A; // 0x486D + DC_GPIO_DDC2_EN :TDC_GPIO_DDC2_EN; // 0x486E + DC_GPIO_DDC2_Y :TDC_GPIO_DDC2_Y; // 0x486F + DC_GPIO_DDC3_MASK :TDC_GPIO_DDC3_MASK; // 0x4870 + DC_GPIO_DDC3_A :TDC_GPIO_DDC3_A; // 0x4871 + DC_GPIO_DDC3_EN :TDC_GPIO_DDC3_EN; // 0x4872 + DC_GPIO_DDC3_Y :TDC_GPIO_DDC3_Y; // 0x4873 + DC_GPIO_DDC4_MASK :TDC_GPIO_DDC4_MASK; // 0x4874 + DC_GPIO_DDC4_A :TDC_GPIO_DDC4_A; // 0x4875 + DC_GPIO_DDC4_EN :TDC_GPIO_DDC4_EN; // 0x4876 + DC_GPIO_DDC4_Y :TDC_GPIO_DDC4_Y; // 0x4877 + DC_GPIO_DDC5_MASK :TDC_GPIO_DDC5_MASK; // 0x4878 + DC_GPIO_DDC5_A :TDC_GPIO_DDC5_A; // 0x4879 + DC_GPIO_DDC5_EN :TDC_GPIO_DDC5_EN; // 0x487A + DC_GPIO_DDC5_Y :TDC_GPIO_DDC5_Y; // 0x487B + DC_GPIO_DDC6_MASK :TDC_GPIO_DDC6_MASK; // 0x487C + DC_GPIO_DDC6_A :TDC_GPIO_DDC6_A; // 0x487D + DC_GPIO_DDC6_EN :TDC_GPIO_DDC6_EN; // 0x487E + DC_GPIO_DDC6_Y :TDC_GPIO_DDC6_Y; // 0x487F + DC_GPIO_DDCVGA_MASK :TDC_GPIO_DDCVGA_MASK; // 0x4880 + DC_GPIO_DDCVGA_A :TDC_GPIO_DDCVGA_A; // 0x4881 + DC_GPIO_DDCVGA_EN :TDC_GPIO_DDCVGA_EN; // 0x4882 + DC_GPIO_DDCVGA_Y :TDC_GPIO_DDCVGA_Y; // 0x4883 + DC_GPIO_SYNCA_MASK :TDC_GPIO_SYNCA_MASK; // 0x4884 + DC_GPIO_SYNCA_A :TDC_GPIO_SYNCA_A; // 0x4885 + DC_GPIO_SYNCA_EN :TDC_GPIO_SYNCA_EN; // 0x4886 + DC_GPIO_SYNCA_Y :TDC_GPIO_SYNCA_Y; // 0x4887 + DC_GPIO_GENLK_MASK :TDC_GPIO_GENLK_MASK; // 0x4888 + DC_GPIO_GENLK_A :TDC_GPIO_GENLK_A; // 0x4889 + DC_GPIO_GENLK_EN :TDC_GPIO_GENLK_EN; // 0x488A + DC_GPIO_GENLK_Y :TDC_GPIO_GENLK_Y; // 0x488B + DC_GPIO_HPD_MASK :TDC_GPIO_HPD_MASK; // 0x488C + DC_GPIO_HPD_A :TDC_GPIO_HPD_A; // 0x488D + DC_GPIO_HPD_EN :TDC_GPIO_HPD_EN; // 0x488E + DC_GPIO_HPD_Y :TDC_GPIO_HPD_Y; // 0x488F + DC_GPIO_PWRSEQ_MASK :TDC_GPIO_PWRSEQ_MASK; // 0x4890 + DC_GPIO_PWRSEQ_A :TDC_GPIO_PWRSEQ_A; // 0x4891 + DC_GPIO_PWRSEQ_EN :TDC_GPIO_PWRSEQ_EN; // 0x4892 + DC_GPIO_PWRSEQ_Y :TDC_GPIO_PWRSEQ_Y; // 0x4893 + DC_GPIO_PAD_STRENGTH_1 :TDC_GPIO_PAD_STRENGTH_1; // 0x4894 + DC_GPIO_PAD_STRENGTH_2 :TDC_GPIO_PAD_STRENGTH_2; // 0x4895 + REG_4896 :DWORD; // 0x4896 + PHY_AUX_CNTL :TPHY_AUX_CNTL; // 0x4897 + DC_GPIO_I2CPAD_MASK :TDC_GPIO_I2CPAD_MASK; // 0x4898 + DC_GPIO_I2CPAD_A :TDC_GPIO_I2CPAD_A; // 0x4899 + DC_GPIO_I2CPAD_EN :TDC_GPIO_I2CPAD_EN; // 0x489A + DC_GPIO_I2CPAD_Y :TDC_GPIO_I2CPAD_Y; // 0x489B + DC_GPIO_I2CPAD_STRENGTH :TDC_GPIO_I2CPAD_STRENGTH; // 0x489C + DVO_STRENGTH_CONTROL :TDVO_STRENGTH_CONTROL; // 0x489D + DVO_VREF_CONTROL :TDVO_VREF_CONTROL; // 0x489E + DVO_SKEW_ADJUST :TDVO_SKEW_ADJUST; // 0x489F + REG_48A0_48B7 :array[0..23] of DWORD; // 0x48A0 + DAC_MACRO_CNTL_RESERVED0 :TDAC_MACRO_CNTL_RESERVED0; // 0x48B8 + BPHYC_DAC_MACRO_CNTL :TBPHYC_DAC_MACRO_CNTL; // 0x48B9 + BPHYC_DAC_AUTO_CALIB_CONTROL :TBPHYC_DAC_AUTO_CALIB_CONTROL; // 0x48BA + DAC_MACRO_CNTL_RESERVED3 :TDAC_MACRO_CNTL_RESERVED3; // 0x48BB + REG_48BC_48BF :array[0..3] of DWORD; // 0x48BC + BPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 :DWORD; // 0x48C0 + BPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 :DWORD; // 0x48C1 + BPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 :DWORD; // 0x48C2 + BPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 :DWORD; // 0x48C3 + BPHYC_UNIPHY0_UNIPHY_POWER_CONTROL :DWORD; // 0x48C4 + BPHYC_UNIPHY0_UNIPHY_PLL_FBDIV :DWORD; // 0x48C5 + BPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 :DWORD; // 0x48C6 + BPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 :DWORD; // 0x48C7 + BPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x48C8 + BPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL :DWORD; // 0x48C9 + BPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x48CA + BPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x48CB + BPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x48CC + BPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x48CD + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x48CE + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x48CF + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x48D0 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x48D1 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x48D2 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x48D3 + BPHYC_UNIPHY0_UNIPHY_TPG_CONTROL :DWORD; // 0x48D4 + BPHYC_UNIPHY0_UNIPHY_TPG_SEED :DWORD; // 0x48D5 + BPHYC_UNIPHY0_UNIPHY_DEBUG :DWORD; // 0x48D6 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x48D7 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x48D8 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x48D9 + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x48DA + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x48DB + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x48DC + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x48DD + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x48DE + DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x48DF + BPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 :DWORD; // 0x48E0 + BPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 :DWORD; // 0x48E1 + BPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 :DWORD; // 0x48E2 + BPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 :DWORD; // 0x48E3 + BPHYC_UNIPHY1_UNIPHY_POWER_CONTROL :DWORD; // 0x48E4 + BPHYC_UNIPHY1_UNIPHY_PLL_FBDIV :DWORD; // 0x48E5 + BPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 :DWORD; // 0x48E6 + BPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 :DWORD; // 0x48E7 + BPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x48E8 + BPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL :DWORD; // 0x48E9 + BPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x48EA + BPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x48EB + BPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x48EC + BPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x48ED + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x48EE + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x48EF + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x48F0 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x48F1 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x48F2 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x48F3 + BPHYC_UNIPHY1_UNIPHY_TPG_CONTROL :DWORD; // 0x48F4 + BPHYC_UNIPHY1_UNIPHY_TPG_SEED :DWORD; // 0x48F5 + BPHYC_UNIPHY1_UNIPHY_DEBUG :DWORD; // 0x48F6 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x48F7 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x48F8 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x48F9 + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x48FA + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x48FB + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x48FC + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x48FD + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x48FE + DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x48FF + BPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 :DWORD; // 0x4900 + BPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 :DWORD; // 0x4901 + BPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 :DWORD; // 0x4902 + BPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 :DWORD; // 0x4903 + BPHYC_UNIPHY2_UNIPHY_POWER_CONTROL :DWORD; // 0x4904 + BPHYC_UNIPHY2_UNIPHY_PLL_FBDIV :DWORD; // 0x4905 + BPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 :DWORD; // 0x4906 + BPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 :DWORD; // 0x4907 + BPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x4908 + BPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL :DWORD; // 0x4909 + BPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x490A + BPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x490B + BPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x490C + BPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x490D + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x490E + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x490F + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x4910 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x4911 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x4912 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x4913 + BPHYC_UNIPHY2_UNIPHY_TPG_CONTROL :DWORD; // 0x4914 + BPHYC_UNIPHY2_UNIPHY_TPG_SEED :DWORD; // 0x4915 + BPHYC_UNIPHY2_UNIPHY_DEBUG :DWORD; // 0x4916 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x4917 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x4918 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x4919 + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x491A + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x491B + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x491C + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x491D + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x491E + DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x491F + BPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 :DWORD; // 0x4920 + BPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 :DWORD; // 0x4921 + BPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 :DWORD; // 0x4922 + BPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 :DWORD; // 0x4923 + BPHYC_UNIPHY3_UNIPHY_POWER_CONTROL :DWORD; // 0x4924 + BPHYC_UNIPHY3_UNIPHY_PLL_FBDIV :DWORD; // 0x4925 + BPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 :DWORD; // 0x4926 + BPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 :DWORD; // 0x4927 + BPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x4928 + BPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL :DWORD; // 0x4929 + BPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x492A + BPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x492B + BPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x492C + BPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x492D + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x492E + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x492F + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x4930 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x4931 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x4932 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x4933 + BPHYC_UNIPHY3_UNIPHY_TPG_CONTROL :DWORD; // 0x4934 + BPHYC_UNIPHY3_UNIPHY_TPG_SEED :DWORD; // 0x4935 + BPHYC_UNIPHY3_UNIPHY_DEBUG :DWORD; // 0x4936 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x4937 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x4938 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x4939 + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x493A + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x493B + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x493C + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x493D + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x493E + DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x493F + BPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 :DWORD; // 0x4940 + BPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 :DWORD; // 0x4941 + BPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 :DWORD; // 0x4942 + BPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 :DWORD; // 0x4943 + BPHYC_UNIPHY4_UNIPHY_POWER_CONTROL :DWORD; // 0x4944 + BPHYC_UNIPHY4_UNIPHY_PLL_FBDIV :DWORD; // 0x4945 + BPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 :DWORD; // 0x4946 + BPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 :DWORD; // 0x4947 + BPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x4948 + BPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL :DWORD; // 0x4949 + BPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x494A + BPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x494B + BPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x494C + BPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x494D + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x494E + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x494F + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x4950 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x4951 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x4952 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x4953 + BPHYC_UNIPHY4_UNIPHY_TPG_CONTROL :DWORD; // 0x4954 + BPHYC_UNIPHY4_UNIPHY_TPG_SEED :DWORD; // 0x4955 + BPHYC_UNIPHY4_UNIPHY_DEBUG :DWORD; // 0x4956 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x4957 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x4958 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x4959 + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x495A + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x495B + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x495C + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x495D + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x495E + DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x495F + BPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 :DWORD; // 0x4960 + BPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 :DWORD; // 0x4961 + BPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 :DWORD; // 0x4962 + BPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 :DWORD; // 0x4963 + BPHYC_UNIPHY5_UNIPHY_POWER_CONTROL :DWORD; // 0x4964 + BPHYC_UNIPHY5_UNIPHY_PLL_FBDIV :DWORD; // 0x4965 + BPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 :DWORD; // 0x4966 + BPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 :DWORD; // 0x4967 + BPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x4968 + BPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL :DWORD; // 0x4969 + BPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x496A + BPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x496B + BPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x496C + BPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x496D + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x496E + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x496F + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x4970 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x4971 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x4972 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x4973 + BPHYC_UNIPHY5_UNIPHY_TPG_CONTROL :DWORD; // 0x4974 + BPHYC_UNIPHY5_UNIPHY_TPG_SEED :DWORD; // 0x4975 + BPHYC_UNIPHY5_UNIPHY_DEBUG :DWORD; // 0x4976 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x4977 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x4978 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x4979 + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x497A + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x497B + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x497C + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x497D + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x497E + DCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x497F + BPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 :DWORD; // 0x4980 + BPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 :DWORD; // 0x4981 + BPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 :DWORD; // 0x4982 + BPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 :DWORD; // 0x4983 + BPHYC_UNIPHY6_UNIPHY_POWER_CONTROL :DWORD; // 0x4984 + BPHYC_UNIPHY6_UNIPHY_PLL_FBDIV :DWORD; // 0x4985 + BPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 :DWORD; // 0x4986 + BPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 :DWORD; // 0x4987 + BPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE :DWORD; // 0x4988 + BPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL :DWORD; // 0x4989 + BPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION :DWORD; // 0x498A + BPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT :DWORD; // 0x498B + BPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL :DWORD; // 0x498C + BPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 :DWORD; // 0x498D + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 :DWORD; // 0x498E + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 :DWORD; // 0x498F + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 :DWORD; // 0x4990 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 :DWORD; // 0x4991 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 :DWORD; // 0x4992 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 :DWORD; // 0x4993 + BPHYC_UNIPHY6_UNIPHY_TPG_CONTROL :DWORD; // 0x4994 + BPHYC_UNIPHY6_UNIPHY_TPG_SEED :DWORD; // 0x4995 + BPHYC_UNIPHY6_UNIPHY_DEBUG :DWORD; // 0x4996 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 :DWORD; // 0x4997 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 :DWORD; // 0x4998 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 :DWORD; // 0x4999 + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 :DWORD; // 0x499A + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 :DWORD; // 0x499B + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 :DWORD; // 0x499C + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 :DWORD; // 0x499D + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 :DWORD; // 0x499E + DCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 :DWORD; // 0x499F + REG_49A0_49FF :array[0..95] of DWORD; // 0x49A0 + DIG0_DIG_FE_CNTL :DWORD; // 0x4A00 + DIG0_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4A01 + DIG0_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4A02 + DIG0_DIG_CLOCK_PATTERN :DWORD; // 0x4A03 + DIG0_DIG_TEST_PATTERN :DWORD; // 0x4A04 + DIG0_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4A05 + DIG0_DIG_FIFO_STATUS :DWORD; // 0x4A06 + DIG0_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4A07 + DIG0_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4A08 + DIG0_HDMI_CONTROL :DWORD; // 0x4A09 + DIG0_HDMI_STATUS :DWORD; // 0x4A0A + DIG0_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4A0B + DIG0_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4A0C + DIG0_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4A0D + DIG0_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4A0E + DIG0_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4A0F + DIG0_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4A10 + REG_4A11_4A12 :array[0..1] of DWORD; // 0x4A11 + DIG0_HDMI_GC :DWORD; // 0x4A13 + AFMT_AUDIO_PACKET_CONTROL2 :TAFMT_AUDIO_PACKET_CONTROL2; // 0x4A14 + AFMT_ISRC1_0 :TAFMT_ISRC1_0; // 0x4A15 + AFMT_ISRC1_1 :TAFMT_ISRC1_1; // 0x4A16 + AFMT_ISRC1_2 :TAFMT_ISRC1_2; // 0x4A17 + AFMT_ISRC1_3 :TAFMT_ISRC1_3; // 0x4A18 + AFMT_ISRC1_4 :TAFMT_ISRC1_4; // 0x4A19 + AFMT_ISRC2_0 :TAFMT_ISRC2_0; // 0x4A1A + AFMT_ISRC2_1 :TAFMT_ISRC2_1; // 0x4A1B + AFMT_ISRC2_2 :TAFMT_ISRC2_2; // 0x4A1C + AFMT_ISRC2_3 :TAFMT_ISRC2_3; // 0x4A1D + AFMT_AVI_INFO0 :TAFMT_AVI_INFO0; // 0x4A1E + AFMT_AVI_INFO1 :TAFMT_AVI_INFO1; // 0x4A1F + AFMT_AVI_INFO2 :TAFMT_AVI_INFO2; // 0x4A20 + AFMT_AVI_INFO3 :TAFMT_AVI_INFO3; // 0x4A21 + AFMT_MPEG_INFO0 :TAFMT_MPEG_INFO0; // 0x4A22 + AFMT_MPEG_INFO1 :TAFMT_MPEG_INFO1; // 0x4A23 + AFMT_GENERIC_HDR :TAFMT_GENERIC_HDR; // 0x4A24 + AFMT_GENERIC_0 :TAFMT_GENERIC_0; // 0x4A25 + AFMT_GENERIC_1 :TAFMT_GENERIC_1; // 0x4A26 + AFMT_GENERIC_2 :TAFMT_GENERIC_2; // 0x4A27 + AFMT_GENERIC_3 :TAFMT_GENERIC_3; // 0x4A28 + AFMT_GENERIC_4 :TAFMT_GENERIC_4; // 0x4A29 + AFMT_GENERIC_5 :TAFMT_GENERIC_5; // 0x4A2A + AFMT_GENERIC_6 :TAFMT_GENERIC_6; // 0x4A2B + AFMT_GENERIC_7 :TAFMT_GENERIC_7; // 0x4A2C + DIG0_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4A2D + DIG0_HDMI_ACR_32_0 :DWORD; // 0x4A2E + DIG0_HDMI_ACR_32_1 :DWORD; // 0x4A2F + DIG0_HDMI_ACR_44_0 :DWORD; // 0x4A30 + DIG0_HDMI_ACR_44_1 :DWORD; // 0x4A31 + DIG0_HDMI_ACR_48_0 :DWORD; // 0x4A32 + DIG0_HDMI_ACR_48_1 :DWORD; // 0x4A33 + DIG0_HDMI_ACR_STATUS_0 :DWORD; // 0x4A34 + DIG0_HDMI_ACR_STATUS_1 :DWORD; // 0x4A35 + AFMT_AUDIO_INFO0 :TAFMT_AUDIO_INFO0; // 0x4A36 + AFMT_AUDIO_INFO1 :TAFMT_AUDIO_INFO1; // 0x4A37 + AFMT_60958_0 :TAFMT_60958_0; // 0x4A38 + AFMT_60958_1 :TAFMT_60958_1; // 0x4A39 + AFMT_AUDIO_CRC_CONTROL :TAFMT_AUDIO_CRC_CONTROL; // 0x4A3A + AFMT_RAMP_CONTROL0 :TAFMT_RAMP_CONTROL0; // 0x4A3B + AFMT_RAMP_CONTROL1 :TAFMT_RAMP_CONTROL1; // 0x4A3C + AFMT_RAMP_CONTROL2 :TAFMT_RAMP_CONTROL2; // 0x4A3D + AFMT_RAMP_CONTROL3 :TAFMT_RAMP_CONTROL3; // 0x4A3E + AFMT_60958_2 :TAFMT_60958_2; // 0x4A3F + AFMT_AUDIO_CRC_RESULT :TAFMT_AUDIO_CRC_RESULT; // 0x4A40 + AFMT_STATUS :TAFMT_STATUS; // 0x4A41 + AFMT_AUDIO_PACKET_CONTROL :TAFMT_AUDIO_PACKET_CONTROL; // 0x4A42 + AFMT_VBI_PACKET_CONTROL :TAFMT_VBI_PACKET_CONTROL; // 0x4A43 + AFMT_INFOFRAME_CONTROL0 :TAFMT_INFOFRAME_CONTROL0; // 0x4A44 + AFMT_AUDIO_SRC_CONTROL :TAFMT_AUDIO_SRC_CONTROL; // 0x4A45 + AFMT_AUDIO_DBG_DTO_CNTL :TAFMT_AUDIO_DBG_DTO_CNTL; // 0x4A46 + DIG0_DIG_BE_CNTL :DWORD; // 0x4A47 + DIG0_DIG_BE_EN_CNTL :DWORD; // 0x4A48 + REG_4A49_4A6A :array[0..33] of DWORD; // 0x4A49 + DIG0_TMDS_CNTL :DWORD; // 0x4A6B + DIG0_TMDS_CONTROL_CHAR :DWORD; // 0x4A6C + DIG0_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4A6D + DIG0_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4A6E + DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4A6F + DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4A70 + DIG0_TMDS_DEBUG :DWORD; // 0x4A71 + DIG0_TMDS_CTL_BITS :DWORD; // 0x4A72 + DIG0_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4A73 + REG_4A74 :DWORD; // 0x4A74 + DIG0_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4A75 + DIG0_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4A76 + REG_4A77 :DWORD; // 0x4A77 + DIG0_LVDS_DATA_CNTL :DWORD; // 0x4A78 + DIG0_DIG_LANE_ENABLE :DWORD; // 0x4A79 + DIG0_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4A7A + DIG0_DIG_TEST_DEBUG_DATA :DWORD; // 0x4A7B + DIG0_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4A7C + DIG0_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4A7D + REG_4A7E_4A99 :array[0..27] of DWORD; // 0x4A7E + CRTC5_CRTC_PIXEL_DATA_READBACK :DWORD; // 0x4A9A + REG_4A9B_4A9F :array[0..4] of DWORD; // 0x4A9B + DP0_DP_LINK_CNTL :DWORD; // 0x4AA0 + DP0_DP_PIXEL_FORMAT :DWORD; // 0x4AA1 + DP0_DP_MSA_COLORIMETRY :DWORD; // 0x4AA2 + DP0_DP_CONFIG :DWORD; // 0x4AA3 + DP0_DP_VID_STREAM_CNTL :DWORD; // 0x4AA4 + DP0_DP_STEER_FIFO :DWORD; // 0x4AA5 + DP0_DP_MSA_MISC :DWORD; // 0x4AA6 + REG_4AA7 :DWORD; // 0x4AA7 + DP0_DP_VID_TIMING :DWORD; // 0x4AA8 + DP0_DP_VID_N :DWORD; // 0x4AA9 + DP0_DP_VID_M :DWORD; // 0x4AAA + DP0_DP_LINK_FRAMING_CNTL :DWORD; // 0x4AAB + DP0_DP_HBR2_EYE_PATTERN :DWORD; // 0x4AAC + DP0_DP_VID_MSA_VBID :DWORD; // 0x4AAD + DP0_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4AAE + DP0_DP_DPHY_CNTL :DWORD; // 0x4AAF + DP0_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4AB0 + DP0_DP_DPHY_SYM0 :DWORD; // 0x4AB1 + DP0_DP_DPHY_SYM1 :DWORD; // 0x4AB2 + DP0_DP_DPHY_SYM2 :DWORD; // 0x4AB3 + DP0_DP_DPHY_8B10B_CNTL :DWORD; // 0x4AB4 + DP0_DP_DPHY_PRBS_CNTL :DWORD; // 0x4AB5 + REG_4AB6 :DWORD; // 0x4AB6 + DP0_DP_DPHY_CRC_EN :DWORD; // 0x4AB7 + DP0_DP_DPHY_CRC_CNTL :DWORD; // 0x4AB8 + DP0_DP_DPHY_CRC_RESULT :DWORD; // 0x4AB9 + DP0_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4ABA + DP0_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4ABB + DP0_DP_DPHY_FAST_TRAINING :DWORD; // 0x4ABC + DP0_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4ABD + DP0_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4ABE + DP0_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4ABF + REG_4AC0_4AC2 :array[0..2] of DWORD; // 0x4AC0 + DP0_DP_SEC_CNTL :DWORD; // 0x4AC3 + DP0_DP_SEC_CNTL1 :DWORD; // 0x4AC4 + DP0_DP_SEC_FRAMING1 :DWORD; // 0x4AC5 + DP0_DP_SEC_FRAMING2 :DWORD; // 0x4AC6 + DP0_DP_SEC_FRAMING3 :DWORD; // 0x4AC7 + DP0_DP_SEC_FRAMING4 :DWORD; // 0x4AC8 + DP0_DP_SEC_AUD_N :DWORD; // 0x4AC9 + DP0_DP_SEC_AUD_N_READBACK :DWORD; // 0x4ACA + DP0_DP_SEC_AUD_M :DWORD; // 0x4ACB + DP0_DP_SEC_AUD_M_READBACK :DWORD; // 0x4ACC + DP0_DP_SEC_TIMESTAMP :DWORD; // 0x4ACD + DP0_DP_SEC_PACKET_CNTL :DWORD; // 0x4ACE + DP0_DP_MSE_RATE_CNTL :DWORD; // 0x4ACF + REG_4AD0 :DWORD; // 0x4AD0 + DP0_DP_MSE_RATE_UPDATE :DWORD; // 0x4AD1 + DP0_DP_MSE_SAT0 :DWORD; // 0x4AD2 + DP0_DP_MSE_SAT1 :DWORD; // 0x4AD3 + DP0_DP_MSE_SAT2 :DWORD; // 0x4AD4 + DP0_DP_MSE_SAT_UPDATE :DWORD; // 0x4AD5 + DP0_DP_MSE_LINK_TIMING :DWORD; // 0x4AD6 + DP0_DP_MSE_MISC_CNTL :DWORD; // 0x4AD7 + DP0_DP_TEST_DEBUG_INDEX :DWORD; // 0x4AD8 + DP0_DP_TEST_DEBUG_DATA :DWORD; // 0x4AD9 + DP0_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4ADA + DP0_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4ADB + REG_4ADC_4AFF :array[0..35] of DWORD; // 0x4ADC + DIG1_DIG_FE_CNTL :DWORD; // 0x4B00 + DIG1_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4B01 + DIG1_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4B02 + DIG1_DIG_CLOCK_PATTERN :DWORD; // 0x4B03 + DIG1_DIG_TEST_PATTERN :DWORD; // 0x4B04 + DIG1_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4B05 + DIG1_DIG_FIFO_STATUS :DWORD; // 0x4B06 + DIG1_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4B07 + DIG1_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4B08 + DIG1_HDMI_CONTROL :DWORD; // 0x4B09 + DIG1_HDMI_STATUS :DWORD; // 0x4B0A + DIG1_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4B0B + DIG1_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4B0C + DIG1_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4B0D + DIG1_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4B0E + DIG1_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4B0F + DIG1_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4B10 + REG_4B11_4B12 :array[0..1] of DWORD; // 0x4B11 + DIG1_HDMI_GC :DWORD; // 0x4B13 + DIG1_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x4B14 + DIG1_AFMT_ISRC1_0 :DWORD; // 0x4B15 + DIG1_AFMT_ISRC1_1 :DWORD; // 0x4B16 + DIG1_AFMT_ISRC1_2 :DWORD; // 0x4B17 + DIG1_AFMT_ISRC1_3 :DWORD; // 0x4B18 + DIG1_AFMT_ISRC1_4 :DWORD; // 0x4B19 + DIG1_AFMT_ISRC2_0 :DWORD; // 0x4B1A + DIG1_AFMT_ISRC2_1 :DWORD; // 0x4B1B + DIG1_AFMT_ISRC2_2 :DWORD; // 0x4B1C + DIG1_AFMT_ISRC2_3 :DWORD; // 0x4B1D + DIG1_AFMT_AVI_INFO0 :DWORD; // 0x4B1E + DIG1_AFMT_AVI_INFO1 :DWORD; // 0x4B1F + DIG1_AFMT_AVI_INFO2 :DWORD; // 0x4B20 + DIG1_AFMT_AVI_INFO3 :DWORD; // 0x4B21 + DIG1_AFMT_MPEG_INFO0 :DWORD; // 0x4B22 + DIG1_AFMT_MPEG_INFO1 :DWORD; // 0x4B23 + DIG1_AFMT_GENERIC_HDR :DWORD; // 0x4B24 + DIG1_AFMT_GENERIC_0 :DWORD; // 0x4B25 + DIG1_AFMT_GENERIC_1 :DWORD; // 0x4B26 + DIG1_AFMT_GENERIC_2 :DWORD; // 0x4B27 + DIG1_AFMT_GENERIC_3 :DWORD; // 0x4B28 + DIG1_AFMT_GENERIC_4 :DWORD; // 0x4B29 + DIG1_AFMT_GENERIC_5 :DWORD; // 0x4B2A + DIG1_AFMT_GENERIC_6 :DWORD; // 0x4B2B + DIG1_AFMT_GENERIC_7 :DWORD; // 0x4B2C + DIG1_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4B2D + DIG1_HDMI_ACR_32_0 :DWORD; // 0x4B2E + DIG1_HDMI_ACR_32_1 :DWORD; // 0x4B2F + DIG1_HDMI_ACR_44_0 :DWORD; // 0x4B30 + DIG1_HDMI_ACR_44_1 :DWORD; // 0x4B31 + DIG1_HDMI_ACR_48_0 :DWORD; // 0x4B32 + DIG1_HDMI_ACR_48_1 :DWORD; // 0x4B33 + DIG1_HDMI_ACR_STATUS_0 :DWORD; // 0x4B34 + DIG1_HDMI_ACR_STATUS_1 :DWORD; // 0x4B35 + DIG1_AFMT_AUDIO_INFO0 :DWORD; // 0x4B36 + DIG1_AFMT_AUDIO_INFO1 :DWORD; // 0x4B37 + DIG1_AFMT_60958_0 :DWORD; // 0x4B38 + DIG1_AFMT_60958_1 :DWORD; // 0x4B39 + DIG1_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x4B3A + DIG1_AFMT_RAMP_CONTROL0 :DWORD; // 0x4B3B + DIG1_AFMT_RAMP_CONTROL1 :DWORD; // 0x4B3C + DIG1_AFMT_RAMP_CONTROL2 :DWORD; // 0x4B3D + DIG1_AFMT_RAMP_CONTROL3 :DWORD; // 0x4B3E + DIG1_AFMT_60958_2 :DWORD; // 0x4B3F + DIG1_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x4B40 + DIG1_AFMT_STATUS :DWORD; // 0x4B41 + DIG1_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x4B42 + DIG1_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x4B43 + DIG1_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x4B44 + DIG1_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x4B45 + DIG1_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x4B46 + DIG1_DIG_BE_CNTL :DWORD; // 0x4B47 + DIG1_DIG_BE_EN_CNTL :DWORD; // 0x4B48 + REG_4B49_4B6A :array[0..33] of DWORD; // 0x4B49 + DIG1_TMDS_CNTL :DWORD; // 0x4B6B + DIG1_TMDS_CONTROL_CHAR :DWORD; // 0x4B6C + DIG1_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4B6D + DIG1_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4B6E + DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4B6F + DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4B70 + DIG1_TMDS_DEBUG :DWORD; // 0x4B71 + DIG1_TMDS_CTL_BITS :DWORD; // 0x4B72 + DIG1_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4B73 + REG_4B74 :DWORD; // 0x4B74 + DIG1_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4B75 + DIG1_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4B76 + REG_4B77 :DWORD; // 0x4B77 + DIG1_LVDS_DATA_CNTL :DWORD; // 0x4B78 + DIG1_DIG_LANE_ENABLE :DWORD; // 0x4B79 + DIG1_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4B7A + DIG1_DIG_TEST_DEBUG_DATA :DWORD; // 0x4B7B + DIG1_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4B7C + DIG1_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4B7D + REG_4B7E_4B9F :array[0..33] of DWORD; // 0x4B7E + DP1_DP_LINK_CNTL :DWORD; // 0x4BA0 + DP1_DP_PIXEL_FORMAT :DWORD; // 0x4BA1 + DP1_DP_MSA_COLORIMETRY :DWORD; // 0x4BA2 + DP1_DP_CONFIG :DWORD; // 0x4BA3 + DP1_DP_VID_STREAM_CNTL :DWORD; // 0x4BA4 + DP1_DP_STEER_FIFO :DWORD; // 0x4BA5 + DP1_DP_MSA_MISC :DWORD; // 0x4BA6 + REG_4BA7 :DWORD; // 0x4BA7 + DP1_DP_VID_TIMING :DWORD; // 0x4BA8 + DP1_DP_VID_N :DWORD; // 0x4BA9 + DP1_DP_VID_M :DWORD; // 0x4BAA + DP1_DP_LINK_FRAMING_CNTL :DWORD; // 0x4BAB + DP1_DP_HBR2_EYE_PATTERN :DWORD; // 0x4BAC + DP1_DP_VID_MSA_VBID :DWORD; // 0x4BAD + DP1_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4BAE + DP1_DP_DPHY_CNTL :DWORD; // 0x4BAF + DP1_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4BB0 + DP1_DP_DPHY_SYM0 :DWORD; // 0x4BB1 + DP1_DP_DPHY_SYM1 :DWORD; // 0x4BB2 + DP1_DP_DPHY_SYM2 :DWORD; // 0x4BB3 + DP1_DP_DPHY_8B10B_CNTL :DWORD; // 0x4BB4 + DP1_DP_DPHY_PRBS_CNTL :DWORD; // 0x4BB5 + REG_4BB6 :DWORD; // 0x4BB6 + DP1_DP_DPHY_CRC_EN :DWORD; // 0x4BB7 + DP1_DP_DPHY_CRC_CNTL :DWORD; // 0x4BB8 + DP1_DP_DPHY_CRC_RESULT :DWORD; // 0x4BB9 + DP1_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4BBA + DP1_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4BBB + DP1_DP_DPHY_FAST_TRAINING :DWORD; // 0x4BBC + DP1_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4BBD + DP1_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4BBE + DP1_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4BBF + REG_4BC0_4BC2 :array[0..2] of DWORD; // 0x4BC0 + DP1_DP_SEC_CNTL :DWORD; // 0x4BC3 + DP1_DP_SEC_CNTL1 :DWORD; // 0x4BC4 + DP1_DP_SEC_FRAMING1 :DWORD; // 0x4BC5 + DP1_DP_SEC_FRAMING2 :DWORD; // 0x4BC6 + DP1_DP_SEC_FRAMING3 :DWORD; // 0x4BC7 + DP1_DP_SEC_FRAMING4 :DWORD; // 0x4BC8 + DP1_DP_SEC_AUD_N :DWORD; // 0x4BC9 + DP1_DP_SEC_AUD_N_READBACK :DWORD; // 0x4BCA + DP1_DP_SEC_AUD_M :DWORD; // 0x4BCB + DP1_DP_SEC_AUD_M_READBACK :DWORD; // 0x4BCC + DP1_DP_SEC_TIMESTAMP :DWORD; // 0x4BCD + DP1_DP_SEC_PACKET_CNTL :DWORD; // 0x4BCE + DP1_DP_MSE_RATE_CNTL :DWORD; // 0x4BCF + REG_4BD0 :DWORD; // 0x4BD0 + DP1_DP_MSE_RATE_UPDATE :DWORD; // 0x4BD1 + DP1_DP_MSE_SAT0 :DWORD; // 0x4BD2 + DP1_DP_MSE_SAT1 :DWORD; // 0x4BD3 + DP1_DP_MSE_SAT2 :DWORD; // 0x4BD4 + DP1_DP_MSE_SAT_UPDATE :DWORD; // 0x4BD5 + DP1_DP_MSE_LINK_TIMING :DWORD; // 0x4BD6 + DP1_DP_MSE_MISC_CNTL :DWORD; // 0x4BD7 + DP1_DP_TEST_DEBUG_INDEX :DWORD; // 0x4BD8 + DP1_DP_TEST_DEBUG_DATA :DWORD; // 0x4BD9 + DP1_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4BDA + DP1_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4BDB + REG_4BDC_4BFF :array[0..35] of DWORD; // 0x4BDC + DIG2_DIG_FE_CNTL :DWORD; // 0x4C00 + DIG2_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4C01 + DIG2_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4C02 + DIG2_DIG_CLOCK_PATTERN :DWORD; // 0x4C03 + DIG2_DIG_TEST_PATTERN :DWORD; // 0x4C04 + DIG2_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4C05 + DIG2_DIG_FIFO_STATUS :DWORD; // 0x4C06 + DIG2_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4C07 + DIG2_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4C08 + DIG2_HDMI_CONTROL :DWORD; // 0x4C09 + DIG2_HDMI_STATUS :DWORD; // 0x4C0A + DIG2_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4C0B + DIG2_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4C0C + DIG2_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4C0D + DIG2_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4C0E + DIG2_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4C0F + DIG2_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4C10 + REG_4C11_4C12 :array[0..1] of DWORD; // 0x4C11 + DIG2_HDMI_GC :DWORD; // 0x4C13 + DIG2_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x4C14 + DIG2_AFMT_ISRC1_0 :DWORD; // 0x4C15 + DIG2_AFMT_ISRC1_1 :DWORD; // 0x4C16 + DIG2_AFMT_ISRC1_2 :DWORD; // 0x4C17 + DIG2_AFMT_ISRC1_3 :DWORD; // 0x4C18 + DIG2_AFMT_ISRC1_4 :DWORD; // 0x4C19 + DIG2_AFMT_ISRC2_0 :DWORD; // 0x4C1A + DIG2_AFMT_ISRC2_1 :DWORD; // 0x4C1B + DIG2_AFMT_ISRC2_2 :DWORD; // 0x4C1C + DIG2_AFMT_ISRC2_3 :DWORD; // 0x4C1D + DIG2_AFMT_AVI_INFO0 :DWORD; // 0x4C1E + DIG2_AFMT_AVI_INFO1 :DWORD; // 0x4C1F + DIG2_AFMT_AVI_INFO2 :DWORD; // 0x4C20 + DIG2_AFMT_AVI_INFO3 :DWORD; // 0x4C21 + DIG2_AFMT_MPEG_INFO0 :DWORD; // 0x4C22 + DIG2_AFMT_MPEG_INFO1 :DWORD; // 0x4C23 + DIG2_AFMT_GENERIC_HDR :DWORD; // 0x4C24 + DIG2_AFMT_GENERIC_0 :DWORD; // 0x4C25 + DIG2_AFMT_GENERIC_1 :DWORD; // 0x4C26 + DIG2_AFMT_GENERIC_2 :DWORD; // 0x4C27 + DIG2_AFMT_GENERIC_3 :DWORD; // 0x4C28 + DIG2_AFMT_GENERIC_4 :DWORD; // 0x4C29 + DIG2_AFMT_GENERIC_5 :DWORD; // 0x4C2A + DIG2_AFMT_GENERIC_6 :DWORD; // 0x4C2B + DIG2_AFMT_GENERIC_7 :DWORD; // 0x4C2C + DIG2_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4C2D + DIG2_HDMI_ACR_32_0 :DWORD; // 0x4C2E + DIG2_HDMI_ACR_32_1 :DWORD; // 0x4C2F + DIG2_HDMI_ACR_44_0 :DWORD; // 0x4C30 + DIG2_HDMI_ACR_44_1 :DWORD; // 0x4C31 + DIG2_HDMI_ACR_48_0 :DWORD; // 0x4C32 + DIG2_HDMI_ACR_48_1 :DWORD; // 0x4C33 + DIG2_HDMI_ACR_STATUS_0 :DWORD; // 0x4C34 + DIG2_HDMI_ACR_STATUS_1 :DWORD; // 0x4C35 + DIG2_AFMT_AUDIO_INFO0 :DWORD; // 0x4C36 + DIG2_AFMT_AUDIO_INFO1 :DWORD; // 0x4C37 + DIG2_AFMT_60958_0 :DWORD; // 0x4C38 + DIG2_AFMT_60958_1 :DWORD; // 0x4C39 + DIG2_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x4C3A + DIG2_AFMT_RAMP_CONTROL0 :DWORD; // 0x4C3B + DIG2_AFMT_RAMP_CONTROL1 :DWORD; // 0x4C3C + DIG2_AFMT_RAMP_CONTROL2 :DWORD; // 0x4C3D + DIG2_AFMT_RAMP_CONTROL3 :DWORD; // 0x4C3E + DIG2_AFMT_60958_2 :DWORD; // 0x4C3F + DIG2_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x4C40 + DIG2_AFMT_STATUS :DWORD; // 0x4C41 + DIG2_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x4C42 + DIG2_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x4C43 + DIG2_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x4C44 + DIG2_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x4C45 + DIG2_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x4C46 + DIG2_DIG_BE_CNTL :DWORD; // 0x4C47 + DIG2_DIG_BE_EN_CNTL :DWORD; // 0x4C48 + REG_4C49_4C6A :array[0..33] of DWORD; // 0x4C49 + DIG2_TMDS_CNTL :DWORD; // 0x4C6B + DIG2_TMDS_CONTROL_CHAR :DWORD; // 0x4C6C + DIG2_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4C6D + DIG2_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4C6E + DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4C6F + DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4C70 + DIG2_TMDS_DEBUG :DWORD; // 0x4C71 + DIG2_TMDS_CTL_BITS :DWORD; // 0x4C72 + DIG2_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4C73 + REG_4C74 :DWORD; // 0x4C74 + DIG2_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4C75 + DIG2_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4C76 + REG_4C77 :DWORD; // 0x4C77 + DIG2_LVDS_DATA_CNTL :DWORD; // 0x4C78 + DIG2_DIG_LANE_ENABLE :DWORD; // 0x4C79 + DIG2_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4C7A + DIG2_DIG_TEST_DEBUG_DATA :DWORD; // 0x4C7B + DIG2_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4C7C + DIG2_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4C7D + REG_4C7E_4C9F :array[0..33] of DWORD; // 0x4C7E + DP2_DP_LINK_CNTL :DWORD; // 0x4CA0 + DP2_DP_PIXEL_FORMAT :DWORD; // 0x4CA1 + DP2_DP_MSA_COLORIMETRY :DWORD; // 0x4CA2 + DP2_DP_CONFIG :DWORD; // 0x4CA3 + DP2_DP_VID_STREAM_CNTL :DWORD; // 0x4CA4 + DP2_DP_STEER_FIFO :DWORD; // 0x4CA5 + DP2_DP_MSA_MISC :DWORD; // 0x4CA6 + REG_4CA7 :DWORD; // 0x4CA7 + DP2_DP_VID_TIMING :DWORD; // 0x4CA8 + DP2_DP_VID_N :DWORD; // 0x4CA9 + DP2_DP_VID_M :DWORD; // 0x4CAA + DP2_DP_LINK_FRAMING_CNTL :DWORD; // 0x4CAB + DP2_DP_HBR2_EYE_PATTERN :DWORD; // 0x4CAC + DP2_DP_VID_MSA_VBID :DWORD; // 0x4CAD + DP2_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4CAE + DP2_DP_DPHY_CNTL :DWORD; // 0x4CAF + DP2_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4CB0 + DP2_DP_DPHY_SYM0 :DWORD; // 0x4CB1 + DP2_DP_DPHY_SYM1 :DWORD; // 0x4CB2 + DP2_DP_DPHY_SYM2 :DWORD; // 0x4CB3 + DP2_DP_DPHY_8B10B_CNTL :DWORD; // 0x4CB4 + DP2_DP_DPHY_PRBS_CNTL :DWORD; // 0x4CB5 + REG_4CB6 :DWORD; // 0x4CB6 + DP2_DP_DPHY_CRC_EN :DWORD; // 0x4CB7 + DP2_DP_DPHY_CRC_CNTL :DWORD; // 0x4CB8 + DP2_DP_DPHY_CRC_RESULT :DWORD; // 0x4CB9 + DP2_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4CBA + DP2_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4CBB + DP2_DP_DPHY_FAST_TRAINING :DWORD; // 0x4CBC + DP2_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4CBD + DP2_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4CBE + DP2_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4CBF + REG_4CC0_4CC2 :array[0..2] of DWORD; // 0x4CC0 + DP2_DP_SEC_CNTL :DWORD; // 0x4CC3 + DP2_DP_SEC_CNTL1 :DWORD; // 0x4CC4 + DP2_DP_SEC_FRAMING1 :DWORD; // 0x4CC5 + DP2_DP_SEC_FRAMING2 :DWORD; // 0x4CC6 + DP2_DP_SEC_FRAMING3 :DWORD; // 0x4CC7 + DP2_DP_SEC_FRAMING4 :DWORD; // 0x4CC8 + DP2_DP_SEC_AUD_N :DWORD; // 0x4CC9 + DP2_DP_SEC_AUD_N_READBACK :DWORD; // 0x4CCA + DP2_DP_SEC_AUD_M :DWORD; // 0x4CCB + DP2_DP_SEC_AUD_M_READBACK :DWORD; // 0x4CCC + DP2_DP_SEC_TIMESTAMP :DWORD; // 0x4CCD + DP2_DP_SEC_PACKET_CNTL :DWORD; // 0x4CCE + DP2_DP_MSE_RATE_CNTL :DWORD; // 0x4CCF + REG_4CD0 :DWORD; // 0x4CD0 + DP2_DP_MSE_RATE_UPDATE :DWORD; // 0x4CD1 + DP2_DP_MSE_SAT0 :DWORD; // 0x4CD2 + DP2_DP_MSE_SAT1 :DWORD; // 0x4CD3 + DP2_DP_MSE_SAT2 :DWORD; // 0x4CD4 + DP2_DP_MSE_SAT_UPDATE :DWORD; // 0x4CD5 + DP2_DP_MSE_LINK_TIMING :DWORD; // 0x4CD6 + DP2_DP_MSE_MISC_CNTL :DWORD; // 0x4CD7 + DP2_DP_TEST_DEBUG_INDEX :DWORD; // 0x4CD8 + DP2_DP_TEST_DEBUG_DATA :DWORD; // 0x4CD9 + DP2_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4CDA + DP2_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4CDB + REG_4CDC_4CFF :array[0..35] of DWORD; // 0x4CDC + DIG3_DIG_FE_CNTL :DWORD; // 0x4D00 + DIG3_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4D01 + DIG3_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4D02 + DIG3_DIG_CLOCK_PATTERN :DWORD; // 0x4D03 + DIG3_DIG_TEST_PATTERN :DWORD; // 0x4D04 + DIG3_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4D05 + DIG3_DIG_FIFO_STATUS :DWORD; // 0x4D06 + DIG3_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4D07 + DIG3_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4D08 + DIG3_HDMI_CONTROL :DWORD; // 0x4D09 + DIG3_HDMI_STATUS :DWORD; // 0x4D0A + DIG3_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4D0B + DIG3_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4D0C + DIG3_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4D0D + DIG3_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4D0E + DIG3_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4D0F + DIG3_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4D10 + REG_4D11_4D12 :array[0..1] of DWORD; // 0x4D11 + DIG3_HDMI_GC :DWORD; // 0x4D13 + DIG3_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x4D14 + DIG3_AFMT_ISRC1_0 :DWORD; // 0x4D15 + DIG3_AFMT_ISRC1_1 :DWORD; // 0x4D16 + DIG3_AFMT_ISRC1_2 :DWORD; // 0x4D17 + DIG3_AFMT_ISRC1_3 :DWORD; // 0x4D18 + DIG3_AFMT_ISRC1_4 :DWORD; // 0x4D19 + DIG3_AFMT_ISRC2_0 :DWORD; // 0x4D1A + DIG3_AFMT_ISRC2_1 :DWORD; // 0x4D1B + DIG3_AFMT_ISRC2_2 :DWORD; // 0x4D1C + DIG3_AFMT_ISRC2_3 :DWORD; // 0x4D1D + DIG3_AFMT_AVI_INFO0 :DWORD; // 0x4D1E + DIG3_AFMT_AVI_INFO1 :DWORD; // 0x4D1F + DIG3_AFMT_AVI_INFO2 :DWORD; // 0x4D20 + DIG3_AFMT_AVI_INFO3 :DWORD; // 0x4D21 + DIG3_AFMT_MPEG_INFO0 :DWORD; // 0x4D22 + DIG3_AFMT_MPEG_INFO1 :DWORD; // 0x4D23 + DIG3_AFMT_GENERIC_HDR :DWORD; // 0x4D24 + DIG3_AFMT_GENERIC_0 :DWORD; // 0x4D25 + DIG3_AFMT_GENERIC_1 :DWORD; // 0x4D26 + DIG3_AFMT_GENERIC_2 :DWORD; // 0x4D27 + DIG3_AFMT_GENERIC_3 :DWORD; // 0x4D28 + DIG3_AFMT_GENERIC_4 :DWORD; // 0x4D29 + DIG3_AFMT_GENERIC_5 :DWORD; // 0x4D2A + DIG3_AFMT_GENERIC_6 :DWORD; // 0x4D2B + DIG3_AFMT_GENERIC_7 :DWORD; // 0x4D2C + DIG3_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4D2D + DIG3_HDMI_ACR_32_0 :DWORD; // 0x4D2E + DIG3_HDMI_ACR_32_1 :DWORD; // 0x4D2F + DIG3_HDMI_ACR_44_0 :DWORD; // 0x4D30 + DIG3_HDMI_ACR_44_1 :DWORD; // 0x4D31 + DIG3_HDMI_ACR_48_0 :DWORD; // 0x4D32 + DIG3_HDMI_ACR_48_1 :DWORD; // 0x4D33 + DIG3_HDMI_ACR_STATUS_0 :DWORD; // 0x4D34 + DIG3_HDMI_ACR_STATUS_1 :DWORD; // 0x4D35 + DIG3_AFMT_AUDIO_INFO0 :DWORD; // 0x4D36 + DIG3_AFMT_AUDIO_INFO1 :DWORD; // 0x4D37 + DIG3_AFMT_60958_0 :DWORD; // 0x4D38 + DIG3_AFMT_60958_1 :DWORD; // 0x4D39 + DIG3_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x4D3A + DIG3_AFMT_RAMP_CONTROL0 :DWORD; // 0x4D3B + DIG3_AFMT_RAMP_CONTROL1 :DWORD; // 0x4D3C + DIG3_AFMT_RAMP_CONTROL2 :DWORD; // 0x4D3D + DIG3_AFMT_RAMP_CONTROL3 :DWORD; // 0x4D3E + DIG3_AFMT_60958_2 :DWORD; // 0x4D3F + DIG3_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x4D40 + DIG3_AFMT_STATUS :DWORD; // 0x4D41 + DIG3_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x4D42 + DIG3_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x4D43 + DIG3_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x4D44 + DIG3_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x4D45 + DIG3_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x4D46 + DIG3_DIG_BE_CNTL :DWORD; // 0x4D47 + DIG3_DIG_BE_EN_CNTL :DWORD; // 0x4D48 + REG_4D49_4D6A :array[0..33] of DWORD; // 0x4D49 + DIG3_TMDS_CNTL :DWORD; // 0x4D6B + DIG3_TMDS_CONTROL_CHAR :DWORD; // 0x4D6C + DIG3_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4D6D + DIG3_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4D6E + DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4D6F + DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4D70 + DIG3_TMDS_DEBUG :DWORD; // 0x4D71 + DIG3_TMDS_CTL_BITS :DWORD; // 0x4D72 + DIG3_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4D73 + REG_4D74 :DWORD; // 0x4D74 + DIG3_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4D75 + DIG3_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4D76 + REG_4D77 :DWORD; // 0x4D77 + DIG3_LVDS_DATA_CNTL :DWORD; // 0x4D78 + DIG3_DIG_LANE_ENABLE :DWORD; // 0x4D79 + DIG3_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4D7A + DIG3_DIG_TEST_DEBUG_DATA :DWORD; // 0x4D7B + DIG3_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4D7C + DIG3_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4D7D + REG_4D7E_4D9F :array[0..33] of DWORD; // 0x4D7E + DP3_DP_LINK_CNTL :DWORD; // 0x4DA0 + DP3_DP_PIXEL_FORMAT :DWORD; // 0x4DA1 + DP3_DP_MSA_COLORIMETRY :DWORD; // 0x4DA2 + DP3_DP_CONFIG :DWORD; // 0x4DA3 + DP3_DP_VID_STREAM_CNTL :DWORD; // 0x4DA4 + DP3_DP_STEER_FIFO :DWORD; // 0x4DA5 + DP3_DP_MSA_MISC :DWORD; // 0x4DA6 + REG_4DA7 :DWORD; // 0x4DA7 + DP3_DP_VID_TIMING :DWORD; // 0x4DA8 + DP3_DP_VID_N :DWORD; // 0x4DA9 + DP3_DP_VID_M :DWORD; // 0x4DAA + DP3_DP_LINK_FRAMING_CNTL :DWORD; // 0x4DAB + DP3_DP_HBR2_EYE_PATTERN :DWORD; // 0x4DAC + DP3_DP_VID_MSA_VBID :DWORD; // 0x4DAD + DP3_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4DAE + DP3_DP_DPHY_CNTL :DWORD; // 0x4DAF + DP3_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4DB0 + DP3_DP_DPHY_SYM0 :DWORD; // 0x4DB1 + DP3_DP_DPHY_SYM1 :DWORD; // 0x4DB2 + DP3_DP_DPHY_SYM2 :DWORD; // 0x4DB3 + DP3_DP_DPHY_8B10B_CNTL :DWORD; // 0x4DB4 + DP3_DP_DPHY_PRBS_CNTL :DWORD; // 0x4DB5 + REG_4DB6 :DWORD; // 0x4DB6 + DP3_DP_DPHY_CRC_EN :DWORD; // 0x4DB7 + DP3_DP_DPHY_CRC_CNTL :DWORD; // 0x4DB8 + DP3_DP_DPHY_CRC_RESULT :DWORD; // 0x4DB9 + DP3_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4DBA + DP3_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4DBB + DP3_DP_DPHY_FAST_TRAINING :DWORD; // 0x4DBC + DP3_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4DBD + DP3_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4DBE + DP3_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4DBF + REG_4DC0_4DC2 :array[0..2] of DWORD; // 0x4DC0 + DP3_DP_SEC_CNTL :DWORD; // 0x4DC3 + DP3_DP_SEC_CNTL1 :DWORD; // 0x4DC4 + DP3_DP_SEC_FRAMING1 :DWORD; // 0x4DC5 + DP3_DP_SEC_FRAMING2 :DWORD; // 0x4DC6 + DP3_DP_SEC_FRAMING3 :DWORD; // 0x4DC7 + DP3_DP_SEC_FRAMING4 :DWORD; // 0x4DC8 + DP3_DP_SEC_AUD_N :DWORD; // 0x4DC9 + DP3_DP_SEC_AUD_N_READBACK :DWORD; // 0x4DCA + DP3_DP_SEC_AUD_M :DWORD; // 0x4DCB + DP3_DP_SEC_AUD_M_READBACK :DWORD; // 0x4DCC + DP3_DP_SEC_TIMESTAMP :DWORD; // 0x4DCD + DP3_DP_SEC_PACKET_CNTL :DWORD; // 0x4DCE + DP3_DP_MSE_RATE_CNTL :DWORD; // 0x4DCF + REG_4DD0 :DWORD; // 0x4DD0 + DP3_DP_MSE_RATE_UPDATE :DWORD; // 0x4DD1 + DP3_DP_MSE_SAT0 :DWORD; // 0x4DD2 + DP3_DP_MSE_SAT1 :DWORD; // 0x4DD3 + DP3_DP_MSE_SAT2 :DWORD; // 0x4DD4 + DP3_DP_MSE_SAT_UPDATE :DWORD; // 0x4DD5 + DP3_DP_MSE_LINK_TIMING :DWORD; // 0x4DD6 + DP3_DP_MSE_MISC_CNTL :DWORD; // 0x4DD7 + DP3_DP_TEST_DEBUG_INDEX :DWORD; // 0x4DD8 + DP3_DP_TEST_DEBUG_DATA :DWORD; // 0x4DD9 + DP3_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4DDA + DP3_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4DDB + REG_4DDC_4DFF :array[0..35] of DWORD; // 0x4DDC + DIG4_DIG_FE_CNTL :DWORD; // 0x4E00 + DIG4_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4E01 + DIG4_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4E02 + DIG4_DIG_CLOCK_PATTERN :DWORD; // 0x4E03 + DIG4_DIG_TEST_PATTERN :DWORD; // 0x4E04 + DIG4_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4E05 + DIG4_DIG_FIFO_STATUS :DWORD; // 0x4E06 + DIG4_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4E07 + DIG4_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4E08 + DIG4_HDMI_CONTROL :DWORD; // 0x4E09 + DIG4_HDMI_STATUS :DWORD; // 0x4E0A + DIG4_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4E0B + DIG4_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4E0C + DIG4_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4E0D + DIG4_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4E0E + DIG4_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4E0F + DIG4_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4E10 + REG_4E11_4E12 :array[0..1] of DWORD; // 0x4E11 + DIG4_HDMI_GC :DWORD; // 0x4E13 + DIG4_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x4E14 + DIG4_AFMT_ISRC1_0 :DWORD; // 0x4E15 + DIG4_AFMT_ISRC1_1 :DWORD; // 0x4E16 + DIG4_AFMT_ISRC1_2 :DWORD; // 0x4E17 + DIG4_AFMT_ISRC1_3 :DWORD; // 0x4E18 + DIG4_AFMT_ISRC1_4 :DWORD; // 0x4E19 + DIG4_AFMT_ISRC2_0 :DWORD; // 0x4E1A + DIG4_AFMT_ISRC2_1 :DWORD; // 0x4E1B + DIG4_AFMT_ISRC2_2 :DWORD; // 0x4E1C + DIG4_AFMT_ISRC2_3 :DWORD; // 0x4E1D + DIG4_AFMT_AVI_INFO0 :DWORD; // 0x4E1E + DIG4_AFMT_AVI_INFO1 :DWORD; // 0x4E1F + DIG4_AFMT_AVI_INFO2 :DWORD; // 0x4E20 + DIG4_AFMT_AVI_INFO3 :DWORD; // 0x4E21 + DIG4_AFMT_MPEG_INFO0 :DWORD; // 0x4E22 + DIG4_AFMT_MPEG_INFO1 :DWORD; // 0x4E23 + DIG4_AFMT_GENERIC_HDR :DWORD; // 0x4E24 + DIG4_AFMT_GENERIC_0 :DWORD; // 0x4E25 + DIG4_AFMT_GENERIC_1 :DWORD; // 0x4E26 + DIG4_AFMT_GENERIC_2 :DWORD; // 0x4E27 + DIG4_AFMT_GENERIC_3 :DWORD; // 0x4E28 + DIG4_AFMT_GENERIC_4 :DWORD; // 0x4E29 + DIG4_AFMT_GENERIC_5 :DWORD; // 0x4E2A + DIG4_AFMT_GENERIC_6 :DWORD; // 0x4E2B + DIG4_AFMT_GENERIC_7 :DWORD; // 0x4E2C + DIG4_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4E2D + DIG4_HDMI_ACR_32_0 :DWORD; // 0x4E2E + DIG4_HDMI_ACR_32_1 :DWORD; // 0x4E2F + DIG4_HDMI_ACR_44_0 :DWORD; // 0x4E30 + DIG4_HDMI_ACR_44_1 :DWORD; // 0x4E31 + DIG4_HDMI_ACR_48_0 :DWORD; // 0x4E32 + DIG4_HDMI_ACR_48_1 :DWORD; // 0x4E33 + DIG4_HDMI_ACR_STATUS_0 :DWORD; // 0x4E34 + DIG4_HDMI_ACR_STATUS_1 :DWORD; // 0x4E35 + DIG4_AFMT_AUDIO_INFO0 :DWORD; // 0x4E36 + DIG4_AFMT_AUDIO_INFO1 :DWORD; // 0x4E37 + DIG4_AFMT_60958_0 :DWORD; // 0x4E38 + DIG4_AFMT_60958_1 :DWORD; // 0x4E39 + DIG4_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x4E3A + DIG4_AFMT_RAMP_CONTROL0 :DWORD; // 0x4E3B + DIG4_AFMT_RAMP_CONTROL1 :DWORD; // 0x4E3C + DIG4_AFMT_RAMP_CONTROL2 :DWORD; // 0x4E3D + DIG4_AFMT_RAMP_CONTROL3 :DWORD; // 0x4E3E + DIG4_AFMT_60958_2 :DWORD; // 0x4E3F + DIG4_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x4E40 + DIG4_AFMT_STATUS :DWORD; // 0x4E41 + DIG4_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x4E42 + DIG4_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x4E43 + DIG4_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x4E44 + DIG4_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x4E45 + DIG4_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x4E46 + DIG4_DIG_BE_CNTL :DWORD; // 0x4E47 + DIG4_DIG_BE_EN_CNTL :DWORD; // 0x4E48 + REG_4E49_4E6A :array[0..33] of DWORD; // 0x4E49 + DIG4_TMDS_CNTL :DWORD; // 0x4E6B + DIG4_TMDS_CONTROL_CHAR :DWORD; // 0x4E6C + DIG4_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4E6D + DIG4_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4E6E + DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4E6F + DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4E70 + DIG4_TMDS_DEBUG :DWORD; // 0x4E71 + DIG4_TMDS_CTL_BITS :DWORD; // 0x4E72 + DIG4_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4E73 + REG_4E74 :DWORD; // 0x4E74 + DIG4_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4E75 + DIG4_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4E76 + REG_4E77 :DWORD; // 0x4E77 + DIG4_LVDS_DATA_CNTL :DWORD; // 0x4E78 + DIG4_DIG_LANE_ENABLE :DWORD; // 0x4E79 + DIG4_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4E7A + DIG4_DIG_TEST_DEBUG_DATA :DWORD; // 0x4E7B + DIG4_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4E7C + DIG4_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4E7D + REG_4E7E_4E9F :array[0..33] of DWORD; // 0x4E7E + DP4_DP_LINK_CNTL :DWORD; // 0x4EA0 + DP4_DP_PIXEL_FORMAT :DWORD; // 0x4EA1 + DP4_DP_MSA_COLORIMETRY :DWORD; // 0x4EA2 + DP4_DP_CONFIG :DWORD; // 0x4EA3 + DP4_DP_VID_STREAM_CNTL :DWORD; // 0x4EA4 + DP4_DP_STEER_FIFO :DWORD; // 0x4EA5 + DP4_DP_MSA_MISC :DWORD; // 0x4EA6 + REG_4EA7 :DWORD; // 0x4EA7 + DP4_DP_VID_TIMING :DWORD; // 0x4EA8 + DP4_DP_VID_N :DWORD; // 0x4EA9 + DP4_DP_VID_M :DWORD; // 0x4EAA + DP4_DP_LINK_FRAMING_CNTL :DWORD; // 0x4EAB + DP4_DP_HBR2_EYE_PATTERN :DWORD; // 0x4EAC + DP4_DP_VID_MSA_VBID :DWORD; // 0x4EAD + DP4_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4EAE + DP4_DP_DPHY_CNTL :DWORD; // 0x4EAF + DP4_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4EB0 + DP4_DP_DPHY_SYM0 :DWORD; // 0x4EB1 + DP4_DP_DPHY_SYM1 :DWORD; // 0x4EB2 + DP4_DP_DPHY_SYM2 :DWORD; // 0x4EB3 + DP4_DP_DPHY_8B10B_CNTL :DWORD; // 0x4EB4 + DP4_DP_DPHY_PRBS_CNTL :DWORD; // 0x4EB5 + REG_4EB6 :DWORD; // 0x4EB6 + DP4_DP_DPHY_CRC_EN :DWORD; // 0x4EB7 + DP4_DP_DPHY_CRC_CNTL :DWORD; // 0x4EB8 + DP4_DP_DPHY_CRC_RESULT :DWORD; // 0x4EB9 + DP4_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4EBA + DP4_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4EBB + DP4_DP_DPHY_FAST_TRAINING :DWORD; // 0x4EBC + DP4_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4EBD + DP4_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4EBE + DP4_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4EBF + REG_4EC0_4EC2 :array[0..2] of DWORD; // 0x4EC0 + DP4_DP_SEC_CNTL :DWORD; // 0x4EC3 + DP4_DP_SEC_CNTL1 :DWORD; // 0x4EC4 + DP4_DP_SEC_FRAMING1 :DWORD; // 0x4EC5 + DP4_DP_SEC_FRAMING2 :DWORD; // 0x4EC6 + DP4_DP_SEC_FRAMING3 :DWORD; // 0x4EC7 + DP4_DP_SEC_FRAMING4 :DWORD; // 0x4EC8 + DP4_DP_SEC_AUD_N :DWORD; // 0x4EC9 + DP4_DP_SEC_AUD_N_READBACK :DWORD; // 0x4ECA + DP4_DP_SEC_AUD_M :DWORD; // 0x4ECB + DP4_DP_SEC_AUD_M_READBACK :DWORD; // 0x4ECC + DP4_DP_SEC_TIMESTAMP :DWORD; // 0x4ECD + DP4_DP_SEC_PACKET_CNTL :DWORD; // 0x4ECE + DP4_DP_MSE_RATE_CNTL :DWORD; // 0x4ECF + REG_4ED0 :DWORD; // 0x4ED0 + DP4_DP_MSE_RATE_UPDATE :DWORD; // 0x4ED1 + DP4_DP_MSE_SAT0 :DWORD; // 0x4ED2 + DP4_DP_MSE_SAT1 :DWORD; // 0x4ED3 + DP4_DP_MSE_SAT2 :DWORD; // 0x4ED4 + DP4_DP_MSE_SAT_UPDATE :DWORD; // 0x4ED5 + DP4_DP_MSE_LINK_TIMING :DWORD; // 0x4ED6 + DP4_DP_MSE_MISC_CNTL :DWORD; // 0x4ED7 + DP4_DP_TEST_DEBUG_INDEX :DWORD; // 0x4ED8 + DP4_DP_TEST_DEBUG_DATA :DWORD; // 0x4ED9 + DP4_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4EDA + DP4_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4EDB + REG_4EDC_4EFF :array[0..35] of DWORD; // 0x4EDC + DIG5_DIG_FE_CNTL :DWORD; // 0x4F00 + DIG5_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x4F01 + DIG5_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x4F02 + DIG5_DIG_CLOCK_PATTERN :DWORD; // 0x4F03 + DIG5_DIG_TEST_PATTERN :DWORD; // 0x4F04 + DIG5_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x4F05 + DIG5_DIG_FIFO_STATUS :DWORD; // 0x4F06 + DIG5_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x4F07 + DIG5_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x4F08 + DIG5_HDMI_CONTROL :DWORD; // 0x4F09 + DIG5_HDMI_STATUS :DWORD; // 0x4F0A + DIG5_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x4F0B + DIG5_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x4F0C + DIG5_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x4F0D + DIG5_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x4F0E + DIG5_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x4F0F + DIG5_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x4F10 + REG_4F11_4F12 :array[0..1] of DWORD; // 0x4F11 + DIG5_HDMI_GC :DWORD; // 0x4F13 + DIG5_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x4F14 + DIG5_AFMT_ISRC1_0 :DWORD; // 0x4F15 + DIG5_AFMT_ISRC1_1 :DWORD; // 0x4F16 + DIG5_AFMT_ISRC1_2 :DWORD; // 0x4F17 + DIG5_AFMT_ISRC1_3 :DWORD; // 0x4F18 + DIG5_AFMT_ISRC1_4 :DWORD; // 0x4F19 + DIG5_AFMT_ISRC2_0 :DWORD; // 0x4F1A + DIG5_AFMT_ISRC2_1 :DWORD; // 0x4F1B + DIG5_AFMT_ISRC2_2 :DWORD; // 0x4F1C + DIG5_AFMT_ISRC2_3 :DWORD; // 0x4F1D + DIG5_AFMT_AVI_INFO0 :DWORD; // 0x4F1E + DIG5_AFMT_AVI_INFO1 :DWORD; // 0x4F1F + DIG5_AFMT_AVI_INFO2 :DWORD; // 0x4F20 + DIG5_AFMT_AVI_INFO3 :DWORD; // 0x4F21 + DIG5_AFMT_MPEG_INFO0 :DWORD; // 0x4F22 + DIG5_AFMT_MPEG_INFO1 :DWORD; // 0x4F23 + DIG5_AFMT_GENERIC_HDR :DWORD; // 0x4F24 + DIG5_AFMT_GENERIC_0 :DWORD; // 0x4F25 + DIG5_AFMT_GENERIC_1 :DWORD; // 0x4F26 + DIG5_AFMT_GENERIC_2 :DWORD; // 0x4F27 + DIG5_AFMT_GENERIC_3 :DWORD; // 0x4F28 + DIG5_AFMT_GENERIC_4 :DWORD; // 0x4F29 + DIG5_AFMT_GENERIC_5 :DWORD; // 0x4F2A + DIG5_AFMT_GENERIC_6 :DWORD; // 0x4F2B + DIG5_AFMT_GENERIC_7 :DWORD; // 0x4F2C + DIG5_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x4F2D + DIG5_HDMI_ACR_32_0 :DWORD; // 0x4F2E + DIG5_HDMI_ACR_32_1 :DWORD; // 0x4F2F + DIG5_HDMI_ACR_44_0 :DWORD; // 0x4F30 + DIG5_HDMI_ACR_44_1 :DWORD; // 0x4F31 + DIG5_HDMI_ACR_48_0 :DWORD; // 0x4F32 + DIG5_HDMI_ACR_48_1 :DWORD; // 0x4F33 + DIG5_HDMI_ACR_STATUS_0 :DWORD; // 0x4F34 + DIG5_HDMI_ACR_STATUS_1 :DWORD; // 0x4F35 + DIG5_AFMT_AUDIO_INFO0 :DWORD; // 0x4F36 + DIG5_AFMT_AUDIO_INFO1 :DWORD; // 0x4F37 + DIG5_AFMT_60958_0 :DWORD; // 0x4F38 + DIG5_AFMT_60958_1 :DWORD; // 0x4F39 + DIG5_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x4F3A + DIG5_AFMT_RAMP_CONTROL0 :DWORD; // 0x4F3B + DIG5_AFMT_RAMP_CONTROL1 :DWORD; // 0x4F3C + DIG5_AFMT_RAMP_CONTROL2 :DWORD; // 0x4F3D + DIG5_AFMT_RAMP_CONTROL3 :DWORD; // 0x4F3E + DIG5_AFMT_60958_2 :DWORD; // 0x4F3F + DIG5_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x4F40 + DIG5_AFMT_STATUS :DWORD; // 0x4F41 + DIG5_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x4F42 + DIG5_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x4F43 + DIG5_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x4F44 + DIG5_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x4F45 + DIG5_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x4F46 + DIG5_DIG_BE_CNTL :DWORD; // 0x4F47 + DIG5_DIG_BE_EN_CNTL :DWORD; // 0x4F48 + REG_4F49_4F6A :array[0..33] of DWORD; // 0x4F49 + DIG5_TMDS_CNTL :DWORD; // 0x4F6B + DIG5_TMDS_CONTROL_CHAR :DWORD; // 0x4F6C + DIG5_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x4F6D + DIG5_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x4F6E + DIG5_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x4F6F + DIG5_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x4F70 + DIG5_TMDS_DEBUG :DWORD; // 0x4F71 + DIG5_TMDS_CTL_BITS :DWORD; // 0x4F72 + DIG5_TMDS_DCBALANCER_CONTROL :DWORD; // 0x4F73 + REG_4F74 :DWORD; // 0x4F74 + DIG5_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x4F75 + DIG5_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x4F76 + REG_4F77 :DWORD; // 0x4F77 + DIG5_LVDS_DATA_CNTL :DWORD; // 0x4F78 + DIG5_DIG_LANE_ENABLE :DWORD; // 0x4F79 + DIG5_DIG_TEST_DEBUG_INDEX :DWORD; // 0x4F7A + DIG5_DIG_TEST_DEBUG_DATA :DWORD; // 0x4F7B + DIG5_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x4F7C + DIG5_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x4F7D + REG_4F7E_4F9F :array[0..33] of DWORD; // 0x4F7E + DP5_DP_LINK_CNTL :DWORD; // 0x4FA0 + DP5_DP_PIXEL_FORMAT :DWORD; // 0x4FA1 + DP5_DP_MSA_COLORIMETRY :DWORD; // 0x4FA2 + DP5_DP_CONFIG :DWORD; // 0x4FA3 + DP5_DP_VID_STREAM_CNTL :DWORD; // 0x4FA4 + DP5_DP_STEER_FIFO :DWORD; // 0x4FA5 + DP5_DP_MSA_MISC :DWORD; // 0x4FA6 + REG_4FA7 :DWORD; // 0x4FA7 + DP5_DP_VID_TIMING :DWORD; // 0x4FA8 + DP5_DP_VID_N :DWORD; // 0x4FA9 + DP5_DP_VID_M :DWORD; // 0x4FAA + DP5_DP_LINK_FRAMING_CNTL :DWORD; // 0x4FAB + DP5_DP_HBR2_EYE_PATTERN :DWORD; // 0x4FAC + DP5_DP_VID_MSA_VBID :DWORD; // 0x4FAD + DP5_DP_VID_INTERRUPT_CNTL :DWORD; // 0x4FAE + DP5_DP_DPHY_CNTL :DWORD; // 0x4FAF + DP5_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x4FB0 + DP5_DP_DPHY_SYM0 :DWORD; // 0x4FB1 + DP5_DP_DPHY_SYM1 :DWORD; // 0x4FB2 + DP5_DP_DPHY_SYM2 :DWORD; // 0x4FB3 + DP5_DP_DPHY_8B10B_CNTL :DWORD; // 0x4FB4 + DP5_DP_DPHY_PRBS_CNTL :DWORD; // 0x4FB5 + REG_4FB6 :DWORD; // 0x4FB6 + DP5_DP_DPHY_CRC_EN :DWORD; // 0x4FB7 + DP5_DP_DPHY_CRC_CNTL :DWORD; // 0x4FB8 + DP5_DP_DPHY_CRC_RESULT :DWORD; // 0x4FB9 + DP5_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x4FBA + DP5_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x4FBB + DP5_DP_DPHY_FAST_TRAINING :DWORD; // 0x4FBC + DP5_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x4FBD + DP5_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x4FBE + DP5_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x4FBF + REG_4FC0_4FC2 :array[0..2] of DWORD; // 0x4FC0 + DP5_DP_SEC_CNTL :DWORD; // 0x4FC3 + DP5_DP_SEC_CNTL1 :DWORD; // 0x4FC4 + DP5_DP_SEC_FRAMING1 :DWORD; // 0x4FC5 + DP5_DP_SEC_FRAMING2 :DWORD; // 0x4FC6 + DP5_DP_SEC_FRAMING3 :DWORD; // 0x4FC7 + DP5_DP_SEC_FRAMING4 :DWORD; // 0x4FC8 + DP5_DP_SEC_AUD_N :DWORD; // 0x4FC9 + DP5_DP_SEC_AUD_N_READBACK :DWORD; // 0x4FCA + DP5_DP_SEC_AUD_M :DWORD; // 0x4FCB + DP5_DP_SEC_AUD_M_READBACK :DWORD; // 0x4FCC + DP5_DP_SEC_TIMESTAMP :DWORD; // 0x4FCD + DP5_DP_SEC_PACKET_CNTL :DWORD; // 0x4FCE + DP5_DP_MSE_RATE_CNTL :DWORD; // 0x4FCF + REG_4FD0 :DWORD; // 0x4FD0 + DP5_DP_MSE_RATE_UPDATE :DWORD; // 0x4FD1 + DP5_DP_MSE_SAT0 :DWORD; // 0x4FD2 + DP5_DP_MSE_SAT1 :DWORD; // 0x4FD3 + DP5_DP_MSE_SAT2 :DWORD; // 0x4FD4 + DP5_DP_MSE_SAT_UPDATE :DWORD; // 0x4FD5 + DP5_DP_MSE_LINK_TIMING :DWORD; // 0x4FD6 + DP5_DP_MSE_MISC_CNTL :DWORD; // 0x4FD7 + DP5_DP_TEST_DEBUG_INDEX :DWORD; // 0x4FD8 + DP5_DP_TEST_DEBUG_DATA :DWORD; // 0x4FD9 + DP5_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x4FDA + DP5_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x4FDB + REG_4FDC_53FF :array[0..1059] of DWORD; // 0x4FDC + DIG6_DIG_FE_CNTL :DWORD; // 0x5400 + DIG6_DIG_OUTPUT_CRC_CNTL :DWORD; // 0x5401 + DIG6_DIG_OUTPUT_CRC_RESULT :DWORD; // 0x5402 + DIG6_DIG_CLOCK_PATTERN :DWORD; // 0x5403 + DIG6_DIG_TEST_PATTERN :DWORD; // 0x5404 + DIG6_DIG_RANDOM_PATTERN_SEED :DWORD; // 0x5405 + DIG6_DIG_FIFO_STATUS :DWORD; // 0x5406 + DIG6_DIG_DISPCLK_SWITCH_CNTL :DWORD; // 0x5407 + DIG6_DIG_DISPCLK_SWITCH_STATUS :DWORD; // 0x5408 + DIG6_HDMI_CONTROL :DWORD; // 0x5409 + DIG6_HDMI_STATUS :DWORD; // 0x540A + DIG6_HDMI_AUDIO_PACKET_CONTROL :DWORD; // 0x540B + DIG6_HDMI_ACR_PACKET_CONTROL :DWORD; // 0x540C + DIG6_HDMI_VBI_PACKET_CONTROL :DWORD; // 0x540D + DIG6_HDMI_INFOFRAME_CONTROL0 :DWORD; // 0x540E + DIG6_HDMI_INFOFRAME_CONTROL1 :DWORD; // 0x540F + DIG6_HDMI_GENERIC_PACKET_CONTROL0 :DWORD; // 0x5410 + REG_5411_5412 :array[0..1] of DWORD; // 0x5411 + DIG6_HDMI_GC :DWORD; // 0x5413 + DIG6_AFMT_AUDIO_PACKET_CONTROL2 :DWORD; // 0x5414 + DIG6_AFMT_ISRC1_0 :DWORD; // 0x5415 + DIG6_AFMT_ISRC1_1 :DWORD; // 0x5416 + DIG6_AFMT_ISRC1_2 :DWORD; // 0x5417 + DIG6_AFMT_ISRC1_3 :DWORD; // 0x5418 + DIG6_AFMT_ISRC1_4 :DWORD; // 0x5419 + DIG6_AFMT_ISRC2_0 :DWORD; // 0x541A + DIG6_AFMT_ISRC2_1 :DWORD; // 0x541B + DIG6_AFMT_ISRC2_2 :DWORD; // 0x541C + DIG6_AFMT_ISRC2_3 :DWORD; // 0x541D + DIG6_AFMT_AVI_INFO0 :DWORD; // 0x541E + DIG6_AFMT_AVI_INFO1 :DWORD; // 0x541F + DIG6_AFMT_AVI_INFO2 :DWORD; // 0x5420 + DIG6_AFMT_AVI_INFO3 :DWORD; // 0x5421 + DIG6_AFMT_MPEG_INFO0 :DWORD; // 0x5422 + DIG6_AFMT_MPEG_INFO1 :DWORD; // 0x5423 + DIG6_AFMT_GENERIC_HDR :DWORD; // 0x5424 + DIG6_AFMT_GENERIC_0 :DWORD; // 0x5425 + DIG6_AFMT_GENERIC_1 :DWORD; // 0x5426 + DIG6_AFMT_GENERIC_2 :DWORD; // 0x5427 + DIG6_AFMT_GENERIC_3 :DWORD; // 0x5428 + DIG6_AFMT_GENERIC_4 :DWORD; // 0x5429 + DIG6_AFMT_GENERIC_5 :DWORD; // 0x542A + DIG6_AFMT_GENERIC_6 :DWORD; // 0x542B + DIG6_AFMT_GENERIC_7 :DWORD; // 0x542C + DIG6_HDMI_GENERIC_PACKET_CONTROL1 :DWORD; // 0x542D + DIG6_HDMI_ACR_32_0 :DWORD; // 0x542E + DIG6_HDMI_ACR_32_1 :DWORD; // 0x542F + DIG6_HDMI_ACR_44_0 :DWORD; // 0x5430 + DIG6_HDMI_ACR_44_1 :DWORD; // 0x5431 + DIG6_HDMI_ACR_48_0 :DWORD; // 0x5432 + DIG6_HDMI_ACR_48_1 :DWORD; // 0x5433 + DIG6_HDMI_ACR_STATUS_0 :DWORD; // 0x5434 + DIG6_HDMI_ACR_STATUS_1 :DWORD; // 0x5435 + DIG6_AFMT_AUDIO_INFO0 :DWORD; // 0x5436 + DIG6_AFMT_AUDIO_INFO1 :DWORD; // 0x5437 + DIG6_AFMT_60958_0 :DWORD; // 0x5438 + DIG6_AFMT_60958_1 :DWORD; // 0x5439 + DIG6_AFMT_AUDIO_CRC_CONTROL :DWORD; // 0x543A + DIG6_AFMT_RAMP_CONTROL0 :DWORD; // 0x543B + DIG6_AFMT_RAMP_CONTROL1 :DWORD; // 0x543C + DIG6_AFMT_RAMP_CONTROL2 :DWORD; // 0x543D + DIG6_AFMT_RAMP_CONTROL3 :DWORD; // 0x543E + DIG6_AFMT_60958_2 :DWORD; // 0x543F + DIG6_AFMT_AUDIO_CRC_RESULT :DWORD; // 0x5440 + DIG6_AFMT_STATUS :DWORD; // 0x5441 + DIG6_AFMT_AUDIO_PACKET_CONTROL :DWORD; // 0x5442 + DIG6_AFMT_VBI_PACKET_CONTROL :DWORD; // 0x5443 + DIG6_AFMT_INFOFRAME_CONTROL0 :DWORD; // 0x5444 + DIG6_AFMT_AUDIO_SRC_CONTROL :DWORD; // 0x5445 + DIG6_AFMT_AUDIO_DBG_DTO_CNTL :DWORD; // 0x5446 + DIG6_DIG_BE_CNTL :DWORD; // 0x5447 + DIG6_DIG_BE_EN_CNTL :DWORD; // 0x5448 + REG_5449_546A :array[0..33] of DWORD; // 0x5449 + DIG6_TMDS_CNTL :DWORD; // 0x546B + DIG6_TMDS_CONTROL_CHAR :DWORD; // 0x546C + DIG6_TMDS_CONTROL0_FEEDBACK :DWORD; // 0x546D + DIG6_TMDS_STEREOSYNC_CTL_SEL :DWORD; // 0x546E + DIG6_TMDS_SYNC_CHAR_PATTERN_0_1 :DWORD; // 0x546F + DIG6_TMDS_SYNC_CHAR_PATTERN_2_3 :DWORD; // 0x5470 + DIG6_TMDS_DEBUG :DWORD; // 0x5471 + DIG6_TMDS_CTL_BITS :DWORD; // 0x5472 + DIG6_TMDS_DCBALANCER_CONTROL :DWORD; // 0x5473 + REG_5474 :DWORD; // 0x5474 + DIG6_TMDS_CTL0_1_GEN_CNTL :DWORD; // 0x5475 + DIG6_TMDS_CTL2_3_GEN_CNTL :DWORD; // 0x5476 + REG_5477 :DWORD; // 0x5477 + DIG6_LVDS_DATA_CNTL :DWORD; // 0x5478 + DIG6_DIG_LANE_ENABLE :DWORD; // 0x5479 + DIG6_DIG_TEST_DEBUG_INDEX :DWORD; // 0x547A + DIG6_DIG_TEST_DEBUG_DATA :DWORD; // 0x547B + DIG6_DIG_FE_TEST_DEBUG_INDEX :DWORD; // 0x547C + DIG6_DIG_FE_TEST_DEBUG_DATA :DWORD; // 0x547D + REG_547E_549F :array[0..33] of DWORD; // 0x547E + DP6_DP_LINK_CNTL :DWORD; // 0x54A0 + DP6_DP_PIXEL_FORMAT :DWORD; // 0x54A1 + DP6_DP_MSA_COLORIMETRY :DWORD; // 0x54A2 + DP6_DP_CONFIG :DWORD; // 0x54A3 + DP6_DP_VID_STREAM_CNTL :DWORD; // 0x54A4 + DP6_DP_STEER_FIFO :DWORD; // 0x54A5 + DP6_DP_MSA_MISC :DWORD; // 0x54A6 + REG_54A7 :DWORD; // 0x54A7 + DP6_DP_VID_TIMING :DWORD; // 0x54A8 + DP6_DP_VID_N :DWORD; // 0x54A9 + DP6_DP_VID_M :DWORD; // 0x54AA + DP6_DP_LINK_FRAMING_CNTL :DWORD; // 0x54AB + DP6_DP_HBR2_EYE_PATTERN :DWORD; // 0x54AC + DP6_DP_VID_MSA_VBID :DWORD; // 0x54AD + DP6_DP_VID_INTERRUPT_CNTL :DWORD; // 0x54AE + DP6_DP_DPHY_CNTL :DWORD; // 0x54AF + DP6_DP_DPHY_TRAINING_PATTERN_SEL :DWORD; // 0x54B0 + DP6_DP_DPHY_SYM0 :DWORD; // 0x54B1 + DP6_DP_DPHY_SYM1 :DWORD; // 0x54B2 + DP6_DP_DPHY_SYM2 :DWORD; // 0x54B3 + DP6_DP_DPHY_8B10B_CNTL :DWORD; // 0x54B4 + DP6_DP_DPHY_PRBS_CNTL :DWORD; // 0x54B5 + REG_54B6 :DWORD; // 0x54B6 + DP6_DP_DPHY_CRC_EN :DWORD; // 0x54B7 + DP6_DP_DPHY_CRC_CNTL :DWORD; // 0x54B8 + DP6_DP_DPHY_CRC_RESULT :DWORD; // 0x54B9 + DP6_DP_DPHY_CRC_MST_CNTL :DWORD; // 0x54BA + DP6_DP_DPHY_CRC_MST_STATUS :DWORD; // 0x54BB + DP6_DP_DPHY_FAST_TRAINING :DWORD; // 0x54BC + DP6_DP_DPHY_FAST_TRAINING_STATUS :DWORD; // 0x54BD + DP6_DP_MSA_V_TIMING_OVERRIDE1 :DWORD; // 0x54BE + DP6_DP_MSA_V_TIMING_OVERRIDE2 :DWORD; // 0x54BF + REG_54C0_54C2 :array[0..2] of DWORD; // 0x54C0 + DP6_DP_SEC_CNTL :DWORD; // 0x54C3 + DP6_DP_SEC_CNTL1 :DWORD; // 0x54C4 + DP6_DP_SEC_FRAMING1 :DWORD; // 0x54C5 + DP6_DP_SEC_FRAMING2 :DWORD; // 0x54C6 + DP6_DP_SEC_FRAMING3 :DWORD; // 0x54C7 + DP6_DP_SEC_FRAMING4 :DWORD; // 0x54C8 + DP6_DP_SEC_AUD_N :DWORD; // 0x54C9 + DP6_DP_SEC_AUD_N_READBACK :DWORD; // 0x54CA + DP6_DP_SEC_AUD_M :DWORD; // 0x54CB + DP6_DP_SEC_AUD_M_READBACK :DWORD; // 0x54CC + DP6_DP_SEC_TIMESTAMP :DWORD; // 0x54CD + DP6_DP_SEC_PACKET_CNTL :DWORD; // 0x54CE + DP6_DP_MSE_RATE_CNTL :DWORD; // 0x54CF + REG_54D0 :DWORD; // 0x54D0 + DP6_DP_MSE_RATE_UPDATE :DWORD; // 0x54D1 + DP6_DP_MSE_SAT0 :DWORD; // 0x54D2 + DP6_DP_MSE_SAT1 :DWORD; // 0x54D3 + DP6_DP_MSE_SAT2 :DWORD; // 0x54D4 + DP6_DP_MSE_SAT_UPDATE :DWORD; // 0x54D5 + DP6_DP_MSE_LINK_TIMING :DWORD; // 0x54D6 + DP6_DP_MSE_MISC_CNTL :DWORD; // 0x54D7 + DP6_DP_TEST_DEBUG_INDEX :DWORD; // 0x54D8 + DP6_DP_TEST_DEBUG_DATA :DWORD; // 0x54D9 + DP6_DP_FE_TEST_DEBUG_INDEX :DWORD; // 0x54DA + DP6_DP_FE_TEST_DEBUG_DATA :DWORD; // 0x54DB + REG_54DC_599F :array[0..1219] of DWORD; // 0x54DC + DC_PERFMON10_PERFCOUNTER_CNTL :DWORD; // 0x59A0 + DC_PERFMON10_PERFCOUNTER_STATE :DWORD; // 0x59A1 + DC_PERFMON10_PERFMON_CVALUE_INT_MISC :DWORD; // 0x59A2 + DC_PERFMON10_PERFMON_CNTL :DWORD; // 0x59A3 + DC_PERFMON10_PERFMON_CVALUE_LOW :DWORD; // 0x59A4 + DC_PERFMON10_PERFMON_HI :DWORD; // 0x59A5 + DC_PERFMON10_PERFMON_LOW :DWORD; // 0x59A6 + DC_PERFMON10_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x59A7 + DC_PERFMON10_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x59A8 + REG_59A9 :DWORD; // 0x59A9 + DC_PERFMON10_PERFMON_CNTL2 :DWORD; // 0x59AA + REG_59AB_59BF :array[0..20] of DWORD; // 0x59AB + AZF0STREAM8_AZALIA_STREAM_INDEX :DWORD; // 0x59C0 + AZF0STREAM8_AZALIA_STREAM_DATA :DWORD; // 0x59C1 + AZF0STREAM9_AZALIA_STREAM_INDEX :DWORD; // 0x59C2 + AZF0STREAM9_AZALIA_STREAM_DATA :DWORD; // 0x59C3 + AZF0STREAM10_AZALIA_STREAM_INDEX :DWORD; // 0x59C4 + AZF0STREAM10_AZALIA_STREAM_DATA :DWORD; // 0x59C5 + AZF0STREAM11_AZALIA_STREAM_INDEX :DWORD; // 0x59C6 + AZF0STREAM11_AZALIA_STREAM_DATA :DWORD; // 0x59C7 + AZF0STREAM12_AZALIA_STREAM_INDEX :DWORD; // 0x59C8 + AZF0STREAM12_AZALIA_STREAM_DATA :DWORD; // 0x59C9 + AZF0STREAM13_AZALIA_STREAM_INDEX :DWORD; // 0x59CA + AZF0STREAM13_AZALIA_STREAM_DATA :DWORD; // 0x59CB + AZF0STREAM14_AZALIA_STREAM_INDEX :DWORD; // 0x59CC + AZF0STREAM14_AZALIA_STREAM_DATA :DWORD; // 0x59CD + AZF0STREAM15_AZALIA_STREAM_INDEX :DWORD; // 0x59CE + AZF0STREAM15_AZALIA_STREAM_DATA :DWORD; // 0x59CF + REG_59D0_59D3 :array[0..3] of DWORD; // 0x59D0 + AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX :TAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX; // 0x59D4 + AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :TAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA; // 0x59D5 + REG_59D6_59D7 :array[0..1] of DWORD; // 0x59D6 + AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59D8 + AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59D9 + REG_59DA_59DB :array[0..1] of DWORD; // 0x59DA + AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59DC + AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59DD + REG_59DE_59DF :array[0..1] of DWORD; // 0x59DE + AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59E0 + AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59E1 + REG_59E2_59E3 :array[0..1] of DWORD; // 0x59E2 + AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59E4 + AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59E5 + REG_59E6_59E7 :array[0..1] of DWORD; // 0x59E6 + AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59E8 + AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59E9 + REG_59EA_59EB :array[0..1] of DWORD; // 0x59EA + AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59EC + AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59ED + REG_59EE_59EF :array[0..1] of DWORD; // 0x59EE + AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:DWORD; // 0x59F0 + AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :DWORD; // 0x59F1 + REG_59F2_5A83 :array[0..145] of DWORD; // 0x59F2 + DCRX_PHY_MACRO_CNTL_RESERVED0 :TDCRX_PHY_MACRO_CNTL_RESERVED0; // 0x5A84 + DCRX_PHY_MACRO_CNTL_RESERVED1 :TDCRX_PHY_MACRO_CNTL_RESERVED1; // 0x5A85 + DCRX_PHY_MACRO_CNTL_RESERVED2 :TDCRX_PHY_MACRO_CNTL_RESERVED2; // 0x5A86 + DCRX_PHY_MACRO_CNTL_RESERVED3 :TDCRX_PHY_MACRO_CNTL_RESERVED3; // 0x5A87 + DCRX_PHY_MACRO_CNTL_RESERVED4 :TDCRX_PHY_MACRO_CNTL_RESERVED4; // 0x5A88 + DCRX_PHY_MACRO_CNTL_RESERVED5 :TDCRX_PHY_MACRO_CNTL_RESERVED5; // 0x5A89 + DCRX_PHY_MACRO_CNTL_RESERVED6 :TDCRX_PHY_MACRO_CNTL_RESERVED6; // 0x5A8A + DCRX_PHY_MACRO_CNTL_RESERVED7 :TDCRX_PHY_MACRO_CNTL_RESERVED7; // 0x5A8B + DCRX_PHY_MACRO_CNTL_RESERVED8 :TDCRX_PHY_MACRO_CNTL_RESERVED8; // 0x5A8C + DCRX_PHY_MACRO_CNTL_RESERVED9 :TDCRX_PHY_MACRO_CNTL_RESERVED9; // 0x5A8D + DCRX_PHY_MACRO_CNTL_RESERVED10 :TDCRX_PHY_MACRO_CNTL_RESERVED10; // 0x5A8E + DCRX_PHY_MACRO_CNTL_RESERVED11 :TDCRX_PHY_MACRO_CNTL_RESERVED11; // 0x5A8F + DCRX_PHY_MACRO_CNTL_RESERVED12 :TDCRX_PHY_MACRO_CNTL_RESERVED12; // 0x5A90 + DCRX_PHY_MACRO_CNTL_RESERVED13 :TDCRX_PHY_MACRO_CNTL_RESERVED13; // 0x5A91 + DCRX_PHY_MACRO_CNTL_RESERVED14 :TDCRX_PHY_MACRO_CNTL_RESERVED14; // 0x5A92 + DCRX_PHY_MACRO_CNTL_RESERVED15 :TDCRX_PHY_MACRO_CNTL_RESERVED15; // 0x5A93 + DCRX_PHY_MACRO_CNTL_RESERVED16 :TDCRX_PHY_MACRO_CNTL_RESERVED16; // 0x5A94 + DCRX_PHY_MACRO_CNTL_RESERVED17 :TDCRX_PHY_MACRO_CNTL_RESERVED17; // 0x5A95 + DCRX_PHY_MACRO_CNTL_RESERVED18 :TDCRX_PHY_MACRO_CNTL_RESERVED18; // 0x5A96 + DCRX_PHY_MACRO_CNTL_RESERVED19 :TDCRX_PHY_MACRO_CNTL_RESERVED19; // 0x5A97 + DCRX_PHY_MACRO_CNTL_RESERVED20 :TDCRX_PHY_MACRO_CNTL_RESERVED20; // 0x5A98 + DCRX_PHY_MACRO_CNTL_RESERVED21 :TDCRX_PHY_MACRO_CNTL_RESERVED21; // 0x5A99 + DCRX_PHY_MACRO_CNTL_RESERVED22 :TDCRX_PHY_MACRO_CNTL_RESERVED22; // 0x5A9A + DCRX_PHY_MACRO_CNTL_RESERVED23 :TDCRX_PHY_MACRO_CNTL_RESERVED23; // 0x5A9B + DCRX_PHY_MACRO_CNTL_RESERVED24 :TDCRX_PHY_MACRO_CNTL_RESERVED24; // 0x5A9C + DCRX_PHY_MACRO_CNTL_RESERVED25 :TDCRX_PHY_MACRO_CNTL_RESERVED25; // 0x5A9D + DCRX_PHY_MACRO_CNTL_RESERVED26 :TDCRX_PHY_MACRO_CNTL_RESERVED26; // 0x5A9E + DCRX_PHY_MACRO_CNTL_RESERVED27 :TDCRX_PHY_MACRO_CNTL_RESERVED27; // 0x5A9F + DCRX_PHY_MACRO_CNTL_RESERVED28 :TDCRX_PHY_MACRO_CNTL_RESERVED28; // 0x5AA0 + DCRX_PHY_MACRO_CNTL_RESERVED29 :TDCRX_PHY_MACRO_CNTL_RESERVED29; // 0x5AA1 + DCRX_PHY_MACRO_CNTL_RESERVED30 :TDCRX_PHY_MACRO_CNTL_RESERVED30; // 0x5AA2 + DCRX_PHY_MACRO_CNTL_RESERVED31 :TDCRX_PHY_MACRO_CNTL_RESERVED31; // 0x5AA3 + DCRX_PHY_MACRO_CNTL_RESERVED32 :TDCRX_PHY_MACRO_CNTL_RESERVED32; // 0x5AA4 + DCRX_PHY_MACRO_CNTL_RESERVED33 :TDCRX_PHY_MACRO_CNTL_RESERVED33; // 0x5AA5 + DCRX_PHY_MACRO_CNTL_RESERVED34 :TDCRX_PHY_MACRO_CNTL_RESERVED34; // 0x5AA6 + DCRX_PHY_MACRO_CNTL_RESERVED35 :TDCRX_PHY_MACRO_CNTL_RESERVED35; // 0x5AA7 + DCRX_PHY_MACRO_CNTL_RESERVED36 :TDCRX_PHY_MACRO_CNTL_RESERVED36; // 0x5AA8 + DCRX_PHY_MACRO_CNTL_RESERVED37 :TDCRX_PHY_MACRO_CNTL_RESERVED37; // 0x5AA9 + DCRX_PHY_MACRO_CNTL_RESERVED38 :TDCRX_PHY_MACRO_CNTL_RESERVED38; // 0x5AAA + DCRX_PHY_MACRO_CNTL_RESERVED39 :TDCRX_PHY_MACRO_CNTL_RESERVED39; // 0x5AAB + DCRX_PHY_MACRO_CNTL_RESERVED40 :TDCRX_PHY_MACRO_CNTL_RESERVED40; // 0x5AAC + DCRX_PHY_MACRO_CNTL_RESERVED41 :TDCRX_PHY_MACRO_CNTL_RESERVED41; // 0x5AAD + DCRX_PHY_MACRO_CNTL_RESERVED42 :TDCRX_PHY_MACRO_CNTL_RESERVED42; // 0x5AAE + DCRX_PHY_MACRO_CNTL_RESERVED43 :TDCRX_PHY_MACRO_CNTL_RESERVED43; // 0x5AAF + DCRX_PHY_MACRO_CNTL_RESERVED44 :TDCRX_PHY_MACRO_CNTL_RESERVED44; // 0x5AB0 + DCRX_PHY_MACRO_CNTL_RESERVED45 :TDCRX_PHY_MACRO_CNTL_RESERVED45; // 0x5AB1 + DCRX_PHY_MACRO_CNTL_RESERVED46 :TDCRX_PHY_MACRO_CNTL_RESERVED46; // 0x5AB2 + DCRX_PHY_MACRO_CNTL_RESERVED47 :TDCRX_PHY_MACRO_CNTL_RESERVED47; // 0x5AB3 + DCRX_PHY_MACRO_CNTL_RESERVED48 :TDCRX_PHY_MACRO_CNTL_RESERVED48; // 0x5AB4 + DCRX_PHY_MACRO_CNTL_RESERVED49 :TDCRX_PHY_MACRO_CNTL_RESERVED49; // 0x5AB5 + DCRX_PHY_MACRO_CNTL_RESERVED50 :TDCRX_PHY_MACRO_CNTL_RESERVED50; // 0x5AB6 + DCRX_PHY_MACRO_CNTL_RESERVED51 :TDCRX_PHY_MACRO_CNTL_RESERVED51; // 0x5AB7 + DCRX_PHY_MACRO_CNTL_RESERVED52 :TDCRX_PHY_MACRO_CNTL_RESERVED52; // 0x5AB8 + DCRX_PHY_MACRO_CNTL_RESERVED53 :TDCRX_PHY_MACRO_CNTL_RESERVED53; // 0x5AB9 + DCRX_PHY_MACRO_CNTL_RESERVED54 :TDCRX_PHY_MACRO_CNTL_RESERVED54; // 0x5ABA + DCRX_PHY_MACRO_CNTL_RESERVED55 :TDCRX_PHY_MACRO_CNTL_RESERVED55; // 0x5ABB + DCRX_PHY_MACRO_CNTL_RESERVED56 :TDCRX_PHY_MACRO_CNTL_RESERVED56; // 0x5ABC + DCRX_PHY_MACRO_CNTL_RESERVED57 :TDCRX_PHY_MACRO_CNTL_RESERVED57; // 0x5ABD + DCRX_PHY_MACRO_CNTL_RESERVED58 :TDCRX_PHY_MACRO_CNTL_RESERVED58; // 0x5ABE + DCRX_PHY_MACRO_CNTL_RESERVED59 :TDCRX_PHY_MACRO_CNTL_RESERVED59; // 0x5ABF + DCRX_PHY_MACRO_CNTL_RESERVED60 :TDCRX_PHY_MACRO_CNTL_RESERVED60; // 0x5AC0 + DCRX_PHY_MACRO_CNTL_RESERVED61 :TDCRX_PHY_MACRO_CNTL_RESERVED61; // 0x5AC1 + DCRX_PHY_MACRO_CNTL_RESERVED62 :TDCRX_PHY_MACRO_CNTL_RESERVED62; // 0x5AC2 + DCRX_PHY_MACRO_CNTL_RESERVED63 :TDCRX_PHY_MACRO_CNTL_RESERVED63; // 0x5AC3 + DCRX_PHY_MACRO_CNTL_RESERVED64 :TDCRX_PHY_MACRO_CNTL_RESERVED64; // 0x5AC4 + DCRX_PHY_MACRO_CNTL_RESERVED65 :TDCRX_PHY_MACRO_CNTL_RESERVED65; // 0x5AC5 + DCRX_PHY_MACRO_CNTL_RESERVED66 :TDCRX_PHY_MACRO_CNTL_RESERVED66; // 0x5AC6 + DCRX_PHY_MACRO_CNTL_RESERVED67 :TDCRX_PHY_MACRO_CNTL_RESERVED67; // 0x5AC7 + DCRX_PHY_MACRO_CNTL_RESERVED68 :TDCRX_PHY_MACRO_CNTL_RESERVED68; // 0x5AC8 + DCRX_PHY_MACRO_CNTL_RESERVED69 :TDCRX_PHY_MACRO_CNTL_RESERVED69; // 0x5AC9 + DCRX_PHY_MACRO_CNTL_RESERVED70 :TDCRX_PHY_MACRO_CNTL_RESERVED70; // 0x5ACA + DCRX_PHY_MACRO_CNTL_RESERVED71 :TDCRX_PHY_MACRO_CNTL_RESERVED71; // 0x5ACB + DCRX_PHY_MACRO_CNTL_RESERVED72 :TDCRX_PHY_MACRO_CNTL_RESERVED72; // 0x5ACC + DCRX_PHY_MACRO_CNTL_RESERVED73 :TDCRX_PHY_MACRO_CNTL_RESERVED73; // 0x5ACD + DCRX_PHY_MACRO_CNTL_RESERVED74 :TDCRX_PHY_MACRO_CNTL_RESERVED74; // 0x5ACE + DCRX_PHY_MACRO_CNTL_RESERVED75 :TDCRX_PHY_MACRO_CNTL_RESERVED75; // 0x5ACF + DCRX_PHY_MACRO_CNTL_RESERVED76 :TDCRX_PHY_MACRO_CNTL_RESERVED76; // 0x5AD0 + DCRX_PHY_MACRO_CNTL_RESERVED77 :TDCRX_PHY_MACRO_CNTL_RESERVED77; // 0x5AD1 + DCRX_PHY_MACRO_CNTL_RESERVED78 :TDCRX_PHY_MACRO_CNTL_RESERVED78; // 0x5AD2 + DCRX_PHY_MACRO_CNTL_RESERVED79 :TDCRX_PHY_MACRO_CNTL_RESERVED79; // 0x5AD3 + DCRX_PHY_MACRO_CNTL_RESERVED80 :TDCRX_PHY_MACRO_CNTL_RESERVED80; // 0x5AD4 + DCRX_PHY_MACRO_CNTL_RESERVED81 :TDCRX_PHY_MACRO_CNTL_RESERVED81; // 0x5AD5 + DCRX_PHY_MACRO_CNTL_RESERVED82 :TDCRX_PHY_MACRO_CNTL_RESERVED82; // 0x5AD6 + DCRX_PHY_MACRO_CNTL_RESERVED83 :TDCRX_PHY_MACRO_CNTL_RESERVED83; // 0x5AD7 + DCRX_PHY_MACRO_CNTL_RESERVED84 :TDCRX_PHY_MACRO_CNTL_RESERVED84; // 0x5AD8 + DCRX_PHY_MACRO_CNTL_RESERVED85 :TDCRX_PHY_MACRO_CNTL_RESERVED85; // 0x5AD9 + DCRX_PHY_MACRO_CNTL_RESERVED86 :TDCRX_PHY_MACRO_CNTL_RESERVED86; // 0x5ADA + DCRX_PHY_MACRO_CNTL_RESERVED87 :TDCRX_PHY_MACRO_CNTL_RESERVED87; // 0x5ADB + DCRX_PHY_MACRO_CNTL_RESERVED88 :TDCRX_PHY_MACRO_CNTL_RESERVED88; // 0x5ADC + DCRX_PHY_MACRO_CNTL_RESERVED89 :TDCRX_PHY_MACRO_CNTL_RESERVED89; // 0x5ADD + DCRX_PHY_MACRO_CNTL_RESERVED90 :TDCRX_PHY_MACRO_CNTL_RESERVED90; // 0x5ADE + DCRX_PHY_MACRO_CNTL_RESERVED91 :TDCRX_PHY_MACRO_CNTL_RESERVED91; // 0x5ADF + DCRX_PHY_MACRO_CNTL_RESERVED92 :TDCRX_PHY_MACRO_CNTL_RESERVED92; // 0x5AE0 + DCRX_PHY_MACRO_CNTL_RESERVED93 :TDCRX_PHY_MACRO_CNTL_RESERVED93; // 0x5AE1 + DCRX_PHY_MACRO_CNTL_RESERVED94 :TDCRX_PHY_MACRO_CNTL_RESERVED94; // 0x5AE2 + DCRX_PHY_MACRO_CNTL_RESERVED95 :TDCRX_PHY_MACRO_CNTL_RESERVED95; // 0x5AE3 + DCRX_PHY_MACRO_CNTL_RESERVED96 :TDCRX_PHY_MACRO_CNTL_RESERVED96; // 0x5AE4 + DCRX_PHY_MACRO_CNTL_RESERVED97 :TDCRX_PHY_MACRO_CNTL_RESERVED97; // 0x5AE5 + DCRX_PHY_MACRO_CNTL_RESERVED98 :TDCRX_PHY_MACRO_CNTL_RESERVED98; // 0x5AE6 + DCRX_PHY_MACRO_CNTL_RESERVED99 :TDCRX_PHY_MACRO_CNTL_RESERVED99; // 0x5AE7 + DCRX_PHY_MACRO_CNTL_RESERVED100 :TDCRX_PHY_MACRO_CNTL_RESERVED100; // 0x5AE8 + DCRX_PHY_MACRO_CNTL_RESERVED101 :TDCRX_PHY_MACRO_CNTL_RESERVED101; // 0x5AE9 + DCRX_PHY_MACRO_CNTL_RESERVED102 :TDCRX_PHY_MACRO_CNTL_RESERVED102; // 0x5AEA + DCRX_PHY_MACRO_CNTL_RESERVED103 :TDCRX_PHY_MACRO_CNTL_RESERVED103; // 0x5AEB + DCRX_PHY_MACRO_CNTL_RESERVED104 :TDCRX_PHY_MACRO_CNTL_RESERVED104; // 0x5AEC + DCRX_PHY_MACRO_CNTL_RESERVED105 :TDCRX_PHY_MACRO_CNTL_RESERVED105; // 0x5AED + DCRX_PHY_MACRO_CNTL_RESERVED106 :TDCRX_PHY_MACRO_CNTL_RESERVED106; // 0x5AEE + DCRX_PHY_MACRO_CNTL_RESERVED107 :TDCRX_PHY_MACRO_CNTL_RESERVED107; // 0x5AEF + DCRX_PHY_MACRO_CNTL_RESERVED108 :TDCRX_PHY_MACRO_CNTL_RESERVED108; // 0x5AF0 + DCRX_PHY_MACRO_CNTL_RESERVED109 :TDCRX_PHY_MACRO_CNTL_RESERVED109; // 0x5AF1 + DCRX_PHY_MACRO_CNTL_RESERVED110 :TDCRX_PHY_MACRO_CNTL_RESERVED110; // 0x5AF2 + DCRX_PHY_MACRO_CNTL_RESERVED111 :TDCRX_PHY_MACRO_CNTL_RESERVED111; // 0x5AF3 + DCRX_PHY_MACRO_CNTL_RESERVED112 :TDCRX_PHY_MACRO_CNTL_RESERVED112; // 0x5AF4 + DCRX_PHY_MACRO_CNTL_RESERVED113 :TDCRX_PHY_MACRO_CNTL_RESERVED113; // 0x5AF5 + DCRX_PHY_MACRO_CNTL_RESERVED114 :TDCRX_PHY_MACRO_CNTL_RESERVED114; // 0x5AF6 + DCRX_PHY_MACRO_CNTL_RESERVED115 :TDCRX_PHY_MACRO_CNTL_RESERVED115; // 0x5AF7 + DCRX_PHY_MACRO_CNTL_RESERVED116 :TDCRX_PHY_MACRO_CNTL_RESERVED116; // 0x5AF8 + DCRX_PHY_MACRO_CNTL_RESERVED117 :TDCRX_PHY_MACRO_CNTL_RESERVED117; // 0x5AF9 + DCRX_PHY_MACRO_CNTL_RESERVED118 :TDCRX_PHY_MACRO_CNTL_RESERVED118; // 0x5AFA + DCRX_PHY_MACRO_CNTL_RESERVED119 :TDCRX_PHY_MACRO_CNTL_RESERVED119; // 0x5AFB + DCRX_PHY_MACRO_CNTL_RESERVED120 :TDCRX_PHY_MACRO_CNTL_RESERVED120; // 0x5AFC + DCRX_PHY_MACRO_CNTL_RESERVED121 :TDCRX_PHY_MACRO_CNTL_RESERVED121; // 0x5AFD + DCRX_PHY_MACRO_CNTL_RESERVED122 :TDCRX_PHY_MACRO_CNTL_RESERVED122; // 0x5AFE + DCRX_PHY_MACRO_CNTL_RESERVED123 :TDCRX_PHY_MACRO_CNTL_RESERVED123; // 0x5AFF + DCRX_PHY_MACRO_CNTL_RESERVED124 :TDCRX_PHY_MACRO_CNTL_RESERVED124; // 0x5B00 + DCRX_PHY_MACRO_CNTL_RESERVED125 :TDCRX_PHY_MACRO_CNTL_RESERVED125; // 0x5B01 + DCRX_PHY_MACRO_CNTL_RESERVED126 :TDCRX_PHY_MACRO_CNTL_RESERVED126; // 0x5B02 + DCRX_PHY_MACRO_CNTL_RESERVED127 :TDCRX_PHY_MACRO_CNTL_RESERVED127; // 0x5B03 + DCRX_PHY_MACRO_CNTL_RESERVED128 :TDCRX_PHY_MACRO_CNTL_RESERVED128; // 0x5B04 + DCRX_PHY_MACRO_CNTL_RESERVED129 :TDCRX_PHY_MACRO_CNTL_RESERVED129; // 0x5B05 + DCRX_PHY_MACRO_CNTL_RESERVED130 :TDCRX_PHY_MACRO_CNTL_RESERVED130; // 0x5B06 + DCRX_PHY_MACRO_CNTL_RESERVED131 :TDCRX_PHY_MACRO_CNTL_RESERVED131; // 0x5B07 + DCRX_PHY_MACRO_CNTL_RESERVED132 :TDCRX_PHY_MACRO_CNTL_RESERVED132; // 0x5B08 + DCRX_PHY_MACRO_CNTL_RESERVED133 :TDCRX_PHY_MACRO_CNTL_RESERVED133; // 0x5B09 + DCRX_PHY_MACRO_CNTL_RESERVED134 :TDCRX_PHY_MACRO_CNTL_RESERVED134; // 0x5B0A + DCRX_PHY_MACRO_CNTL_RESERVED135 :TDCRX_PHY_MACRO_CNTL_RESERVED135; // 0x5B0B + DCRX_PHY_MACRO_CNTL_RESERVED136 :TDCRX_PHY_MACRO_CNTL_RESERVED136; // 0x5B0C + DCRX_PHY_MACRO_CNTL_RESERVED137 :TDCRX_PHY_MACRO_CNTL_RESERVED137; // 0x5B0D + DCRX_PHY_MACRO_CNTL_RESERVED138 :TDCRX_PHY_MACRO_CNTL_RESERVED138; // 0x5B0E + DCRX_PHY_MACRO_CNTL_RESERVED139 :TDCRX_PHY_MACRO_CNTL_RESERVED139; // 0x5B0F + DCRX_PHY_MACRO_CNTL_RESERVED140 :TDCRX_PHY_MACRO_CNTL_RESERVED140; // 0x5B10 + DCRX_PHY_MACRO_CNTL_RESERVED141 :TDCRX_PHY_MACRO_CNTL_RESERVED141; // 0x5B11 + DCRX_PHY_MACRO_CNTL_RESERVED142 :TDCRX_PHY_MACRO_CNTL_RESERVED142; // 0x5B12 + DCRX_PHY_MACRO_CNTL_RESERVED143 :TDCRX_PHY_MACRO_CNTL_RESERVED143; // 0x5B13 + DCRX_PHY_MACRO_CNTL_RESERVED144 :TDCRX_PHY_MACRO_CNTL_RESERVED144; // 0x5B14 + DCRX_PHY_MACRO_CNTL_RESERVED145 :TDCRX_PHY_MACRO_CNTL_RESERVED145; // 0x5B15 + DCRX_PHY_MACRO_CNTL_RESERVED146 :TDCRX_PHY_MACRO_CNTL_RESERVED146; // 0x5B16 + DCRX_PHY_MACRO_CNTL_RESERVED147 :TDCRX_PHY_MACRO_CNTL_RESERVED147; // 0x5B17 + DCRX_PHY_MACRO_CNTL_RESERVED148 :TDCRX_PHY_MACRO_CNTL_RESERVED148; // 0x5B18 + DCRX_PHY_MACRO_CNTL_RESERVED149 :TDCRX_PHY_MACRO_CNTL_RESERVED149; // 0x5B19 + DCRX_PHY_MACRO_CNTL_RESERVED150 :TDCRX_PHY_MACRO_CNTL_RESERVED150; // 0x5B1A + DCRX_PHY_MACRO_CNTL_RESERVED151 :TDCRX_PHY_MACRO_CNTL_RESERVED151; // 0x5B1B + DCRX_PHY_MACRO_CNTL_RESERVED152 :TDCRX_PHY_MACRO_CNTL_RESERVED152; // 0x5B1C + DCRX_PHY_MACRO_CNTL_RESERVED153 :TDCRX_PHY_MACRO_CNTL_RESERVED153; // 0x5B1D + DCRX_PHY_MACRO_CNTL_RESERVED154 :TDCRX_PHY_MACRO_CNTL_RESERVED154; // 0x5B1E + DCRX_PHY_MACRO_CNTL_RESERVED155 :TDCRX_PHY_MACRO_CNTL_RESERVED155; // 0x5B1F + DCRX_PHY_MACRO_CNTL_RESERVED156 :TDCRX_PHY_MACRO_CNTL_RESERVED156; // 0x5B20 + DCRX_PHY_MACRO_CNTL_RESERVED157 :TDCRX_PHY_MACRO_CNTL_RESERVED157; // 0x5B21 + DCRX_PHY_MACRO_CNTL_RESERVED158 :TDCRX_PHY_MACRO_CNTL_RESERVED158; // 0x5B22 + DCRX_PHY_MACRO_CNTL_RESERVED159 :TDCRX_PHY_MACRO_CNTL_RESERVED159; // 0x5B23 + DCRX_PHY_MACRO_CNTL_RESERVED160 :TDCRX_PHY_MACRO_CNTL_RESERVED160; // 0x5B24 + DCRX_PHY_MACRO_CNTL_RESERVED161 :TDCRX_PHY_MACRO_CNTL_RESERVED161; // 0x5B25 + DCRX_PHY_MACRO_CNTL_RESERVED162 :TDCRX_PHY_MACRO_CNTL_RESERVED162; // 0x5B26 + DCRX_PHY_MACRO_CNTL_RESERVED163 :TDCRX_PHY_MACRO_CNTL_RESERVED163; // 0x5B27 + DCRX_PHY_MACRO_CNTL_RESERVED164 :TDCRX_PHY_MACRO_CNTL_RESERVED164; // 0x5B28 + DCRX_PHY_MACRO_CNTL_RESERVED165 :TDCRX_PHY_MACRO_CNTL_RESERVED165; // 0x5B29 + DCRX_PHY_MACRO_CNTL_RESERVED166 :TDCRX_PHY_MACRO_CNTL_RESERVED166; // 0x5B2A + DCRX_PHY_MACRO_CNTL_RESERVED167 :TDCRX_PHY_MACRO_CNTL_RESERVED167; // 0x5B2B + DCRX_PHY_MACRO_CNTL_RESERVED168 :TDCRX_PHY_MACRO_CNTL_RESERVED168; // 0x5B2C + DCRX_PHY_MACRO_CNTL_RESERVED169 :TDCRX_PHY_MACRO_CNTL_RESERVED169; // 0x5B2D + DCRX_PHY_MACRO_CNTL_RESERVED170 :TDCRX_PHY_MACRO_CNTL_RESERVED170; // 0x5B2E + DCRX_PHY_MACRO_CNTL_RESERVED171 :TDCRX_PHY_MACRO_CNTL_RESERVED171; // 0x5B2F + DCRX_PHY_MACRO_CNTL_RESERVED172 :TDCRX_PHY_MACRO_CNTL_RESERVED172; // 0x5B30 + DCRX_PHY_MACRO_CNTL_RESERVED173 :TDCRX_PHY_MACRO_CNTL_RESERVED173; // 0x5B31 + DCRX_PHY_MACRO_CNTL_RESERVED174 :TDCRX_PHY_MACRO_CNTL_RESERVED174; // 0x5B32 + DCRX_PHY_MACRO_CNTL_RESERVED175 :TDCRX_PHY_MACRO_CNTL_RESERVED175; // 0x5B33 + DCRX_PHY_MACRO_CNTL_RESERVED176 :TDCRX_PHY_MACRO_CNTL_RESERVED176; // 0x5B34 + DCRX_PHY_MACRO_CNTL_RESERVED177 :TDCRX_PHY_MACRO_CNTL_RESERVED177; // 0x5B35 + DCRX_PHY_MACRO_CNTL_RESERVED178 :TDCRX_PHY_MACRO_CNTL_RESERVED178; // 0x5B36 + DCRX_PHY_MACRO_CNTL_RESERVED179 :TDCRX_PHY_MACRO_CNTL_RESERVED179; // 0x5B37 + DCRX_PHY_MACRO_CNTL_RESERVED180 :TDCRX_PHY_MACRO_CNTL_RESERVED180; // 0x5B38 + DCRX_PHY_MACRO_CNTL_RESERVED181 :TDCRX_PHY_MACRO_CNTL_RESERVED181; // 0x5B39 + DCRX_PHY_MACRO_CNTL_RESERVED182 :TDCRX_PHY_MACRO_CNTL_RESERVED182; // 0x5B3A + DCRX_PHY_MACRO_CNTL_RESERVED183 :TDCRX_PHY_MACRO_CNTL_RESERVED183; // 0x5B3B + DCRX_PHY_MACRO_CNTL_RESERVED184 :TDCRX_PHY_MACRO_CNTL_RESERVED184; // 0x5B3C + DCRX_PHY_MACRO_CNTL_RESERVED185 :TDCRX_PHY_MACRO_CNTL_RESERVED185; // 0x5B3D + DCRX_PHY_MACRO_CNTL_RESERVED186 :TDCRX_PHY_MACRO_CNTL_RESERVED186; // 0x5B3E + DCRX_PHY_MACRO_CNTL_RESERVED187 :TDCRX_PHY_MACRO_CNTL_RESERVED187; // 0x5B3F + DCRX_PHY_MACRO_CNTL_RESERVED188 :TDCRX_PHY_MACRO_CNTL_RESERVED188; // 0x5B40 + DCRX_PHY_MACRO_CNTL_RESERVED189 :TDCRX_PHY_MACRO_CNTL_RESERVED189; // 0x5B41 + DCRX_PHY_MACRO_CNTL_RESERVED190 :TDCRX_PHY_MACRO_CNTL_RESERVED190; // 0x5B42 + DCRX_PHY_MACRO_CNTL_RESERVED191 :TDCRX_PHY_MACRO_CNTL_RESERVED191; // 0x5B43 + DCRX_PHY_MACRO_CNTL_RESERVED192 :TDCRX_PHY_MACRO_CNTL_RESERVED192; // 0x5B44 + DCRX_PHY_MACRO_CNTL_RESERVED193 :TDCRX_PHY_MACRO_CNTL_RESERVED193; // 0x5B45 + DCRX_PHY_MACRO_CNTL_RESERVED194 :TDCRX_PHY_MACRO_CNTL_RESERVED194; // 0x5B46 + DCRX_PHY_MACRO_CNTL_RESERVED195 :TDCRX_PHY_MACRO_CNTL_RESERVED195; // 0x5B47 + DCRX_PHY_MACRO_CNTL_RESERVED196 :TDCRX_PHY_MACRO_CNTL_RESERVED196; // 0x5B48 + DCRX_PHY_MACRO_CNTL_RESERVED197 :TDCRX_PHY_MACRO_CNTL_RESERVED197; // 0x5B49 + DCRX_PHY_MACRO_CNTL_RESERVED198 :TDCRX_PHY_MACRO_CNTL_RESERVED198; // 0x5B4A + DCRX_PHY_MACRO_CNTL_RESERVED199 :TDCRX_PHY_MACRO_CNTL_RESERVED199; // 0x5B4B + DCRX_PHY_MACRO_CNTL_RESERVED200 :TDCRX_PHY_MACRO_CNTL_RESERVED200; // 0x5B4C + DCRX_PHY_MACRO_CNTL_RESERVED201 :TDCRX_PHY_MACRO_CNTL_RESERVED201; // 0x5B4D + DCRX_PHY_MACRO_CNTL_RESERVED202 :TDCRX_PHY_MACRO_CNTL_RESERVED202; // 0x5B4E + DCRX_PHY_MACRO_CNTL_RESERVED203 :TDCRX_PHY_MACRO_CNTL_RESERVED203; // 0x5B4F + DCRX_PHY_MACRO_CNTL_RESERVED204 :TDCRX_PHY_MACRO_CNTL_RESERVED204; // 0x5B50 + DCRX_PHY_MACRO_CNTL_RESERVED205 :TDCRX_PHY_MACRO_CNTL_RESERVED205; // 0x5B51 + DCRX_PHY_MACRO_CNTL_RESERVED206 :TDCRX_PHY_MACRO_CNTL_RESERVED206; // 0x5B52 + DCRX_PHY_MACRO_CNTL_RESERVED207 :TDCRX_PHY_MACRO_CNTL_RESERVED207; // 0x5B53 + DCRX_PHY_MACRO_CNTL_RESERVED208 :TDCRX_PHY_MACRO_CNTL_RESERVED208; // 0x5B54 + DCRX_PHY_MACRO_CNTL_RESERVED209 :TDCRX_PHY_MACRO_CNTL_RESERVED209; // 0x5B55 + DCRX_PHY_MACRO_CNTL_RESERVED210 :TDCRX_PHY_MACRO_CNTL_RESERVED210; // 0x5B56 + DCRX_PHY_MACRO_CNTL_RESERVED211 :TDCRX_PHY_MACRO_CNTL_RESERVED211; // 0x5B57 + DCRX_PHY_MACRO_CNTL_RESERVED212 :TDCRX_PHY_MACRO_CNTL_RESERVED212; // 0x5B58 + DCRX_PHY_MACRO_CNTL_RESERVED213 :TDCRX_PHY_MACRO_CNTL_RESERVED213; // 0x5B59 + DCRX_PHY_MACRO_CNTL_RESERVED214 :TDCRX_PHY_MACRO_CNTL_RESERVED214; // 0x5B5A + DCRX_PHY_MACRO_CNTL_RESERVED215 :TDCRX_PHY_MACRO_CNTL_RESERVED215; // 0x5B5B + DCRX_PHY_MACRO_CNTL_RESERVED216 :TDCRX_PHY_MACRO_CNTL_RESERVED216; // 0x5B5C + DCRX_PHY_MACRO_CNTL_RESERVED217 :TDCRX_PHY_MACRO_CNTL_RESERVED217; // 0x5B5D + DCRX_PHY_MACRO_CNTL_RESERVED218 :TDCRX_PHY_MACRO_CNTL_RESERVED218; // 0x5B5E + DCRX_PHY_MACRO_CNTL_RESERVED219 :TDCRX_PHY_MACRO_CNTL_RESERVED219; // 0x5B5F + DCRX_PHY_MACRO_CNTL_RESERVED220 :TDCRX_PHY_MACRO_CNTL_RESERVED220; // 0x5B60 + DCRX_PHY_MACRO_CNTL_RESERVED221 :TDCRX_PHY_MACRO_CNTL_RESERVED221; // 0x5B61 + DCRX_PHY_MACRO_CNTL_RESERVED222 :TDCRX_PHY_MACRO_CNTL_RESERVED222; // 0x5B62 + DCRX_PHY_MACRO_CNTL_RESERVED223 :TDCRX_PHY_MACRO_CNTL_RESERVED223; // 0x5B63 + DCRX_PHY_MACRO_CNTL_RESERVED224 :TDCRX_PHY_MACRO_CNTL_RESERVED224; // 0x5B64 + DCRX_PHY_MACRO_CNTL_RESERVED225 :TDCRX_PHY_MACRO_CNTL_RESERVED225; // 0x5B65 + DCRX_PHY_MACRO_CNTL_RESERVED226 :TDCRX_PHY_MACRO_CNTL_RESERVED226; // 0x5B66 + DCRX_PHY_MACRO_CNTL_RESERVED227 :TDCRX_PHY_MACRO_CNTL_RESERVED227; // 0x5B67 + DCRX_PHY_MACRO_CNTL_RESERVED228 :TDCRX_PHY_MACRO_CNTL_RESERVED228; // 0x5B68 + DCRX_PHY_MACRO_CNTL_RESERVED229 :TDCRX_PHY_MACRO_CNTL_RESERVED229; // 0x5B69 + DCRX_PHY_MACRO_CNTL_RESERVED230 :TDCRX_PHY_MACRO_CNTL_RESERVED230; // 0x5B6A + DCRX_PHY_MACRO_CNTL_RESERVED231 :TDCRX_PHY_MACRO_CNTL_RESERVED231; // 0x5B6B + DCRX_PHY_MACRO_CNTL_RESERVED232 :TDCRX_PHY_MACRO_CNTL_RESERVED232; // 0x5B6C + DCRX_PHY_MACRO_CNTL_RESERVED233 :TDCRX_PHY_MACRO_CNTL_RESERVED233; // 0x5B6D + DCRX_PHY_MACRO_CNTL_RESERVED234 :TDCRX_PHY_MACRO_CNTL_RESERVED234; // 0x5B6E + DCRX_PHY_MACRO_CNTL_RESERVED235 :TDCRX_PHY_MACRO_CNTL_RESERVED235; // 0x5B6F + DCRX_PHY_MACRO_CNTL_RESERVED236 :TDCRX_PHY_MACRO_CNTL_RESERVED236; // 0x5B70 + DCRX_PHY_MACRO_CNTL_RESERVED237 :TDCRX_PHY_MACRO_CNTL_RESERVED237; // 0x5B71 + DCRX_PHY_MACRO_CNTL_RESERVED238 :TDCRX_PHY_MACRO_CNTL_RESERVED238; // 0x5B72 + DCRX_PHY_MACRO_CNTL_RESERVED239 :TDCRX_PHY_MACRO_CNTL_RESERVED239; // 0x5B73 + DCRX_PHY_MACRO_CNTL_RESERVED240 :TDCRX_PHY_MACRO_CNTL_RESERVED240; // 0x5B74 + DCRX_PHY_MACRO_CNTL_RESERVED241 :TDCRX_PHY_MACRO_CNTL_RESERVED241; // 0x5B75 + DCRX_PHY_MACRO_CNTL_RESERVED242 :TDCRX_PHY_MACRO_CNTL_RESERVED242; // 0x5B76 + DCRX_PHY_MACRO_CNTL_RESERVED243 :TDCRX_PHY_MACRO_CNTL_RESERVED243; // 0x5B77 + DCRX_PHY_MACRO_CNTL_RESERVED244 :TDCRX_PHY_MACRO_CNTL_RESERVED244; // 0x5B78 + DCRX_PHY_MACRO_CNTL_RESERVED245 :TDCRX_PHY_MACRO_CNTL_RESERVED245; // 0x5B79 + DCRX_PHY_MACRO_CNTL_RESERVED246 :TDCRX_PHY_MACRO_CNTL_RESERVED246; // 0x5B7A + DCRX_PHY_MACRO_CNTL_RESERVED247 :TDCRX_PHY_MACRO_CNTL_RESERVED247; // 0x5B7B + DCRX_PHY_MACRO_CNTL_RESERVED248 :TDCRX_PHY_MACRO_CNTL_RESERVED248; // 0x5B7C + DCRX_PHY_MACRO_CNTL_RESERVED249 :TDCRX_PHY_MACRO_CNTL_RESERVED249; // 0x5B7D + DCRX_PHY_MACRO_CNTL_RESERVED250 :TDCRX_PHY_MACRO_CNTL_RESERVED250; // 0x5B7E + DCRX_PHY_MACRO_CNTL_RESERVED251 :TDCRX_PHY_MACRO_CNTL_RESERVED251; // 0x5B7F + DCRX_PHY_MACRO_CNTL_RESERVED252 :TDCRX_PHY_MACRO_CNTL_RESERVED252; // 0x5B80 + DCRX_PHY_MACRO_CNTL_RESERVED253 :TDCRX_PHY_MACRO_CNTL_RESERVED253; // 0x5B81 + DCRX_PHY_MACRO_CNTL_RESERVED254 :TDCRX_PHY_MACRO_CNTL_RESERVED254; // 0x5B82 + DCRX_PHY_MACRO_CNTL_RESERVED255 :TDCRX_PHY_MACRO_CNTL_RESERVED255; // 0x5B83 + DCRX_PHY_MACRO_CNTL_RESERVED256 :TDCRX_PHY_MACRO_CNTL_RESERVED256; // 0x5B84 + DCRX_PHY_MACRO_CNTL_RESERVED257 :TDCRX_PHY_MACRO_CNTL_RESERVED257; // 0x5B85 + DCRX_PHY_MACRO_CNTL_RESERVED258 :TDCRX_PHY_MACRO_CNTL_RESERVED258; // 0x5B86 + DCRX_PHY_MACRO_CNTL_RESERVED259 :TDCRX_PHY_MACRO_CNTL_RESERVED259; // 0x5B87 + DCRX_PHY_MACRO_CNTL_RESERVED260 :TDCRX_PHY_MACRO_CNTL_RESERVED260; // 0x5B88 + DCRX_PHY_MACRO_CNTL_RESERVED261 :TDCRX_PHY_MACRO_CNTL_RESERVED261; // 0x5B89 + DCRX_PHY_MACRO_CNTL_RESERVED262 :TDCRX_PHY_MACRO_CNTL_RESERVED262; // 0x5B8A + DCRX_PHY_MACRO_CNTL_RESERVED263 :TDCRX_PHY_MACRO_CNTL_RESERVED263; // 0x5B8B + DCRX_PHY_MACRO_CNTL_RESERVED264 :TDCRX_PHY_MACRO_CNTL_RESERVED264; // 0x5B8C + DCRX_PHY_MACRO_CNTL_RESERVED265 :TDCRX_PHY_MACRO_CNTL_RESERVED265; // 0x5B8D + DCRX_PHY_MACRO_CNTL_RESERVED266 :TDCRX_PHY_MACRO_CNTL_RESERVED266; // 0x5B8E + DCRX_PHY_MACRO_CNTL_RESERVED267 :TDCRX_PHY_MACRO_CNTL_RESERVED267; // 0x5B8F + DCRX_PHY_MACRO_CNTL_RESERVED268 :TDCRX_PHY_MACRO_CNTL_RESERVED268; // 0x5B90 + DCRX_PHY_MACRO_CNTL_RESERVED269 :TDCRX_PHY_MACRO_CNTL_RESERVED269; // 0x5B91 + DCRX_PHY_MACRO_CNTL_RESERVED270 :TDCRX_PHY_MACRO_CNTL_RESERVED270; // 0x5B92 + DCRX_PHY_MACRO_CNTL_RESERVED271 :TDCRX_PHY_MACRO_CNTL_RESERVED271; // 0x5B93 + DCRX_PHY_MACRO_CNTL_RESERVED272 :TDCRX_PHY_MACRO_CNTL_RESERVED272; // 0x5B94 + DCRX_PHY_MACRO_CNTL_RESERVED273 :TDCRX_PHY_MACRO_CNTL_RESERVED273; // 0x5B95 + DCRX_PHY_MACRO_CNTL_RESERVED274 :TDCRX_PHY_MACRO_CNTL_RESERVED274; // 0x5B96 + DCRX_PHY_MACRO_CNTL_RESERVED275 :TDCRX_PHY_MACRO_CNTL_RESERVED275; // 0x5B97 + DCRX_PHY_MACRO_CNTL_RESERVED276 :TDCRX_PHY_MACRO_CNTL_RESERVED276; // 0x5B98 + DCRX_PHY_MACRO_CNTL_RESERVED277 :TDCRX_PHY_MACRO_CNTL_RESERVED277; // 0x5B99 + DCRX_PHY_MACRO_CNTL_RESERVED278 :TDCRX_PHY_MACRO_CNTL_RESERVED278; // 0x5B9A + DCRX_PHY_MACRO_CNTL_RESERVED279 :TDCRX_PHY_MACRO_CNTL_RESERVED279; // 0x5B9B + DCRX_PHY_MACRO_CNTL_RESERVED280 :TDCRX_PHY_MACRO_CNTL_RESERVED280; // 0x5B9C + DCRX_PHY_MACRO_CNTL_RESERVED281 :TDCRX_PHY_MACRO_CNTL_RESERVED281; // 0x5B9D + DCRX_PHY_MACRO_CNTL_RESERVED282 :TDCRX_PHY_MACRO_CNTL_RESERVED282; // 0x5B9E + DCRX_PHY_MACRO_CNTL_RESERVED283 :TDCRX_PHY_MACRO_CNTL_RESERVED283; // 0x5B9F + DCRX_PHY_MACRO_CNTL_RESERVED284 :TDCRX_PHY_MACRO_CNTL_RESERVED284; // 0x5BA0 + DCRX_PHY_MACRO_CNTL_RESERVED285 :TDCRX_PHY_MACRO_CNTL_RESERVED285; // 0x5BA1 + DCRX_PHY_MACRO_CNTL_RESERVED286 :TDCRX_PHY_MACRO_CNTL_RESERVED286; // 0x5BA2 + DCRX_PHY_MACRO_CNTL_RESERVED287 :TDCRX_PHY_MACRO_CNTL_RESERVED287; // 0x5BA3 + DCRX_PHY_MACRO_CNTL_RESERVED288 :TDCRX_PHY_MACRO_CNTL_RESERVED288; // 0x5BA4 + DCRX_PHY_MACRO_CNTL_RESERVED289 :TDCRX_PHY_MACRO_CNTL_RESERVED289; // 0x5BA5 + DCRX_PHY_MACRO_CNTL_RESERVED290 :TDCRX_PHY_MACRO_CNTL_RESERVED290; // 0x5BA6 + DCRX_PHY_MACRO_CNTL_RESERVED291 :TDCRX_PHY_MACRO_CNTL_RESERVED291; // 0x5BA7 + DCRX_PHY_MACRO_CNTL_RESERVED292 :TDCRX_PHY_MACRO_CNTL_RESERVED292; // 0x5BA8 + DCRX_PHY_MACRO_CNTL_RESERVED293 :TDCRX_PHY_MACRO_CNTL_RESERVED293; // 0x5BA9 + DCRX_PHY_MACRO_CNTL_RESERVED294 :TDCRX_PHY_MACRO_CNTL_RESERVED294; // 0x5BAA + DCRX_PHY_MACRO_CNTL_RESERVED295 :TDCRX_PHY_MACRO_CNTL_RESERVED295; // 0x5BAB + DCRX_PHY_MACRO_CNTL_RESERVED296 :TDCRX_PHY_MACRO_CNTL_RESERVED296; // 0x5BAC + DCRX_PHY_MACRO_CNTL_RESERVED297 :TDCRX_PHY_MACRO_CNTL_RESERVED297; // 0x5BAD + DCRX_PHY_MACRO_CNTL_RESERVED298 :TDCRX_PHY_MACRO_CNTL_RESERVED298; // 0x5BAE + DCRX_PHY_MACRO_CNTL_RESERVED299 :TDCRX_PHY_MACRO_CNTL_RESERVED299; // 0x5BAF + DCRX_PHY_MACRO_CNTL_RESERVED300 :TDCRX_PHY_MACRO_CNTL_RESERVED300; // 0x5BB0 + DCRX_PHY_MACRO_CNTL_RESERVED301 :TDCRX_PHY_MACRO_CNTL_RESERVED301; // 0x5BB1 + DCRX_PHY_MACRO_CNTL_RESERVED302 :TDCRX_PHY_MACRO_CNTL_RESERVED302; // 0x5BB2 + DCRX_PHY_MACRO_CNTL_RESERVED303 :TDCRX_PHY_MACRO_CNTL_RESERVED303; // 0x5BB3 + DCRX_PHY_MACRO_CNTL_RESERVED304 :TDCRX_PHY_MACRO_CNTL_RESERVED304; // 0x5BB4 + DCRX_PHY_MACRO_CNTL_RESERVED305 :TDCRX_PHY_MACRO_CNTL_RESERVED305; // 0x5BB5 + DCRX_PHY_MACRO_CNTL_RESERVED306 :TDCRX_PHY_MACRO_CNTL_RESERVED306; // 0x5BB6 + DCRX_PHY_MACRO_CNTL_RESERVED307 :TDCRX_PHY_MACRO_CNTL_RESERVED307; // 0x5BB7 + DCRX_PHY_MACRO_CNTL_RESERVED308 :TDCRX_PHY_MACRO_CNTL_RESERVED308; // 0x5BB8 + DCRX_PHY_MACRO_CNTL_RESERVED309 :TDCRX_PHY_MACRO_CNTL_RESERVED309; // 0x5BB9 + DCRX_PHY_MACRO_CNTL_RESERVED310 :TDCRX_PHY_MACRO_CNTL_RESERVED310; // 0x5BBA + DCRX_PHY_MACRO_CNTL_RESERVED311 :TDCRX_PHY_MACRO_CNTL_RESERVED311; // 0x5BBB + DCRX_PHY_MACRO_CNTL_RESERVED312 :TDCRX_PHY_MACRO_CNTL_RESERVED312; // 0x5BBC + DCRX_PHY_MACRO_CNTL_RESERVED313 :TDCRX_PHY_MACRO_CNTL_RESERVED313; // 0x5BBD + DCRX_PHY_MACRO_CNTL_RESERVED314 :TDCRX_PHY_MACRO_CNTL_RESERVED314; // 0x5BBE + DCRX_PHY_MACRO_CNTL_RESERVED315 :TDCRX_PHY_MACRO_CNTL_RESERVED315; // 0x5BBF + DCRX_PHY_MACRO_CNTL_RESERVED316 :TDCRX_PHY_MACRO_CNTL_RESERVED316; // 0x5BC0 + DCRX_PHY_MACRO_CNTL_RESERVED317 :TDCRX_PHY_MACRO_CNTL_RESERVED317; // 0x5BC1 + DCRX_PHY_MACRO_CNTL_RESERVED318 :TDCRX_PHY_MACRO_CNTL_RESERVED318; // 0x5BC2 + DCRX_PHY_MACRO_CNTL_RESERVED319 :TDCRX_PHY_MACRO_CNTL_RESERVED319; // 0x5BC3 + DCRX_PHY_MACRO_CNTL_RESERVED320 :TDCRX_PHY_MACRO_CNTL_RESERVED320; // 0x5BC4 + DCRX_PHY_MACRO_CNTL_RESERVED321 :TDCRX_PHY_MACRO_CNTL_RESERVED321; // 0x5BC5 + DCRX_PHY_MACRO_CNTL_RESERVED322 :TDCRX_PHY_MACRO_CNTL_RESERVED322; // 0x5BC6 + DCRX_PHY_MACRO_CNTL_RESERVED323 :TDCRX_PHY_MACRO_CNTL_RESERVED323; // 0x5BC7 + DCRX_PHY_MACRO_CNTL_RESERVED324 :TDCRX_PHY_MACRO_CNTL_RESERVED324; // 0x5BC8 + DCRX_PHY_MACRO_CNTL_RESERVED325 :TDCRX_PHY_MACRO_CNTL_RESERVED325; // 0x5BC9 + DCRX_PHY_MACRO_CNTL_RESERVED326 :TDCRX_PHY_MACRO_CNTL_RESERVED326; // 0x5BCA + DCRX_PHY_MACRO_CNTL_RESERVED327 :TDCRX_PHY_MACRO_CNTL_RESERVED327; // 0x5BCB + DCRX_PHY_MACRO_CNTL_RESERVED328 :TDCRX_PHY_MACRO_CNTL_RESERVED328; // 0x5BCC + DCRX_PHY_MACRO_CNTL_RESERVED329 :TDCRX_PHY_MACRO_CNTL_RESERVED329; // 0x5BCD + DCRX_PHY_MACRO_CNTL_RESERVED330 :TDCRX_PHY_MACRO_CNTL_RESERVED330; // 0x5BCE + DCRX_PHY_MACRO_CNTL_RESERVED331 :TDCRX_PHY_MACRO_CNTL_RESERVED331; // 0x5BCF + DCRX_PHY_MACRO_CNTL_RESERVED332 :TDCRX_PHY_MACRO_CNTL_RESERVED332; // 0x5BD0 + DCRX_PHY_MACRO_CNTL_RESERVED333 :TDCRX_PHY_MACRO_CNTL_RESERVED333; // 0x5BD1 + DCRX_PHY_MACRO_CNTL_RESERVED334 :TDCRX_PHY_MACRO_CNTL_RESERVED334; // 0x5BD2 + DCRX_PHY_MACRO_CNTL_RESERVED335 :TDCRX_PHY_MACRO_CNTL_RESERVED335; // 0x5BD3 + DCRX_PHY_MACRO_CNTL_RESERVED336 :TDCRX_PHY_MACRO_CNTL_RESERVED336; // 0x5BD4 + DCRX_PHY_MACRO_CNTL_RESERVED337 :TDCRX_PHY_MACRO_CNTL_RESERVED337; // 0x5BD5 + DCRX_PHY_MACRO_CNTL_RESERVED338 :TDCRX_PHY_MACRO_CNTL_RESERVED338; // 0x5BD6 + DCRX_PHY_MACRO_CNTL_RESERVED339 :TDCRX_PHY_MACRO_CNTL_RESERVED339; // 0x5BD7 + DCRX_PHY_MACRO_CNTL_RESERVED340 :TDCRX_PHY_MACRO_CNTL_RESERVED340; // 0x5BD8 + DCRX_PHY_MACRO_CNTL_RESERVED341 :TDCRX_PHY_MACRO_CNTL_RESERVED341; // 0x5BD9 + DCRX_PHY_MACRO_CNTL_RESERVED342 :TDCRX_PHY_MACRO_CNTL_RESERVED342; // 0x5BDA + DCRX_PHY_MACRO_CNTL_RESERVED343 :TDCRX_PHY_MACRO_CNTL_RESERVED343; // 0x5BDB + DCRX_PHY_MACRO_CNTL_RESERVED344 :TDCRX_PHY_MACRO_CNTL_RESERVED344; // 0x5BDC + DCRX_PHY_MACRO_CNTL_RESERVED345 :TDCRX_PHY_MACRO_CNTL_RESERVED345; // 0x5BDD + DCRX_PHY_MACRO_CNTL_RESERVED346 :TDCRX_PHY_MACRO_CNTL_RESERVED346; // 0x5BDE + DCRX_PHY_MACRO_CNTL_RESERVED347 :TDCRX_PHY_MACRO_CNTL_RESERVED347; // 0x5BDF + DCRX_PHY_MACRO_CNTL_RESERVED348 :TDCRX_PHY_MACRO_CNTL_RESERVED348; // 0x5BE0 + DCRX_PHY_MACRO_CNTL_RESERVED349 :TDCRX_PHY_MACRO_CNTL_RESERVED349; // 0x5BE1 + DCRX_PHY_MACRO_CNTL_RESERVED350 :TDCRX_PHY_MACRO_CNTL_RESERVED350; // 0x5BE2 + DCRX_PHY_MACRO_CNTL_RESERVED351 :TDCRX_PHY_MACRO_CNTL_RESERVED351; // 0x5BE3 + DCRX_PHY_MACRO_CNTL_RESERVED352 :TDCRX_PHY_MACRO_CNTL_RESERVED352; // 0x5BE4 + DCRX_PHY_MACRO_CNTL_RESERVED353 :TDCRX_PHY_MACRO_CNTL_RESERVED353; // 0x5BE5 + DCRX_PHY_MACRO_CNTL_RESERVED354 :TDCRX_PHY_MACRO_CNTL_RESERVED354; // 0x5BE6 + DCRX_PHY_MACRO_CNTL_RESERVED355 :TDCRX_PHY_MACRO_CNTL_RESERVED355; // 0x5BE7 + DCRX_PHY_MACRO_CNTL_RESERVED356 :TDCRX_PHY_MACRO_CNTL_RESERVED356; // 0x5BE8 + DCRX_PHY_MACRO_CNTL_RESERVED357 :TDCRX_PHY_MACRO_CNTL_RESERVED357; // 0x5BE9 + DCRX_PHY_MACRO_CNTL_RESERVED358 :TDCRX_PHY_MACRO_CNTL_RESERVED358; // 0x5BEA + DCRX_PHY_MACRO_CNTL_RESERVED359 :TDCRX_PHY_MACRO_CNTL_RESERVED359; // 0x5BEB + DCRX_PHY_MACRO_CNTL_RESERVED360 :TDCRX_PHY_MACRO_CNTL_RESERVED360; // 0x5BEC + DCRX_PHY_MACRO_CNTL_RESERVED361 :TDCRX_PHY_MACRO_CNTL_RESERVED361; // 0x5BED + DCRX_PHY_MACRO_CNTL_RESERVED362 :TDCRX_PHY_MACRO_CNTL_RESERVED362; // 0x5BEE + DCRX_PHY_MACRO_CNTL_RESERVED363 :TDCRX_PHY_MACRO_CNTL_RESERVED363; // 0x5BEF + DCRX_PHY_MACRO_CNTL_RESERVED364 :TDCRX_PHY_MACRO_CNTL_RESERVED364; // 0x5BF0 + DCRX_PHY_MACRO_CNTL_RESERVED365 :TDCRX_PHY_MACRO_CNTL_RESERVED365; // 0x5BF1 + DCRX_PHY_MACRO_CNTL_RESERVED366 :TDCRX_PHY_MACRO_CNTL_RESERVED366; // 0x5BF2 + DCRX_PHY_MACRO_CNTL_RESERVED367 :TDCRX_PHY_MACRO_CNTL_RESERVED367; // 0x5BF3 + DCRX_PHY_MACRO_CNTL_RESERVED368 :TDCRX_PHY_MACRO_CNTL_RESERVED368; // 0x5BF4 + DCRX_PHY_MACRO_CNTL_RESERVED369 :TDCRX_PHY_MACRO_CNTL_RESERVED369; // 0x5BF5 + DCRX_PHY_MACRO_CNTL_RESERVED370 :TDCRX_PHY_MACRO_CNTL_RESERVED370; // 0x5BF6 + DCRX_PHY_MACRO_CNTL_RESERVED371 :TDCRX_PHY_MACRO_CNTL_RESERVED371; // 0x5BF7 + DCRX_PHY_MACRO_CNTL_RESERVED372 :TDCRX_PHY_MACRO_CNTL_RESERVED372; // 0x5BF8 + DCRX_PHY_MACRO_CNTL_RESERVED373 :TDCRX_PHY_MACRO_CNTL_RESERVED373; // 0x5BF9 + DCRX_PHY_MACRO_CNTL_RESERVED374 :TDCRX_PHY_MACRO_CNTL_RESERVED374; // 0x5BFA + DCRX_PHY_MACRO_CNTL_RESERVED375 :TDCRX_PHY_MACRO_CNTL_RESERVED375; // 0x5BFB + DCRX_PHY_MACRO_CNTL_RESERVED376 :TDCRX_PHY_MACRO_CNTL_RESERVED376; // 0x5BFC + DCRX_PHY_MACRO_CNTL_RESERVED377 :TDCRX_PHY_MACRO_CNTL_RESERVED377; // 0x5BFD + DCRX_PHY_MACRO_CNTL_RESERVED378 :TDCRX_PHY_MACRO_CNTL_RESERVED378; // 0x5BFE + DCRX_PHY_MACRO_CNTL_RESERVED379 :TDCRX_PHY_MACRO_CNTL_RESERVED379; // 0x5BFF + AUX_CONTROL :TAUX_CONTROL; // 0x5C00 + AUX_SW_CONTROL :TAUX_SW_CONTROL; // 0x5C01 + AUX_ARB_CONTROL :TAUX_ARB_CONTROL; // 0x5C02 + AUX_INTERRUPT_CONTROL :TAUX_INTERRUPT_CONTROL; // 0x5C03 + AUX_SW_STATUS :TAUX_SW_STATUS; // 0x5C04 + AUX_LS_STATUS :TAUX_LS_STATUS; // 0x5C05 + AUX_SW_DATA :TAUX_SW_DATA; // 0x5C06 + AUX_LS_DATA :TAUX_LS_DATA; // 0x5C07 + AUX_DPHY_TX_REF_CONTROL :TAUX_DPHY_TX_REF_CONTROL; // 0x5C08 + AUX_DPHY_TX_CONTROL :TAUX_DPHY_TX_CONTROL; // 0x5C09 + AUX_DPHY_RX_CONTROL0 :TAUX_DPHY_RX_CONTROL0; // 0x5C0A + AUX_DPHY_RX_CONTROL1 :TAUX_DPHY_RX_CONTROL1; // 0x5C0B + AUX_DPHY_TX_STATUS :TAUX_DPHY_TX_STATUS; // 0x5C0C + AUX_DPHY_RX_STATUS :TAUX_DPHY_RX_STATUS; // 0x5C0D + AUX_GTC_SYNC_CONTROL :TAUX_GTC_SYNC_CONTROL; // 0x5C0E + AUX_GTC_SYNC_ERROR_CONTROL :TAUX_GTC_SYNC_ERROR_CONTROL; // 0x5C0F + AUX_GTC_SYNC_CONTROLLER_STATUS :TAUX_GTC_SYNC_CONTROLLER_STATUS; // 0x5C10 + AUX_GTC_SYNC_STATUS :TAUX_GTC_SYNC_STATUS; // 0x5C11 + AUX_GTC_SYNC_DATA :TAUX_GTC_SYNC_DATA; // 0x5C12 + AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :TAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE; // 0x5C13 + AUX_TEST_DEBUG_INDEX :TAUX_TEST_DEBUG_INDEX; // 0x5C14 + AUX_TEST_DEBUG_DATA :TAUX_TEST_DEBUG_DATA; // 0x5C15 + REG_5C16_5C1B :array[0..5] of DWORD; // 0x5C16 + DP_AUX1_AUX_CONTROL :DWORD; // 0x5C1C + DP_AUX1_AUX_SW_CONTROL :DWORD; // 0x5C1D + DP_AUX1_AUX_ARB_CONTROL :DWORD; // 0x5C1E + DP_AUX1_AUX_INTERRUPT_CONTROL :DWORD; // 0x5C1F + DP_AUX1_AUX_SW_STATUS :DWORD; // 0x5C20 + DP_AUX1_AUX_LS_STATUS :DWORD; // 0x5C21 + DP_AUX1_AUX_SW_DATA :DWORD; // 0x5C22 + DP_AUX1_AUX_LS_DATA :DWORD; // 0x5C23 + DP_AUX1_AUX_DPHY_TX_REF_CONTROL :DWORD; // 0x5C24 + DP_AUX1_AUX_DPHY_TX_CONTROL :DWORD; // 0x5C25 + DP_AUX1_AUX_DPHY_RX_CONTROL0 :DWORD; // 0x5C26 + DP_AUX1_AUX_DPHY_RX_CONTROL1 :DWORD; // 0x5C27 + DP_AUX1_AUX_DPHY_TX_STATUS :DWORD; // 0x5C28 + DP_AUX1_AUX_DPHY_RX_STATUS :DWORD; // 0x5C29 + DP_AUX1_AUX_GTC_SYNC_CONTROL :DWORD; // 0x5C2A + DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL :DWORD; // 0x5C2B + DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS :DWORD; // 0x5C2C + DP_AUX1_AUX_GTC_SYNC_STATUS :DWORD; // 0x5C2D + DP_AUX1_AUX_GTC_SYNC_DATA :DWORD; // 0x5C2E + DP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :DWORD; // 0x5C2F + DP_AUX1_AUX_TEST_DEBUG_INDEX :DWORD; // 0x5C30 + DP_AUX1_AUX_TEST_DEBUG_DATA :DWORD; // 0x5C31 + REG_5C32_5C37 :array[0..5] of DWORD; // 0x5C32 + DP_AUX2_AUX_CONTROL :DWORD; // 0x5C38 + DP_AUX2_AUX_SW_CONTROL :DWORD; // 0x5C39 + DP_AUX2_AUX_ARB_CONTROL :DWORD; // 0x5C3A + DP_AUX2_AUX_INTERRUPT_CONTROL :DWORD; // 0x5C3B + DP_AUX2_AUX_SW_STATUS :DWORD; // 0x5C3C + DP_AUX2_AUX_LS_STATUS :DWORD; // 0x5C3D + DP_AUX2_AUX_SW_DATA :DWORD; // 0x5C3E + DP_AUX2_AUX_LS_DATA :DWORD; // 0x5C3F + DP_AUX2_AUX_DPHY_TX_REF_CONTROL :DWORD; // 0x5C40 + DP_AUX2_AUX_DPHY_TX_CONTROL :DWORD; // 0x5C41 + DP_AUX2_AUX_DPHY_RX_CONTROL0 :DWORD; // 0x5C42 + DP_AUX2_AUX_DPHY_RX_CONTROL1 :DWORD; // 0x5C43 + DP_AUX2_AUX_DPHY_TX_STATUS :DWORD; // 0x5C44 + DP_AUX2_AUX_DPHY_RX_STATUS :DWORD; // 0x5C45 + DP_AUX2_AUX_GTC_SYNC_CONTROL :DWORD; // 0x5C46 + DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL :DWORD; // 0x5C47 + DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS :DWORD; // 0x5C48 + DP_AUX2_AUX_GTC_SYNC_STATUS :DWORD; // 0x5C49 + DP_AUX2_AUX_GTC_SYNC_DATA :DWORD; // 0x5C4A + DP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :DWORD; // 0x5C4B + DP_AUX2_AUX_TEST_DEBUG_INDEX :DWORD; // 0x5C4C + DP_AUX2_AUX_TEST_DEBUG_DATA :DWORD; // 0x5C4D + REG_5C4E_5C53 :array[0..5] of DWORD; // 0x5C4E + DP_AUX3_AUX_CONTROL :DWORD; // 0x5C54 + DP_AUX3_AUX_SW_CONTROL :DWORD; // 0x5C55 + DP_AUX3_AUX_ARB_CONTROL :DWORD; // 0x5C56 + DP_AUX3_AUX_INTERRUPT_CONTROL :DWORD; // 0x5C57 + DP_AUX3_AUX_SW_STATUS :DWORD; // 0x5C58 + DP_AUX3_AUX_LS_STATUS :DWORD; // 0x5C59 + DP_AUX3_AUX_SW_DATA :DWORD; // 0x5C5A + DP_AUX3_AUX_LS_DATA :DWORD; // 0x5C5B + DP_AUX3_AUX_DPHY_TX_REF_CONTROL :DWORD; // 0x5C5C + DP_AUX3_AUX_DPHY_TX_CONTROL :DWORD; // 0x5C5D + DP_AUX3_AUX_DPHY_RX_CONTROL0 :DWORD; // 0x5C5E + DP_AUX3_AUX_DPHY_RX_CONTROL1 :DWORD; // 0x5C5F + DP_AUX3_AUX_DPHY_TX_STATUS :DWORD; // 0x5C60 + DP_AUX3_AUX_DPHY_RX_STATUS :DWORD; // 0x5C61 + DP_AUX3_AUX_GTC_SYNC_CONTROL :DWORD; // 0x5C62 + DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL :DWORD; // 0x5C63 + DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS :DWORD; // 0x5C64 + DP_AUX3_AUX_GTC_SYNC_STATUS :DWORD; // 0x5C65 + DP_AUX3_AUX_GTC_SYNC_DATA :DWORD; // 0x5C66 + DP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :DWORD; // 0x5C67 + DP_AUX3_AUX_TEST_DEBUG_INDEX :DWORD; // 0x5C68 + DP_AUX3_AUX_TEST_DEBUG_DATA :DWORD; // 0x5C69 + REG_5C6A_5C6F :array[0..5] of DWORD; // 0x5C6A + DP_AUX4_AUX_CONTROL :DWORD; // 0x5C70 + DP_AUX4_AUX_SW_CONTROL :DWORD; // 0x5C71 + DP_AUX4_AUX_ARB_CONTROL :DWORD; // 0x5C72 + DP_AUX4_AUX_INTERRUPT_CONTROL :DWORD; // 0x5C73 + DP_AUX4_AUX_SW_STATUS :DWORD; // 0x5C74 + DP_AUX4_AUX_LS_STATUS :DWORD; // 0x5C75 + DP_AUX4_AUX_SW_DATA :DWORD; // 0x5C76 + DP_AUX4_AUX_LS_DATA :DWORD; // 0x5C77 + DP_AUX4_AUX_DPHY_TX_REF_CONTROL :DWORD; // 0x5C78 + DP_AUX4_AUX_DPHY_TX_CONTROL :DWORD; // 0x5C79 + DP_AUX4_AUX_DPHY_RX_CONTROL0 :DWORD; // 0x5C7A + DP_AUX4_AUX_DPHY_RX_CONTROL1 :DWORD; // 0x5C7B + DP_AUX4_AUX_DPHY_TX_STATUS :DWORD; // 0x5C7C + DP_AUX4_AUX_DPHY_RX_STATUS :DWORD; // 0x5C7D + DP_AUX4_AUX_GTC_SYNC_CONTROL :DWORD; // 0x5C7E + DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL :DWORD; // 0x5C7F + DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS :DWORD; // 0x5C80 + DP_AUX4_AUX_GTC_SYNC_STATUS :DWORD; // 0x5C81 + DP_AUX4_AUX_GTC_SYNC_DATA :DWORD; // 0x5C82 + DP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :DWORD; // 0x5C83 + DP_AUX4_AUX_TEST_DEBUG_INDEX :DWORD; // 0x5C84 + DP_AUX4_AUX_TEST_DEBUG_DATA :DWORD; // 0x5C85 + REG_5C86_5C8B :array[0..5] of DWORD; // 0x5C86 + DP_AUX5_AUX_CONTROL :DWORD; // 0x5C8C + DP_AUX5_AUX_SW_CONTROL :DWORD; // 0x5C8D + DP_AUX5_AUX_ARB_CONTROL :DWORD; // 0x5C8E + DP_AUX5_AUX_INTERRUPT_CONTROL :DWORD; // 0x5C8F + DP_AUX5_AUX_SW_STATUS :DWORD; // 0x5C90 + DP_AUX5_AUX_LS_STATUS :DWORD; // 0x5C91 + DP_AUX5_AUX_SW_DATA :DWORD; // 0x5C92 + DP_AUX5_AUX_LS_DATA :DWORD; // 0x5C93 + DP_AUX5_AUX_DPHY_TX_REF_CONTROL :DWORD; // 0x5C94 + DP_AUX5_AUX_DPHY_TX_CONTROL :DWORD; // 0x5C95 + DP_AUX5_AUX_DPHY_RX_CONTROL0 :DWORD; // 0x5C96 + DP_AUX5_AUX_DPHY_RX_CONTROL1 :DWORD; // 0x5C97 + DP_AUX5_AUX_DPHY_TX_STATUS :DWORD; // 0x5C98 + DP_AUX5_AUX_DPHY_RX_STATUS :DWORD; // 0x5C99 + DP_AUX5_AUX_GTC_SYNC_CONTROL :DWORD; // 0x5C9A + DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL :DWORD; // 0x5C9B + DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS :DWORD; // 0x5C9C + DP_AUX5_AUX_GTC_SYNC_STATUS :DWORD; // 0x5C9D + DP_AUX5_AUX_GTC_SYNC_DATA :DWORD; // 0x5C9E + DP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :DWORD; // 0x5C9F + DP_AUX5_AUX_TEST_DEBUG_INDEX :DWORD; // 0x5CA0 + DP_AUX5_AUX_TEST_DEBUG_DATA :DWORD; // 0x5CA1 + REG_5CA2_5D97 :array[0..245] of DWORD; // 0x5CA2 + DPHY_MACRO_CNTL_RESERVED0 :TDPHY_MACRO_CNTL_RESERVED0; // 0x5D98 + DPHY_MACRO_CNTL_RESERVED1 :TDPHY_MACRO_CNTL_RESERVED1; // 0x5D99 + DPHY_MACRO_CNTL_RESERVED2 :TDPHY_MACRO_CNTL_RESERVED2; // 0x5D9A + DPHY_MACRO_CNTL_RESERVED3 :TDPHY_MACRO_CNTL_RESERVED3; // 0x5D9B + DPHY_MACRO_CNTL_RESERVED4 :TDPHY_MACRO_CNTL_RESERVED4; // 0x5D9C + DPHY_MACRO_CNTL_RESERVED5 :TDPHY_MACRO_CNTL_RESERVED5; // 0x5D9D + DPHY_MACRO_CNTL_RESERVED6 :TDPHY_MACRO_CNTL_RESERVED6; // 0x5D9E + DPHY_MACRO_CNTL_RESERVED7 :TDPHY_MACRO_CNTL_RESERVED7; // 0x5D9F + DPHY_MACRO_CNTL_RESERVED8 :TDPHY_MACRO_CNTL_RESERVED8; // 0x5DA0 + DPHY_MACRO_CNTL_RESERVED9 :TDPHY_MACRO_CNTL_RESERVED9; // 0x5DA1 + DPHY_MACRO_CNTL_RESERVED10 :TDPHY_MACRO_CNTL_RESERVED10; // 0x5DA2 + DPHY_MACRO_CNTL_RESERVED11 :TDPHY_MACRO_CNTL_RESERVED11; // 0x5DA3 + DPHY_MACRO_CNTL_RESERVED12 :TDPHY_MACRO_CNTL_RESERVED12; // 0x5DA4 + DPHY_MACRO_CNTL_RESERVED13 :TDPHY_MACRO_CNTL_RESERVED13; // 0x5DA5 + DPHY_MACRO_CNTL_RESERVED14 :TDPHY_MACRO_CNTL_RESERVED14; // 0x5DA6 + DPHY_MACRO_CNTL_RESERVED15 :TDPHY_MACRO_CNTL_RESERVED15; // 0x5DA7 + DPHY_MACRO_CNTL_RESERVED16 :TDPHY_MACRO_CNTL_RESERVED16; // 0x5DA8 + DPHY_MACRO_CNTL_RESERVED17 :TDPHY_MACRO_CNTL_RESERVED17; // 0x5DA9 + DPHY_MACRO_CNTL_RESERVED18 :TDPHY_MACRO_CNTL_RESERVED18; // 0x5DAA + DPHY_MACRO_CNTL_RESERVED19 :TDPHY_MACRO_CNTL_RESERVED19; // 0x5DAB + DPHY_MACRO_CNTL_RESERVED20 :TDPHY_MACRO_CNTL_RESERVED20; // 0x5DAC + DPHY_MACRO_CNTL_RESERVED21 :TDPHY_MACRO_CNTL_RESERVED21; // 0x5DAD + DPHY_MACRO_CNTL_RESERVED22 :TDPHY_MACRO_CNTL_RESERVED22; // 0x5DAE + DPHY_MACRO_CNTL_RESERVED23 :TDPHY_MACRO_CNTL_RESERVED23; // 0x5DAF + DPHY_MACRO_CNTL_RESERVED24 :TDPHY_MACRO_CNTL_RESERVED24; // 0x5DB0 + DPHY_MACRO_CNTL_RESERVED25 :TDPHY_MACRO_CNTL_RESERVED25; // 0x5DB1 + DPHY_MACRO_CNTL_RESERVED26 :TDPHY_MACRO_CNTL_RESERVED26; // 0x5DB2 + DPHY_MACRO_CNTL_RESERVED27 :TDPHY_MACRO_CNTL_RESERVED27; // 0x5DB3 + DPHY_MACRO_CNTL_RESERVED28 :TDPHY_MACRO_CNTL_RESERVED28; // 0x5DB4 + DPHY_MACRO_CNTL_RESERVED29 :TDPHY_MACRO_CNTL_RESERVED29; // 0x5DB5 + DPHY_MACRO_CNTL_RESERVED30 :TDPHY_MACRO_CNTL_RESERVED30; // 0x5DB6 + DPHY_MACRO_CNTL_RESERVED31 :TDPHY_MACRO_CNTL_RESERVED31; // 0x5DB7 + DPHY_MACRO_CNTL_RESERVED32 :TDPHY_MACRO_CNTL_RESERVED32; // 0x5DB8 + DPHY_MACRO_CNTL_RESERVED33 :TDPHY_MACRO_CNTL_RESERVED33; // 0x5DB9 + DPHY_MACRO_CNTL_RESERVED34 :TDPHY_MACRO_CNTL_RESERVED34; // 0x5DBA + DPHY_MACRO_CNTL_RESERVED35 :TDPHY_MACRO_CNTL_RESERVED35; // 0x5DBB + DPHY_MACRO_CNTL_RESERVED36 :TDPHY_MACRO_CNTL_RESERVED36; // 0x5DBC + DPHY_MACRO_CNTL_RESERVED37 :TDPHY_MACRO_CNTL_RESERVED37; // 0x5DBD + DPHY_MACRO_CNTL_RESERVED38 :TDPHY_MACRO_CNTL_RESERVED38; // 0x5DBE + DPHY_MACRO_CNTL_RESERVED39 :TDPHY_MACRO_CNTL_RESERVED39; // 0x5DBF + DPHY_MACRO_CNTL_RESERVED40 :TDPHY_MACRO_CNTL_RESERVED40; // 0x5DC0 + DPHY_MACRO_CNTL_RESERVED41 :TDPHY_MACRO_CNTL_RESERVED41; // 0x5DC1 + DPHY_MACRO_CNTL_RESERVED42 :TDPHY_MACRO_CNTL_RESERVED42; // 0x5DC2 + DPHY_MACRO_CNTL_RESERVED43 :TDPHY_MACRO_CNTL_RESERVED43; // 0x5DC3 + DPHY_MACRO_CNTL_RESERVED44 :TDPHY_MACRO_CNTL_RESERVED44; // 0x5DC4 + DPHY_MACRO_CNTL_RESERVED45 :TDPHY_MACRO_CNTL_RESERVED45; // 0x5DC5 + DPHY_MACRO_CNTL_RESERVED46 :TDPHY_MACRO_CNTL_RESERVED46; // 0x5DC6 + DPHY_MACRO_CNTL_RESERVED47 :TDPHY_MACRO_CNTL_RESERVED47; // 0x5DC7 + DPHY_MACRO_CNTL_RESERVED48 :TDPHY_MACRO_CNTL_RESERVED48; // 0x5DC8 + DPHY_MACRO_CNTL_RESERVED49 :TDPHY_MACRO_CNTL_RESERVED49; // 0x5DC9 + DPHY_MACRO_CNTL_RESERVED50 :TDPHY_MACRO_CNTL_RESERVED50; // 0x5DCA + DPHY_MACRO_CNTL_RESERVED51 :TDPHY_MACRO_CNTL_RESERVED51; // 0x5DCB + DPHY_MACRO_CNTL_RESERVED52 :TDPHY_MACRO_CNTL_RESERVED52; // 0x5DCC + DPHY_MACRO_CNTL_RESERVED53 :TDPHY_MACRO_CNTL_RESERVED53; // 0x5DCD + DPHY_MACRO_CNTL_RESERVED54 :TDPHY_MACRO_CNTL_RESERVED54; // 0x5DCE + DPHY_MACRO_CNTL_RESERVED55 :TDPHY_MACRO_CNTL_RESERVED55; // 0x5DCF + DPHY_MACRO_CNTL_RESERVED56 :TDPHY_MACRO_CNTL_RESERVED56; // 0x5DD0 + DPHY_MACRO_CNTL_RESERVED57 :TDPHY_MACRO_CNTL_RESERVED57; // 0x5DD1 + DPHY_MACRO_CNTL_RESERVED58 :TDPHY_MACRO_CNTL_RESERVED58; // 0x5DD2 + DPHY_MACRO_CNTL_RESERVED59 :TDPHY_MACRO_CNTL_RESERVED59; // 0x5DD3 + DPHY_MACRO_CNTL_RESERVED60 :TDPHY_MACRO_CNTL_RESERVED60; // 0x5DD4 + DPHY_MACRO_CNTL_RESERVED61 :TDPHY_MACRO_CNTL_RESERVED61; // 0x5DD5 + DPHY_MACRO_CNTL_RESERVED62 :TDPHY_MACRO_CNTL_RESERVED62; // 0x5DD6 + DPHY_MACRO_CNTL_RESERVED63 :TDPHY_MACRO_CNTL_RESERVED63; // 0x5DD7 + REG_5DD8_5E17 :array[0..63] of DWORD; // 0x5DD8 + WB_ENABLE :TWB_ENABLE; // 0x5E18 + WB_EC_CONFIG :TWB_EC_CONFIG; // 0x5E19 + CNV_MODE :TCNV_MODE; // 0x5E1A + CNV_WINDOW_START :TCNV_WINDOW_START; // 0x5E1B + CNV_WINDOW_SIZE :TCNV_WINDOW_SIZE; // 0x5E1C + CNV_UPDATE :TCNV_UPDATE; // 0x5E1D + CNV_SOURCE_SIZE :TCNV_SOURCE_SIZE; // 0x5E1E + CNV_CSC_CONTROL :TCNV_CSC_CONTROL; // 0x5E1F + CNV_CSC_C11_C12 :TCNV_CSC_C11_C12; // 0x5E20 + CNV_CSC_C13_C14 :TCNV_CSC_C13_C14; // 0x5E21 + CNV_CSC_C21_C22 :TCNV_CSC_C21_C22; // 0x5E22 + CNV_CSC_C23_C24 :TCNV_CSC_C23_C24; // 0x5E23 + CNV_CSC_C31_C32 :TCNV_CSC_C31_C32; // 0x5E24 + CNV_CSC_C33_C34 :TCNV_CSC_C33_C34; // 0x5E25 + CNV_CSC_ROUND_OFFSET_R :TCNV_CSC_ROUND_OFFSET_R; // 0x5E26 + CNV_CSC_ROUND_OFFSET_G :TCNV_CSC_ROUND_OFFSET_G; // 0x5E27 + CNV_CSC_ROUND_OFFSET_B :TCNV_CSC_ROUND_OFFSET_B; // 0x5E28 + CNV_CSC_CLAMP_R :TCNV_CSC_CLAMP_R; // 0x5E29 + CNV_CSC_CLAMP_G :TCNV_CSC_CLAMP_G; // 0x5E2A + CNV_CSC_CLAMP_B :TCNV_CSC_CLAMP_B; // 0x5E2B + CNV_TEST_CNTL :TCNV_TEST_CNTL; // 0x5E2C + CNV_TEST_CRC_RED :TCNV_TEST_CRC_RED; // 0x5E2D + CNV_TEST_CRC_GREEN :TCNV_TEST_CRC_GREEN; // 0x5E2E + CNV_TEST_CRC_BLUE :TCNV_TEST_CRC_BLUE; // 0x5E2F + WB_DEBUG_CTRL :TWB_DEBUG_CTRL; // 0x5E30 + WB_DBG_MODE :TWB_DBG_MODE; // 0x5E31 + WB_HW_DEBUG :TWB_HW_DEBUG; // 0x5E32 + CNV_INPUT_SELECT :TCNV_INPUT_SELECT; // 0x5E33 + CNV_TEST_DEBUG_INDEX :TCNV_TEST_DEBUG_INDEX; // 0x5E34 + CNV_TEST_DEBUG_DATA :TCNV_TEST_DEBUG_DATA; // 0x5E35 + WB_SOFT_RESET :TWB_SOFT_RESET; // 0x5E36 + REG_5E37_5E77 :array[0..64] of DWORD; // 0x5E37 + MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL :DWORD; // 0x5E78 + MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R :DWORD; // 0x5E79 + MCIF_WB0_MCIF_WB_BUFMGR_STATUS :DWORD; // 0x5E7A + MCIF_WB0_MCIF_WB_BUF_PITCH :DWORD; // 0x5E7B + MCIF_WB0_MCIF_WB_BUF_1_STATUS :DWORD; // 0x5E7C + MCIF_WB0_MCIF_WB_BUF_1_STATUS2 :DWORD; // 0x5E7D + MCIF_WB0_MCIF_WB_BUF_2_STATUS :DWORD; // 0x5E7E + MCIF_WB0_MCIF_WB_BUF_2_STATUS2 :DWORD; // 0x5E7F + MCIF_WB0_MCIF_WB_BUF_3_STATUS :DWORD; // 0x5E80 + MCIF_WB0_MCIF_WB_BUF_3_STATUS2 :DWORD; // 0x5E81 + MCIF_WB0_MCIF_WB_BUF_4_STATUS :DWORD; // 0x5E82 + MCIF_WB0_MCIF_WB_BUF_4_STATUS2 :DWORD; // 0x5E83 + MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL :DWORD; // 0x5E84 + MCIF_WB0_MCIF_WB_URGENCY_WATERMARK :DWORD; // 0x5E85 + MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX :DWORD; // 0x5E86 + MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA :DWORD; // 0x5E87 + MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y :DWORD; // 0x5E88 + MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET :DWORD; // 0x5E89 + MCIF_WB0_MCIF_WB_BUF_1_ADDR_C :DWORD; // 0x5E8A + MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET :DWORD; // 0x5E8B + MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y :DWORD; // 0x5E8C + MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET :DWORD; // 0x5E8D + MCIF_WB0_MCIF_WB_BUF_2_ADDR_C :DWORD; // 0x5E8E + MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET :DWORD; // 0x5E8F + MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y :DWORD; // 0x5E90 + MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET :DWORD; // 0x5E91 + MCIF_WB0_MCIF_WB_BUF_3_ADDR_C :DWORD; // 0x5E92 + MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET :DWORD; // 0x5E93 + MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y :DWORD; // 0x5E94 + MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET :DWORD; // 0x5E95 + MCIF_WB0_MCIF_WB_BUF_4_ADDR_C :DWORD; // 0x5E96 + MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET :DWORD; // 0x5E97 + MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL :DWORD; // 0x5E98 + MCIF_WB0_MCIF_WB_HVVMID_CONTROL :DWORD; // 0x5E99 + REG_5E9A_5EB7 :array[0..29] of DWORD; // 0x5E9A + MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL :DWORD; // 0x5EB8 + MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R :DWORD; // 0x5EB9 + MCIF_WB1_MCIF_WB_BUFMGR_STATUS :DWORD; // 0x5EBA + MCIF_WB1_MCIF_WB_BUF_PITCH :DWORD; // 0x5EBB + MCIF_WB1_MCIF_WB_BUF_1_STATUS :DWORD; // 0x5EBC + MCIF_WB1_MCIF_WB_BUF_1_STATUS2 :DWORD; // 0x5EBD + MCIF_WB1_MCIF_WB_BUF_2_STATUS :DWORD; // 0x5EBE + MCIF_WB1_MCIF_WB_BUF_2_STATUS2 :DWORD; // 0x5EBF + MCIF_WB1_MCIF_WB_BUF_3_STATUS :DWORD; // 0x5EC0 + MCIF_WB1_MCIF_WB_BUF_3_STATUS2 :DWORD; // 0x5EC1 + MCIF_WB1_MCIF_WB_BUF_4_STATUS :DWORD; // 0x5EC2 + MCIF_WB1_MCIF_WB_BUF_4_STATUS2 :DWORD; // 0x5EC3 + MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL :DWORD; // 0x5EC4 + MCIF_WB1_MCIF_WB_URGENCY_WATERMARK :DWORD; // 0x5EC5 + MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX :DWORD; // 0x5EC6 + MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA :DWORD; // 0x5EC7 + MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y :DWORD; // 0x5EC8 + MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET :DWORD; // 0x5EC9 + MCIF_WB1_MCIF_WB_BUF_1_ADDR_C :DWORD; // 0x5ECA + MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET :DWORD; // 0x5ECB + MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y :DWORD; // 0x5ECC + MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET :DWORD; // 0x5ECD + MCIF_WB1_MCIF_WB_BUF_2_ADDR_C :DWORD; // 0x5ECE + MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET :DWORD; // 0x5ECF + MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y :DWORD; // 0x5ED0 + MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET :DWORD; // 0x5ED1 + MCIF_WB1_MCIF_WB_BUF_3_ADDR_C :DWORD; // 0x5ED2 + MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET :DWORD; // 0x5ED3 + MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y :DWORD; // 0x5ED4 + MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET :DWORD; // 0x5ED5 + MCIF_WB1_MCIF_WB_BUF_4_ADDR_C :DWORD; // 0x5ED6 + MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET :DWORD; // 0x5ED7 + MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL :DWORD; // 0x5ED8 + MCIF_WB1_MCIF_WB_HVVMID_CONTROL :DWORD; // 0x5ED9 + REG_5EDA_5EF7 :array[0..29] of DWORD; // 0x5EDA + MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL :DWORD; // 0x5EF8 + MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R :DWORD; // 0x5EF9 + MCIF_WB2_MCIF_WB_BUFMGR_STATUS :DWORD; // 0x5EFA + MCIF_WB2_MCIF_WB_BUF_PITCH :DWORD; // 0x5EFB + MCIF_WB2_MCIF_WB_BUF_1_STATUS :DWORD; // 0x5EFC + MCIF_WB2_MCIF_WB_BUF_1_STATUS2 :DWORD; // 0x5EFD + MCIF_WB2_MCIF_WB_BUF_2_STATUS :DWORD; // 0x5EFE + MCIF_WB2_MCIF_WB_BUF_2_STATUS2 :DWORD; // 0x5EFF + MCIF_WB2_MCIF_WB_BUF_3_STATUS :DWORD; // 0x5F00 + MCIF_WB2_MCIF_WB_BUF_3_STATUS2 :DWORD; // 0x5F01 + MCIF_WB2_MCIF_WB_BUF_4_STATUS :DWORD; // 0x5F02 + MCIF_WB2_MCIF_WB_BUF_4_STATUS2 :DWORD; // 0x5F03 + MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL :DWORD; // 0x5F04 + MCIF_WB2_MCIF_WB_URGENCY_WATERMARK :DWORD; // 0x5F05 + MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX :DWORD; // 0x5F06 + MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA :DWORD; // 0x5F07 + MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y :DWORD; // 0x5F08 + MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET :DWORD; // 0x5F09 + MCIF_WB2_MCIF_WB_BUF_1_ADDR_C :DWORD; // 0x5F0A + MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET :DWORD; // 0x5F0B + MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y :DWORD; // 0x5F0C + MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET :DWORD; // 0x5F0D + MCIF_WB2_MCIF_WB_BUF_2_ADDR_C :DWORD; // 0x5F0E + MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET :DWORD; // 0x5F0F + MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y :DWORD; // 0x5F10 + MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET :DWORD; // 0x5F11 + MCIF_WB2_MCIF_WB_BUF_3_ADDR_C :DWORD; // 0x5F12 + MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET :DWORD; // 0x5F13 + MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y :DWORD; // 0x5F14 + MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET :DWORD; // 0x5F15 + MCIF_WB2_MCIF_WB_BUF_4_ADDR_C :DWORD; // 0x5F16 + MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET :DWORD; // 0x5F17 + MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL :DWORD; // 0x5F18 + MCIF_WB2_MCIF_WB_HVVMID_CONTROL :DWORD; // 0x5F19 + REG_5F1A_5F67 :array[0..77] of DWORD; // 0x5F1A + DC_PERFMON9_PERFCOUNTER_CNTL :DWORD; // 0x5F68 + DC_PERFMON9_PERFCOUNTER_STATE :DWORD; // 0x5F69 + DC_PERFMON9_PERFMON_CVALUE_INT_MISC :DWORD; // 0x5F6A + DC_PERFMON9_PERFMON_CNTL :DWORD; // 0x5F6B + DC_PERFMON9_PERFMON_CVALUE_LOW :DWORD; // 0x5F6C + DC_PERFMON9_PERFMON_HI :DWORD; // 0x5F6D + DC_PERFMON9_PERFMON_LOW :DWORD; // 0x5F6E + DC_PERFMON9_PERFMON_TEST_DEBUG_INDEX :DWORD; // 0x5F6F + DC_PERFMON9_PERFMON_TEST_DEBUG_DATA :DWORD; // 0x5F70 + REG_5F71 :DWORD; // 0x5F71 + DC_PERFMON9_PERFMON_CNTL2 :DWORD; // 0x5F72 + REG_5F73_5FCF :array[0..92] of DWORD; // 0x5F73 + CPLL_MACRO_CNTL_RESERVED0 :TCPLL_MACRO_CNTL_RESERVED0; // 0x5FD0 + CPLL_MACRO_CNTL_RESERVED1 :TCPLL_MACRO_CNTL_RESERVED1; // 0x5FD1 + CPLL_MACRO_CNTL_RESERVED2 :TCPLL_MACRO_CNTL_RESERVED2; // 0x5FD2 + CPLL_MACRO_CNTL_RESERVED3 :TCPLL_MACRO_CNTL_RESERVED3; // 0x5FD3 + CPLL_MACRO_CNTL_RESERVED4 :TCPLL_MACRO_CNTL_RESERVED4; // 0x5FD4 + CPLL_MACRO_CNTL_RESERVED5 :TCPLL_MACRO_CNTL_RESERVED5; // 0x5FD5 + CPLL_MACRO_CNTL_RESERVED6 :TCPLL_MACRO_CNTL_RESERVED6; // 0x5FD6 + CPLL_MACRO_CNTL_RESERVED7 :TCPLL_MACRO_CNTL_RESERVED7; // 0x5FD7 + CPLL_MACRO_CNTL_RESERVED8 :TCPLL_MACRO_CNTL_RESERVED8; // 0x5FD8 + CPLL_MACRO_CNTL_RESERVED9 :TCPLL_MACRO_CNTL_RESERVED9; // 0x5FD9 + CPLL_MACRO_CNTL_RESERVED10 :TCPLL_MACRO_CNTL_RESERVED10; // 0x5FDA + CPLL_MACRO_CNTL_RESERVED11 :TCPLL_MACRO_CNTL_RESERVED11; // 0x5FDB + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 :DWORD; // 0x5FDC + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 :DWORD; // 0x5FDD + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 :DWORD; // 0x5FDE + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 :DWORD; // 0x5FDF + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 :DWORD; // 0x5FE0 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 :DWORD; // 0x5FE1 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 :DWORD; // 0x5FE2 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 :DWORD; // 0x5FE3 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 :DWORD; // 0x5FE4 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 :DWORD; // 0x5FE5 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 :DWORD; // 0x5FE6 + DCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 :DWORD; // 0x5FE7 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 :DWORD; // 0x5FE8 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 :DWORD; // 0x5FE9 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 :DWORD; // 0x5FEA + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 :DWORD; // 0x5FEB + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 :DWORD; // 0x5FEC + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 :DWORD; // 0x5FED + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 :DWORD; // 0x5FEE + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 :DWORD; // 0x5FEF + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 :DWORD; // 0x5FF0 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 :DWORD; // 0x5FF1 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 :DWORD; // 0x5FF2 + DCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 :DWORD; // 0x5FF3 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 :DWORD; // 0x5FF4 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 :DWORD; // 0x5FF5 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 :DWORD; // 0x5FF6 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 :DWORD; // 0x5FF7 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 :DWORD; // 0x5FF8 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 :DWORD; // 0x5FF9 + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 :DWORD; // 0x5FFA + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 :DWORD; // 0x5FFB + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 :DWORD; // 0x5FFC + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 :DWORD; // 0x5FFD + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 :DWORD; // 0x5FFE + DCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 :DWORD; // 0x5FFF + REG_6000_7BFF :array[0..7167] of DWORD; // 0x6000 + SRBM_PERFMON_CNTL :TSRBM_PERFMON_CNTL; // 0x7C00 + SRBM_PERFCOUNTER0_SELECT :TSRBM_PERFCOUNTER0_SELECT; // 0x7C01 + SRBM_PERFCOUNTER1_SELECT :TSRBM_PERFCOUNTER1_SELECT; // 0x7C02 + SRBM_PERFCOUNTER0_LO :TSRBM_PERFCOUNTER0_LO; // 0x7C03 + SRBM_PERFCOUNTER0_HI :TSRBM_PERFCOUNTER0_HI; // 0x7C04 + SRBM_PERFCOUNTER1_LO :TSRBM_PERFCOUNTER1_LO; // 0x7C05 + SRBM_PERFCOUNTER1_HI :TSRBM_PERFCOUNTER1_HI; // 0x7C06 + REG_7C07_8000 :array[0..1017] of DWORD; // 0x7C07 + VCE_STATUS :TVCE_STATUS; // 0x8001 + REG_8002_8004 :array[0..2] of DWORD; // 0x8002 + VCE_VCPU_CNTL :TVCE_VCPU_CNTL; // 0x8005 + REG_8006_8008 :array[0..2] of DWORD; // 0x8006 + VCE_VCPU_CACHE_OFFSET0 :TVCE_VCPU_CACHE_OFFSET0; // 0x8009 + VCE_VCPU_CACHE_SIZE0 :TVCE_VCPU_CACHE_SIZE0; // 0x800A + VCE_VCPU_CACHE_OFFSET1 :TVCE_VCPU_CACHE_OFFSET1; // 0x800B + VCE_VCPU_CACHE_SIZE1 :TVCE_VCPU_CACHE_SIZE1; // 0x800C + VCE_VCPU_CACHE_OFFSET2 :TVCE_VCPU_CACHE_OFFSET2; // 0x800D + VCE_VCPU_CACHE_SIZE2 :TVCE_VCPU_CACHE_SIZE2; // 0x800E + REG_800F_8047 :array[0..56] of DWORD; // 0x800F + VCE_SOFT_RESET :TVCE_SOFT_RESET; // 0x8048 + REG_8049_805A :array[0..17] of DWORD; // 0x8049 + VCE_RB_BASE_LO2 :TVCE_RB_BASE_LO2; // 0x805B + VCE_RB_BASE_HI2 :TVCE_RB_BASE_HI2; // 0x805C + VCE_RB_SIZE2 :TVCE_RB_SIZE2; // 0x805D + VCE_RB_RPTR2 :TVCE_RB_RPTR2; // 0x805E + VCE_RB_WPTR2 :TVCE_RB_WPTR2; // 0x805F + VCE_RB_BASE_LO :TVCE_RB_BASE_LO; // 0x8060 + VCE_RB_BASE_HI :TVCE_RB_BASE_HI; // 0x8061 + VCE_RB_SIZE :TVCE_RB_SIZE; // 0x8062 + VCE_RB_RPTR :TVCE_RB_RPTR; // 0x8063 + VCE_RB_WPTR :TVCE_RB_WPTR; // 0x8064 + REG_8065_809E :array[0..57] of DWORD; // 0x8065 + VCE_RB_ARB_CTRL :TVCE_RB_ARB_CTRL; // 0x809F + REG_80A0_80D3 :array[0..51] of DWORD; // 0x80A0 + VCE_RB_BASE_LO3 :TVCE_RB_BASE_LO3; // 0x80D4 + VCE_RB_BASE_HI3 :TVCE_RB_BASE_HI3; // 0x80D5 + VCE_RB_SIZE3 :TVCE_RB_SIZE3; // 0x80D6 + VCE_RB_RPTR3 :TVCE_RB_RPTR3; // 0x80D7 + VCE_RB_WPTR3 :TVCE_RB_WPTR3; // 0x80D8 + REG_80D9_838F :array[0..694] of DWORD; // 0x80D9 + VCE_UENC_DMA_DCLK_CTRL :TVCE_UENC_DMA_DCLK_CTRL; // 0x8390 + REG_8391_853F :array[0..430] of DWORD; // 0x8391 + VCE_SYS_INT_EN :TVCE_SYS_INT_EN; // 0x8540 + VCE_SYS_INT_ACK :TVCE_SYS_INT_ACK; // 0x8541 + REG_8542_8596 :array[0..84] of DWORD; // 0x8542 + VCE_LMI_VCPU_CACHE_40BIT_BAR :TVCE_LMI_VCPU_CACHE_40BIT_BAR; // 0x8597 + REG_8598_859C :array[0..4] of DWORD; // 0x8598 + VCE_LMI_CTRL2 :TVCE_LMI_CTRL2; // 0x859D + VCE_LMI_SWAP_CNTL3 :TVCE_LMI_SWAP_CNTL3; // 0x859E + REG_859F_85A5 :array[0..6] of DWORD; // 0x859F + VCE_LMI_CTRL :TVCE_LMI_CTRL; // 0x85A6 + REG_85A7_85AC :array[0..5] of DWORD; // 0x85A7 + VCE_LMI_SWAP_CNTL :TVCE_LMI_SWAP_CNTL; // 0x85AD + VCE_LMI_SWAP_CNTL1 :TVCE_LMI_SWAP_CNTL1; // 0x85AE + REG_85AF_85B2 :array[0..3] of DWORD; // 0x85AF + VCE_LMI_SWAP_CNTL2 :TVCE_LMI_SWAP_CNTL2; // 0x85B3 + REG_85B4_85BC :array[0..8] of DWORD; // 0x85B4 + VCE_LMI_CACHE_CTRL :TVCE_LMI_CACHE_CTRL; // 0x85BD + REG_85BE_880F :array[0..593] of DWORD; // 0x85BE + SAM_IH_EXT_ERR_INTR :TSAM_IH_EXT_ERR_INTR; // 0x8810 + REG_8811 :DWORD; // 0x8811 + SAM_IH_EXT_ERR_INTR_STATUS :TSAM_IH_EXT_ERR_INTR_STATUS; // 0x8812 + REG_8813_8FFF :array[0..2028] of DWORD; // 0x8813 + SDMA0_PERFMON_CNTL :TSDMA0_PERFMON_CNTL; // 0x9000 + SDMA0_PERFCOUNTER0_RESULT :TSDMA0_PERFCOUNTER0_RESULT; // 0x9001 + SDMA0_PERFCOUNTER1_RESULT :TSDMA0_PERFCOUNTER1_RESULT; // 0x9002 + REG_9003_900F :array[0..12] of DWORD; // 0x9003 + SDMA1_PERFMON_CNTL :TSDMA1_PERFMON_CNTL; // 0x9010 + SDMA1_PERFCOUNTER0_RESULT :TSDMA1_PERFCOUNTER0_RESULT; // 0x9011 + SDMA1_PERFCOUNTER1_RESULT :TSDMA1_PERFCOUNTER1_RESULT; // 0x9012 end; TUSERCONFIG_REG_GROUP=bitpacked record @@ -1275,7 +6005,17 @@ type CP_PIPE_STATS_CONTROL :TCP_PIPE_STATS_CONTROL; // 0xC03D CP_STREAM_OUT_CONTROL :TCP_STREAM_OUT_CONTROL; // 0xC03E CP_STRMOUT_CNTL :TCP_STRMOUT_CNTL; // 0xC03F - REG_C040_C051 :array[0..17] of DWORD; // 0xC040 + SCRATCH_REG0 :TSCRATCH_REG0; // 0xC040 + SCRATCH_REG1 :TSCRATCH_REG1; // 0xC041 + SCRATCH_REG2 :TSCRATCH_REG2; // 0xC042 + SCRATCH_REG3 :TSCRATCH_REG3; // 0xC043 + SCRATCH_REG4 :TSCRATCH_REG4; // 0xC044 + SCRATCH_REG5 :TSCRATCH_REG5; // 0xC045 + SCRATCH_REG6 :TSCRATCH_REG6; // 0xC046 + SCRATCH_REG7 :TSCRATCH_REG7; // 0xC047 + REG_C048_C04F :array[0..7] of DWORD; // 0xC048 + SCRATCH_UMSK :TSCRATCH_UMSK; // 0xC050 + SCRATCH_ADDR :TSCRATCH_ADDR; // 0xC051 CP_PFP_ATOMIC_PREOP_LO :TCP_PFP_ATOMIC_PREOP_LO; // 0xC052 CP_PFP_ATOMIC_PREOP_HI :TCP_PFP_ATOMIC_PREOP_HI; // 0xC053 CP_PFP_GDS_ATOMIC0_PREOP_LO :TCP_PFP_GDS_ATOMIC0_PREOP_LO; // 0xC054 @@ -1293,7 +6033,13 @@ type CP_GDS_ATOMIC0_PREOP_HI :TCP_GDS_ATOMIC0_PREOP_HI; // 0xC060 CP_GDS_ATOMIC1_PREOP_LO :TCP_GDS_ATOMIC1_PREOP_LO; // 0xC061 CP_GDS_ATOMIC1_PREOP_HI :TCP_GDS_ATOMIC1_PREOP_HI; // 0xC062 - REG_C063_C06E :array[0..11] of DWORD; // 0xC063 + REG_C063_C068 :array[0..5] of DWORD; // 0xC063 + CP_ME_MC_WADDR_LO :TCP_ME_MC_WADDR_LO; // 0xC069 + CP_ME_MC_WADDR_HI :TCP_ME_MC_WADDR_HI; // 0xC06A + CP_ME_MC_WDATA_LO :TCP_ME_MC_WDATA_LO; // 0xC06B + CP_ME_MC_WDATA_HI :TCP_ME_MC_WDATA_HI; // 0xC06C + CP_ME_MC_RADDR_LO :TCP_ME_MC_RADDR_LO; // 0xC06D + CP_ME_MC_RADDR_HI :TCP_ME_MC_RADDR_HI; // 0xC06E CP_SEM_WAIT_TIMER :TCP_SEM_WAIT_TIMER; // 0xC06F CP_SIG_SEM_ADDR_LO :TCP_SIG_SEM_ADDR_LO; // 0xC070 CP_SIG_SEM_ADDR_HI :TCP_SIG_SEM_ADDR_HI; // 0xC071 @@ -1327,7 +6073,7 @@ type CP_PFP_LOAD_CONTROL :TCP_PFP_LOAD_CONTROL; // 0xC08E CP_SCRATCH_INDEX :TCP_SCRATCH_INDEX; // 0xC08F CP_SCRATCH_DATA :TCP_SCRATCH_DATA; // 0xC090 - REG_C091 :DWORD; // 0xC091 + CP_RB_OFFSET :TCP_RB_OFFSET; // 0xC091 CP_IB1_OFFSET :TCP_IB1_OFFSET; // 0xC092 CP_IB2_OFFSET :TCP_IB2_OFFSET; // 0xC093 CP_IB1_PREAMBLE_BEGIN :TCP_IB1_PREAMBLE_BEGIN; // 0xC094 @@ -1435,7 +6181,10 @@ type SQ_THREAD_TRACE_USERDATA_1 :TSQ_THREAD_TRACE_USERDATA_1; // 0xC341 SQ_THREAD_TRACE_USERDATA_2 :TSQ_THREAD_TRACE_USERDATA_2; // 0xC342 SQ_THREAD_TRACE_USERDATA_3 :TSQ_THREAD_TRACE_USERDATA_3; // 0xC343 - REG_C344_C37F :array[0..59] of DWORD; // 0xC344 + REG_C344_C347 :array[0..3] of DWORD; // 0xC344 + SQC_CACHES :TSQC_CACHES; // 0xC348 + SQC_WRITEBACK :TSQC_WRITEBACK; // 0xC349 + REG_C34A_C37F :array[0..53] of DWORD; // 0xC34A TA_CS_BC_BASE_ADDR :TTA_CS_BC_BASE_ADDR; // 0xC380 TA_CS_BC_BASE_ADDR_HI :TTA_CS_BC_BASE_ADDR_HI; // 0xC381 REG_C382_C3BF :array[0..61] of DWORD; // 0xC382 @@ -1681,7 +6430,12 @@ type DB_PERFCOUNTER2_HI :TDB_PERFCOUNTER2_HI; // 0xD445 DB_PERFCOUNTER3_LO :TDB_PERFCOUNTER3_LO; // 0xD446 DB_PERFCOUNTER3_HI :TDB_PERFCOUNTER3_HI; // 0xD447 - REG_D448_D7FF :array[0..951] of DWORD; // 0xD448 + REG_D448_D47F :array[0..55] of DWORD; // 0xD448 + RLC_PERFCOUNTER0_LO :TRLC_PERFCOUNTER0_LO; // 0xD480 + RLC_PERFCOUNTER0_HI :TRLC_PERFCOUNTER0_HI; // 0xD481 + RLC_PERFCOUNTER1_LO :TRLC_PERFCOUNTER1_LO; // 0xD482 + RLC_PERFCOUNTER1_HI :TRLC_PERFCOUNTER1_HI; // 0xD483 + REG_D484_D7FF :array[0..891] of DWORD; // 0xD484 CPG_PERFCOUNTER1_SELECT :TCPG_PERFCOUNTER1_SELECT; // 0xD800 CPG_PERFCOUNTER0_SELECT1 :TCPG_PERFCOUNTER0_SELECT1; // 0xD801 CPG_PERFCOUNTER0_SELECT :TCPG_PERFCOUNTER0_SELECT; // 0xD802 diff --git a/chip/si_ci_vi_merged_offset.pas b/chip/si_ci_vi_merged_offset.pas index 6b62564b..0feb8a9c 100644 --- a/chip/si_ci_vi_merged_offset.pas +++ b/chip/si_ci_vi_merged_offset.pas @@ -5,1999 +5,6433 @@ interface {$mode objfpc}{$H+} const - mmGRBM_CNTL =$2000; - mmGRBM_SKEW_CNTL =$2001; - mmGRBM_STATUS2 =$2002; - mmGRBM_PWR_CNTL =$2003; - mmGRBM_STATUS =$2004; - mmGRBM_STATUS_SE0 =$2005; - mmGRBM_STATUS_SE1 =$2006; - mmGRBM_SOFT_RESET =$2008; - mmGRBM_DEBUG_CNTL =$2009; - mmGRBM_DEBUG_DATA =$200A; - mmGRBM_GFX_CLKEN_CNTL =$200C; - mmGRBM_WAIT_IDLE_CLOCKS =$200D; - mmGRBM_STATUS_SE2 =$200E; - mmGRBM_STATUS_SE3 =$200F; - mmGRBM_DEBUG =$2014; - mmGRBM_DEBUG_SNAPSHOT =$2015; - mmGRBM_READ_ERROR =$2016; - mmGRBM_READ_ERROR2 =$2017; - mmGRBM_INT_CNTL =$2018; - mmGRBM_TRAP_OP =$2019; - mmGRBM_TRAP_ADDR =$201A; - mmGRBM_TRAP_ADDR_MSK =$201B; - mmGRBM_TRAP_WD =$201C; - mmGRBM_TRAP_WD_MSK =$201D; - mmGRBM_DSM_BYPASS =$201E; - mmGRBM_WRITE_ERROR =$201F; - mmGRBM_NOWHERE =$203F; - mmGRBM_SCRATCH_REG0 =$2040; - mmGRBM_SCRATCH_REG1 =$2041; - mmGRBM_SCRATCH_REG2 =$2042; - mmGRBM_SCRATCH_REG3 =$2043; - mmGRBM_SCRATCH_REG4 =$2044; - mmGRBM_SCRATCH_REG5 =$2045; - mmGRBM_SCRATCH_REG6 =$2046; - mmGRBM_SCRATCH_REG7 =$2047; - mmCP_CPC_STATUS =$2084; - mmCP_CPC_BUSY_STAT =$2085; - mmCP_CPC_STALLED_STAT1 =$2086; - mmCP_CPF_STATUS =$2087; - mmCP_CPF_BUSY_STAT =$2088; - mmCP_CPF_STALLED_STAT1 =$2089; - mmCP_CPC_GRBM_FREE_COUNT =$208B; - mmCP_MEC_CNTL =$208D; - mmCP_MEC_ME1_HEADER_DUMP =$208E; - mmCP_MEC_ME2_HEADER_DUMP =$208F; - mmCP_CPC_SCRATCH_INDEX =$2090; - mmCP_CPC_SCRATCH_DATA =$2091; - mmCP_CPC_HALT_HYST_COUNT =$20A7; - mmCP_PRT_LOD_STATS_CNTL0 =$20AD; - mmCP_PRT_LOD_STATS_CNTL1 =$20AE; - mmCP_PRT_LOD_STATS_CNTL2 =$20AF; - mmCP_CE_COMPARE_COUNT =$20C0; - mmCP_CE_DE_COUNT =$20C1; - mmCP_DE_CE_COUNT =$20C2; - mmCP_DE_LAST_INVAL_COUNT =$20C3; - mmCP_DE_DE_COUNT =$20C4; - mmCP_STALLED_STAT3 =$219C; - mmCP_STALLED_STAT1 =$219D; - mmCP_STALLED_STAT2 =$219E; - mmCP_BUSY_STAT =$219F; - mmCP_STAT =$21A0; - mmCP_PFP_HEADER_DUMP =$21A2; - mmCP_GRBM_FREE_COUNT =$21A3; - mmCP_CE_HEADER_DUMP =$21A4; - mmCP_CSF_STAT =$21B4; - mmCP_CSF_CNTL =$21B5; - mmCP_CNTX_STAT =$21B8; - mmCP_ROQ_THRESHOLDS =$21BC; - mmCP_MEQ_STQ_THRESHOLD =$21BD; - mmCP_RB2_RPTR =$21BE; - mmCP_RB1_RPTR =$21BF; - mmCP_RB0_RPTR =$21C0; - mmCP_ROQ1_THRESHOLDS =$21D5; - mmCP_ROQ2_THRESHOLDS =$21D6; - mmCP_STQ_THRESHOLDS =$21D7; - mmCP_QUEUE_THRESHOLDS =$21D8; - mmCP_MEQ_THRESHOLDS =$21D9; - mmCP_ROQ_AVAIL =$21DA; - mmCP_STQ_AVAIL =$21DB; - mmCP_ROQ2_AVAIL =$21DC; - mmCP_MEQ_AVAIL =$21DD; - mmCP_CMD_INDEX =$21DE; - mmCP_CMD_DATA =$21DF; - mmCP_ROQ_RB_STAT =$21E0; - mmCP_ROQ_IB1_STAT =$21E1; - mmCP_ROQ_IB2_STAT =$21E2; - mmCP_STQ_STAT =$21E3; - mmCP_STQ_WR_STAT =$21E4; - mmCP_MEQ_STAT =$21E5; - mmCP_CEQ1_AVAIL =$21E6; - mmCP_CEQ2_AVAIL =$21E7; - mmCP_CE_ROQ_RB_STAT =$21E8; - mmCP_CE_ROQ_IB1_STAT =$21E9; - mmCP_CE_ROQ_IB2_STAT =$21EA; - mmCP_INT_STAT_DEBUG =$21F7; - mmVGT_VTX_VECT_EJECT_REG =$222C; - mmVGT_DMA_DATA_FIFO_DEPTH =$222D; - mmVGT_DMA_REQ_FIFO_DEPTH =$222E; - mmVGT_DRAW_INIT_FIFO_DEPTH =$222F; - mmVGT_LAST_COPY_STATE =$2230; - mmVGT_CACHE_INVALIDATION =$2231; - mmVGT_RESET_DEBUG =$2232; - mmVGT_STRMOUT_DELAY =$2233; - mmVGT_FIFO_DEPTHS =$2234; - mmVGT_GS_VERTEX_REUSE =$2235; - mmVGT_MC_LAT_CNTL =$2236; - mmIA_CNTL_STATUS =$2237; - mmVGT_DEBUG_CNTL =$2238; - mmVGT_DEBUG_DATA =$2239; - mmIA_DEBUG_CNTL =$223A; - mmIA_DEBUG_DATA =$223B; - mmVGT_CNTL_STATUS =$223C; - mmWD_DEBUG_CNTL =$223D; - mmWD_DEBUG_DATA =$223E; - mmWD_CNTL_STATUS =$223F; - mmWD_QOS =$2242; - mmVGT_SYS_CONFIG =$2263; - mmVGT_VS_MAX_WAVE_ID =$2268; - mmVGT_DMA_PRIMITIVE_TYPE =$2271; - mmVGT_DMA_CONTROL =$2272; - mmVGT_DMA_LS_HS_CONFIG =$2273; - mmPA_SU_DEBUG_CNTL =$2280; - mmPA_SU_DEBUG_DATA =$2281; - mmPA_CL_CNTL_STATUS =$2284; - mmPA_CL_ENHANCE =$2285; - mmPA_CL_RESET_DEBUG =$2286; - mmPA_SU_CNTL_STATUS =$2294; - mmPA_SC_FIFO_DEPTH_CNTL =$2295; - mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK =$22C0; - mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK =$22C1; - mmPA_SC_TRAP_SCREEN_HV_LOCK =$22C2; - mmPA_SC_FORCE_EOV_MAX_CNTS =$22C9; - mmPA_SC_FIFO_SIZE =$22F3; - mmPA_SC_IF_FIFO_SIZE =$22F5; - mmPA_SC_DEBUG_CNTL =$22F6; - mmPA_SC_DEBUG_DATA =$22F7; - mmPA_SC_ENHANCE =$22FC; - mmSQ_THREAD_TRACE_CNTR =$2390; - mmSQ_BUF_RSRC_WORD0 =$23C0; - mmSQ_BUF_RSRC_WORD1 =$23C1; - mmSQ_BUF_RSRC_WORD2 =$23C2; - mmSQ_BUF_RSRC_WORD3 =$23C3; - mmSQ_IMG_RSRC_WORD0 =$23C4; - mmSQ_IMG_RSRC_WORD1 =$23C5; - mmSQ_IMG_RSRC_WORD2 =$23C6; - mmSQ_IMG_RSRC_WORD3 =$23C7; - mmSQ_IMG_RSRC_WORD4 =$23C8; - mmSQ_IMG_RSRC_WORD5 =$23C9; - mmSQ_IMG_RSRC_WORD6 =$23CA; - mmSQ_IMG_RSRC_WORD7 =$23CB; - mmSQ_IMG_SAMP_WORD0 =$23CC; - mmSQ_IMG_SAMP_WORD1 =$23CD; - mmSQ_IMG_SAMP_WORD2 =$23CE; - mmSQ_IMG_SAMP_WORD3 =$23CF; - mmSX_DEBUG_BUSY =$2414; - mmSX_DEBUG_BUSY_2 =$2415; - mmSX_DEBUG_BUSY_3 =$2416; - mmSX_DEBUG_BUSY_4 =$2417; - mmSX_DEBUG_1 =$2418; - mmSPI_PS_MAX_WAVE_ID =$243A; - mmSPI_START_PHASE =$243B; - mmSPI_GFX_CNTL =$243C; - mmSPI_CONFIG_CNTL =$2440; - mmSPI_DEBUG_CNTL =$2441; - mmSPI_DEBUG_READ =$2442; - mmSPI_DSM_CNTL =$2443; - mmSPI_EDC_CNT =$2444; - mmSPI_CONFIG_CNTL_1 =$244F; - mmSPI_DEBUG_BUSY =$2450; - mmSPI_CONFIG_CNTL_2 =$2451; - mmSPI_WF_LIFETIME_CNTL =$24AA; - mmSPI_WF_LIFETIME_LIMIT_0 =$24AB; - mmSPI_WF_LIFETIME_LIMIT_1 =$24AC; - mmSPI_WF_LIFETIME_LIMIT_2 =$24AD; - mmSPI_WF_LIFETIME_LIMIT_3 =$24AE; - mmSPI_WF_LIFETIME_LIMIT_4 =$24AF; - mmSPI_WF_LIFETIME_LIMIT_5 =$24B0; - mmSPI_WF_LIFETIME_LIMIT_6 =$24B1; - mmSPI_WF_LIFETIME_LIMIT_7 =$24B2; - mmSPI_WF_LIFETIME_LIMIT_8 =$24B3; - mmSPI_WF_LIFETIME_LIMIT_9 =$24B4; - mmSPI_WF_LIFETIME_STATUS_0 =$24B5; - mmSPI_WF_LIFETIME_STATUS_1 =$24B6; - mmSPI_WF_LIFETIME_STATUS_2 =$24B7; - mmSPI_WF_LIFETIME_STATUS_3 =$24B8; - mmSPI_WF_LIFETIME_STATUS_4 =$24B9; - mmSPI_WF_LIFETIME_STATUS_5 =$24BA; - mmSPI_WF_LIFETIME_STATUS_6 =$24BB; - mmSPI_WF_LIFETIME_STATUS_7 =$24BC; - mmSPI_WF_LIFETIME_STATUS_8 =$24BD; - mmSPI_WF_LIFETIME_STATUS_9 =$24BE; - mmSPI_WF_LIFETIME_STATUS_10 =$24BF; - mmSPI_WF_LIFETIME_STATUS_11 =$24C0; - mmSPI_WF_LIFETIME_STATUS_12 =$24C1; - mmSPI_WF_LIFETIME_STATUS_13 =$24C2; - mmSPI_WF_LIFETIME_STATUS_14 =$24C3; - mmSPI_WF_LIFETIME_STATUS_15 =$24C4; - mmSPI_WF_LIFETIME_STATUS_16 =$24C5; - mmSPI_WF_LIFETIME_STATUS_17 =$24C6; - mmSPI_WF_LIFETIME_STATUS_18 =$24C7; - mmSPI_WF_LIFETIME_STATUS_19 =$24C8; - mmSPI_WF_LIFETIME_STATUS_20 =$24C9; - mmSPI_WF_LIFETIME_DEBUG =$24CA; - mmSPI_SLAVE_DEBUG_BUSY =$24D3; - mmSPI_LB_CTR_CTRL =$24D4; - mmSPI_LB_CU_MASK =$24D5; - mmSPI_LB_DATA_REG =$24D6; - mmSPI_PG_ENABLE_STATIC_CU_MASK =$24D7; - mmSPI_GDS_CREDITS =$24D8; - mmSPI_SX_EXPORT_BUFFER_SIZES =$24D9; - mmSPI_SX_SCOREBOARD_BUFFER_SIZES =$24DA; - mmSPI_CSQ_WF_ACTIVE_STATUS =$24DB; - mmSPI_CSQ_WF_ACTIVE_COUNT_0 =$24DC; - mmSPI_CSQ_WF_ACTIVE_COUNT_1 =$24DD; - mmSPI_CSQ_WF_ACTIVE_COUNT_2 =$24DE; - mmSPI_CSQ_WF_ACTIVE_COUNT_3 =$24DF; - mmSPI_CSQ_WF_ACTIVE_COUNT_4 =$24E0; - mmSPI_CSQ_WF_ACTIVE_COUNT_5 =$24E1; - mmSPI_CSQ_WF_ACTIVE_COUNT_6 =$24E2; - mmSPI_CSQ_WF_ACTIVE_COUNT_7 =$24E3; - mmSPI_P0_TRAP_SCREEN_PSBA_LO =$24EC; - mmSPI_P0_TRAP_SCREEN_PSBA_HI =$24ED; - mmSPI_P0_TRAP_SCREEN_PSMA_LO =$24EE; - mmSPI_P0_TRAP_SCREEN_PSMA_HI =$24EF; - mmSPI_P0_TRAP_SCREEN_GPR_MIN =$24F0; - mmSPI_P1_TRAP_SCREEN_PSBA_LO =$24F1; - mmSPI_P1_TRAP_SCREEN_PSBA_HI =$24F2; - mmSPI_P1_TRAP_SCREEN_PSMA_LO =$24F3; - mmSPI_P1_TRAP_SCREEN_PSMA_HI =$24F4; - mmSPI_P1_TRAP_SCREEN_GPR_MIN =$24F5; - mmTD_CNTL =$2525; - mmTD_STATUS =$2526; - mmTD_DEBUG_INDEX =$2528; - mmTD_DEBUG_DATA =$2529; - mmTD_DSM_CNTL =$252F; - mmTD_SCRATCH =$2533; - mmTA_CNTL =$2541; - mmTA_CNTL_AUX =$2542; - mmTA_RESERVED_010C =$2543; - mmTA_STATUS =$2548; - mmTA_DEBUG_INDEX =$254C; - mmTA_DEBUG_DATA =$254D; - mmTA_SCRATCH =$2564; - mmGDS_CONFIG =$25C0; - mmGDS_CNTL_STATUS =$25C1; - mmGDS_ENHANCE2 =$25C2; - mmGDS_PROTECTION_FAULT =$25C3; - mmGDS_VM_PROTECTION_FAULT =$25C4; - mmGDS_EDC_CNT =$25C5; - mmGDS_EDC_GRBM_CNT =$25C6; - mmGDS_EDC_OA_DED =$25C7; - mmGDS_DEBUG_CNTL =$25C8; - mmGDS_DEBUG_DATA =$25C9; - mmGDS_DSM_CNTL =$25CA; - mmDB_DEBUG =$260C; - mmDB_DEBUG2 =$260D; - mmDB_DEBUG3 =$260E; - mmDB_DEBUG4 =$260F; - mmDB_CREDIT_LIMIT =$2614; - mmDB_WATERMARKS =$2615; - mmDB_SUBTILE_CONTROL =$2616; - mmDB_FREE_CACHELINES =$2617; - mmDB_FIFO_DEPTH1 =$2618; - mmDB_FIFO_DEPTH2 =$2619; - mmDB_RING_CONTROL =$261B; - mmDB_READ_DEBUG_0 =$2620; - mmDB_READ_DEBUG_1 =$2621; - mmDB_READ_DEBUG_2 =$2622; - mmDB_READ_DEBUG_3 =$2623; - mmDB_READ_DEBUG_4 =$2624; - mmDB_READ_DEBUG_5 =$2625; - mmDB_READ_DEBUG_6 =$2626; - mmDB_READ_DEBUG_7 =$2627; - mmDB_READ_DEBUG_8 =$2628; - mmDB_READ_DEBUG_9 =$2629; - mmDB_READ_DEBUG_A =$262A; - mmDB_READ_DEBUG_B =$262B; - mmDB_READ_DEBUG_C =$262C; - mmDB_READ_DEBUG_D =$262D; - mmDB_READ_DEBUG_E =$262E; - mmDB_READ_DEBUG_F =$262F; - mmCB_HW_CONTROL_3 =$2683; - mmCB_HW_CONTROL =$2684; - mmCB_HW_CONTROL_1 =$2685; - mmCB_HW_CONTROL_2 =$2686; - mmCB_DCC_CONFIG =$2687; - mmCB_DEBUG_BUS_1 =$2699; - mmCB_DEBUG_BUS_2 =$269A; - mmCB_DEBUG_BUS_13 =$26A5; - mmCB_DEBUG_BUS_14 =$26A6; - mmCB_DEBUG_BUS_15 =$26A7; - mmCB_DEBUG_BUS_16 =$26A8; - mmCB_DEBUG_BUS_17 =$26A9; - mmCB_DEBUG_BUS_18 =$26AA; - mmCB_DEBUG_BUS_19 =$26AB; - mmCB_DEBUG_BUS_20 =$26AC; - mmCB_DEBUG_BUS_21 =$26AD; - mmCB_DEBUG_BUS_22 =$26AE; - mmTCP_INVALIDATE =$2B00; - mmTCP_STATUS =$2B01; - mmTCP_CNTL =$2B02; - mmTCP_CHAN_STEER_LO =$2B03; - mmTCP_CHAN_STEER_HI =$2B04; - mmTCP_ADDR_CONFIG =$2B05; - mmTCP_CREDIT =$2B06; - mmTCP_BUFFER_ADDR_HASH_CNTL =$2B16; - mmTCP_EDC_CNT =$2B17; - mmTCC_CTRL =$2B80; - mmTCC_EDC_CNT =$2B82; - mmTCC_REDUNDANCY =$2B83; - mmTCC_EXE_DISABLE =$2B84; - mmTCC_DSM_CNTL =$2B85; - mmTCA_CTRL =$2BC0; - mmSPI_SHADER_TBA_LO_PS =$2C00; - mmSPI_SHADER_TBA_HI_PS =$2C01; - mmSPI_SHADER_TMA_LO_PS =$2C02; - mmSPI_SHADER_TMA_HI_PS =$2C03; - mmSPI_SHADER_PGM_RSRC3_PS =$2C07; - mmSPI_SHADER_PGM_LO_PS =$2C08; - mmSPI_SHADER_PGM_HI_PS =$2C09; - mmSPI_SHADER_PGM_RSRC1_PS =$2C0A; - mmSPI_SHADER_PGM_RSRC2_PS =$2C0B; - mmSPI_SHADER_USER_DATA_PS_0 =$2C0C; - mmSPI_SHADER_USER_DATA_PS_1 =$2C0D; - mmSPI_SHADER_USER_DATA_PS_2 =$2C0E; - mmSPI_SHADER_USER_DATA_PS_3 =$2C0F; - mmSPI_SHADER_USER_DATA_PS_4 =$2C10; - mmSPI_SHADER_USER_DATA_PS_5 =$2C11; - mmSPI_SHADER_USER_DATA_PS_6 =$2C12; - mmSPI_SHADER_USER_DATA_PS_7 =$2C13; - mmSPI_SHADER_USER_DATA_PS_8 =$2C14; - mmSPI_SHADER_USER_DATA_PS_9 =$2C15; - mmSPI_SHADER_USER_DATA_PS_10 =$2C16; - mmSPI_SHADER_USER_DATA_PS_11 =$2C17; - mmSPI_SHADER_USER_DATA_PS_12 =$2C18; - mmSPI_SHADER_USER_DATA_PS_13 =$2C19; - mmSPI_SHADER_USER_DATA_PS_14 =$2C1A; - mmSPI_SHADER_USER_DATA_PS_15 =$2C1B; - mmSPI_SHADER_TBA_LO_VS =$2C40; - mmSPI_SHADER_TBA_HI_VS =$2C41; - mmSPI_SHADER_TMA_LO_VS =$2C42; - mmSPI_SHADER_TMA_HI_VS =$2C43; - mmSPI_SHADER_PGM_RSRC3_VS =$2C46; - mmSPI_SHADER_LATE_ALLOC_VS =$2C47; - mmSPI_SHADER_PGM_LO_VS =$2C48; - mmSPI_SHADER_PGM_HI_VS =$2C49; - mmSPI_SHADER_PGM_RSRC1_VS =$2C4A; - mmSPI_SHADER_PGM_RSRC2_VS =$2C4B; - mmSPI_SHADER_USER_DATA_VS_0 =$2C4C; - mmSPI_SHADER_USER_DATA_VS_1 =$2C4D; - mmSPI_SHADER_USER_DATA_VS_2 =$2C4E; - mmSPI_SHADER_USER_DATA_VS_3 =$2C4F; - mmSPI_SHADER_USER_DATA_VS_4 =$2C50; - mmSPI_SHADER_USER_DATA_VS_5 =$2C51; - mmSPI_SHADER_USER_DATA_VS_6 =$2C52; - mmSPI_SHADER_USER_DATA_VS_7 =$2C53; - mmSPI_SHADER_USER_DATA_VS_8 =$2C54; - mmSPI_SHADER_USER_DATA_VS_9 =$2C55; - mmSPI_SHADER_USER_DATA_VS_10 =$2C56; - mmSPI_SHADER_USER_DATA_VS_11 =$2C57; - mmSPI_SHADER_USER_DATA_VS_12 =$2C58; - mmSPI_SHADER_USER_DATA_VS_13 =$2C59; - mmSPI_SHADER_USER_DATA_VS_14 =$2C5A; - mmSPI_SHADER_USER_DATA_VS_15 =$2C5B; - mmSPI_SHADER_PGM_RSRC2_ES_VS =$2C7C; - mmSPI_SHADER_PGM_RSRC2_LS_VS =$2C7D; - mmSPI_SHADER_TBA_LO_GS =$2C80; - mmSPI_SHADER_TBA_HI_GS =$2C81; - mmSPI_SHADER_TMA_LO_GS =$2C82; - mmSPI_SHADER_TMA_HI_GS =$2C83; - mmSPI_SHADER_PGM_RSRC3_GS =$2C87; - mmSPI_SHADER_PGM_LO_GS =$2C88; - mmSPI_SHADER_PGM_HI_GS =$2C89; - mmSPI_SHADER_PGM_RSRC1_GS =$2C8A; - mmSPI_SHADER_PGM_RSRC2_GS =$2C8B; - mmSPI_SHADER_USER_DATA_GS_0 =$2C8C; - mmSPI_SHADER_USER_DATA_GS_1 =$2C8D; - mmSPI_SHADER_USER_DATA_GS_2 =$2C8E; - mmSPI_SHADER_USER_DATA_GS_3 =$2C8F; - mmSPI_SHADER_USER_DATA_GS_4 =$2C90; - mmSPI_SHADER_USER_DATA_GS_5 =$2C91; - mmSPI_SHADER_USER_DATA_GS_6 =$2C92; - mmSPI_SHADER_USER_DATA_GS_7 =$2C93; - mmSPI_SHADER_USER_DATA_GS_8 =$2C94; - mmSPI_SHADER_USER_DATA_GS_9 =$2C95; - mmSPI_SHADER_USER_DATA_GS_10 =$2C96; - mmSPI_SHADER_USER_DATA_GS_11 =$2C97; - mmSPI_SHADER_USER_DATA_GS_12 =$2C98; - mmSPI_SHADER_USER_DATA_GS_13 =$2C99; - mmSPI_SHADER_USER_DATA_GS_14 =$2C9A; - mmSPI_SHADER_USER_DATA_GS_15 =$2C9B; - mmSPI_SHADER_PGM_RSRC2_ES_GS =$2CBC; - mmSPI_SHADER_TBA_LO_ES =$2CC0; - mmSPI_SHADER_TBA_HI_ES =$2CC1; - mmSPI_SHADER_TMA_LO_ES =$2CC2; - mmSPI_SHADER_TMA_HI_ES =$2CC3; - mmSPI_SHADER_PGM_RSRC3_ES =$2CC7; - mmSPI_SHADER_PGM_LO_ES =$2CC8; - mmSPI_SHADER_PGM_HI_ES =$2CC9; - mmSPI_SHADER_PGM_RSRC1_ES =$2CCA; - mmSPI_SHADER_PGM_RSRC2_ES =$2CCB; - mmSPI_SHADER_USER_DATA_ES_0 =$2CCC; - mmSPI_SHADER_USER_DATA_ES_1 =$2CCD; - mmSPI_SHADER_USER_DATA_ES_2 =$2CCE; - mmSPI_SHADER_USER_DATA_ES_3 =$2CCF; - mmSPI_SHADER_USER_DATA_ES_4 =$2CD0; - mmSPI_SHADER_USER_DATA_ES_5 =$2CD1; - mmSPI_SHADER_USER_DATA_ES_6 =$2CD2; - mmSPI_SHADER_USER_DATA_ES_7 =$2CD3; - mmSPI_SHADER_USER_DATA_ES_8 =$2CD4; - mmSPI_SHADER_USER_DATA_ES_9 =$2CD5; - mmSPI_SHADER_USER_DATA_ES_10 =$2CD6; - mmSPI_SHADER_USER_DATA_ES_11 =$2CD7; - mmSPI_SHADER_USER_DATA_ES_12 =$2CD8; - mmSPI_SHADER_USER_DATA_ES_13 =$2CD9; - mmSPI_SHADER_USER_DATA_ES_14 =$2CDA; - mmSPI_SHADER_USER_DATA_ES_15 =$2CDB; - mmSPI_SHADER_PGM_RSRC2_LS_ES =$2CFD; - mmSPI_SHADER_TBA_LO_HS =$2D00; - mmSPI_SHADER_TBA_HI_HS =$2D01; - mmSPI_SHADER_TMA_LO_HS =$2D02; - mmSPI_SHADER_TMA_HI_HS =$2D03; - mmSPI_SHADER_PGM_RSRC3_HS =$2D07; - mmSPI_SHADER_PGM_LO_HS =$2D08; - mmSPI_SHADER_PGM_HI_HS =$2D09; - mmSPI_SHADER_PGM_RSRC1_HS =$2D0A; - mmSPI_SHADER_PGM_RSRC2_HS =$2D0B; - mmSPI_SHADER_USER_DATA_HS_0 =$2D0C; - mmSPI_SHADER_USER_DATA_HS_1 =$2D0D; - mmSPI_SHADER_USER_DATA_HS_2 =$2D0E; - mmSPI_SHADER_USER_DATA_HS_3 =$2D0F; - mmSPI_SHADER_USER_DATA_HS_4 =$2D10; - mmSPI_SHADER_USER_DATA_HS_5 =$2D11; - mmSPI_SHADER_USER_DATA_HS_6 =$2D12; - mmSPI_SHADER_USER_DATA_HS_7 =$2D13; - mmSPI_SHADER_USER_DATA_HS_8 =$2D14; - mmSPI_SHADER_USER_DATA_HS_9 =$2D15; - mmSPI_SHADER_USER_DATA_HS_10 =$2D16; - mmSPI_SHADER_USER_DATA_HS_11 =$2D17; - mmSPI_SHADER_USER_DATA_HS_12 =$2D18; - mmSPI_SHADER_USER_DATA_HS_13 =$2D19; - mmSPI_SHADER_USER_DATA_HS_14 =$2D1A; - mmSPI_SHADER_USER_DATA_HS_15 =$2D1B; - mmSPI_SHADER_PGM_RSRC2_LS_HS =$2D3D; - mmSPI_SHADER_TBA_LO_LS =$2D40; - mmSPI_SHADER_TBA_HI_LS =$2D41; - mmSPI_SHADER_TMA_LO_LS =$2D42; - mmSPI_SHADER_TMA_HI_LS =$2D43; - mmSPI_SHADER_PGM_RSRC3_LS =$2D47; - mmSPI_SHADER_PGM_LO_LS =$2D48; - mmSPI_SHADER_PGM_HI_LS =$2D49; - mmSPI_SHADER_PGM_RSRC1_LS =$2D4A; - mmSPI_SHADER_PGM_RSRC2_LS =$2D4B; - mmSPI_SHADER_USER_DATA_LS_0 =$2D4C; - mmSPI_SHADER_USER_DATA_LS_1 =$2D4D; - mmSPI_SHADER_USER_DATA_LS_2 =$2D4E; - mmSPI_SHADER_USER_DATA_LS_3 =$2D4F; - mmSPI_SHADER_USER_DATA_LS_4 =$2D50; - mmSPI_SHADER_USER_DATA_LS_5 =$2D51; - mmSPI_SHADER_USER_DATA_LS_6 =$2D52; - mmSPI_SHADER_USER_DATA_LS_7 =$2D53; - mmSPI_SHADER_USER_DATA_LS_8 =$2D54; - mmSPI_SHADER_USER_DATA_LS_9 =$2D55; - mmSPI_SHADER_USER_DATA_LS_10 =$2D56; - mmSPI_SHADER_USER_DATA_LS_11 =$2D57; - mmSPI_SHADER_USER_DATA_LS_12 =$2D58; - mmSPI_SHADER_USER_DATA_LS_13 =$2D59; - mmSPI_SHADER_USER_DATA_LS_14 =$2D5A; - mmSPI_SHADER_USER_DATA_LS_15 =$2D5B; - mmCOMPUTE_DISPATCH_INITIATOR =$2E00; - mmCOMPUTE_DIM_X =$2E01; - mmCOMPUTE_DIM_Y =$2E02; - mmCOMPUTE_DIM_Z =$2E03; - mmCOMPUTE_START_X =$2E04; - mmCOMPUTE_START_Y =$2E05; - mmCOMPUTE_START_Z =$2E06; - mmCOMPUTE_NUM_THREAD_X =$2E07; - mmCOMPUTE_NUM_THREAD_Y =$2E08; - mmCOMPUTE_NUM_THREAD_Z =$2E09; - mmCOMPUTE_PIPELINESTAT_ENABLE =$2E0A; - mmCOMPUTE_PERFCOUNT_ENABLE =$2E0B; - mmCOMPUTE_PGM_LO =$2E0C; - mmCOMPUTE_PGM_HI =$2E0D; - mmCOMPUTE_TBA_LO =$2E0E; - mmCOMPUTE_TBA_HI =$2E0F; - mmCOMPUTE_TMA_LO =$2E10; - mmCOMPUTE_TMA_HI =$2E11; - mmCOMPUTE_PGM_RSRC1 =$2E12; - mmCOMPUTE_PGM_RSRC2 =$2E13; - mmCOMPUTE_VMID =$2E14; - mmCOMPUTE_RESOURCE_LIMITS =$2E15; - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 =$2E16; - mmCOMPUTE_STATIC_THREAD_MGMT_SE1 =$2E17; - mmCOMPUTE_TMPRING_SIZE =$2E18; - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 =$2E19; - mmCOMPUTE_STATIC_THREAD_MGMT_SE3 =$2E1A; - mmCOMPUTE_RESTART_X =$2E1B; - mmCOMPUTE_RESTART_Y =$2E1C; - mmCOMPUTE_RESTART_Z =$2E1D; - mmCOMPUTE_THREAD_TRACE_ENABLE =$2E1E; - mmCOMPUTE_MISC_RESERVED =$2E1F; - mmCOMPUTE_DISPATCH_ID =$2E20; - mmCOMPUTE_THREADGROUP_ID =$2E21; - mmCOMPUTE_RELAUNCH =$2E22; - mmCOMPUTE_WAVE_RESTORE_ADDR_LO =$2E23; - mmCOMPUTE_WAVE_RESTORE_ADDR_HI =$2E24; - mmCOMPUTE_WAVE_RESTORE_CONTROL =$2E25; - mmCOMPUTE_USER_DATA_0 =$2E40; - mmCOMPUTE_USER_DATA_1 =$2E41; - mmCOMPUTE_USER_DATA_2 =$2E42; - mmCOMPUTE_USER_DATA_3 =$2E43; - mmCOMPUTE_USER_DATA_4 =$2E44; - mmCOMPUTE_USER_DATA_5 =$2E45; - mmCOMPUTE_USER_DATA_6 =$2E46; - mmCOMPUTE_USER_DATA_7 =$2E47; - mmCOMPUTE_USER_DATA_8 =$2E48; - mmCOMPUTE_USER_DATA_9 =$2E49; - mmCOMPUTE_USER_DATA_10 =$2E4A; - mmCOMPUTE_USER_DATA_11 =$2E4B; - mmCOMPUTE_USER_DATA_12 =$2E4C; - mmCOMPUTE_USER_DATA_13 =$2E4D; - mmCOMPUTE_USER_DATA_14 =$2E4E; - mmCOMPUTE_USER_DATA_15 =$2E4F; - mmCOMPUTE_NOWHERE =$2E7F; - mmCP_DFY_CNTL =$3020; - mmCP_DFY_STAT =$3021; - mmCP_DFY_ADDR_HI =$3022; - mmCP_DFY_ADDR_LO =$3023; - mmCP_DFY_DATA_0 =$3024; - mmCP_DFY_DATA_1 =$3025; - mmCP_DFY_DATA_2 =$3026; - mmCP_DFY_DATA_3 =$3027; - mmCP_DFY_DATA_4 =$3028; - mmCP_DFY_DATA_5 =$3029; - mmCP_DFY_DATA_6 =$302A; - mmCP_DFY_DATA_7 =$302B; - mmCP_DFY_DATA_8 =$302C; - mmCP_DFY_DATA_9 =$302D; - mmCP_DFY_DATA_10 =$302E; - mmCP_DFY_DATA_11 =$302F; - mmCP_DFY_DATA_12 =$3030; - mmCP_DFY_DATA_13 =$3031; - mmCP_DFY_DATA_14 =$3032; - mmCP_DFY_DATA_15 =$3033; - mmCP_DFY_CMD =$3034; - mmCP_CPC_MGCG_SYNC_CNTL =$3036; - mmCP_VIRT_STATUS =$3038; - mmCP_RB0_BASE =$3040; - mmCP_RB0_CNTL =$3041; - mmCP_RB0_RPTR_ADDR =$3043; - mmCP_RB0_RPTR_ADDR_HI =$3044; - mmCP_RB0_WPTR =$3045; - mmCP_INT_CNTL =$3049; - mmCP_INT_STATUS =$304A; - mmCP_DEVICE_ID =$304B; - mmCP_ME0_PIPE_PRIORITY_CNTS =$304C; - mmCP_ME0_PIPE0_PRIORITY =$304D; - mmCP_ME0_PIPE1_PRIORITY =$304E; - mmCP_ME0_PIPE2_PRIORITY =$304F; - mmCP_ENDIAN_SWAP =$3050; - mmCP_ME0_PIPE0_VMID =$3052; - mmCP_ME0_PIPE1_VMID =$3053; - mmCP_MEC_DOORBELL_RANGE_LOWER =$305C; - mmCP_MEC_DOORBELL_RANGE_UPPER =$305D; - mmCP_RB1_BASE =$3060; - mmCP_RB1_CNTL =$3061; - mmCP_RB1_RPTR_ADDR =$3062; - mmCP_RB1_RPTR_ADDR_HI =$3063; - mmCP_RB1_WPTR =$3064; - mmCP_RB2_BASE =$3065; - mmCP_RB2_CNTL =$3066; - mmCP_RB2_RPTR_ADDR =$3067; - mmCP_RB2_RPTR_ADDR_HI =$3068; - mmCP_RB2_WPTR =$3069; - mmCP_INT_CNTL_RING0 =$306A; - mmCP_INT_CNTL_RING1 =$306B; - mmCP_INT_CNTL_RING2 =$306C; - mmCP_INT_STATUS_RING0 =$306D; - mmCP_INT_STATUS_RING1 =$306E; - mmCP_INT_STATUS_RING2 =$306F; - mmCP_PWR_CNTL =$3078; - mmCP_MEM_SLP_CNTL =$3079; - mmCP_ECC_FIRSTOCCURRENCE =$307A; - mmCP_ECC_FIRSTOCCURRENCE_RING0 =$307B; - mmCP_ECC_FIRSTOCCURRENCE_RING1 =$307C; - mmCP_ECC_FIRSTOCCURRENCE_RING2 =$307D; - mmCP_DEBUG =$307F; - mmCP_PQ_WPTR_POLL_CNTL =$3083; - mmCP_PQ_WPTR_POLL_CNTL1 =$3084; - mmCP_ME1_PIPE0_INT_CNTL =$3085; - mmCP_ME1_PIPE1_INT_CNTL =$3086; - mmCP_ME1_PIPE2_INT_CNTL =$3087; - mmCP_ME1_PIPE3_INT_CNTL =$3088; - mmCP_ME2_PIPE0_INT_CNTL =$3089; - mmCP_ME2_PIPE1_INT_CNTL =$308A; - mmCP_ME2_PIPE2_INT_CNTL =$308B; - mmCP_ME2_PIPE3_INT_CNTL =$308C; - mmCP_ME1_PIPE0_INT_STATUS =$308D; - mmCP_ME1_PIPE1_INT_STATUS =$308E; - mmCP_ME1_PIPE2_INT_STATUS =$308F; - mmCP_ME1_PIPE3_INT_STATUS =$3090; - mmCP_ME2_PIPE0_INT_STATUS =$3091; - mmCP_ME2_PIPE1_INT_STATUS =$3092; - mmCP_ME2_PIPE2_INT_STATUS =$3093; - mmCP_ME2_PIPE3_INT_STATUS =$3094; - mmCP_ME1_INT_STAT_DEBUG =$3095; - mmCP_ME2_INT_STAT_DEBUG =$3096; - mmCP_ME1_PIPE_PRIORITY_CNTS =$3099; - mmCP_ME1_PIPE0_PRIORITY =$309A; - mmCP_ME1_PIPE1_PRIORITY =$309B; - mmCP_ME1_PIPE2_PRIORITY =$309C; - mmCP_ME1_PIPE3_PRIORITY =$309D; - mmCP_ME2_PIPE_PRIORITY_CNTS =$309E; - mmCP_ME2_PIPE0_PRIORITY =$309F; - mmCP_ME2_PIPE1_PRIORITY =$30A0; - mmCP_ME2_PIPE2_PRIORITY =$30A1; - mmCP_ME2_PIPE3_PRIORITY =$30A2; - mmCP_CE_PRGRM_CNTR_START =$30A3; - mmCP_PFP_PRGRM_CNTR_START =$30A4; - mmCP_MEC1_PRGRM_CNTR_START =$30A6; - mmCP_MEC2_PRGRM_CNTR_START =$30A7; - mmCP_CE_INTR_ROUTINE_START =$30A8; - mmCP_PFP_INTR_ROUTINE_START =$30A9; - mmCP_MEC1_INTR_ROUTINE_START =$30AB; - mmCP_MEC2_INTR_ROUTINE_START =$30AC; - mmCP_CONTEXT_CNTL =$30AD; - mmCP_MAX_CONTEXT =$30AE; - mmCP_IQ_WAIT_TIME1 =$30AF; - mmCP_IQ_WAIT_TIME2 =$30B0; - mmCP_RB0_BASE_HI =$30B1; - mmCP_RB1_BASE_HI =$30B2; - mmCP_VMID_RESET =$30B3; - mmCPC_INT_CNTL =$30B4; - mmCPC_INT_STATUS =$30B5; - mmCP_VMID_PREEMPT =$30B6; - mmCPC_INT_CNTX_ID =$30B7; - mmCP_PQ_STATUS =$30B8; - mmCP_CPC_IC_BASE_LO =$30B9; - mmCP_CPC_IC_BASE_HI =$30BA; - mmCP_CPC_IC_BASE_CNTL =$30BB; - mmCP_CPC_IC_OP_CNTL =$30BC; - mmCP_MEC1_F32_INT_DIS =$30BD; - mmCP_MEC2_F32_INT_DIS =$30BE; - mmCP_VMID_STATUS =$30BF; - mmSPI_ARB_PRIORITY =$31C0; - mmSPI_ARB_CYCLES_0 =$31C1; - mmSPI_ARB_CYCLES_1 =$31C2; - mmSPI_CDBG_SYS_GFX =$31C3; - mmSPI_CDBG_SYS_HP3D =$31C4; - mmSPI_CDBG_SYS_CS0 =$31C5; - mmSPI_CDBG_SYS_CS1 =$31C6; - mmSPI_WCL_PIPE_PERCENT_GFX =$31C7; - mmSPI_WCL_PIPE_PERCENT_HP3D =$31C8; - mmSPI_WCL_PIPE_PERCENT_CS0 =$31C9; - mmSPI_WCL_PIPE_PERCENT_CS1 =$31CA; - mmSPI_WCL_PIPE_PERCENT_CS2 =$31CB; - mmSPI_WCL_PIPE_PERCENT_CS3 =$31CC; - mmSPI_WCL_PIPE_PERCENT_CS4 =$31CD; - mmSPI_WCL_PIPE_PERCENT_CS5 =$31CE; - mmSPI_WCL_PIPE_PERCENT_CS6 =$31CF; - mmSPI_WCL_PIPE_PERCENT_CS7 =$31D0; - mmSPI_GDBG_WAVE_CNTL =$31D1; - mmSPI_GDBG_TRAP_CONFIG =$31D2; - mmSPI_GDBG_TRAP_MASK =$31D3; - mmSPI_GDBG_TBA_LO =$31D4; - mmSPI_GDBG_TBA_HI =$31D5; - mmSPI_GDBG_TMA_LO =$31D6; - mmSPI_GDBG_TMA_HI =$31D7; - mmSPI_GDBG_TRAP_DATA0 =$31D8; - mmSPI_GDBG_TRAP_DATA1 =$31D9; - mmSPI_RESET_DEBUG =$31DA; - mmSPI_COMPUTE_QUEUE_RESET =$31DB; - mmSPI_RESOURCE_RESERVE_CU_0 =$31DC; - mmSPI_RESOURCE_RESERVE_CU_1 =$31DD; - mmSPI_RESOURCE_RESERVE_CU_2 =$31DE; - mmSPI_RESOURCE_RESERVE_CU_3 =$31DF; - mmSPI_RESOURCE_RESERVE_CU_4 =$31E0; - mmSPI_RESOURCE_RESERVE_CU_5 =$31E1; - mmSPI_RESOURCE_RESERVE_CU_6 =$31E2; - mmSPI_RESOURCE_RESERVE_CU_7 =$31E3; - mmSPI_RESOURCE_RESERVE_CU_8 =$31E4; - mmSPI_RESOURCE_RESERVE_CU_9 =$31E5; - mmSPI_RESOURCE_RESERVE_EN_CU_0 =$31E6; - mmSPI_RESOURCE_RESERVE_EN_CU_1 =$31E7; - mmSPI_RESOURCE_RESERVE_EN_CU_2 =$31E8; - mmSPI_RESOURCE_RESERVE_EN_CU_3 =$31E9; - mmSPI_RESOURCE_RESERVE_EN_CU_4 =$31EA; - mmSPI_RESOURCE_RESERVE_EN_CU_5 =$31EB; - mmSPI_RESOURCE_RESERVE_EN_CU_6 =$31EC; - mmSPI_RESOURCE_RESERVE_EN_CU_7 =$31ED; - mmSPI_RESOURCE_RESERVE_EN_CU_8 =$31EE; - mmSPI_RESOURCE_RESERVE_EN_CU_9 =$31EF; - mmSPI_RESOURCE_RESERVE_CU_10 =$31F0; - mmSPI_RESOURCE_RESERVE_CU_11 =$31F1; - mmSPI_RESOURCE_RESERVE_EN_CU_10 =$31F2; - mmSPI_RESOURCE_RESERVE_EN_CU_11 =$31F3; - mmSPI_RESOURCE_RESERVE_CU_12 =$31F4; - mmSPI_RESOURCE_RESERVE_CU_13 =$31F5; - mmSPI_RESOURCE_RESERVE_CU_14 =$31F6; - mmSPI_RESOURCE_RESERVE_CU_15 =$31F7; - mmSPI_RESOURCE_RESERVE_EN_CU_12 =$31F8; - mmSPI_RESOURCE_RESERVE_EN_CU_13 =$31F9; - mmSPI_RESOURCE_RESERVE_EN_CU_14 =$31FA; - mmSPI_RESOURCE_RESERVE_EN_CU_15 =$31FB; - mmSPI_COMPUTE_WF_CTX_SAVE =$31FC; - mmCP_HPD_ROQ_OFFSETS =$3240; - mmCP_HPD_STATUS0 =$3241; - mmCP_MQD_BASE_ADDR =$3245; - mmCP_MQD_BASE_ADDR_HI =$3246; - mmCP_HQD_ACTIVE =$3247; - mmCP_HQD_VMID =$3248; - mmCP_HQD_PERSISTENT_STATE =$3249; - mmCP_HQD_PIPE_PRIORITY =$324A; - mmCP_HQD_QUEUE_PRIORITY =$324B; - mmCP_HQD_QUANTUM =$324C; - mmCP_HQD_PQ_BASE =$324D; - mmCP_HQD_PQ_BASE_HI =$324E; - mmCP_HQD_PQ_RPTR =$324F; - mmCP_HQD_PQ_RPTR_REPORT_ADDR =$3250; - mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI =$3251; - mmCP_HQD_PQ_WPTR_POLL_ADDR =$3252; - mmCP_HQD_PQ_WPTR_POLL_ADDR_HI =$3253; - mmCP_HQD_PQ_DOORBELL_CONTROL =$3254; - mmCP_HQD_PQ_WPTR =$3255; - mmCP_HQD_PQ_CONTROL =$3256; - mmCP_HQD_IB_BASE_ADDR =$3257; - mmCP_HQD_IB_BASE_ADDR_HI =$3258; - mmCP_HQD_IB_RPTR =$3259; - mmCP_HQD_IB_CONTROL =$325A; - mmCP_HQD_IQ_TIMER =$325B; - mmCP_HQD_IQ_RPTR =$325C; - mmCP_HQD_DEQUEUE_REQUEST =$325D; - mmCP_HQD_OFFLOAD =$325E; - mmCP_HQD_SEMA_CMD =$325F; - mmCP_HQD_MSG_TYPE =$3260; - mmCP_HQD_ATOMIC0_PREOP_LO =$3261; - mmCP_HQD_ATOMIC0_PREOP_HI =$3262; - mmCP_HQD_ATOMIC1_PREOP_LO =$3263; - mmCP_HQD_ATOMIC1_PREOP_HI =$3264; - mmCP_HQD_HQ_STATUS0 =$3265; - mmCP_HQD_HQ_CONTROL0 =$3266; - mmCP_MQD_CONTROL =$3267; - mmCP_HQD_HQ_STATUS1 =$3268; - mmCP_HQD_HQ_CONTROL1 =$3269; - mmCP_HQD_EOP_BASE_ADDR =$326A; - mmCP_HQD_EOP_BASE_ADDR_HI =$326B; - mmCP_HQD_EOP_CONTROL =$326C; - mmCP_HQD_EOP_RPTR =$326D; - mmCP_HQD_EOP_WPTR =$326E; - mmCP_HQD_EOP_EVENTS =$326F; - mmCP_HQD_CTX_SAVE_BASE_ADDR_LO =$3270; - mmCP_HQD_CTX_SAVE_BASE_ADDR_HI =$3271; - mmCP_HQD_CTX_SAVE_CONTROL =$3272; - mmCP_HQD_CNTL_STACK_OFFSET =$3273; - mmCP_HQD_CNTL_STACK_SIZE =$3274; - mmCP_HQD_WG_STATE_OFFSET =$3275; - mmCP_HQD_CTX_SAVE_SIZE =$3276; - mmCP_HQD_GDS_RESOURCE_STATE =$3277; - mmCP_HQD_ERROR =$3278; - mmCP_HQD_EOP_WPTR_MEM =$3279; - mmCP_HQD_EOP_DONES =$327A; - mmTCP_WATCH0_ADDR_H =$32A0; - mmTCP_WATCH0_ADDR_L =$32A1; - mmTCP_WATCH0_CNTL =$32A2; - mmTCP_WATCH1_ADDR_H =$32A3; - mmTCP_WATCH1_ADDR_L =$32A4; - mmTCP_WATCH1_CNTL =$32A5; - mmTCP_WATCH2_ADDR_H =$32A6; - mmTCP_WATCH2_ADDR_L =$32A7; - mmTCP_WATCH2_CNTL =$32A8; - mmTCP_WATCH3_ADDR_H =$32A9; - mmTCP_WATCH3_ADDR_L =$32AA; - mmTCP_WATCH3_CNTL =$32AB; - mmTCP_GATCL1_CNTL =$32B0; - mmTCP_ATC_EDC_GATCL1_CNT =$32B1; - mmTCP_GATCL1_DSM_CNTL =$32B2; - mmTCP_DSM_CNTL =$32B3; - mmTCP_CNTL2 =$32B4; - mmGDS_VMID0_BASE =$3300; - mmGDS_VMID0_SIZE =$3301; - mmGDS_VMID1_BASE =$3302; - mmGDS_VMID1_SIZE =$3303; - mmGDS_VMID2_BASE =$3304; - mmGDS_VMID2_SIZE =$3305; - mmGDS_VMID3_BASE =$3306; - mmGDS_VMID3_SIZE =$3307; - mmGDS_VMID4_BASE =$3308; - mmGDS_VMID4_SIZE =$3309; - mmGDS_VMID5_BASE =$330A; - mmGDS_VMID5_SIZE =$330B; - mmGDS_VMID6_BASE =$330C; - mmGDS_VMID6_SIZE =$330D; - mmGDS_VMID7_BASE =$330E; - mmGDS_VMID7_SIZE =$330F; - mmGDS_VMID8_BASE =$3310; - mmGDS_VMID8_SIZE =$3311; - mmGDS_VMID9_BASE =$3312; - mmGDS_VMID9_SIZE =$3313; - mmGDS_VMID10_BASE =$3314; - mmGDS_VMID10_SIZE =$3315; - mmGDS_VMID11_BASE =$3316; - mmGDS_VMID11_SIZE =$3317; - mmGDS_VMID12_BASE =$3318; - mmGDS_VMID12_SIZE =$3319; - mmGDS_VMID13_BASE =$331A; - mmGDS_VMID13_SIZE =$331B; - mmGDS_VMID14_BASE =$331C; - mmGDS_VMID14_SIZE =$331D; - mmGDS_VMID15_BASE =$331E; - mmGDS_VMID15_SIZE =$331F; - mmGDS_GWS_VMID0 =$3320; - mmGDS_GWS_VMID1 =$3321; - mmGDS_GWS_VMID2 =$3322; - mmGDS_GWS_VMID3 =$3323; - mmGDS_GWS_VMID4 =$3324; - mmGDS_GWS_VMID5 =$3325; - mmGDS_GWS_VMID6 =$3326; - mmGDS_GWS_VMID7 =$3327; - mmGDS_GWS_VMID8 =$3328; - mmGDS_GWS_VMID9 =$3329; - mmGDS_GWS_VMID10 =$332A; - mmGDS_GWS_VMID11 =$332B; - mmGDS_GWS_VMID12 =$332C; - mmGDS_GWS_VMID13 =$332D; - mmGDS_GWS_VMID14 =$332E; - mmGDS_GWS_VMID15 =$332F; - mmGDS_OA_VMID0 =$3330; - mmGDS_OA_VMID1 =$3331; - mmGDS_OA_VMID2 =$3332; - mmGDS_OA_VMID3 =$3333; - mmGDS_OA_VMID4 =$3334; - mmGDS_OA_VMID5 =$3335; - mmGDS_OA_VMID6 =$3336; - mmGDS_OA_VMID7 =$3337; - mmGDS_OA_VMID8 =$3338; - mmGDS_OA_VMID9 =$3339; - mmGDS_OA_VMID10 =$333A; - mmGDS_OA_VMID11 =$333B; - mmGDS_OA_VMID12 =$333C; - mmGDS_OA_VMID13 =$333D; - mmGDS_OA_VMID14 =$333E; - mmGDS_OA_VMID15 =$333F; - mmGDS_GWS_RESET0 =$3344; - mmGDS_GWS_RESET1 =$3345; - mmGDS_GWS_RESOURCE_RESET =$3346; - mmGDS_COMPUTE_MAX_WAVE_ID =$3348; - mmGDS_OA_RESET_MASK =$3349; - mmGDS_OA_RESET =$334A; - mmGDS_ENHANCE =$334B; - mmGDS_OA_CGPG_RESTORE =$334C; - mmGDS_CS_CTXSW_STATUS =$334D; - mmGDS_CS_CTXSW_CNT0 =$334E; - mmGDS_CS_CTXSW_CNT1 =$334F; - mmGDS_CS_CTXSW_CNT2 =$3350; - mmGDS_CS_CTXSW_CNT3 =$3351; - mmGDS_GFX_CTXSW_STATUS =$3352; - mmGDS_VS_CTXSW_CNT0 =$3353; - mmGDS_VS_CTXSW_CNT1 =$3354; - mmGDS_VS_CTXSW_CNT2 =$3355; - mmGDS_VS_CTXSW_CNT3 =$3356; - mmGDS_PS0_CTXSW_CNT0 =$3357; - mmGDS_PS0_CTXSW_CNT1 =$3358; - mmGDS_PS0_CTXSW_CNT2 =$3359; - mmGDS_PS0_CTXSW_CNT3 =$335A; - mmGDS_PS1_CTXSW_CNT0 =$335B; - mmGDS_PS1_CTXSW_CNT1 =$335C; - mmGDS_PS1_CTXSW_CNT2 =$335D; - mmGDS_PS1_CTXSW_CNT3 =$335E; - mmGDS_PS2_CTXSW_CNT0 =$335F; - mmGDS_PS2_CTXSW_CNT1 =$3360; - mmGDS_PS2_CTXSW_CNT2 =$3361; - mmGDS_PS2_CTXSW_CNT3 =$3362; - mmGDS_PS3_CTXSW_CNT0 =$3363; - mmGDS_PS3_CTXSW_CNT1 =$3364; - mmGDS_PS3_CTXSW_CNT2 =$3365; - mmGDS_PS3_CTXSW_CNT3 =$3366; - mmGDS_PS4_CTXSW_CNT0 =$3367; - mmGDS_PS4_CTXSW_CNT1 =$3368; - mmGDS_PS4_CTXSW_CNT2 =$3369; - mmGDS_PS4_CTXSW_CNT3 =$336A; - mmGDS_PS5_CTXSW_CNT0 =$336B; - mmGDS_PS5_CTXSW_CNT1 =$336C; - mmGDS_PS5_CTXSW_CNT2 =$336D; - mmGDS_PS5_CTXSW_CNT3 =$336E; - mmGDS_PS6_CTXSW_CNT0 =$336F; - mmGDS_PS6_CTXSW_CNT1 =$3370; - mmGDS_PS6_CTXSW_CNT2 =$3371; - mmGDS_PS6_CTXSW_CNT3 =$3372; - mmGDS_PS7_CTXSW_CNT0 =$3373; - mmGDS_PS7_CTXSW_CNT1 =$3374; - mmGDS_PS7_CTXSW_CNT2 =$3375; - mmGDS_PS7_CTXSW_CNT3 =$3376; - mmDB_RENDER_CONTROL =$A000; - mmDB_COUNT_CONTROL =$A001; - mmDB_DEPTH_VIEW =$A002; - mmDB_RENDER_OVERRIDE =$A003; - mmDB_RENDER_OVERRIDE2 =$A004; - mmDB_HTILE_DATA_BASE =$A005; - mmDB_DEPTH_BOUNDS_MIN =$A008; - mmDB_DEPTH_BOUNDS_MAX =$A009; - mmDB_STENCIL_CLEAR =$A00A; - mmDB_DEPTH_CLEAR =$A00B; - mmPA_SC_SCREEN_SCISSOR_TL =$A00C; - mmPA_SC_SCREEN_SCISSOR_BR =$A00D; - mmDB_DEPTH_INFO =$A00F; - mmDB_Z_INFO =$A010; - mmDB_STENCIL_INFO =$A011; - mmDB_Z_READ_BASE =$A012; - mmDB_STENCIL_READ_BASE =$A013; - mmDB_Z_WRITE_BASE =$A014; - mmDB_STENCIL_WRITE_BASE =$A015; - mmDB_DEPTH_SIZE =$A016; - mmDB_DEPTH_SLICE =$A017; - mmTA_BC_BASE_ADDR =$A020; - mmTA_BC_BASE_ADDR_HI =$A021; - mmPA_SC_WINDOW_OFFSET =$A080; - mmPA_SC_WINDOW_SCISSOR_TL =$A081; - mmPA_SC_WINDOW_SCISSOR_BR =$A082; - mmPA_SC_CLIPRECT_RULE =$A083; - mmPA_SC_CLIPRECT_0_TL =$A084; - mmPA_SC_CLIPRECT_0_BR =$A085; - mmPA_SC_CLIPRECT_1_TL =$A086; - mmPA_SC_CLIPRECT_1_BR =$A087; - mmPA_SC_CLIPRECT_2_TL =$A088; - mmPA_SC_CLIPRECT_2_BR =$A089; - mmPA_SC_CLIPRECT_3_TL =$A08A; - mmPA_SC_CLIPRECT_3_BR =$A08B; - mmPA_SC_EDGERULE =$A08C; - mmPA_SU_HARDWARE_SCREEN_OFFSET =$A08D; - mmCB_TARGET_MASK =$A08E; - mmCB_SHADER_MASK =$A08F; - mmPA_SC_GENERIC_SCISSOR_TL =$A090; - mmPA_SC_GENERIC_SCISSOR_BR =$A091; - mmPA_SC_VPORT_SCISSOR_0_TL =$A094; - mmPA_SC_VPORT_SCISSOR_0_BR =$A095; - mmPA_SC_VPORT_SCISSOR_1_TL =$A096; - mmPA_SC_VPORT_SCISSOR_1_BR =$A097; - mmPA_SC_VPORT_SCISSOR_2_TL =$A098; - mmPA_SC_VPORT_SCISSOR_2_BR =$A099; - mmPA_SC_VPORT_SCISSOR_3_TL =$A09A; - mmPA_SC_VPORT_SCISSOR_3_BR =$A09B; - mmPA_SC_VPORT_SCISSOR_4_TL =$A09C; - mmPA_SC_VPORT_SCISSOR_4_BR =$A09D; - mmPA_SC_VPORT_SCISSOR_5_TL =$A09E; - mmPA_SC_VPORT_SCISSOR_5_BR =$A09F; - mmPA_SC_VPORT_SCISSOR_6_TL =$A0A0; - mmPA_SC_VPORT_SCISSOR_6_BR =$A0A1; - mmPA_SC_VPORT_SCISSOR_7_TL =$A0A2; - mmPA_SC_VPORT_SCISSOR_7_BR =$A0A3; - mmPA_SC_VPORT_SCISSOR_8_TL =$A0A4; - mmPA_SC_VPORT_SCISSOR_8_BR =$A0A5; - mmPA_SC_VPORT_SCISSOR_9_TL =$A0A6; - mmPA_SC_VPORT_SCISSOR_9_BR =$A0A7; - mmPA_SC_VPORT_SCISSOR_10_TL =$A0A8; - mmPA_SC_VPORT_SCISSOR_10_BR =$A0A9; - mmPA_SC_VPORT_SCISSOR_11_TL =$A0AA; - mmPA_SC_VPORT_SCISSOR_11_BR =$A0AB; - mmPA_SC_VPORT_SCISSOR_12_TL =$A0AC; - mmPA_SC_VPORT_SCISSOR_12_BR =$A0AD; - mmPA_SC_VPORT_SCISSOR_13_TL =$A0AE; - mmPA_SC_VPORT_SCISSOR_13_BR =$A0AF; - mmPA_SC_VPORT_SCISSOR_14_TL =$A0B0; - mmPA_SC_VPORT_SCISSOR_14_BR =$A0B1; - mmPA_SC_VPORT_SCISSOR_15_TL =$A0B2; - mmPA_SC_VPORT_SCISSOR_15_BR =$A0B3; - mmPA_SC_VPORT_ZMIN_0 =$A0B4; - mmPA_SC_VPORT_ZMAX_0 =$A0B5; - mmPA_SC_VPORT_ZMIN_1 =$A0B6; - mmPA_SC_VPORT_ZMAX_1 =$A0B7; - mmPA_SC_VPORT_ZMIN_2 =$A0B8; - mmPA_SC_VPORT_ZMAX_2 =$A0B9; - mmPA_SC_VPORT_ZMIN_3 =$A0BA; - mmPA_SC_VPORT_ZMAX_3 =$A0BB; - mmPA_SC_VPORT_ZMIN_4 =$A0BC; - mmPA_SC_VPORT_ZMAX_4 =$A0BD; - mmPA_SC_VPORT_ZMIN_5 =$A0BE; - mmPA_SC_VPORT_ZMAX_5 =$A0BF; - mmPA_SC_VPORT_ZMIN_6 =$A0C0; - mmPA_SC_VPORT_ZMAX_6 =$A0C1; - mmPA_SC_VPORT_ZMIN_7 =$A0C2; - mmPA_SC_VPORT_ZMAX_7 =$A0C3; - mmPA_SC_VPORT_ZMIN_8 =$A0C4; - mmPA_SC_VPORT_ZMAX_8 =$A0C5; - mmPA_SC_VPORT_ZMIN_9 =$A0C6; - mmPA_SC_VPORT_ZMAX_9 =$A0C7; - mmPA_SC_VPORT_ZMIN_10 =$A0C8; - mmPA_SC_VPORT_ZMAX_10 =$A0C9; - mmPA_SC_VPORT_ZMIN_11 =$A0CA; - mmPA_SC_VPORT_ZMAX_11 =$A0CB; - mmPA_SC_VPORT_ZMIN_12 =$A0CC; - mmPA_SC_VPORT_ZMAX_12 =$A0CD; - mmPA_SC_VPORT_ZMIN_13 =$A0CE; - mmPA_SC_VPORT_ZMAX_13 =$A0CF; - mmPA_SC_VPORT_ZMIN_14 =$A0D0; - mmPA_SC_VPORT_ZMAX_14 =$A0D1; - mmPA_SC_VPORT_ZMIN_15 =$A0D2; - mmPA_SC_VPORT_ZMAX_15 =$A0D3; - mmPA_SC_RASTER_CONFIG =$A0D4; - mmPA_SC_RASTER_CONFIG_1 =$A0D5; - mmCP_PERFMON_CNTX_CNTL =$A0D8; - mmCP_PIPEID =$A0D9; - mmCP_VMID =$A0DA; - mmVGT_MAX_VTX_INDX =$A100; - mmVGT_MIN_VTX_INDX =$A101; - mmVGT_INDX_OFFSET =$A102; - mmVGT_MULTI_PRIM_IB_RESET_INDX =$A103; - mmCB_BLEND_RED =$A105; - mmCB_BLEND_GREEN =$A106; - mmCB_BLEND_BLUE =$A107; - mmCB_BLEND_ALPHA =$A108; - mmCB_DCC_CONTROL =$A109; - mmDB_STENCIL_CONTROL =$A10B; - mmDB_STENCILREFMASK =$A10C; - mmDB_STENCILREFMASK_BF =$A10D; - mmPA_CL_VPORT_XSCALE =$A10F; - mmPA_CL_VPORT_XOFFSET =$A110; - mmPA_CL_VPORT_YSCALE =$A111; - mmPA_CL_VPORT_YOFFSET =$A112; - mmPA_CL_VPORT_ZSCALE =$A113; - mmPA_CL_VPORT_ZOFFSET =$A114; - mmPA_CL_VPORT_XSCALE_1 =$A115; - mmPA_CL_VPORT_XOFFSET_1 =$A116; - mmPA_CL_VPORT_YSCALE_1 =$A117; - mmPA_CL_VPORT_YOFFSET_1 =$A118; - mmPA_CL_VPORT_ZSCALE_1 =$A119; - mmPA_CL_VPORT_ZOFFSET_1 =$A11A; - mmPA_CL_VPORT_XSCALE_2 =$A11B; - mmPA_CL_VPORT_XOFFSET_2 =$A11C; - mmPA_CL_VPORT_YSCALE_2 =$A11D; - mmPA_CL_VPORT_YOFFSET_2 =$A11E; - mmPA_CL_VPORT_ZSCALE_2 =$A11F; - mmPA_CL_VPORT_ZOFFSET_2 =$A120; - mmPA_CL_VPORT_XSCALE_3 =$A121; - mmPA_CL_VPORT_XOFFSET_3 =$A122; - mmPA_CL_VPORT_YSCALE_3 =$A123; - mmPA_CL_VPORT_YOFFSET_3 =$A124; - mmPA_CL_VPORT_ZSCALE_3 =$A125; - mmPA_CL_VPORT_ZOFFSET_3 =$A126; - mmPA_CL_VPORT_XSCALE_4 =$A127; - mmPA_CL_VPORT_XOFFSET_4 =$A128; - mmPA_CL_VPORT_YSCALE_4 =$A129; - mmPA_CL_VPORT_YOFFSET_4 =$A12A; - mmPA_CL_VPORT_ZSCALE_4 =$A12B; - mmPA_CL_VPORT_ZOFFSET_4 =$A12C; - mmPA_CL_VPORT_XSCALE_5 =$A12D; - mmPA_CL_VPORT_XOFFSET_5 =$A12E; - mmPA_CL_VPORT_YSCALE_5 =$A12F; - mmPA_CL_VPORT_YOFFSET_5 =$A130; - mmPA_CL_VPORT_ZSCALE_5 =$A131; - mmPA_CL_VPORT_ZOFFSET_5 =$A132; - mmPA_CL_VPORT_XSCALE_6 =$A133; - mmPA_CL_VPORT_XOFFSET_6 =$A134; - mmPA_CL_VPORT_YSCALE_6 =$A135; - mmPA_CL_VPORT_YOFFSET_6 =$A136; - mmPA_CL_VPORT_ZSCALE_6 =$A137; - mmPA_CL_VPORT_ZOFFSET_6 =$A138; - mmPA_CL_VPORT_XSCALE_7 =$A139; - mmPA_CL_VPORT_XOFFSET_7 =$A13A; - mmPA_CL_VPORT_YSCALE_7 =$A13B; - mmPA_CL_VPORT_YOFFSET_7 =$A13C; - mmPA_CL_VPORT_ZSCALE_7 =$A13D; - mmPA_CL_VPORT_ZOFFSET_7 =$A13E; - mmPA_CL_VPORT_XSCALE_8 =$A13F; - mmPA_CL_VPORT_XOFFSET_8 =$A140; - mmPA_CL_VPORT_YSCALE_8 =$A141; - mmPA_CL_VPORT_YOFFSET_8 =$A142; - mmPA_CL_VPORT_ZSCALE_8 =$A143; - mmPA_CL_VPORT_ZOFFSET_8 =$A144; - mmPA_CL_VPORT_XSCALE_9 =$A145; - mmPA_CL_VPORT_XOFFSET_9 =$A146; - mmPA_CL_VPORT_YSCALE_9 =$A147; - mmPA_CL_VPORT_YOFFSET_9 =$A148; - mmPA_CL_VPORT_ZSCALE_9 =$A149; - mmPA_CL_VPORT_ZOFFSET_9 =$A14A; - mmPA_CL_VPORT_XSCALE_10 =$A14B; - mmPA_CL_VPORT_XOFFSET_10 =$A14C; - mmPA_CL_VPORT_YSCALE_10 =$A14D; - mmPA_CL_VPORT_YOFFSET_10 =$A14E; - mmPA_CL_VPORT_ZSCALE_10 =$A14F; - mmPA_CL_VPORT_ZOFFSET_10 =$A150; - mmPA_CL_VPORT_XSCALE_11 =$A151; - mmPA_CL_VPORT_XOFFSET_11 =$A152; - mmPA_CL_VPORT_YSCALE_11 =$A153; - mmPA_CL_VPORT_YOFFSET_11 =$A154; - mmPA_CL_VPORT_ZSCALE_11 =$A155; - mmPA_CL_VPORT_ZOFFSET_11 =$A156; - mmPA_CL_VPORT_XSCALE_12 =$A157; - mmPA_CL_VPORT_XOFFSET_12 =$A158; - mmPA_CL_VPORT_YSCALE_12 =$A159; - mmPA_CL_VPORT_YOFFSET_12 =$A15A; - mmPA_CL_VPORT_ZSCALE_12 =$A15B; - mmPA_CL_VPORT_ZOFFSET_12 =$A15C; - mmPA_CL_VPORT_XSCALE_13 =$A15D; - mmPA_CL_VPORT_XOFFSET_13 =$A15E; - mmPA_CL_VPORT_YSCALE_13 =$A15F; - mmPA_CL_VPORT_YOFFSET_13 =$A160; - mmPA_CL_VPORT_ZSCALE_13 =$A161; - mmPA_CL_VPORT_ZOFFSET_13 =$A162; - mmPA_CL_VPORT_XSCALE_14 =$A163; - mmPA_CL_VPORT_XOFFSET_14 =$A164; - mmPA_CL_VPORT_YSCALE_14 =$A165; - mmPA_CL_VPORT_YOFFSET_14 =$A166; - mmPA_CL_VPORT_ZSCALE_14 =$A167; - mmPA_CL_VPORT_ZOFFSET_14 =$A168; - mmPA_CL_VPORT_XSCALE_15 =$A169; - mmPA_CL_VPORT_XOFFSET_15 =$A16A; - mmPA_CL_VPORT_YSCALE_15 =$A16B; - mmPA_CL_VPORT_YOFFSET_15 =$A16C; - mmPA_CL_VPORT_ZSCALE_15 =$A16D; - mmPA_CL_VPORT_ZOFFSET_15 =$A16E; - mmPA_CL_UCP_0_X =$A16F; - mmPA_CL_UCP_0_Y =$A170; - mmPA_CL_UCP_0_Z =$A171; - mmPA_CL_UCP_0_W =$A172; - mmPA_CL_UCP_1_X =$A173; - mmPA_CL_UCP_1_Y =$A174; - mmPA_CL_UCP_1_Z =$A175; - mmPA_CL_UCP_1_W =$A176; - mmPA_CL_UCP_2_X =$A177; - mmPA_CL_UCP_2_Y =$A178; - mmPA_CL_UCP_2_Z =$A179; - mmPA_CL_UCP_2_W =$A17A; - mmPA_CL_UCP_3_X =$A17B; - mmPA_CL_UCP_3_Y =$A17C; - mmPA_CL_UCP_3_Z =$A17D; - mmPA_CL_UCP_3_W =$A17E; - mmPA_CL_UCP_4_X =$A17F; - mmPA_CL_UCP_4_Y =$A180; - mmPA_CL_UCP_4_Z =$A181; - mmPA_CL_UCP_4_W =$A182; - mmPA_CL_UCP_5_X =$A183; - mmPA_CL_UCP_5_Y =$A184; - mmPA_CL_UCP_5_Z =$A185; - mmPA_CL_UCP_5_W =$A186; - mmSPI_PS_INPUT_CNTL_0 =$A191; - mmSPI_PS_INPUT_CNTL_1 =$A192; - mmSPI_PS_INPUT_CNTL_2 =$A193; - mmSPI_PS_INPUT_CNTL_3 =$A194; - mmSPI_PS_INPUT_CNTL_4 =$A195; - mmSPI_PS_INPUT_CNTL_5 =$A196; - mmSPI_PS_INPUT_CNTL_6 =$A197; - mmSPI_PS_INPUT_CNTL_7 =$A198; - mmSPI_PS_INPUT_CNTL_8 =$A199; - mmSPI_PS_INPUT_CNTL_9 =$A19A; - mmSPI_PS_INPUT_CNTL_10 =$A19B; - mmSPI_PS_INPUT_CNTL_11 =$A19C; - mmSPI_PS_INPUT_CNTL_12 =$A19D; - mmSPI_PS_INPUT_CNTL_13 =$A19E; - mmSPI_PS_INPUT_CNTL_14 =$A19F; - mmSPI_PS_INPUT_CNTL_15 =$A1A0; - mmSPI_PS_INPUT_CNTL_16 =$A1A1; - mmSPI_PS_INPUT_CNTL_17 =$A1A2; - mmSPI_PS_INPUT_CNTL_18 =$A1A3; - mmSPI_PS_INPUT_CNTL_19 =$A1A4; - mmSPI_PS_INPUT_CNTL_20 =$A1A5; - mmSPI_PS_INPUT_CNTL_21 =$A1A6; - mmSPI_PS_INPUT_CNTL_22 =$A1A7; - mmSPI_PS_INPUT_CNTL_23 =$A1A8; - mmSPI_PS_INPUT_CNTL_24 =$A1A9; - mmSPI_PS_INPUT_CNTL_25 =$A1AA; - mmSPI_PS_INPUT_CNTL_26 =$A1AB; - mmSPI_PS_INPUT_CNTL_27 =$A1AC; - mmSPI_PS_INPUT_CNTL_28 =$A1AD; - mmSPI_PS_INPUT_CNTL_29 =$A1AE; - mmSPI_PS_INPUT_CNTL_30 =$A1AF; - mmSPI_PS_INPUT_CNTL_31 =$A1B0; - mmSPI_VS_OUT_CONFIG =$A1B1; - mmSPI_PS_INPUT_ENA =$A1B3; - mmSPI_PS_INPUT_ADDR =$A1B4; - mmSPI_INTERP_CONTROL_0 =$A1B5; - mmSPI_PS_IN_CONTROL =$A1B6; - mmSPI_BARYC_CNTL =$A1B8; - mmSPI_TMPRING_SIZE =$A1BA; - mmSPI_SHADER_POS_FORMAT =$A1C3; - mmSPI_SHADER_Z_FORMAT =$A1C4; - mmSPI_SHADER_COL_FORMAT =$A1C5; - mmSX_PS_DOWNCONVERT =$A1D5; - mmSX_BLEND_OPT_EPSILON =$A1D6; - mmSX_BLEND_OPT_CONTROL =$A1D7; - mmSX_MRT0_BLEND_OPT =$A1D8; - mmSX_MRT1_BLEND_OPT =$A1D9; - mmSX_MRT2_BLEND_OPT =$A1DA; - mmSX_MRT3_BLEND_OPT =$A1DB; - mmSX_MRT4_BLEND_OPT =$A1DC; - mmSX_MRT5_BLEND_OPT =$A1DD; - mmSX_MRT6_BLEND_OPT =$A1DE; - mmSX_MRT7_BLEND_OPT =$A1DF; - mmCB_BLEND0_CONTROL =$A1E0; - mmCB_BLEND1_CONTROL =$A1E1; - mmCB_BLEND2_CONTROL =$A1E2; - mmCB_BLEND3_CONTROL =$A1E3; - mmCB_BLEND4_CONTROL =$A1E4; - mmCB_BLEND5_CONTROL =$A1E5; - mmCB_BLEND6_CONTROL =$A1E6; - mmCB_BLEND7_CONTROL =$A1E7; - mmPA_CL_POINT_X_RAD =$A1F5; - mmPA_CL_POINT_Y_RAD =$A1F6; - mmPA_CL_POINT_SIZE =$A1F7; - mmPA_CL_POINT_CULL_RAD =$A1F8; - mmVGT_DMA_BASE_HI =$A1F9; - mmVGT_DMA_BASE =$A1FA; - mmVGT_DRAW_INITIATOR =$A1FC; - mmVGT_IMMED_DATA =$A1FD; - mmVGT_EVENT_ADDRESS_REG =$A1FE; - mmDB_DEPTH_CONTROL =$A200; - mmDB_EQAA =$A201; - mmCB_COLOR_CONTROL =$A202; - mmDB_SHADER_CONTROL =$A203; - mmPA_CL_CLIP_CNTL =$A204; - mmPA_SU_SC_MODE_CNTL =$A205; - mmPA_CL_VTE_CNTL =$A206; - mmPA_CL_VS_OUT_CNTL =$A207; - mmPA_CL_NANINF_CNTL =$A208; - mmPA_SU_LINE_STIPPLE_CNTL =$A209; - mmPA_SU_LINE_STIPPLE_SCALE =$A20A; - mmPA_SU_PRIM_FILTER_CNTL =$A20B; - mmPA_SU_POINT_SIZE =$A280; - mmPA_SU_POINT_MINMAX =$A281; - mmPA_SU_LINE_CNTL =$A282; - mmPA_SC_LINE_STIPPLE =$A283; - mmVGT_OUTPUT_PATH_CNTL =$A284; - mmVGT_HOS_CNTL =$A285; - mmVGT_HOS_MAX_TESS_LEVEL =$A286; - mmVGT_HOS_MIN_TESS_LEVEL =$A287; - mmVGT_HOS_REUSE_DEPTH =$A288; - mmVGT_GROUP_PRIM_TYPE =$A289; - mmVGT_GROUP_FIRST_DECR =$A28A; - mmVGT_GROUP_DECR =$A28B; - mmVGT_GROUP_VECT_0_CNTL =$A28C; - mmVGT_GROUP_VECT_1_CNTL =$A28D; - mmVGT_GROUP_VECT_0_FMT_CNTL =$A28E; - mmVGT_GROUP_VECT_1_FMT_CNTL =$A28F; - mmVGT_GS_MODE =$A290; - mmVGT_GS_ONCHIP_CNTL =$A291; - mmPA_SC_MODE_CNTL_0 =$A292; - mmPA_SC_MODE_CNTL_1 =$A293; - mmVGT_ENHANCE =$A294; - mmVGT_GS_PER_ES =$A295; - mmVGT_ES_PER_GS =$A296; - mmVGT_GS_PER_VS =$A297; - mmVGT_GSVS_RING_OFFSET_1 =$A298; - mmVGT_GSVS_RING_OFFSET_2 =$A299; - mmVGT_GSVS_RING_OFFSET_3 =$A29A; - mmVGT_GS_OUT_PRIM_TYPE =$A29B; - mmIA_ENHANCE =$A29C; - mmVGT_DMA_SIZE =$A29D; - mmVGT_DMA_MAX_SIZE =$A29E; - mmVGT_DMA_INDEX_TYPE =$A29F; - mmWD_ENHANCE =$A2A0; - mmVGT_PRIMITIVEID_EN =$A2A1; - mmVGT_DMA_NUM_INSTANCES =$A2A2; - mmVGT_PRIMITIVEID_RESET =$A2A3; - mmVGT_EVENT_INITIATOR =$A2A4; - mmVGT_MULTI_PRIM_IB_RESET_EN =$A2A5; - mmVGT_INSTANCE_STEP_RATE_0 =$A2A8; - mmVGT_INSTANCE_STEP_RATE_1 =$A2A9; - mmIA_MULTI_VGT_PARAM =$A2AA; - mmVGT_ESGS_RING_ITEMSIZE =$A2AB; - mmVGT_GSVS_RING_ITEMSIZE =$A2AC; - mmVGT_REUSE_OFF =$A2AD; - mmVGT_VTX_CNT_EN =$A2AE; - mmDB_HTILE_SURFACE =$A2AF; - mmDB_SRESULTS_COMPARE_STATE0 =$A2B0; - mmDB_SRESULTS_COMPARE_STATE1 =$A2B1; - mmDB_PRELOAD_CONTROL =$A2B2; - mmVGT_STRMOUT_BUFFER_SIZE_0 =$A2B4; - mmVGT_STRMOUT_VTX_STRIDE_0 =$A2B5; - mmVGT_STRMOUT_BUFFER_OFFSET_0 =$A2B7; - mmVGT_STRMOUT_BUFFER_SIZE_1 =$A2B8; - mmVGT_STRMOUT_VTX_STRIDE_1 =$A2B9; - mmVGT_STRMOUT_BUFFER_OFFSET_1 =$A2BB; - mmVGT_STRMOUT_BUFFER_SIZE_2 =$A2BC; - mmVGT_STRMOUT_VTX_STRIDE_2 =$A2BD; - mmVGT_STRMOUT_BUFFER_OFFSET_2 =$A2BF; - mmVGT_STRMOUT_BUFFER_SIZE_3 =$A2C0; - mmVGT_STRMOUT_VTX_STRIDE_3 =$A2C1; - mmVGT_STRMOUT_BUFFER_OFFSET_3 =$A2C3; - mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET =$A2CA; - mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE=$A2CB; - mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE =$A2CC; - mmVGT_GS_MAX_VERT_OUT =$A2CE; - mmVGT_TESS_DISTRIBUTION =$A2D4; - mmVGT_SHADER_STAGES_EN =$A2D5; - mmVGT_LS_HS_CONFIG =$A2D6; - mmVGT_GS_VERT_ITEMSIZE =$A2D7; - mmVGT_GS_VERT_ITEMSIZE_1 =$A2D8; - mmVGT_GS_VERT_ITEMSIZE_2 =$A2D9; - mmVGT_GS_VERT_ITEMSIZE_3 =$A2DA; - mmVGT_TF_PARAM =$A2DB; - mmDB_ALPHA_TO_MASK =$A2DC; - mmVGT_DISPATCH_DRAW_INDEX =$A2DD; - mmPA_SU_POLY_OFFSET_DB_FMT_CNTL =$A2DE; - mmPA_SU_POLY_OFFSET_CLAMP =$A2DF; - mmPA_SU_POLY_OFFSET_FRONT_SCALE =$A2E0; - mmPA_SU_POLY_OFFSET_FRONT_OFFSET =$A2E1; - mmPA_SU_POLY_OFFSET_BACK_SCALE =$A2E2; - mmPA_SU_POLY_OFFSET_BACK_OFFSET =$A2E3; - mmVGT_GS_INSTANCE_CNT =$A2E4; - mmVGT_STRMOUT_CONFIG =$A2E5; - mmVGT_STRMOUT_BUFFER_CONFIG =$A2E6; - mmPA_SC_CENTROID_PRIORITY_0 =$A2F5; - mmPA_SC_CENTROID_PRIORITY_1 =$A2F6; - mmPA_SC_LINE_CNTL =$A2F7; - mmPA_SC_AA_CONFIG =$A2F8; - mmPA_SU_VTX_CNTL =$A2F9; - mmPA_CL_GB_VERT_CLIP_ADJ =$A2FA; - mmPA_CL_GB_VERT_DISC_ADJ =$A2FB; - mmPA_CL_GB_HORZ_CLIP_ADJ =$A2FC; - mmPA_CL_GB_HORZ_DISC_ADJ =$A2FD; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 =$A2FE; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 =$A2FF; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 =$A300; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 =$A301; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 =$A302; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 =$A303; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 =$A304; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 =$A305; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 =$A306; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 =$A307; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 =$A308; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 =$A309; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 =$A30A; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 =$A30B; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 =$A30C; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 =$A30D; - mmPA_SC_AA_MASK_X0Y0_X1Y0 =$A30E; - mmPA_SC_AA_MASK_X0Y1_X1Y1 =$A30F; - mmVGT_VERTEX_REUSE_BLOCK_CNTL =$A316; - mmVGT_OUT_DEALLOC_CNTL =$A317; - mmCB_COLOR0_BASE =$A318; - mmCB_COLOR0_PITCH =$A319; - mmCB_COLOR0_SLICE =$A31A; - mmCB_COLOR0_VIEW =$A31B; - mmCB_COLOR0_INFO =$A31C; - mmCB_COLOR0_ATTRIB =$A31D; - mmCB_COLOR0_DCC_CONTROL =$A31E; - mmCB_COLOR0_CMASK =$A31F; - mmCB_COLOR0_CMASK_SLICE =$A320; - mmCB_COLOR0_FMASK =$A321; - mmCB_COLOR0_FMASK_SLICE =$A322; - mmCB_COLOR0_CLEAR_WORD0 =$A323; - mmCB_COLOR0_CLEAR_WORD1 =$A324; - mmCB_COLOR0_DCC_BASE =$A325; - mmCB_COLOR1_BASE =$A327; - mmCB_COLOR1_PITCH =$A328; - mmCB_COLOR1_SLICE =$A329; - mmCB_COLOR1_VIEW =$A32A; - mmCB_COLOR1_INFO =$A32B; - mmCB_COLOR1_ATTRIB =$A32C; - mmCB_COLOR1_DCC_CONTROL =$A32D; - mmCB_COLOR1_CMASK =$A32E; - mmCB_COLOR1_CMASK_SLICE =$A32F; - mmCB_COLOR1_FMASK =$A330; - mmCB_COLOR1_FMASK_SLICE =$A331; - mmCB_COLOR1_CLEAR_WORD0 =$A332; - mmCB_COLOR1_CLEAR_WORD1 =$A333; - mmCB_COLOR1_DCC_BASE =$A334; - mmCB_COLOR2_BASE =$A336; - mmCB_COLOR2_PITCH =$A337; - mmCB_COLOR2_SLICE =$A338; - mmCB_COLOR2_VIEW =$A339; - mmCB_COLOR2_INFO =$A33A; - mmCB_COLOR2_ATTRIB =$A33B; - mmCB_COLOR2_DCC_CONTROL =$A33C; - mmCB_COLOR2_CMASK =$A33D; - mmCB_COLOR2_CMASK_SLICE =$A33E; - mmCB_COLOR2_FMASK =$A33F; - mmCB_COLOR2_FMASK_SLICE =$A340; - mmCB_COLOR2_CLEAR_WORD0 =$A341; - mmCB_COLOR2_CLEAR_WORD1 =$A342; - mmCB_COLOR2_DCC_BASE =$A343; - mmCB_COLOR3_BASE =$A345; - mmCB_COLOR3_PITCH =$A346; - mmCB_COLOR3_SLICE =$A347; - mmCB_COLOR3_VIEW =$A348; - mmCB_COLOR3_INFO =$A349; - mmCB_COLOR3_ATTRIB =$A34A; - mmCB_COLOR3_DCC_CONTROL =$A34B; - mmCB_COLOR3_CMASK =$A34C; - mmCB_COLOR3_CMASK_SLICE =$A34D; - mmCB_COLOR3_FMASK =$A34E; - mmCB_COLOR3_FMASK_SLICE =$A34F; - mmCB_COLOR3_CLEAR_WORD0 =$A350; - mmCB_COLOR3_CLEAR_WORD1 =$A351; - mmCB_COLOR3_DCC_BASE =$A352; - mmCB_COLOR4_BASE =$A354; - mmCB_COLOR4_PITCH =$A355; - mmCB_COLOR4_SLICE =$A356; - mmCB_COLOR4_VIEW =$A357; - mmCB_COLOR4_INFO =$A358; - mmCB_COLOR4_ATTRIB =$A359; - mmCB_COLOR4_DCC_CONTROL =$A35A; - mmCB_COLOR4_CMASK =$A35B; - mmCB_COLOR4_CMASK_SLICE =$A35C; - mmCB_COLOR4_FMASK =$A35D; - mmCB_COLOR4_FMASK_SLICE =$A35E; - mmCB_COLOR4_CLEAR_WORD0 =$A35F; - mmCB_COLOR4_CLEAR_WORD1 =$A360; - mmCB_COLOR4_DCC_BASE =$A361; - mmCB_COLOR5_BASE =$A363; - mmCB_COLOR5_PITCH =$A364; - mmCB_COLOR5_SLICE =$A365; - mmCB_COLOR5_VIEW =$A366; - mmCB_COLOR5_INFO =$A367; - mmCB_COLOR5_ATTRIB =$A368; - mmCB_COLOR5_DCC_CONTROL =$A369; - mmCB_COLOR5_CMASK =$A36A; - mmCB_COLOR5_CMASK_SLICE =$A36B; - mmCB_COLOR5_FMASK =$A36C; - mmCB_COLOR5_FMASK_SLICE =$A36D; - mmCB_COLOR5_CLEAR_WORD0 =$A36E; - mmCB_COLOR5_CLEAR_WORD1 =$A36F; - mmCB_COLOR5_DCC_BASE =$A370; - mmCB_COLOR6_BASE =$A372; - mmCB_COLOR6_PITCH =$A373; - mmCB_COLOR6_SLICE =$A374; - mmCB_COLOR6_VIEW =$A375; - mmCB_COLOR6_INFO =$A376; - mmCB_COLOR6_ATTRIB =$A377; - mmCB_COLOR6_DCC_CONTROL =$A378; - mmCB_COLOR6_CMASK =$A379; - mmCB_COLOR6_CMASK_SLICE =$A37A; - mmCB_COLOR6_FMASK =$A37B; - mmCB_COLOR6_FMASK_SLICE =$A37C; - mmCB_COLOR6_CLEAR_WORD0 =$A37D; - mmCB_COLOR6_CLEAR_WORD1 =$A37E; - mmCB_COLOR6_DCC_BASE =$A37F; - mmCB_COLOR7_BASE =$A381; - mmCB_COLOR7_PITCH =$A382; - mmCB_COLOR7_SLICE =$A383; - mmCB_COLOR7_VIEW =$A384; - mmCB_COLOR7_INFO =$A385; - mmCB_COLOR7_ATTRIB =$A386; - mmCB_COLOR7_DCC_CONTROL =$A387; - mmCB_COLOR7_CMASK =$A388; - mmCB_COLOR7_CMASK_SLICE =$A389; - mmCB_COLOR7_FMASK =$A38A; - mmCB_COLOR7_FMASK_SLICE =$A38B; - mmCB_COLOR7_CLEAR_WORD0 =$A38C; - mmCB_COLOR7_CLEAR_WORD1 =$A38D; - mmCB_COLOR7_DCC_BASE =$A38E; - mmCP_EOP_DONE_ADDR_LO =$C000; - mmCP_EOP_DONE_ADDR_HI =$C001; - mmCP_EOP_DONE_DATA_LO =$C002; - mmCP_EOP_DONE_DATA_HI =$C003; - mmCP_EOP_LAST_FENCE_LO =$C004; - mmCP_EOP_LAST_FENCE_HI =$C005; - mmCP_STREAM_OUT_ADDR_LO =$C006; - mmCP_STREAM_OUT_ADDR_HI =$C007; - mmCP_NUM_PRIM_WRITTEN_COUNT0_LO =$C008; - mmCP_NUM_PRIM_WRITTEN_COUNT0_HI =$C009; - mmCP_NUM_PRIM_NEEDED_COUNT0_LO =$C00A; - mmCP_NUM_PRIM_NEEDED_COUNT0_HI =$C00B; - mmCP_NUM_PRIM_WRITTEN_COUNT1_LO =$C00C; - mmCP_NUM_PRIM_WRITTEN_COUNT1_HI =$C00D; - mmCP_NUM_PRIM_NEEDED_COUNT1_LO =$C00E; - mmCP_NUM_PRIM_NEEDED_COUNT1_HI =$C00F; - mmCP_NUM_PRIM_WRITTEN_COUNT2_LO =$C010; - mmCP_NUM_PRIM_WRITTEN_COUNT2_HI =$C011; - mmCP_NUM_PRIM_NEEDED_COUNT2_LO =$C012; - mmCP_NUM_PRIM_NEEDED_COUNT2_HI =$C013; - mmCP_NUM_PRIM_WRITTEN_COUNT3_LO =$C014; - mmCP_NUM_PRIM_WRITTEN_COUNT3_HI =$C015; - mmCP_NUM_PRIM_NEEDED_COUNT3_LO =$C016; - mmCP_NUM_PRIM_NEEDED_COUNT3_HI =$C017; - mmCP_PIPE_STATS_ADDR_LO =$C018; - mmCP_PIPE_STATS_ADDR_HI =$C019; - mmCP_VGT_IAVERT_COUNT_LO =$C01A; - mmCP_VGT_IAVERT_COUNT_HI =$C01B; - mmCP_VGT_IAPRIM_COUNT_LO =$C01C; - mmCP_VGT_IAPRIM_COUNT_HI =$C01D; - mmCP_VGT_GSPRIM_COUNT_LO =$C01E; - mmCP_VGT_GSPRIM_COUNT_HI =$C01F; - mmCP_VGT_VSINVOC_COUNT_LO =$C020; - mmCP_VGT_VSINVOC_COUNT_HI =$C021; - mmCP_VGT_GSINVOC_COUNT_LO =$C022; - mmCP_VGT_GSINVOC_COUNT_HI =$C023; - mmCP_VGT_HSINVOC_COUNT_LO =$C024; - mmCP_VGT_HSINVOC_COUNT_HI =$C025; - mmCP_VGT_DSINVOC_COUNT_LO =$C026; - mmCP_VGT_DSINVOC_COUNT_HI =$C027; - mmCP_PA_CINVOC_COUNT_LO =$C028; - mmCP_PA_CINVOC_COUNT_HI =$C029; - mmCP_PA_CPRIM_COUNT_LO =$C02A; - mmCP_PA_CPRIM_COUNT_HI =$C02B; - mmCP_SC_PSINVOC_COUNT0_LO =$C02C; - mmCP_SC_PSINVOC_COUNT0_HI =$C02D; - mmCP_SC_PSINVOC_COUNT1_LO =$C02E; - mmCP_SC_PSINVOC_COUNT1_HI =$C02F; - mmCP_VGT_CSINVOC_COUNT_LO =$C030; - mmCP_VGT_CSINVOC_COUNT_HI =$C031; - mmCP_PIPE_STATS_CONTROL =$C03D; - mmCP_STREAM_OUT_CONTROL =$C03E; - mmCP_STRMOUT_CNTL =$C03F; - mmCP_PFP_ATOMIC_PREOP_LO =$C052; - mmCP_PFP_ATOMIC_PREOP_HI =$C053; - mmCP_PFP_GDS_ATOMIC0_PREOP_LO =$C054; - mmCP_PFP_GDS_ATOMIC0_PREOP_HI =$C055; - mmCP_PFP_GDS_ATOMIC1_PREOP_LO =$C056; - mmCP_PFP_GDS_ATOMIC1_PREOP_HI =$C057; - mmCP_APPEND_ADDR_LO =$C058; - mmCP_APPEND_ADDR_HI =$C059; - mmCP_APPEND_DATA =$C05A; - mmCP_APPEND_LAST_CS_FENCE =$C05B; - mmCP_APPEND_LAST_PS_FENCE =$C05C; - mmCP_ATOMIC_PREOP_LO =$C05D; - mmCP_ATOMIC_PREOP_HI =$C05E; - mmCP_GDS_ATOMIC0_PREOP_LO =$C05F; - mmCP_GDS_ATOMIC0_PREOP_HI =$C060; - mmCP_GDS_ATOMIC1_PREOP_LO =$C061; - mmCP_GDS_ATOMIC1_PREOP_HI =$C062; - mmCP_SEM_WAIT_TIMER =$C06F; - mmCP_SIG_SEM_ADDR_LO =$C070; - mmCP_SIG_SEM_ADDR_HI =$C071; - mmCP_WAIT_REG_MEM_TIMEOUT =$C074; - mmCP_WAIT_SEM_ADDR_LO =$C075; - mmCP_WAIT_SEM_ADDR_HI =$C076; - mmCP_DMA_PFP_CONTROL =$C077; - mmCP_DMA_ME_CONTROL =$C078; - mmCP_COHER_BASE_HI =$C079; - mmCP_COHER_START_DELAY =$C07B; - mmCP_COHER_CNTL =$C07C; - mmCP_COHER_SIZE =$C07D; - mmCP_COHER_BASE =$C07E; - mmCP_COHER_STATUS =$C07F; - mmCP_DMA_ME_SRC_ADDR =$C080; - mmCP_DMA_ME_SRC_ADDR_HI =$C081; - mmCP_DMA_ME_DST_ADDR =$C082; - mmCP_DMA_ME_DST_ADDR_HI =$C083; - mmCP_DMA_ME_COMMAND =$C084; - mmCP_DMA_PFP_SRC_ADDR =$C085; - mmCP_DMA_PFP_SRC_ADDR_HI =$C086; - mmCP_DMA_PFP_DST_ADDR =$C087; - mmCP_DMA_PFP_DST_ADDR_HI =$C088; - mmCP_DMA_PFP_COMMAND =$C089; - mmCP_DMA_CNTL =$C08A; - mmCP_DMA_READ_TAGS =$C08B; - mmCP_COHER_SIZE_HI =$C08C; - mmCP_PFP_IB_CONTROL =$C08D; - mmCP_PFP_LOAD_CONTROL =$C08E; - mmCP_SCRATCH_INDEX =$C08F; - mmCP_SCRATCH_DATA =$C090; - mmCP_IB1_OFFSET =$C092; - mmCP_IB2_OFFSET =$C093; - mmCP_IB1_PREAMBLE_BEGIN =$C094; - mmCP_IB1_PREAMBLE_END =$C095; - mmCP_IB2_PREAMBLE_BEGIN =$C096; - mmCP_IB2_PREAMBLE_END =$C097; - mmCP_CE_IB1_OFFSET =$C098; - mmCP_CE_IB2_OFFSET =$C099; - mmCP_CE_COUNTER =$C09A; - mmCP_CE_RB_OFFSET =$C09B; - mmCP_CE_INIT_BASE_LO =$C0C3; - mmCP_CE_INIT_BASE_HI =$C0C4; - mmCP_CE_INIT_BUFSZ =$C0C5; - mmCP_CE_IB1_BASE_LO =$C0C6; - mmCP_CE_IB1_BASE_HI =$C0C7; - mmCP_CE_IB1_BUFSZ =$C0C8; - mmCP_CE_IB2_BASE_LO =$C0C9; - mmCP_CE_IB2_BASE_HI =$C0CA; - mmCP_CE_IB2_BUFSZ =$C0CB; - mmCP_IB1_BASE_LO =$C0CC; - mmCP_IB1_BASE_HI =$C0CD; - mmCP_IB1_BUFSZ =$C0CE; - mmCP_IB2_BASE_LO =$C0CF; - mmCP_IB2_BASE_HI =$C0D0; - mmCP_IB2_BUFSZ =$C0D1; - mmCP_ST_BASE_LO =$C0D2; - mmCP_ST_BASE_HI =$C0D3; - mmCP_ST_BUFSZ =$C0D4; - mmCP_EOP_DONE_EVENT_CNTL =$C0D5; - mmCP_EOP_DONE_DATA_CNTL =$C0D6; - mmCP_EOP_DONE_CNTX_ID =$C0D7; - mmCP_PFP_COMPLETION_STATUS =$C0EC; - mmCP_CE_COMPLETION_STATUS =$C0ED; - mmCP_PRED_NOT_VISIBLE =$C0EE; - mmCP_PFP_METADATA_BASE_ADDR =$C0F0; - mmCP_PFP_METADATA_BASE_ADDR_HI =$C0F1; - mmCP_CE_METADATA_BASE_ADDR =$C0F2; - mmCP_CE_METADATA_BASE_ADDR_HI =$C0F3; - mmCP_DRAW_INDX_INDR_ADDR =$C0F4; - mmCP_DRAW_INDX_INDR_ADDR_HI =$C0F5; - mmCP_DISPATCH_INDR_ADDR =$C0F6; - mmCP_DISPATCH_INDR_ADDR_HI =$C0F7; - mmCP_INDEX_BASE_ADDR =$C0F8; - mmCP_INDEX_BASE_ADDR_HI =$C0F9; - mmCP_INDEX_TYPE =$C0FA; - mmCP_GDS_BKUP_ADDR =$C0FB; - mmCP_GDS_BKUP_ADDR_HI =$C0FC; - mmCP_SAMPLE_STATUS =$C0FD; - mmGRBM_GFX_INDEX =$C200; - mmVGT_ESGS_RING_SIZE =$C240; - mmVGT_GSVS_RING_SIZE =$C241; - mmVGT_PRIMITIVE_TYPE =$C242; - mmVGT_INDEX_TYPE =$C243; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 =$C244; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 =$C245; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 =$C246; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 =$C247; - mmVGT_NUM_INDICES =$C24C; - mmVGT_NUM_INSTANCES =$C24D; - mmVGT_TF_RING_SIZE =$C24E; - mmVGT_HS_OFFCHIP_PARAM =$C24F; - mmVGT_TF_MEMORY_BASE =$C250; - mmPA_SU_LINE_STIPPLE_VALUE =$C280; - mmPA_SC_LINE_STIPPLE_STATE =$C281; - mmPA_SC_P3D_TRAP_SCREEN_HV_EN =$C2A0; - mmPA_SC_P3D_TRAP_SCREEN_H =$C2A1; - mmPA_SC_P3D_TRAP_SCREEN_V =$C2A2; - mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE =$C2A3; - mmPA_SC_P3D_TRAP_SCREEN_COUNT =$C2A4; - mmPA_SC_HP3D_TRAP_SCREEN_HV_EN =$C2A8; - mmPA_SC_HP3D_TRAP_SCREEN_H =$C2A9; - mmPA_SC_HP3D_TRAP_SCREEN_V =$C2AA; - mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE =$C2AB; - mmPA_SC_HP3D_TRAP_SCREEN_COUNT =$C2AC; - mmPA_SC_TRAP_SCREEN_HV_EN =$C2B0; - mmPA_SC_TRAP_SCREEN_H =$C2B1; - mmPA_SC_TRAP_SCREEN_V =$C2B2; - mmPA_SC_TRAP_SCREEN_OCCURRENCE =$C2B3; - mmPA_SC_TRAP_SCREEN_COUNT =$C2B4; - mmSQ_THREAD_TRACE_BASE =$C330; - mmSQ_THREAD_TRACE_SIZE =$C331; - mmSQ_THREAD_TRACE_MASK =$C332; - mmSQ_THREAD_TRACE_TOKEN_MASK =$C333; - mmSQ_THREAD_TRACE_PERF_MASK =$C334; - mmSQ_THREAD_TRACE_CTRL =$C335; - mmSQ_THREAD_TRACE_MODE =$C336; - mmSQ_THREAD_TRACE_BASE2 =$C337; - mmSQ_THREAD_TRACE_TOKEN_MASK2 =$C338; - mmSQ_THREAD_TRACE_WPTR =$C339; - mmSQ_THREAD_TRACE_STATUS =$C33A; - mmSQ_THREAD_TRACE_HIWATER =$C33B; - mmSQ_THREAD_TRACE_USERDATA_0 =$C340; - mmSQ_THREAD_TRACE_USERDATA_1 =$C341; - mmSQ_THREAD_TRACE_USERDATA_2 =$C342; - mmSQ_THREAD_TRACE_USERDATA_3 =$C343; - mmTA_CS_BC_BASE_ADDR =$C380; - mmTA_CS_BC_BASE_ADDR_HI =$C381; - mmDB_OCCLUSION_COUNT0_LOW =$C3C0; - mmDB_OCCLUSION_COUNT0_HI =$C3C1; - mmDB_OCCLUSION_COUNT1_LOW =$C3C2; - mmDB_OCCLUSION_COUNT1_HI =$C3C3; - mmDB_OCCLUSION_COUNT2_LOW =$C3C4; - mmDB_OCCLUSION_COUNT2_HI =$C3C5; - mmDB_OCCLUSION_COUNT3_LOW =$C3C6; - mmDB_OCCLUSION_COUNT3_HI =$C3C7; - mmDB_ZPASS_COUNT_LOW =$C3FE; - mmDB_ZPASS_COUNT_HI =$C3FF; - mmGDS_RD_ADDR =$C400; - mmGDS_RD_DATA =$C401; - mmGDS_RD_BURST_ADDR =$C402; - mmGDS_RD_BURST_COUNT =$C403; - mmGDS_RD_BURST_DATA =$C404; - mmGDS_WR_ADDR =$C405; - mmGDS_WR_DATA =$C406; - mmGDS_WR_BURST_ADDR =$C407; - mmGDS_WR_BURST_DATA =$C408; - mmGDS_WRITE_COMPLETE =$C409; - mmGDS_ATOM_CNTL =$C40A; - mmGDS_ATOM_COMPLETE =$C40B; - mmGDS_ATOM_BASE =$C40C; - mmGDS_ATOM_SIZE =$C40D; - mmGDS_ATOM_OFFSET0 =$C40E; - mmGDS_ATOM_OFFSET1 =$C40F; - mmGDS_ATOM_DST =$C410; - mmGDS_ATOM_OP =$C411; - mmGDS_ATOM_SRC0 =$C412; - mmGDS_ATOM_SRC0_U =$C413; - mmGDS_ATOM_SRC1 =$C414; - mmGDS_ATOM_SRC1_U =$C415; - mmGDS_ATOM_READ0 =$C416; - mmGDS_ATOM_READ0_U =$C417; - mmGDS_ATOM_READ1 =$C418; - mmGDS_ATOM_READ1_U =$C419; - mmGDS_GWS_RESOURCE_CNTL =$C41A; - mmGDS_GWS_RESOURCE =$C41B; - mmGDS_GWS_RESOURCE_CNT =$C41C; - mmGDS_OA_CNTL =$C41D; - mmGDS_OA_COUNTER =$C41E; - mmGDS_OA_ADDRESS =$C41F; - mmGDS_OA_INCDEC =$C420; - mmGDS_OA_RING_SIZE =$C421; - mmCPG_PERFCOUNTER1_LO =$D000; - mmCPG_PERFCOUNTER1_HI =$D001; - mmCPG_PERFCOUNTER0_LO =$D002; - mmCPG_PERFCOUNTER0_HI =$D003; - mmCPC_PERFCOUNTER1_LO =$D004; - mmCPC_PERFCOUNTER1_HI =$D005; - mmCPC_PERFCOUNTER0_LO =$D006; - mmCPC_PERFCOUNTER0_HI =$D007; - mmCPF_PERFCOUNTER1_LO =$D008; - mmCPF_PERFCOUNTER1_HI =$D009; - mmCPF_PERFCOUNTER0_LO =$D00A; - mmCPF_PERFCOUNTER0_HI =$D00B; - mmGRBM_PERFCOUNTER0_LO =$D040; - mmGRBM_PERFCOUNTER0_HI =$D041; - mmGRBM_PERFCOUNTER1_LO =$D043; - mmGRBM_PERFCOUNTER1_HI =$D044; - mmGRBM_SE0_PERFCOUNTER_LO =$D045; - mmGRBM_SE0_PERFCOUNTER_HI =$D046; - mmGRBM_SE1_PERFCOUNTER_LO =$D047; - mmGRBM_SE1_PERFCOUNTER_HI =$D048; - mmGRBM_SE2_PERFCOUNTER_LO =$D049; - mmGRBM_SE2_PERFCOUNTER_HI =$D04A; - mmGRBM_SE3_PERFCOUNTER_LO =$D04B; - mmGRBM_SE3_PERFCOUNTER_HI =$D04C; - mmWD_PERFCOUNTER0_LO =$D080; - mmWD_PERFCOUNTER0_HI =$D081; - mmWD_PERFCOUNTER1_LO =$D082; - mmWD_PERFCOUNTER1_HI =$D083; - mmWD_PERFCOUNTER2_LO =$D084; - mmWD_PERFCOUNTER2_HI =$D085; - mmWD_PERFCOUNTER3_LO =$D086; - mmWD_PERFCOUNTER3_HI =$D087; - mmIA_PERFCOUNTER0_LO =$D088; - mmIA_PERFCOUNTER0_HI =$D089; - mmIA_PERFCOUNTER1_LO =$D08A; - mmIA_PERFCOUNTER1_HI =$D08B; - mmIA_PERFCOUNTER2_LO =$D08C; - mmIA_PERFCOUNTER2_HI =$D08D; - mmIA_PERFCOUNTER3_LO =$D08E; - mmIA_PERFCOUNTER3_HI =$D08F; - mmVGT_PERFCOUNTER0_LO =$D090; - mmVGT_PERFCOUNTER0_HI =$D091; - mmVGT_PERFCOUNTER1_LO =$D092; - mmVGT_PERFCOUNTER1_HI =$D093; - mmVGT_PERFCOUNTER2_LO =$D094; - mmVGT_PERFCOUNTER2_HI =$D095; - mmVGT_PERFCOUNTER3_LO =$D096; - mmVGT_PERFCOUNTER3_HI =$D097; - mmPA_SU_PERFCOUNTER0_LO =$D100; - mmPA_SU_PERFCOUNTER0_HI =$D101; - mmPA_SU_PERFCOUNTER1_LO =$D102; - mmPA_SU_PERFCOUNTER1_HI =$D103; - mmPA_SU_PERFCOUNTER2_LO =$D104; - mmPA_SU_PERFCOUNTER2_HI =$D105; - mmPA_SU_PERFCOUNTER3_LO =$D106; - mmPA_SU_PERFCOUNTER3_HI =$D107; - mmPA_SC_PERFCOUNTER0_LO =$D140; - mmPA_SC_PERFCOUNTER0_HI =$D141; - mmPA_SC_PERFCOUNTER1_LO =$D142; - mmPA_SC_PERFCOUNTER1_HI =$D143; - mmPA_SC_PERFCOUNTER2_LO =$D144; - mmPA_SC_PERFCOUNTER2_HI =$D145; - mmPA_SC_PERFCOUNTER3_LO =$D146; - mmPA_SC_PERFCOUNTER3_HI =$D147; - mmPA_SC_PERFCOUNTER4_LO =$D148; - mmPA_SC_PERFCOUNTER4_HI =$D149; - mmPA_SC_PERFCOUNTER5_LO =$D14A; - mmPA_SC_PERFCOUNTER5_HI =$D14B; - mmPA_SC_PERFCOUNTER6_LO =$D14C; - mmPA_SC_PERFCOUNTER6_HI =$D14D; - mmPA_SC_PERFCOUNTER7_LO =$D14E; - mmPA_SC_PERFCOUNTER7_HI =$D14F; - mmSPI_PERFCOUNTER0_HI =$D180; - mmSPI_PERFCOUNTER0_LO =$D181; - mmSPI_PERFCOUNTER1_HI =$D182; - mmSPI_PERFCOUNTER1_LO =$D183; - mmSPI_PERFCOUNTER2_HI =$D184; - mmSPI_PERFCOUNTER2_LO =$D185; - mmSPI_PERFCOUNTER3_HI =$D186; - mmSPI_PERFCOUNTER3_LO =$D187; - mmSPI_PERFCOUNTER4_HI =$D188; - mmSPI_PERFCOUNTER4_LO =$D189; - mmSPI_PERFCOUNTER5_HI =$D18A; - mmSPI_PERFCOUNTER5_LO =$D18B; - mmSQ_PERFCOUNTER0_LO =$D1C0; - mmSQ_PERFCOUNTER0_HI =$D1C1; - mmSQ_PERFCOUNTER1_LO =$D1C2; - mmSQ_PERFCOUNTER1_HI =$D1C3; - mmSQ_PERFCOUNTER2_LO =$D1C4; - mmSQ_PERFCOUNTER2_HI =$D1C5; - mmSQ_PERFCOUNTER3_LO =$D1C6; - mmSQ_PERFCOUNTER3_HI =$D1C7; - mmSQ_PERFCOUNTER4_LO =$D1C8; - mmSQ_PERFCOUNTER4_HI =$D1C9; - mmSQ_PERFCOUNTER5_LO =$D1CA; - mmSQ_PERFCOUNTER5_HI =$D1CB; - mmSQ_PERFCOUNTER6_LO =$D1CC; - mmSQ_PERFCOUNTER6_HI =$D1CD; - mmSQ_PERFCOUNTER7_LO =$D1CE; - mmSQ_PERFCOUNTER7_HI =$D1CF; - mmSQ_PERFCOUNTER8_LO =$D1D0; - mmSQ_PERFCOUNTER8_HI =$D1D1; - mmSQ_PERFCOUNTER9_LO =$D1D2; - mmSQ_PERFCOUNTER9_HI =$D1D3; - mmSQ_PERFCOUNTER10_LO =$D1D4; - mmSQ_PERFCOUNTER10_HI =$D1D5; - mmSQ_PERFCOUNTER11_LO =$D1D6; - mmSQ_PERFCOUNTER11_HI =$D1D7; - mmSQ_PERFCOUNTER12_LO =$D1D8; - mmSQ_PERFCOUNTER12_HI =$D1D9; - mmSQ_PERFCOUNTER13_LO =$D1DA; - mmSQ_PERFCOUNTER13_HI =$D1DB; - mmSQ_PERFCOUNTER14_LO =$D1DC; - mmSQ_PERFCOUNTER14_HI =$D1DD; - mmSQ_PERFCOUNTER15_LO =$D1DE; - mmSQ_PERFCOUNTER15_HI =$D1DF; - mmSX_PERFCOUNTER0_LO =$D240; - mmSX_PERFCOUNTER0_HI =$D241; - mmSX_PERFCOUNTER1_LO =$D242; - mmSX_PERFCOUNTER1_HI =$D243; - mmSX_PERFCOUNTER2_LO =$D244; - mmSX_PERFCOUNTER2_HI =$D245; - mmSX_PERFCOUNTER3_LO =$D246; - mmSX_PERFCOUNTER3_HI =$D247; - mmGDS_PERFCOUNTER0_LO =$D280; - mmGDS_PERFCOUNTER0_HI =$D281; - mmGDS_PERFCOUNTER1_LO =$D282; - mmGDS_PERFCOUNTER1_HI =$D283; - mmGDS_PERFCOUNTER2_LO =$D284; - mmGDS_PERFCOUNTER2_HI =$D285; - mmGDS_PERFCOUNTER3_LO =$D286; - mmGDS_PERFCOUNTER3_HI =$D287; - mmTA_PERFCOUNTER0_LO =$D2C0; - mmTA_PERFCOUNTER0_HI =$D2C1; - mmTA_PERFCOUNTER1_LO =$D2C2; - mmTA_PERFCOUNTER1_HI =$D2C3; - mmTD_PERFCOUNTER0_LO =$D300; - mmTD_PERFCOUNTER0_HI =$D301; - mmTD_PERFCOUNTER1_LO =$D302; - mmTD_PERFCOUNTER1_HI =$D303; - mmTCP_PERFCOUNTER0_LO =$D340; - mmTCP_PERFCOUNTER0_HI =$D341; - mmTCP_PERFCOUNTER1_LO =$D342; - mmTCP_PERFCOUNTER1_HI =$D343; - mmTCP_PERFCOUNTER2_LO =$D344; - mmTCP_PERFCOUNTER2_HI =$D345; - mmTCP_PERFCOUNTER3_LO =$D346; - mmTCP_PERFCOUNTER3_HI =$D347; - mmTCC_PERFCOUNTER0_LO =$D380; - mmTCC_PERFCOUNTER0_HI =$D381; - mmTCC_PERFCOUNTER1_LO =$D382; - mmTCC_PERFCOUNTER1_HI =$D383; - mmTCC_PERFCOUNTER2_LO =$D384; - mmTCC_PERFCOUNTER2_HI =$D385; - mmTCC_PERFCOUNTER3_LO =$D386; - mmTCC_PERFCOUNTER3_HI =$D387; - mmTCA_PERFCOUNTER0_LO =$D390; - mmTCA_PERFCOUNTER0_HI =$D391; - mmTCA_PERFCOUNTER1_LO =$D392; - mmTCA_PERFCOUNTER1_HI =$D393; - mmTCA_PERFCOUNTER2_LO =$D394; - mmTCA_PERFCOUNTER2_HI =$D395; - mmTCA_PERFCOUNTER3_LO =$D396; - mmTCA_PERFCOUNTER3_HI =$D397; - mmCB_PERFCOUNTER0_LO =$D406; - mmCB_PERFCOUNTER0_HI =$D407; - mmCB_PERFCOUNTER1_LO =$D408; - mmCB_PERFCOUNTER1_HI =$D409; - mmCB_PERFCOUNTER2_LO =$D40A; - mmCB_PERFCOUNTER2_HI =$D40B; - mmCB_PERFCOUNTER3_LO =$D40C; - mmCB_PERFCOUNTER3_HI =$D40D; - mmDB_PERFCOUNTER0_LO =$D440; - mmDB_PERFCOUNTER0_HI =$D441; - mmDB_PERFCOUNTER1_LO =$D442; - mmDB_PERFCOUNTER1_HI =$D443; - mmDB_PERFCOUNTER2_LO =$D444; - mmDB_PERFCOUNTER2_HI =$D445; - mmDB_PERFCOUNTER3_LO =$D446; - mmDB_PERFCOUNTER3_HI =$D447; - mmCPG_PERFCOUNTER1_SELECT =$D800; - mmCPG_PERFCOUNTER0_SELECT1 =$D801; - mmCPG_PERFCOUNTER0_SELECT =$D802; - mmCPC_PERFCOUNTER1_SELECT =$D803; - mmCPC_PERFCOUNTER0_SELECT1 =$D804; - mmCPF_PERFCOUNTER1_SELECT =$D805; - mmCPF_PERFCOUNTER0_SELECT1 =$D806; - mmCPF_PERFCOUNTER0_SELECT =$D807; - mmCP_PERFMON_CNTL =$D808; - mmCPC_PERFCOUNTER0_SELECT =$D809; - mmCP_DRAW_OBJECT =$D810; - mmCP_DRAW_OBJECT_COUNTER =$D811; - mmCP_DRAW_WINDOW_MASK_HI =$D812; - mmCP_DRAW_WINDOW_HI =$D813; - mmCP_DRAW_WINDOW_LO =$D814; - mmCP_DRAW_WINDOW_CNTL =$D815; - mmGRBM_PERFCOUNTER0_SELECT =$D840; - mmGRBM_PERFCOUNTER1_SELECT =$D841; - mmGRBM_SE0_PERFCOUNTER_SELECT =$D842; - mmGRBM_SE1_PERFCOUNTER_SELECT =$D843; - mmGRBM_SE2_PERFCOUNTER_SELECT =$D844; - mmGRBM_SE3_PERFCOUNTER_SELECT =$D845; - mmWD_PERFCOUNTER0_SELECT =$D880; - mmWD_PERFCOUNTER1_SELECT =$D881; - mmWD_PERFCOUNTER2_SELECT =$D882; - mmWD_PERFCOUNTER3_SELECT =$D883; - mmIA_PERFCOUNTER0_SELECT =$D884; - mmIA_PERFCOUNTER1_SELECT =$D885; - mmIA_PERFCOUNTER2_SELECT =$D886; - mmIA_PERFCOUNTER3_SELECT =$D887; - mmIA_PERFCOUNTER0_SELECT1 =$D888; - mmVGT_PERFCOUNTER0_SELECT =$D88C; - mmVGT_PERFCOUNTER1_SELECT =$D88D; - mmVGT_PERFCOUNTER2_SELECT =$D88E; - mmVGT_PERFCOUNTER3_SELECT =$D88F; - mmVGT_PERFCOUNTER0_SELECT1 =$D890; - mmVGT_PERFCOUNTER1_SELECT1 =$D891; - mmVGT_PERFCOUNTER_SEID_MASK =$D894; - mmPA_SU_PERFCOUNTER0_SELECT =$D900; - mmPA_SU_PERFCOUNTER0_SELECT1 =$D901; - mmPA_SU_PERFCOUNTER1_SELECT =$D902; - mmPA_SU_PERFCOUNTER1_SELECT1 =$D903; - mmPA_SU_PERFCOUNTER2_SELECT =$D904; - mmPA_SU_PERFCOUNTER3_SELECT =$D905; - mmPA_SC_PERFCOUNTER0_SELECT =$D940; - mmPA_SC_PERFCOUNTER0_SELECT1 =$D941; - mmPA_SC_PERFCOUNTER1_SELECT =$D942; - mmPA_SC_PERFCOUNTER2_SELECT =$D943; - mmPA_SC_PERFCOUNTER3_SELECT =$D944; - mmPA_SC_PERFCOUNTER4_SELECT =$D945; - mmPA_SC_PERFCOUNTER5_SELECT =$D946; - mmPA_SC_PERFCOUNTER6_SELECT =$D947; - mmPA_SC_PERFCOUNTER7_SELECT =$D948; - mmSPI_PERFCOUNTER0_SELECT =$D980; - mmSPI_PERFCOUNTER1_SELECT =$D981; - mmSPI_PERFCOUNTER2_SELECT =$D982; - mmSPI_PERFCOUNTER3_SELECT =$D983; - mmSPI_PERFCOUNTER0_SELECT1 =$D984; - mmSPI_PERFCOUNTER1_SELECT1 =$D985; - mmSPI_PERFCOUNTER2_SELECT1 =$D986; - mmSPI_PERFCOUNTER3_SELECT1 =$D987; - mmSPI_PERFCOUNTER4_SELECT =$D988; - mmSPI_PERFCOUNTER5_SELECT =$D989; - mmSPI_PERFCOUNTER_BINS =$D98A; - mmSQ_PERFCOUNTER0_SELECT =$D9C0; - mmSQ_PERFCOUNTER1_SELECT =$D9C1; - mmSQ_PERFCOUNTER2_SELECT =$D9C2; - mmSQ_PERFCOUNTER3_SELECT =$D9C3; - mmSQ_PERFCOUNTER4_SELECT =$D9C4; - mmSQ_PERFCOUNTER5_SELECT =$D9C5; - mmSQ_PERFCOUNTER6_SELECT =$D9C6; - mmSQ_PERFCOUNTER7_SELECT =$D9C7; - mmSQ_PERFCOUNTER8_SELECT =$D9C8; - mmSQ_PERFCOUNTER9_SELECT =$D9C9; - mmSQ_PERFCOUNTER10_SELECT =$D9CA; - mmSQ_PERFCOUNTER11_SELECT =$D9CB; - mmSQ_PERFCOUNTER12_SELECT =$D9CC; - mmSQ_PERFCOUNTER13_SELECT =$D9CD; - mmSQ_PERFCOUNTER14_SELECT =$D9CE; - mmSQ_PERFCOUNTER15_SELECT =$D9CF; - mmSQ_PERFCOUNTER_CTRL =$D9E0; - mmSQ_PERFCOUNTER_MASK =$D9E1; - mmSQ_PERFCOUNTER_CTRL2 =$D9E2; - mmSX_PERFCOUNTER0_SELECT =$DA40; - mmSX_PERFCOUNTER1_SELECT =$DA41; - mmSX_PERFCOUNTER2_SELECT =$DA42; - mmSX_PERFCOUNTER3_SELECT =$DA43; - mmSX_PERFCOUNTER0_SELECT1 =$DA44; - mmSX_PERFCOUNTER1_SELECT1 =$DA45; - mmGDS_PERFCOUNTER0_SELECT =$DA80; - mmGDS_PERFCOUNTER1_SELECT =$DA81; - mmGDS_PERFCOUNTER2_SELECT =$DA82; - mmGDS_PERFCOUNTER3_SELECT =$DA83; - mmGDS_PERFCOUNTER0_SELECT1 =$DA84; - mmTA_PERFCOUNTER0_SELECT =$DAC0; - mmTA_PERFCOUNTER0_SELECT1 =$DAC1; - mmTA_PERFCOUNTER1_SELECT =$DAC2; - mmTD_PERFCOUNTER0_SELECT =$DB00; - mmTD_PERFCOUNTER0_SELECT1 =$DB01; - mmTD_PERFCOUNTER1_SELECT =$DB02; - mmTCP_PERFCOUNTER0_SELECT =$DB40; - mmTCP_PERFCOUNTER0_SELECT1 =$DB41; - mmTCP_PERFCOUNTER1_SELECT =$DB42; - mmTCP_PERFCOUNTER1_SELECT1 =$DB43; - mmTCP_PERFCOUNTER2_SELECT =$DB44; - mmTCP_PERFCOUNTER3_SELECT =$DB45; - mmTCC_PERFCOUNTER0_SELECT =$DB80; - mmTCC_PERFCOUNTER0_SELECT1 =$DB81; - mmTCC_PERFCOUNTER1_SELECT =$DB82; - mmTCC_PERFCOUNTER1_SELECT1 =$DB83; - mmTCC_PERFCOUNTER2_SELECT =$DB84; - mmTCC_PERFCOUNTER3_SELECT =$DB85; - mmTCA_PERFCOUNTER0_SELECT =$DB90; - mmTCA_PERFCOUNTER0_SELECT1 =$DB91; - mmTCA_PERFCOUNTER1_SELECT =$DB92; - mmTCA_PERFCOUNTER1_SELECT1 =$DB93; - mmTCA_PERFCOUNTER2_SELECT =$DB94; - mmTCA_PERFCOUNTER3_SELECT =$DB95; - mmCB_PERFCOUNTER_FILTER =$DC00; - mmCB_PERFCOUNTER0_SELECT =$DC01; - mmCB_PERFCOUNTER0_SELECT1 =$DC02; - mmCB_PERFCOUNTER1_SELECT =$DC03; - mmCB_PERFCOUNTER2_SELECT =$DC04; - mmCB_PERFCOUNTER3_SELECT =$DC05; - mmDB_PERFCOUNTER0_SELECT =$DC40; - mmDB_PERFCOUNTER0_SELECT1 =$DC41; - mmDB_PERFCOUNTER1_SELECT =$DC42; - mmDB_PERFCOUNTER1_SELECT1 =$DC43; - mmDB_PERFCOUNTER2_SELECT =$DC44; - mmDB_PERFCOUNTER3_SELECT =$DC46; + mmGRBM_CNTL =$2000; + mmGRBM_SKEW_CNTL =$2001; + mmGRBM_STATUS2 =$2002; + mmGRBM_PWR_CNTL =$2003; + mmGRBM_STATUS =$2004; + mmGRBM_STATUS_SE0 =$2005; + mmGRBM_STATUS_SE1 =$2006; + mmGRBM_SOFT_RESET =$2008; + mmGRBM_DEBUG_CNTL =$2009; + mmGRBM_DEBUG_DATA =$200A; + mmGRBM_GFX_CLKEN_CNTL =$200C; + mmGRBM_WAIT_IDLE_CLOCKS =$200D; + mmGRBM_STATUS_SE2 =$200E; + mmGRBM_STATUS_SE3 =$200F; + mmGRBM_DEBUG =$2014; + mmGRBM_DEBUG_SNAPSHOT =$2015; + mmGRBM_READ_ERROR =$2016; + mmGRBM_READ_ERROR2 =$2017; + mmGRBM_INT_CNTL =$2018; + mmGRBM_TRAP_OP =$2019; + mmGRBM_TRAP_ADDR =$201A; + mmGRBM_TRAP_ADDR_MSK =$201B; + mmGRBM_TRAP_WD =$201C; + mmGRBM_TRAP_WD_MSK =$201D; + mmGRBM_DSM_BYPASS =$201E; + mmGRBM_WRITE_ERROR =$201F; + mmDEBUG_INDEX =$203C; + mmDEBUG_DATA =$203D; + mmGRBM_NOWHERE =$203F; + mmGRBM_SCRATCH_REG0 =$2040; + mmGRBM_SCRATCH_REG1 =$2041; + mmGRBM_SCRATCH_REG2 =$2042; + mmGRBM_SCRATCH_REG3 =$2043; + mmGRBM_SCRATCH_REG4 =$2044; + mmGRBM_SCRATCH_REG5 =$2045; + mmGRBM_SCRATCH_REG6 =$2046; + mmGRBM_SCRATCH_REG7 =$2047; + mmCP_CPC_STATUS =$2084; + mmCP_CPC_BUSY_STAT =$2085; + mmCP_CPC_STALLED_STAT1 =$2086; + mmCP_CPF_STATUS =$2087; + mmCP_CPF_BUSY_STAT =$2088; + mmCP_CPF_STALLED_STAT1 =$2089; + mmCP_CPC_GRBM_FREE_COUNT =$208B; + mmCP_MEC_CNTL =$208D; + mmCP_MEC_ME1_HEADER_DUMP =$208E; + mmCP_MEC_ME2_HEADER_DUMP =$208F; + mmCP_CPC_SCRATCH_INDEX =$2090; + mmCP_CPC_SCRATCH_DATA =$2091; + mmCP_CPC_HALT_HYST_COUNT =$20A7; + mmCP_PRT_LOD_STATS_CNTL0 =$20AD; + mmCP_PRT_LOD_STATS_CNTL1 =$20AE; + mmCP_PRT_LOD_STATS_CNTL2 =$20AF; + mmCP_CE_COMPARE_COUNT =$20C0; + mmCP_CE_DE_COUNT =$20C1; + mmCP_DE_CE_COUNT =$20C2; + mmCP_DE_LAST_INVAL_COUNT =$20C3; + mmCP_DE_DE_COUNT =$20C4; + mmCP_STALLED_STAT3 =$219C; + mmCP_STALLED_STAT1 =$219D; + mmCP_STALLED_STAT2 =$219E; + mmCP_BUSY_STAT =$219F; + mmCP_STAT =$21A0; + mmCP_ME_HEADER_DUMP =$21A1; + mmCP_PFP_HEADER_DUMP =$21A2; + mmCP_GRBM_FREE_COUNT =$21A3; + mmCP_CE_HEADER_DUMP =$21A4; + mmCP_CSF_STAT =$21B4; + mmCP_CSF_CNTL =$21B5; + mmCP_ME_CNTL =$21B6; + mmCP_CNTX_STAT =$21B8; + mmCP_ME_PREEMPTION =$21B9; + mmCP_ROQ_THRESHOLDS =$21BC; + mmCP_MEQ_STQ_THRESHOLD =$21BD; + mmCP_RB2_RPTR =$21BE; + mmCP_RB1_RPTR =$21BF; + mmCP_RB0_RPTR =$21C0; + mmCP_RB_WPTR_DELAY =$21C1; + mmCP_RB_WPTR_POLL_CNTL =$21C2; + mmCP_ROQ1_THRESHOLDS =$21D5; + mmCP_ROQ2_THRESHOLDS =$21D6; + mmCP_STQ_THRESHOLDS =$21D7; + mmCP_QUEUE_THRESHOLDS =$21D8; + mmCP_MEQ_THRESHOLDS =$21D9; + mmCP_ROQ_AVAIL =$21DA; + mmCP_STQ_AVAIL =$21DB; + mmCP_ROQ2_AVAIL =$21DC; + mmCP_MEQ_AVAIL =$21DD; + mmCP_CMD_INDEX =$21DE; + mmCP_CMD_DATA =$21DF; + mmCP_ROQ_RB_STAT =$21E0; + mmCP_ROQ_IB1_STAT =$21E1; + mmCP_ROQ_IB2_STAT =$21E2; + mmCP_STQ_STAT =$21E3; + mmCP_STQ_WR_STAT =$21E4; + mmCP_MEQ_STAT =$21E5; + mmCP_CEQ1_AVAIL =$21E6; + mmCP_CEQ2_AVAIL =$21E7; + mmCP_CE_ROQ_RB_STAT =$21E8; + mmCP_CE_ROQ_IB1_STAT =$21E9; + mmCP_CE_ROQ_IB2_STAT =$21EA; + mmCP_INT_STAT_DEBUG =$21F7; + mmCP_PERFCOUNTER_SELECT =$21FC; + mmCP_PERFCOUNTER_LO =$21FD; + mmCP_PERFCOUNTER_HI =$21FE; + mmVGT_VTX_VECT_EJECT_REG =$222C; + mmVGT_DMA_DATA_FIFO_DEPTH =$222D; + mmVGT_DMA_REQ_FIFO_DEPTH =$222E; + mmVGT_DRAW_INIT_FIFO_DEPTH =$222F; + mmVGT_LAST_COPY_STATE =$2230; + mmVGT_CACHE_INVALIDATION =$2231; + mmVGT_RESET_DEBUG =$2232; + mmVGT_STRMOUT_DELAY =$2233; + mmVGT_FIFO_DEPTHS =$2234; + mmVGT_GS_VERTEX_REUSE =$2235; + mmVGT_MC_LAT_CNTL =$2236; + mmIA_CNTL_STATUS =$2237; + mmVGT_DEBUG_CNTL =$2238; + mmVGT_DEBUG_DATA =$2239; + mmIA_DEBUG_CNTL =$223A; + mmIA_DEBUG_DATA =$223B; + mmVGT_CNTL_STATUS =$223C; + mmWD_DEBUG_CNTL =$223D; + mmWD_DEBUG_DATA =$223E; + mmWD_CNTL_STATUS =$223F; + mmCC_GC_PRIM_CONFIG =$2240; + mmGC_USER_PRIM_CONFIG =$2241; + mmWD_QOS =$2242; + mmCGTT_VGT_CLK_CTRL =$225F; + mmCGTT_IA_CLK_CTRL =$2261; + mmVGT_SYS_CONFIG =$2263; + mmVGT_VS_MAX_WAVE_ID =$2268; + mmGFX_PIPE_CONTROL =$226D; + mmCC_GC_SHADER_ARRAY_CONFIG =$226F; + mmGC_USER_SHADER_ARRAY_CONFIG =$2270; + mmVGT_DMA_PRIMITIVE_TYPE =$2271; + mmVGT_DMA_CONTROL =$2272; + mmVGT_DMA_LS_HS_CONFIG =$2273; + mmPA_SU_DEBUG_CNTL =$2280; + mmPA_SU_DEBUG_DATA =$2281; + mmPA_CL_CNTL_STATUS =$2284; + mmPA_CL_ENHANCE =$2285; + mmPA_CL_RESET_DEBUG =$2286; + mmPA_SU_CNTL_STATUS =$2294; + mmPA_SC_FIFO_DEPTH_CNTL =$2295; + mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK =$22C0; + mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK =$22C1; + mmPA_SC_TRAP_SCREEN_HV_LOCK =$22C2; + mmPA_SC_FORCE_EOV_MAX_CNTS =$22C9; + mmCGTT_SC_CLK_CTRL =$22CA; + mmPA_SC_FIFO_SIZE =$22F3; + mmPA_SC_IF_FIFO_SIZE =$22F5; + mmPA_SC_DEBUG_CNTL =$22F6; + mmPA_SC_DEBUG_DATA =$22F7; + mmPA_SC_ENHANCE =$22FC; + mmSQ_CONFIG =$2300; + mmSQC_CONFIG =$2301; + mmSQ_RANDOM_WAVE_PRI =$2303; + mmSQ_REG_CREDITS =$2304; + mmSQ_FIFO_SIZES =$2305; + mmSQ_DSM_CNTL =$2306; + mmCC_SQC_BANK_DISABLE =$2307; + mmUSER_SQC_BANK_DISABLE =$2308; + mmSQ_DEBUG_STS_GLOBAL =$2309; + mmSH_MEM_BASES =$230A; + mmSH_MEM_APE1_BASE =$230B; + mmSH_MEM_APE1_LIMIT =$230C; + mmSH_MEM_CONFIG =$230D; + mmSQC_DSM_CNTL =$230F; + mmSQ_DEBUG_STS_GLOBAL2 =$2310; + mmSQ_DEBUG_STS_GLOBAL3 =$2311; + mmCC_GC_SHADER_RATE_CONFIG =$2312; + mmGC_USER_SHADER_RATE_CONFIG =$2313; + mmSQ_INTERRUPT_AUTO_MASK =$2314; + mmSQ_INTERRUPT_MSG_CTRL =$2315; + mmSQ_ALU_CLK_CTRL =$2360; + mmSQ_TEX_CLK_CTRL =$2361; + mmCGTT_SQ_CLK_CTRL =$2362; + mmCGTT_SQG_CLK_CTRL =$2363; + mmSQ_REG_TIMESTAMP =$2374; + mmSQ_CMD_TIMESTAMP =$2375; + mmSQ_IND_INDEX =$2378; + mmSQ_IND_DATA =$2379; + mmSQ_CMD =$237B; + mmSQ_TIME_HI =$237C; + mmSQ_TIME_LO =$237D; + mmSQ_DS_0 =$237F; + mmSQ_THREAD_TRACE_CNTR =$2390; + mmSQ_POWER_THROTTLE =$2396; + mmSQ_POWER_THROTTLE2 =$2397; + mmSQ_LB_CTR_CTRL =$2398; + mmSQ_LB_DATA_ALU_CYCLES =$2399; + mmSQ_LB_DATA_TEX_CYCLES =$239A; + mmSQ_LB_DATA_ALU_STALLS =$239B; + mmSQ_LB_DATA_TEX_STALLS =$239C; + mmSQC_EDC_CNT =$23A0; + mmSQ_EDC_SEC_CNT =$23A1; + mmSQ_EDC_DED_CNT =$23A2; + mmSQ_EDC_INFO =$23A3; + mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 =$23B0; + mmSQ_WREXEC_EXEC_HI =$23B1; + mmSQC_GATCL1_CNTL =$23B2; + mmSQC_ATC_EDC_GATCL1_CNT =$23B3; + mmSQ_BUF_RSRC_WORD0 =$23C0; + mmSQ_BUF_RSRC_WORD1 =$23C1; + mmSQ_BUF_RSRC_WORD2 =$23C2; + mmSQ_BUF_RSRC_WORD3 =$23C3; + mmSQ_IMG_RSRC_WORD0 =$23C4; + mmSQ_IMG_RSRC_WORD1 =$23C5; + mmSQ_IMG_RSRC_WORD2 =$23C6; + mmSQ_IMG_RSRC_WORD3 =$23C7; + mmSQ_IMG_RSRC_WORD4 =$23C8; + mmSQ_IMG_RSRC_WORD5 =$23C9; + mmSQ_IMG_RSRC_WORD6 =$23CA; + mmSQ_IMG_RSRC_WORD7 =$23CB; + mmSQ_IMG_SAMP_WORD0 =$23CC; + mmSQ_IMG_SAMP_WORD1 =$23CD; + mmSQ_IMG_SAMP_WORD2 =$23CE; + mmSQ_IMG_SAMP_WORD3 =$23CF; + mmSQ_FLAT_SCRATCH_WORD0 =$23D0; + mmSQ_FLAT_SCRATCH_WORD1 =$23D1; + mmSQ_M0_GPR_IDX_WORD =$23D2; + mmCGTT_SX_CLK_CTRL0 =$240C; + mmCGTT_SX_CLK_CTRL1 =$240D; + mmCGTT_SX_CLK_CTRL2 =$240E; + mmCGTT_SX_CLK_CTRL3 =$240F; + mmCGTT_SX_CLK_CTRL4 =$2410; + mmSX_DEBUG_BUSY =$2414; + mmSX_DEBUG_BUSY_2 =$2415; + mmSX_DEBUG_BUSY_3 =$2416; + mmSX_DEBUG_BUSY_4 =$2417; + mmSX_DEBUG_1 =$2418; + mmSPI_PS_MAX_WAVE_ID =$243A; + mmSPI_START_PHASE =$243B; + mmSPI_GFX_CNTL =$243C; + mmSPI_CONFIG_CNTL =$2440; + mmSPI_DEBUG_CNTL =$2441; + mmSPI_DEBUG_READ =$2442; + mmSPI_DSM_CNTL =$2443; + mmSPI_EDC_CNT =$2444; + mmSPI_CONFIG_CNTL_1 =$244F; + mmSPI_DEBUG_BUSY =$2450; + mmSPI_CONFIG_CNTL_2 =$2451; + mmCGTS_TCC_DISABLE =$2452; + mmCGTS_USER_TCC_DISABLE =$2453; + mmCGTS_SM_CTRL_REG =$2454; + mmCGTS_RD_CTRL_REG =$2455; + mmCGTS_RD_REG =$2456; + mmCGTT_PC_CLK_CTRL =$24A8; + mmCGTT_BCI_CLK_CTRL =$24A9; + mmSPI_WF_LIFETIME_CNTL =$24AA; + mmSPI_WF_LIFETIME_LIMIT_0 =$24AB; + mmSPI_WF_LIFETIME_LIMIT_1 =$24AC; + mmSPI_WF_LIFETIME_LIMIT_2 =$24AD; + mmSPI_WF_LIFETIME_LIMIT_3 =$24AE; + mmSPI_WF_LIFETIME_LIMIT_4 =$24AF; + mmSPI_WF_LIFETIME_LIMIT_5 =$24B0; + mmSPI_WF_LIFETIME_LIMIT_6 =$24B1; + mmSPI_WF_LIFETIME_LIMIT_7 =$24B2; + mmSPI_WF_LIFETIME_LIMIT_8 =$24B3; + mmSPI_WF_LIFETIME_LIMIT_9 =$24B4; + mmSPI_WF_LIFETIME_STATUS_0 =$24B5; + mmSPI_WF_LIFETIME_STATUS_1 =$24B6; + mmSPI_WF_LIFETIME_STATUS_2 =$24B7; + mmSPI_WF_LIFETIME_STATUS_3 =$24B8; + mmSPI_WF_LIFETIME_STATUS_4 =$24B9; + mmSPI_WF_LIFETIME_STATUS_5 =$24BA; + mmSPI_WF_LIFETIME_STATUS_6 =$24BB; + mmSPI_WF_LIFETIME_STATUS_7 =$24BC; + mmSPI_WF_LIFETIME_STATUS_8 =$24BD; + mmSPI_WF_LIFETIME_STATUS_9 =$24BE; + mmSPI_WF_LIFETIME_STATUS_10 =$24BF; + mmSPI_WF_LIFETIME_STATUS_11 =$24C0; + mmSPI_WF_LIFETIME_STATUS_12 =$24C1; + mmSPI_WF_LIFETIME_STATUS_13 =$24C2; + mmSPI_WF_LIFETIME_STATUS_14 =$24C3; + mmSPI_WF_LIFETIME_STATUS_15 =$24C4; + mmSPI_WF_LIFETIME_STATUS_16 =$24C5; + mmSPI_WF_LIFETIME_STATUS_17 =$24C6; + mmSPI_WF_LIFETIME_STATUS_18 =$24C7; + mmSPI_WF_LIFETIME_STATUS_19 =$24C8; + mmSPI_WF_LIFETIME_STATUS_20 =$24C9; + mmSPI_WF_LIFETIME_DEBUG =$24CA; + mmSPI_SLAVE_DEBUG_BUSY =$24D3; + mmSPI_LB_CTR_CTRL =$24D4; + mmSPI_LB_CU_MASK =$24D5; + mmSPI_LB_DATA_REG =$24D6; + mmSPI_PG_ENABLE_STATIC_CU_MASK =$24D7; + mmSPI_GDS_CREDITS =$24D8; + mmSPI_SX_EXPORT_BUFFER_SIZES =$24D9; + mmSPI_SX_SCOREBOARD_BUFFER_SIZES =$24DA; + mmSPI_CSQ_WF_ACTIVE_STATUS =$24DB; + mmSPI_CSQ_WF_ACTIVE_COUNT_0 =$24DC; + mmSPI_CSQ_WF_ACTIVE_COUNT_1 =$24DD; + mmSPI_CSQ_WF_ACTIVE_COUNT_2 =$24DE; + mmSPI_CSQ_WF_ACTIVE_COUNT_3 =$24DF; + mmSPI_CSQ_WF_ACTIVE_COUNT_4 =$24E0; + mmSPI_CSQ_WF_ACTIVE_COUNT_5 =$24E1; + mmSPI_CSQ_WF_ACTIVE_COUNT_6 =$24E2; + mmSPI_CSQ_WF_ACTIVE_COUNT_7 =$24E3; + mmBCI_DEBUG_READ =$24EB; + mmSPI_P0_TRAP_SCREEN_PSBA_LO =$24EC; + mmSPI_P0_TRAP_SCREEN_PSBA_HI =$24ED; + mmSPI_P0_TRAP_SCREEN_PSMA_LO =$24EE; + mmSPI_P0_TRAP_SCREEN_PSMA_HI =$24EF; + mmSPI_P0_TRAP_SCREEN_GPR_MIN =$24F0; + mmSPI_P1_TRAP_SCREEN_PSBA_LO =$24F1; + mmSPI_P1_TRAP_SCREEN_PSBA_HI =$24F2; + mmSPI_P1_TRAP_SCREEN_PSMA_LO =$24F3; + mmSPI_P1_TRAP_SCREEN_PSMA_HI =$24F4; + mmSPI_P1_TRAP_SCREEN_GPR_MIN =$24F5; + mmTD_CNTL =$2525; + mmTD_STATUS =$2526; + mmTD_CGTT_CTRL =$2527; + mmTD_DEBUG_INDEX =$2528; + mmTD_DEBUG_DATA =$2529; + mmTD_DSM_CNTL =$252F; + mmTD_SCRATCH =$2533; + mmTA_CNTL =$2541; + mmTA_CNTL_AUX =$2542; + mmTA_RESERVED_010C =$2543; + mmTA_CGTT_CTRL =$2544; + mmTA_STATUS =$2548; + mmTA_DEBUG_INDEX =$254C; + mmTA_DEBUG_DATA =$254D; + mmTA_SCRATCH =$2564; + mmSH_HIDDEN_PRIVATE_BASE_VMID =$2580; + mmSH_STATIC_MEM_CONFIG =$2581; + mmGDS_CONFIG =$25C0; + mmGDS_CNTL_STATUS =$25C1; + mmGDS_ENHANCE2 =$25C2; + mmGDS_PROTECTION_FAULT =$25C3; + mmGDS_VM_PROTECTION_FAULT =$25C4; + mmGDS_EDC_CNT =$25C5; + mmGDS_EDC_GRBM_CNT =$25C6; + mmGDS_EDC_OA_DED =$25C7; + mmGDS_DEBUG_CNTL =$25C8; + mmGDS_DEBUG_DATA =$25C9; + mmGDS_DSM_CNTL =$25CA; + mmCGTT_GDS_CLK_CTRL =$25DD; + mmGDS_SECDED_CNT =$25E2; + mmGDS_GRBM_SECDED_CNT =$25E3; + mmGDS_OA_DED =$25E4; + mmDB_DEBUG =$260C; + mmDB_DEBUG2 =$260D; + mmDB_DEBUG3 =$260E; + mmDB_DEBUG4 =$260F; + mmDB_CREDIT_LIMIT =$2614; + mmDB_WATERMARKS =$2615; + mmDB_SUBTILE_CONTROL =$2616; + mmDB_FREE_CACHELINES =$2617; + mmDB_FIFO_DEPTH1 =$2618; + mmDB_FIFO_DEPTH2 =$2619; + mmDB_CGTT_CLK_CTRL_0 =$261A; + mmDB_RING_CONTROL =$261B; + mmDB_READ_DEBUG_0 =$2620; + mmDB_READ_DEBUG_1 =$2621; + mmDB_READ_DEBUG_2 =$2622; + mmDB_READ_DEBUG_3 =$2623; + mmDB_READ_DEBUG_4 =$2624; + mmDB_READ_DEBUG_5 =$2625; + mmDB_READ_DEBUG_6 =$2626; + mmDB_READ_DEBUG_7 =$2627; + mmDB_READ_DEBUG_8 =$2628; + mmDB_READ_DEBUG_9 =$2629; + mmDB_READ_DEBUG_A =$262A; + mmDB_READ_DEBUG_B =$262B; + mmDB_READ_DEBUG_C =$262C; + mmDB_READ_DEBUG_D =$262D; + mmDB_READ_DEBUG_E =$262E; + mmDB_READ_DEBUG_F =$262F; + mmCC_RB_REDUNDANCY =$263C; + mmCC_RB_BACKEND_DISABLE =$263D; + mmGB_ADDR_CONFIG =$263E; + mmGB_BACKEND_MAP =$263F; + mmGB_GPU_ID =$2640; + mmCC_RB_DAISY_CHAIN =$2641; + mmGB_TILE_MODE0 =$2644; + mmGB_TILE_MODE1 =$2645; + mmGB_TILE_MODE2 =$2646; + mmGB_TILE_MODE3 =$2647; + mmGB_TILE_MODE4 =$2648; + mmGB_TILE_MODE5 =$2649; + mmGB_TILE_MODE6 =$264A; + mmGB_TILE_MODE7 =$264B; + mmGB_TILE_MODE8 =$264C; + mmGB_TILE_MODE9 =$264D; + mmGB_TILE_MODE10 =$264E; + mmGB_TILE_MODE11 =$264F; + mmGB_TILE_MODE12 =$2650; + mmGB_TILE_MODE13 =$2651; + mmGB_TILE_MODE14 =$2652; + mmGB_TILE_MODE15 =$2653; + mmGB_TILE_MODE16 =$2654; + mmGB_TILE_MODE17 =$2655; + mmGB_TILE_MODE18 =$2656; + mmGB_TILE_MODE19 =$2657; + mmGB_TILE_MODE20 =$2658; + mmGB_TILE_MODE21 =$2659; + mmGB_TILE_MODE22 =$265A; + mmGB_TILE_MODE23 =$265B; + mmGB_TILE_MODE24 =$265C; + mmGB_TILE_MODE25 =$265D; + mmGB_TILE_MODE26 =$265E; + mmGB_TILE_MODE27 =$265F; + mmGB_TILE_MODE28 =$2660; + mmGB_TILE_MODE29 =$2661; + mmGB_TILE_MODE30 =$2662; + mmGB_TILE_MODE31 =$2663; + mmGB_MACROTILE_MODE0 =$2664; + mmGB_MACROTILE_MODE1 =$2665; + mmGB_MACROTILE_MODE2 =$2666; + mmGB_MACROTILE_MODE3 =$2667; + mmGB_MACROTILE_MODE4 =$2668; + mmGB_MACROTILE_MODE5 =$2669; + mmGB_MACROTILE_MODE6 =$266A; + mmGB_MACROTILE_MODE7 =$266B; + mmGB_MACROTILE_MODE8 =$266C; + mmGB_MACROTILE_MODE9 =$266D; + mmGB_MACROTILE_MODE10 =$266E; + mmGB_MACROTILE_MODE11 =$266F; + mmGB_MACROTILE_MODE12 =$2670; + mmGB_MACROTILE_MODE13 =$2671; + mmGB_MACROTILE_MODE14 =$2672; + mmGB_MACROTILE_MODE15 =$2673; + mmCB_HW_CONTROL_3 =$2683; + mmCB_HW_CONTROL =$2684; + mmCB_HW_CONTROL_1 =$2685; + mmCB_HW_CONTROL_2 =$2686; + mmCB_DCC_CONFIG =$2687; + mmCB_PERFCOUNTER0_SELECT0 =$2688; + mmCB_PERFCOUNTER1_SELECT0 =$268A; + mmCB_PERFCOUNTER1_SELECT1 =$268B; + mmCB_PERFCOUNTER2_SELECT0 =$268C; + mmCB_PERFCOUNTER2_SELECT1 =$268D; + mmCB_PERFCOUNTER3_SELECT0 =$268E; + mmCB_PERFCOUNTER3_SELECT1 =$268F; + mmCB_CGTT_SCLK_CTRL =$2698; + mmCB_DEBUG_BUS_1 =$2699; + mmCB_DEBUG_BUS_2 =$269A; + mmCB_DEBUG_BUS_13 =$26A5; + mmCB_DEBUG_BUS_14 =$26A6; + mmCB_DEBUG_BUS_15 =$26A7; + mmCB_DEBUG_BUS_16 =$26A8; + mmCB_DEBUG_BUS_17 =$26A9; + mmCB_DEBUG_BUS_18 =$26AA; + mmCB_DEBUG_BUS_19 =$26AB; + mmCB_DEBUG_BUS_20 =$26AC; + mmCB_DEBUG_BUS_21 =$26AD; + mmCB_DEBUG_BUS_22 =$26AE; + mmGC_USER_RB_REDUNDANCY =$26DE; + mmGC_USER_RB_BACKEND_DISABLE =$26DF; + mmTCP_INVALIDATE =$2B00; + mmTCP_STATUS =$2B01; + mmTCP_CNTL =$2B02; + mmTCP_CHAN_STEER_LO =$2B03; + mmTCP_CHAN_STEER_HI =$2B04; + mmTCP_ADDR_CONFIG =$2B05; + mmTCP_CREDIT =$2B06; + mmCGTT_TCP_CLK_CTRL =$2B15; + mmTCP_BUFFER_ADDR_HASH_CNTL =$2B16; + mmTCP_EDC_CNT =$2B17; + mmTC_CFG_L1_LOAD_POLICY0 =$2B1A; + mmTC_CFG_L1_LOAD_POLICY1 =$2B1B; + mmTC_CFG_L1_STORE_POLICY =$2B1C; + mmTC_CFG_L2_LOAD_POLICY0 =$2B1D; + mmTC_CFG_L2_LOAD_POLICY1 =$2B1E; + mmTC_CFG_L2_STORE_POLICY0 =$2B1F; + mmTC_CFG_L2_STORE_POLICY1 =$2B20; + mmTC_CFG_L2_ATOMIC_POLICY =$2B21; + mmTC_CFG_L1_VOLATILE =$2B22; + mmTC_CFG_L2_VOLATILE =$2B23; + mmCGTT_TCI_CLK_CTRL =$2B60; + mmTCI_STATUS =$2B61; + mmTCI_CNTL_1 =$2B62; + mmTCI_CNTL_2 =$2B63; + mmTCC_CTRL =$2B80; + mmTCC_CGTT_SCLK_CTRL =$2B81; + mmTCC_EDC_CNT =$2B82; + mmTCC_REDUNDANCY =$2B83; + mmTCC_EXE_DISABLE =$2B84; + mmTCC_DSM_CNTL =$2B85; + mmTCA_CTRL =$2BC0; + mmTCA_CGTT_SCLK_CTRL =$2BC1; + mmSPI_SHADER_TBA_LO_PS =$2C00; + mmSPI_SHADER_TBA_HI_PS =$2C01; + mmSPI_SHADER_TMA_LO_PS =$2C02; + mmSPI_SHADER_TMA_HI_PS =$2C03; + mmSPI_SHADER_PGM_RSRC3_PS =$2C07; + mmSPI_SHADER_PGM_LO_PS =$2C08; + mmSPI_SHADER_PGM_HI_PS =$2C09; + mmSPI_SHADER_PGM_RSRC1_PS =$2C0A; + mmSPI_SHADER_PGM_RSRC2_PS =$2C0B; + mmSPI_SHADER_USER_DATA_PS_0 =$2C0C; + mmSPI_SHADER_USER_DATA_PS_1 =$2C0D; + mmSPI_SHADER_USER_DATA_PS_2 =$2C0E; + mmSPI_SHADER_USER_DATA_PS_3 =$2C0F; + mmSPI_SHADER_USER_DATA_PS_4 =$2C10; + mmSPI_SHADER_USER_DATA_PS_5 =$2C11; + mmSPI_SHADER_USER_DATA_PS_6 =$2C12; + mmSPI_SHADER_USER_DATA_PS_7 =$2C13; + mmSPI_SHADER_USER_DATA_PS_8 =$2C14; + mmSPI_SHADER_USER_DATA_PS_9 =$2C15; + mmSPI_SHADER_USER_DATA_PS_10 =$2C16; + mmSPI_SHADER_USER_DATA_PS_11 =$2C17; + mmSPI_SHADER_USER_DATA_PS_12 =$2C18; + mmSPI_SHADER_USER_DATA_PS_13 =$2C19; + mmSPI_SHADER_USER_DATA_PS_14 =$2C1A; + mmSPI_SHADER_USER_DATA_PS_15 =$2C1B; + mmSPI_SHADER_TBA_LO_VS =$2C40; + mmSPI_SHADER_TBA_HI_VS =$2C41; + mmSPI_SHADER_TMA_LO_VS =$2C42; + mmSPI_SHADER_TMA_HI_VS =$2C43; + mmSPI_SHADER_PGM_RSRC3_VS =$2C46; + mmSPI_SHADER_LATE_ALLOC_VS =$2C47; + mmSPI_SHADER_PGM_LO_VS =$2C48; + mmSPI_SHADER_PGM_HI_VS =$2C49; + mmSPI_SHADER_PGM_RSRC1_VS =$2C4A; + mmSPI_SHADER_PGM_RSRC2_VS =$2C4B; + mmSPI_SHADER_USER_DATA_VS_0 =$2C4C; + mmSPI_SHADER_USER_DATA_VS_1 =$2C4D; + mmSPI_SHADER_USER_DATA_VS_2 =$2C4E; + mmSPI_SHADER_USER_DATA_VS_3 =$2C4F; + mmSPI_SHADER_USER_DATA_VS_4 =$2C50; + mmSPI_SHADER_USER_DATA_VS_5 =$2C51; + mmSPI_SHADER_USER_DATA_VS_6 =$2C52; + mmSPI_SHADER_USER_DATA_VS_7 =$2C53; + mmSPI_SHADER_USER_DATA_VS_8 =$2C54; + mmSPI_SHADER_USER_DATA_VS_9 =$2C55; + mmSPI_SHADER_USER_DATA_VS_10 =$2C56; + mmSPI_SHADER_USER_DATA_VS_11 =$2C57; + mmSPI_SHADER_USER_DATA_VS_12 =$2C58; + mmSPI_SHADER_USER_DATA_VS_13 =$2C59; + mmSPI_SHADER_USER_DATA_VS_14 =$2C5A; + mmSPI_SHADER_USER_DATA_VS_15 =$2C5B; + mmSPI_SHADER_PGM_RSRC2_ES_VS =$2C7C; + mmSPI_SHADER_PGM_RSRC2_LS_VS =$2C7D; + mmSPI_SHADER_TBA_LO_GS =$2C80; + mmSPI_SHADER_TBA_HI_GS =$2C81; + mmSPI_SHADER_TMA_LO_GS =$2C82; + mmSPI_SHADER_TMA_HI_GS =$2C83; + mmSPI_SHADER_PGM_RSRC3_GS =$2C87; + mmSPI_SHADER_PGM_LO_GS =$2C88; + mmSPI_SHADER_PGM_HI_GS =$2C89; + mmSPI_SHADER_PGM_RSRC1_GS =$2C8A; + mmSPI_SHADER_PGM_RSRC2_GS =$2C8B; + mmSPI_SHADER_USER_DATA_GS_0 =$2C8C; + mmSPI_SHADER_USER_DATA_GS_1 =$2C8D; + mmSPI_SHADER_USER_DATA_GS_2 =$2C8E; + mmSPI_SHADER_USER_DATA_GS_3 =$2C8F; + mmSPI_SHADER_USER_DATA_GS_4 =$2C90; + mmSPI_SHADER_USER_DATA_GS_5 =$2C91; + mmSPI_SHADER_USER_DATA_GS_6 =$2C92; + mmSPI_SHADER_USER_DATA_GS_7 =$2C93; + mmSPI_SHADER_USER_DATA_GS_8 =$2C94; + mmSPI_SHADER_USER_DATA_GS_9 =$2C95; + mmSPI_SHADER_USER_DATA_GS_10 =$2C96; + mmSPI_SHADER_USER_DATA_GS_11 =$2C97; + mmSPI_SHADER_USER_DATA_GS_12 =$2C98; + mmSPI_SHADER_USER_DATA_GS_13 =$2C99; + mmSPI_SHADER_USER_DATA_GS_14 =$2C9A; + mmSPI_SHADER_USER_DATA_GS_15 =$2C9B; + mmSPI_SHADER_PGM_RSRC2_ES_GS =$2CBC; + mmSPI_SHADER_TBA_LO_ES =$2CC0; + mmSPI_SHADER_TBA_HI_ES =$2CC1; + mmSPI_SHADER_TMA_LO_ES =$2CC2; + mmSPI_SHADER_TMA_HI_ES =$2CC3; + mmSPI_SHADER_PGM_RSRC3_ES =$2CC7; + mmSPI_SHADER_PGM_LO_ES =$2CC8; + mmSPI_SHADER_PGM_HI_ES =$2CC9; + mmSPI_SHADER_PGM_RSRC1_ES =$2CCA; + mmSPI_SHADER_PGM_RSRC2_ES =$2CCB; + mmSPI_SHADER_USER_DATA_ES_0 =$2CCC; + mmSPI_SHADER_USER_DATA_ES_1 =$2CCD; + mmSPI_SHADER_USER_DATA_ES_2 =$2CCE; + mmSPI_SHADER_USER_DATA_ES_3 =$2CCF; + mmSPI_SHADER_USER_DATA_ES_4 =$2CD0; + mmSPI_SHADER_USER_DATA_ES_5 =$2CD1; + mmSPI_SHADER_USER_DATA_ES_6 =$2CD2; + mmSPI_SHADER_USER_DATA_ES_7 =$2CD3; + mmSPI_SHADER_USER_DATA_ES_8 =$2CD4; + mmSPI_SHADER_USER_DATA_ES_9 =$2CD5; + mmSPI_SHADER_USER_DATA_ES_10 =$2CD6; + mmSPI_SHADER_USER_DATA_ES_11 =$2CD7; + mmSPI_SHADER_USER_DATA_ES_12 =$2CD8; + mmSPI_SHADER_USER_DATA_ES_13 =$2CD9; + mmSPI_SHADER_USER_DATA_ES_14 =$2CDA; + mmSPI_SHADER_USER_DATA_ES_15 =$2CDB; + mmSPI_SHADER_PGM_RSRC2_LS_ES =$2CFD; + mmSPI_SHADER_TBA_LO_HS =$2D00; + mmSPI_SHADER_TBA_HI_HS =$2D01; + mmSPI_SHADER_TMA_LO_HS =$2D02; + mmSPI_SHADER_TMA_HI_HS =$2D03; + mmSPI_SHADER_PGM_RSRC3_HS =$2D07; + mmSPI_SHADER_PGM_LO_HS =$2D08; + mmSPI_SHADER_PGM_HI_HS =$2D09; + mmSPI_SHADER_PGM_RSRC1_HS =$2D0A; + mmSPI_SHADER_PGM_RSRC2_HS =$2D0B; + mmSPI_SHADER_USER_DATA_HS_0 =$2D0C; + mmSPI_SHADER_USER_DATA_HS_1 =$2D0D; + mmSPI_SHADER_USER_DATA_HS_2 =$2D0E; + mmSPI_SHADER_USER_DATA_HS_3 =$2D0F; + mmSPI_SHADER_USER_DATA_HS_4 =$2D10; + mmSPI_SHADER_USER_DATA_HS_5 =$2D11; + mmSPI_SHADER_USER_DATA_HS_6 =$2D12; + mmSPI_SHADER_USER_DATA_HS_7 =$2D13; + mmSPI_SHADER_USER_DATA_HS_8 =$2D14; + mmSPI_SHADER_USER_DATA_HS_9 =$2D15; + mmSPI_SHADER_USER_DATA_HS_10 =$2D16; + mmSPI_SHADER_USER_DATA_HS_11 =$2D17; + mmSPI_SHADER_USER_DATA_HS_12 =$2D18; + mmSPI_SHADER_USER_DATA_HS_13 =$2D19; + mmSPI_SHADER_USER_DATA_HS_14 =$2D1A; + mmSPI_SHADER_USER_DATA_HS_15 =$2D1B; + mmSPI_SHADER_PGM_RSRC2_LS_HS =$2D3D; + mmSPI_SHADER_TBA_LO_LS =$2D40; + mmSPI_SHADER_TBA_HI_LS =$2D41; + mmSPI_SHADER_TMA_LO_LS =$2D42; + mmSPI_SHADER_TMA_HI_LS =$2D43; + mmSPI_SHADER_PGM_RSRC3_LS =$2D47; + mmSPI_SHADER_PGM_LO_LS =$2D48; + mmSPI_SHADER_PGM_HI_LS =$2D49; + mmSPI_SHADER_PGM_RSRC1_LS =$2D4A; + mmSPI_SHADER_PGM_RSRC2_LS =$2D4B; + mmSPI_SHADER_USER_DATA_LS_0 =$2D4C; + mmSPI_SHADER_USER_DATA_LS_1 =$2D4D; + mmSPI_SHADER_USER_DATA_LS_2 =$2D4E; + mmSPI_SHADER_USER_DATA_LS_3 =$2D4F; + mmSPI_SHADER_USER_DATA_LS_4 =$2D50; + mmSPI_SHADER_USER_DATA_LS_5 =$2D51; + mmSPI_SHADER_USER_DATA_LS_6 =$2D52; + mmSPI_SHADER_USER_DATA_LS_7 =$2D53; + mmSPI_SHADER_USER_DATA_LS_8 =$2D54; + mmSPI_SHADER_USER_DATA_LS_9 =$2D55; + mmSPI_SHADER_USER_DATA_LS_10 =$2D56; + mmSPI_SHADER_USER_DATA_LS_11 =$2D57; + mmSPI_SHADER_USER_DATA_LS_12 =$2D58; + mmSPI_SHADER_USER_DATA_LS_13 =$2D59; + mmSPI_SHADER_USER_DATA_LS_14 =$2D5A; + mmSPI_SHADER_USER_DATA_LS_15 =$2D5B; + mmCOMPUTE_DISPATCH_INITIATOR =$2E00; + mmCOMPUTE_DIM_X =$2E01; + mmCOMPUTE_DIM_Y =$2E02; + mmCOMPUTE_DIM_Z =$2E03; + mmCOMPUTE_START_X =$2E04; + mmCOMPUTE_START_Y =$2E05; + mmCOMPUTE_START_Z =$2E06; + mmCOMPUTE_NUM_THREAD_X =$2E07; + mmCOMPUTE_NUM_THREAD_Y =$2E08; + mmCOMPUTE_NUM_THREAD_Z =$2E09; + mmCOMPUTE_PIPELINESTAT_ENABLE =$2E0A; + mmCOMPUTE_PERFCOUNT_ENABLE =$2E0B; + mmCOMPUTE_PGM_LO =$2E0C; + mmCOMPUTE_PGM_HI =$2E0D; + mmCOMPUTE_TBA_LO =$2E0E; + mmCOMPUTE_TBA_HI =$2E0F; + mmCOMPUTE_TMA_LO =$2E10; + mmCOMPUTE_TMA_HI =$2E11; + mmCOMPUTE_PGM_RSRC1 =$2E12; + mmCOMPUTE_PGM_RSRC2 =$2E13; + mmCOMPUTE_VMID =$2E14; + mmCOMPUTE_RESOURCE_LIMITS =$2E15; + mmCOMPUTE_STATIC_THREAD_MGMT_SE0 =$2E16; + mmCOMPUTE_STATIC_THREAD_MGMT_SE1 =$2E17; + mmCOMPUTE_TMPRING_SIZE =$2E18; + mmCOMPUTE_STATIC_THREAD_MGMT_SE2 =$2E19; + mmCOMPUTE_STATIC_THREAD_MGMT_SE3 =$2E1A; + mmCOMPUTE_RESTART_X =$2E1B; + mmCOMPUTE_RESTART_Y =$2E1C; + mmCOMPUTE_RESTART_Z =$2E1D; + mmCOMPUTE_THREAD_TRACE_ENABLE =$2E1E; + mmCOMPUTE_MISC_RESERVED =$2E1F; + mmCOMPUTE_DISPATCH_ID =$2E20; + mmCOMPUTE_THREADGROUP_ID =$2E21; + mmCOMPUTE_RELAUNCH =$2E22; + mmCOMPUTE_WAVE_RESTORE_ADDR_LO =$2E23; + mmCOMPUTE_WAVE_RESTORE_ADDR_HI =$2E24; + mmCOMPUTE_WAVE_RESTORE_CONTROL =$2E25; + mmCOMPUTE_USER_DATA_0 =$2E40; + mmCOMPUTE_USER_DATA_1 =$2E41; + mmCOMPUTE_USER_DATA_2 =$2E42; + mmCOMPUTE_USER_DATA_3 =$2E43; + mmCOMPUTE_USER_DATA_4 =$2E44; + mmCOMPUTE_USER_DATA_5 =$2E45; + mmCOMPUTE_USER_DATA_6 =$2E46; + mmCOMPUTE_USER_DATA_7 =$2E47; + mmCOMPUTE_USER_DATA_8 =$2E48; + mmCOMPUTE_USER_DATA_9 =$2E49; + mmCOMPUTE_USER_DATA_10 =$2E4A; + mmCOMPUTE_USER_DATA_11 =$2E4B; + mmCOMPUTE_USER_DATA_12 =$2E4C; + mmCOMPUTE_USER_DATA_13 =$2E4D; + mmCOMPUTE_USER_DATA_14 =$2E4E; + mmCOMPUTE_USER_DATA_15 =$2E4F; + mmCOMPUTE_NOWHERE =$2E7F; + mmCP_DFY_CNTL =$3020; + mmCP_DFY_STAT =$3021; + mmCP_DFY_ADDR_HI =$3022; + mmCP_DFY_ADDR_LO =$3023; + mmCP_DFY_DATA_0 =$3024; + mmCP_DFY_DATA_1 =$3025; + mmCP_DFY_DATA_2 =$3026; + mmCP_DFY_DATA_3 =$3027; + mmCP_DFY_DATA_4 =$3028; + mmCP_DFY_DATA_5 =$3029; + mmCP_DFY_DATA_6 =$302A; + mmCP_DFY_DATA_7 =$302B; + mmCP_DFY_DATA_8 =$302C; + mmCP_DFY_DATA_9 =$302D; + mmCP_DFY_DATA_10 =$302E; + mmCP_DFY_DATA_11 =$302F; + mmCP_DFY_DATA_12 =$3030; + mmCP_DFY_DATA_13 =$3031; + mmCP_DFY_DATA_14 =$3032; + mmCP_DFY_DATA_15 =$3033; + mmCP_DFY_CMD =$3034; + mmCP_CPC_MGCG_SYNC_CNTL =$3036; + mmCP_VIRT_STATUS =$3038; + mmCP_RB0_BASE =$3040; + mmCP_RB0_CNTL =$3041; + mmCP_RB_RPTR_WR =$3042; + mmCP_RB0_RPTR_ADDR =$3043; + mmCP_RB0_RPTR_ADDR_HI =$3044; + mmCP_RB0_WPTR =$3045; + mmCP_RB_WPTR_POLL_ADDR_LO =$3046; + mmCP_RB_WPTR_POLL_ADDR_HI =$3047; + mmCP_INT_CNTL =$3049; + mmCP_INT_STATUS =$304A; + mmCP_DEVICE_ID =$304B; + mmCP_ME0_PIPE_PRIORITY_CNTS =$304C; + mmCP_ME0_PIPE0_PRIORITY =$304D; + mmCP_ME0_PIPE1_PRIORITY =$304E; + mmCP_ME0_PIPE2_PRIORITY =$304F; + mmCP_ENDIAN_SWAP =$3050; + mmCP_RB_VMID =$3051; + mmCP_ME0_PIPE0_VMID =$3052; + mmCP_ME0_PIPE1_VMID =$3053; + mmCP_RB_DOORBELL_CONTROL =$3059; + mmCP_RB_DOORBELL_RANGE_LOWER =$305A; + mmCP_RB_DOORBELL_RANGE_UPPER =$305B; + mmCP_MEC_DOORBELL_RANGE_LOWER =$305C; + mmCP_MEC_DOORBELL_RANGE_UPPER =$305D; + mmCP_RB1_BASE =$3060; + mmCP_RB1_CNTL =$3061; + mmCP_RB1_RPTR_ADDR =$3062; + mmCP_RB1_RPTR_ADDR_HI =$3063; + mmCP_RB1_WPTR =$3064; + mmCP_RB2_BASE =$3065; + mmCP_RB2_CNTL =$3066; + mmCP_RB2_RPTR_ADDR =$3067; + mmCP_RB2_RPTR_ADDR_HI =$3068; + mmCP_RB2_WPTR =$3069; + mmCP_INT_CNTL_RING0 =$306A; + mmCP_INT_CNTL_RING1 =$306B; + mmCP_INT_CNTL_RING2 =$306C; + mmCP_INT_STATUS_RING0 =$306D; + mmCP_INT_STATUS_RING1 =$306E; + mmCP_INT_STATUS_RING2 =$306F; + mmCP_PWR_CNTL =$3078; + mmCP_MEM_SLP_CNTL =$3079; + mmCP_ECC_FIRSTOCCURRENCE =$307A; + mmCP_ECC_FIRSTOCCURRENCE_RING0 =$307B; + mmCP_ECC_FIRSTOCCURRENCE_RING1 =$307C; + mmCP_ECC_FIRSTOCCURRENCE_RING2 =$307D; + mmGB_EDC_MODE =$307E; + mmCP_DEBUG =$307F; + mmCP_PQ_WPTR_POLL_CNTL =$3083; + mmCP_PQ_WPTR_POLL_CNTL1 =$3084; + mmCP_ME1_PIPE0_INT_CNTL =$3085; + mmCP_ME1_PIPE1_INT_CNTL =$3086; + mmCP_ME1_PIPE2_INT_CNTL =$3087; + mmCP_ME1_PIPE3_INT_CNTL =$3088; + mmCP_ME2_PIPE0_INT_CNTL =$3089; + mmCP_ME2_PIPE1_INT_CNTL =$308A; + mmCP_ME2_PIPE2_INT_CNTL =$308B; + mmCP_ME2_PIPE3_INT_CNTL =$308C; + mmCP_ME1_PIPE0_INT_STATUS =$308D; + mmCP_ME1_PIPE1_INT_STATUS =$308E; + mmCP_ME1_PIPE2_INT_STATUS =$308F; + mmCP_ME1_PIPE3_INT_STATUS =$3090; + mmCP_ME2_PIPE0_INT_STATUS =$3091; + mmCP_ME2_PIPE1_INT_STATUS =$3092; + mmCP_ME2_PIPE2_INT_STATUS =$3093; + mmCP_ME2_PIPE3_INT_STATUS =$3094; + mmCP_ME1_INT_STAT_DEBUG =$3095; + mmCP_ME2_INT_STAT_DEBUG =$3096; + mmCC_GC_EDC_CONFIG =$3098; + mmCP_ME1_PIPE_PRIORITY_CNTS =$3099; + mmCP_ME1_PIPE0_PRIORITY =$309A; + mmCP_ME1_PIPE1_PRIORITY =$309B; + mmCP_ME1_PIPE2_PRIORITY =$309C; + mmCP_ME1_PIPE3_PRIORITY =$309D; + mmCP_ME2_PIPE_PRIORITY_CNTS =$309E; + mmCP_ME2_PIPE0_PRIORITY =$309F; + mmCP_ME2_PIPE1_PRIORITY =$30A0; + mmCP_ME2_PIPE2_PRIORITY =$30A1; + mmCP_ME2_PIPE3_PRIORITY =$30A2; + mmCP_CE_PRGRM_CNTR_START =$30A3; + mmCP_PFP_PRGRM_CNTR_START =$30A4; + mmCP_ME_PRGRM_CNTR_START =$30A5; + mmCP_MEC1_PRGRM_CNTR_START =$30A6; + mmCP_MEC2_PRGRM_CNTR_START =$30A7; + mmCP_CE_INTR_ROUTINE_START =$30A8; + mmCP_PFP_INTR_ROUTINE_START =$30A9; + mmCP_ME_INTR_ROUTINE_START =$30AA; + mmCP_MEC1_INTR_ROUTINE_START =$30AB; + mmCP_MEC2_INTR_ROUTINE_START =$30AC; + mmCP_CONTEXT_CNTL =$30AD; + mmCP_MAX_CONTEXT =$30AE; + mmCP_IQ_WAIT_TIME1 =$30AF; + mmCP_IQ_WAIT_TIME2 =$30B0; + mmCP_RB0_BASE_HI =$30B1; + mmCP_RB1_BASE_HI =$30B2; + mmCP_VMID_RESET =$30B3; + mmCPC_INT_CNTL =$30B4; + mmCPC_INT_STATUS =$30B5; + mmCP_VMID_PREEMPT =$30B6; + mmCPC_INT_CNTX_ID =$30B7; + mmCP_PQ_STATUS =$30B8; + mmCP_CPC_IC_BASE_LO =$30B9; + mmCP_CPC_IC_BASE_HI =$30BA; + mmCP_CPC_IC_BASE_CNTL =$30BB; + mmCP_CPC_IC_OP_CNTL =$30BC; + mmCP_MEC1_F32_INT_DIS =$30BD; + mmCP_MEC2_F32_INT_DIS =$30BE; + mmCP_VMID_STATUS =$30BF; + mmRLC_LB_CNTL =$30C3; + mmRLC_SAVE_AND_RESTORE_BASE =$30C4; + mmRLC_LB_CNTR_MAX =$30C5; + mmRLC_LB_CNTR_INIT =$30C6; + mmRLC_DRIVER_CPDMA_STATUS =$30C7; + mmRLC_DEBUG_SELECT =$30C9; + mmRLC_DEBUG =$30CA; + mmRLC_GPU_CLOCK_COUNT_LSB =$30CE; + mmRLC_GPU_CLOCK_COUNT_MSB =$30CF; + mmRLC_CAPTURE_GPU_CLOCK_COUNT =$30D0; + mmRLC_MC_CNTL =$30D1; + mmRLC_UCODE_CNTL =$30D2; + mmRLC_STAT =$30D3; + mmRLC_GPU_CLOCK_32_RES_SEL =$30D4; + mmRLC_GPU_CLOCK_32 =$30D5; + mmRLC_SOFT_RESET_GPU =$30D6; + mmRLC_PG_CNTL =$30D7; + mmRLC_MEM_SLP_CNTL =$30D8; + mmRLC_PERFMON_CNTL =$30D9; + mmRLC_PERFCOUNTER0_SELECT =$30DA; + mmRLC_PERFCOUNTER1_SELECT =$30DD; + mmCGTT_RLC_CLK_CTRL =$30E0; + mmRLC_LOAD_BALANCE_CNTR =$30F6; + mmRLC_CGTT_MGCG_OVERRIDE =$3100; + mmRLC_CGCG_CGLS_CTRL =$3101; + mmRLC_CGCG_RAMP_CTRL =$3102; + mmRLC_DYN_PG_STATUS =$3103; + mmRLC_DYN_PG_REQUEST =$3104; + mmRLC_CU_STATUS =$3106; + mmRLC_LB_INIT_CU_MASK =$3107; + mmRLC_LB_ALWAYS_ACTIVE_CU_MASK =$3108; + mmRLC_LB_PARAMS =$3109; + mmRLC_THREAD1_DELAY =$310A; + mmRLC_PG_ALWAYS_ON_CU_MASK =$310B; + mmRLC_MAX_PG_CU =$310C; + mmRLC_AUTO_PG_CTRL =$310D; + mmRLC_SMU_GRBM_REG_SAVE_CTRL =$310E; + mmRLC_SMU_PG_CTRL =$310F; + mmRLC_SMU_PG_WAKE_UP_CTRL =$3110; + mmRLC_SERDES_RD_MASTER_INDEX =$3111; + mmRLC_SERDES_RD_DATA_0 =$3112; + mmRLC_SERDES_RD_DATA_1 =$3113; + mmRLC_SERDES_RD_DATA_2 =$3114; + mmRLC_SERDES_WR_CTRL =$3117; + mmRLC_SERDES_WR_DATA =$3118; + mmSPI_ARB_PRIORITY =$31C0; + mmSPI_ARB_CYCLES_0 =$31C1; + mmSPI_ARB_CYCLES_1 =$31C2; + mmSPI_CDBG_SYS_GFX =$31C3; + mmSPI_CDBG_SYS_HP3D =$31C4; + mmSPI_CDBG_SYS_CS0 =$31C5; + mmSPI_CDBG_SYS_CS1 =$31C6; + mmSPI_WCL_PIPE_PERCENT_GFX =$31C7; + mmSPI_WCL_PIPE_PERCENT_HP3D =$31C8; + mmSPI_WCL_PIPE_PERCENT_CS0 =$31C9; + mmSPI_WCL_PIPE_PERCENT_CS1 =$31CA; + mmSPI_WCL_PIPE_PERCENT_CS2 =$31CB; + mmSPI_WCL_PIPE_PERCENT_CS3 =$31CC; + mmSPI_WCL_PIPE_PERCENT_CS4 =$31CD; + mmSPI_WCL_PIPE_PERCENT_CS5 =$31CE; + mmSPI_WCL_PIPE_PERCENT_CS6 =$31CF; + mmSPI_WCL_PIPE_PERCENT_CS7 =$31D0; + mmSPI_GDBG_WAVE_CNTL =$31D1; + mmSPI_GDBG_TRAP_CONFIG =$31D2; + mmSPI_GDBG_TRAP_MASK =$31D3; + mmSPI_GDBG_TBA_LO =$31D4; + mmSPI_GDBG_TBA_HI =$31D5; + mmSPI_GDBG_TMA_LO =$31D6; + mmSPI_GDBG_TMA_HI =$31D7; + mmSPI_GDBG_TRAP_DATA0 =$31D8; + mmSPI_GDBG_TRAP_DATA1 =$31D9; + mmSPI_RESET_DEBUG =$31DA; + mmSPI_COMPUTE_QUEUE_RESET =$31DB; + mmSPI_RESOURCE_RESERVE_CU_0 =$31DC; + mmSPI_RESOURCE_RESERVE_CU_1 =$31DD; + mmSPI_RESOURCE_RESERVE_CU_2 =$31DE; + mmSPI_RESOURCE_RESERVE_CU_3 =$31DF; + mmSPI_RESOURCE_RESERVE_CU_4 =$31E0; + mmSPI_RESOURCE_RESERVE_CU_5 =$31E1; + mmSPI_RESOURCE_RESERVE_CU_6 =$31E2; + mmSPI_RESOURCE_RESERVE_CU_7 =$31E3; + mmSPI_RESOURCE_RESERVE_CU_8 =$31E4; + mmSPI_RESOURCE_RESERVE_CU_9 =$31E5; + mmSPI_RESOURCE_RESERVE_EN_CU_0 =$31E6; + mmSPI_RESOURCE_RESERVE_EN_CU_1 =$31E7; + mmSPI_RESOURCE_RESERVE_EN_CU_2 =$31E8; + mmSPI_RESOURCE_RESERVE_EN_CU_3 =$31E9; + mmSPI_RESOURCE_RESERVE_EN_CU_4 =$31EA; + mmSPI_RESOURCE_RESERVE_EN_CU_5 =$31EB; + mmSPI_RESOURCE_RESERVE_EN_CU_6 =$31EC; + mmSPI_RESOURCE_RESERVE_EN_CU_7 =$31ED; + mmSPI_RESOURCE_RESERVE_EN_CU_8 =$31EE; + mmSPI_RESOURCE_RESERVE_EN_CU_9 =$31EF; + mmSPI_RESOURCE_RESERVE_CU_10 =$31F0; + mmSPI_RESOURCE_RESERVE_CU_11 =$31F1; + mmSPI_RESOURCE_RESERVE_EN_CU_10 =$31F2; + mmSPI_RESOURCE_RESERVE_EN_CU_11 =$31F3; + mmSPI_RESOURCE_RESERVE_CU_12 =$31F4; + mmSPI_RESOURCE_RESERVE_CU_13 =$31F5; + mmSPI_RESOURCE_RESERVE_CU_14 =$31F6; + mmSPI_RESOURCE_RESERVE_CU_15 =$31F7; + mmSPI_RESOURCE_RESERVE_EN_CU_12 =$31F8; + mmSPI_RESOURCE_RESERVE_EN_CU_13 =$31F9; + mmSPI_RESOURCE_RESERVE_EN_CU_14 =$31FA; + mmSPI_RESOURCE_RESERVE_EN_CU_15 =$31FB; + mmSPI_COMPUTE_WF_CTX_SAVE =$31FC; + mmCP_HPD_ROQ_OFFSETS =$3240; + mmCP_HPD_STATUS0 =$3241; + mmCP_MQD_BASE_ADDR =$3245; + mmCP_MQD_BASE_ADDR_HI =$3246; + mmCP_HQD_ACTIVE =$3247; + mmCP_HQD_VMID =$3248; + mmCP_HQD_PERSISTENT_STATE =$3249; + mmCP_HQD_PIPE_PRIORITY =$324A; + mmCP_HQD_QUEUE_PRIORITY =$324B; + mmCP_HQD_QUANTUM =$324C; + mmCP_HQD_PQ_BASE =$324D; + mmCP_HQD_PQ_BASE_HI =$324E; + mmCP_HQD_PQ_RPTR =$324F; + mmCP_HQD_PQ_RPTR_REPORT_ADDR =$3250; + mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI =$3251; + mmCP_HQD_PQ_WPTR_POLL_ADDR =$3252; + mmCP_HQD_PQ_WPTR_POLL_ADDR_HI =$3253; + mmCP_HQD_PQ_DOORBELL_CONTROL =$3254; + mmCP_HQD_PQ_WPTR =$3255; + mmCP_HQD_PQ_CONTROL =$3256; + mmCP_HQD_IB_BASE_ADDR =$3257; + mmCP_HQD_IB_BASE_ADDR_HI =$3258; + mmCP_HQD_IB_RPTR =$3259; + mmCP_HQD_IB_CONTROL =$325A; + mmCP_HQD_IQ_TIMER =$325B; + mmCP_HQD_IQ_RPTR =$325C; + mmCP_HQD_DEQUEUE_REQUEST =$325D; + mmCP_HQD_DMA_OFFLOAD =$325E; + mmCP_HQD_SEMA_CMD =$325F; + mmCP_HQD_MSG_TYPE =$3260; + mmCP_HQD_ATOMIC0_PREOP_LO =$3261; + mmCP_HQD_ATOMIC0_PREOP_HI =$3262; + mmCP_HQD_ATOMIC1_PREOP_LO =$3263; + mmCP_HQD_ATOMIC1_PREOP_HI =$3264; + mmCP_HQD_HQ_SCHEDULER0 =$3265; + mmCP_HQD_HQ_SCHEDULER1 =$3266; + mmCP_MQD_CONTROL =$3267; + mmCP_HQD_HQ_STATUS1 =$3268; + mmCP_HQD_HQ_CONTROL1 =$3269; + mmCP_HQD_EOP_BASE_ADDR =$326A; + mmCP_HQD_EOP_BASE_ADDR_HI =$326B; + mmCP_HQD_EOP_CONTROL =$326C; + mmCP_HQD_EOP_RPTR =$326D; + mmCP_HQD_EOP_WPTR =$326E; + mmCP_HQD_EOP_EVENTS =$326F; + mmCP_HQD_CTX_SAVE_BASE_ADDR_LO =$3270; + mmCP_HQD_CTX_SAVE_BASE_ADDR_HI =$3271; + mmCP_HQD_CTX_SAVE_CONTROL =$3272; + mmCP_HQD_CNTL_STACK_OFFSET =$3273; + mmCP_HQD_CNTL_STACK_SIZE =$3274; + mmCP_HQD_WG_STATE_OFFSET =$3275; + mmCP_HQD_CTX_SAVE_SIZE =$3276; + mmCP_HQD_GDS_RESOURCE_STATE =$3277; + mmCP_HQD_ERROR =$3278; + mmCP_HQD_EOP_WPTR_MEM =$3279; + mmCP_HQD_EOP_DONES =$327A; + mmDIDT_IND_INDEX =$3280; + mmDIDT_IND_DATA =$3281; + mmGC_CAC_CGTT_CLK_CTRL =$3292; + mmSE_CAC_CGTT_CLK_CTRL =$3293; + mmGC_CAC_LKG_AGGR_LOWER =$3296; + mmGC_CAC_LKG_AGGR_UPPER =$3297; + mmTCP_WATCH0_ADDR_H =$32A0; + mmTCP_WATCH0_ADDR_L =$32A1; + mmTCP_WATCH0_CNTL =$32A2; + mmTCP_WATCH1_ADDR_H =$32A3; + mmTCP_WATCH1_ADDR_L =$32A4; + mmTCP_WATCH1_CNTL =$32A5; + mmTCP_WATCH2_ADDR_H =$32A6; + mmTCP_WATCH2_ADDR_L =$32A7; + mmTCP_WATCH2_CNTL =$32A8; + mmTCP_WATCH3_ADDR_H =$32A9; + mmTCP_WATCH3_ADDR_L =$32AA; + mmTCP_WATCH3_CNTL =$32AB; + mmTCP_GATCL1_CNTL =$32B0; + mmTCP_ATC_EDC_GATCL1_CNT =$32B1; + mmTCP_GATCL1_DSM_CNTL =$32B2; + mmTCP_DSM_CNTL =$32B3; + mmTCP_CNTL2 =$32B4; + mmGDS_VMID0_BASE =$3300; + mmGDS_VMID0_SIZE =$3301; + mmGDS_VMID1_BASE =$3302; + mmGDS_VMID1_SIZE =$3303; + mmGDS_VMID2_BASE =$3304; + mmGDS_VMID2_SIZE =$3305; + mmGDS_VMID3_BASE =$3306; + mmGDS_VMID3_SIZE =$3307; + mmGDS_VMID4_BASE =$3308; + mmGDS_VMID4_SIZE =$3309; + mmGDS_VMID5_BASE =$330A; + mmGDS_VMID5_SIZE =$330B; + mmGDS_VMID6_BASE =$330C; + mmGDS_VMID6_SIZE =$330D; + mmGDS_VMID7_BASE =$330E; + mmGDS_VMID7_SIZE =$330F; + mmGDS_VMID8_BASE =$3310; + mmGDS_VMID8_SIZE =$3311; + mmGDS_VMID9_BASE =$3312; + mmGDS_VMID9_SIZE =$3313; + mmGDS_VMID10_BASE =$3314; + mmGDS_VMID10_SIZE =$3315; + mmGDS_VMID11_BASE =$3316; + mmGDS_VMID11_SIZE =$3317; + mmGDS_VMID12_BASE =$3318; + mmGDS_VMID12_SIZE =$3319; + mmGDS_VMID13_BASE =$331A; + mmGDS_VMID13_SIZE =$331B; + mmGDS_VMID14_BASE =$331C; + mmGDS_VMID14_SIZE =$331D; + mmGDS_VMID15_BASE =$331E; + mmGDS_VMID15_SIZE =$331F; + mmGDS_GWS_VMID0 =$3320; + mmGDS_GWS_VMID1 =$3321; + mmGDS_GWS_VMID2 =$3322; + mmGDS_GWS_VMID3 =$3323; + mmGDS_GWS_VMID4 =$3324; + mmGDS_GWS_VMID5 =$3325; + mmGDS_GWS_VMID6 =$3326; + mmGDS_GWS_VMID7 =$3327; + mmGDS_GWS_VMID8 =$3328; + mmGDS_GWS_VMID9 =$3329; + mmGDS_GWS_VMID10 =$332A; + mmGDS_GWS_VMID11 =$332B; + mmGDS_GWS_VMID12 =$332C; + mmGDS_GWS_VMID13 =$332D; + mmGDS_GWS_VMID14 =$332E; + mmGDS_GWS_VMID15 =$332F; + mmGDS_OA_VMID0 =$3330; + mmGDS_OA_VMID1 =$3331; + mmGDS_OA_VMID2 =$3332; + mmGDS_OA_VMID3 =$3333; + mmGDS_OA_VMID4 =$3334; + mmGDS_OA_VMID5 =$3335; + mmGDS_OA_VMID6 =$3336; + mmGDS_OA_VMID7 =$3337; + mmGDS_OA_VMID8 =$3338; + mmGDS_OA_VMID9 =$3339; + mmGDS_OA_VMID10 =$333A; + mmGDS_OA_VMID11 =$333B; + mmGDS_OA_VMID12 =$333C; + mmGDS_OA_VMID13 =$333D; + mmGDS_OA_VMID14 =$333E; + mmGDS_OA_VMID15 =$333F; + mmGDS_GWS_RESET0 =$3344; + mmGDS_GWS_RESET1 =$3345; + mmGDS_GWS_RESOURCE_RESET =$3346; + mmGDS_COMPUTE_MAX_WAVE_ID =$3348; + mmGDS_OA_RESET_MASK =$3349; + mmGDS_OA_RESET =$334A; + mmGDS_ENHANCE =$334B; + mmGDS_OA_CGPG_RESTORE =$334C; + mmGDS_CS_CTXSW_STATUS =$334D; + mmGDS_CS_CTXSW_CNT0 =$334E; + mmGDS_CS_CTXSW_CNT1 =$334F; + mmGDS_CS_CTXSW_CNT2 =$3350; + mmGDS_CS_CTXSW_CNT3 =$3351; + mmGDS_GFX_CTXSW_STATUS =$3352; + mmGDS_VS_CTXSW_CNT0 =$3353; + mmGDS_VS_CTXSW_CNT1 =$3354; + mmGDS_VS_CTXSW_CNT2 =$3355; + mmGDS_VS_CTXSW_CNT3 =$3356; + mmGDS_PS0_CTXSW_CNT0 =$3357; + mmGDS_PS0_CTXSW_CNT1 =$3358; + mmGDS_PS0_CTXSW_CNT2 =$3359; + mmGDS_PS0_CTXSW_CNT3 =$335A; + mmGDS_PS1_CTXSW_CNT0 =$335B; + mmGDS_PS1_CTXSW_CNT1 =$335C; + mmGDS_PS1_CTXSW_CNT2 =$335D; + mmGDS_PS1_CTXSW_CNT3 =$335E; + mmGDS_PS2_CTXSW_CNT0 =$335F; + mmGDS_PS2_CTXSW_CNT1 =$3360; + mmGDS_PS2_CTXSW_CNT2 =$3361; + mmGDS_PS2_CTXSW_CNT3 =$3362; + mmGDS_PS3_CTXSW_CNT0 =$3363; + mmGDS_PS3_CTXSW_CNT1 =$3364; + mmGDS_PS3_CTXSW_CNT2 =$3365; + mmGDS_PS3_CTXSW_CNT3 =$3366; + mmGDS_PS4_CTXSW_CNT0 =$3367; + mmGDS_PS4_CTXSW_CNT1 =$3368; + mmGDS_PS4_CTXSW_CNT2 =$3369; + mmGDS_PS4_CTXSW_CNT3 =$336A; + mmGDS_PS5_CTXSW_CNT0 =$336B; + mmGDS_PS5_CTXSW_CNT1 =$336C; + mmGDS_PS5_CTXSW_CNT2 =$336D; + mmGDS_PS5_CTXSW_CNT3 =$336E; + mmGDS_PS6_CTXSW_CNT0 =$336F; + mmGDS_PS6_CTXSW_CNT1 =$3370; + mmGDS_PS6_CTXSW_CNT2 =$3371; + mmGDS_PS6_CTXSW_CNT3 =$3372; + mmGDS_PS7_CTXSW_CNT0 =$3373; + mmGDS_PS7_CTXSW_CNT1 =$3374; + mmGDS_PS7_CTXSW_CNT2 =$3375; + mmGDS_PS7_CTXSW_CNT3 =$3376; + mmRAS_SIGNATURE_CONTROL =$3380; + mmRAS_SIGNATURE_MASK =$3381; + mmRAS_SX_SIGNATURE0 =$3382; + mmRAS_SX_SIGNATURE1 =$3383; + mmRAS_SX_SIGNATURE2 =$3384; + mmRAS_SX_SIGNATURE3 =$3385; + mmRAS_DB_SIGNATURE0 =$338B; + mmRAS_PA_SIGNATURE0 =$338C; + mmRAS_VGT_SIGNATURE0 =$338D; + mmRAS_SQ_SIGNATURE0 =$338E; + mmRAS_SC_SIGNATURE0 =$338F; + mmRAS_SC_SIGNATURE1 =$3390; + mmRAS_SC_SIGNATURE2 =$3391; + mmRAS_SC_SIGNATURE3 =$3392; + mmRAS_SC_SIGNATURE4 =$3393; + mmRAS_SC_SIGNATURE5 =$3394; + mmRAS_SC_SIGNATURE6 =$3395; + mmRAS_SC_SIGNATURE7 =$3396; + mmRAS_IA_SIGNATURE0 =$3397; + mmRAS_IA_SIGNATURE1 =$3398; + mmRAS_SPI_SIGNATURE0 =$3399; + mmRAS_SPI_SIGNATURE1 =$339A; + mmRAS_TA_SIGNATURE0 =$339B; + mmRAS_TD_SIGNATURE0 =$339C; + mmRAS_CB_SIGNATURE0 =$339D; + mmRAS_BCI_SIGNATURE0 =$339E; + mmRAS_BCI_SIGNATURE1 =$339F; + mmRAS_TA_SIGNATURE1 =$33A0; + mmSDMA0_UCODE_ADDR =$3400; + mmSDMA0_UCODE_DATA =$3401; + mmSDMA0_POWER_CNTL =$3402; + mmSDMA0_CLK_CTRL =$3403; + mmSDMA0_CNTL =$3404; + mmSDMA0_CHICKEN_BITS =$3405; + mmSDMA0_TILING_CONFIG =$3406; + mmSDMA0_HASH =$3407; + mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL =$3409; + mmSDMA0_RB_RPTR_FETCH =$340A; + mmSDMA0_IB_OFFSET_FETCH =$340B; + mmSDMA0_PROGRAM =$340C; + mmSDMA0_STATUS_REG =$340D; + mmSDMA0_STATUS1_REG =$340E; + mmSDMA0_RD_BURST_CNTL =$340F; + mmSDMA0_F32_CNTL =$3412; + mmSDMA0_FREEZE =$3413; + mmSDMA0_PHASE0_QUANTUM =$3414; + mmSDMA0_PHASE1_QUANTUM =$3415; + mmSDMA_POWER_GATING =$3416; + mmSDMA_PGFSM_CONFIG =$3417; + mmSDMA_PGFSM_WRITE =$3418; + mmSDMA_PGFSM_READ =$3419; + mmSDMA0_EDC_CONFIG =$341A; + mmSDMA0_VM_CNTL =$341B; + mmSDMA0_VM_CTX_LO =$341C; + mmSDMA0_VM_CTX_HI =$341D; + mmSDMA0_STATUS2_REG =$341E; + mmSDMA0_ACTIVE_FCN_ID =$341F; + mmSDMA0_VM_CTX_CNTL =$3420; + mmSDMA0_VIRT_RESET_REQ =$3421; + mmSDMA0_VF_ENABLE =$342A; + mmSDMA0_BA_THRESHOLD =$342B; + mmSDMA0_ID =$342C; + mmSDMA0_VERSION =$342D; + mmSDMA0_ATOMIC_CNTL =$342E; + mmSDMA0_ATOMIC_PREOP_LO =$342F; + mmSDMA0_ATOMIC_PREOP_HI =$3430; + mmSDMA0_PERF_REG_TYPE0 =$3477; + mmSDMA0_CONTEXT_REG_TYPE0 =$3478; + mmSDMA0_CONTEXT_REG_TYPE1 =$3479; + mmSDMA0_CONTEXT_REG_TYPE2 =$347A; + mmSDMA0_PUB_REG_TYPE0 =$347C; + mmSDMA0_PUB_REG_TYPE1 =$347D; + mmSDMA0_GFX_RB_CNTL =$3480; + mmSDMA0_GFX_RB_BASE =$3481; + mmSDMA0_GFX_RB_BASE_HI =$3482; + mmSDMA0_GFX_RB_RPTR =$3483; + mmSDMA0_GFX_RB_WPTR =$3484; + mmSDMA0_GFX_RB_WPTR_POLL_CNTL =$3485; + mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI =$3486; + mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO =$3487; + mmSDMA0_GFX_RB_RPTR_ADDR_HI =$3488; + mmSDMA0_GFX_RB_RPTR_ADDR_LO =$3489; + mmSDMA0_GFX_IB_CNTL =$348A; + mmSDMA0_GFX_IB_RPTR =$348B; + mmSDMA0_GFX_IB_OFFSET =$348C; + mmSDMA0_GFX_IB_BASE_LO =$348D; + mmSDMA0_GFX_IB_BASE_HI =$348E; + mmSDMA0_GFX_IB_SIZE =$348F; + mmSDMA0_GFX_SKIP_CNTL =$3490; + mmSDMA0_GFX_CONTEXT_STATUS =$3491; + mmSDMA0_GFX_DOORBELL =$3492; + mmSDMA0_GFX_CONTEXT_CNTL =$3493; + mmSDMA0_GFX_VIRTUAL_ADDR =$34A7; + mmSDMA0_GFX_APE1_CNTL =$34A8; + mmSDMA0_GFX_DOORBELL_LOG =$34A9; + mmSDMA0_GFX_WATERMARK =$34AA; + mmSDMA0_GFX_CSA_ADDR_LO =$34AC; + mmSDMA0_GFX_CSA_ADDR_HI =$34AD; + mmSDMA0_GFX_IB_SUB_REMAIN =$34AF; + mmSDMA0_GFX_PREEMPT =$34B0; + mmSDMA0_GFX_DUMMY_REG =$34B1; + mmSDMA0_GFX_MIDCMD_DATA0 =$34C1; + mmSDMA0_GFX_MIDCMD_DATA1 =$34C2; + mmSDMA0_GFX_MIDCMD_DATA2 =$34C3; + mmSDMA0_GFX_MIDCMD_DATA3 =$34C4; + mmSDMA0_GFX_MIDCMD_DATA4 =$34C5; + mmSDMA0_GFX_MIDCMD_DATA5 =$34C6; + mmSDMA0_GFX_MIDCMD_CNTL =$34C7; + mmSDMA0_RLC0_RB_CNTL =$3500; + mmSDMA0_RLC0_RB_BASE =$3501; + mmSDMA0_RLC0_RB_BASE_HI =$3502; + mmSDMA0_RLC0_RB_RPTR =$3503; + mmSDMA0_RLC0_RB_WPTR =$3504; + mmSDMA0_RLC0_RB_WPTR_POLL_CNTL =$3505; + mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI =$3506; + mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO =$3507; + mmSDMA0_RLC0_RB_RPTR_ADDR_HI =$3508; + mmSDMA0_RLC0_RB_RPTR_ADDR_LO =$3509; + mmSDMA0_RLC0_IB_CNTL =$350A; + mmSDMA0_RLC0_IB_RPTR =$350B; + mmSDMA0_RLC0_IB_OFFSET =$350C; + mmSDMA0_RLC0_IB_BASE_LO =$350D; + mmSDMA0_RLC0_IB_BASE_HI =$350E; + mmSDMA0_RLC0_IB_SIZE =$350F; + mmSDMA0_RLC0_SKIP_CNTL =$3510; + mmSDMA0_RLC0_CONTEXT_STATUS =$3511; + mmSDMA0_RLC0_DOORBELL =$3512; + mmSDMA0_RLC0_VIRTUAL_ADDR =$3527; + mmSDMA0_RLC0_APE1_CNTL =$3528; + mmSDMA0_RLC0_DOORBELL_LOG =$3529; + mmSDMA0_RLC0_WATERMARK =$352A; + mmSDMA0_RLC0_CSA_ADDR_LO =$352C; + mmSDMA0_RLC0_CSA_ADDR_HI =$352D; + mmSDMA0_RLC0_IB_SUB_REMAIN =$352F; + mmSDMA0_RLC0_PREEMPT =$3530; + mmSDMA0_RLC0_DUMMY_REG =$3531; + mmSDMA0_RLC0_MIDCMD_DATA0 =$3541; + mmSDMA0_RLC0_MIDCMD_DATA1 =$3542; + mmSDMA0_RLC0_MIDCMD_DATA2 =$3543; + mmSDMA0_RLC0_MIDCMD_DATA3 =$3544; + mmSDMA0_RLC0_MIDCMD_DATA4 =$3545; + mmSDMA0_RLC0_MIDCMD_DATA5 =$3546; + mmSDMA0_RLC0_MIDCMD_CNTL =$3547; + mmSDMA0_RLC1_RB_CNTL =$3580; + mmSDMA0_RLC1_RB_BASE =$3581; + mmSDMA0_RLC1_RB_BASE_HI =$3582; + mmSDMA0_RLC1_RB_RPTR =$3583; + mmSDMA0_RLC1_RB_WPTR =$3584; + mmSDMA0_RLC1_RB_WPTR_POLL_CNTL =$3585; + mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI =$3586; + mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO =$3587; + mmSDMA0_RLC1_RB_RPTR_ADDR_HI =$3588; + mmSDMA0_RLC1_RB_RPTR_ADDR_LO =$3589; + mmSDMA0_RLC1_IB_CNTL =$358A; + mmSDMA0_RLC1_IB_RPTR =$358B; + mmSDMA0_RLC1_IB_OFFSET =$358C; + mmSDMA0_RLC1_IB_BASE_LO =$358D; + mmSDMA0_RLC1_IB_BASE_HI =$358E; + mmSDMA0_RLC1_IB_SIZE =$358F; + mmSDMA0_RLC1_SKIP_CNTL =$3590; + mmSDMA0_RLC1_CONTEXT_STATUS =$3591; + mmSDMA0_RLC1_DOORBELL =$3592; + mmSDMA0_RLC1_VIRTUAL_ADDR =$35A7; + mmSDMA0_RLC1_APE1_CNTL =$35A8; + mmSDMA0_RLC1_DOORBELL_LOG =$35A9; + mmSDMA0_RLC1_WATERMARK =$35AA; + mmSDMA0_RLC1_CSA_ADDR_LO =$35AC; + mmSDMA0_RLC1_CSA_ADDR_HI =$35AD; + mmSDMA0_RLC1_IB_SUB_REMAIN =$35AF; + mmSDMA0_RLC1_PREEMPT =$35B0; + mmSDMA0_RLC1_DUMMY_REG =$35B1; + mmSDMA0_RLC1_MIDCMD_DATA0 =$35C1; + mmSDMA0_RLC1_MIDCMD_DATA1 =$35C2; + mmSDMA0_RLC1_MIDCMD_DATA2 =$35C3; + mmSDMA0_RLC1_MIDCMD_DATA3 =$35C4; + mmSDMA0_RLC1_MIDCMD_DATA4 =$35C5; + mmSDMA0_RLC1_MIDCMD_DATA5 =$35C6; + mmSDMA0_RLC1_MIDCMD_CNTL =$35C7; + mmSDMA1_UCODE_ADDR =$3600; + mmSDMA1_UCODE_DATA =$3601; + mmSDMA1_POWER_CNTL =$3602; + mmSDMA1_CLK_CTRL =$3603; + mmSDMA1_CNTL =$3604; + mmSDMA1_CHICKEN_BITS =$3605; + mmSDMA1_TILING_CONFIG =$3606; + mmSDMA1_HASH =$3607; + mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL =$3609; + mmSDMA1_RB_RPTR_FETCH =$360A; + mmSDMA1_IB_OFFSET_FETCH =$360B; + mmSDMA1_PROGRAM =$360C; + mmSDMA1_STATUS_REG =$360D; + mmSDMA1_STATUS1_REG =$360E; + mmSDMA1_RD_BURST_CNTL =$360F; + mmSDMA1_F32_CNTL =$3612; + mmSDMA1_FREEZE =$3613; + mmSDMA1_PHASE0_QUANTUM =$3614; + mmSDMA1_PHASE1_QUANTUM =$3615; + mmSDMA1_EDC_CONFIG =$361A; + mmSDMA1_VM_CNTL =$361B; + mmSDMA1_VM_CTX_LO =$361C; + mmSDMA1_VM_CTX_HI =$361D; + mmSDMA1_STATUS2_REG =$361E; + mmSDMA1_ACTIVE_FCN_ID =$361F; + mmSDMA1_VM_CTX_CNTL =$3620; + mmSDMA1_VIRT_RESET_REQ =$3621; + mmSDMA1_VF_ENABLE =$362A; + mmSDMA1_BA_THRESHOLD =$362B; + mmSDMA1_ID =$362C; + mmSDMA1_VERSION =$362D; + mmSDMA1_ATOMIC_CNTL =$362E; + mmSDMA1_ATOMIC_PREOP_LO =$362F; + mmSDMA1_ATOMIC_PREOP_HI =$3630; + mmSDMA1_PERF_REG_TYPE0 =$3677; + mmSDMA1_CONTEXT_REG_TYPE0 =$3678; + mmSDMA1_CONTEXT_REG_TYPE1 =$3679; + mmSDMA1_CONTEXT_REG_TYPE2 =$367A; + mmSDMA1_PUB_REG_TYPE0 =$367C; + mmSDMA1_PUB_REG_TYPE1 =$367D; + mmSDMA1_GFX_RB_CNTL =$3680; + mmSDMA1_GFX_RB_BASE =$3681; + mmSDMA1_GFX_RB_BASE_HI =$3682; + mmSDMA1_GFX_RB_RPTR =$3683; + mmSDMA1_GFX_RB_WPTR =$3684; + mmSDMA1_GFX_RB_WPTR_POLL_CNTL =$3685; + mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI =$3686; + mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO =$3687; + mmSDMA1_GFX_RB_RPTR_ADDR_HI =$3688; + mmSDMA1_GFX_RB_RPTR_ADDR_LO =$3689; + mmSDMA1_GFX_IB_CNTL =$368A; + mmSDMA1_GFX_IB_RPTR =$368B; + mmSDMA1_GFX_IB_OFFSET =$368C; + mmSDMA1_GFX_IB_BASE_LO =$368D; + mmSDMA1_GFX_IB_BASE_HI =$368E; + mmSDMA1_GFX_IB_SIZE =$368F; + mmSDMA1_GFX_SKIP_CNTL =$3690; + mmSDMA1_GFX_CONTEXT_STATUS =$3691; + mmSDMA1_GFX_DOORBELL =$3692; + mmSDMA1_GFX_CONTEXT_CNTL =$3693; + mmSDMA1_GFX_VIRTUAL_ADDR =$36A7; + mmSDMA1_GFX_APE1_CNTL =$36A8; + mmSDMA1_GFX_DOORBELL_LOG =$36A9; + mmSDMA1_GFX_WATERMARK =$36AA; + mmSDMA1_GFX_CSA_ADDR_LO =$36AC; + mmSDMA1_GFX_CSA_ADDR_HI =$36AD; + mmSDMA1_GFX_IB_SUB_REMAIN =$36AF; + mmSDMA1_GFX_PREEMPT =$36B0; + mmSDMA1_GFX_DUMMY_REG =$36B1; + mmSDMA1_GFX_MIDCMD_DATA0 =$36C1; + mmSDMA1_GFX_MIDCMD_DATA1 =$36C2; + mmSDMA1_GFX_MIDCMD_DATA2 =$36C3; + mmSDMA1_GFX_MIDCMD_DATA3 =$36C4; + mmSDMA1_GFX_MIDCMD_DATA4 =$36C5; + mmSDMA1_GFX_MIDCMD_DATA5 =$36C6; + mmSDMA1_GFX_MIDCMD_CNTL =$36C7; + mmSDMA1_RLC0_RB_CNTL =$3700; + mmSDMA1_RLC0_RB_BASE =$3701; + mmSDMA1_RLC0_RB_BASE_HI =$3702; + mmSDMA1_RLC0_RB_RPTR =$3703; + mmSDMA1_RLC0_RB_WPTR =$3704; + mmSDMA1_RLC0_RB_WPTR_POLL_CNTL =$3705; + mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI =$3706; + mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO =$3707; + mmSDMA1_RLC0_RB_RPTR_ADDR_HI =$3708; + mmSDMA1_RLC0_RB_RPTR_ADDR_LO =$3709; + mmSDMA1_RLC0_IB_CNTL =$370A; + mmSDMA1_RLC0_IB_RPTR =$370B; + mmSDMA1_RLC0_IB_OFFSET =$370C; + mmSDMA1_RLC0_IB_BASE_LO =$370D; + mmSDMA1_RLC0_IB_BASE_HI =$370E; + mmSDMA1_RLC0_IB_SIZE =$370F; + mmSDMA1_RLC0_SKIP_CNTL =$3710; + mmSDMA1_RLC0_CONTEXT_STATUS =$3711; + mmSDMA1_RLC0_DOORBELL =$3712; + mmSDMA1_RLC0_VIRTUAL_ADDR =$3727; + mmSDMA1_RLC0_APE1_CNTL =$3728; + mmSDMA1_RLC0_DOORBELL_LOG =$3729; + mmSDMA1_RLC0_WATERMARK =$372A; + mmSDMA1_RLC0_CSA_ADDR_LO =$372C; + mmSDMA1_RLC0_CSA_ADDR_HI =$372D; + mmSDMA1_RLC0_IB_SUB_REMAIN =$372F; + mmSDMA1_RLC0_PREEMPT =$3730; + mmSDMA1_RLC0_DUMMY_REG =$3731; + mmSDMA1_RLC0_MIDCMD_DATA0 =$3741; + mmSDMA1_RLC0_MIDCMD_DATA1 =$3742; + mmSDMA1_RLC0_MIDCMD_DATA2 =$3743; + mmSDMA1_RLC0_MIDCMD_DATA3 =$3744; + mmSDMA1_RLC0_MIDCMD_DATA4 =$3745; + mmSDMA1_RLC0_MIDCMD_DATA5 =$3746; + mmSDMA1_RLC0_MIDCMD_CNTL =$3747; + mmSDMA1_RLC1_RB_CNTL =$3780; + mmSDMA1_RLC1_RB_BASE =$3781; + mmSDMA1_RLC1_RB_BASE_HI =$3782; + mmSDMA1_RLC1_RB_RPTR =$3783; + mmSDMA1_RLC1_RB_WPTR =$3784; + mmSDMA1_RLC1_RB_WPTR_POLL_CNTL =$3785; + mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI =$3786; + mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO =$3787; + mmSDMA1_RLC1_RB_RPTR_ADDR_HI =$3788; + mmSDMA1_RLC1_RB_RPTR_ADDR_LO =$3789; + mmSDMA1_RLC1_IB_CNTL =$378A; + mmSDMA1_RLC1_IB_RPTR =$378B; + mmSDMA1_RLC1_IB_OFFSET =$378C; + mmSDMA1_RLC1_IB_BASE_LO =$378D; + mmSDMA1_RLC1_IB_BASE_HI =$378E; + mmSDMA1_RLC1_IB_SIZE =$378F; + mmSDMA1_RLC1_SKIP_CNTL =$3790; + mmSDMA1_RLC1_CONTEXT_STATUS =$3791; + mmSDMA1_RLC1_DOORBELL =$3792; + mmSDMA1_RLC1_VIRTUAL_ADDR =$37A7; + mmSDMA1_RLC1_APE1_CNTL =$37A8; + mmSDMA1_RLC1_DOORBELL_LOG =$37A9; + mmSDMA1_RLC1_WATERMARK =$37AA; + mmSDMA1_RLC1_CSA_ADDR_LO =$37AC; + mmSDMA1_RLC1_CSA_ADDR_HI =$37AD; + mmSDMA1_RLC1_IB_SUB_REMAIN =$37AF; + mmSDMA1_RLC1_PREEMPT =$37B0; + mmSDMA1_RLC1_DUMMY_REG =$37B1; + mmSDMA1_RLC1_MIDCMD_DATA0 =$37C1; + mmSDMA1_RLC1_MIDCMD_DATA1 =$37C2; + mmSDMA1_RLC1_MIDCMD_DATA2 =$37C3; + mmSDMA1_RLC1_MIDCMD_DATA3 =$37C4; + mmSDMA1_RLC1_MIDCMD_DATA4 =$37C5; + mmSDMA1_RLC1_MIDCMD_DATA5 =$37C6; + mmSDMA1_RLC1_MIDCMD_CNTL =$37C7; + mmUVD_PGFSM_CONFIG =$38C0; + mmUVD_PGFSM_READ_TILE1 =$38C2; + mmUVD_PGFSM_READ_TILE2 =$38C3; + mmUVD_POWER_STATUS =$38C4; + mmUVD_PGFSM_READ_TILE3 =$38C5; + mmUVD_PGFSM_READ_TILE4 =$38C6; + mmUVD_PGFSM_READ_TILE5 =$38C8; + mmUVD_PGFSM_READ_TILE6 =$38EE; + mmUVD_PGFSM_READ_TILE7 =$38EF; + mmUVD_MIF_CURR_ADDR_CONFIG =$3992; + mmUVD_MIF_REF_ADDR_CONFIG =$3993; + mmUVD_MIF_RECON1_ADDR_CONFIG =$39C5; + mmUVD_JPEG_ADDR_CONFIG =$3A1F; + mmUVD_SEMA_ADDR_LOW =$3BC0; + mmUVD_SEMA_ADDR_HIGH =$3BC1; + mmUVD_SEMA_CMD =$3BC2; + mmUVD_GPCOM_VCPU_CMD =$3BC3; + mmUVD_GPCOM_VCPU_DATA0 =$3BC4; + mmUVD_GPCOM_VCPU_DATA1 =$3BC5; + mmUVD_ENGINE_CNTL =$3BC6; + mmUVD_UDEC_ADDR_CONFIG =$3BD3; + mmUVD_UDEC_DB_ADDR_CONFIG =$3BD4; + mmUVD_UDEC_DBW_ADDR_CONFIG =$3BD5; + mmUVD_SUVD_CGC_GATE =$3BE4; + mmUVD_SUVD_CGC_STATUS =$3BE5; + mmUVD_SUVD_CGC_CTRL =$3BE6; + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH =$3C5E; + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW =$3C5F; + mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH =$3C66; + mmUVD_LMI_RBC_IB_64BIT_BAR_LOW =$3C67; + mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH =$3C68; + mmUVD_LMI_RBC_RB_64BIT_BAR_LOW =$3C69; + mmUVD_SEMA_CNTL =$3D00; + mmUVD_LMI_EXT40_ADDR =$3D26; + mmUVD_CTX_INDEX =$3D28; + mmUVD_CTX_DATA =$3D29; + mmUVD_CGC_GATE =$3D2A; + mmUVD_CGC_STATUS =$3D2B; + mmUVD_CGC_CTRL =$3D2C; + mmUVD_CGC_UDEC_STATUS =$3D2D; + mmUVD_LMI_CTRL2 =$3D3D; + mmUVD_MASTINT_EN =$3D40; + mmUVD_LMI_ADDR_EXT =$3D65; + mmUVD_LMI_CTRL =$3D66; + mmUVD_LMI_STATUS =$3D67; + mmUVD_LMI_SWAP_CNTL =$3D6D; + mmUVD_MP_SWAP_CNTL =$3D6F; + mmUVD_MPC_CNTL =$3D77; + mmUVD_MPC_SET_MUXA0 =$3D79; + mmUVD_MPC_SET_MUXA1 =$3D7A; + mmUVD_MPC_SET_MUXB0 =$3D7B; + mmUVD_MPC_SET_MUXB1 =$3D7C; + mmUVD_MPC_SET_MUX =$3D7D; + mmUVD_MPC_SET_ALU =$3D7E; + mmUVD_VCPU_CACHE_OFFSET0 =$3D82; + mmUVD_VCPU_CACHE_SIZE0 =$3D83; + mmUVD_VCPU_CACHE_OFFSET1 =$3D84; + mmUVD_VCPU_CACHE_SIZE1 =$3D85; + mmUVD_VCPU_CACHE_OFFSET2 =$3D86; + mmUVD_VCPU_CACHE_SIZE2 =$3D87; + mmUVD_VCPU_CNTL =$3D98; + mmUVD_SOFT_RESET =$3DA0; + mmUVD_LMI_RBC_IB_VMID =$3DA1; + mmUVD_RBC_IB_SIZE =$3DA2; + mmUVD_LMI_RBC_RB_VMID =$3DA3; + mmUVD_RBC_RB_RPTR =$3DA4; + mmUVD_RBC_RB_WPTR =$3DA5; + mmUVD_RBC_RB_CNTL =$3DA9; + mmUVD_RBC_RB_RPTR_ADDR =$3DAA; + mmUVD_STATUS =$3DAF; + mmUVD_SEMA_TIMEOUT_STATUS =$3DB0; + mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL =$3DB1; + mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL =$3DB2; + mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL =$3DB3; + mmUVD_CONTEXT_ID =$3DBD; + mmDCP3_GRPH_ENABLE =$4000; + mmDCP3_GRPH_CONTROL =$4001; + mmDCP3_GRPH_LUT_10BIT_BYPASS =$4002; + mmDCP3_GRPH_SWAP_CNTL =$4003; + mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS =$4004; + mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS =$4005; + mmDCP3_GRPH_PITCH =$4006; + mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH =$4007; + mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH =$4008; + mmDCP3_GRPH_SURFACE_OFFSET_X =$4009; + mmDCP3_GRPH_SURFACE_OFFSET_Y =$400A; + mmDCP3_GRPH_X_START =$400B; + mmDCP3_GRPH_Y_START =$400C; + mmDCP3_GRPH_X_END =$400D; + mmDCP3_GRPH_Y_END =$400E; + mmDCP3_INPUT_GAMMA_CONTROL =$4010; + mmDCP3_GRPH_UPDATE =$4011; + mmDCP3_GRPH_FLIP_CONTROL =$4012; + mmDCP3_GRPH_SURFACE_ADDRESS_INUSE =$4013; + mmDCP3_GRPH_DFQ_CONTROL =$4014; + mmDCP3_GRPH_DFQ_STATUS =$4015; + mmDCP3_GRPH_INTERRUPT_STATUS =$4016; + mmDCP3_GRPH_INTERRUPT_CONTROL =$4017; + mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE =$4018; + mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS =$4019; + mmDCP3_GRPH_COMPRESS_PITCH =$401A; + mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH =$401B; + mmDCP3_OVL_ENABLE =$401C; + mmDCP3_OVL_CONTROL1 =$401D; + mmDCP3_OVL_CONTROL2 =$401E; + mmDCP3_OVL_SWAP_CNTL =$401F; + mmDCP3_OVL_SURFACE_ADDRESS =$4020; + mmDCP3_OVL_PITCH =$4021; + mmDCP3_OVL_SURFACE_ADDRESS_HIGH =$4022; + mmDCP3_OVL_SURFACE_OFFSET_X =$4023; + mmDCP3_OVL_SURFACE_OFFSET_Y =$4024; + mmDCP3_OVL_START =$4025; + mmDCP3_OVL_END =$4026; + mmDCP3_OVL_UPDATE =$4027; + mmDCP3_OVL_SURFACE_ADDRESS_INUSE =$4028; + mmDCP3_OVL_DFQ_CONTROL =$4029; + mmDCP3_OVL_DFQ_STATUS =$402A; + mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE =$402B; + mmDCP3_OVLSCL_EDGE_PIXEL_CNTL =$402C; + mmDCP3_PRESCALE_GRPH_CONTROL =$402D; + mmDCP3_PRESCALE_VALUES_GRPH_R =$402E; + mmDCP3_PRESCALE_VALUES_GRPH_G =$402F; + mmDCP3_PRESCALE_VALUES_GRPH_B =$4030; + mmDCP3_PRESCALE_OVL_CONTROL =$4031; + mmDCP3_PRESCALE_VALUES_OVL_CB =$4032; + mmDCP3_PRESCALE_VALUES_OVL_Y =$4033; + mmDCP3_PRESCALE_VALUES_OVL_CR =$4034; + mmDCP3_INPUT_CSC_CONTROL =$4035; + mmDCP3_INPUT_CSC_C11_C12 =$4036; + mmDCP3_INPUT_CSC_C13_C14 =$4037; + mmDCP3_INPUT_CSC_C21_C22 =$4038; + mmDCP3_INPUT_CSC_C23_C24 =$4039; + mmDCP3_INPUT_CSC_C31_C32 =$403A; + mmDCP3_INPUT_CSC_C33_C34 =$403B; + mmDCP3_OUTPUT_CSC_CONTROL =$403C; + mmDCP3_OUTPUT_CSC_C11_C12 =$403D; + mmDCP3_OUTPUT_CSC_C13_C14 =$403E; + mmDCP3_OUTPUT_CSC_C21_C22 =$403F; + mmDCP3_OUTPUT_CSC_C23_C24 =$4040; + mmDCP3_OUTPUT_CSC_C31_C32 =$4041; + mmDCP3_OUTPUT_CSC_C33_C34 =$4042; + mmDCP3_COMM_MATRIXA_TRANS_C11_C12 =$4043; + mmDCP3_COMM_MATRIXA_TRANS_C13_C14 =$4044; + mmDCP3_COMM_MATRIXA_TRANS_C21_C22 =$4045; + mmDCP3_COMM_MATRIXA_TRANS_C23_C24 =$4046; + mmDCP3_COMM_MATRIXA_TRANS_C31_C32 =$4047; + mmDCP3_COMM_MATRIXA_TRANS_C33_C34 =$4048; + mmDCP3_COMM_MATRIXB_TRANS_C11_C12 =$4049; + mmDCP3_COMM_MATRIXB_TRANS_C13_C14 =$404A; + mmDCP3_COMM_MATRIXB_TRANS_C21_C22 =$404B; + mmDCP3_COMM_MATRIXB_TRANS_C23_C24 =$404C; + mmDCP3_COMM_MATRIXB_TRANS_C31_C32 =$404D; + mmDCP3_COMM_MATRIXB_TRANS_C33_C34 =$404E; + mmDCP3_DENORM_CONTROL =$4050; + mmDCP3_OUT_ROUND_CONTROL =$4051; + mmDCP3_OUT_CLAMP_CONTROL_R_CR =$4052; + mmDCP3_KEY_CONTROL =$4053; + mmDCP3_KEY_RANGE_ALPHA =$4054; + mmDCP3_KEY_RANGE_RED =$4055; + mmDCP3_KEY_RANGE_GREEN =$4056; + mmDCP3_KEY_RANGE_BLUE =$4057; + mmDCP3_DEGAMMA_CONTROL =$4058; + mmDCP3_GAMUT_REMAP_CONTROL =$4059; + mmDCP3_GAMUT_REMAP_C11_C12 =$405A; + mmDCP3_GAMUT_REMAP_C13_C14 =$405B; + mmDCP3_GAMUT_REMAP_C21_C22 =$405C; + mmDCP3_GAMUT_REMAP_C23_C24 =$405D; + mmDCP3_GAMUT_REMAP_C31_C32 =$405E; + mmDCP3_GAMUT_REMAP_C33_C34 =$405F; + mmDCP3_DCP_SPATIAL_DITHER_CNTL =$4060; + mmDCP3_DCP_RANDOM_SEEDS =$4061; + mmDCP3_DCP_FP_CONVERTED_FIELD =$4065; + mmDCP3_CUR_CONTROL =$4066; + mmDCP3_CUR_SURFACE_ADDRESS =$4067; + mmDCP3_CUR_SIZE =$4068; + mmDCP3_CUR_SURFACE_ADDRESS_HIGH =$4069; + mmDCP3_CUR_POSITION =$406A; + mmDCP3_CUR_HOT_SPOT =$406B; + mmDCP3_CUR_COLOR1 =$406C; + mmDCP3_CUR_COLOR2 =$406D; + mmDCP3_CUR_UPDATE =$406E; + mmDCP3_CUR2_CONTROL =$406F; + mmDCP3_CUR2_SURFACE_ADDRESS =$4070; + mmDCP3_CUR2_SIZE =$4071; + mmDCP3_CUR2_SURFACE_ADDRESS_HIGH =$4072; + mmDCP3_CUR2_POSITION =$4073; + mmDCP3_CUR2_HOT_SPOT =$4074; + mmDCP3_CUR2_COLOR1 =$4075; + mmDCP3_CUR2_COLOR2 =$4076; + mmDCP3_CUR2_UPDATE =$4077; + mmDCP3_DC_LUT_RW_MODE =$4078; + mmDCP3_DC_LUT_RW_INDEX =$4079; + mmDCP3_DC_LUT_SEQ_COLOR =$407A; + mmDCP3_DC_LUT_PWL_DATA =$407B; + mmDCP3_DC_LUT_30_COLOR =$407C; + mmDCP3_DC_LUT_VGA_ACCESS_ENABLE =$407D; + mmDCP3_DC_LUT_WRITE_EN_MASK =$407E; + mmDCP3_DC_LUT_AUTOFILL =$407F; + mmDCP3_DC_LUT_CONTROL =$4080; + mmDCP3_DC_LUT_BLACK_OFFSET_BLUE =$4081; + mmDCP3_DC_LUT_BLACK_OFFSET_GREEN =$4082; + mmDCP3_DC_LUT_BLACK_OFFSET_RED =$4083; + mmDCP3_DC_LUT_WHITE_OFFSET_BLUE =$4084; + mmDCP3_DC_LUT_WHITE_OFFSET_GREEN =$4085; + mmDCP3_DC_LUT_WHITE_OFFSET_RED =$4086; + mmDCP3_DCP_CRC_CONTROL =$4087; + mmDCP3_DCP_CRC_MASK =$4088; + mmDCP3_DCP_CRC_CURRENT =$4089; + mmDCP3_DCP_CRC_LAST =$408B; + mmDCP3_DCP_DEBUG =$408D; + mmDCP3_GRPH_FLIP_RATE_CNTL =$408E; + mmDCP3_DCP_GSL_CONTROL =$4090; + mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK =$4091; + mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS =$4092; + mmDCP3_OVL_STEREOSYNC_FLIP =$4093; + mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH =$4094; + mmDCP3_DCP_TEST_DEBUG_INDEX =$4095; + mmDCP3_DCP_TEST_DEBUG_DATA =$4096; + mmDCP3_GRPH_STEREOSYNC_FLIP =$4097; + mmDCP3_DCP_DEBUG2 =$4098; + mmDCP3_CUR_REQUEST_FILTER_CNTL =$4099; + mmDCP3_CUR_STEREO_CONTROL =$409A; + mmDCP3_CUR2_STEREO_CONTROL =$409B; + mmDCP3_OUT_CLAMP_CONTROL_G_Y =$409C; + mmDCP3_OUT_CLAMP_CONTROL_B_CB =$409D; + mmDCP3_HW_ROTATION =$409E; + mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL =$409F; + mmDCP3_REGAMMA_CONTROL =$40A0; + mmDCP3_REGAMMA_LUT_INDEX =$40A1; + mmDCP3_REGAMMA_LUT_DATA =$40A2; + mmDCP3_REGAMMA_LUT_WRITE_EN_MASK =$40A3; + mmDCP3_REGAMMA_CNTLA_START_CNTL =$40A4; + mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL =$40A5; + mmDCP3_REGAMMA_CNTLA_END_CNTL1 =$40A6; + mmDCP3_REGAMMA_CNTLA_END_CNTL2 =$40A7; + mmDCP3_REGAMMA_CNTLA_REGION_0_1 =$40A8; + mmDCP3_REGAMMA_CNTLA_REGION_2_3 =$40A9; + mmDCP3_REGAMMA_CNTLA_REGION_4_5 =$40AA; + mmDCP3_REGAMMA_CNTLA_REGION_6_7 =$40AB; + mmDCP3_REGAMMA_CNTLA_REGION_8_9 =$40AC; + mmDCP3_REGAMMA_CNTLA_REGION_10_11 =$40AD; + mmDCP3_REGAMMA_CNTLA_REGION_12_13 =$40AE; + mmDCP3_REGAMMA_CNTLA_REGION_14_15 =$40AF; + mmDCP3_REGAMMA_CNTLB_START_CNTL =$40B0; + mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL =$40B1; + mmDCP3_REGAMMA_CNTLB_END_CNTL1 =$40B2; + mmDCP3_REGAMMA_CNTLB_END_CNTL2 =$40B3; + mmDCP3_REGAMMA_CNTLB_REGION_0_1 =$40B4; + mmDCP3_REGAMMA_CNTLB_REGION_2_3 =$40B5; + mmDCP3_REGAMMA_CNTLB_REGION_4_5 =$40B6; + mmDCP3_REGAMMA_CNTLB_REGION_6_7 =$40B7; + mmDCP3_REGAMMA_CNTLB_REGION_8_9 =$40B8; + mmDCP3_REGAMMA_CNTLB_REGION_10_11 =$40B9; + mmDCP3_REGAMMA_CNTLB_REGION_12_13 =$40BA; + mmDCP3_REGAMMA_CNTLB_REGION_14_15 =$40BB; + mmDCP3_ALPHA_CONTROL =$40BC; + mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS =$40BD; + mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH =$40BE; + mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS =$40BF; + mmLB3_LB_DATA_FORMAT =$40C0; + mmLB3_LB_MEMORY_CTRL =$40C1; + mmLB3_LB_MEMORY_SIZE_STATUS =$40C2; + mmLB3_LB_DESKTOP_HEIGHT =$40C3; + mmLB3_LB_VLINE_START_END =$40C4; + mmLB3_LB_VLINE2_START_END =$40C5; + mmLB3_LB_V_COUNTER =$40C6; + mmLB3_LB_SNAPSHOT_V_COUNTER =$40C7; + mmLB3_LB_INTERRUPT_MASK =$40C8; + mmLB3_LB_VLINE_STATUS =$40C9; + mmLB3_LB_VLINE2_STATUS =$40CA; + mmLB3_LB_VBLANK_STATUS =$40CB; + mmLB3_LB_SYNC_RESET_SEL =$40CC; + mmLB3_LB_BLACK_KEYER_R_CR =$40CD; + mmLB3_LB_BLACK_KEYER_G_Y =$40CE; + mmLB3_LB_BLACK_KEYER_B_CB =$40CF; + mmLB3_LB_KEYER_COLOR_CTRL =$40D0; + mmLB3_LB_KEYER_COLOR_R_CR =$40D1; + mmLB3_LB_KEYER_COLOR_G_Y =$40D2; + mmLB3_LB_KEYER_COLOR_B_CB =$40D3; + mmLB3_LB_KEYER_COLOR_REP_R_CR =$40D4; + mmLB3_LB_KEYER_COLOR_REP_G_Y =$40D5; + mmLB3_LB_KEYER_COLOR_REP_B_CB =$40D6; + mmLB3_LB_BUFFER_LEVEL_STATUS =$40D7; + mmLB3_LB_BUFFER_URGENCY_CTRL =$40D8; + mmLB3_LB_BUFFER_URGENCY_STATUS =$40D9; + mmLB3_LB_BUFFER_STATUS =$40DA; + mmLB2_DC_MVP_LB_CONTROL =$40DB; + mmLB3_LB_NO_OUTSTANDING_REQ_STATUS =$40DC; + mmLB3_MVP_AFR_FLIP_MODE =$40E0; + mmLB3_MVP_AFR_FLIP_FIFO_CNTL =$40E1; + mmLB3_MVP_FLIP_LINE_NUM_INSERT =$40E2; + mmLB3_DC_MVP_LB_CONTROL =$40E3; + mmLB3_LB_DEBUG =$40E4; + mmLB3_LB_DEBUG2 =$40E5; + mmLB3_LB_DEBUG3 =$40E6; + mmLB2_LB_DEBUG =$40FC; + mmLB3_LB_TEST_DEBUG_INDEX =$40FE; + mmLB3_LB_TEST_DEBUG_DATA =$40FF; + mmDCFE3_DCFE_CLOCK_CONTROL =$4100; + mmDCFE3_DCFE_SOFT_RESET =$4101; + mmDCFE3_DCFE_DBG_CONFIG =$4102; + mmDC_PERFMON6_PERFCOUNTER_CNTL =$4124; + mmDC_PERFMON6_PERFCOUNTER_STATE =$4125; + mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC =$4126; + mmDC_PERFMON6_PERFMON_CNTL =$4127; + mmDC_PERFMON6_PERFMON_CVALUE_LOW =$4128; + mmDC_PERFMON6_PERFMON_HI =$4129; + mmDC_PERFMON6_PERFMON_LOW =$412A; + mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX =$412B; + mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA =$412C; + mmDC_PERFMON6_PERFMON_CNTL2 =$412E; + mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 =$4130; + mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 =$4131; + mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL =$4132; + mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL =$4133; + mmDMIF_PG3_DPG_PIPE_DPM_CONTROL =$4134; + mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL =$4135; + mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL =$4136; + mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH =$4137; + mmDMIF_PG3_DPG_TEST_DEBUG_INDEX =$4138; + mmDMIF_PG3_DPG_TEST_DEBUG_DATA =$4139; + mmDMIF_PG3_DPG_REPEATER_PROGRAM =$413A; + mmDMIF_PG3_DPG_HW_DEBUG_A =$413B; + mmDMIF_PG3_DPG_HW_DEBUG_B =$413C; + mmDMIF_PG3_DPG_HW_DEBUG_11 =$413D; + mmSCL3_SCL_COEF_RAM_SELECT =$4140; + mmSCL3_SCL_COEF_RAM_TAP_DATA =$4141; + mmSCL3_SCL_MODE =$4142; + mmSCL3_SCL_TAP_CONTROL =$4143; + mmSCL3_SCL_CONTROL =$4144; + mmSCL3_SCL_BYPASS_CONTROL =$4145; + mmSCL3_SCL_MANUAL_REPLICATE_CONTROL =$4146; + mmSCL3_SCL_AUTOMATIC_MODE_CONTROL =$4147; + mmSCL3_SCL_HORZ_FILTER_CONTROL =$4148; + mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO =$4149; + mmSCL3_SCL_HORZ_FILTER_INIT =$414A; + mmSCL3_SCL_VERT_FILTER_CONTROL =$414B; + mmSCL3_SCL_VERT_FILTER_SCALE_RATIO =$414C; + mmSCL3_SCL_VERT_FILTER_INIT =$414D; + mmSCL3_SCL_VERT_FILTER_INIT_BOT =$414E; + mmSCL3_SCL_ROUND_OFFSET =$414F; + mmSCL2_SCL_VERT_FILTER_INIT =$4150; + mmSCL3_SCL_UPDATE =$4151; + mmSCL3_SCL_F_SHARP_CONTROL =$4153; + mmSCL3_SCL_ALU_CONTROL =$4154; + mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS =$4155; + mmSCL2_SCL_VERT_FILTER_INIT_BOT =$4157; + mmSCL3_VIEWPORT_START_SECONDARY =$415B; + mmSCL3_VIEWPORT_START =$415C; + mmSCL3_VIEWPORT_SIZE =$415D; + mmSCL3_EXT_OVERSCAN_LEFT_RIGHT =$415E; + mmSCL3_EXT_OVERSCAN_TOP_BOTTOM =$415F; + mmSCL3_SCL_MODE_CHANGE_DET1 =$4160; + mmSCL3_SCL_MODE_CHANGE_DET2 =$4161; + mmSCL3_SCL_MODE_CHANGE_DET3 =$4162; + mmSCL3_SCL_MODE_CHANGE_MASK =$4163; + mmSCL3_SCL_DEBUG2 =$4169; + mmSCL3_SCL_DEBUG =$416A; + mmSCL3_SCL_TEST_DEBUG_INDEX =$416B; + mmSCL3_SCL_TEST_DEBUG_DATA =$416C; + mmBLND3_BLND_CONTROL =$416D; + mmBLND3_SM_CONTROL2 =$416E; + mmBLND3_BLND_CONTROL2 =$416F; + mmBLND3_BLND_UPDATE =$4170; + mmBLND3_BLND_UNDERFLOW_INTERRUPT =$4171; + mmBLND3_BLND_V_UPDATE_LOCK =$4173; + mmBLND3_BLND_DEBUG =$4174; + mmBLND3_BLND_TEST_DEBUG_INDEX =$4175; + mmBLND3_BLND_TEST_DEBUG_DATA =$4176; + mmBLND3_BLND_REG_UPDATE_STATUS =$4177; + mmCRTC3_CRTC_3D_STRUCTURE_CONTROL =$4178; + mmCRTC3_CRTC_GSL_VSYNC_GAP =$4179; + mmCRTC3_CRTC_GSL_WINDOW =$417A; + mmCRTC3_CRTC_GSL_CONTROL =$417B; + mmCRTC3_CRTC_DCFE_CLOCK_CONTROL =$417C; + mmCRTC3_CRTC_H_BLANK_EARLY_NUM =$417D; + mmCRTC3_DCFE_DBG_SEL =$417E; + mmCRTC3_DCFE_MEM_PWR_CTRL =$417F; + mmCRTC3_CRTC_H_TOTAL =$4180; + mmCRTC3_CRTC_H_BLANK_START_END =$4181; + mmCRTC3_CRTC_H_SYNC_A =$4182; + mmCRTC3_CRTC_H_SYNC_A_CNTL =$4183; + mmCRTC3_CRTC_H_SYNC_B =$4184; + mmCRTC3_CRTC_H_SYNC_B_CNTL =$4185; + mmCRTC3_CRTC_VBI_END =$4186; + mmCRTC3_CRTC_V_TOTAL =$4187; + mmCRTC3_CRTC_V_TOTAL_MIN =$4188; + mmCRTC3_CRTC_V_TOTAL_MAX =$4189; + mmCRTC3_CRTC_V_TOTAL_CONTROL =$418A; + mmCRTC3_CRTC_V_TOTAL_INT_STATUS =$418B; + mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS =$418C; + mmCRTC3_CRTC_V_BLANK_START_END =$418D; + mmCRTC3_CRTC_V_SYNC_A =$418E; + mmCRTC3_CRTC_V_SYNC_A_CNTL =$418F; + mmCRTC3_CRTC_V_SYNC_B =$4190; + mmCRTC3_CRTC_V_SYNC_B_CNTL =$4191; + mmCRTC3_CRTC_DTMTEST_CNTL =$4192; + mmCRTC3_CRTC_DTMTEST_STATUS_POSITION =$4193; + mmCRTC3_CRTC_TRIGA_CNTL =$4194; + mmCRTC3_CRTC_TRIGA_MANUAL_TRIG =$4195; + mmCRTC3_CRTC_TRIGB_CNTL =$4196; + mmCRTC3_CRTC_TRIGB_MANUAL_TRIG =$4197; + mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL =$4198; + mmCRTC3_CRTC_FLOW_CONTROL =$4199; + mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE =$419A; + mmCRTC3_CRTC_AVSYNC_COUNTER =$419B; + mmCRTC3_CRTC_CONTROL =$419C; + mmCRTC3_CRTC_BLANK_CONTROL =$419D; + mmCRTC3_CRTC_INTERLACE_CONTROL =$419E; + mmCRTC3_CRTC_INTERLACE_STATUS =$419F; + mmCRTC3_CRTC_FIELD_INDICATION_CONTROL =$41A0; + mmCRTC3_CRTC_PIXEL_DATA_READBACK0 =$41A1; + mmCRTC3_CRTC_PIXEL_DATA_READBACK1 =$41A2; + mmCRTC3_CRTC_STATUS =$41A3; + mmCRTC3_CRTC_STATUS_POSITION =$41A4; + mmCRTC3_CRTC_NOM_VERT_POSITION =$41A5; + mmCRTC3_CRTC_STATUS_FRAME_COUNT =$41A6; + mmCRTC3_CRTC_STATUS_VF_COUNT =$41A7; + mmCRTC3_CRTC_STATUS_HV_COUNT =$41A8; + mmCRTC3_CRTC_COUNT_CONTROL =$41A9; + mmCRTC3_CRTC_COUNT_RESET =$41AA; + mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE =$41AB; + mmCRTC3_CRTC_VERT_SYNC_CONTROL =$41AC; + mmCRTC3_CRTC_STEREO_STATUS =$41AD; + mmCRTC3_CRTC_STEREO_CONTROL =$41AE; + mmCRTC3_CRTC_SNAPSHOT_STATUS =$41AF; + mmCRTC3_CRTC_SNAPSHOT_CONTROL =$41B0; + mmCRTC3_CRTC_SNAPSHOT_POSITION =$41B1; + mmCRTC3_CRTC_SNAPSHOT_FRAME =$41B2; + mmCRTC3_CRTC_START_LINE_CONTROL =$41B3; + mmCRTC3_CRTC_INTERRUPT_CONTROL =$41B4; + mmCRTC3_CRTC_UPDATE_LOCK =$41B5; + mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL =$41B6; + mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE =$41B7; + mmCRTC3_DCFE_MEM_PWR_CTRL2 =$41B8; + mmCRTC3_DCFE_MEM_PWR_STATUS =$41B9; + mmCRTC3_CRTC_TEST_PATTERN_CONTROL =$41BA; + mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS =$41BB; + mmCRTC3_CRTC_TEST_PATTERN_COLOR =$41BC; + mmCRTC3_MASTER_UPDATE_LOCK =$41BD; + mmCRTC3_MASTER_UPDATE_MODE =$41BE; + mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT =$41BF; + mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER =$41C0; + mmCRTC3_CRTC_MVP_STATUS =$41C1; + mmCRTC3_CRTC_MASTER_EN =$41C2; + mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT =$41C3; + mmCRTC3_CRTC_V_UPDATE_INT_STATUS =$41C4; + mmCRTC3_CRTC_TEST_DEBUG_INDEX =$41C6; + mmCRTC3_CRTC_TEST_DEBUG_DATA =$41C7; + mmCRTC3_CRTC_OVERSCAN_COLOR =$41C8; + mmCRTC3_CRTC_OVERSCAN_COLOR_EXT =$41C9; + mmCRTC3_CRTC_BLANK_DATA_COLOR =$41CA; + mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT =$41CB; + mmCRTC3_CRTC_BLACK_COLOR =$41CC; + mmCRTC3_CRTC_BLACK_COLOR_EXT =$41CD; + mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION =$41CE; + mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL =$41CF; + mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION =$41D0; + mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL =$41D1; + mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION =$41D2; + mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL =$41D3; + mmCRTC3_CRTC_CRC_CNTL =$41D4; + mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL =$41D5; + mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL =$41D6; + mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL =$41D7; + mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL =$41D8; + mmCRTC3_CRTC_CRC0_DATA_RG =$41D9; + mmCRTC3_CRTC_CRC0_DATA_B =$41DA; + mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL =$41DB; + mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL =$41DC; + mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL =$41DD; + mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL =$41DE; + mmCRTC3_CRTC_CRC1_DATA_RG =$41DF; + mmCRTC3_CRTC_CRC1_DATA_B =$41E0; + mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL =$41E1; + mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START =$41E2; + mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END =$41E3; + mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL =$41E4; + mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL =$41E5; + mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL =$41E6; + mmCRTC3_CRTC_STATIC_SCREEN_CONTROL =$41E7; + mmFMT3_FMT_CLAMP_COMPONENT_R =$41E8; + mmFMT3_FMT_CLAMP_COMPONENT_G =$41E9; + mmFMT3_FMT_CLAMP_COMPONENT_B =$41EA; + mmFMT3_FMT_TEST_DEBUG_INDEX =$41EB; + mmFMT3_FMT_TEST_DEBUG_DATA =$41EC; + mmFMT3_FMT_DYNAMIC_EXP_CNTL =$41ED; + mmFMT3_FMT_CONTROL =$41EE; + mmFMT3_FMT_FORCE_OUTPUT_CNTL =$41EF; + mmFMT3_FMT_FORCE_DATA_0_1 =$41F0; + mmFMT3_FMT_FORCE_DATA_2_3 =$41F1; + mmFMT3_FMT_BIT_DEPTH_CONTROL =$41F2; + mmFMT3_FMT_DITHER_RAND_R_SEED =$41F3; + mmFMT3_FMT_DITHER_RAND_G_SEED =$41F4; + mmFMT3_FMT_DITHER_RAND_B_SEED =$41F5; + mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL =$41F6; + mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$41F7; + mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$41F8; + mmFMT3_FMT_CLAMP_CNTL =$41F9; + mmFMT3_FMT_CRC_CNTL =$41FA; + mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK =$41FB; + mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK =$41FC; + mmFMT3_FMT_CRC_SIG_RED_GREEN =$41FD; + mmFMT3_FMT_CRC_SIG_BLUE_CONTROL =$41FE; + mmFMT3_FMT_DEBUG_CNTL =$41FF; + mmDCP4_GRPH_ENABLE =$4200; + mmDCP4_GRPH_CONTROL =$4201; + mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS =$4204; + mmDCP4_GRPH_PITCH =$4206; + mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH =$4207; + mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH =$4208; + mmDCP4_GRPH_SURFACE_OFFSET_X =$4209; + mmDCP4_GRPH_SURFACE_OFFSET_Y =$420A; + mmDCP4_GRPH_X_START =$420B; + mmDCP4_INPUT_GAMMA_CONTROL =$4210; + mmDCP4_GRPH_UPDATE =$4211; + mmDCP4_GRPH_FLIP_CONTROL =$4212; + mmDCP4_GRPH_SURFACE_ADDRESS_INUSE =$4213; + mmDCP4_GRPH_DFQ_CONTROL =$4214; + mmDCP4_GRPH_DFQ_STATUS =$4215; + mmDCP4_OVL_SURFACE_ADDRESS =$4220; + mmDCP4_OVL_UPDATE =$4227; + mmDCP4_OVL_SURFACE_ADDRESS_INUSE =$4228; + mmDCP4_OVL_DFQ_CONTROL =$4229; + mmDCP4_OVL_DFQ_STATUS =$422A; + mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE =$422B; + mmDCP4_OVLSCL_EDGE_PIXEL_CNTL =$422C; + mmDCP4_PRESCALE_GRPH_CONTROL =$422D; + mmDCP4_PRESCALE_VALUES_GRPH_R =$422E; + mmDCP4_PRESCALE_VALUES_GRPH_G =$422F; + mmDCP4_PRESCALE_VALUES_GRPH_B =$4230; + mmDCP4_PRESCALE_OVL_CONTROL =$4231; + mmDCP4_PRESCALE_VALUES_OVL_CB =$4232; + mmDCP4_PRESCALE_VALUES_OVL_Y =$4233; + mmDCP4_PRESCALE_VALUES_OVL_CR =$4234; + mmDCP4_INPUT_CSC_CONTROL =$4235; + mmDCP4_INPUT_CSC_C11_C12 =$4236; + mmDCP4_INPUT_CSC_C13_C14 =$4237; + mmDCP4_INPUT_CSC_C21_C22 =$4238; + mmDCP4_INPUT_CSC_C23_C24 =$4239; + mmDCP4_INPUT_CSC_C31_C32 =$423A; + mmDCP4_INPUT_CSC_C33_C34 =$423B; + mmDCP4_OUTPUT_CSC_CONTROL =$423C; + mmDCP4_OUTPUT_CSC_C11_C12 =$423D; + mmDCP4_OUTPUT_CSC_C13_C14 =$423E; + mmDCP4_OUTPUT_CSC_C21_C22 =$423F; + mmDCP4_OUTPUT_CSC_C23_C24 =$4240; + mmDCP4_OUTPUT_CSC_C31_C32 =$4241; + mmDCP4_OUTPUT_CSC_C33_C34 =$4242; + mmDCP4_COMM_MATRIXA_TRANS_C11_C12 =$4243; + mmDCP4_COMM_MATRIXA_TRANS_C13_C14 =$4244; + mmDCP4_COMM_MATRIXA_TRANS_C21_C22 =$4245; + mmDCP4_COMM_MATRIXA_TRANS_C23_C24 =$4246; + mmDCP4_COMM_MATRIXA_TRANS_C31_C32 =$4247; + mmDCP4_COMM_MATRIXA_TRANS_C33_C34 =$4248; + mmDCP4_COMM_MATRIXB_TRANS_C11_C12 =$4249; + mmDCP4_COMM_MATRIXB_TRANS_C13_C14 =$424A; + mmDCP4_COMM_MATRIXB_TRANS_C21_C22 =$424B; + mmDCP4_COMM_MATRIXB_TRANS_C23_C24 =$424C; + mmDCP4_COMM_MATRIXB_TRANS_C31_C32 =$424D; + mmDCP4_COMM_MATRIXB_TRANS_C33_C34 =$424E; + mmDCP4_DENORM_CONTROL =$4250; + mmDCP4_OUT_ROUND_CONTROL =$4251; + mmDCP4_OUT_CLAMP_CONTROL_R_CR =$4252; + mmDCP4_KEY_CONTROL =$4253; + mmDCP4_KEY_RANGE_ALPHA =$4254; + mmDCP4_KEY_RANGE_RED =$4255; + mmDCP4_KEY_RANGE_GREEN =$4256; + mmDCP4_KEY_RANGE_BLUE =$4257; + mmDCP4_DEGAMMA_CONTROL =$4258; + mmDCP4_GAMUT_REMAP_CONTROL =$4259; + mmDCP4_GAMUT_REMAP_C11_C12 =$425A; + mmDCP4_GAMUT_REMAP_C13_C14 =$425B; + mmDCP4_GAMUT_REMAP_C21_C22 =$425C; + mmDCP4_GAMUT_REMAP_C23_C24 =$425D; + mmDCP4_GAMUT_REMAP_C31_C32 =$425E; + mmDCP4_GAMUT_REMAP_C33_C34 =$425F; + mmDCP4_DCP_SPATIAL_DITHER_CNTL =$4260; + mmDCP4_DCP_RANDOM_SEEDS =$4261; + mmDCP4_DCP_FP_CONVERTED_FIELD =$4265; + mmDCP4_CUR_CONTROL =$4266; + mmDCP4_CUR_SURFACE_ADDRESS =$4267; + mmDCP4_CUR_SIZE =$4268; + mmDCP4_CUR_SURFACE_ADDRESS_HIGH =$4269; + mmDCP4_CUR_POSITION =$426A; + mmDCP4_CUR_HOT_SPOT =$426B; + mmDCP4_CUR_COLOR1 =$426C; + mmDCP4_CUR_COLOR2 =$426D; + mmDCP4_CUR_UPDATE =$426E; + mmDCP4_CUR2_CONTROL =$426F; + mmDCP4_CUR2_SURFACE_ADDRESS =$4270; + mmDCP4_CUR2_SIZE =$4271; + mmDCP4_CUR2_SURFACE_ADDRESS_HIGH =$4272; + mmDCP4_CUR2_POSITION =$4273; + mmDCP4_CUR2_HOT_SPOT =$4274; + mmDCP4_CUR2_COLOR1 =$4275; + mmDCP4_CUR2_COLOR2 =$4276; + mmDCP4_CUR2_UPDATE =$4277; + mmDCP4_DC_LUT_RW_MODE =$4278; + mmDCP4_DC_LUT_RW_INDEX =$4279; + mmDCP4_DC_LUT_SEQ_COLOR =$427A; + mmDCP4_DC_LUT_PWL_DATA =$427B; + mmDCP4_DC_LUT_VGA_ACCESS_ENABLE =$427D; + mmDCP4_DC_LUT_WHITE_OFFSET_GREEN =$4285; + mmDCP4_DCP_CRC_MASK =$4288; + mmDCP4_DCP_CRC_CURRENT =$4289; + mmDCP4_DCP_CRC_LAST =$428B; + mmDCP4_DCP_DEBUG =$428D; + mmDCP4_GRPH_FLIP_RATE_CNTL =$428E; + mmDCP4_DCP_GSL_CONTROL =$4290; + mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK =$4291; + mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS =$4292; + mmDCP4_OVL_STEREOSYNC_FLIP =$4293; + mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH =$4294; + mmDCP4_DCP_TEST_DEBUG_INDEX =$4295; + mmDCP4_DCP_TEST_DEBUG_DATA =$4296; + mmDCP4_GRPH_STEREOSYNC_FLIP =$4297; + mmDCP4_DCP_DEBUG2 =$4298; + mmDCP4_CUR_REQUEST_FILTER_CNTL =$4299; + mmDCP4_CUR_STEREO_CONTROL =$429A; + mmDCP4_CUR2_STEREO_CONTROL =$429B; + mmDCP4_OUT_CLAMP_CONTROL_G_Y =$429C; + mmDCP4_OUT_CLAMP_CONTROL_B_CB =$429D; + mmDCP4_HW_ROTATION =$429E; + mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL =$429F; + mmDCP4_REGAMMA_CONTROL =$42A0; + mmDCP4_REGAMMA_LUT_INDEX =$42A1; + mmDCP4_REGAMMA_LUT_DATA =$42A2; + mmDCP4_REGAMMA_LUT_WRITE_EN_MASK =$42A3; + mmDCP4_REGAMMA_CNTLA_START_CNTL =$42A4; + mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL =$42A5; + mmDCP4_REGAMMA_CNTLA_END_CNTL1 =$42A6; + mmDCP4_REGAMMA_CNTLA_END_CNTL2 =$42A7; + mmDCP4_REGAMMA_CNTLA_REGION_0_1 =$42A8; + mmDCP4_REGAMMA_CNTLA_REGION_2_3 =$42A9; + mmDCP4_REGAMMA_CNTLA_REGION_4_5 =$42AA; + mmDCP4_REGAMMA_CNTLA_REGION_6_7 =$42AB; + mmDCP4_REGAMMA_CNTLA_REGION_8_9 =$42AC; + mmDCP4_REGAMMA_CNTLA_REGION_10_11 =$42AD; + mmDCP4_REGAMMA_CNTLA_REGION_12_13 =$42AE; + mmDCP4_REGAMMA_CNTLA_REGION_14_15 =$42AF; + mmDCP4_REGAMMA_CNTLB_START_CNTL =$42B0; + mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL =$42B1; + mmDCP4_REGAMMA_CNTLB_END_CNTL1 =$42B2; + mmDCP4_REGAMMA_CNTLB_END_CNTL2 =$42B3; + mmDCP4_REGAMMA_CNTLB_REGION_0_1 =$42B4; + mmDCP4_REGAMMA_CNTLB_REGION_2_3 =$42B5; + mmDCP4_REGAMMA_CNTLB_REGION_4_5 =$42B6; + mmDCP4_REGAMMA_CNTLB_REGION_6_7 =$42B7; + mmDCP4_REGAMMA_CNTLB_REGION_8_9 =$42B8; + mmDCP4_REGAMMA_CNTLB_REGION_10_11 =$42B9; + mmDCP4_REGAMMA_CNTLB_REGION_12_13 =$42BA; + mmDCP4_REGAMMA_CNTLB_REGION_14_15 =$42BB; + mmDCP4_ALPHA_CONTROL =$42BC; + mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS =$42BD; + mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH =$42BE; + mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS =$42BF; + mmLB4_LB_DATA_FORMAT =$42C0; + mmLB4_LB_MEMORY_CTRL =$42C1; + mmLB4_LB_MEMORY_SIZE_STATUS =$42C2; + mmLB4_LB_DESKTOP_HEIGHT =$42C3; + mmLB4_LB_VLINE_START_END =$42C4; + mmLB4_LB_VLINE2_START_END =$42C5; + mmLB4_LB_V_COUNTER =$42C6; + mmLB4_LB_SNAPSHOT_V_COUNTER =$42C7; + mmLB4_LB_INTERRUPT_MASK =$42C8; + mmLB4_LB_VLINE_STATUS =$42C9; + mmLB4_LB_VLINE2_STATUS =$42CA; + mmLB4_LB_VBLANK_STATUS =$42CB; + mmLB4_LB_SYNC_RESET_SEL =$42CC; + mmLB4_LB_BLACK_KEYER_R_CR =$42CD; + mmLB4_LB_BLACK_KEYER_G_Y =$42CE; + mmLB4_LB_BLACK_KEYER_B_CB =$42CF; + mmLB4_LB_KEYER_COLOR_CTRL =$42D0; + mmLB4_LB_KEYER_COLOR_R_CR =$42D1; + mmLB4_LB_KEYER_COLOR_G_Y =$42D2; + mmLB4_LB_KEYER_COLOR_B_CB =$42D3; + mmLB4_LB_KEYER_COLOR_REP_R_CR =$42D4; + mmLB4_LB_KEYER_COLOR_REP_G_Y =$42D5; + mmLB4_LB_KEYER_COLOR_REP_B_CB =$42D6; + mmLB4_LB_BUFFER_LEVEL_STATUS =$42D7; + mmLB4_LB_BUFFER_URGENCY_CTRL =$42D8; + mmLB4_LB_BUFFER_URGENCY_STATUS =$42D9; + mmLB4_LB_BUFFER_STATUS =$42DA; + mmLB4_LB_NO_OUTSTANDING_REQ_STATUS =$42DC; + mmLB4_MVP_AFR_FLIP_MODE =$42E0; + mmLB4_MVP_AFR_FLIP_FIFO_CNTL =$42E1; + mmLB4_MVP_FLIP_LINE_NUM_INSERT =$42E2; + mmLB4_DC_MVP_LB_CONTROL =$42E3; + mmLB4_LB_DEBUG =$42E4; + mmLB4_LB_DEBUG2 =$42E5; + mmLB4_LB_DEBUG3 =$42E6; + mmLB4_LB_TEST_DEBUG_INDEX =$42FE; + mmLB4_LB_TEST_DEBUG_DATA =$42FF; + mmDCFE4_DCFE_CLOCK_CONTROL =$4300; + mmDCFE4_DCFE_SOFT_RESET =$4301; + mmDCFE4_DCFE_DBG_CONFIG =$4302; + mmDC_PERFMON7_PERFCOUNTER_CNTL =$4324; + mmDC_PERFMON7_PERFCOUNTER_STATE =$4325; + mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC =$4326; + mmDC_PERFMON7_PERFMON_CNTL =$4327; + mmDC_PERFMON7_PERFMON_CVALUE_LOW =$4328; + mmDC_PERFMON7_PERFMON_HI =$4329; + mmDC_PERFMON7_PERFMON_LOW =$432A; + mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX =$432B; + mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA =$432C; + mmDC_PERFMON7_PERFMON_CNTL2 =$432E; + mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 =$4330; + mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 =$4331; + mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL =$4332; + mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL =$4333; + mmDMIF_PG4_DPG_PIPE_DPM_CONTROL =$4334; + mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL =$4335; + mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL =$4336; + mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH =$4337; + mmDMIF_PG4_DPG_TEST_DEBUG_INDEX =$4338; + mmDMIF_PG4_DPG_TEST_DEBUG_DATA =$4339; + mmDMIF_PG4_DPG_REPEATER_PROGRAM =$433A; + mmDMIF_PG4_DPG_HW_DEBUG_A =$433B; + mmDMIF_PG4_DPG_HW_DEBUG_B =$433C; + mmDMIF_PG4_DPG_HW_DEBUG_11 =$433D; + mmSCL4_SCL_COEF_RAM_SELECT =$4340; + mmSCL4_SCL_COEF_RAM_TAP_DATA =$4341; + mmSCL4_SCL_MODE =$4342; + mmSCL4_SCL_TAP_CONTROL =$4343; + mmSCL4_SCL_CONTROL =$4344; + mmSCL4_SCL_BYPASS_CONTROL =$4345; + mmSCL4_SCL_MANUAL_REPLICATE_CONTROL =$4346; + mmSCL4_SCL_AUTOMATIC_MODE_CONTROL =$4347; + mmSCL4_SCL_HORZ_FILTER_CONTROL =$4348; + mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO =$4349; + mmSCL4_SCL_HORZ_FILTER_INIT =$434A; + mmSCL4_SCL_VERT_FILTER_CONTROL =$434B; + mmSCL4_SCL_VERT_FILTER_SCALE_RATIO =$434C; + mmSCL4_SCL_VERT_FILTER_INIT =$434D; + mmSCL4_SCL_VERT_FILTER_INIT_BOT =$434E; + mmSCL4_SCL_ROUND_OFFSET =$434F; + mmSCL4_SCL_UPDATE =$4351; + mmSCL4_SCL_F_SHARP_CONTROL =$4353; + mmSCL4_SCL_ALU_CONTROL =$4354; + mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS =$4355; + mmSCL4_VIEWPORT_START_SECONDARY =$435B; + mmSCL4_VIEWPORT_START =$435C; + mmSCL4_VIEWPORT_SIZE =$435D; + mmSCL4_EXT_OVERSCAN_LEFT_RIGHT =$435E; + mmSCL4_EXT_OVERSCAN_TOP_BOTTOM =$435F; + mmSCL4_SCL_MODE_CHANGE_DET1 =$4360; + mmSCL4_SCL_MODE_CHANGE_DET2 =$4361; + mmSCL4_SCL_MODE_CHANGE_DET3 =$4362; + mmSCL4_SCL_MODE_CHANGE_MASK =$4363; + mmSCL4_SCL_DEBUG2 =$4369; + mmSCL4_SCL_DEBUG =$436A; + mmSCL4_SCL_TEST_DEBUG_INDEX =$436B; + mmSCL4_SCL_TEST_DEBUG_DATA =$436C; + mmBLND4_BLND_CONTROL =$436D; + mmBLND4_SM_CONTROL2 =$436E; + mmBLND4_BLND_CONTROL2 =$436F; + mmBLND4_BLND_UPDATE =$4370; + mmBLND4_BLND_UNDERFLOW_INTERRUPT =$4371; + mmBLND4_BLND_V_UPDATE_LOCK =$4373; + mmBLND4_BLND_DEBUG =$4374; + mmBLND4_BLND_TEST_DEBUG_INDEX =$4375; + mmBLND4_BLND_TEST_DEBUG_DATA =$4376; + mmBLND4_BLND_REG_UPDATE_STATUS =$4377; + mmCRTC4_CRTC_3D_STRUCTURE_CONTROL =$4378; + mmCRTC4_CRTC_GSL_VSYNC_GAP =$4379; + mmCRTC4_CRTC_GSL_WINDOW =$437A; + mmCRTC4_CRTC_GSL_CONTROL =$437B; + mmCRTC4_CRTC_DCFE_CLOCK_CONTROL =$437C; + mmCRTC4_CRTC_H_BLANK_EARLY_NUM =$437D; + mmCRTC4_DCFE_DBG_SEL =$437E; + mmCRTC4_DCFE_MEM_PWR_CTRL =$437F; + mmCRTC4_CRTC_V_TOTAL_CONTROL =$438A; + mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS =$438C; + mmCRTC4_CRTC_V_SYNC_A =$438E; + mmCRTC4_CRTC_V_SYNC_A_CNTL =$438F; + mmCRTC4_CRTC_V_SYNC_B =$4390; + mmCRTC4_CRTC_DTMTEST_CNTL =$4392; + mmCRTC4_CRTC_DTMTEST_STATUS_POSITION =$4393; + mmCRTC4_CRTC_TRIGA_CNTL =$4394; + mmCRTC4_CRTC_TRIGB_MANUAL_TRIG =$4397; + mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL =$4398; + mmCRTC4_CRTC_FLOW_CONTROL =$4399; + mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE =$439A; + mmCRTC4_CRTC_AVSYNC_COUNTER =$439B; + mmCRTC4_CRTC_CONTROL =$439C; + mmCRTC4_CRTC_BLANK_CONTROL =$439D; + mmCRTC4_CRTC_INTERLACE_CONTROL =$439E; + mmCRTC4_CRTC_INTERLACE_STATUS =$439F; + mmCRTC4_CRTC_FIELD_INDICATION_CONTROL =$43A0; + mmCRTC4_CRTC_PIXEL_DATA_READBACK0 =$43A1; + mmCRTC4_CRTC_PIXEL_DATA_READBACK1 =$43A2; + mmCRTC4_CRTC_STATUS =$43A3; + mmCRTC4_CRTC_STATUS_POSITION =$43A4; + mmCRTC4_CRTC_NOM_VERT_POSITION =$43A5; + mmCRTC4_CRTC_STATUS_FRAME_COUNT =$43A6; + mmCRTC4_CRTC_STATUS_VF_COUNT =$43A7; + mmCRTC4_CRTC_STATUS_HV_COUNT =$43A8; + mmCRTC4_CRTC_COUNT_CONTROL =$43A9; + mmCRTC4_CRTC_COUNT_RESET =$43AA; + mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE =$43AB; + mmCRTC4_CRTC_VERT_SYNC_CONTROL =$43AC; + mmCRTC4_CRTC_STEREO_STATUS =$43AD; + mmCRTC4_CRTC_STEREO_CONTROL =$43AE; + mmCRTC4_CRTC_SNAPSHOT_STATUS =$43AF; + mmCRTC4_CRTC_SNAPSHOT_CONTROL =$43B0; + mmCRTC4_CRTC_SNAPSHOT_POSITION =$43B1; + mmCRTC4_CRTC_SNAPSHOT_FRAME =$43B2; + mmCRTC4_CRTC_START_LINE_CONTROL =$43B3; + mmCRTC4_CRTC_INTERRUPT_CONTROL =$43B4; + mmCRTC4_CRTC_UPDATE_LOCK =$43B5; + mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL =$43B6; + mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE =$43B7; + mmCRTC4_DCFE_MEM_PWR_CTRL2 =$43B8; + mmCRTC4_DCFE_MEM_PWR_STATUS =$43B9; + mmCRTC4_CRTC_TEST_PATTERN_CONTROL =$43BA; + mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS =$43BB; + mmCRTC4_CRTC_TEST_PATTERN_COLOR =$43BC; + mmCRTC4_MASTER_UPDATE_LOCK =$43BD; + mmCRTC4_MASTER_UPDATE_MODE =$43BE; + mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT =$43BF; + mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER =$43C0; + mmCRTC4_CRTC_MVP_STATUS =$43C1; + mmCRTC4_CRTC_MASTER_EN =$43C2; + mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT =$43C3; + mmCRTC4_CRTC_V_UPDATE_INT_STATUS =$43C4; + mmCRTC4_CRTC_TEST_DEBUG_INDEX =$43C6; + mmCRTC4_CRTC_TEST_DEBUG_DATA =$43C7; + mmCRTC4_CRTC_OVERSCAN_COLOR =$43C8; + mmCRTC4_CRTC_OVERSCAN_COLOR_EXT =$43C9; + mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT =$43CB; + mmCRTC4_CRTC_BLACK_COLOR =$43CC; + mmCRTC4_CRTC_BLACK_COLOR_EXT =$43CD; + mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION =$43CE; + mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL =$43CF; + mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION =$43D0; + mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL =$43D1; + mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION =$43D2; + mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL =$43D3; + mmCRTC4_CRTC_CRC_CNTL =$43D4; + mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL =$43D5; + mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL =$43D6; + mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL =$43D7; + mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL =$43D8; + mmCRTC4_CRTC_CRC0_DATA_RG =$43D9; + mmCRTC4_CRTC_CRC0_DATA_B =$43DA; + mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL =$43DB; + mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL =$43DC; + mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL =$43DD; + mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL =$43DE; + mmCRTC4_CRTC_CRC1_DATA_RG =$43DF; + mmCRTC4_CRTC_CRC1_DATA_B =$43E0; + mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL =$43E1; + mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START =$43E2; + mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END =$43E3; + mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL =$43E4; + mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL =$43E5; + mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL =$43E6; + mmCRTC4_CRTC_STATIC_SCREEN_CONTROL =$43E7; + mmFMT4_FMT_CLAMP_COMPONENT_R =$43E8; + mmFMT4_FMT_CLAMP_COMPONENT_G =$43E9; + mmFMT4_FMT_CLAMP_COMPONENT_B =$43EA; + mmFMT4_FMT_TEST_DEBUG_INDEX =$43EB; + mmFMT4_FMT_TEST_DEBUG_DATA =$43EC; + mmFMT4_FMT_DYNAMIC_EXP_CNTL =$43ED; + mmFMT4_FMT_CONTROL =$43EE; + mmFMT4_FMT_FORCE_OUTPUT_CNTL =$43EF; + mmFMT4_FMT_FORCE_DATA_0_1 =$43F0; + mmFMT4_FMT_FORCE_DATA_2_3 =$43F1; + mmFMT4_FMT_BIT_DEPTH_CONTROL =$43F2; + mmFMT4_FMT_DITHER_RAND_R_SEED =$43F3; + mmFMT4_FMT_DITHER_RAND_G_SEED =$43F4; + mmFMT4_FMT_DITHER_RAND_B_SEED =$43F5; + mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL =$43F6; + mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$43F7; + mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$43F8; + mmFMT4_FMT_CLAMP_CNTL =$43F9; + mmFMT4_FMT_CRC_CNTL =$43FA; + mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK =$43FB; + mmFMT4_FMT_CRC_SIG_RED_GREEN =$43FD; + mmDCP5_GRPH_ENABLE =$4400; + mmDCP5_GRPH_CONTROL =$4401; + mmDCP5_GRPH_LUT_10BIT_BYPASS =$4402; + mmDCP5_GRPH_SWAP_CNTL =$4403; + mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS =$4404; + mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS =$4405; + mmDCP5_GRPH_PITCH =$4406; + mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH =$4407; + mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH =$4408; + mmDCP5_GRPH_SURFACE_OFFSET_X =$4409; + mmDCP5_GRPH_SURFACE_OFFSET_Y =$440A; + mmDCP5_GRPH_X_START =$440B; + mmDCP5_GRPH_Y_START =$440C; + mmDCP5_GRPH_X_END =$440D; + mmDCP5_GRPH_Y_END =$440E; + mmDCP5_INPUT_GAMMA_CONTROL =$4410; + mmDCP5_GRPH_UPDATE =$4411; + mmDCP5_GRPH_FLIP_CONTROL =$4412; + mmDCP5_GRPH_SURFACE_ADDRESS_INUSE =$4413; + mmDCP5_GRPH_DFQ_CONTROL =$4414; + mmDCP5_GRPH_DFQ_STATUS =$4415; + mmDCP5_GRPH_INTERRUPT_STATUS =$4416; + mmDCP5_GRPH_INTERRUPT_CONTROL =$4417; + mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE =$4418; + mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS =$4419; + mmDCP5_GRPH_COMPRESS_PITCH =$441A; + mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH =$441B; + mmDCP5_OVL_ENABLE =$441C; + mmDCP5_OVL_CONTROL1 =$441D; + mmDCP5_OVL_CONTROL2 =$441E; + mmDCP5_OVL_SWAP_CNTL =$441F; + mmDCP5_OVL_SURFACE_ADDRESS =$4420; + mmDCP5_OVL_PITCH =$4421; + mmDCP5_OVL_SURFACE_ADDRESS_HIGH =$4422; + mmDCP5_OVL_SURFACE_OFFSET_X =$4423; + mmDCP5_OVL_SURFACE_OFFSET_Y =$4424; + mmDCP5_OVL_START =$4425; + mmDCP5_OVL_END =$4426; + mmDCP5_OVL_UPDATE =$4427; + mmDCP5_OVL_SURFACE_ADDRESS_INUSE =$4428; + mmDCP5_OVL_DFQ_CONTROL =$4429; + mmDCP5_OVL_DFQ_STATUS =$442A; + mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE =$442B; + mmDCP5_OVLSCL_EDGE_PIXEL_CNTL =$442C; + mmDCP5_PRESCALE_GRPH_CONTROL =$442D; + mmDCP5_PRESCALE_VALUES_GRPH_R =$442E; + mmDCP5_PRESCALE_VALUES_GRPH_G =$442F; + mmDCP5_PRESCALE_VALUES_GRPH_B =$4430; + mmDCP5_PRESCALE_OVL_CONTROL =$4431; + mmDCP5_PRESCALE_VALUES_OVL_CB =$4432; + mmDCP5_PRESCALE_VALUES_OVL_Y =$4433; + mmDCP5_PRESCALE_VALUES_OVL_CR =$4434; + mmDCP5_INPUT_CSC_CONTROL =$4435; + mmDCP5_INPUT_CSC_C11_C12 =$4436; + mmDCP5_INPUT_CSC_C13_C14 =$4437; + mmDCP5_INPUT_CSC_C21_C22 =$4438; + mmDCP5_INPUT_CSC_C23_C24 =$4439; + mmDCP5_INPUT_CSC_C31_C32 =$443A; + mmDCP5_INPUT_CSC_C33_C34 =$443B; + mmDCP5_OUTPUT_CSC_CONTROL =$443C; + mmDCP5_OUTPUT_CSC_C11_C12 =$443D; + mmDCP5_OUTPUT_CSC_C13_C14 =$443E; + mmDCP5_OUTPUT_CSC_C21_C22 =$443F; + mmDCP5_OUTPUT_CSC_C23_C24 =$4440; + mmDCP5_OUTPUT_CSC_C31_C32 =$4441; + mmDCP5_OUTPUT_CSC_C33_C34 =$4442; + mmDCP5_COMM_MATRIXA_TRANS_C11_C12 =$4443; + mmDCP5_COMM_MATRIXA_TRANS_C13_C14 =$4444; + mmDCP5_COMM_MATRIXA_TRANS_C21_C22 =$4445; + mmDCP5_COMM_MATRIXA_TRANS_C23_C24 =$4446; + mmDCP5_COMM_MATRIXA_TRANS_C31_C32 =$4447; + mmDCP5_COMM_MATRIXA_TRANS_C33_C34 =$4448; + mmDCP5_COMM_MATRIXB_TRANS_C11_C12 =$4449; + mmDCP5_COMM_MATRIXB_TRANS_C13_C14 =$444A; + mmDCP5_COMM_MATRIXB_TRANS_C21_C22 =$444B; + mmDCP5_COMM_MATRIXB_TRANS_C23_C24 =$444C; + mmDCP5_COMM_MATRIXB_TRANS_C31_C32 =$444D; + mmDCP5_COMM_MATRIXB_TRANS_C33_C34 =$444E; + mmDCP5_DENORM_CONTROL =$4450; + mmDCP5_OUT_ROUND_CONTROL =$4451; + mmDCP5_OUT_CLAMP_CONTROL_R_CR =$4452; + mmDCP5_KEY_CONTROL =$4453; + mmDCP5_KEY_RANGE_ALPHA =$4454; + mmDCP5_KEY_RANGE_RED =$4455; + mmDCP5_KEY_RANGE_GREEN =$4456; + mmDCP5_KEY_RANGE_BLUE =$4457; + mmDCP5_DEGAMMA_CONTROL =$4458; + mmDCP5_GAMUT_REMAP_CONTROL =$4459; + mmDCP5_GAMUT_REMAP_C11_C12 =$445A; + mmDCP5_GAMUT_REMAP_C13_C14 =$445B; + mmDCP5_GAMUT_REMAP_C21_C22 =$445C; + mmDCP5_GAMUT_REMAP_C23_C24 =$445D; + mmDCP5_GAMUT_REMAP_C31_C32 =$445E; + mmDCP5_GAMUT_REMAP_C33_C34 =$445F; + mmDCP5_DCP_SPATIAL_DITHER_CNTL =$4460; + mmDCP5_DCP_RANDOM_SEEDS =$4461; + mmDCP5_DCP_FP_CONVERTED_FIELD =$4465; + mmDCP5_CUR_CONTROL =$4466; + mmDCP5_CUR_SURFACE_ADDRESS =$4467; + mmDCP5_CUR_SIZE =$4468; + mmDCP5_CUR_SURFACE_ADDRESS_HIGH =$4469; + mmDCP5_CUR_POSITION =$446A; + mmDCP5_CUR_HOT_SPOT =$446B; + mmDCP5_CUR_COLOR1 =$446C; + mmDCP5_CUR_COLOR2 =$446D; + mmDCP5_CUR_UPDATE =$446E; + mmDCP5_CUR2_CONTROL =$446F; + mmDCP5_CUR2_SURFACE_ADDRESS =$4470; + mmDCP5_CUR2_SIZE =$4471; + mmDCP5_CUR2_SURFACE_ADDRESS_HIGH =$4472; + mmDCP5_CUR2_POSITION =$4473; + mmDCP5_CUR2_HOT_SPOT =$4474; + mmDCP5_CUR2_COLOR1 =$4475; + mmDCP5_CUR2_COLOR2 =$4476; + mmDCP5_CUR2_UPDATE =$4477; + mmDCP5_DC_LUT_RW_MODE =$4478; + mmDCP5_DC_LUT_RW_INDEX =$4479; + mmDCP5_DC_LUT_SEQ_COLOR =$447A; + mmDCP5_DC_LUT_PWL_DATA =$447B; + mmDCP5_DC_LUT_30_COLOR =$447C; + mmDCP5_DC_LUT_VGA_ACCESS_ENABLE =$447D; + mmDCP5_DC_LUT_WRITE_EN_MASK =$447E; + mmDCP5_DC_LUT_AUTOFILL =$447F; + mmDCP5_DC_LUT_CONTROL =$4480; + mmDCP5_DC_LUT_BLACK_OFFSET_BLUE =$4481; + mmDCP5_DC_LUT_BLACK_OFFSET_GREEN =$4482; + mmDCP5_DC_LUT_BLACK_OFFSET_RED =$4483; + mmDCP5_DC_LUT_WHITE_OFFSET_BLUE =$4484; + mmDCP5_DC_LUT_WHITE_OFFSET_GREEN =$4485; + mmDCP5_DC_LUT_WHITE_OFFSET_RED =$4486; + mmDCP5_DCP_CRC_CONTROL =$4487; + mmDCP5_DCP_CRC_MASK =$4488; + mmDCP5_DCP_CRC_CURRENT =$4489; + mmDCP5_DCP_CRC_LAST =$448B; + mmDCP5_DCP_DEBUG =$448D; + mmDCP5_GRPH_FLIP_RATE_CNTL =$448E; + mmDCP5_DCP_GSL_CONTROL =$4490; + mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK =$4491; + mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS =$4492; + mmDCP5_OVL_STEREOSYNC_FLIP =$4493; + mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH =$4494; + mmDCP5_DCP_TEST_DEBUG_INDEX =$4495; + mmDCP5_DCP_TEST_DEBUG_DATA =$4496; + mmDCP5_GRPH_STEREOSYNC_FLIP =$4497; + mmDCP5_DCP_DEBUG2 =$4498; + mmDCP5_CUR_REQUEST_FILTER_CNTL =$4499; + mmDCP5_CUR_STEREO_CONTROL =$449A; + mmDCP5_CUR2_STEREO_CONTROL =$449B; + mmDCP5_OUT_CLAMP_CONTROL_G_Y =$449C; + mmDCP5_OUT_CLAMP_CONTROL_B_CB =$449D; + mmDCP5_HW_ROTATION =$449E; + mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL =$449F; + mmDCP5_REGAMMA_CONTROL =$44A0; + mmDCP5_REGAMMA_LUT_INDEX =$44A1; + mmDCP5_REGAMMA_LUT_DATA =$44A2; + mmDCP5_REGAMMA_LUT_WRITE_EN_MASK =$44A3; + mmDCP5_REGAMMA_CNTLA_START_CNTL =$44A4; + mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL =$44A5; + mmDCP5_REGAMMA_CNTLA_END_CNTL1 =$44A6; + mmDCP5_REGAMMA_CNTLA_END_CNTL2 =$44A7; + mmDCP5_REGAMMA_CNTLA_REGION_0_1 =$44A8; + mmDCP5_REGAMMA_CNTLA_REGION_2_3 =$44A9; + mmDCP5_REGAMMA_CNTLA_REGION_4_5 =$44AA; + mmDCP5_REGAMMA_CNTLA_REGION_6_7 =$44AB; + mmDCP5_REGAMMA_CNTLA_REGION_8_9 =$44AC; + mmDCP5_REGAMMA_CNTLA_REGION_10_11 =$44AD; + mmDCP5_REGAMMA_CNTLA_REGION_12_13 =$44AE; + mmDCP5_REGAMMA_CNTLA_REGION_14_15 =$44AF; + mmDCP5_REGAMMA_CNTLB_START_CNTL =$44B0; + mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL =$44B1; + mmDCP5_REGAMMA_CNTLB_END_CNTL1 =$44B2; + mmDCP5_REGAMMA_CNTLB_END_CNTL2 =$44B3; + mmDCP5_REGAMMA_CNTLB_REGION_0_1 =$44B4; + mmDCP5_REGAMMA_CNTLB_REGION_2_3 =$44B5; + mmDCP5_REGAMMA_CNTLB_REGION_4_5 =$44B6; + mmDCP5_REGAMMA_CNTLB_REGION_6_7 =$44B7; + mmDCP5_REGAMMA_CNTLB_REGION_8_9 =$44B8; + mmDCP5_REGAMMA_CNTLB_REGION_10_11 =$44B9; + mmDCP5_REGAMMA_CNTLB_REGION_12_13 =$44BA; + mmDCP5_REGAMMA_CNTLB_REGION_14_15 =$44BB; + mmDCP5_ALPHA_CONTROL =$44BC; + mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS =$44BD; + mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH =$44BE; + mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS =$44BF; + mmLB5_LB_DATA_FORMAT =$44C0; + mmLB5_LB_MEMORY_CTRL =$44C1; + mmLB5_LB_MEMORY_SIZE_STATUS =$44C2; + mmLB5_LB_DESKTOP_HEIGHT =$44C3; + mmLB5_LB_VLINE_START_END =$44C4; + mmLB5_LB_VLINE2_START_END =$44C5; + mmLB5_LB_V_COUNTER =$44C6; + mmLB5_LB_SNAPSHOT_V_COUNTER =$44C7; + mmLB5_LB_INTERRUPT_MASK =$44C8; + mmLB5_LB_VLINE_STATUS =$44C9; + mmLB5_LB_VLINE2_STATUS =$44CA; + mmLB5_LB_VBLANK_STATUS =$44CB; + mmLB5_LB_SYNC_RESET_SEL =$44CC; + mmLB5_LB_BLACK_KEYER_R_CR =$44CD; + mmLB5_LB_BLACK_KEYER_G_Y =$44CE; + mmLB5_LB_BLACK_KEYER_B_CB =$44CF; + mmLB5_LB_KEYER_COLOR_CTRL =$44D0; + mmLB5_LB_KEYER_COLOR_R_CR =$44D1; + mmLB5_LB_KEYER_COLOR_G_Y =$44D2; + mmLB5_LB_KEYER_COLOR_B_CB =$44D3; + mmLB5_LB_KEYER_COLOR_REP_R_CR =$44D4; + mmLB5_LB_KEYER_COLOR_REP_G_Y =$44D5; + mmLB5_LB_KEYER_COLOR_REP_B_CB =$44D6; + mmLB5_LB_BUFFER_LEVEL_STATUS =$44D7; + mmLB5_LB_BUFFER_URGENCY_CTRL =$44D8; + mmLB5_LB_BUFFER_URGENCY_STATUS =$44D9; + mmLB5_LB_BUFFER_STATUS =$44DA; + mmLB5_LB_NO_OUTSTANDING_REQ_STATUS =$44DC; + mmLB5_MVP_AFR_FLIP_MODE =$44E0; + mmLB5_MVP_AFR_FLIP_FIFO_CNTL =$44E1; + mmLB5_MVP_FLIP_LINE_NUM_INSERT =$44E2; + mmLB5_DC_MVP_LB_CONTROL =$44E3; + mmLB5_LB_DEBUG =$44E4; + mmLB5_LB_DEBUG2 =$44E5; + mmLB5_LB_DEBUG3 =$44E6; + mmLB5_LB_TEST_DEBUG_INDEX =$44FE; + mmLB5_LB_TEST_DEBUG_DATA =$44FF; + mmDCFE5_DCFE_CLOCK_CONTROL =$4500; + mmDCFE5_DCFE_SOFT_RESET =$4501; + mmDCFE5_DCFE_DBG_CONFIG =$4502; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL =$4513; + mmDC_PERFMON8_PERFCOUNTER_CNTL =$4524; + mmDC_PERFMON8_PERFCOUNTER_STATE =$4525; + mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC =$4526; + mmDC_PERFMON8_PERFMON_CNTL =$4527; + mmDC_PERFMON8_PERFMON_CVALUE_LOW =$4528; + mmDC_PERFMON8_PERFMON_HI =$4529; + mmDC_PERFMON8_PERFMON_LOW =$452A; + mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX =$452B; + mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA =$452C; + mmDC_PERFMON8_PERFMON_CNTL2 =$452E; + mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 =$4530; + mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 =$4531; + mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL =$4532; + mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL =$4533; + mmDMIF_PG5_DPG_PIPE_DPM_CONTROL =$4534; + mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL =$4535; + mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL =$4536; + mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH =$4537; + mmDMIF_PG5_DPG_TEST_DEBUG_INDEX =$4538; + mmDMIF_PG5_DPG_TEST_DEBUG_DATA =$4539; + mmDMIF_PG5_DPG_REPEATER_PROGRAM =$453A; + mmDMIF_PG5_DPG_HW_DEBUG_A =$453B; + mmDMIF_PG5_DPG_HW_DEBUG_B =$453C; + mmDMIF_PG5_DPG_HW_DEBUG_11 =$453D; + mmSCL5_SCL_COEF_RAM_SELECT =$4540; + mmSCL5_SCL_COEF_RAM_TAP_DATA =$4541; + mmSCL5_SCL_MODE =$4542; + mmSCL5_SCL_TAP_CONTROL =$4543; + mmSCL5_SCL_CONTROL =$4544; + mmSCL5_SCL_BYPASS_CONTROL =$4545; + mmSCL5_SCL_MANUAL_REPLICATE_CONTROL =$4546; + mmSCL5_SCL_AUTOMATIC_MODE_CONTROL =$4547; + mmSCL5_SCL_HORZ_FILTER_CONTROL =$4548; + mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO =$4549; + mmSCL5_SCL_HORZ_FILTER_INIT =$454A; + mmSCL5_SCL_VERT_FILTER_CONTROL =$454B; + mmSCL5_SCL_VERT_FILTER_SCALE_RATIO =$454C; + mmSCL5_SCL_VERT_FILTER_INIT =$454D; + mmSCL5_SCL_VERT_FILTER_INIT_BOT =$454E; + mmSCL5_SCL_ROUND_OFFSET =$454F; + mmSCL5_SCL_UPDATE =$4551; + mmSCL5_SCL_F_SHARP_CONTROL =$4553; + mmSCL5_SCL_ALU_CONTROL =$4554; + mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS =$4555; + mmSCL5_VIEWPORT_START_SECONDARY =$455B; + mmSCL5_VIEWPORT_START =$455C; + mmSCL5_VIEWPORT_SIZE =$455D; + mmSCL5_EXT_OVERSCAN_LEFT_RIGHT =$455E; + mmSCL5_EXT_OVERSCAN_TOP_BOTTOM =$455F; + mmSCL5_SCL_MODE_CHANGE_DET1 =$4560; + mmSCL5_SCL_MODE_CHANGE_DET2 =$4561; + mmSCL5_SCL_MODE_CHANGE_DET3 =$4562; + mmSCL5_SCL_MODE_CHANGE_MASK =$4563; + mmSCL5_SCL_DEBUG2 =$4569; + mmSCL5_SCL_DEBUG =$456A; + mmSCL5_SCL_TEST_DEBUG_INDEX =$456B; + mmSCL5_SCL_TEST_DEBUG_DATA =$456C; + mmBLND5_BLND_CONTROL =$456D; + mmBLND5_SM_CONTROL2 =$456E; + mmBLND5_BLND_CONTROL2 =$456F; + mmBLND5_BLND_UPDATE =$4570; + mmBLND5_BLND_UNDERFLOW_INTERRUPT =$4571; + mmBLND5_BLND_V_UPDATE_LOCK =$4573; + mmBLND5_BLND_DEBUG =$4574; + mmBLND5_BLND_TEST_DEBUG_INDEX =$4575; + mmBLND5_BLND_TEST_DEBUG_DATA =$4576; + mmBLND5_BLND_REG_UPDATE_STATUS =$4577; + mmCRTC5_CRTC_3D_STRUCTURE_CONTROL =$4578; + mmCRTC5_CRTC_GSL_VSYNC_GAP =$4579; + mmCRTC5_CRTC_GSL_WINDOW =$457A; + mmCRTC5_CRTC_GSL_CONTROL =$457B; + mmCRTC5_CRTC_DCFE_CLOCK_CONTROL =$457C; + mmCRTC5_CRTC_H_BLANK_EARLY_NUM =$457D; + mmCRTC5_DCFE_DBG_SEL =$457E; + mmCRTC5_DCFE_MEM_PWR_CTRL =$457F; + mmCRTC5_CRTC_H_SYNC_B_CNTL =$4585; + mmCRTC5_CRTC_V_TOTAL_MIN =$4588; + mmCRTC5_CRTC_V_TOTAL_MAX =$4589; + mmCRTC5_CRTC_V_TOTAL_CONTROL =$458A; + mmCRTC5_CRTC_V_TOTAL_INT_STATUS =$458B; + mmCRTC5_CRTC_V_BLANK_START_END =$458D; + mmCRTC5_CRTC_V_SYNC_A =$458E; + mmCRTC5_CRTC_V_SYNC_A_CNTL =$458F; + mmCRTC5_CRTC_V_SYNC_B =$4590; + mmCRTC5_CRTC_V_SYNC_B_CNTL =$4591; + mmCRTC5_CRTC_DTMTEST_CNTL =$4592; + mmCRTC5_CRTC_DTMTEST_STATUS_POSITION =$4593; + mmCRTC5_CRTC_TRIGA_CNTL =$4594; + mmCRTC5_CRTC_TRIGA_MANUAL_TRIG =$4595; + mmCRTC5_CRTC_TRIGB_CNTL =$4596; + mmCRTC5_CRTC_TRIGB_MANUAL_TRIG =$4597; + mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL =$4598; + mmCRTC5_CRTC_FLOW_CONTROL =$4599; + mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE =$459A; + mmCRTC5_CRTC_AVSYNC_COUNTER =$459B; + mmCRTC5_CRTC_CONTROL =$459C; + mmCRTC5_CRTC_BLANK_CONTROL =$459D; + mmCRTC5_CRTC_INTERLACE_CONTROL =$459E; + mmCRTC5_CRTC_INTERLACE_STATUS =$459F; + mmCRTC5_CRTC_FIELD_INDICATION_CONTROL =$45A0; + mmCRTC5_CRTC_PIXEL_DATA_READBACK0 =$45A1; + mmCRTC5_CRTC_PIXEL_DATA_READBACK1 =$45A2; + mmCRTC5_CRTC_STATUS =$45A3; + mmCRTC5_CRTC_STATUS_POSITION =$45A4; + mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE =$45AB; + mmCRTC5_CRTC_VERT_SYNC_CONTROL =$45AC; + mmCRTC5_CRTC_STEREO_STATUS =$45AD; + mmCRTC5_CRTC_STEREO_CONTROL =$45AE; + mmCRTC5_CRTC_SNAPSHOT_STATUS =$45AF; + mmCRTC5_CRTC_SNAPSHOT_CONTROL =$45B0; + mmCRTC5_CRTC_SNAPSHOT_POSITION =$45B1; + mmCRTC5_CRTC_SNAPSHOT_FRAME =$45B2; + mmCRTC5_CRTC_START_LINE_CONTROL =$45B3; + mmCRTC5_CRTC_INTERRUPT_CONTROL =$45B4; + mmCRTC5_CRTC_UPDATE_LOCK =$45B5; + mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL =$45B6; + mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE =$45B7; + mmCRTC5_DCFE_MEM_PWR_CTRL2 =$45B8; + mmCRTC5_DCFE_MEM_PWR_STATUS =$45B9; + mmCRTC5_CRTC_TEST_PATTERN_CONTROL =$45BA; + mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS =$45BB; + mmCRTC5_CRTC_TEST_PATTERN_COLOR =$45BC; + mmCRTC5_MASTER_UPDATE_LOCK =$45BD; + mmCRTC5_MASTER_UPDATE_MODE =$45BE; + mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT =$45BF; + mmCRTC5_CRTC_TEST_DEBUG_INDEX =$45C6; + mmCRTC5_CRTC_TEST_DEBUG_DATA =$45C7; + mmCRTC5_CRTC_OVERSCAN_COLOR =$45C8; + mmCRTC5_CRTC_OVERSCAN_COLOR_EXT =$45C9; + mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT =$45CB; + mmCRTC5_CRTC_BLACK_COLOR =$45CC; + mmCRTC5_CRTC_BLACK_COLOR_EXT =$45CD; + mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION =$45CE; + mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL =$45CF; + mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION =$45D0; + mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL =$45D1; + mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION =$45D2; + mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL =$45D3; + mmCRTC5_CRTC_CRC_CNTL =$45D4; + mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL =$45D5; + mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL =$45D6; + mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL =$45D7; + mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL =$45D8; + mmCRTC5_CRTC_CRC0_DATA_RG =$45D9; + mmCRTC5_CRTC_CRC0_DATA_B =$45DA; + mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL =$45DB; + mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL =$45DC; + mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL =$45DD; + mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL =$45DE; + mmCRTC5_CRTC_CRC1_DATA_RG =$45DF; + mmCRTC5_CRTC_CRC1_DATA_B =$45E0; + mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL =$45E1; + mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START =$45E2; + mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END =$45E3; + mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL =$45E4; + mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL =$45E5; + mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL =$45E6; + mmCRTC5_CRTC_STATIC_SCREEN_CONTROL =$45E7; + mmFMT5_FMT_CLAMP_COMPONENT_R =$45E8; + mmFMT5_FMT_CLAMP_COMPONENT_G =$45E9; + mmFMT5_FMT_CLAMP_COMPONENT_B =$45EA; + mmFMT5_FMT_TEST_DEBUG_INDEX =$45EB; + mmFMT5_FMT_TEST_DEBUG_DATA =$45EC; + mmFMT5_FMT_DYNAMIC_EXP_CNTL =$45ED; + mmFMT5_FMT_CONTROL =$45EE; + mmFMT5_FMT_FORCE_OUTPUT_CNTL =$45EF; + mmFMT5_FMT_FORCE_DATA_0_1 =$45F0; + mmFMT5_FMT_FORCE_DATA_2_3 =$45F1; + mmFMT5_FMT_BIT_DEPTH_CONTROL =$45F2; + mmFMT5_FMT_DITHER_RAND_R_SEED =$45F3; + mmFMT5_FMT_DITHER_RAND_G_SEED =$45F4; + mmFMT5_FMT_DITHER_RAND_B_SEED =$45F5; + mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL =$45F6; + mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX =$45F7; + mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX =$45F8; + mmFMT5_FMT_CLAMP_CNTL =$45F9; + mmFMT5_FMT_CRC_CNTL =$45FA; + mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK =$45FB; + mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK =$45FC; + mmFMT5_FMT_CRC_SIG_RED_GREEN =$45FD; + mmFMT5_FMT_CRC_SIG_BLUE_CONTROL =$45FE; + mmFMT5_FMT_DEBUG_CNTL =$45FF; + mmUNP_GRPH_ENABLE =$4600; + mmUNP_GRPH_CONTROL =$4601; + mmUNP_GRPH_CONTROL_EXP =$4603; + mmUNP_GRPH_SWAP_CNTL =$4605; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L =$4606; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C =$4607; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L =$4608; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C =$4609; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L =$460A; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C =$460B; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L =$460C; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C =$460D; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L =$460E; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C =$460F; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L =$4610; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C =$4611; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L =$4612; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C =$4613; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L =$4614; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C =$4615; + mmUNP_GRPH_PITCH_L =$4616; + mmUNP_GRPH_PITCH_C =$4617; + mmUNP_GRPH_SURFACE_OFFSET_X_L =$4618; + mmUNP_GRPH_SURFACE_OFFSET_X_C =$4619; + mmUNP_GRPH_SURFACE_OFFSET_Y_L =$461A; + mmUNP_GRPH_SURFACE_OFFSET_Y_C =$461B; + mmUNP_GRPH_X_START_L =$461C; + mmUNP_GRPH_X_START_C =$461D; + mmUNP_GRPH_Y_START_L =$461E; + mmUNP_GRPH_Y_START_C =$461F; + mmUNP_GRPH_X_END_L =$4620; + mmUNP_GRPH_X_END_C =$4621; + mmUNP_GRPH_Y_END_L =$4622; + mmUNP_GRPH_Y_END_C =$4623; + mmUNP_GRPH_UPDATE =$4624; + mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L =$4625; + mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C =$4626; + mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L =$4627; + mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C =$4628; + mmUNP_GRPH_DFQ_CONTROL =$4629; + mmUNP_GRPH_DFQ_STATUS =$462A; + mmUNP_GRPH_INTERRUPT_STATUS =$462B; + mmUNP_GRPH_INTERRUPT_CONTROL =$462C; + mmUNP_GRPH_STEREOSYNC_FLIP =$462E; + mmUNP_GRPH_FLIP_RATE_CNTL =$462F; + mmUNP_CRC_CONTROL =$4630; + mmUNP_CRC_MASK =$4631; + mmUNP_CRC_CURRENT =$4632; + mmUNP_CRC_LAST =$4633; + mmUNP_LB_DATA_GAP_BETWEEN_CHUNK =$4634; + mmUNP_HW_ROTATION =$4635; + mmUNP_DEBUG =$4636; + mmUNP_DEBUG2 =$4637; + mmUNP_TEST_DEBUG_INDEX =$4638; + mmUNP_TEST_DEBUG_DATA =$4639; + mmLBV_DATA_FORMAT =$463C; + mmLBV_MEMORY_CTRL =$463D; + mmLBV_MEMORY_SIZE_STATUS =$463E; + mmLBV_DESKTOP_HEIGHT =$463F; + mmLBV_VLINE_START_END =$4640; + mmLBV_VLINE2_START_END =$4641; + mmLBV_V_COUNTER =$4642; + mmLBV_SNAPSHOT_V_COUNTER =$4643; + mmLBV_V_COUNTER_CHROMA =$4644; + mmLBV_SNAPSHOT_V_COUNTER_CHROMA =$4645; + mmLBV_INTERRUPT_MASK =$4646; + mmLBV_VLINE_STATUS =$4647; + mmLBV_VLINE2_STATUS =$4648; + mmLBV_VBLANK_STATUS =$4649; + mmLBV_SYNC_RESET_SEL =$464A; + mmLBV_BLACK_KEYER_R_CR =$464B; + mmLBV_BLACK_KEYER_G_Y =$464C; + mmLBV_BLACK_KEYER_B_CB =$464D; + mmLBV_KEYER_COLOR_CTRL =$464E; + mmLBV_KEYER_COLOR_R_CR =$464F; + mmLBV_KEYER_COLOR_G_Y =$4650; + mmLBV_KEYER_COLOR_B_CB =$4651; + mmLBV_KEYER_COLOR_REP_R_CR =$4652; + mmLBV_KEYER_COLOR_REP_G_Y =$4653; + mmLBV_KEYER_COLOR_REP_B_CB =$4654; + mmLBV_BUFFER_LEVEL_STATUS =$4655; + mmLBV_BUFFER_URGENCY_CTRL =$4656; + mmLBV_BUFFER_URGENCY_STATUS =$4657; + mmLBV_BUFFER_STATUS =$4658; + mmLBV_NO_OUTSTANDING_REQ_STATUS =$4659; + mmLBV_DEBUG =$465A; + mmLBV_DEBUG2 =$465B; + mmLBV_DEBUG3 =$465C; + mmLBV_TEST_DEBUG_INDEX =$4666; + mmLBV_TEST_DEBUG_DATA =$4667; + mmSCLV_COEF_RAM_SELECT =$4670; + mmSCLV_COEF_RAM_TAP_DATA =$4671; + mmSCLV_MODE =$4672; + mmSCLV_TAP_CONTROL =$4673; + mmSCLV_CONTROL =$4674; + mmSCLV_MANUAL_REPLICATE_CONTROL =$4675; + mmSCLV_AUTOMATIC_MODE_CONTROL =$4676; + mmSCLV_HORZ_FILTER_CONTROL =$4677; + mmSCLV_HORZ_FILTER_SCALE_RATIO =$4678; + mmSCLV_HORZ_FILTER_INIT =$4679; + mmSCLV_HORZ_FILTER_SCALE_RATIO_C =$467A; + mmSCLV_HORZ_FILTER_INIT_C =$467B; + mmSCLV_VERT_FILTER_CONTROL =$467C; + mmSCLV_VERT_FILTER_SCALE_RATIO =$467D; + mmSCLV_VERT_FILTER_INIT =$467E; + mmSCLV_VERT_FILTER_INIT_BOT =$467F; + mmSCLV_VERT_FILTER_SCALE_RATIO_C =$4680; + mmSCLV_VERT_FILTER_INIT_C =$4681; + mmSCLV_VERT_FILTER_INIT_BOT_C =$4682; + mmSCLV_ROUND_OFFSET =$4683; + mmSCLV_UPDATE =$4684; + mmSCLV_ALU_CONTROL =$4685; + mmSCLV_VIEWPORT_START =$4686; + mmSCLV_VIEWPORT_START_SECONDARY =$4687; + mmSCLV_VIEWPORT_SIZE =$4688; + mmSCLV_VIEWPORT_START_C =$4689; + mmSCLV_VIEWPORT_START_SECONDARY_C =$468A; + mmSCLV_VIEWPORT_SIZE_C =$468B; + mmSCLV_EXT_OVERSCAN_LEFT_RIGHT =$468C; + mmSCLV_EXT_OVERSCAN_TOP_BOTTOM =$468D; + mmSCLV_MODE_CHANGE_DET1 =$468E; + mmSCLV_MODE_CHANGE_DET2 =$468F; + mmSCLV_MODE_CHANGE_DET3 =$4690; + mmSCLV_MODE_CHANGE_MASK =$4691; + mmSCLV_DEBUG2 =$4692; + mmSCLV_DEBUG =$4693; + mmSCLV_TEST_DEBUG_INDEX =$4694; + mmSCLV_TEST_DEBUG_DATA =$4695; + mmCOL_MAN_UPDATE =$46A4; + mmCOL_MAN_INPUT_CSC_CONTROL =$46A5; + mmINPUT_CSC_C11_C12_A =$46A6; + mmINPUT_CSC_C13_C14_A =$46A7; + mmINPUT_CSC_C21_C22_A =$46A8; + mmINPUT_CSC_C23_C24_A =$46A9; + mmINPUT_CSC_C31_C32_A =$46AA; + mmINPUT_CSC_C33_C34_A =$46AB; + mmINPUT_CSC_C11_C12_B =$46AC; + mmINPUT_CSC_C13_C14_B =$46AD; + mmINPUT_CSC_C21_C22_B =$46AE; + mmINPUT_CSC_C23_C24_B =$46AF; + mmINPUT_CSC_C31_C32_B =$46B0; + mmINPUT_CSC_C33_C34_B =$46B1; + mmPRESCALE_CONTROL =$46B2; + mmPRESCALE_VALUES_R =$46B3; + mmPRESCALE_VALUES_G =$46B4; + mmPRESCALE_VALUES_B =$46B5; + mmCOL_MAN_OUTPUT_CSC_CONTROL =$46B6; + mmOUTPUT_CSC_C11_C12_A =$46B7; + mmOUTPUT_CSC_C13_C14_A =$46B8; + mmOUTPUT_CSC_C21_C22_A =$46B9; + mmOUTPUT_CSC_C23_C24_A =$46BA; + mmOUTPUT_CSC_C31_C32_A =$46BB; + mmOUTPUT_CSC_C33_C34_A =$46BC; + mmOUTPUT_CSC_C11_C12_B =$46BD; + mmOUTPUT_CSC_C13_C14_B =$46BE; + mmOUTPUT_CSC_C21_C22_B =$46BF; + mmOUTPUT_CSC_C23_C24_B =$46C0; + mmOUTPUT_CSC_C31_C32_B =$46C1; + mmOUTPUT_CSC_C33_C34_B =$46C2; + mmDENORM_CLAMP_CONTROL =$46C3; + mmDENORM_CLAMP_RANGE_R_CR =$46C4; + mmDENORM_CLAMP_RANGE_G_Y =$46C5; + mmDENORM_CLAMP_RANGE_B_CB =$46C6; + mmCOL_MAN_FP_CONVERTED_FIELD =$46C7; + mmGAMMA_CORR_CONTROL =$46C8; + mmGAMMA_CORR_LUT_INDEX =$46C9; + mmGAMMA_CORR_LUT_DATA =$46CA; + mmGAMMA_CORR_LUT_WRITE_EN_MASK =$46CB; + mmGAMMA_CORR_CNTLA_START_CNTL =$46CC; + mmGAMMA_CORR_CNTLA_SLOPE_CNTL =$46CD; + mmGAMMA_CORR_CNTLA_END_CNTL1 =$46CE; + mmGAMMA_CORR_CNTLA_END_CNTL2 =$46CF; + mmGAMMA_CORR_CNTLA_REGION_0_1 =$46D0; + mmGAMMA_CORR_CNTLA_REGION_2_3 =$46D1; + mmGAMMA_CORR_CNTLA_REGION_4_5 =$46D2; + mmGAMMA_CORR_CNTLA_REGION_6_7 =$46D3; + mmGAMMA_CORR_CNTLA_REGION_8_9 =$46D4; + mmGAMMA_CORR_CNTLA_REGION_10_11 =$46D5; + mmGAMMA_CORR_CNTLA_REGION_12_13 =$46D6; + mmGAMMA_CORR_CNTLA_REGION_14_15 =$46D7; + mmGAMMA_CORR_CNTLB_START_CNTL =$46D8; + mmGAMMA_CORR_CNTLB_SLOPE_CNTL =$46D9; + mmGAMMA_CORR_CNTLB_END_CNTL1 =$46DA; + mmGAMMA_CORR_CNTLB_END_CNTL2 =$46DB; + mmGAMMA_CORR_CNTLB_REGION_0_1 =$46DC; + mmGAMMA_CORR_CNTLB_REGION_2_3 =$46DD; + mmGAMMA_CORR_CNTLB_REGION_4_5 =$46DE; + mmGAMMA_CORR_CNTLB_REGION_6_7 =$46DF; + mmGAMMA_CORR_CNTLB_REGION_8_9 =$46E0; + mmGAMMA_CORR_CNTLB_REGION_10_11 =$46E1; + mmGAMMA_CORR_CNTLB_REGION_12_13 =$46E2; + mmGAMMA_CORR_CNTLB_REGION_14_15 =$46E3; + mmCOL_MAN_TEST_DEBUG_INDEX =$46E4; + mmCOL_MAN_TEST_DEBUG_DATA =$46E5; + mmCOL_MAN_DEBUG_CONTROL =$46E6; + mmDCFEV_CLOCK_CONTROL =$46F4; + mmDCFEV_SOFT_RESET =$46F5; + mmDCFEV_DMIFV_CLOCK_CONTROL =$46F6; + mmDCFEV_DBG_CONFIG =$46F7; + mmDCFEV_DMIFV_MEM_PWR_CTRL =$46F8; + mmDCFEV_DMIFV_MEM_PWR_STATUS =$46F9; + mmDC_PERFMON11_PERFCOUNTER_CNTL =$4724; + mmDC_PERFMON11_PERFCOUNTER_STATE =$4725; + mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC =$4726; + mmDC_PERFMON11_PERFMON_CNTL =$4727; + mmDC_PERFMON11_PERFMON_CVALUE_LOW =$4728; + mmDC_PERFMON11_PERFMON_HI =$4729; + mmDC_PERFMON11_PERFMON_LOW =$472A; + mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX =$472B; + mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA =$472C; + mmDC_PERFMON11_PERFMON_CNTL2 =$472E; + mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 =$4730; + mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 =$4731; + mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL =$4732; + mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL =$4733; + mmDMIF_PG6_DPG_PIPE_DPM_CONTROL =$4734; + mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL =$4735; + mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL =$4736; + mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH =$4737; + mmDMIF_PG6_DPG_TEST_DEBUG_INDEX =$4738; + mmDMIF_PG6_DPG_TEST_DEBUG_DATA =$4739; + mmDMIF_PG6_DPG_REPEATER_PROGRAM =$473A; + mmDMIF_PG6_DPG_HW_DEBUG_A =$473B; + mmDMIF_PG6_DPG_HW_DEBUG_B =$473C; + mmDMIF_PG6_DPG_HW_DEBUG_11 =$473D; + mmBLND6_BLND_CONTROL =$476D; + mmBLND6_SM_CONTROL2 =$476E; + mmBLND6_BLND_CONTROL2 =$476F; + mmBLND6_BLND_UPDATE =$4770; + mmBLND6_BLND_UNDERFLOW_INTERRUPT =$4771; + mmBLND6_BLND_V_UPDATE_LOCK =$4773; + mmBLND6_BLND_DEBUG =$4774; + mmBLND6_BLND_TEST_DEBUG_INDEX =$4775; + mmBLND6_BLND_TEST_DEBUG_DATA =$4776; + mmBLND6_BLND_REG_UPDATE_STATUS =$4777; + mmCRTC6_CRTC_3D_STRUCTURE_CONTROL =$4778; + mmCRTC6_CRTC_GSL_VSYNC_GAP =$4779; + mmCRTC6_CRTC_GSL_WINDOW =$477A; + mmCRTC6_CRTC_GSL_CONTROL =$477B; + mmCRTC6_CRTC_DCFE_CLOCK_CONTROL =$477C; + mmCRTC6_CRTC_H_BLANK_EARLY_NUM =$477D; + mmCRTC6_DCFE_DBG_SEL =$477E; + mmCRTC6_DCFE_MEM_PWR_CTRL =$477F; + mmCRTC6_CRTC_H_TOTAL =$4780; + mmCRTC6_CRTC_H_BLANK_START_END =$4781; + mmCRTC6_CRTC_H_SYNC_A =$4782; + mmCRTC6_CRTC_H_SYNC_A_CNTL =$4783; + mmCRTC6_CRTC_H_SYNC_B =$4784; + mmCRTC6_CRTC_H_SYNC_B_CNTL =$4785; + mmCRTC6_CRTC_VBI_END =$4786; + mmCRTC6_CRTC_V_TOTAL =$4787; + mmCRTC6_CRTC_V_TOTAL_MIN =$4788; + mmCRTC6_CRTC_V_TOTAL_MAX =$4789; + mmCRTC6_CRTC_V_TOTAL_CONTROL =$478A; + mmCRTC6_CRTC_V_TOTAL_INT_STATUS =$478B; + mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS =$478C; + mmCRTC6_CRTC_V_BLANK_START_END =$478D; + mmCRTC6_CRTC_V_SYNC_A =$478E; + mmCRTC6_CRTC_V_SYNC_A_CNTL =$478F; + mmCRTC6_CRTC_V_SYNC_B =$4790; + mmCRTC6_CRTC_V_SYNC_B_CNTL =$4791; + mmCRTC6_CRTC_DTMTEST_CNTL =$4792; + mmCRTC6_CRTC_DTMTEST_STATUS_POSITION =$4793; + mmCRTC6_CRTC_TRIGA_CNTL =$4794; + mmCRTC6_CRTC_TRIGA_MANUAL_TRIG =$4795; + mmCRTC6_CRTC_TRIGB_CNTL =$4796; + mmCRTC6_CRTC_TRIGB_MANUAL_TRIG =$4797; + mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL =$4798; + mmCRTC6_CRTC_FLOW_CONTROL =$4799; + mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE =$479A; + mmCRTC6_CRTC_AVSYNC_COUNTER =$479B; + mmCRTC6_CRTC_CONTROL =$479C; + mmCRTC6_CRTC_BLANK_CONTROL =$479D; + mmCRTC6_CRTC_INTERLACE_CONTROL =$479E; + mmCRTC6_CRTC_INTERLACE_STATUS =$479F; + mmCRTC6_CRTC_FIELD_INDICATION_CONTROL =$47A0; + mmCRTC6_CRTC_PIXEL_DATA_READBACK0 =$47A1; + mmCRTC6_CRTC_PIXEL_DATA_READBACK1 =$47A2; + mmCRTC6_CRTC_STATUS =$47A3; + mmCRTC6_CRTC_STATUS_POSITION =$47A4; + mmCRTC6_CRTC_NOM_VERT_POSITION =$47A5; + mmCRTC6_CRTC_STATUS_FRAME_COUNT =$47A6; + mmCRTC6_CRTC_STATUS_VF_COUNT =$47A7; + mmCRTC6_CRTC_STATUS_HV_COUNT =$47A8; + mmCRTC6_CRTC_COUNT_CONTROL =$47A9; + mmCRTC6_CRTC_COUNT_RESET =$47AA; + mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE =$47AB; + mmCRTC6_CRTC_VERT_SYNC_CONTROL =$47AC; + mmCRTC6_CRTC_STEREO_STATUS =$47AD; + mmCRTC6_CRTC_STEREO_CONTROL =$47AE; + mmCRTC6_CRTC_SNAPSHOT_STATUS =$47AF; + mmCRTC6_CRTC_SNAPSHOT_CONTROL =$47B0; + mmCRTC6_CRTC_SNAPSHOT_POSITION =$47B1; + mmCRTC6_CRTC_SNAPSHOT_FRAME =$47B2; + mmCRTC6_CRTC_START_LINE_CONTROL =$47B3; + mmCRTC6_CRTC_INTERRUPT_CONTROL =$47B4; + mmCRTC6_CRTC_UPDATE_LOCK =$47B5; + mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL =$47B6; + mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE =$47B7; + mmCRTC6_DCFE_MEM_PWR_CTRL2 =$47B8; + mmCRTC6_DCFE_MEM_PWR_STATUS =$47B9; + mmCRTC6_CRTC_TEST_PATTERN_CONTROL =$47BA; + mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS =$47BB; + mmCRTC6_CRTC_TEST_PATTERN_COLOR =$47BC; + mmCRTC6_MASTER_UPDATE_LOCK =$47BD; + mmCRTC6_MASTER_UPDATE_MODE =$47BE; + mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT =$47BF; + mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER =$47C0; + mmCRTC6_CRTC_MVP_STATUS =$47C1; + mmCRTC6_CRTC_MASTER_EN =$47C2; + mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT =$47C3; + mmCRTC6_CRTC_V_UPDATE_INT_STATUS =$47C4; + mmCRTC6_CRTC_TEST_DEBUG_INDEX =$47C6; + mmCRTC6_CRTC_TEST_DEBUG_DATA =$47C7; + mmCRTC6_CRTC_OVERSCAN_COLOR =$47C8; + mmCRTC6_CRTC_OVERSCAN_COLOR_EXT =$47C9; + mmCRTC6_CRTC_BLANK_DATA_COLOR =$47CA; + mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT =$47CB; + mmCRTC6_CRTC_BLACK_COLOR =$47CC; + mmCRTC6_CRTC_BLACK_COLOR_EXT =$47CD; + mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION =$47CE; + mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL =$47CF; + mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION =$47D0; + mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL =$47D1; + mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION =$47D2; + mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL =$47D3; + mmCRTC6_CRTC_CRC_CNTL =$47D4; + mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL =$47D5; + mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL =$47D6; + mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL =$47D7; + mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL =$47D8; + mmCRTC6_CRTC_CRC0_DATA_RG =$47D9; + mmCRTC6_CRTC_CRC0_DATA_B =$47DA; + mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL =$47DB; + mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL =$47DC; + mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL =$47DD; + mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL =$47DE; + mmCRTC6_CRTC_CRC1_DATA_RG =$47DF; + mmCRTC6_CRTC_CRC1_DATA_B =$47E0; + mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL =$47E1; + mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START =$47E2; + mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END =$47E3; + mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL =$47E4; + mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL =$47E5; + mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL =$47E6; + mmCRTC6_CRTC_STATIC_SCREEN_CONTROL =$47E7; + mmDC_GENERICA =$4800; + mmDC_GENERICB =$4801; + mmDC_PAD_EXTERN_SIG =$4802; + mmDC_REF_CLK_CNTL =$4803; + mmDC_GPIO_DEBUG =$4804; + mmUNIPHYA_LINK_CNTL =$4805; + mmUNIPHYA_CHANNEL_XBAR_CNTL =$4806; + mmUNIPHYB_LINK_CNTL =$4807; + mmUNIPHYB_CHANNEL_XBAR_CNTL =$4808; + mmUNIPHYC_LINK_CNTL =$4809; + mmUNIPHYC_CHANNEL_XBAR_CNTL =$480A; + mmUNIPHYD_LINK_CNTL =$480B; + mmUNIPHYD_CHANNEL_XBAR_CNTL =$480C; + mmUNIPHYE_LINK_CNTL =$480D; + mmUNIPHYE_CHANNEL_XBAR_CNTL =$480E; + mmUNIPHYF_LINK_CNTL =$480F; + mmUNIPHYF_CHANNEL_XBAR_CNTL =$4810; + mmUNIPHYG_LINK_CNTL =$4811; + mmUNIPHYG_CHANNEL_XBAR_CNTL =$4812; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL =$4813; + mmDCIO_WRCMD_DELAY =$4816; + mmDC_PINSTRAPS =$4818; + mmDC_DVODATA_CONFIG =$481A; + mmLVTMA_PWRSEQ_CNTL =$481B; + mmLVTMA_PWRSEQ_STATE =$481C; + mmLVTMA_PWRSEQ_REF_DIV =$481D; + mmLVTMA_PWRSEQ_DELAY1 =$481E; + mmLVTMA_PWRSEQ_DELAY2 =$481F; + mmBL_PWM_CNTL =$4820; + mmBL_PWM_CNTL2 =$4821; + mmBL_PWM_PERIOD_CNTL =$4822; + mmBL_PWM_GRP1_REG_LOCK =$4823; + mmDCIO_GSL_GENLK_PAD_CNTL =$4824; + mmDCIO_GSL_SWAPLOCK_PAD_CNTL =$4825; + mmDCIO_GSL0_CNTL =$4826; + mmDCIO_GSL1_CNTL =$4827; + mmDCIO_GSL2_CNTL =$4828; + mmDC_GPU_TIMER_START_POSITION_V_UPDATE =$4829; + mmDC_GPU_TIMER_START_POSITION_P_FLIP =$482A; + mmDC_GPU_TIMER_READ =$482B; + mmDC_GPU_TIMER_READ_CNTL =$482C; + mmDCIO_CLOCK_CNTL =$482D; + mmDCIO_DEBUG =$482F; + mmDCO_DCFE_EXT_VSYNC_CNTL =$4830; + mmDCIO_TEST_DEBUG_INDEX =$4831; + mmDCIO_TEST_DEBUG_DATA =$4832; + mmDBG_OUT_CNTL =$4834; + mmDCIO_DEBUG_CONFIG =$4835; + mmDCIO_SOFT_RESET =$4836; + mmDCIO_DPHY_SEL =$4837; + mmUNIPHY_IMPCAL_LINKA =$4838; + mmUNIPHY_IMPCAL_LINKB =$4839; + mmUNIPHY_IMPCAL_PERIOD =$483A; + mmAUXP_IMPCAL =$483B; + mmAUXN_IMPCAL =$483C; + mmDCIO_IMPCAL_CNTL =$483D; + mmUNIPHY_IMPCAL_PSW_AB =$483E; + mmUNIPHY_IMPCAL_LINKC =$483F; + mmUNIPHY_IMPCAL_LINKD =$4840; + mmDCIO_IMPCAL_CNTL_CD =$4841; + mmUNIPHY_IMPCAL_PSW_CD =$4842; + mmUNIPHY_IMPCAL_LINKE =$4843; + mmUNIPHY_IMPCAL_LINKF =$4844; + mmDCIO_IMPCAL_CNTL_EF =$4845; + mmUNIPHY_IMPCAL_PSW_EF =$4846; + mmDC_GPIO_GENERIC_MASK =$4860; + mmDC_GPIO_GENERIC_A =$4861; + mmDC_GPIO_GENERIC_EN =$4862; + mmDC_GPIO_GENERIC_Y =$4863; + mmDC_GPIO_DVODATA_MASK =$4864; + mmDC_GPIO_DVODATA_A =$4865; + mmDC_GPIO_DVODATA_EN =$4866; + mmDC_GPIO_DVODATA_Y =$4867; + mmDC_GPIO_DDC1_MASK =$4868; + mmDC_GPIO_DDC1_A =$4869; + mmDC_GPIO_DDC1_EN =$486A; + mmDC_GPIO_DDC1_Y =$486B; + mmDC_GPIO_DDC2_MASK =$486C; + mmDC_GPIO_DDC2_A =$486D; + mmDC_GPIO_DDC2_EN =$486E; + mmDC_GPIO_DDC2_Y =$486F; + mmDC_GPIO_DDC3_MASK =$4870; + mmDC_GPIO_DDC3_A =$4871; + mmDC_GPIO_DDC3_EN =$4872; + mmDC_GPIO_DDC3_Y =$4873; + mmDC_GPIO_DDC4_MASK =$4874; + mmDC_GPIO_DDC4_A =$4875; + mmDC_GPIO_DDC4_EN =$4876; + mmDC_GPIO_DDC4_Y =$4877; + mmDC_GPIO_DDC5_MASK =$4878; + mmDC_GPIO_DDC5_A =$4879; + mmDC_GPIO_DDC5_EN =$487A; + mmDC_GPIO_DDC5_Y =$487B; + mmDC_GPIO_DDC6_MASK =$487C; + mmDC_GPIO_DDC6_A =$487D; + mmDC_GPIO_DDC6_EN =$487E; + mmDC_GPIO_DDC6_Y =$487F; + mmDC_GPIO_DDCVGA_MASK =$4880; + mmDC_GPIO_DDCVGA_A =$4881; + mmDC_GPIO_DDCVGA_EN =$4882; + mmDC_GPIO_DDCVGA_Y =$4883; + mmDC_GPIO_SYNCA_MASK =$4884; + mmDC_GPIO_SYNCA_A =$4885; + mmDC_GPIO_SYNCA_EN =$4886; + mmDC_GPIO_SYNCA_Y =$4887; + mmDC_GPIO_GENLK_MASK =$4888; + mmDC_GPIO_GENLK_A =$4889; + mmDC_GPIO_GENLK_EN =$488A; + mmDC_GPIO_GENLK_Y =$488B; + mmDC_GPIO_HPD_MASK =$488C; + mmDC_GPIO_HPD_A =$488D; + mmDC_GPIO_HPD_EN =$488E; + mmDC_GPIO_HPD_Y =$488F; + mmDC_GPIO_PWRSEQ_MASK =$4890; + mmDC_GPIO_PWRSEQ_A =$4891; + mmDC_GPIO_PWRSEQ_EN =$4892; + mmDC_GPIO_PWRSEQ_Y =$4893; + mmDC_GPIO_PAD_STRENGTH_1 =$4894; + mmDC_GPIO_PAD_STRENGTH_2 =$4895; + mmPHY_AUX_CNTL =$4897; + mmDC_GPIO_I2CPAD_MASK =$4898; + mmDC_GPIO_I2CPAD_A =$4899; + mmDC_GPIO_I2CPAD_EN =$489A; + mmDC_GPIO_I2CPAD_Y =$489B; + mmDC_GPIO_I2CPAD_STRENGTH =$489C; + mmDVO_STRENGTH_CONTROL =$489D; + mmDVO_VREF_CONTROL =$489E; + mmDVO_SKEW_ADJUST =$489F; + mmDAC_MACRO_CNTL_RESERVED0 =$48B8; + mmBPHYC_DAC_MACRO_CNTL =$48B9; + mmBPHYC_DAC_AUTO_CALIB_CONTROL =$48BA; + mmDAC_MACRO_CNTL_RESERVED3 =$48BB; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 =$48C0; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 =$48C1; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 =$48C2; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 =$48C3; + mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL =$48C4; + mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV =$48C5; + mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 =$48C6; + mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 =$48C7; + mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE =$48C8; + mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL =$48C9; + mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION =$48CA; + mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT =$48CB; + mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL =$48CC; + mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 =$48CD; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 =$48CE; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 =$48CF; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 =$48D0; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 =$48D1; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 =$48D2; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 =$48D3; + mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL =$48D4; + mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED =$48D5; + mmBPHYC_UNIPHY0_UNIPHY_DEBUG =$48D6; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 =$48D7; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 =$48D8; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 =$48D9; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 =$48DA; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 =$48DB; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 =$48DC; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 =$48DD; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 =$48DE; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 =$48DF; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 =$48E0; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 =$48E1; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 =$48E2; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 =$48E3; + mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL =$48E4; + mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV =$48E5; + mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 =$48E6; + mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 =$48E7; + mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE =$48E8; + mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL =$48E9; + mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION =$48EA; + mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT =$48EB; + mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL =$48EC; + mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 =$48ED; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 =$48EE; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 =$48EF; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 =$48F0; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 =$48F1; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 =$48F2; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 =$48F3; + mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL =$48F4; + mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED =$48F5; + mmBPHYC_UNIPHY1_UNIPHY_DEBUG =$48F6; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 =$48F7; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 =$48F8; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 =$48F9; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 =$48FA; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 =$48FB; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 =$48FC; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 =$48FD; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 =$48FE; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 =$48FF; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 =$4900; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 =$4901; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 =$4902; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 =$4903; + mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL =$4904; + mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV =$4905; + mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 =$4906; + mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 =$4907; + mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE =$4908; + mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL =$4909; + mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION =$490A; + mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT =$490B; + mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL =$490C; + mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 =$490D; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 =$490E; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 =$490F; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 =$4910; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 =$4911; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 =$4912; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 =$4913; + mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL =$4914; + mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED =$4915; + mmBPHYC_UNIPHY2_UNIPHY_DEBUG =$4916; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 =$4917; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 =$4918; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 =$4919; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 =$491A; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 =$491B; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 =$491C; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 =$491D; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 =$491E; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 =$491F; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 =$4920; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 =$4921; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 =$4922; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 =$4923; + mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL =$4924; + mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV =$4925; + mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 =$4926; + mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 =$4927; + mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE =$4928; + mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL =$4929; + mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION =$492A; + mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT =$492B; + mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL =$492C; + mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 =$492D; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 =$492E; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 =$492F; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 =$4930; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 =$4931; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 =$4932; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 =$4933; + mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL =$4934; + mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED =$4935; + mmBPHYC_UNIPHY3_UNIPHY_DEBUG =$4936; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 =$4937; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 =$4938; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 =$4939; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 =$493A; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 =$493B; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 =$493C; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 =$493D; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 =$493E; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 =$493F; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 =$4940; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 =$4941; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 =$4942; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 =$4943; + mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL =$4944; + mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV =$4945; + mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 =$4946; + mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 =$4947; + mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE =$4948; + mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL =$4949; + mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION =$494A; + mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT =$494B; + mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL =$494C; + mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 =$494D; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 =$494E; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 =$494F; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 =$4950; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 =$4951; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 =$4952; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 =$4953; + mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL =$4954; + mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED =$4955; + mmBPHYC_UNIPHY4_UNIPHY_DEBUG =$4956; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 =$4957; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 =$4958; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 =$4959; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 =$495A; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 =$495B; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 =$495C; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 =$495D; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 =$495E; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 =$495F; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 =$4960; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 =$4961; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 =$4962; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 =$4963; + mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL =$4964; + mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV =$4965; + mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 =$4966; + mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 =$4967; + mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE =$4968; + mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL =$4969; + mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION =$496A; + mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT =$496B; + mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL =$496C; + mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 =$496D; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 =$496E; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 =$496F; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 =$4970; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 =$4971; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 =$4972; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 =$4973; + mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL =$4974; + mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED =$4975; + mmBPHYC_UNIPHY5_UNIPHY_DEBUG =$4976; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 =$4977; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 =$4978; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 =$4979; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 =$497A; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 =$497B; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 =$497C; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 =$497D; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 =$497E; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 =$497F; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 =$4980; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 =$4981; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 =$4982; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 =$4983; + mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL =$4984; + mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV =$4985; + mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 =$4986; + mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 =$4987; + mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE =$4988; + mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL =$4989; + mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION =$498A; + mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT =$498B; + mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL =$498C; + mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 =$498D; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 =$498E; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 =$498F; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 =$4990; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 =$4991; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 =$4992; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 =$4993; + mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL =$4994; + mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED =$4995; + mmBPHYC_UNIPHY6_UNIPHY_DEBUG =$4996; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 =$4997; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 =$4998; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 =$4999; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 =$499A; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 =$499B; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 =$499C; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 =$499D; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 =$499E; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 =$499F; + mmDIG0_DIG_FE_CNTL =$4A00; + mmDIG0_DIG_OUTPUT_CRC_CNTL =$4A01; + mmDIG0_DIG_OUTPUT_CRC_RESULT =$4A02; + mmDIG0_DIG_CLOCK_PATTERN =$4A03; + mmDIG0_DIG_TEST_PATTERN =$4A04; + mmDIG0_DIG_RANDOM_PATTERN_SEED =$4A05; + mmDIG0_DIG_FIFO_STATUS =$4A06; + mmDIG0_DIG_DISPCLK_SWITCH_CNTL =$4A07; + mmDIG0_DIG_DISPCLK_SWITCH_STATUS =$4A08; + mmDIG0_HDMI_CONTROL =$4A09; + mmDIG0_HDMI_STATUS =$4A0A; + mmDIG0_HDMI_AUDIO_PACKET_CONTROL =$4A0B; + mmDIG0_HDMI_ACR_PACKET_CONTROL =$4A0C; + mmDIG0_HDMI_VBI_PACKET_CONTROL =$4A0D; + mmDIG0_HDMI_INFOFRAME_CONTROL0 =$4A0E; + mmDIG0_HDMI_INFOFRAME_CONTROL1 =$4A0F; + mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 =$4A10; + mmDIG0_HDMI_GC =$4A13; + mmAFMT_AUDIO_PACKET_CONTROL2 =$4A14; + mmAFMT_ISRC1_0 =$4A15; + mmAFMT_ISRC1_1 =$4A16; + mmAFMT_ISRC1_2 =$4A17; + mmAFMT_ISRC1_3 =$4A18; + mmAFMT_ISRC1_4 =$4A19; + mmAFMT_ISRC2_0 =$4A1A; + mmAFMT_ISRC2_1 =$4A1B; + mmAFMT_ISRC2_2 =$4A1C; + mmAFMT_ISRC2_3 =$4A1D; + mmAFMT_AVI_INFO0 =$4A1E; + mmAFMT_AVI_INFO1 =$4A1F; + mmAFMT_AVI_INFO2 =$4A20; + mmAFMT_AVI_INFO3 =$4A21; + mmAFMT_MPEG_INFO0 =$4A22; + mmAFMT_MPEG_INFO1 =$4A23; + mmAFMT_GENERIC_HDR =$4A24; + mmAFMT_GENERIC_0 =$4A25; + mmAFMT_GENERIC_1 =$4A26; + mmAFMT_GENERIC_2 =$4A27; + mmAFMT_GENERIC_3 =$4A28; + mmAFMT_GENERIC_4 =$4A29; + mmAFMT_GENERIC_5 =$4A2A; + mmAFMT_GENERIC_6 =$4A2B; + mmAFMT_GENERIC_7 =$4A2C; + mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 =$4A2D; + mmDIG0_HDMI_ACR_32_0 =$4A2E; + mmDIG0_HDMI_ACR_32_1 =$4A2F; + mmDIG0_HDMI_ACR_44_0 =$4A30; + mmDIG0_HDMI_ACR_44_1 =$4A31; + mmDIG0_HDMI_ACR_48_0 =$4A32; + mmDIG0_HDMI_ACR_48_1 =$4A33; + mmDIG0_HDMI_ACR_STATUS_0 =$4A34; + mmDIG0_HDMI_ACR_STATUS_1 =$4A35; + mmAFMT_AUDIO_INFO0 =$4A36; + mmAFMT_AUDIO_INFO1 =$4A37; + mmAFMT_60958_0 =$4A38; + mmAFMT_60958_1 =$4A39; + mmAFMT_AUDIO_CRC_CONTROL =$4A3A; + mmAFMT_RAMP_CONTROL0 =$4A3B; + mmAFMT_RAMP_CONTROL1 =$4A3C; + mmAFMT_RAMP_CONTROL2 =$4A3D; + mmAFMT_RAMP_CONTROL3 =$4A3E; + mmAFMT_60958_2 =$4A3F; + mmAFMT_AUDIO_CRC_RESULT =$4A40; + mmAFMT_STATUS =$4A41; + mmAFMT_AUDIO_PACKET_CONTROL =$4A42; + mmAFMT_VBI_PACKET_CONTROL =$4A43; + mmAFMT_INFOFRAME_CONTROL0 =$4A44; + mmAFMT_AUDIO_SRC_CONTROL =$4A45; + mmAFMT_AUDIO_DBG_DTO_CNTL =$4A46; + mmDIG0_DIG_BE_CNTL =$4A47; + mmDIG0_DIG_BE_EN_CNTL =$4A48; + mmDIG0_TMDS_CNTL =$4A6B; + mmDIG0_TMDS_CONTROL_CHAR =$4A6C; + mmDIG0_TMDS_CONTROL0_FEEDBACK =$4A6D; + mmDIG0_TMDS_STEREOSYNC_CTL_SEL =$4A6E; + mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 =$4A6F; + mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 =$4A70; + mmDIG0_TMDS_DEBUG =$4A71; + mmDIG0_TMDS_CTL_BITS =$4A72; + mmDIG0_TMDS_DCBALANCER_CONTROL =$4A73; + mmDIG0_TMDS_CTL0_1_GEN_CNTL =$4A75; + mmDIG0_TMDS_CTL2_3_GEN_CNTL =$4A76; + mmDIG0_LVDS_DATA_CNTL =$4A78; + mmDIG0_DIG_LANE_ENABLE =$4A79; + mmDIG0_DIG_TEST_DEBUG_INDEX =$4A7A; + mmDIG0_DIG_TEST_DEBUG_DATA =$4A7B; + mmDIG0_DIG_FE_TEST_DEBUG_INDEX =$4A7C; + mmDIG0_DIG_FE_TEST_DEBUG_DATA =$4A7D; + mmCRTC5_CRTC_PIXEL_DATA_READBACK =$4A9A; + mmDP0_DP_LINK_CNTL =$4AA0; + mmDP0_DP_PIXEL_FORMAT =$4AA1; + mmDP0_DP_MSA_COLORIMETRY =$4AA2; + mmDP0_DP_CONFIG =$4AA3; + mmDP0_DP_VID_STREAM_CNTL =$4AA4; + mmDP0_DP_STEER_FIFO =$4AA5; + mmDP0_DP_MSA_MISC =$4AA6; + mmDP0_DP_VID_TIMING =$4AA8; + mmDP0_DP_VID_N =$4AA9; + mmDP0_DP_VID_M =$4AAA; + mmDP0_DP_LINK_FRAMING_CNTL =$4AAB; + mmDP0_DP_HBR2_EYE_PATTERN =$4AAC; + mmDP0_DP_VID_MSA_VBID =$4AAD; + mmDP0_DP_VID_INTERRUPT_CNTL =$4AAE; + mmDP0_DP_DPHY_CNTL =$4AAF; + mmDP0_DP_DPHY_TRAINING_PATTERN_SEL =$4AB0; + mmDP0_DP_DPHY_SYM0 =$4AB1; + mmDP0_DP_DPHY_SYM1 =$4AB2; + mmDP0_DP_DPHY_SYM2 =$4AB3; + mmDP0_DP_DPHY_8B10B_CNTL =$4AB4; + mmDP0_DP_DPHY_PRBS_CNTL =$4AB5; + mmDP0_DP_DPHY_CRC_EN =$4AB7; + mmDP0_DP_DPHY_CRC_CNTL =$4AB8; + mmDP0_DP_DPHY_CRC_RESULT =$4AB9; + mmDP0_DP_DPHY_CRC_MST_CNTL =$4ABA; + mmDP0_DP_DPHY_CRC_MST_STATUS =$4ABB; + mmDP0_DP_DPHY_FAST_TRAINING =$4ABC; + mmDP0_DP_DPHY_FAST_TRAINING_STATUS =$4ABD; + mmDP0_DP_MSA_V_TIMING_OVERRIDE1 =$4ABE; + mmDP0_DP_MSA_V_TIMING_OVERRIDE2 =$4ABF; + mmDP0_DP_SEC_CNTL =$4AC3; + mmDP0_DP_SEC_CNTL1 =$4AC4; + mmDP0_DP_SEC_FRAMING1 =$4AC5; + mmDP0_DP_SEC_FRAMING2 =$4AC6; + mmDP0_DP_SEC_FRAMING3 =$4AC7; + mmDP0_DP_SEC_FRAMING4 =$4AC8; + mmDP0_DP_SEC_AUD_N =$4AC9; + mmDP0_DP_SEC_AUD_N_READBACK =$4ACA; + mmDP0_DP_SEC_AUD_M =$4ACB; + mmDP0_DP_SEC_AUD_M_READBACK =$4ACC; + mmDP0_DP_SEC_TIMESTAMP =$4ACD; + mmDP0_DP_SEC_PACKET_CNTL =$4ACE; + mmDP0_DP_MSE_RATE_CNTL =$4ACF; + mmDP0_DP_MSE_RATE_UPDATE =$4AD1; + mmDP0_DP_MSE_SAT0 =$4AD2; + mmDP0_DP_MSE_SAT1 =$4AD3; + mmDP0_DP_MSE_SAT2 =$4AD4; + mmDP0_DP_MSE_SAT_UPDATE =$4AD5; + mmDP0_DP_MSE_LINK_TIMING =$4AD6; + mmDP0_DP_MSE_MISC_CNTL =$4AD7; + mmDP0_DP_TEST_DEBUG_INDEX =$4AD8; + mmDP0_DP_TEST_DEBUG_DATA =$4AD9; + mmDP0_DP_FE_TEST_DEBUG_INDEX =$4ADA; + mmDP0_DP_FE_TEST_DEBUG_DATA =$4ADB; + mmDIG1_DIG_FE_CNTL =$4B00; + mmDIG1_DIG_OUTPUT_CRC_CNTL =$4B01; + mmDIG1_DIG_OUTPUT_CRC_RESULT =$4B02; + mmDIG1_DIG_CLOCK_PATTERN =$4B03; + mmDIG1_DIG_TEST_PATTERN =$4B04; + mmDIG1_DIG_RANDOM_PATTERN_SEED =$4B05; + mmDIG1_DIG_FIFO_STATUS =$4B06; + mmDIG1_DIG_DISPCLK_SWITCH_CNTL =$4B07; + mmDIG1_DIG_DISPCLK_SWITCH_STATUS =$4B08; + mmDIG1_HDMI_CONTROL =$4B09; + mmDIG1_HDMI_STATUS =$4B0A; + mmDIG1_HDMI_AUDIO_PACKET_CONTROL =$4B0B; + mmDIG1_HDMI_ACR_PACKET_CONTROL =$4B0C; + mmDIG1_HDMI_VBI_PACKET_CONTROL =$4B0D; + mmDIG1_HDMI_INFOFRAME_CONTROL0 =$4B0E; + mmDIG1_HDMI_INFOFRAME_CONTROL1 =$4B0F; + mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 =$4B10; + mmDIG1_HDMI_GC =$4B13; + mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 =$4B14; + mmDIG1_AFMT_ISRC1_0 =$4B15; + mmDIG1_AFMT_ISRC1_1 =$4B16; + mmDIG1_AFMT_ISRC1_2 =$4B17; + mmDIG1_AFMT_ISRC1_3 =$4B18; + mmDIG1_AFMT_ISRC1_4 =$4B19; + mmDIG1_AFMT_ISRC2_0 =$4B1A; + mmDIG1_AFMT_ISRC2_1 =$4B1B; + mmDIG1_AFMT_ISRC2_2 =$4B1C; + mmDIG1_AFMT_ISRC2_3 =$4B1D; + mmDIG1_AFMT_AVI_INFO0 =$4B1E; + mmDIG1_AFMT_AVI_INFO1 =$4B1F; + mmDIG1_AFMT_AVI_INFO2 =$4B20; + mmDIG1_AFMT_AVI_INFO3 =$4B21; + mmDIG1_AFMT_MPEG_INFO0 =$4B22; + mmDIG1_AFMT_MPEG_INFO1 =$4B23; + mmDIG1_AFMT_GENERIC_HDR =$4B24; + mmDIG1_AFMT_GENERIC_0 =$4B25; + mmDIG1_AFMT_GENERIC_1 =$4B26; + mmDIG1_AFMT_GENERIC_2 =$4B27; + mmDIG1_AFMT_GENERIC_3 =$4B28; + mmDIG1_AFMT_GENERIC_4 =$4B29; + mmDIG1_AFMT_GENERIC_5 =$4B2A; + mmDIG1_AFMT_GENERIC_6 =$4B2B; + mmDIG1_AFMT_GENERIC_7 =$4B2C; + mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 =$4B2D; + mmDIG1_HDMI_ACR_32_0 =$4B2E; + mmDIG1_HDMI_ACR_32_1 =$4B2F; + mmDIG1_HDMI_ACR_44_0 =$4B30; + mmDIG1_HDMI_ACR_44_1 =$4B31; + mmDIG1_HDMI_ACR_48_0 =$4B32; + mmDIG1_HDMI_ACR_48_1 =$4B33; + mmDIG1_HDMI_ACR_STATUS_0 =$4B34; + mmDIG1_HDMI_ACR_STATUS_1 =$4B35; + mmDIG1_AFMT_AUDIO_INFO0 =$4B36; + mmDIG1_AFMT_AUDIO_INFO1 =$4B37; + mmDIG1_AFMT_60958_0 =$4B38; + mmDIG1_AFMT_60958_1 =$4B39; + mmDIG1_AFMT_AUDIO_CRC_CONTROL =$4B3A; + mmDIG1_AFMT_RAMP_CONTROL0 =$4B3B; + mmDIG1_AFMT_RAMP_CONTROL1 =$4B3C; + mmDIG1_AFMT_RAMP_CONTROL2 =$4B3D; + mmDIG1_AFMT_RAMP_CONTROL3 =$4B3E; + mmDIG1_AFMT_60958_2 =$4B3F; + mmDIG1_AFMT_AUDIO_CRC_RESULT =$4B40; + mmDIG1_AFMT_STATUS =$4B41; + mmDIG1_AFMT_AUDIO_PACKET_CONTROL =$4B42; + mmDIG1_AFMT_VBI_PACKET_CONTROL =$4B43; + mmDIG1_AFMT_INFOFRAME_CONTROL0 =$4B44; + mmDIG1_AFMT_AUDIO_SRC_CONTROL =$4B45; + mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL =$4B46; + mmDIG1_DIG_BE_CNTL =$4B47; + mmDIG1_DIG_BE_EN_CNTL =$4B48; + mmDIG1_TMDS_CNTL =$4B6B; + mmDIG1_TMDS_CONTROL_CHAR =$4B6C; + mmDIG1_TMDS_CONTROL0_FEEDBACK =$4B6D; + mmDIG1_TMDS_STEREOSYNC_CTL_SEL =$4B6E; + mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 =$4B6F; + mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 =$4B70; + mmDIG1_TMDS_DEBUG =$4B71; + mmDIG1_TMDS_CTL_BITS =$4B72; + mmDIG1_TMDS_DCBALANCER_CONTROL =$4B73; + mmDIG1_TMDS_CTL0_1_GEN_CNTL =$4B75; + mmDIG1_TMDS_CTL2_3_GEN_CNTL =$4B76; + mmDIG1_LVDS_DATA_CNTL =$4B78; + mmDIG1_DIG_LANE_ENABLE =$4B79; + mmDIG1_DIG_TEST_DEBUG_INDEX =$4B7A; + mmDIG1_DIG_TEST_DEBUG_DATA =$4B7B; + mmDIG1_DIG_FE_TEST_DEBUG_INDEX =$4B7C; + mmDIG1_DIG_FE_TEST_DEBUG_DATA =$4B7D; + mmDP1_DP_LINK_CNTL =$4BA0; + mmDP1_DP_PIXEL_FORMAT =$4BA1; + mmDP1_DP_MSA_COLORIMETRY =$4BA2; + mmDP1_DP_CONFIG =$4BA3; + mmDP1_DP_VID_STREAM_CNTL =$4BA4; + mmDP1_DP_STEER_FIFO =$4BA5; + mmDP1_DP_MSA_MISC =$4BA6; + mmDP1_DP_VID_TIMING =$4BA8; + mmDP1_DP_VID_N =$4BA9; + mmDP1_DP_VID_M =$4BAA; + mmDP1_DP_LINK_FRAMING_CNTL =$4BAB; + mmDP1_DP_HBR2_EYE_PATTERN =$4BAC; + mmDP1_DP_VID_MSA_VBID =$4BAD; + mmDP1_DP_VID_INTERRUPT_CNTL =$4BAE; + mmDP1_DP_DPHY_CNTL =$4BAF; + mmDP1_DP_DPHY_TRAINING_PATTERN_SEL =$4BB0; + mmDP1_DP_DPHY_SYM0 =$4BB1; + mmDP1_DP_DPHY_SYM1 =$4BB2; + mmDP1_DP_DPHY_SYM2 =$4BB3; + mmDP1_DP_DPHY_8B10B_CNTL =$4BB4; + mmDP1_DP_DPHY_PRBS_CNTL =$4BB5; + mmDP1_DP_DPHY_CRC_EN =$4BB7; + mmDP1_DP_DPHY_CRC_CNTL =$4BB8; + mmDP1_DP_DPHY_CRC_RESULT =$4BB9; + mmDP1_DP_DPHY_CRC_MST_CNTL =$4BBA; + mmDP1_DP_DPHY_CRC_MST_STATUS =$4BBB; + mmDP1_DP_DPHY_FAST_TRAINING =$4BBC; + mmDP1_DP_DPHY_FAST_TRAINING_STATUS =$4BBD; + mmDP1_DP_MSA_V_TIMING_OVERRIDE1 =$4BBE; + mmDP1_DP_MSA_V_TIMING_OVERRIDE2 =$4BBF; + mmDP1_DP_SEC_CNTL =$4BC3; + mmDP1_DP_SEC_CNTL1 =$4BC4; + mmDP1_DP_SEC_FRAMING1 =$4BC5; + mmDP1_DP_SEC_FRAMING2 =$4BC6; + mmDP1_DP_SEC_FRAMING3 =$4BC7; + mmDP1_DP_SEC_FRAMING4 =$4BC8; + mmDP1_DP_SEC_AUD_N =$4BC9; + mmDP1_DP_SEC_AUD_N_READBACK =$4BCA; + mmDP1_DP_SEC_AUD_M =$4BCB; + mmDP1_DP_SEC_AUD_M_READBACK =$4BCC; + mmDP1_DP_SEC_TIMESTAMP =$4BCD; + mmDP1_DP_SEC_PACKET_CNTL =$4BCE; + mmDP1_DP_MSE_RATE_CNTL =$4BCF; + mmDP1_DP_MSE_RATE_UPDATE =$4BD1; + mmDP1_DP_MSE_SAT0 =$4BD2; + mmDP1_DP_MSE_SAT1 =$4BD3; + mmDP1_DP_MSE_SAT2 =$4BD4; + mmDP1_DP_MSE_SAT_UPDATE =$4BD5; + mmDP1_DP_MSE_LINK_TIMING =$4BD6; + mmDP1_DP_MSE_MISC_CNTL =$4BD7; + mmDP1_DP_TEST_DEBUG_INDEX =$4BD8; + mmDP1_DP_TEST_DEBUG_DATA =$4BD9; + mmDP1_DP_FE_TEST_DEBUG_INDEX =$4BDA; + mmDP1_DP_FE_TEST_DEBUG_DATA =$4BDB; + mmDIG2_DIG_FE_CNTL =$4C00; + mmDIG2_DIG_OUTPUT_CRC_CNTL =$4C01; + mmDIG2_DIG_OUTPUT_CRC_RESULT =$4C02; + mmDIG2_DIG_CLOCK_PATTERN =$4C03; + mmDIG2_DIG_TEST_PATTERN =$4C04; + mmDIG2_DIG_RANDOM_PATTERN_SEED =$4C05; + mmDIG2_DIG_FIFO_STATUS =$4C06; + mmDIG2_DIG_DISPCLK_SWITCH_CNTL =$4C07; + mmDIG2_DIG_DISPCLK_SWITCH_STATUS =$4C08; + mmDIG2_HDMI_CONTROL =$4C09; + mmDIG2_HDMI_STATUS =$4C0A; + mmDIG2_HDMI_AUDIO_PACKET_CONTROL =$4C0B; + mmDIG2_HDMI_ACR_PACKET_CONTROL =$4C0C; + mmDIG2_HDMI_VBI_PACKET_CONTROL =$4C0D; + mmDIG2_HDMI_INFOFRAME_CONTROL0 =$4C0E; + mmDIG2_HDMI_INFOFRAME_CONTROL1 =$4C0F; + mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 =$4C10; + mmDIG2_HDMI_GC =$4C13; + mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 =$4C14; + mmDIG2_AFMT_ISRC1_0 =$4C15; + mmDIG2_AFMT_ISRC1_1 =$4C16; + mmDIG2_AFMT_ISRC1_2 =$4C17; + mmDIG2_AFMT_ISRC1_3 =$4C18; + mmDIG2_AFMT_ISRC1_4 =$4C19; + mmDIG2_AFMT_ISRC2_0 =$4C1A; + mmDIG2_AFMT_ISRC2_1 =$4C1B; + mmDIG2_AFMT_ISRC2_2 =$4C1C; + mmDIG2_AFMT_ISRC2_3 =$4C1D; + mmDIG2_AFMT_AVI_INFO0 =$4C1E; + mmDIG2_AFMT_AVI_INFO1 =$4C1F; + mmDIG2_AFMT_AVI_INFO2 =$4C20; + mmDIG2_AFMT_AVI_INFO3 =$4C21; + mmDIG2_AFMT_MPEG_INFO0 =$4C22; + mmDIG2_AFMT_MPEG_INFO1 =$4C23; + mmDIG2_AFMT_GENERIC_HDR =$4C24; + mmDIG2_AFMT_GENERIC_0 =$4C25; + mmDIG2_AFMT_GENERIC_1 =$4C26; + mmDIG2_AFMT_GENERIC_2 =$4C27; + mmDIG2_AFMT_GENERIC_3 =$4C28; + mmDIG2_AFMT_GENERIC_4 =$4C29; + mmDIG2_AFMT_GENERIC_5 =$4C2A; + mmDIG2_AFMT_GENERIC_6 =$4C2B; + mmDIG2_AFMT_GENERIC_7 =$4C2C; + mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 =$4C2D; + mmDIG2_HDMI_ACR_32_0 =$4C2E; + mmDIG2_HDMI_ACR_32_1 =$4C2F; + mmDIG2_HDMI_ACR_44_0 =$4C30; + mmDIG2_HDMI_ACR_44_1 =$4C31; + mmDIG2_HDMI_ACR_48_0 =$4C32; + mmDIG2_HDMI_ACR_48_1 =$4C33; + mmDIG2_HDMI_ACR_STATUS_0 =$4C34; + mmDIG2_HDMI_ACR_STATUS_1 =$4C35; + mmDIG2_AFMT_AUDIO_INFO0 =$4C36; + mmDIG2_AFMT_AUDIO_INFO1 =$4C37; + mmDIG2_AFMT_60958_0 =$4C38; + mmDIG2_AFMT_60958_1 =$4C39; + mmDIG2_AFMT_AUDIO_CRC_CONTROL =$4C3A; + mmDIG2_AFMT_RAMP_CONTROL0 =$4C3B; + mmDIG2_AFMT_RAMP_CONTROL1 =$4C3C; + mmDIG2_AFMT_RAMP_CONTROL2 =$4C3D; + mmDIG2_AFMT_RAMP_CONTROL3 =$4C3E; + mmDIG2_AFMT_60958_2 =$4C3F; + mmDIG2_AFMT_AUDIO_CRC_RESULT =$4C40; + mmDIG2_AFMT_STATUS =$4C41; + mmDIG2_AFMT_AUDIO_PACKET_CONTROL =$4C42; + mmDIG2_AFMT_VBI_PACKET_CONTROL =$4C43; + mmDIG2_AFMT_INFOFRAME_CONTROL0 =$4C44; + mmDIG2_AFMT_AUDIO_SRC_CONTROL =$4C45; + mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL =$4C46; + mmDIG2_DIG_BE_CNTL =$4C47; + mmDIG2_DIG_BE_EN_CNTL =$4C48; + mmDIG2_TMDS_CNTL =$4C6B; + mmDIG2_TMDS_CONTROL_CHAR =$4C6C; + mmDIG2_TMDS_CONTROL0_FEEDBACK =$4C6D; + mmDIG2_TMDS_STEREOSYNC_CTL_SEL =$4C6E; + mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 =$4C6F; + mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 =$4C70; + mmDIG2_TMDS_DEBUG =$4C71; + mmDIG2_TMDS_CTL_BITS =$4C72; + mmDIG2_TMDS_DCBALANCER_CONTROL =$4C73; + mmDIG2_TMDS_CTL0_1_GEN_CNTL =$4C75; + mmDIG2_TMDS_CTL2_3_GEN_CNTL =$4C76; + mmDIG2_LVDS_DATA_CNTL =$4C78; + mmDIG2_DIG_LANE_ENABLE =$4C79; + mmDIG2_DIG_TEST_DEBUG_INDEX =$4C7A; + mmDIG2_DIG_TEST_DEBUG_DATA =$4C7B; + mmDIG2_DIG_FE_TEST_DEBUG_INDEX =$4C7C; + mmDIG2_DIG_FE_TEST_DEBUG_DATA =$4C7D; + mmDP2_DP_LINK_CNTL =$4CA0; + mmDP2_DP_PIXEL_FORMAT =$4CA1; + mmDP2_DP_MSA_COLORIMETRY =$4CA2; + mmDP2_DP_CONFIG =$4CA3; + mmDP2_DP_VID_STREAM_CNTL =$4CA4; + mmDP2_DP_STEER_FIFO =$4CA5; + mmDP2_DP_MSA_MISC =$4CA6; + mmDP2_DP_VID_TIMING =$4CA8; + mmDP2_DP_VID_N =$4CA9; + mmDP2_DP_VID_M =$4CAA; + mmDP2_DP_LINK_FRAMING_CNTL =$4CAB; + mmDP2_DP_HBR2_EYE_PATTERN =$4CAC; + mmDP2_DP_VID_MSA_VBID =$4CAD; + mmDP2_DP_VID_INTERRUPT_CNTL =$4CAE; + mmDP2_DP_DPHY_CNTL =$4CAF; + mmDP2_DP_DPHY_TRAINING_PATTERN_SEL =$4CB0; + mmDP2_DP_DPHY_SYM0 =$4CB1; + mmDP2_DP_DPHY_SYM1 =$4CB2; + mmDP2_DP_DPHY_SYM2 =$4CB3; + mmDP2_DP_DPHY_8B10B_CNTL =$4CB4; + mmDP2_DP_DPHY_PRBS_CNTL =$4CB5; + mmDP2_DP_DPHY_CRC_EN =$4CB7; + mmDP2_DP_DPHY_CRC_CNTL =$4CB8; + mmDP2_DP_DPHY_CRC_RESULT =$4CB9; + mmDP2_DP_DPHY_CRC_MST_CNTL =$4CBA; + mmDP2_DP_DPHY_CRC_MST_STATUS =$4CBB; + mmDP2_DP_DPHY_FAST_TRAINING =$4CBC; + mmDP2_DP_DPHY_FAST_TRAINING_STATUS =$4CBD; + mmDP2_DP_MSA_V_TIMING_OVERRIDE1 =$4CBE; + mmDP2_DP_MSA_V_TIMING_OVERRIDE2 =$4CBF; + mmDP2_DP_SEC_CNTL =$4CC3; + mmDP2_DP_SEC_CNTL1 =$4CC4; + mmDP2_DP_SEC_FRAMING1 =$4CC5; + mmDP2_DP_SEC_FRAMING2 =$4CC6; + mmDP2_DP_SEC_FRAMING3 =$4CC7; + mmDP2_DP_SEC_FRAMING4 =$4CC8; + mmDP2_DP_SEC_AUD_N =$4CC9; + mmDP2_DP_SEC_AUD_N_READBACK =$4CCA; + mmDP2_DP_SEC_AUD_M =$4CCB; + mmDP2_DP_SEC_AUD_M_READBACK =$4CCC; + mmDP2_DP_SEC_TIMESTAMP =$4CCD; + mmDP2_DP_SEC_PACKET_CNTL =$4CCE; + mmDP2_DP_MSE_RATE_CNTL =$4CCF; + mmDP2_DP_MSE_RATE_UPDATE =$4CD1; + mmDP2_DP_MSE_SAT0 =$4CD2; + mmDP2_DP_MSE_SAT1 =$4CD3; + mmDP2_DP_MSE_SAT2 =$4CD4; + mmDP2_DP_MSE_SAT_UPDATE =$4CD5; + mmDP2_DP_MSE_LINK_TIMING =$4CD6; + mmDP2_DP_MSE_MISC_CNTL =$4CD7; + mmDP2_DP_TEST_DEBUG_INDEX =$4CD8; + mmDP2_DP_TEST_DEBUG_DATA =$4CD9; + mmDP2_DP_FE_TEST_DEBUG_INDEX =$4CDA; + mmDP2_DP_FE_TEST_DEBUG_DATA =$4CDB; + mmDIG3_DIG_FE_CNTL =$4D00; + mmDIG3_DIG_OUTPUT_CRC_CNTL =$4D01; + mmDIG3_DIG_OUTPUT_CRC_RESULT =$4D02; + mmDIG3_DIG_CLOCK_PATTERN =$4D03; + mmDIG3_DIG_TEST_PATTERN =$4D04; + mmDIG3_DIG_RANDOM_PATTERN_SEED =$4D05; + mmDIG3_DIG_FIFO_STATUS =$4D06; + mmDIG3_DIG_DISPCLK_SWITCH_CNTL =$4D07; + mmDIG3_DIG_DISPCLK_SWITCH_STATUS =$4D08; + mmDIG3_HDMI_CONTROL =$4D09; + mmDIG3_HDMI_STATUS =$4D0A; + mmDIG3_HDMI_AUDIO_PACKET_CONTROL =$4D0B; + mmDIG3_HDMI_ACR_PACKET_CONTROL =$4D0C; + mmDIG3_HDMI_VBI_PACKET_CONTROL =$4D0D; + mmDIG3_HDMI_INFOFRAME_CONTROL0 =$4D0E; + mmDIG3_HDMI_INFOFRAME_CONTROL1 =$4D0F; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 =$4D10; + mmDIG3_HDMI_GC =$4D13; + mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 =$4D14; + mmDIG3_AFMT_ISRC1_0 =$4D15; + mmDIG3_AFMT_ISRC1_1 =$4D16; + mmDIG3_AFMT_ISRC1_2 =$4D17; + mmDIG3_AFMT_ISRC1_3 =$4D18; + mmDIG3_AFMT_ISRC1_4 =$4D19; + mmDIG3_AFMT_ISRC2_0 =$4D1A; + mmDIG3_AFMT_ISRC2_1 =$4D1B; + mmDIG3_AFMT_ISRC2_2 =$4D1C; + mmDIG3_AFMT_ISRC2_3 =$4D1D; + mmDIG3_AFMT_AVI_INFO0 =$4D1E; + mmDIG3_AFMT_AVI_INFO1 =$4D1F; + mmDIG3_AFMT_AVI_INFO2 =$4D20; + mmDIG3_AFMT_AVI_INFO3 =$4D21; + mmDIG3_AFMT_MPEG_INFO0 =$4D22; + mmDIG3_AFMT_MPEG_INFO1 =$4D23; + mmDIG3_AFMT_GENERIC_HDR =$4D24; + mmDIG3_AFMT_GENERIC_0 =$4D25; + mmDIG3_AFMT_GENERIC_1 =$4D26; + mmDIG3_AFMT_GENERIC_2 =$4D27; + mmDIG3_AFMT_GENERIC_3 =$4D28; + mmDIG3_AFMT_GENERIC_4 =$4D29; + mmDIG3_AFMT_GENERIC_5 =$4D2A; + mmDIG3_AFMT_GENERIC_6 =$4D2B; + mmDIG3_AFMT_GENERIC_7 =$4D2C; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 =$4D2D; + mmDIG3_HDMI_ACR_32_0 =$4D2E; + mmDIG3_HDMI_ACR_32_1 =$4D2F; + mmDIG3_HDMI_ACR_44_0 =$4D30; + mmDIG3_HDMI_ACR_44_1 =$4D31; + mmDIG3_HDMI_ACR_48_0 =$4D32; + mmDIG3_HDMI_ACR_48_1 =$4D33; + mmDIG3_HDMI_ACR_STATUS_0 =$4D34; + mmDIG3_HDMI_ACR_STATUS_1 =$4D35; + mmDIG3_AFMT_AUDIO_INFO0 =$4D36; + mmDIG3_AFMT_AUDIO_INFO1 =$4D37; + mmDIG3_AFMT_60958_0 =$4D38; + mmDIG3_AFMT_60958_1 =$4D39; + mmDIG3_AFMT_AUDIO_CRC_CONTROL =$4D3A; + mmDIG3_AFMT_RAMP_CONTROL0 =$4D3B; + mmDIG3_AFMT_RAMP_CONTROL1 =$4D3C; + mmDIG3_AFMT_RAMP_CONTROL2 =$4D3D; + mmDIG3_AFMT_RAMP_CONTROL3 =$4D3E; + mmDIG3_AFMT_60958_2 =$4D3F; + mmDIG3_AFMT_AUDIO_CRC_RESULT =$4D40; + mmDIG3_AFMT_STATUS =$4D41; + mmDIG3_AFMT_AUDIO_PACKET_CONTROL =$4D42; + mmDIG3_AFMT_VBI_PACKET_CONTROL =$4D43; + mmDIG3_AFMT_INFOFRAME_CONTROL0 =$4D44; + mmDIG3_AFMT_AUDIO_SRC_CONTROL =$4D45; + mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL =$4D46; + mmDIG3_DIG_BE_CNTL =$4D47; + mmDIG3_DIG_BE_EN_CNTL =$4D48; + mmDIG3_TMDS_CNTL =$4D6B; + mmDIG3_TMDS_CONTROL_CHAR =$4D6C; + mmDIG3_TMDS_CONTROL0_FEEDBACK =$4D6D; + mmDIG3_TMDS_STEREOSYNC_CTL_SEL =$4D6E; + mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 =$4D6F; + mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 =$4D70; + mmDIG3_TMDS_DEBUG =$4D71; + mmDIG3_TMDS_CTL_BITS =$4D72; + mmDIG3_TMDS_DCBALANCER_CONTROL =$4D73; + mmDIG3_TMDS_CTL0_1_GEN_CNTL =$4D75; + mmDIG3_TMDS_CTL2_3_GEN_CNTL =$4D76; + mmDIG3_LVDS_DATA_CNTL =$4D78; + mmDIG3_DIG_LANE_ENABLE =$4D79; + mmDIG3_DIG_TEST_DEBUG_INDEX =$4D7A; + mmDIG3_DIG_TEST_DEBUG_DATA =$4D7B; + mmDIG3_DIG_FE_TEST_DEBUG_INDEX =$4D7C; + mmDIG3_DIG_FE_TEST_DEBUG_DATA =$4D7D; + mmDP3_DP_LINK_CNTL =$4DA0; + mmDP3_DP_PIXEL_FORMAT =$4DA1; + mmDP3_DP_MSA_COLORIMETRY =$4DA2; + mmDP3_DP_CONFIG =$4DA3; + mmDP3_DP_VID_STREAM_CNTL =$4DA4; + mmDP3_DP_STEER_FIFO =$4DA5; + mmDP3_DP_MSA_MISC =$4DA6; + mmDP3_DP_VID_TIMING =$4DA8; + mmDP3_DP_VID_N =$4DA9; + mmDP3_DP_VID_M =$4DAA; + mmDP3_DP_LINK_FRAMING_CNTL =$4DAB; + mmDP3_DP_HBR2_EYE_PATTERN =$4DAC; + mmDP3_DP_VID_MSA_VBID =$4DAD; + mmDP3_DP_VID_INTERRUPT_CNTL =$4DAE; + mmDP3_DP_DPHY_CNTL =$4DAF; + mmDP3_DP_DPHY_TRAINING_PATTERN_SEL =$4DB0; + mmDP3_DP_DPHY_SYM0 =$4DB1; + mmDP3_DP_DPHY_SYM1 =$4DB2; + mmDP3_DP_DPHY_SYM2 =$4DB3; + mmDP3_DP_DPHY_8B10B_CNTL =$4DB4; + mmDP3_DP_DPHY_PRBS_CNTL =$4DB5; + mmDP3_DP_DPHY_CRC_EN =$4DB7; + mmDP3_DP_DPHY_CRC_CNTL =$4DB8; + mmDP3_DP_DPHY_CRC_RESULT =$4DB9; + mmDP3_DP_DPHY_CRC_MST_CNTL =$4DBA; + mmDP3_DP_DPHY_CRC_MST_STATUS =$4DBB; + mmDP3_DP_DPHY_FAST_TRAINING =$4DBC; + mmDP3_DP_DPHY_FAST_TRAINING_STATUS =$4DBD; + mmDP3_DP_MSA_V_TIMING_OVERRIDE1 =$4DBE; + mmDP3_DP_MSA_V_TIMING_OVERRIDE2 =$4DBF; + mmDP3_DP_SEC_CNTL =$4DC3; + mmDP3_DP_SEC_CNTL1 =$4DC4; + mmDP3_DP_SEC_FRAMING1 =$4DC5; + mmDP3_DP_SEC_FRAMING2 =$4DC6; + mmDP3_DP_SEC_FRAMING3 =$4DC7; + mmDP3_DP_SEC_FRAMING4 =$4DC8; + mmDP3_DP_SEC_AUD_N =$4DC9; + mmDP3_DP_SEC_AUD_N_READBACK =$4DCA; + mmDP3_DP_SEC_AUD_M =$4DCB; + mmDP3_DP_SEC_AUD_M_READBACK =$4DCC; + mmDP3_DP_SEC_TIMESTAMP =$4DCD; + mmDP3_DP_SEC_PACKET_CNTL =$4DCE; + mmDP3_DP_MSE_RATE_CNTL =$4DCF; + mmDP3_DP_MSE_RATE_UPDATE =$4DD1; + mmDP3_DP_MSE_SAT0 =$4DD2; + mmDP3_DP_MSE_SAT1 =$4DD3; + mmDP3_DP_MSE_SAT2 =$4DD4; + mmDP3_DP_MSE_SAT_UPDATE =$4DD5; + mmDP3_DP_MSE_LINK_TIMING =$4DD6; + mmDP3_DP_MSE_MISC_CNTL =$4DD7; + mmDP3_DP_TEST_DEBUG_INDEX =$4DD8; + mmDP3_DP_TEST_DEBUG_DATA =$4DD9; + mmDP3_DP_FE_TEST_DEBUG_INDEX =$4DDA; + mmDP3_DP_FE_TEST_DEBUG_DATA =$4DDB; + mmDIG4_DIG_FE_CNTL =$4E00; + mmDIG4_DIG_OUTPUT_CRC_CNTL =$4E01; + mmDIG4_DIG_OUTPUT_CRC_RESULT =$4E02; + mmDIG4_DIG_CLOCK_PATTERN =$4E03; + mmDIG4_DIG_TEST_PATTERN =$4E04; + mmDIG4_DIG_RANDOM_PATTERN_SEED =$4E05; + mmDIG4_DIG_FIFO_STATUS =$4E06; + mmDIG4_DIG_DISPCLK_SWITCH_CNTL =$4E07; + mmDIG4_DIG_DISPCLK_SWITCH_STATUS =$4E08; + mmDIG4_HDMI_CONTROL =$4E09; + mmDIG4_HDMI_STATUS =$4E0A; + mmDIG4_HDMI_AUDIO_PACKET_CONTROL =$4E0B; + mmDIG4_HDMI_ACR_PACKET_CONTROL =$4E0C; + mmDIG4_HDMI_VBI_PACKET_CONTROL =$4E0D; + mmDIG4_HDMI_INFOFRAME_CONTROL0 =$4E0E; + mmDIG4_HDMI_INFOFRAME_CONTROL1 =$4E0F; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 =$4E10; + mmDIG4_HDMI_GC =$4E13; + mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 =$4E14; + mmDIG4_AFMT_ISRC1_0 =$4E15; + mmDIG4_AFMT_ISRC1_1 =$4E16; + mmDIG4_AFMT_ISRC1_2 =$4E17; + mmDIG4_AFMT_ISRC1_3 =$4E18; + mmDIG4_AFMT_ISRC1_4 =$4E19; + mmDIG4_AFMT_ISRC2_0 =$4E1A; + mmDIG4_AFMT_ISRC2_1 =$4E1B; + mmDIG4_AFMT_ISRC2_2 =$4E1C; + mmDIG4_AFMT_ISRC2_3 =$4E1D; + mmDIG4_AFMT_AVI_INFO0 =$4E1E; + mmDIG4_AFMT_AVI_INFO1 =$4E1F; + mmDIG4_AFMT_AVI_INFO2 =$4E20; + mmDIG4_AFMT_AVI_INFO3 =$4E21; + mmDIG4_AFMT_MPEG_INFO0 =$4E22; + mmDIG4_AFMT_MPEG_INFO1 =$4E23; + mmDIG4_AFMT_GENERIC_HDR =$4E24; + mmDIG4_AFMT_GENERIC_0 =$4E25; + mmDIG4_AFMT_GENERIC_1 =$4E26; + mmDIG4_AFMT_GENERIC_2 =$4E27; + mmDIG4_AFMT_GENERIC_3 =$4E28; + mmDIG4_AFMT_GENERIC_4 =$4E29; + mmDIG4_AFMT_GENERIC_5 =$4E2A; + mmDIG4_AFMT_GENERIC_6 =$4E2B; + mmDIG4_AFMT_GENERIC_7 =$4E2C; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 =$4E2D; + mmDIG4_HDMI_ACR_32_0 =$4E2E; + mmDIG4_HDMI_ACR_32_1 =$4E2F; + mmDIG4_HDMI_ACR_44_0 =$4E30; + mmDIG4_HDMI_ACR_44_1 =$4E31; + mmDIG4_HDMI_ACR_48_0 =$4E32; + mmDIG4_HDMI_ACR_48_1 =$4E33; + mmDIG4_HDMI_ACR_STATUS_0 =$4E34; + mmDIG4_HDMI_ACR_STATUS_1 =$4E35; + mmDIG4_AFMT_AUDIO_INFO0 =$4E36; + mmDIG4_AFMT_AUDIO_INFO1 =$4E37; + mmDIG4_AFMT_60958_0 =$4E38; + mmDIG4_AFMT_60958_1 =$4E39; + mmDIG4_AFMT_AUDIO_CRC_CONTROL =$4E3A; + mmDIG4_AFMT_RAMP_CONTROL0 =$4E3B; + mmDIG4_AFMT_RAMP_CONTROL1 =$4E3C; + mmDIG4_AFMT_RAMP_CONTROL2 =$4E3D; + mmDIG4_AFMT_RAMP_CONTROL3 =$4E3E; + mmDIG4_AFMT_60958_2 =$4E3F; + mmDIG4_AFMT_AUDIO_CRC_RESULT =$4E40; + mmDIG4_AFMT_STATUS =$4E41; + mmDIG4_AFMT_AUDIO_PACKET_CONTROL =$4E42; + mmDIG4_AFMT_VBI_PACKET_CONTROL =$4E43; + mmDIG4_AFMT_INFOFRAME_CONTROL0 =$4E44; + mmDIG4_AFMT_AUDIO_SRC_CONTROL =$4E45; + mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL =$4E46; + mmDIG4_DIG_BE_CNTL =$4E47; + mmDIG4_DIG_BE_EN_CNTL =$4E48; + mmDIG4_TMDS_CNTL =$4E6B; + mmDIG4_TMDS_CONTROL_CHAR =$4E6C; + mmDIG4_TMDS_CONTROL0_FEEDBACK =$4E6D; + mmDIG4_TMDS_STEREOSYNC_CTL_SEL =$4E6E; + mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 =$4E6F; + mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 =$4E70; + mmDIG4_TMDS_DEBUG =$4E71; + mmDIG4_TMDS_CTL_BITS =$4E72; + mmDIG4_TMDS_DCBALANCER_CONTROL =$4E73; + mmDIG4_TMDS_CTL0_1_GEN_CNTL =$4E75; + mmDIG4_TMDS_CTL2_3_GEN_CNTL =$4E76; + mmDIG4_LVDS_DATA_CNTL =$4E78; + mmDIG4_DIG_LANE_ENABLE =$4E79; + mmDIG4_DIG_TEST_DEBUG_INDEX =$4E7A; + mmDIG4_DIG_TEST_DEBUG_DATA =$4E7B; + mmDIG4_DIG_FE_TEST_DEBUG_INDEX =$4E7C; + mmDIG4_DIG_FE_TEST_DEBUG_DATA =$4E7D; + mmDP4_DP_LINK_CNTL =$4EA0; + mmDP4_DP_PIXEL_FORMAT =$4EA1; + mmDP4_DP_MSA_COLORIMETRY =$4EA2; + mmDP4_DP_CONFIG =$4EA3; + mmDP4_DP_VID_STREAM_CNTL =$4EA4; + mmDP4_DP_STEER_FIFO =$4EA5; + mmDP4_DP_MSA_MISC =$4EA6; + mmDP4_DP_VID_TIMING =$4EA8; + mmDP4_DP_VID_N =$4EA9; + mmDP4_DP_VID_M =$4EAA; + mmDP4_DP_LINK_FRAMING_CNTL =$4EAB; + mmDP4_DP_HBR2_EYE_PATTERN =$4EAC; + mmDP4_DP_VID_MSA_VBID =$4EAD; + mmDP4_DP_VID_INTERRUPT_CNTL =$4EAE; + mmDP4_DP_DPHY_CNTL =$4EAF; + mmDP4_DP_DPHY_TRAINING_PATTERN_SEL =$4EB0; + mmDP4_DP_DPHY_SYM0 =$4EB1; + mmDP4_DP_DPHY_SYM1 =$4EB2; + mmDP4_DP_DPHY_SYM2 =$4EB3; + mmDP4_DP_DPHY_8B10B_CNTL =$4EB4; + mmDP4_DP_DPHY_PRBS_CNTL =$4EB5; + mmDP4_DP_DPHY_CRC_EN =$4EB7; + mmDP4_DP_DPHY_CRC_CNTL =$4EB8; + mmDP4_DP_DPHY_CRC_RESULT =$4EB9; + mmDP4_DP_DPHY_CRC_MST_CNTL =$4EBA; + mmDP4_DP_DPHY_CRC_MST_STATUS =$4EBB; + mmDP4_DP_DPHY_FAST_TRAINING =$4EBC; + mmDP4_DP_DPHY_FAST_TRAINING_STATUS =$4EBD; + mmDP4_DP_MSA_V_TIMING_OVERRIDE1 =$4EBE; + mmDP4_DP_MSA_V_TIMING_OVERRIDE2 =$4EBF; + mmDP4_DP_SEC_CNTL =$4EC3; + mmDP4_DP_SEC_CNTL1 =$4EC4; + mmDP4_DP_SEC_FRAMING1 =$4EC5; + mmDP4_DP_SEC_FRAMING2 =$4EC6; + mmDP4_DP_SEC_FRAMING3 =$4EC7; + mmDP4_DP_SEC_FRAMING4 =$4EC8; + mmDP4_DP_SEC_AUD_N =$4EC9; + mmDP4_DP_SEC_AUD_N_READBACK =$4ECA; + mmDP4_DP_SEC_AUD_M =$4ECB; + mmDP4_DP_SEC_AUD_M_READBACK =$4ECC; + mmDP4_DP_SEC_TIMESTAMP =$4ECD; + mmDP4_DP_SEC_PACKET_CNTL =$4ECE; + mmDP4_DP_MSE_RATE_CNTL =$4ECF; + mmDP4_DP_MSE_RATE_UPDATE =$4ED1; + mmDP4_DP_MSE_SAT0 =$4ED2; + mmDP4_DP_MSE_SAT1 =$4ED3; + mmDP4_DP_MSE_SAT2 =$4ED4; + mmDP4_DP_MSE_SAT_UPDATE =$4ED5; + mmDP4_DP_MSE_LINK_TIMING =$4ED6; + mmDP4_DP_MSE_MISC_CNTL =$4ED7; + mmDP4_DP_TEST_DEBUG_INDEX =$4ED8; + mmDP4_DP_TEST_DEBUG_DATA =$4ED9; + mmDP4_DP_FE_TEST_DEBUG_INDEX =$4EDA; + mmDP4_DP_FE_TEST_DEBUG_DATA =$4EDB; + mmDIG5_DIG_FE_CNTL =$4F00; + mmDIG5_DIG_OUTPUT_CRC_CNTL =$4F01; + mmDIG5_DIG_OUTPUT_CRC_RESULT =$4F02; + mmDIG5_DIG_CLOCK_PATTERN =$4F03; + mmDIG5_DIG_TEST_PATTERN =$4F04; + mmDIG5_DIG_RANDOM_PATTERN_SEED =$4F05; + mmDIG5_DIG_FIFO_STATUS =$4F06; + mmDIG5_DIG_DISPCLK_SWITCH_CNTL =$4F07; + mmDIG5_DIG_DISPCLK_SWITCH_STATUS =$4F08; + mmDIG5_HDMI_CONTROL =$4F09; + mmDIG5_HDMI_STATUS =$4F0A; + mmDIG5_HDMI_AUDIO_PACKET_CONTROL =$4F0B; + mmDIG5_HDMI_ACR_PACKET_CONTROL =$4F0C; + mmDIG5_HDMI_VBI_PACKET_CONTROL =$4F0D; + mmDIG5_HDMI_INFOFRAME_CONTROL0 =$4F0E; + mmDIG5_HDMI_INFOFRAME_CONTROL1 =$4F0F; + mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 =$4F10; + mmDIG5_HDMI_GC =$4F13; + mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 =$4F14; + mmDIG5_AFMT_ISRC1_0 =$4F15; + mmDIG5_AFMT_ISRC1_1 =$4F16; + mmDIG5_AFMT_ISRC1_2 =$4F17; + mmDIG5_AFMT_ISRC1_3 =$4F18; + mmDIG5_AFMT_ISRC1_4 =$4F19; + mmDIG5_AFMT_ISRC2_0 =$4F1A; + mmDIG5_AFMT_ISRC2_1 =$4F1B; + mmDIG5_AFMT_ISRC2_2 =$4F1C; + mmDIG5_AFMT_ISRC2_3 =$4F1D; + mmDIG5_AFMT_AVI_INFO0 =$4F1E; + mmDIG5_AFMT_AVI_INFO1 =$4F1F; + mmDIG5_AFMT_AVI_INFO2 =$4F20; + mmDIG5_AFMT_AVI_INFO3 =$4F21; + mmDIG5_AFMT_MPEG_INFO0 =$4F22; + mmDIG5_AFMT_MPEG_INFO1 =$4F23; + mmDIG5_AFMT_GENERIC_HDR =$4F24; + mmDIG5_AFMT_GENERIC_0 =$4F25; + mmDIG5_AFMT_GENERIC_1 =$4F26; + mmDIG5_AFMT_GENERIC_2 =$4F27; + mmDIG5_AFMT_GENERIC_3 =$4F28; + mmDIG5_AFMT_GENERIC_4 =$4F29; + mmDIG5_AFMT_GENERIC_5 =$4F2A; + mmDIG5_AFMT_GENERIC_6 =$4F2B; + mmDIG5_AFMT_GENERIC_7 =$4F2C; + mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 =$4F2D; + mmDIG5_HDMI_ACR_32_0 =$4F2E; + mmDIG5_HDMI_ACR_32_1 =$4F2F; + mmDIG5_HDMI_ACR_44_0 =$4F30; + mmDIG5_HDMI_ACR_44_1 =$4F31; + mmDIG5_HDMI_ACR_48_0 =$4F32; + mmDIG5_HDMI_ACR_48_1 =$4F33; + mmDIG5_HDMI_ACR_STATUS_0 =$4F34; + mmDIG5_HDMI_ACR_STATUS_1 =$4F35; + mmDIG5_AFMT_AUDIO_INFO0 =$4F36; + mmDIG5_AFMT_AUDIO_INFO1 =$4F37; + mmDIG5_AFMT_60958_0 =$4F38; + mmDIG5_AFMT_60958_1 =$4F39; + mmDIG5_AFMT_AUDIO_CRC_CONTROL =$4F3A; + mmDIG5_AFMT_RAMP_CONTROL0 =$4F3B; + mmDIG5_AFMT_RAMP_CONTROL1 =$4F3C; + mmDIG5_AFMT_RAMP_CONTROL2 =$4F3D; + mmDIG5_AFMT_RAMP_CONTROL3 =$4F3E; + mmDIG5_AFMT_60958_2 =$4F3F; + mmDIG5_AFMT_AUDIO_CRC_RESULT =$4F40; + mmDIG5_AFMT_STATUS =$4F41; + mmDIG5_AFMT_AUDIO_PACKET_CONTROL =$4F42; + mmDIG5_AFMT_VBI_PACKET_CONTROL =$4F43; + mmDIG5_AFMT_INFOFRAME_CONTROL0 =$4F44; + mmDIG5_AFMT_AUDIO_SRC_CONTROL =$4F45; + mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL =$4F46; + mmDIG5_DIG_BE_CNTL =$4F47; + mmDIG5_DIG_BE_EN_CNTL =$4F48; + mmDIG5_TMDS_CNTL =$4F6B; + mmDIG5_TMDS_CONTROL_CHAR =$4F6C; + mmDIG5_TMDS_CONTROL0_FEEDBACK =$4F6D; + mmDIG5_TMDS_STEREOSYNC_CTL_SEL =$4F6E; + mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 =$4F6F; + mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 =$4F70; + mmDIG5_TMDS_DEBUG =$4F71; + mmDIG5_TMDS_CTL_BITS =$4F72; + mmDIG5_TMDS_DCBALANCER_CONTROL =$4F73; + mmDIG5_TMDS_CTL0_1_GEN_CNTL =$4F75; + mmDIG5_TMDS_CTL2_3_GEN_CNTL =$4F76; + mmDIG5_LVDS_DATA_CNTL =$4F78; + mmDIG5_DIG_LANE_ENABLE =$4F79; + mmDIG5_DIG_TEST_DEBUG_INDEX =$4F7A; + mmDIG5_DIG_TEST_DEBUG_DATA =$4F7B; + mmDIG5_DIG_FE_TEST_DEBUG_INDEX =$4F7C; + mmDIG5_DIG_FE_TEST_DEBUG_DATA =$4F7D; + mmDP5_DP_LINK_CNTL =$4FA0; + mmDP5_DP_PIXEL_FORMAT =$4FA1; + mmDP5_DP_MSA_COLORIMETRY =$4FA2; + mmDP5_DP_CONFIG =$4FA3; + mmDP5_DP_VID_STREAM_CNTL =$4FA4; + mmDP5_DP_STEER_FIFO =$4FA5; + mmDP5_DP_MSA_MISC =$4FA6; + mmDP5_DP_VID_TIMING =$4FA8; + mmDP5_DP_VID_N =$4FA9; + mmDP5_DP_VID_M =$4FAA; + mmDP5_DP_LINK_FRAMING_CNTL =$4FAB; + mmDP5_DP_HBR2_EYE_PATTERN =$4FAC; + mmDP5_DP_VID_MSA_VBID =$4FAD; + mmDP5_DP_VID_INTERRUPT_CNTL =$4FAE; + mmDP5_DP_DPHY_CNTL =$4FAF; + mmDP5_DP_DPHY_TRAINING_PATTERN_SEL =$4FB0; + mmDP5_DP_DPHY_SYM0 =$4FB1; + mmDP5_DP_DPHY_SYM1 =$4FB2; + mmDP5_DP_DPHY_SYM2 =$4FB3; + mmDP5_DP_DPHY_8B10B_CNTL =$4FB4; + mmDP5_DP_DPHY_PRBS_CNTL =$4FB5; + mmDP5_DP_DPHY_CRC_EN =$4FB7; + mmDP5_DP_DPHY_CRC_CNTL =$4FB8; + mmDP5_DP_DPHY_CRC_RESULT =$4FB9; + mmDP5_DP_DPHY_CRC_MST_CNTL =$4FBA; + mmDP5_DP_DPHY_CRC_MST_STATUS =$4FBB; + mmDP5_DP_DPHY_FAST_TRAINING =$4FBC; + mmDP5_DP_DPHY_FAST_TRAINING_STATUS =$4FBD; + mmDP5_DP_MSA_V_TIMING_OVERRIDE1 =$4FBE; + mmDP5_DP_MSA_V_TIMING_OVERRIDE2 =$4FBF; + mmDP5_DP_SEC_CNTL =$4FC3; + mmDP5_DP_SEC_CNTL1 =$4FC4; + mmDP5_DP_SEC_FRAMING1 =$4FC5; + mmDP5_DP_SEC_FRAMING2 =$4FC6; + mmDP5_DP_SEC_FRAMING3 =$4FC7; + mmDP5_DP_SEC_FRAMING4 =$4FC8; + mmDP5_DP_SEC_AUD_N =$4FC9; + mmDP5_DP_SEC_AUD_N_READBACK =$4FCA; + mmDP5_DP_SEC_AUD_M =$4FCB; + mmDP5_DP_SEC_AUD_M_READBACK =$4FCC; + mmDP5_DP_SEC_TIMESTAMP =$4FCD; + mmDP5_DP_SEC_PACKET_CNTL =$4FCE; + mmDP5_DP_MSE_RATE_CNTL =$4FCF; + mmDP5_DP_MSE_RATE_UPDATE =$4FD1; + mmDP5_DP_MSE_SAT0 =$4FD2; + mmDP5_DP_MSE_SAT1 =$4FD3; + mmDP5_DP_MSE_SAT2 =$4FD4; + mmDP5_DP_MSE_SAT_UPDATE =$4FD5; + mmDP5_DP_MSE_LINK_TIMING =$4FD6; + mmDP5_DP_MSE_MISC_CNTL =$4FD7; + mmDP5_DP_TEST_DEBUG_INDEX =$4FD8; + mmDP5_DP_TEST_DEBUG_DATA =$4FD9; + mmDP5_DP_FE_TEST_DEBUG_INDEX =$4FDA; + mmDP5_DP_FE_TEST_DEBUG_DATA =$4FDB; + mmDIG6_DIG_FE_CNTL =$5400; + mmDIG6_DIG_OUTPUT_CRC_CNTL =$5401; + mmDIG6_DIG_OUTPUT_CRC_RESULT =$5402; + mmDIG6_DIG_CLOCK_PATTERN =$5403; + mmDIG6_DIG_TEST_PATTERN =$5404; + mmDIG6_DIG_RANDOM_PATTERN_SEED =$5405; + mmDIG6_DIG_FIFO_STATUS =$5406; + mmDIG6_DIG_DISPCLK_SWITCH_CNTL =$5407; + mmDIG6_DIG_DISPCLK_SWITCH_STATUS =$5408; + mmDIG6_HDMI_CONTROL =$5409; + mmDIG6_HDMI_STATUS =$540A; + mmDIG6_HDMI_AUDIO_PACKET_CONTROL =$540B; + mmDIG6_HDMI_ACR_PACKET_CONTROL =$540C; + mmDIG6_HDMI_VBI_PACKET_CONTROL =$540D; + mmDIG6_HDMI_INFOFRAME_CONTROL0 =$540E; + mmDIG6_HDMI_INFOFRAME_CONTROL1 =$540F; + mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 =$5410; + mmDIG6_HDMI_GC =$5413; + mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 =$5414; + mmDIG6_AFMT_ISRC1_0 =$5415; + mmDIG6_AFMT_ISRC1_1 =$5416; + mmDIG6_AFMT_ISRC1_2 =$5417; + mmDIG6_AFMT_ISRC1_3 =$5418; + mmDIG6_AFMT_ISRC1_4 =$5419; + mmDIG6_AFMT_ISRC2_0 =$541A; + mmDIG6_AFMT_ISRC2_1 =$541B; + mmDIG6_AFMT_ISRC2_2 =$541C; + mmDIG6_AFMT_ISRC2_3 =$541D; + mmDIG6_AFMT_AVI_INFO0 =$541E; + mmDIG6_AFMT_AVI_INFO1 =$541F; + mmDIG6_AFMT_AVI_INFO2 =$5420; + mmDIG6_AFMT_AVI_INFO3 =$5421; + mmDIG6_AFMT_MPEG_INFO0 =$5422; + mmDIG6_AFMT_MPEG_INFO1 =$5423; + mmDIG6_AFMT_GENERIC_HDR =$5424; + mmDIG6_AFMT_GENERIC_0 =$5425; + mmDIG6_AFMT_GENERIC_1 =$5426; + mmDIG6_AFMT_GENERIC_2 =$5427; + mmDIG6_AFMT_GENERIC_3 =$5428; + mmDIG6_AFMT_GENERIC_4 =$5429; + mmDIG6_AFMT_GENERIC_5 =$542A; + mmDIG6_AFMT_GENERIC_6 =$542B; + mmDIG6_AFMT_GENERIC_7 =$542C; + mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 =$542D; + mmDIG6_HDMI_ACR_32_0 =$542E; + mmDIG6_HDMI_ACR_32_1 =$542F; + mmDIG6_HDMI_ACR_44_0 =$5430; + mmDIG6_HDMI_ACR_44_1 =$5431; + mmDIG6_HDMI_ACR_48_0 =$5432; + mmDIG6_HDMI_ACR_48_1 =$5433; + mmDIG6_HDMI_ACR_STATUS_0 =$5434; + mmDIG6_HDMI_ACR_STATUS_1 =$5435; + mmDIG6_AFMT_AUDIO_INFO0 =$5436; + mmDIG6_AFMT_AUDIO_INFO1 =$5437; + mmDIG6_AFMT_60958_0 =$5438; + mmDIG6_AFMT_60958_1 =$5439; + mmDIG6_AFMT_AUDIO_CRC_CONTROL =$543A; + mmDIG6_AFMT_RAMP_CONTROL0 =$543B; + mmDIG6_AFMT_RAMP_CONTROL1 =$543C; + mmDIG6_AFMT_RAMP_CONTROL2 =$543D; + mmDIG6_AFMT_RAMP_CONTROL3 =$543E; + mmDIG6_AFMT_60958_2 =$543F; + mmDIG6_AFMT_AUDIO_CRC_RESULT =$5440; + mmDIG6_AFMT_STATUS =$5441; + mmDIG6_AFMT_AUDIO_PACKET_CONTROL =$5442; + mmDIG6_AFMT_VBI_PACKET_CONTROL =$5443; + mmDIG6_AFMT_INFOFRAME_CONTROL0 =$5444; + mmDIG6_AFMT_AUDIO_SRC_CONTROL =$5445; + mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL =$5446; + mmDIG6_DIG_BE_CNTL =$5447; + mmDIG6_DIG_BE_EN_CNTL =$5448; + mmDIG6_TMDS_CNTL =$546B; + mmDIG6_TMDS_CONTROL_CHAR =$546C; + mmDIG6_TMDS_CONTROL0_FEEDBACK =$546D; + mmDIG6_TMDS_STEREOSYNC_CTL_SEL =$546E; + mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 =$546F; + mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 =$5470; + mmDIG6_TMDS_DEBUG =$5471; + mmDIG6_TMDS_CTL_BITS =$5472; + mmDIG6_TMDS_DCBALANCER_CONTROL =$5473; + mmDIG6_TMDS_CTL0_1_GEN_CNTL =$5475; + mmDIG6_TMDS_CTL2_3_GEN_CNTL =$5476; + mmDIG6_LVDS_DATA_CNTL =$5478; + mmDIG6_DIG_LANE_ENABLE =$5479; + mmDIG6_DIG_TEST_DEBUG_INDEX =$547A; + mmDIG6_DIG_TEST_DEBUG_DATA =$547B; + mmDIG6_DIG_FE_TEST_DEBUG_INDEX =$547C; + mmDIG6_DIG_FE_TEST_DEBUG_DATA =$547D; + mmDP6_DP_LINK_CNTL =$54A0; + mmDP6_DP_PIXEL_FORMAT =$54A1; + mmDP6_DP_MSA_COLORIMETRY =$54A2; + mmDP6_DP_CONFIG =$54A3; + mmDP6_DP_VID_STREAM_CNTL =$54A4; + mmDP6_DP_STEER_FIFO =$54A5; + mmDP6_DP_MSA_MISC =$54A6; + mmDP6_DP_VID_TIMING =$54A8; + mmDP6_DP_VID_N =$54A9; + mmDP6_DP_VID_M =$54AA; + mmDP6_DP_LINK_FRAMING_CNTL =$54AB; + mmDP6_DP_HBR2_EYE_PATTERN =$54AC; + mmDP6_DP_VID_MSA_VBID =$54AD; + mmDP6_DP_VID_INTERRUPT_CNTL =$54AE; + mmDP6_DP_DPHY_CNTL =$54AF; + mmDP6_DP_DPHY_TRAINING_PATTERN_SEL =$54B0; + mmDP6_DP_DPHY_SYM0 =$54B1; + mmDP6_DP_DPHY_SYM1 =$54B2; + mmDP6_DP_DPHY_SYM2 =$54B3; + mmDP6_DP_DPHY_8B10B_CNTL =$54B4; + mmDP6_DP_DPHY_PRBS_CNTL =$54B5; + mmDP6_DP_DPHY_CRC_EN =$54B7; + mmDP6_DP_DPHY_CRC_CNTL =$54B8; + mmDP6_DP_DPHY_CRC_RESULT =$54B9; + mmDP6_DP_DPHY_CRC_MST_CNTL =$54BA; + mmDP6_DP_DPHY_CRC_MST_STATUS =$54BB; + mmDP6_DP_DPHY_FAST_TRAINING =$54BC; + mmDP6_DP_DPHY_FAST_TRAINING_STATUS =$54BD; + mmDP6_DP_MSA_V_TIMING_OVERRIDE1 =$54BE; + mmDP6_DP_MSA_V_TIMING_OVERRIDE2 =$54BF; + mmDP6_DP_SEC_CNTL =$54C3; + mmDP6_DP_SEC_CNTL1 =$54C4; + mmDP6_DP_SEC_FRAMING1 =$54C5; + mmDP6_DP_SEC_FRAMING2 =$54C6; + mmDP6_DP_SEC_FRAMING3 =$54C7; + mmDP6_DP_SEC_FRAMING4 =$54C8; + mmDP6_DP_SEC_AUD_N =$54C9; + mmDP6_DP_SEC_AUD_N_READBACK =$54CA; + mmDP6_DP_SEC_AUD_M =$54CB; + mmDP6_DP_SEC_AUD_M_READBACK =$54CC; + mmDP6_DP_SEC_TIMESTAMP =$54CD; + mmDP6_DP_SEC_PACKET_CNTL =$54CE; + mmDP6_DP_MSE_RATE_CNTL =$54CF; + mmDP6_DP_MSE_RATE_UPDATE =$54D1; + mmDP6_DP_MSE_SAT0 =$54D2; + mmDP6_DP_MSE_SAT1 =$54D3; + mmDP6_DP_MSE_SAT2 =$54D4; + mmDP6_DP_MSE_SAT_UPDATE =$54D5; + mmDP6_DP_MSE_LINK_TIMING =$54D6; + mmDP6_DP_MSE_MISC_CNTL =$54D7; + mmDP6_DP_TEST_DEBUG_INDEX =$54D8; + mmDP6_DP_TEST_DEBUG_DATA =$54D9; + mmDP6_DP_FE_TEST_DEBUG_INDEX =$54DA; + mmDP6_DP_FE_TEST_DEBUG_DATA =$54DB; + mmDC_PERFMON10_PERFCOUNTER_CNTL =$59A0; + mmDC_PERFMON10_PERFCOUNTER_STATE =$59A1; + mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC =$59A2; + mmDC_PERFMON10_PERFMON_CNTL =$59A3; + mmDC_PERFMON10_PERFMON_CVALUE_LOW =$59A4; + mmDC_PERFMON10_PERFMON_HI =$59A5; + mmDC_PERFMON10_PERFMON_LOW =$59A6; + mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX =$59A7; + mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA =$59A8; + mmDC_PERFMON10_PERFMON_CNTL2 =$59AA; + mmAZF0STREAM8_AZALIA_STREAM_INDEX =$59C0; + mmAZF0STREAM8_AZALIA_STREAM_DATA =$59C1; + mmAZF0STREAM9_AZALIA_STREAM_INDEX =$59C2; + mmAZF0STREAM9_AZALIA_STREAM_DATA =$59C3; + mmAZF0STREAM10_AZALIA_STREAM_INDEX =$59C4; + mmAZF0STREAM10_AZALIA_STREAM_DATA =$59C5; + mmAZF0STREAM11_AZALIA_STREAM_INDEX =$59C6; + mmAZF0STREAM11_AZALIA_STREAM_DATA =$59C7; + mmAZF0STREAM12_AZALIA_STREAM_INDEX =$59C8; + mmAZF0STREAM12_AZALIA_STREAM_DATA =$59C9; + mmAZF0STREAM13_AZALIA_STREAM_INDEX =$59CA; + mmAZF0STREAM13_AZALIA_STREAM_DATA =$59CB; + mmAZF0STREAM14_AZALIA_STREAM_INDEX =$59CC; + mmAZF0STREAM14_AZALIA_STREAM_DATA =$59CD; + mmAZF0STREAM15_AZALIA_STREAM_INDEX =$59CE; + mmAZF0STREAM15_AZALIA_STREAM_DATA =$59CF; + mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX =$59D4; + mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59D5; + mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59D8; + mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59D9; + mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59DC; + mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59DD; + mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E0; + mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E1; + mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E4; + mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E5; + mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59E8; + mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59E9; + mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59EC; + mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59ED; + mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=$59F0; + mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA =$59F1; + mmDCRX_PHY_MACRO_CNTL_RESERVED0 =$5A84; + mmDCRX_PHY_MACRO_CNTL_RESERVED1 =$5A85; + mmDCRX_PHY_MACRO_CNTL_RESERVED2 =$5A86; + mmDCRX_PHY_MACRO_CNTL_RESERVED3 =$5A87; + mmDCRX_PHY_MACRO_CNTL_RESERVED4 =$5A88; + mmDCRX_PHY_MACRO_CNTL_RESERVED5 =$5A89; + mmDCRX_PHY_MACRO_CNTL_RESERVED6 =$5A8A; + mmDCRX_PHY_MACRO_CNTL_RESERVED7 =$5A8B; + mmDCRX_PHY_MACRO_CNTL_RESERVED8 =$5A8C; + mmDCRX_PHY_MACRO_CNTL_RESERVED9 =$5A8D; + mmDCRX_PHY_MACRO_CNTL_RESERVED10 =$5A8E; + mmDCRX_PHY_MACRO_CNTL_RESERVED11 =$5A8F; + mmDCRX_PHY_MACRO_CNTL_RESERVED12 =$5A90; + mmDCRX_PHY_MACRO_CNTL_RESERVED13 =$5A91; + mmDCRX_PHY_MACRO_CNTL_RESERVED14 =$5A92; + mmDCRX_PHY_MACRO_CNTL_RESERVED15 =$5A93; + mmDCRX_PHY_MACRO_CNTL_RESERVED16 =$5A94; + mmDCRX_PHY_MACRO_CNTL_RESERVED17 =$5A95; + mmDCRX_PHY_MACRO_CNTL_RESERVED18 =$5A96; + mmDCRX_PHY_MACRO_CNTL_RESERVED19 =$5A97; + mmDCRX_PHY_MACRO_CNTL_RESERVED20 =$5A98; + mmDCRX_PHY_MACRO_CNTL_RESERVED21 =$5A99; + mmDCRX_PHY_MACRO_CNTL_RESERVED22 =$5A9A; + mmDCRX_PHY_MACRO_CNTL_RESERVED23 =$5A9B; + mmDCRX_PHY_MACRO_CNTL_RESERVED24 =$5A9C; + mmDCRX_PHY_MACRO_CNTL_RESERVED25 =$5A9D; + mmDCRX_PHY_MACRO_CNTL_RESERVED26 =$5A9E; + mmDCRX_PHY_MACRO_CNTL_RESERVED27 =$5A9F; + mmDCRX_PHY_MACRO_CNTL_RESERVED28 =$5AA0; + mmDCRX_PHY_MACRO_CNTL_RESERVED29 =$5AA1; + mmDCRX_PHY_MACRO_CNTL_RESERVED30 =$5AA2; + mmDCRX_PHY_MACRO_CNTL_RESERVED31 =$5AA3; + mmDCRX_PHY_MACRO_CNTL_RESERVED32 =$5AA4; + mmDCRX_PHY_MACRO_CNTL_RESERVED33 =$5AA5; + mmDCRX_PHY_MACRO_CNTL_RESERVED34 =$5AA6; + mmDCRX_PHY_MACRO_CNTL_RESERVED35 =$5AA7; + mmDCRX_PHY_MACRO_CNTL_RESERVED36 =$5AA8; + mmDCRX_PHY_MACRO_CNTL_RESERVED37 =$5AA9; + mmDCRX_PHY_MACRO_CNTL_RESERVED38 =$5AAA; + mmDCRX_PHY_MACRO_CNTL_RESERVED39 =$5AAB; + mmDCRX_PHY_MACRO_CNTL_RESERVED40 =$5AAC; + mmDCRX_PHY_MACRO_CNTL_RESERVED41 =$5AAD; + mmDCRX_PHY_MACRO_CNTL_RESERVED42 =$5AAE; + mmDCRX_PHY_MACRO_CNTL_RESERVED43 =$5AAF; + mmDCRX_PHY_MACRO_CNTL_RESERVED44 =$5AB0; + mmDCRX_PHY_MACRO_CNTL_RESERVED45 =$5AB1; + mmDCRX_PHY_MACRO_CNTL_RESERVED46 =$5AB2; + mmDCRX_PHY_MACRO_CNTL_RESERVED47 =$5AB3; + mmDCRX_PHY_MACRO_CNTL_RESERVED48 =$5AB4; + mmDCRX_PHY_MACRO_CNTL_RESERVED49 =$5AB5; + mmDCRX_PHY_MACRO_CNTL_RESERVED50 =$5AB6; + mmDCRX_PHY_MACRO_CNTL_RESERVED51 =$5AB7; + mmDCRX_PHY_MACRO_CNTL_RESERVED52 =$5AB8; + mmDCRX_PHY_MACRO_CNTL_RESERVED53 =$5AB9; + mmDCRX_PHY_MACRO_CNTL_RESERVED54 =$5ABA; + mmDCRX_PHY_MACRO_CNTL_RESERVED55 =$5ABB; + mmDCRX_PHY_MACRO_CNTL_RESERVED56 =$5ABC; + mmDCRX_PHY_MACRO_CNTL_RESERVED57 =$5ABD; + mmDCRX_PHY_MACRO_CNTL_RESERVED58 =$5ABE; + mmDCRX_PHY_MACRO_CNTL_RESERVED59 =$5ABF; + mmDCRX_PHY_MACRO_CNTL_RESERVED60 =$5AC0; + mmDCRX_PHY_MACRO_CNTL_RESERVED61 =$5AC1; + mmDCRX_PHY_MACRO_CNTL_RESERVED62 =$5AC2; + mmDCRX_PHY_MACRO_CNTL_RESERVED63 =$5AC3; + mmDCRX_PHY_MACRO_CNTL_RESERVED64 =$5AC4; + mmDCRX_PHY_MACRO_CNTL_RESERVED65 =$5AC5; + mmDCRX_PHY_MACRO_CNTL_RESERVED66 =$5AC6; + mmDCRX_PHY_MACRO_CNTL_RESERVED67 =$5AC7; + mmDCRX_PHY_MACRO_CNTL_RESERVED68 =$5AC8; + mmDCRX_PHY_MACRO_CNTL_RESERVED69 =$5AC9; + mmDCRX_PHY_MACRO_CNTL_RESERVED70 =$5ACA; + mmDCRX_PHY_MACRO_CNTL_RESERVED71 =$5ACB; + mmDCRX_PHY_MACRO_CNTL_RESERVED72 =$5ACC; + mmDCRX_PHY_MACRO_CNTL_RESERVED73 =$5ACD; + mmDCRX_PHY_MACRO_CNTL_RESERVED74 =$5ACE; + mmDCRX_PHY_MACRO_CNTL_RESERVED75 =$5ACF; + mmDCRX_PHY_MACRO_CNTL_RESERVED76 =$5AD0; + mmDCRX_PHY_MACRO_CNTL_RESERVED77 =$5AD1; + mmDCRX_PHY_MACRO_CNTL_RESERVED78 =$5AD2; + mmDCRX_PHY_MACRO_CNTL_RESERVED79 =$5AD3; + mmDCRX_PHY_MACRO_CNTL_RESERVED80 =$5AD4; + mmDCRX_PHY_MACRO_CNTL_RESERVED81 =$5AD5; + mmDCRX_PHY_MACRO_CNTL_RESERVED82 =$5AD6; + mmDCRX_PHY_MACRO_CNTL_RESERVED83 =$5AD7; + mmDCRX_PHY_MACRO_CNTL_RESERVED84 =$5AD8; + mmDCRX_PHY_MACRO_CNTL_RESERVED85 =$5AD9; + mmDCRX_PHY_MACRO_CNTL_RESERVED86 =$5ADA; + mmDCRX_PHY_MACRO_CNTL_RESERVED87 =$5ADB; + mmDCRX_PHY_MACRO_CNTL_RESERVED88 =$5ADC; + mmDCRX_PHY_MACRO_CNTL_RESERVED89 =$5ADD; + mmDCRX_PHY_MACRO_CNTL_RESERVED90 =$5ADE; + mmDCRX_PHY_MACRO_CNTL_RESERVED91 =$5ADF; + mmDCRX_PHY_MACRO_CNTL_RESERVED92 =$5AE0; + mmDCRX_PHY_MACRO_CNTL_RESERVED93 =$5AE1; + mmDCRX_PHY_MACRO_CNTL_RESERVED94 =$5AE2; + mmDCRX_PHY_MACRO_CNTL_RESERVED95 =$5AE3; + mmDCRX_PHY_MACRO_CNTL_RESERVED96 =$5AE4; + mmDCRX_PHY_MACRO_CNTL_RESERVED97 =$5AE5; + mmDCRX_PHY_MACRO_CNTL_RESERVED98 =$5AE6; + mmDCRX_PHY_MACRO_CNTL_RESERVED99 =$5AE7; + mmDCRX_PHY_MACRO_CNTL_RESERVED100 =$5AE8; + mmDCRX_PHY_MACRO_CNTL_RESERVED101 =$5AE9; + mmDCRX_PHY_MACRO_CNTL_RESERVED102 =$5AEA; + mmDCRX_PHY_MACRO_CNTL_RESERVED103 =$5AEB; + mmDCRX_PHY_MACRO_CNTL_RESERVED104 =$5AEC; + mmDCRX_PHY_MACRO_CNTL_RESERVED105 =$5AED; + mmDCRX_PHY_MACRO_CNTL_RESERVED106 =$5AEE; + mmDCRX_PHY_MACRO_CNTL_RESERVED107 =$5AEF; + mmDCRX_PHY_MACRO_CNTL_RESERVED108 =$5AF0; + mmDCRX_PHY_MACRO_CNTL_RESERVED109 =$5AF1; + mmDCRX_PHY_MACRO_CNTL_RESERVED110 =$5AF2; + mmDCRX_PHY_MACRO_CNTL_RESERVED111 =$5AF3; + mmDCRX_PHY_MACRO_CNTL_RESERVED112 =$5AF4; + mmDCRX_PHY_MACRO_CNTL_RESERVED113 =$5AF5; + mmDCRX_PHY_MACRO_CNTL_RESERVED114 =$5AF6; + mmDCRX_PHY_MACRO_CNTL_RESERVED115 =$5AF7; + mmDCRX_PHY_MACRO_CNTL_RESERVED116 =$5AF8; + mmDCRX_PHY_MACRO_CNTL_RESERVED117 =$5AF9; + mmDCRX_PHY_MACRO_CNTL_RESERVED118 =$5AFA; + mmDCRX_PHY_MACRO_CNTL_RESERVED119 =$5AFB; + mmDCRX_PHY_MACRO_CNTL_RESERVED120 =$5AFC; + mmDCRX_PHY_MACRO_CNTL_RESERVED121 =$5AFD; + mmDCRX_PHY_MACRO_CNTL_RESERVED122 =$5AFE; + mmDCRX_PHY_MACRO_CNTL_RESERVED123 =$5AFF; + mmDCRX_PHY_MACRO_CNTL_RESERVED124 =$5B00; + mmDCRX_PHY_MACRO_CNTL_RESERVED125 =$5B01; + mmDCRX_PHY_MACRO_CNTL_RESERVED126 =$5B02; + mmDCRX_PHY_MACRO_CNTL_RESERVED127 =$5B03; + mmDCRX_PHY_MACRO_CNTL_RESERVED128 =$5B04; + mmDCRX_PHY_MACRO_CNTL_RESERVED129 =$5B05; + mmDCRX_PHY_MACRO_CNTL_RESERVED130 =$5B06; + mmDCRX_PHY_MACRO_CNTL_RESERVED131 =$5B07; + mmDCRX_PHY_MACRO_CNTL_RESERVED132 =$5B08; + mmDCRX_PHY_MACRO_CNTL_RESERVED133 =$5B09; + mmDCRX_PHY_MACRO_CNTL_RESERVED134 =$5B0A; + mmDCRX_PHY_MACRO_CNTL_RESERVED135 =$5B0B; + mmDCRX_PHY_MACRO_CNTL_RESERVED136 =$5B0C; + mmDCRX_PHY_MACRO_CNTL_RESERVED137 =$5B0D; + mmDCRX_PHY_MACRO_CNTL_RESERVED138 =$5B0E; + mmDCRX_PHY_MACRO_CNTL_RESERVED139 =$5B0F; + mmDCRX_PHY_MACRO_CNTL_RESERVED140 =$5B10; + mmDCRX_PHY_MACRO_CNTL_RESERVED141 =$5B11; + mmDCRX_PHY_MACRO_CNTL_RESERVED142 =$5B12; + mmDCRX_PHY_MACRO_CNTL_RESERVED143 =$5B13; + mmDCRX_PHY_MACRO_CNTL_RESERVED144 =$5B14; + mmDCRX_PHY_MACRO_CNTL_RESERVED145 =$5B15; + mmDCRX_PHY_MACRO_CNTL_RESERVED146 =$5B16; + mmDCRX_PHY_MACRO_CNTL_RESERVED147 =$5B17; + mmDCRX_PHY_MACRO_CNTL_RESERVED148 =$5B18; + mmDCRX_PHY_MACRO_CNTL_RESERVED149 =$5B19; + mmDCRX_PHY_MACRO_CNTL_RESERVED150 =$5B1A; + mmDCRX_PHY_MACRO_CNTL_RESERVED151 =$5B1B; + mmDCRX_PHY_MACRO_CNTL_RESERVED152 =$5B1C; + mmDCRX_PHY_MACRO_CNTL_RESERVED153 =$5B1D; + mmDCRX_PHY_MACRO_CNTL_RESERVED154 =$5B1E; + mmDCRX_PHY_MACRO_CNTL_RESERVED155 =$5B1F; + mmDCRX_PHY_MACRO_CNTL_RESERVED156 =$5B20; + mmDCRX_PHY_MACRO_CNTL_RESERVED157 =$5B21; + mmDCRX_PHY_MACRO_CNTL_RESERVED158 =$5B22; + mmDCRX_PHY_MACRO_CNTL_RESERVED159 =$5B23; + mmDCRX_PHY_MACRO_CNTL_RESERVED160 =$5B24; + mmDCRX_PHY_MACRO_CNTL_RESERVED161 =$5B25; + mmDCRX_PHY_MACRO_CNTL_RESERVED162 =$5B26; + mmDCRX_PHY_MACRO_CNTL_RESERVED163 =$5B27; + mmDCRX_PHY_MACRO_CNTL_RESERVED164 =$5B28; + mmDCRX_PHY_MACRO_CNTL_RESERVED165 =$5B29; + mmDCRX_PHY_MACRO_CNTL_RESERVED166 =$5B2A; + mmDCRX_PHY_MACRO_CNTL_RESERVED167 =$5B2B; + mmDCRX_PHY_MACRO_CNTL_RESERVED168 =$5B2C; + mmDCRX_PHY_MACRO_CNTL_RESERVED169 =$5B2D; + mmDCRX_PHY_MACRO_CNTL_RESERVED170 =$5B2E; + mmDCRX_PHY_MACRO_CNTL_RESERVED171 =$5B2F; + mmDCRX_PHY_MACRO_CNTL_RESERVED172 =$5B30; + mmDCRX_PHY_MACRO_CNTL_RESERVED173 =$5B31; + mmDCRX_PHY_MACRO_CNTL_RESERVED174 =$5B32; + mmDCRX_PHY_MACRO_CNTL_RESERVED175 =$5B33; + mmDCRX_PHY_MACRO_CNTL_RESERVED176 =$5B34; + mmDCRX_PHY_MACRO_CNTL_RESERVED177 =$5B35; + mmDCRX_PHY_MACRO_CNTL_RESERVED178 =$5B36; + mmDCRX_PHY_MACRO_CNTL_RESERVED179 =$5B37; + mmDCRX_PHY_MACRO_CNTL_RESERVED180 =$5B38; + mmDCRX_PHY_MACRO_CNTL_RESERVED181 =$5B39; + mmDCRX_PHY_MACRO_CNTL_RESERVED182 =$5B3A; + mmDCRX_PHY_MACRO_CNTL_RESERVED183 =$5B3B; + mmDCRX_PHY_MACRO_CNTL_RESERVED184 =$5B3C; + mmDCRX_PHY_MACRO_CNTL_RESERVED185 =$5B3D; + mmDCRX_PHY_MACRO_CNTL_RESERVED186 =$5B3E; + mmDCRX_PHY_MACRO_CNTL_RESERVED187 =$5B3F; + mmDCRX_PHY_MACRO_CNTL_RESERVED188 =$5B40; + mmDCRX_PHY_MACRO_CNTL_RESERVED189 =$5B41; + mmDCRX_PHY_MACRO_CNTL_RESERVED190 =$5B42; + mmDCRX_PHY_MACRO_CNTL_RESERVED191 =$5B43; + mmDCRX_PHY_MACRO_CNTL_RESERVED192 =$5B44; + mmDCRX_PHY_MACRO_CNTL_RESERVED193 =$5B45; + mmDCRX_PHY_MACRO_CNTL_RESERVED194 =$5B46; + mmDCRX_PHY_MACRO_CNTL_RESERVED195 =$5B47; + mmDCRX_PHY_MACRO_CNTL_RESERVED196 =$5B48; + mmDCRX_PHY_MACRO_CNTL_RESERVED197 =$5B49; + mmDCRX_PHY_MACRO_CNTL_RESERVED198 =$5B4A; + mmDCRX_PHY_MACRO_CNTL_RESERVED199 =$5B4B; + mmDCRX_PHY_MACRO_CNTL_RESERVED200 =$5B4C; + mmDCRX_PHY_MACRO_CNTL_RESERVED201 =$5B4D; + mmDCRX_PHY_MACRO_CNTL_RESERVED202 =$5B4E; + mmDCRX_PHY_MACRO_CNTL_RESERVED203 =$5B4F; + mmDCRX_PHY_MACRO_CNTL_RESERVED204 =$5B50; + mmDCRX_PHY_MACRO_CNTL_RESERVED205 =$5B51; + mmDCRX_PHY_MACRO_CNTL_RESERVED206 =$5B52; + mmDCRX_PHY_MACRO_CNTL_RESERVED207 =$5B53; + mmDCRX_PHY_MACRO_CNTL_RESERVED208 =$5B54; + mmDCRX_PHY_MACRO_CNTL_RESERVED209 =$5B55; + mmDCRX_PHY_MACRO_CNTL_RESERVED210 =$5B56; + mmDCRX_PHY_MACRO_CNTL_RESERVED211 =$5B57; + mmDCRX_PHY_MACRO_CNTL_RESERVED212 =$5B58; + mmDCRX_PHY_MACRO_CNTL_RESERVED213 =$5B59; + mmDCRX_PHY_MACRO_CNTL_RESERVED214 =$5B5A; + mmDCRX_PHY_MACRO_CNTL_RESERVED215 =$5B5B; + mmDCRX_PHY_MACRO_CNTL_RESERVED216 =$5B5C; + mmDCRX_PHY_MACRO_CNTL_RESERVED217 =$5B5D; + mmDCRX_PHY_MACRO_CNTL_RESERVED218 =$5B5E; + mmDCRX_PHY_MACRO_CNTL_RESERVED219 =$5B5F; + mmDCRX_PHY_MACRO_CNTL_RESERVED220 =$5B60; + mmDCRX_PHY_MACRO_CNTL_RESERVED221 =$5B61; + mmDCRX_PHY_MACRO_CNTL_RESERVED222 =$5B62; + mmDCRX_PHY_MACRO_CNTL_RESERVED223 =$5B63; + mmDCRX_PHY_MACRO_CNTL_RESERVED224 =$5B64; + mmDCRX_PHY_MACRO_CNTL_RESERVED225 =$5B65; + mmDCRX_PHY_MACRO_CNTL_RESERVED226 =$5B66; + mmDCRX_PHY_MACRO_CNTL_RESERVED227 =$5B67; + mmDCRX_PHY_MACRO_CNTL_RESERVED228 =$5B68; + mmDCRX_PHY_MACRO_CNTL_RESERVED229 =$5B69; + mmDCRX_PHY_MACRO_CNTL_RESERVED230 =$5B6A; + mmDCRX_PHY_MACRO_CNTL_RESERVED231 =$5B6B; + mmDCRX_PHY_MACRO_CNTL_RESERVED232 =$5B6C; + mmDCRX_PHY_MACRO_CNTL_RESERVED233 =$5B6D; + mmDCRX_PHY_MACRO_CNTL_RESERVED234 =$5B6E; + mmDCRX_PHY_MACRO_CNTL_RESERVED235 =$5B6F; + mmDCRX_PHY_MACRO_CNTL_RESERVED236 =$5B70; + mmDCRX_PHY_MACRO_CNTL_RESERVED237 =$5B71; + mmDCRX_PHY_MACRO_CNTL_RESERVED238 =$5B72; + mmDCRX_PHY_MACRO_CNTL_RESERVED239 =$5B73; + mmDCRX_PHY_MACRO_CNTL_RESERVED240 =$5B74; + mmDCRX_PHY_MACRO_CNTL_RESERVED241 =$5B75; + mmDCRX_PHY_MACRO_CNTL_RESERVED242 =$5B76; + mmDCRX_PHY_MACRO_CNTL_RESERVED243 =$5B77; + mmDCRX_PHY_MACRO_CNTL_RESERVED244 =$5B78; + mmDCRX_PHY_MACRO_CNTL_RESERVED245 =$5B79; + mmDCRX_PHY_MACRO_CNTL_RESERVED246 =$5B7A; + mmDCRX_PHY_MACRO_CNTL_RESERVED247 =$5B7B; + mmDCRX_PHY_MACRO_CNTL_RESERVED248 =$5B7C; + mmDCRX_PHY_MACRO_CNTL_RESERVED249 =$5B7D; + mmDCRX_PHY_MACRO_CNTL_RESERVED250 =$5B7E; + mmDCRX_PHY_MACRO_CNTL_RESERVED251 =$5B7F; + mmDCRX_PHY_MACRO_CNTL_RESERVED252 =$5B80; + mmDCRX_PHY_MACRO_CNTL_RESERVED253 =$5B81; + mmDCRX_PHY_MACRO_CNTL_RESERVED254 =$5B82; + mmDCRX_PHY_MACRO_CNTL_RESERVED255 =$5B83; + mmDCRX_PHY_MACRO_CNTL_RESERVED256 =$5B84; + mmDCRX_PHY_MACRO_CNTL_RESERVED257 =$5B85; + mmDCRX_PHY_MACRO_CNTL_RESERVED258 =$5B86; + mmDCRX_PHY_MACRO_CNTL_RESERVED259 =$5B87; + mmDCRX_PHY_MACRO_CNTL_RESERVED260 =$5B88; + mmDCRX_PHY_MACRO_CNTL_RESERVED261 =$5B89; + mmDCRX_PHY_MACRO_CNTL_RESERVED262 =$5B8A; + mmDCRX_PHY_MACRO_CNTL_RESERVED263 =$5B8B; + mmDCRX_PHY_MACRO_CNTL_RESERVED264 =$5B8C; + mmDCRX_PHY_MACRO_CNTL_RESERVED265 =$5B8D; + mmDCRX_PHY_MACRO_CNTL_RESERVED266 =$5B8E; + mmDCRX_PHY_MACRO_CNTL_RESERVED267 =$5B8F; + mmDCRX_PHY_MACRO_CNTL_RESERVED268 =$5B90; + mmDCRX_PHY_MACRO_CNTL_RESERVED269 =$5B91; + mmDCRX_PHY_MACRO_CNTL_RESERVED270 =$5B92; + mmDCRX_PHY_MACRO_CNTL_RESERVED271 =$5B93; + mmDCRX_PHY_MACRO_CNTL_RESERVED272 =$5B94; + mmDCRX_PHY_MACRO_CNTL_RESERVED273 =$5B95; + mmDCRX_PHY_MACRO_CNTL_RESERVED274 =$5B96; + mmDCRX_PHY_MACRO_CNTL_RESERVED275 =$5B97; + mmDCRX_PHY_MACRO_CNTL_RESERVED276 =$5B98; + mmDCRX_PHY_MACRO_CNTL_RESERVED277 =$5B99; + mmDCRX_PHY_MACRO_CNTL_RESERVED278 =$5B9A; + mmDCRX_PHY_MACRO_CNTL_RESERVED279 =$5B9B; + mmDCRX_PHY_MACRO_CNTL_RESERVED280 =$5B9C; + mmDCRX_PHY_MACRO_CNTL_RESERVED281 =$5B9D; + mmDCRX_PHY_MACRO_CNTL_RESERVED282 =$5B9E; + mmDCRX_PHY_MACRO_CNTL_RESERVED283 =$5B9F; + mmDCRX_PHY_MACRO_CNTL_RESERVED284 =$5BA0; + mmDCRX_PHY_MACRO_CNTL_RESERVED285 =$5BA1; + mmDCRX_PHY_MACRO_CNTL_RESERVED286 =$5BA2; + mmDCRX_PHY_MACRO_CNTL_RESERVED287 =$5BA3; + mmDCRX_PHY_MACRO_CNTL_RESERVED288 =$5BA4; + mmDCRX_PHY_MACRO_CNTL_RESERVED289 =$5BA5; + mmDCRX_PHY_MACRO_CNTL_RESERVED290 =$5BA6; + mmDCRX_PHY_MACRO_CNTL_RESERVED291 =$5BA7; + mmDCRX_PHY_MACRO_CNTL_RESERVED292 =$5BA8; + mmDCRX_PHY_MACRO_CNTL_RESERVED293 =$5BA9; + mmDCRX_PHY_MACRO_CNTL_RESERVED294 =$5BAA; + mmDCRX_PHY_MACRO_CNTL_RESERVED295 =$5BAB; + mmDCRX_PHY_MACRO_CNTL_RESERVED296 =$5BAC; + mmDCRX_PHY_MACRO_CNTL_RESERVED297 =$5BAD; + mmDCRX_PHY_MACRO_CNTL_RESERVED298 =$5BAE; + mmDCRX_PHY_MACRO_CNTL_RESERVED299 =$5BAF; + mmDCRX_PHY_MACRO_CNTL_RESERVED300 =$5BB0; + mmDCRX_PHY_MACRO_CNTL_RESERVED301 =$5BB1; + mmDCRX_PHY_MACRO_CNTL_RESERVED302 =$5BB2; + mmDCRX_PHY_MACRO_CNTL_RESERVED303 =$5BB3; + mmDCRX_PHY_MACRO_CNTL_RESERVED304 =$5BB4; + mmDCRX_PHY_MACRO_CNTL_RESERVED305 =$5BB5; + mmDCRX_PHY_MACRO_CNTL_RESERVED306 =$5BB6; + mmDCRX_PHY_MACRO_CNTL_RESERVED307 =$5BB7; + mmDCRX_PHY_MACRO_CNTL_RESERVED308 =$5BB8; + mmDCRX_PHY_MACRO_CNTL_RESERVED309 =$5BB9; + mmDCRX_PHY_MACRO_CNTL_RESERVED310 =$5BBA; + mmDCRX_PHY_MACRO_CNTL_RESERVED311 =$5BBB; + mmDCRX_PHY_MACRO_CNTL_RESERVED312 =$5BBC; + mmDCRX_PHY_MACRO_CNTL_RESERVED313 =$5BBD; + mmDCRX_PHY_MACRO_CNTL_RESERVED314 =$5BBE; + mmDCRX_PHY_MACRO_CNTL_RESERVED315 =$5BBF; + mmDCRX_PHY_MACRO_CNTL_RESERVED316 =$5BC0; + mmDCRX_PHY_MACRO_CNTL_RESERVED317 =$5BC1; + mmDCRX_PHY_MACRO_CNTL_RESERVED318 =$5BC2; + mmDCRX_PHY_MACRO_CNTL_RESERVED319 =$5BC3; + mmDCRX_PHY_MACRO_CNTL_RESERVED320 =$5BC4; + mmDCRX_PHY_MACRO_CNTL_RESERVED321 =$5BC5; + mmDCRX_PHY_MACRO_CNTL_RESERVED322 =$5BC6; + mmDCRX_PHY_MACRO_CNTL_RESERVED323 =$5BC7; + mmDCRX_PHY_MACRO_CNTL_RESERVED324 =$5BC8; + mmDCRX_PHY_MACRO_CNTL_RESERVED325 =$5BC9; + mmDCRX_PHY_MACRO_CNTL_RESERVED326 =$5BCA; + mmDCRX_PHY_MACRO_CNTL_RESERVED327 =$5BCB; + mmDCRX_PHY_MACRO_CNTL_RESERVED328 =$5BCC; + mmDCRX_PHY_MACRO_CNTL_RESERVED329 =$5BCD; + mmDCRX_PHY_MACRO_CNTL_RESERVED330 =$5BCE; + mmDCRX_PHY_MACRO_CNTL_RESERVED331 =$5BCF; + mmDCRX_PHY_MACRO_CNTL_RESERVED332 =$5BD0; + mmDCRX_PHY_MACRO_CNTL_RESERVED333 =$5BD1; + mmDCRX_PHY_MACRO_CNTL_RESERVED334 =$5BD2; + mmDCRX_PHY_MACRO_CNTL_RESERVED335 =$5BD3; + mmDCRX_PHY_MACRO_CNTL_RESERVED336 =$5BD4; + mmDCRX_PHY_MACRO_CNTL_RESERVED337 =$5BD5; + mmDCRX_PHY_MACRO_CNTL_RESERVED338 =$5BD6; + mmDCRX_PHY_MACRO_CNTL_RESERVED339 =$5BD7; + mmDCRX_PHY_MACRO_CNTL_RESERVED340 =$5BD8; + mmDCRX_PHY_MACRO_CNTL_RESERVED341 =$5BD9; + mmDCRX_PHY_MACRO_CNTL_RESERVED342 =$5BDA; + mmDCRX_PHY_MACRO_CNTL_RESERVED343 =$5BDB; + mmDCRX_PHY_MACRO_CNTL_RESERVED344 =$5BDC; + mmDCRX_PHY_MACRO_CNTL_RESERVED345 =$5BDD; + mmDCRX_PHY_MACRO_CNTL_RESERVED346 =$5BDE; + mmDCRX_PHY_MACRO_CNTL_RESERVED347 =$5BDF; + mmDCRX_PHY_MACRO_CNTL_RESERVED348 =$5BE0; + mmDCRX_PHY_MACRO_CNTL_RESERVED349 =$5BE1; + mmDCRX_PHY_MACRO_CNTL_RESERVED350 =$5BE2; + mmDCRX_PHY_MACRO_CNTL_RESERVED351 =$5BE3; + mmDCRX_PHY_MACRO_CNTL_RESERVED352 =$5BE4; + mmDCRX_PHY_MACRO_CNTL_RESERVED353 =$5BE5; + mmDCRX_PHY_MACRO_CNTL_RESERVED354 =$5BE6; + mmDCRX_PHY_MACRO_CNTL_RESERVED355 =$5BE7; + mmDCRX_PHY_MACRO_CNTL_RESERVED356 =$5BE8; + mmDCRX_PHY_MACRO_CNTL_RESERVED357 =$5BE9; + mmDCRX_PHY_MACRO_CNTL_RESERVED358 =$5BEA; + mmDCRX_PHY_MACRO_CNTL_RESERVED359 =$5BEB; + mmDCRX_PHY_MACRO_CNTL_RESERVED360 =$5BEC; + mmDCRX_PHY_MACRO_CNTL_RESERVED361 =$5BED; + mmDCRX_PHY_MACRO_CNTL_RESERVED362 =$5BEE; + mmDCRX_PHY_MACRO_CNTL_RESERVED363 =$5BEF; + mmDCRX_PHY_MACRO_CNTL_RESERVED364 =$5BF0; + mmDCRX_PHY_MACRO_CNTL_RESERVED365 =$5BF1; + mmDCRX_PHY_MACRO_CNTL_RESERVED366 =$5BF2; + mmDCRX_PHY_MACRO_CNTL_RESERVED367 =$5BF3; + mmDCRX_PHY_MACRO_CNTL_RESERVED368 =$5BF4; + mmDCRX_PHY_MACRO_CNTL_RESERVED369 =$5BF5; + mmDCRX_PHY_MACRO_CNTL_RESERVED370 =$5BF6; + mmDCRX_PHY_MACRO_CNTL_RESERVED371 =$5BF7; + mmDCRX_PHY_MACRO_CNTL_RESERVED372 =$5BF8; + mmDCRX_PHY_MACRO_CNTL_RESERVED373 =$5BF9; + mmDCRX_PHY_MACRO_CNTL_RESERVED374 =$5BFA; + mmDCRX_PHY_MACRO_CNTL_RESERVED375 =$5BFB; + mmDCRX_PHY_MACRO_CNTL_RESERVED376 =$5BFC; + mmDCRX_PHY_MACRO_CNTL_RESERVED377 =$5BFD; + mmDCRX_PHY_MACRO_CNTL_RESERVED378 =$5BFE; + mmDCRX_PHY_MACRO_CNTL_RESERVED379 =$5BFF; + mmAUX_CONTROL =$5C00; + mmAUX_SW_CONTROL =$5C01; + mmAUX_ARB_CONTROL =$5C02; + mmAUX_INTERRUPT_CONTROL =$5C03; + mmAUX_SW_STATUS =$5C04; + mmAUX_LS_STATUS =$5C05; + mmAUX_SW_DATA =$5C06; + mmAUX_LS_DATA =$5C07; + mmAUX_DPHY_TX_REF_CONTROL =$5C08; + mmAUX_DPHY_TX_CONTROL =$5C09; + mmAUX_DPHY_RX_CONTROL0 =$5C0A; + mmAUX_DPHY_RX_CONTROL1 =$5C0B; + mmAUX_DPHY_TX_STATUS =$5C0C; + mmAUX_DPHY_RX_STATUS =$5C0D; + mmAUX_GTC_SYNC_CONTROL =$5C0E; + mmAUX_GTC_SYNC_ERROR_CONTROL =$5C0F; + mmAUX_GTC_SYNC_CONTROLLER_STATUS =$5C10; + mmAUX_GTC_SYNC_STATUS =$5C11; + mmAUX_GTC_SYNC_DATA =$5C12; + mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C13; + mmAUX_TEST_DEBUG_INDEX =$5C14; + mmAUX_TEST_DEBUG_DATA =$5C15; + mmDP_AUX1_AUX_CONTROL =$5C1C; + mmDP_AUX1_AUX_SW_CONTROL =$5C1D; + mmDP_AUX1_AUX_ARB_CONTROL =$5C1E; + mmDP_AUX1_AUX_INTERRUPT_CONTROL =$5C1F; + mmDP_AUX1_AUX_SW_STATUS =$5C20; + mmDP_AUX1_AUX_LS_STATUS =$5C21; + mmDP_AUX1_AUX_SW_DATA =$5C22; + mmDP_AUX1_AUX_LS_DATA =$5C23; + mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL =$5C24; + mmDP_AUX1_AUX_DPHY_TX_CONTROL =$5C25; + mmDP_AUX1_AUX_DPHY_RX_CONTROL0 =$5C26; + mmDP_AUX1_AUX_DPHY_RX_CONTROL1 =$5C27; + mmDP_AUX1_AUX_DPHY_TX_STATUS =$5C28; + mmDP_AUX1_AUX_DPHY_RX_STATUS =$5C29; + mmDP_AUX1_AUX_GTC_SYNC_CONTROL =$5C2A; + mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL =$5C2B; + mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS =$5C2C; + mmDP_AUX1_AUX_GTC_SYNC_STATUS =$5C2D; + mmDP_AUX1_AUX_GTC_SYNC_DATA =$5C2E; + mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C2F; + mmDP_AUX1_AUX_TEST_DEBUG_INDEX =$5C30; + mmDP_AUX1_AUX_TEST_DEBUG_DATA =$5C31; + mmDP_AUX2_AUX_CONTROL =$5C38; + mmDP_AUX2_AUX_SW_CONTROL =$5C39; + mmDP_AUX2_AUX_ARB_CONTROL =$5C3A; + mmDP_AUX2_AUX_INTERRUPT_CONTROL =$5C3B; + mmDP_AUX2_AUX_SW_STATUS =$5C3C; + mmDP_AUX2_AUX_LS_STATUS =$5C3D; + mmDP_AUX2_AUX_SW_DATA =$5C3E; + mmDP_AUX2_AUX_LS_DATA =$5C3F; + mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL =$5C40; + mmDP_AUX2_AUX_DPHY_TX_CONTROL =$5C41; + mmDP_AUX2_AUX_DPHY_RX_CONTROL0 =$5C42; + mmDP_AUX2_AUX_DPHY_RX_CONTROL1 =$5C43; + mmDP_AUX2_AUX_DPHY_TX_STATUS =$5C44; + mmDP_AUX2_AUX_DPHY_RX_STATUS =$5C45; + mmDP_AUX2_AUX_GTC_SYNC_CONTROL =$5C46; + mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL =$5C47; + mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS =$5C48; + mmDP_AUX2_AUX_GTC_SYNC_STATUS =$5C49; + mmDP_AUX2_AUX_GTC_SYNC_DATA =$5C4A; + mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C4B; + mmDP_AUX2_AUX_TEST_DEBUG_INDEX =$5C4C; + mmDP_AUX2_AUX_TEST_DEBUG_DATA =$5C4D; + mmDP_AUX3_AUX_CONTROL =$5C54; + mmDP_AUX3_AUX_SW_CONTROL =$5C55; + mmDP_AUX3_AUX_ARB_CONTROL =$5C56; + mmDP_AUX3_AUX_INTERRUPT_CONTROL =$5C57; + mmDP_AUX3_AUX_SW_STATUS =$5C58; + mmDP_AUX3_AUX_LS_STATUS =$5C59; + mmDP_AUX3_AUX_SW_DATA =$5C5A; + mmDP_AUX3_AUX_LS_DATA =$5C5B; + mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL =$5C5C; + mmDP_AUX3_AUX_DPHY_TX_CONTROL =$5C5D; + mmDP_AUX3_AUX_DPHY_RX_CONTROL0 =$5C5E; + mmDP_AUX3_AUX_DPHY_RX_CONTROL1 =$5C5F; + mmDP_AUX3_AUX_DPHY_TX_STATUS =$5C60; + mmDP_AUX3_AUX_DPHY_RX_STATUS =$5C61; + mmDP_AUX3_AUX_GTC_SYNC_CONTROL =$5C62; + mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL =$5C63; + mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS =$5C64; + mmDP_AUX3_AUX_GTC_SYNC_STATUS =$5C65; + mmDP_AUX3_AUX_GTC_SYNC_DATA =$5C66; + mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C67; + mmDP_AUX3_AUX_TEST_DEBUG_INDEX =$5C68; + mmDP_AUX3_AUX_TEST_DEBUG_DATA =$5C69; + mmDP_AUX4_AUX_CONTROL =$5C70; + mmDP_AUX4_AUX_SW_CONTROL =$5C71; + mmDP_AUX4_AUX_ARB_CONTROL =$5C72; + mmDP_AUX4_AUX_INTERRUPT_CONTROL =$5C73; + mmDP_AUX4_AUX_SW_STATUS =$5C74; + mmDP_AUX4_AUX_LS_STATUS =$5C75; + mmDP_AUX4_AUX_SW_DATA =$5C76; + mmDP_AUX4_AUX_LS_DATA =$5C77; + mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL =$5C78; + mmDP_AUX4_AUX_DPHY_TX_CONTROL =$5C79; + mmDP_AUX4_AUX_DPHY_RX_CONTROL0 =$5C7A; + mmDP_AUX4_AUX_DPHY_RX_CONTROL1 =$5C7B; + mmDP_AUX4_AUX_DPHY_TX_STATUS =$5C7C; + mmDP_AUX4_AUX_DPHY_RX_STATUS =$5C7D; + mmDP_AUX4_AUX_GTC_SYNC_CONTROL =$5C7E; + mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL =$5C7F; + mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS =$5C80; + mmDP_AUX4_AUX_GTC_SYNC_STATUS =$5C81; + mmDP_AUX4_AUX_GTC_SYNC_DATA =$5C82; + mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C83; + mmDP_AUX4_AUX_TEST_DEBUG_INDEX =$5C84; + mmDP_AUX4_AUX_TEST_DEBUG_DATA =$5C85; + mmDP_AUX5_AUX_CONTROL =$5C8C; + mmDP_AUX5_AUX_SW_CONTROL =$5C8D; + mmDP_AUX5_AUX_ARB_CONTROL =$5C8E; + mmDP_AUX5_AUX_INTERRUPT_CONTROL =$5C8F; + mmDP_AUX5_AUX_SW_STATUS =$5C90; + mmDP_AUX5_AUX_LS_STATUS =$5C91; + mmDP_AUX5_AUX_SW_DATA =$5C92; + mmDP_AUX5_AUX_LS_DATA =$5C93; + mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL =$5C94; + mmDP_AUX5_AUX_DPHY_TX_CONTROL =$5C95; + mmDP_AUX5_AUX_DPHY_RX_CONTROL0 =$5C96; + mmDP_AUX5_AUX_DPHY_RX_CONTROL1 =$5C97; + mmDP_AUX5_AUX_DPHY_TX_STATUS =$5C98; + mmDP_AUX5_AUX_DPHY_RX_STATUS =$5C99; + mmDP_AUX5_AUX_GTC_SYNC_CONTROL =$5C9A; + mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL =$5C9B; + mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS =$5C9C; + mmDP_AUX5_AUX_GTC_SYNC_STATUS =$5C9D; + mmDP_AUX5_AUX_GTC_SYNC_DATA =$5C9E; + mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE =$5C9F; + mmDP_AUX5_AUX_TEST_DEBUG_INDEX =$5CA0; + mmDP_AUX5_AUX_TEST_DEBUG_DATA =$5CA1; + mmDPHY_MACRO_CNTL_RESERVED0 =$5D98; + mmDPHY_MACRO_CNTL_RESERVED1 =$5D99; + mmDPHY_MACRO_CNTL_RESERVED2 =$5D9A; + mmDPHY_MACRO_CNTL_RESERVED3 =$5D9B; + mmDPHY_MACRO_CNTL_RESERVED4 =$5D9C; + mmDPHY_MACRO_CNTL_RESERVED5 =$5D9D; + mmDPHY_MACRO_CNTL_RESERVED6 =$5D9E; + mmDPHY_MACRO_CNTL_RESERVED7 =$5D9F; + mmDPHY_MACRO_CNTL_RESERVED8 =$5DA0; + mmDPHY_MACRO_CNTL_RESERVED9 =$5DA1; + mmDPHY_MACRO_CNTL_RESERVED10 =$5DA2; + mmDPHY_MACRO_CNTL_RESERVED11 =$5DA3; + mmDPHY_MACRO_CNTL_RESERVED12 =$5DA4; + mmDPHY_MACRO_CNTL_RESERVED13 =$5DA5; + mmDPHY_MACRO_CNTL_RESERVED14 =$5DA6; + mmDPHY_MACRO_CNTL_RESERVED15 =$5DA7; + mmDPHY_MACRO_CNTL_RESERVED16 =$5DA8; + mmDPHY_MACRO_CNTL_RESERVED17 =$5DA9; + mmDPHY_MACRO_CNTL_RESERVED18 =$5DAA; + mmDPHY_MACRO_CNTL_RESERVED19 =$5DAB; + mmDPHY_MACRO_CNTL_RESERVED20 =$5DAC; + mmDPHY_MACRO_CNTL_RESERVED21 =$5DAD; + mmDPHY_MACRO_CNTL_RESERVED22 =$5DAE; + mmDPHY_MACRO_CNTL_RESERVED23 =$5DAF; + mmDPHY_MACRO_CNTL_RESERVED24 =$5DB0; + mmDPHY_MACRO_CNTL_RESERVED25 =$5DB1; + mmDPHY_MACRO_CNTL_RESERVED26 =$5DB2; + mmDPHY_MACRO_CNTL_RESERVED27 =$5DB3; + mmDPHY_MACRO_CNTL_RESERVED28 =$5DB4; + mmDPHY_MACRO_CNTL_RESERVED29 =$5DB5; + mmDPHY_MACRO_CNTL_RESERVED30 =$5DB6; + mmDPHY_MACRO_CNTL_RESERVED31 =$5DB7; + mmDPHY_MACRO_CNTL_RESERVED32 =$5DB8; + mmDPHY_MACRO_CNTL_RESERVED33 =$5DB9; + mmDPHY_MACRO_CNTL_RESERVED34 =$5DBA; + mmDPHY_MACRO_CNTL_RESERVED35 =$5DBB; + mmDPHY_MACRO_CNTL_RESERVED36 =$5DBC; + mmDPHY_MACRO_CNTL_RESERVED37 =$5DBD; + mmDPHY_MACRO_CNTL_RESERVED38 =$5DBE; + mmDPHY_MACRO_CNTL_RESERVED39 =$5DBF; + mmDPHY_MACRO_CNTL_RESERVED40 =$5DC0; + mmDPHY_MACRO_CNTL_RESERVED41 =$5DC1; + mmDPHY_MACRO_CNTL_RESERVED42 =$5DC2; + mmDPHY_MACRO_CNTL_RESERVED43 =$5DC3; + mmDPHY_MACRO_CNTL_RESERVED44 =$5DC4; + mmDPHY_MACRO_CNTL_RESERVED45 =$5DC5; + mmDPHY_MACRO_CNTL_RESERVED46 =$5DC6; + mmDPHY_MACRO_CNTL_RESERVED47 =$5DC7; + mmDPHY_MACRO_CNTL_RESERVED48 =$5DC8; + mmDPHY_MACRO_CNTL_RESERVED49 =$5DC9; + mmDPHY_MACRO_CNTL_RESERVED50 =$5DCA; + mmDPHY_MACRO_CNTL_RESERVED51 =$5DCB; + mmDPHY_MACRO_CNTL_RESERVED52 =$5DCC; + mmDPHY_MACRO_CNTL_RESERVED53 =$5DCD; + mmDPHY_MACRO_CNTL_RESERVED54 =$5DCE; + mmDPHY_MACRO_CNTL_RESERVED55 =$5DCF; + mmDPHY_MACRO_CNTL_RESERVED56 =$5DD0; + mmDPHY_MACRO_CNTL_RESERVED57 =$5DD1; + mmDPHY_MACRO_CNTL_RESERVED58 =$5DD2; + mmDPHY_MACRO_CNTL_RESERVED59 =$5DD3; + mmDPHY_MACRO_CNTL_RESERVED60 =$5DD4; + mmDPHY_MACRO_CNTL_RESERVED61 =$5DD5; + mmDPHY_MACRO_CNTL_RESERVED62 =$5DD6; + mmDPHY_MACRO_CNTL_RESERVED63 =$5DD7; + mmWB_ENABLE =$5E18; + mmWB_EC_CONFIG =$5E19; + mmCNV_MODE =$5E1A; + mmCNV_WINDOW_START =$5E1B; + mmCNV_WINDOW_SIZE =$5E1C; + mmCNV_UPDATE =$5E1D; + mmCNV_SOURCE_SIZE =$5E1E; + mmCNV_CSC_CONTROL =$5E1F; + mmCNV_CSC_C11_C12 =$5E20; + mmCNV_CSC_C13_C14 =$5E21; + mmCNV_CSC_C21_C22 =$5E22; + mmCNV_CSC_C23_C24 =$5E23; + mmCNV_CSC_C31_C32 =$5E24; + mmCNV_CSC_C33_C34 =$5E25; + mmCNV_CSC_ROUND_OFFSET_R =$5E26; + mmCNV_CSC_ROUND_OFFSET_G =$5E27; + mmCNV_CSC_ROUND_OFFSET_B =$5E28; + mmCNV_CSC_CLAMP_R =$5E29; + mmCNV_CSC_CLAMP_G =$5E2A; + mmCNV_CSC_CLAMP_B =$5E2B; + mmCNV_TEST_CNTL =$5E2C; + mmCNV_TEST_CRC_RED =$5E2D; + mmCNV_TEST_CRC_GREEN =$5E2E; + mmCNV_TEST_CRC_BLUE =$5E2F; + mmWB_DEBUG_CTRL =$5E30; + mmWB_DBG_MODE =$5E31; + mmWB_HW_DEBUG =$5E32; + mmCNV_INPUT_SELECT =$5E33; + mmCNV_TEST_DEBUG_INDEX =$5E34; + mmCNV_TEST_DEBUG_DATA =$5E35; + mmWB_SOFT_RESET =$5E36; + mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL =$5E78; + mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R =$5E79; + mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS =$5E7A; + mmMCIF_WB0_MCIF_WB_BUF_PITCH =$5E7B; + mmMCIF_WB0_MCIF_WB_BUF_1_STATUS =$5E7C; + mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 =$5E7D; + mmMCIF_WB0_MCIF_WB_BUF_2_STATUS =$5E7E; + mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 =$5E7F; + mmMCIF_WB0_MCIF_WB_BUF_3_STATUS =$5E80; + mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 =$5E81; + mmMCIF_WB0_MCIF_WB_BUF_4_STATUS =$5E82; + mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 =$5E83; + mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL =$5E84; + mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK =$5E85; + mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX =$5E86; + mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA =$5E87; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y =$5E88; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET =$5E89; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C =$5E8A; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET =$5E8B; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y =$5E8C; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET =$5E8D; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C =$5E8E; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET =$5E8F; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y =$5E90; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET =$5E91; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C =$5E92; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET =$5E93; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y =$5E94; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET =$5E95; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C =$5E96; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET =$5E97; + mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL =$5E98; + mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL =$5E99; + mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL =$5EB8; + mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R =$5EB9; + mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS =$5EBA; + mmMCIF_WB1_MCIF_WB_BUF_PITCH =$5EBB; + mmMCIF_WB1_MCIF_WB_BUF_1_STATUS =$5EBC; + mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 =$5EBD; + mmMCIF_WB1_MCIF_WB_BUF_2_STATUS =$5EBE; + mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 =$5EBF; + mmMCIF_WB1_MCIF_WB_BUF_3_STATUS =$5EC0; + mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 =$5EC1; + mmMCIF_WB1_MCIF_WB_BUF_4_STATUS =$5EC2; + mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 =$5EC3; + mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL =$5EC4; + mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK =$5EC5; + mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX =$5EC6; + mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA =$5EC7; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y =$5EC8; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET =$5EC9; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C =$5ECA; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET =$5ECB; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y =$5ECC; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET =$5ECD; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C =$5ECE; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET =$5ECF; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y =$5ED0; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET =$5ED1; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C =$5ED2; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET =$5ED3; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y =$5ED4; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET =$5ED5; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C =$5ED6; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET =$5ED7; + mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL =$5ED8; + mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL =$5ED9; + mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL =$5EF8; + mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R =$5EF9; + mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS =$5EFA; + mmMCIF_WB2_MCIF_WB_BUF_PITCH =$5EFB; + mmMCIF_WB2_MCIF_WB_BUF_1_STATUS =$5EFC; + mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 =$5EFD; + mmMCIF_WB2_MCIF_WB_BUF_2_STATUS =$5EFE; + mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 =$5EFF; + mmMCIF_WB2_MCIF_WB_BUF_3_STATUS =$5F00; + mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 =$5F01; + mmMCIF_WB2_MCIF_WB_BUF_4_STATUS =$5F02; + mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 =$5F03; + mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL =$5F04; + mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK =$5F05; + mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX =$5F06; + mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA =$5F07; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y =$5F08; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET =$5F09; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C =$5F0A; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET =$5F0B; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y =$5F0C; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET =$5F0D; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C =$5F0E; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET =$5F0F; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y =$5F10; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET =$5F11; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C =$5F12; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET =$5F13; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y =$5F14; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET =$5F15; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C =$5F16; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET =$5F17; + mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL =$5F18; + mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL =$5F19; + mmDC_PERFMON9_PERFCOUNTER_CNTL =$5F68; + mmDC_PERFMON9_PERFCOUNTER_STATE =$5F69; + mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC =$5F6A; + mmDC_PERFMON9_PERFMON_CNTL =$5F6B; + mmDC_PERFMON9_PERFMON_CVALUE_LOW =$5F6C; + mmDC_PERFMON9_PERFMON_HI =$5F6D; + mmDC_PERFMON9_PERFMON_LOW =$5F6E; + mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX =$5F6F; + mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA =$5F70; + mmDC_PERFMON9_PERFMON_CNTL2 =$5F72; + mmCPLL_MACRO_CNTL_RESERVED0 =$5FD0; + mmCPLL_MACRO_CNTL_RESERVED1 =$5FD1; + mmCPLL_MACRO_CNTL_RESERVED2 =$5FD2; + mmCPLL_MACRO_CNTL_RESERVED3 =$5FD3; + mmCPLL_MACRO_CNTL_RESERVED4 =$5FD4; + mmCPLL_MACRO_CNTL_RESERVED5 =$5FD5; + mmCPLL_MACRO_CNTL_RESERVED6 =$5FD6; + mmCPLL_MACRO_CNTL_RESERVED7 =$5FD7; + mmCPLL_MACRO_CNTL_RESERVED8 =$5FD8; + mmCPLL_MACRO_CNTL_RESERVED9 =$5FD9; + mmCPLL_MACRO_CNTL_RESERVED10 =$5FDA; + mmCPLL_MACRO_CNTL_RESERVED11 =$5FDB; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 =$5FDC; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 =$5FDD; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 =$5FDE; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 =$5FDF; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 =$5FE0; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 =$5FE1; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 =$5FE2; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 =$5FE3; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 =$5FE4; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 =$5FE5; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 =$5FE6; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 =$5FE7; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 =$5FE8; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 =$5FE9; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 =$5FEA; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 =$5FEB; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 =$5FEC; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 =$5FED; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 =$5FEE; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 =$5FEF; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 =$5FF0; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 =$5FF1; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 =$5FF2; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 =$5FF3; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 =$5FF4; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 =$5FF5; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 =$5FF6; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 =$5FF7; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 =$5FF8; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 =$5FF9; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 =$5FFA; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 =$5FFB; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 =$5FFC; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 =$5FFD; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 =$5FFE; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 =$5FFF; + mmSRBM_PERFMON_CNTL =$7C00; + mmSRBM_PERFCOUNTER0_SELECT =$7C01; + mmSRBM_PERFCOUNTER1_SELECT =$7C02; + mmSRBM_PERFCOUNTER0_LO =$7C03; + mmSRBM_PERFCOUNTER0_HI =$7C04; + mmSRBM_PERFCOUNTER1_LO =$7C05; + mmSRBM_PERFCOUNTER1_HI =$7C06; + mmVCE_STATUS =$8001; + mmVCE_VCPU_CNTL =$8005; + mmVCE_VCPU_CACHE_OFFSET0 =$8009; + mmVCE_VCPU_CACHE_SIZE0 =$800A; + mmVCE_VCPU_CACHE_OFFSET1 =$800B; + mmVCE_VCPU_CACHE_SIZE1 =$800C; + mmVCE_VCPU_CACHE_OFFSET2 =$800D; + mmVCE_VCPU_CACHE_SIZE2 =$800E; + mmVCE_SOFT_RESET =$8048; + mmVCE_RB_BASE_LO2 =$805B; + mmVCE_RB_BASE_HI2 =$805C; + mmVCE_RB_SIZE2 =$805D; + mmVCE_RB_RPTR2 =$805E; + mmVCE_RB_WPTR2 =$805F; + mmVCE_RB_BASE_LO =$8060; + mmVCE_RB_BASE_HI =$8061; + mmVCE_RB_SIZE =$8062; + mmVCE_RB_RPTR =$8063; + mmVCE_RB_WPTR =$8064; + mmVCE_RB_ARB_CTRL =$809F; + mmVCE_RB_BASE_LO3 =$80D4; + mmVCE_RB_BASE_HI3 =$80D5; + mmVCE_RB_SIZE3 =$80D6; + mmVCE_RB_RPTR3 =$80D7; + mmVCE_RB_WPTR3 =$80D8; + mmVCE_UENC_DMA_DCLK_CTRL =$8390; + mmVCE_SYS_INT_EN =$8540; + mmVCE_SYS_INT_ACK =$8541; + mmVCE_LMI_VCPU_CACHE_40BIT_BAR =$8597; + mmVCE_LMI_CTRL2 =$859D; + mmVCE_LMI_SWAP_CNTL3 =$859E; + mmVCE_LMI_CTRL =$85A6; + mmVCE_LMI_SWAP_CNTL =$85AD; + mmVCE_LMI_SWAP_CNTL1 =$85AE; + mmVCE_LMI_SWAP_CNTL2 =$85B3; + mmVCE_LMI_CACHE_CTRL =$85BD; + mmSAM_IH_EXT_ERR_INTR =$8810; + mmSAM_IH_EXT_ERR_INTR_STATUS =$8812; + mmSDMA0_PERFMON_CNTL =$9000; + mmSDMA0_PERFCOUNTER0_RESULT =$9001; + mmSDMA0_PERFCOUNTER1_RESULT =$9002; + mmSDMA1_PERFMON_CNTL =$9010; + mmSDMA1_PERFCOUNTER0_RESULT =$9011; + mmSDMA1_PERFCOUNTER1_RESULT =$9012; + mmDB_RENDER_CONTROL =$A000; + mmDB_COUNT_CONTROL =$A001; + mmDB_DEPTH_VIEW =$A002; + mmDB_RENDER_OVERRIDE =$A003; + mmDB_RENDER_OVERRIDE2 =$A004; + mmDB_HTILE_DATA_BASE =$A005; + mmDB_DEPTH_BOUNDS_MIN =$A008; + mmDB_DEPTH_BOUNDS_MAX =$A009; + mmDB_STENCIL_CLEAR =$A00A; + mmDB_DEPTH_CLEAR =$A00B; + mmPA_SC_SCREEN_SCISSOR_TL =$A00C; + mmPA_SC_SCREEN_SCISSOR_BR =$A00D; + mmDB_DEPTH_INFO =$A00F; + mmDB_Z_INFO =$A010; + mmDB_STENCIL_INFO =$A011; + mmDB_Z_READ_BASE =$A012; + mmDB_STENCIL_READ_BASE =$A013; + mmDB_Z_WRITE_BASE =$A014; + mmDB_STENCIL_WRITE_BASE =$A015; + mmDB_DEPTH_SIZE =$A016; + mmDB_DEPTH_SLICE =$A017; + mmTA_BC_BASE_ADDR =$A020; + mmTA_BC_BASE_ADDR_HI =$A021; + mmCOHER_DEST_BASE_HI_0 =$A07A; + mmCOHER_DEST_BASE_HI_1 =$A07B; + mmCOHER_DEST_BASE_HI_2 =$A07C; + mmCOHER_DEST_BASE_HI_3 =$A07D; + mmCOHER_DEST_BASE_2 =$A07E; + mmCOHER_DEST_BASE_3 =$A07F; + mmPA_SC_WINDOW_OFFSET =$A080; + mmPA_SC_WINDOW_SCISSOR_TL =$A081; + mmPA_SC_WINDOW_SCISSOR_BR =$A082; + mmPA_SC_CLIPRECT_RULE =$A083; + mmPA_SC_CLIPRECT_0_TL =$A084; + mmPA_SC_CLIPRECT_0_BR =$A085; + mmPA_SC_CLIPRECT_1_TL =$A086; + mmPA_SC_CLIPRECT_1_BR =$A087; + mmPA_SC_CLIPRECT_2_TL =$A088; + mmPA_SC_CLIPRECT_2_BR =$A089; + mmPA_SC_CLIPRECT_3_TL =$A08A; + mmPA_SC_CLIPRECT_3_BR =$A08B; + mmPA_SC_EDGERULE =$A08C; + mmPA_SU_HARDWARE_SCREEN_OFFSET =$A08D; + mmCB_TARGET_MASK =$A08E; + mmCB_SHADER_MASK =$A08F; + mmPA_SC_GENERIC_SCISSOR_TL =$A090; + mmPA_SC_GENERIC_SCISSOR_BR =$A091; + mmCOHER_DEST_BASE_0 =$A092; + mmCOHER_DEST_BASE_1 =$A093; + mmPA_SC_VPORT_SCISSOR_0_TL =$A094; + mmPA_SC_VPORT_SCISSOR_0_BR =$A095; + mmPA_SC_VPORT_SCISSOR_1_TL =$A096; + mmPA_SC_VPORT_SCISSOR_1_BR =$A097; + mmPA_SC_VPORT_SCISSOR_2_TL =$A098; + mmPA_SC_VPORT_SCISSOR_2_BR =$A099; + mmPA_SC_VPORT_SCISSOR_3_TL =$A09A; + mmPA_SC_VPORT_SCISSOR_3_BR =$A09B; + mmPA_SC_VPORT_SCISSOR_4_TL =$A09C; + mmPA_SC_VPORT_SCISSOR_4_BR =$A09D; + mmPA_SC_VPORT_SCISSOR_5_TL =$A09E; + mmPA_SC_VPORT_SCISSOR_5_BR =$A09F; + mmPA_SC_VPORT_SCISSOR_6_TL =$A0A0; + mmPA_SC_VPORT_SCISSOR_6_BR =$A0A1; + mmPA_SC_VPORT_SCISSOR_7_TL =$A0A2; + mmPA_SC_VPORT_SCISSOR_7_BR =$A0A3; + mmPA_SC_VPORT_SCISSOR_8_TL =$A0A4; + mmPA_SC_VPORT_SCISSOR_8_BR =$A0A5; + mmPA_SC_VPORT_SCISSOR_9_TL =$A0A6; + mmPA_SC_VPORT_SCISSOR_9_BR =$A0A7; + mmPA_SC_VPORT_SCISSOR_10_TL =$A0A8; + mmPA_SC_VPORT_SCISSOR_10_BR =$A0A9; + mmPA_SC_VPORT_SCISSOR_11_TL =$A0AA; + mmPA_SC_VPORT_SCISSOR_11_BR =$A0AB; + mmPA_SC_VPORT_SCISSOR_12_TL =$A0AC; + mmPA_SC_VPORT_SCISSOR_12_BR =$A0AD; + mmPA_SC_VPORT_SCISSOR_13_TL =$A0AE; + mmPA_SC_VPORT_SCISSOR_13_BR =$A0AF; + mmPA_SC_VPORT_SCISSOR_14_TL =$A0B0; + mmPA_SC_VPORT_SCISSOR_14_BR =$A0B1; + mmPA_SC_VPORT_SCISSOR_15_TL =$A0B2; + mmPA_SC_VPORT_SCISSOR_15_BR =$A0B3; + mmPA_SC_VPORT_ZMIN_0 =$A0B4; + mmPA_SC_VPORT_ZMAX_0 =$A0B5; + mmPA_SC_VPORT_ZMIN_1 =$A0B6; + mmPA_SC_VPORT_ZMAX_1 =$A0B7; + mmPA_SC_VPORT_ZMIN_2 =$A0B8; + mmPA_SC_VPORT_ZMAX_2 =$A0B9; + mmPA_SC_VPORT_ZMIN_3 =$A0BA; + mmPA_SC_VPORT_ZMAX_3 =$A0BB; + mmPA_SC_VPORT_ZMIN_4 =$A0BC; + mmPA_SC_VPORT_ZMAX_4 =$A0BD; + mmPA_SC_VPORT_ZMIN_5 =$A0BE; + mmPA_SC_VPORT_ZMAX_5 =$A0BF; + mmPA_SC_VPORT_ZMIN_6 =$A0C0; + mmPA_SC_VPORT_ZMAX_6 =$A0C1; + mmPA_SC_VPORT_ZMIN_7 =$A0C2; + mmPA_SC_VPORT_ZMAX_7 =$A0C3; + mmPA_SC_VPORT_ZMIN_8 =$A0C4; + mmPA_SC_VPORT_ZMAX_8 =$A0C5; + mmPA_SC_VPORT_ZMIN_9 =$A0C6; + mmPA_SC_VPORT_ZMAX_9 =$A0C7; + mmPA_SC_VPORT_ZMIN_10 =$A0C8; + mmPA_SC_VPORT_ZMAX_10 =$A0C9; + mmPA_SC_VPORT_ZMIN_11 =$A0CA; + mmPA_SC_VPORT_ZMAX_11 =$A0CB; + mmPA_SC_VPORT_ZMIN_12 =$A0CC; + mmPA_SC_VPORT_ZMAX_12 =$A0CD; + mmPA_SC_VPORT_ZMIN_13 =$A0CE; + mmPA_SC_VPORT_ZMAX_13 =$A0CF; + mmPA_SC_VPORT_ZMIN_14 =$A0D0; + mmPA_SC_VPORT_ZMAX_14 =$A0D1; + mmPA_SC_VPORT_ZMIN_15 =$A0D2; + mmPA_SC_VPORT_ZMAX_15 =$A0D3; + mmPA_SC_RASTER_CONFIG =$A0D4; + mmPA_SC_RASTER_CONFIG_1 =$A0D5; + mmCP_PERFMON_CNTX_CNTL =$A0D8; + mmCP_PIPEID =$A0D9; + mmCP_VMID =$A0DA; + mmVGT_MAX_VTX_INDX =$A100; + mmVGT_MIN_VTX_INDX =$A101; + mmVGT_INDX_OFFSET =$A102; + mmVGT_MULTI_PRIM_IB_RESET_INDX =$A103; + mmCB_BLEND_RED =$A105; + mmCB_BLEND_GREEN =$A106; + mmCB_BLEND_BLUE =$A107; + mmCB_BLEND_ALPHA =$A108; + mmCB_DCC_CONTROL =$A109; + mmDB_STENCIL_CONTROL =$A10B; + mmDB_STENCILREFMASK =$A10C; + mmDB_STENCILREFMASK_BF =$A10D; + mmPA_CL_VPORT_XSCALE =$A10F; + mmPA_CL_VPORT_XOFFSET =$A110; + mmPA_CL_VPORT_YSCALE =$A111; + mmPA_CL_VPORT_YOFFSET =$A112; + mmPA_CL_VPORT_ZSCALE =$A113; + mmPA_CL_VPORT_ZOFFSET =$A114; + mmPA_CL_VPORT_XSCALE_1 =$A115; + mmPA_CL_VPORT_XOFFSET_1 =$A116; + mmPA_CL_VPORT_YSCALE_1 =$A117; + mmPA_CL_VPORT_YOFFSET_1 =$A118; + mmPA_CL_VPORT_ZSCALE_1 =$A119; + mmPA_CL_VPORT_ZOFFSET_1 =$A11A; + mmPA_CL_VPORT_XSCALE_2 =$A11B; + mmPA_CL_VPORT_XOFFSET_2 =$A11C; + mmPA_CL_VPORT_YSCALE_2 =$A11D; + mmPA_CL_VPORT_YOFFSET_2 =$A11E; + mmPA_CL_VPORT_ZSCALE_2 =$A11F; + mmPA_CL_VPORT_ZOFFSET_2 =$A120; + mmPA_CL_VPORT_XSCALE_3 =$A121; + mmPA_CL_VPORT_XOFFSET_3 =$A122; + mmPA_CL_VPORT_YSCALE_3 =$A123; + mmPA_CL_VPORT_YOFFSET_3 =$A124; + mmPA_CL_VPORT_ZSCALE_3 =$A125; + mmPA_CL_VPORT_ZOFFSET_3 =$A126; + mmPA_CL_VPORT_XSCALE_4 =$A127; + mmPA_CL_VPORT_XOFFSET_4 =$A128; + mmPA_CL_VPORT_YSCALE_4 =$A129; + mmPA_CL_VPORT_YOFFSET_4 =$A12A; + mmPA_CL_VPORT_ZSCALE_4 =$A12B; + mmPA_CL_VPORT_ZOFFSET_4 =$A12C; + mmPA_CL_VPORT_XSCALE_5 =$A12D; + mmPA_CL_VPORT_XOFFSET_5 =$A12E; + mmPA_CL_VPORT_YSCALE_5 =$A12F; + mmPA_CL_VPORT_YOFFSET_5 =$A130; + mmPA_CL_VPORT_ZSCALE_5 =$A131; + mmPA_CL_VPORT_ZOFFSET_5 =$A132; + mmPA_CL_VPORT_XSCALE_6 =$A133; + mmPA_CL_VPORT_XOFFSET_6 =$A134; + mmPA_CL_VPORT_YSCALE_6 =$A135; + mmPA_CL_VPORT_YOFFSET_6 =$A136; + mmPA_CL_VPORT_ZSCALE_6 =$A137; + mmPA_CL_VPORT_ZOFFSET_6 =$A138; + mmPA_CL_VPORT_XSCALE_7 =$A139; + mmPA_CL_VPORT_XOFFSET_7 =$A13A; + mmPA_CL_VPORT_YSCALE_7 =$A13B; + mmPA_CL_VPORT_YOFFSET_7 =$A13C; + mmPA_CL_VPORT_ZSCALE_7 =$A13D; + mmPA_CL_VPORT_ZOFFSET_7 =$A13E; + mmPA_CL_VPORT_XSCALE_8 =$A13F; + mmPA_CL_VPORT_XOFFSET_8 =$A140; + mmPA_CL_VPORT_YSCALE_8 =$A141; + mmPA_CL_VPORT_YOFFSET_8 =$A142; + mmPA_CL_VPORT_ZSCALE_8 =$A143; + mmPA_CL_VPORT_ZOFFSET_8 =$A144; + mmPA_CL_VPORT_XSCALE_9 =$A145; + mmPA_CL_VPORT_XOFFSET_9 =$A146; + mmPA_CL_VPORT_YSCALE_9 =$A147; + mmPA_CL_VPORT_YOFFSET_9 =$A148; + mmPA_CL_VPORT_ZSCALE_9 =$A149; + mmPA_CL_VPORT_ZOFFSET_9 =$A14A; + mmPA_CL_VPORT_XSCALE_10 =$A14B; + mmPA_CL_VPORT_XOFFSET_10 =$A14C; + mmPA_CL_VPORT_YSCALE_10 =$A14D; + mmPA_CL_VPORT_YOFFSET_10 =$A14E; + mmPA_CL_VPORT_ZSCALE_10 =$A14F; + mmPA_CL_VPORT_ZOFFSET_10 =$A150; + mmPA_CL_VPORT_XSCALE_11 =$A151; + mmPA_CL_VPORT_XOFFSET_11 =$A152; + mmPA_CL_VPORT_YSCALE_11 =$A153; + mmPA_CL_VPORT_YOFFSET_11 =$A154; + mmPA_CL_VPORT_ZSCALE_11 =$A155; + mmPA_CL_VPORT_ZOFFSET_11 =$A156; + mmPA_CL_VPORT_XSCALE_12 =$A157; + mmPA_CL_VPORT_XOFFSET_12 =$A158; + mmPA_CL_VPORT_YSCALE_12 =$A159; + mmPA_CL_VPORT_YOFFSET_12 =$A15A; + mmPA_CL_VPORT_ZSCALE_12 =$A15B; + mmPA_CL_VPORT_ZOFFSET_12 =$A15C; + mmPA_CL_VPORT_XSCALE_13 =$A15D; + mmPA_CL_VPORT_XOFFSET_13 =$A15E; + mmPA_CL_VPORT_YSCALE_13 =$A15F; + mmPA_CL_VPORT_YOFFSET_13 =$A160; + mmPA_CL_VPORT_ZSCALE_13 =$A161; + mmPA_CL_VPORT_ZOFFSET_13 =$A162; + mmPA_CL_VPORT_XSCALE_14 =$A163; + mmPA_CL_VPORT_XOFFSET_14 =$A164; + mmPA_CL_VPORT_YSCALE_14 =$A165; + mmPA_CL_VPORT_YOFFSET_14 =$A166; + mmPA_CL_VPORT_ZSCALE_14 =$A167; + mmPA_CL_VPORT_ZOFFSET_14 =$A168; + mmPA_CL_VPORT_XSCALE_15 =$A169; + mmPA_CL_VPORT_XOFFSET_15 =$A16A; + mmPA_CL_VPORT_YSCALE_15 =$A16B; + mmPA_CL_VPORT_YOFFSET_15 =$A16C; + mmPA_CL_VPORT_ZSCALE_15 =$A16D; + mmPA_CL_VPORT_ZOFFSET_15 =$A16E; + mmPA_CL_UCP_0_X =$A16F; + mmPA_CL_UCP_0_Y =$A170; + mmPA_CL_UCP_0_Z =$A171; + mmPA_CL_UCP_0_W =$A172; + mmPA_CL_UCP_1_X =$A173; + mmPA_CL_UCP_1_Y =$A174; + mmPA_CL_UCP_1_Z =$A175; + mmPA_CL_UCP_1_W =$A176; + mmPA_CL_UCP_2_X =$A177; + mmPA_CL_UCP_2_Y =$A178; + mmPA_CL_UCP_2_Z =$A179; + mmPA_CL_UCP_2_W =$A17A; + mmPA_CL_UCP_3_X =$A17B; + mmPA_CL_UCP_3_Y =$A17C; + mmPA_CL_UCP_3_Z =$A17D; + mmPA_CL_UCP_3_W =$A17E; + mmPA_CL_UCP_4_X =$A17F; + mmPA_CL_UCP_4_Y =$A180; + mmPA_CL_UCP_4_Z =$A181; + mmPA_CL_UCP_4_W =$A182; + mmPA_CL_UCP_5_X =$A183; + mmPA_CL_UCP_5_Y =$A184; + mmPA_CL_UCP_5_Z =$A185; + mmPA_CL_UCP_5_W =$A186; + mmSPI_PS_INPUT_CNTL_0 =$A191; + mmSPI_PS_INPUT_CNTL_1 =$A192; + mmSPI_PS_INPUT_CNTL_2 =$A193; + mmSPI_PS_INPUT_CNTL_3 =$A194; + mmSPI_PS_INPUT_CNTL_4 =$A195; + mmSPI_PS_INPUT_CNTL_5 =$A196; + mmSPI_PS_INPUT_CNTL_6 =$A197; + mmSPI_PS_INPUT_CNTL_7 =$A198; + mmSPI_PS_INPUT_CNTL_8 =$A199; + mmSPI_PS_INPUT_CNTL_9 =$A19A; + mmSPI_PS_INPUT_CNTL_10 =$A19B; + mmSPI_PS_INPUT_CNTL_11 =$A19C; + mmSPI_PS_INPUT_CNTL_12 =$A19D; + mmSPI_PS_INPUT_CNTL_13 =$A19E; + mmSPI_PS_INPUT_CNTL_14 =$A19F; + mmSPI_PS_INPUT_CNTL_15 =$A1A0; + mmSPI_PS_INPUT_CNTL_16 =$A1A1; + mmSPI_PS_INPUT_CNTL_17 =$A1A2; + mmSPI_PS_INPUT_CNTL_18 =$A1A3; + mmSPI_PS_INPUT_CNTL_19 =$A1A4; + mmSPI_PS_INPUT_CNTL_20 =$A1A5; + mmSPI_PS_INPUT_CNTL_21 =$A1A6; + mmSPI_PS_INPUT_CNTL_22 =$A1A7; + mmSPI_PS_INPUT_CNTL_23 =$A1A8; + mmSPI_PS_INPUT_CNTL_24 =$A1A9; + mmSPI_PS_INPUT_CNTL_25 =$A1AA; + mmSPI_PS_INPUT_CNTL_26 =$A1AB; + mmSPI_PS_INPUT_CNTL_27 =$A1AC; + mmSPI_PS_INPUT_CNTL_28 =$A1AD; + mmSPI_PS_INPUT_CNTL_29 =$A1AE; + mmSPI_PS_INPUT_CNTL_30 =$A1AF; + mmSPI_PS_INPUT_CNTL_31 =$A1B0; + mmSPI_VS_OUT_CONFIG =$A1B1; + mmSPI_PS_INPUT_ENA =$A1B3; + mmSPI_PS_INPUT_ADDR =$A1B4; + mmSPI_INTERP_CONTROL_0 =$A1B5; + mmSPI_PS_IN_CONTROL =$A1B6; + mmSPI_BARYC_CNTL =$A1B8; + mmSPI_TMPRING_SIZE =$A1BA; + mmSPI_SHADER_POS_FORMAT =$A1C3; + mmSPI_SHADER_Z_FORMAT =$A1C4; + mmSPI_SHADER_COL_FORMAT =$A1C5; + mmSX_PS_DOWNCONVERT =$A1D5; + mmSX_BLEND_OPT_EPSILON =$A1D6; + mmSX_BLEND_OPT_CONTROL =$A1D7; + mmSX_MRT0_BLEND_OPT =$A1D8; + mmSX_MRT1_BLEND_OPT =$A1D9; + mmSX_MRT2_BLEND_OPT =$A1DA; + mmSX_MRT3_BLEND_OPT =$A1DB; + mmSX_MRT4_BLEND_OPT =$A1DC; + mmSX_MRT5_BLEND_OPT =$A1DD; + mmSX_MRT6_BLEND_OPT =$A1DE; + mmSX_MRT7_BLEND_OPT =$A1DF; + mmCB_BLEND0_CONTROL =$A1E0; + mmCB_BLEND1_CONTROL =$A1E1; + mmCB_BLEND2_CONTROL =$A1E2; + mmCB_BLEND3_CONTROL =$A1E3; + mmCB_BLEND4_CONTROL =$A1E4; + mmCB_BLEND5_CONTROL =$A1E5; + mmCB_BLEND6_CONTROL =$A1E6; + mmCB_BLEND7_CONTROL =$A1E7; + mmCS_COPY_STATE =$A1F3; + mmGFX_COPY_STATE =$A1F4; + mmPA_CL_POINT_X_RAD =$A1F5; + mmPA_CL_POINT_Y_RAD =$A1F6; + mmPA_CL_POINT_SIZE =$A1F7; + mmPA_CL_POINT_CULL_RAD =$A1F8; + mmVGT_DMA_BASE_HI =$A1F9; + mmVGT_DMA_BASE =$A1FA; + mmVGT_DRAW_INITIATOR =$A1FC; + mmVGT_IMMED_DATA =$A1FD; + mmVGT_EVENT_ADDRESS_REG =$A1FE; + mmDB_DEPTH_CONTROL =$A200; + mmDB_EQAA =$A201; + mmCB_COLOR_CONTROL =$A202; + mmDB_SHADER_CONTROL =$A203; + mmPA_CL_CLIP_CNTL =$A204; + mmPA_SU_SC_MODE_CNTL =$A205; + mmPA_CL_VTE_CNTL =$A206; + mmPA_CL_VS_OUT_CNTL =$A207; + mmPA_CL_NANINF_CNTL =$A208; + mmPA_SU_LINE_STIPPLE_CNTL =$A209; + mmPA_SU_LINE_STIPPLE_SCALE =$A20A; + mmPA_SU_PRIM_FILTER_CNTL =$A20B; + mmPA_SU_POINT_SIZE =$A280; + mmPA_SU_POINT_MINMAX =$A281; + mmPA_SU_LINE_CNTL =$A282; + mmPA_SC_LINE_STIPPLE =$A283; + mmVGT_OUTPUT_PATH_CNTL =$A284; + mmVGT_HOS_CNTL =$A285; + mmVGT_HOS_MAX_TESS_LEVEL =$A286; + mmVGT_HOS_MIN_TESS_LEVEL =$A287; + mmVGT_HOS_REUSE_DEPTH =$A288; + mmVGT_GROUP_PRIM_TYPE =$A289; + mmVGT_GROUP_FIRST_DECR =$A28A; + mmVGT_GROUP_DECR =$A28B; + mmVGT_GROUP_VECT_0_CNTL =$A28C; + mmVGT_GROUP_VECT_1_CNTL =$A28D; + mmVGT_GROUP_VECT_0_FMT_CNTL =$A28E; + mmVGT_GROUP_VECT_1_FMT_CNTL =$A28F; + mmVGT_GS_MODE =$A290; + mmVGT_GS_ONCHIP_CNTL =$A291; + mmPA_SC_MODE_CNTL_0 =$A292; + mmPA_SC_MODE_CNTL_1 =$A293; + mmVGT_ENHANCE =$A294; + mmVGT_GS_PER_ES =$A295; + mmVGT_ES_PER_GS =$A296; + mmVGT_GS_PER_VS =$A297; + mmVGT_GSVS_RING_OFFSET_1 =$A298; + mmVGT_GSVS_RING_OFFSET_2 =$A299; + mmVGT_GSVS_RING_OFFSET_3 =$A29A; + mmVGT_GS_OUT_PRIM_TYPE =$A29B; + mmIA_ENHANCE =$A29C; + mmVGT_DMA_SIZE =$A29D; + mmVGT_DMA_MAX_SIZE =$A29E; + mmVGT_DMA_INDEX_TYPE =$A29F; + mmWD_ENHANCE =$A2A0; + mmVGT_PRIMITIVEID_EN =$A2A1; + mmVGT_DMA_NUM_INSTANCES =$A2A2; + mmVGT_PRIMITIVEID_RESET =$A2A3; + mmVGT_EVENT_INITIATOR =$A2A4; + mmVGT_MULTI_PRIM_IB_RESET_EN =$A2A5; + mmVGT_INSTANCE_STEP_RATE_0 =$A2A8; + mmVGT_INSTANCE_STEP_RATE_1 =$A2A9; + mmIA_MULTI_VGT_PARAM =$A2AA; + mmVGT_ESGS_RING_ITEMSIZE =$A2AB; + mmVGT_GSVS_RING_ITEMSIZE =$A2AC; + mmVGT_REUSE_OFF =$A2AD; + mmVGT_VTX_CNT_EN =$A2AE; + mmDB_HTILE_SURFACE =$A2AF; + mmDB_SRESULTS_COMPARE_STATE0 =$A2B0; + mmDB_SRESULTS_COMPARE_STATE1 =$A2B1; + mmDB_PRELOAD_CONTROL =$A2B2; + mmVGT_STRMOUT_BUFFER_SIZE_0 =$A2B4; + mmVGT_STRMOUT_VTX_STRIDE_0 =$A2B5; + mmVGT_STRMOUT_BUFFER_OFFSET_0 =$A2B7; + mmVGT_STRMOUT_BUFFER_SIZE_1 =$A2B8; + mmVGT_STRMOUT_VTX_STRIDE_1 =$A2B9; + mmVGT_STRMOUT_BUFFER_OFFSET_1 =$A2BB; + mmVGT_STRMOUT_BUFFER_SIZE_2 =$A2BC; + mmVGT_STRMOUT_VTX_STRIDE_2 =$A2BD; + mmVGT_STRMOUT_BUFFER_OFFSET_2 =$A2BF; + mmVGT_STRMOUT_BUFFER_SIZE_3 =$A2C0; + mmVGT_STRMOUT_VTX_STRIDE_3 =$A2C1; + mmVGT_STRMOUT_BUFFER_OFFSET_3 =$A2C3; + mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET =$A2CA; + mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE =$A2CB; + mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE =$A2CC; + mmVGT_GS_MAX_VERT_OUT =$A2CE; + mmVGT_TESS_DISTRIBUTION =$A2D4; + mmVGT_SHADER_STAGES_EN =$A2D5; + mmVGT_LS_HS_CONFIG =$A2D6; + mmVGT_GS_VERT_ITEMSIZE =$A2D7; + mmVGT_GS_VERT_ITEMSIZE_1 =$A2D8; + mmVGT_GS_VERT_ITEMSIZE_2 =$A2D9; + mmVGT_GS_VERT_ITEMSIZE_3 =$A2DA; + mmVGT_TF_PARAM =$A2DB; + mmDB_ALPHA_TO_MASK =$A2DC; + mmVGT_DISPATCH_DRAW_INDEX =$A2DD; + mmPA_SU_POLY_OFFSET_DB_FMT_CNTL =$A2DE; + mmPA_SU_POLY_OFFSET_CLAMP =$A2DF; + mmPA_SU_POLY_OFFSET_FRONT_SCALE =$A2E0; + mmPA_SU_POLY_OFFSET_FRONT_OFFSET =$A2E1; + mmPA_SU_POLY_OFFSET_BACK_SCALE =$A2E2; + mmPA_SU_POLY_OFFSET_BACK_OFFSET =$A2E3; + mmVGT_GS_INSTANCE_CNT =$A2E4; + mmVGT_STRMOUT_CONFIG =$A2E5; + mmVGT_STRMOUT_BUFFER_CONFIG =$A2E6; + mmPA_SC_CENTROID_PRIORITY_0 =$A2F5; + mmPA_SC_CENTROID_PRIORITY_1 =$A2F6; + mmPA_SC_LINE_CNTL =$A2F7; + mmPA_SC_AA_CONFIG =$A2F8; + mmPA_SU_VTX_CNTL =$A2F9; + mmPA_CL_GB_VERT_CLIP_ADJ =$A2FA; + mmPA_CL_GB_VERT_DISC_ADJ =$A2FB; + mmPA_CL_GB_HORZ_CLIP_ADJ =$A2FC; + mmPA_CL_GB_HORZ_DISC_ADJ =$A2FD; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 =$A2FE; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 =$A2FF; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 =$A300; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 =$A301; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 =$A302; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 =$A303; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 =$A304; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 =$A305; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 =$A306; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 =$A307; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 =$A308; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 =$A309; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 =$A30A; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 =$A30B; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 =$A30C; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 =$A30D; + mmPA_SC_AA_MASK_X0Y0_X1Y0 =$A30E; + mmPA_SC_AA_MASK_X0Y1_X1Y1 =$A30F; + mmVGT_VERTEX_REUSE_BLOCK_CNTL =$A316; + mmVGT_OUT_DEALLOC_CNTL =$A317; + mmCB_COLOR0_BASE =$A318; + mmCB_COLOR0_PITCH =$A319; + mmCB_COLOR0_SLICE =$A31A; + mmCB_COLOR0_VIEW =$A31B; + mmCB_COLOR0_INFO =$A31C; + mmCB_COLOR0_ATTRIB =$A31D; + mmCB_COLOR0_DCC_CONTROL =$A31E; + mmCB_COLOR0_CMASK =$A31F; + mmCB_COLOR0_CMASK_SLICE =$A320; + mmCB_COLOR0_FMASK =$A321; + mmCB_COLOR0_FMASK_SLICE =$A322; + mmCB_COLOR0_CLEAR_WORD0 =$A323; + mmCB_COLOR0_CLEAR_WORD1 =$A324; + mmCB_COLOR0_DCC_BASE =$A325; + mmCB_COLOR1_BASE =$A327; + mmCB_COLOR1_PITCH =$A328; + mmCB_COLOR1_SLICE =$A329; + mmCB_COLOR1_VIEW =$A32A; + mmCB_COLOR1_INFO =$A32B; + mmCB_COLOR1_ATTRIB =$A32C; + mmCB_COLOR1_DCC_CONTROL =$A32D; + mmCB_COLOR1_CMASK =$A32E; + mmCB_COLOR1_CMASK_SLICE =$A32F; + mmCB_COLOR1_FMASK =$A330; + mmCB_COLOR1_FMASK_SLICE =$A331; + mmCB_COLOR1_CLEAR_WORD0 =$A332; + mmCB_COLOR1_CLEAR_WORD1 =$A333; + mmCB_COLOR1_DCC_BASE =$A334; + mmCB_COLOR2_BASE =$A336; + mmCB_COLOR2_PITCH =$A337; + mmCB_COLOR2_SLICE =$A338; + mmCB_COLOR2_VIEW =$A339; + mmCB_COLOR2_INFO =$A33A; + mmCB_COLOR2_ATTRIB =$A33B; + mmCB_COLOR2_DCC_CONTROL =$A33C; + mmCB_COLOR2_CMASK =$A33D; + mmCB_COLOR2_CMASK_SLICE =$A33E; + mmCB_COLOR2_FMASK =$A33F; + mmCB_COLOR2_FMASK_SLICE =$A340; + mmCB_COLOR2_CLEAR_WORD0 =$A341; + mmCB_COLOR2_CLEAR_WORD1 =$A342; + mmCB_COLOR2_DCC_BASE =$A343; + mmCB_COLOR3_BASE =$A345; + mmCB_COLOR3_PITCH =$A346; + mmCB_COLOR3_SLICE =$A347; + mmCB_COLOR3_VIEW =$A348; + mmCB_COLOR3_INFO =$A349; + mmCB_COLOR3_ATTRIB =$A34A; + mmCB_COLOR3_DCC_CONTROL =$A34B; + mmCB_COLOR3_CMASK =$A34C; + mmCB_COLOR3_CMASK_SLICE =$A34D; + mmCB_COLOR3_FMASK =$A34E; + mmCB_COLOR3_FMASK_SLICE =$A34F; + mmCB_COLOR3_CLEAR_WORD0 =$A350; + mmCB_COLOR3_CLEAR_WORD1 =$A351; + mmCB_COLOR3_DCC_BASE =$A352; + mmCB_COLOR4_BASE =$A354; + mmCB_COLOR4_PITCH =$A355; + mmCB_COLOR4_SLICE =$A356; + mmCB_COLOR4_VIEW =$A357; + mmCB_COLOR4_INFO =$A358; + mmCB_COLOR4_ATTRIB =$A359; + mmCB_COLOR4_DCC_CONTROL =$A35A; + mmCB_COLOR4_CMASK =$A35B; + mmCB_COLOR4_CMASK_SLICE =$A35C; + mmCB_COLOR4_FMASK =$A35D; + mmCB_COLOR4_FMASK_SLICE =$A35E; + mmCB_COLOR4_CLEAR_WORD0 =$A35F; + mmCB_COLOR4_CLEAR_WORD1 =$A360; + mmCB_COLOR4_DCC_BASE =$A361; + mmCB_COLOR5_BASE =$A363; + mmCB_COLOR5_PITCH =$A364; + mmCB_COLOR5_SLICE =$A365; + mmCB_COLOR5_VIEW =$A366; + mmCB_COLOR5_INFO =$A367; + mmCB_COLOR5_ATTRIB =$A368; + mmCB_COLOR5_DCC_CONTROL =$A369; + mmCB_COLOR5_CMASK =$A36A; + mmCB_COLOR5_CMASK_SLICE =$A36B; + mmCB_COLOR5_FMASK =$A36C; + mmCB_COLOR5_FMASK_SLICE =$A36D; + mmCB_COLOR5_CLEAR_WORD0 =$A36E; + mmCB_COLOR5_CLEAR_WORD1 =$A36F; + mmCB_COLOR5_DCC_BASE =$A370; + mmCB_COLOR6_BASE =$A372; + mmCB_COLOR6_PITCH =$A373; + mmCB_COLOR6_SLICE =$A374; + mmCB_COLOR6_VIEW =$A375; + mmCB_COLOR6_INFO =$A376; + mmCB_COLOR6_ATTRIB =$A377; + mmCB_COLOR6_DCC_CONTROL =$A378; + mmCB_COLOR6_CMASK =$A379; + mmCB_COLOR6_CMASK_SLICE =$A37A; + mmCB_COLOR6_FMASK =$A37B; + mmCB_COLOR6_FMASK_SLICE =$A37C; + mmCB_COLOR6_CLEAR_WORD0 =$A37D; + mmCB_COLOR6_CLEAR_WORD1 =$A37E; + mmCB_COLOR6_DCC_BASE =$A37F; + mmCB_COLOR7_BASE =$A381; + mmCB_COLOR7_PITCH =$A382; + mmCB_COLOR7_SLICE =$A383; + mmCB_COLOR7_VIEW =$A384; + mmCB_COLOR7_INFO =$A385; + mmCB_COLOR7_ATTRIB =$A386; + mmCB_COLOR7_DCC_CONTROL =$A387; + mmCB_COLOR7_CMASK =$A388; + mmCB_COLOR7_CMASK_SLICE =$A389; + mmCB_COLOR7_FMASK =$A38A; + mmCB_COLOR7_FMASK_SLICE =$A38B; + mmCB_COLOR7_CLEAR_WORD0 =$A38C; + mmCB_COLOR7_CLEAR_WORD1 =$A38D; + mmCB_COLOR7_DCC_BASE =$A38E; + mmCP_EOP_DONE_ADDR_LO =$C000; + mmCP_EOP_DONE_ADDR_HI =$C001; + mmCP_EOP_DONE_DATA_LO =$C002; + mmCP_EOP_DONE_DATA_HI =$C003; + mmCP_EOP_LAST_FENCE_LO =$C004; + mmCP_EOP_LAST_FENCE_HI =$C005; + mmCP_STREAM_OUT_ADDR_LO =$C006; + mmCP_STREAM_OUT_ADDR_HI =$C007; + mmCP_NUM_PRIM_WRITTEN_COUNT0_LO =$C008; + mmCP_NUM_PRIM_WRITTEN_COUNT0_HI =$C009; + mmCP_NUM_PRIM_NEEDED_COUNT0_LO =$C00A; + mmCP_NUM_PRIM_NEEDED_COUNT0_HI =$C00B; + mmCP_NUM_PRIM_WRITTEN_COUNT1_LO =$C00C; + mmCP_NUM_PRIM_WRITTEN_COUNT1_HI =$C00D; + mmCP_NUM_PRIM_NEEDED_COUNT1_LO =$C00E; + mmCP_NUM_PRIM_NEEDED_COUNT1_HI =$C00F; + mmCP_NUM_PRIM_WRITTEN_COUNT2_LO =$C010; + mmCP_NUM_PRIM_WRITTEN_COUNT2_HI =$C011; + mmCP_NUM_PRIM_NEEDED_COUNT2_LO =$C012; + mmCP_NUM_PRIM_NEEDED_COUNT2_HI =$C013; + mmCP_NUM_PRIM_WRITTEN_COUNT3_LO =$C014; + mmCP_NUM_PRIM_WRITTEN_COUNT3_HI =$C015; + mmCP_NUM_PRIM_NEEDED_COUNT3_LO =$C016; + mmCP_NUM_PRIM_NEEDED_COUNT3_HI =$C017; + mmCP_PIPE_STATS_ADDR_LO =$C018; + mmCP_PIPE_STATS_ADDR_HI =$C019; + mmCP_VGT_IAVERT_COUNT_LO =$C01A; + mmCP_VGT_IAVERT_COUNT_HI =$C01B; + mmCP_VGT_IAPRIM_COUNT_LO =$C01C; + mmCP_VGT_IAPRIM_COUNT_HI =$C01D; + mmCP_VGT_GSPRIM_COUNT_LO =$C01E; + mmCP_VGT_GSPRIM_COUNT_HI =$C01F; + mmCP_VGT_VSINVOC_COUNT_LO =$C020; + mmCP_VGT_VSINVOC_COUNT_HI =$C021; + mmCP_VGT_GSINVOC_COUNT_LO =$C022; + mmCP_VGT_GSINVOC_COUNT_HI =$C023; + mmCP_VGT_HSINVOC_COUNT_LO =$C024; + mmCP_VGT_HSINVOC_COUNT_HI =$C025; + mmCP_VGT_DSINVOC_COUNT_LO =$C026; + mmCP_VGT_DSINVOC_COUNT_HI =$C027; + mmCP_PA_CINVOC_COUNT_LO =$C028; + mmCP_PA_CINVOC_COUNT_HI =$C029; + mmCP_PA_CPRIM_COUNT_LO =$C02A; + mmCP_PA_CPRIM_COUNT_HI =$C02B; + mmCP_SC_PSINVOC_COUNT0_LO =$C02C; + mmCP_SC_PSINVOC_COUNT0_HI =$C02D; + mmCP_SC_PSINVOC_COUNT1_LO =$C02E; + mmCP_SC_PSINVOC_COUNT1_HI =$C02F; + mmCP_VGT_CSINVOC_COUNT_LO =$C030; + mmCP_VGT_CSINVOC_COUNT_HI =$C031; + mmCP_PIPE_STATS_CONTROL =$C03D; + mmCP_STREAM_OUT_CONTROL =$C03E; + mmCP_STRMOUT_CNTL =$C03F; + mmSCRATCH_REG0 =$C040; + mmSCRATCH_REG1 =$C041; + mmSCRATCH_REG2 =$C042; + mmSCRATCH_REG3 =$C043; + mmSCRATCH_REG4 =$C044; + mmSCRATCH_REG5 =$C045; + mmSCRATCH_REG6 =$C046; + mmSCRATCH_REG7 =$C047; + mmSCRATCH_UMSK =$C050; + mmSCRATCH_ADDR =$C051; + mmCP_PFP_ATOMIC_PREOP_LO =$C052; + mmCP_PFP_ATOMIC_PREOP_HI =$C053; + mmCP_PFP_GDS_ATOMIC0_PREOP_LO =$C054; + mmCP_PFP_GDS_ATOMIC0_PREOP_HI =$C055; + mmCP_PFP_GDS_ATOMIC1_PREOP_LO =$C056; + mmCP_PFP_GDS_ATOMIC1_PREOP_HI =$C057; + mmCP_APPEND_ADDR_LO =$C058; + mmCP_APPEND_ADDR_HI =$C059; + mmCP_APPEND_DATA =$C05A; + mmCP_APPEND_LAST_CS_FENCE =$C05B; + mmCP_APPEND_LAST_PS_FENCE =$C05C; + mmCP_ATOMIC_PREOP_LO =$C05D; + mmCP_ATOMIC_PREOP_HI =$C05E; + mmCP_GDS_ATOMIC0_PREOP_LO =$C05F; + mmCP_GDS_ATOMIC0_PREOP_HI =$C060; + mmCP_GDS_ATOMIC1_PREOP_LO =$C061; + mmCP_GDS_ATOMIC1_PREOP_HI =$C062; + mmCP_ME_MC_WADDR_LO =$C069; + mmCP_ME_MC_WADDR_HI =$C06A; + mmCP_ME_MC_WDATA_LO =$C06B; + mmCP_ME_MC_WDATA_HI =$C06C; + mmCP_ME_MC_RADDR_LO =$C06D; + mmCP_ME_MC_RADDR_HI =$C06E; + mmCP_SEM_WAIT_TIMER =$C06F; + mmCP_SIG_SEM_ADDR_LO =$C070; + mmCP_SIG_SEM_ADDR_HI =$C071; + mmCP_WAIT_REG_MEM_TIMEOUT =$C074; + mmCP_WAIT_SEM_ADDR_LO =$C075; + mmCP_WAIT_SEM_ADDR_HI =$C076; + mmCP_DMA_PFP_CONTROL =$C077; + mmCP_DMA_ME_CONTROL =$C078; + mmCP_COHER_BASE_HI =$C079; + mmCP_COHER_START_DELAY =$C07B; + mmCP_COHER_CNTL =$C07C; + mmCP_COHER_SIZE =$C07D; + mmCP_COHER_BASE =$C07E; + mmCP_COHER_STATUS =$C07F; + mmCP_DMA_ME_SRC_ADDR =$C080; + mmCP_DMA_ME_SRC_ADDR_HI =$C081; + mmCP_DMA_ME_DST_ADDR =$C082; + mmCP_DMA_ME_DST_ADDR_HI =$C083; + mmCP_DMA_ME_COMMAND =$C084; + mmCP_DMA_PFP_SRC_ADDR =$C085; + mmCP_DMA_PFP_SRC_ADDR_HI =$C086; + mmCP_DMA_PFP_DST_ADDR =$C087; + mmCP_DMA_PFP_DST_ADDR_HI =$C088; + mmCP_DMA_PFP_COMMAND =$C089; + mmCP_DMA_CNTL =$C08A; + mmCP_DMA_READ_TAGS =$C08B; + mmCP_COHER_SIZE_HI =$C08C; + mmCP_PFP_IB_CONTROL =$C08D; + mmCP_PFP_LOAD_CONTROL =$C08E; + mmCP_SCRATCH_INDEX =$C08F; + mmCP_SCRATCH_DATA =$C090; + mmCP_RB_OFFSET =$C091; + mmCP_IB1_OFFSET =$C092; + mmCP_IB2_OFFSET =$C093; + mmCP_IB1_PREAMBLE_BEGIN =$C094; + mmCP_IB1_PREAMBLE_END =$C095; + mmCP_IB2_PREAMBLE_BEGIN =$C096; + mmCP_IB2_PREAMBLE_END =$C097; + mmCP_CE_IB1_OFFSET =$C098; + mmCP_CE_IB2_OFFSET =$C099; + mmCP_CE_COUNTER =$C09A; + mmCP_CE_RB_OFFSET =$C09B; + mmCP_CE_INIT_BASE_LO =$C0C3; + mmCP_CE_INIT_BASE_HI =$C0C4; + mmCP_CE_INIT_BUFSZ =$C0C5; + mmCP_CE_IB1_BASE_LO =$C0C6; + mmCP_CE_IB1_BASE_HI =$C0C7; + mmCP_CE_IB1_BUFSZ =$C0C8; + mmCP_CE_IB2_BASE_LO =$C0C9; + mmCP_CE_IB2_BASE_HI =$C0CA; + mmCP_CE_IB2_BUFSZ =$C0CB; + mmCP_IB1_BASE_LO =$C0CC; + mmCP_IB1_BASE_HI =$C0CD; + mmCP_IB1_BUFSZ =$C0CE; + mmCP_IB2_BASE_LO =$C0CF; + mmCP_IB2_BASE_HI =$C0D0; + mmCP_IB2_BUFSZ =$C0D1; + mmCP_ST_BASE_LO =$C0D2; + mmCP_ST_BASE_HI =$C0D3; + mmCP_ST_BUFSZ =$C0D4; + mmCP_EOP_DONE_EVENT_CNTL =$C0D5; + mmCP_EOP_DONE_DATA_CNTL =$C0D6; + mmCP_EOP_DONE_CNTX_ID =$C0D7; + mmCP_PFP_COMPLETION_STATUS =$C0EC; + mmCP_CE_COMPLETION_STATUS =$C0ED; + mmCP_PRED_NOT_VISIBLE =$C0EE; + mmCP_PFP_METADATA_BASE_ADDR =$C0F0; + mmCP_PFP_METADATA_BASE_ADDR_HI =$C0F1; + mmCP_CE_METADATA_BASE_ADDR =$C0F2; + mmCP_CE_METADATA_BASE_ADDR_HI =$C0F3; + mmCP_DRAW_INDX_INDR_ADDR =$C0F4; + mmCP_DRAW_INDX_INDR_ADDR_HI =$C0F5; + mmCP_DISPATCH_INDR_ADDR =$C0F6; + mmCP_DISPATCH_INDR_ADDR_HI =$C0F7; + mmCP_INDEX_BASE_ADDR =$C0F8; + mmCP_INDEX_BASE_ADDR_HI =$C0F9; + mmCP_INDEX_TYPE =$C0FA; + mmCP_GDS_BKUP_ADDR =$C0FB; + mmCP_GDS_BKUP_ADDR_HI =$C0FC; + mmCP_SAMPLE_STATUS =$C0FD; + mmGRBM_GFX_INDEX =$C200; + mmVGT_ESGS_RING_SIZE =$C240; + mmVGT_GSVS_RING_SIZE =$C241; + mmVGT_PRIMITIVE_TYPE =$C242; + mmVGT_INDEX_TYPE =$C243; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 =$C244; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 =$C245; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 =$C246; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 =$C247; + mmVGT_NUM_INDICES =$C24C; + mmVGT_NUM_INSTANCES =$C24D; + mmVGT_TF_RING_SIZE =$C24E; + mmVGT_HS_OFFCHIP_PARAM =$C24F; + mmVGT_TF_MEMORY_BASE =$C250; + mmPA_SU_LINE_STIPPLE_VALUE =$C280; + mmPA_SC_LINE_STIPPLE_STATE =$C281; + mmPA_SC_P3D_TRAP_SCREEN_HV_EN =$C2A0; + mmPA_SC_P3D_TRAP_SCREEN_H =$C2A1; + mmPA_SC_P3D_TRAP_SCREEN_V =$C2A2; + mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE =$C2A3; + mmPA_SC_P3D_TRAP_SCREEN_COUNT =$C2A4; + mmPA_SC_HP3D_TRAP_SCREEN_HV_EN =$C2A8; + mmPA_SC_HP3D_TRAP_SCREEN_H =$C2A9; + mmPA_SC_HP3D_TRAP_SCREEN_V =$C2AA; + mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE =$C2AB; + mmPA_SC_HP3D_TRAP_SCREEN_COUNT =$C2AC; + mmPA_SC_TRAP_SCREEN_HV_EN =$C2B0; + mmPA_SC_TRAP_SCREEN_H =$C2B1; + mmPA_SC_TRAP_SCREEN_V =$C2B2; + mmPA_SC_TRAP_SCREEN_OCCURRENCE =$C2B3; + mmPA_SC_TRAP_SCREEN_COUNT =$C2B4; + mmSQ_THREAD_TRACE_BASE =$C330; + mmSQ_THREAD_TRACE_SIZE =$C331; + mmSQ_THREAD_TRACE_MASK =$C332; + mmSQ_THREAD_TRACE_TOKEN_MASK =$C333; + mmSQ_THREAD_TRACE_PERF_MASK =$C334; + mmSQ_THREAD_TRACE_CTRL =$C335; + mmSQ_THREAD_TRACE_MODE =$C336; + mmSQ_THREAD_TRACE_BASE2 =$C337; + mmSQ_THREAD_TRACE_TOKEN_MASK2 =$C338; + mmSQ_THREAD_TRACE_WPTR =$C339; + mmSQ_THREAD_TRACE_STATUS =$C33A; + mmSQ_THREAD_TRACE_HIWATER =$C33B; + mmSQ_THREAD_TRACE_USERDATA_0 =$C340; + mmSQ_THREAD_TRACE_USERDATA_1 =$C341; + mmSQ_THREAD_TRACE_USERDATA_2 =$C342; + mmSQ_THREAD_TRACE_USERDATA_3 =$C343; + mmSQC_CACHES =$C348; + mmSQC_WRITEBACK =$C349; + mmTA_CS_BC_BASE_ADDR =$C380; + mmTA_CS_BC_BASE_ADDR_HI =$C381; + mmDB_OCCLUSION_COUNT0_LOW =$C3C0; + mmDB_OCCLUSION_COUNT0_HI =$C3C1; + mmDB_OCCLUSION_COUNT1_LOW =$C3C2; + mmDB_OCCLUSION_COUNT1_HI =$C3C3; + mmDB_OCCLUSION_COUNT2_LOW =$C3C4; + mmDB_OCCLUSION_COUNT2_HI =$C3C5; + mmDB_OCCLUSION_COUNT3_LOW =$C3C6; + mmDB_OCCLUSION_COUNT3_HI =$C3C7; + mmDB_ZPASS_COUNT_LOW =$C3FE; + mmDB_ZPASS_COUNT_HI =$C3FF; + mmGDS_RD_ADDR =$C400; + mmGDS_RD_DATA =$C401; + mmGDS_RD_BURST_ADDR =$C402; + mmGDS_RD_BURST_COUNT =$C403; + mmGDS_RD_BURST_DATA =$C404; + mmGDS_WR_ADDR =$C405; + mmGDS_WR_DATA =$C406; + mmGDS_WR_BURST_ADDR =$C407; + mmGDS_WR_BURST_DATA =$C408; + mmGDS_WRITE_COMPLETE =$C409; + mmGDS_ATOM_CNTL =$C40A; + mmGDS_ATOM_COMPLETE =$C40B; + mmGDS_ATOM_BASE =$C40C; + mmGDS_ATOM_SIZE =$C40D; + mmGDS_ATOM_OFFSET0 =$C40E; + mmGDS_ATOM_OFFSET1 =$C40F; + mmGDS_ATOM_DST =$C410; + mmGDS_ATOM_OP =$C411; + mmGDS_ATOM_SRC0 =$C412; + mmGDS_ATOM_SRC0_U =$C413; + mmGDS_ATOM_SRC1 =$C414; + mmGDS_ATOM_SRC1_U =$C415; + mmGDS_ATOM_READ0 =$C416; + mmGDS_ATOM_READ0_U =$C417; + mmGDS_ATOM_READ1 =$C418; + mmGDS_ATOM_READ1_U =$C419; + mmGDS_GWS_RESOURCE_CNTL =$C41A; + mmGDS_GWS_RESOURCE =$C41B; + mmGDS_GWS_RESOURCE_CNT =$C41C; + mmGDS_OA_CNTL =$C41D; + mmGDS_OA_COUNTER =$C41E; + mmGDS_OA_ADDRESS =$C41F; + mmGDS_OA_INCDEC =$C420; + mmGDS_OA_RING_SIZE =$C421; + mmCPG_PERFCOUNTER1_LO =$D000; + mmCPG_PERFCOUNTER1_HI =$D001; + mmCPG_PERFCOUNTER0_LO =$D002; + mmCPG_PERFCOUNTER0_HI =$D003; + mmCPC_PERFCOUNTER1_LO =$D004; + mmCPC_PERFCOUNTER1_HI =$D005; + mmCPC_PERFCOUNTER0_LO =$D006; + mmCPC_PERFCOUNTER0_HI =$D007; + mmCPF_PERFCOUNTER1_LO =$D008; + mmCPF_PERFCOUNTER1_HI =$D009; + mmCPF_PERFCOUNTER0_LO =$D00A; + mmCPF_PERFCOUNTER0_HI =$D00B; + mmGRBM_PERFCOUNTER0_LO =$D040; + mmGRBM_PERFCOUNTER0_HI =$D041; + mmGRBM_PERFCOUNTER1_LO =$D043; + mmGRBM_PERFCOUNTER1_HI =$D044; + mmGRBM_SE0_PERFCOUNTER_LO =$D045; + mmGRBM_SE0_PERFCOUNTER_HI =$D046; + mmGRBM_SE1_PERFCOUNTER_LO =$D047; + mmGRBM_SE1_PERFCOUNTER_HI =$D048; + mmGRBM_SE2_PERFCOUNTER_LO =$D049; + mmGRBM_SE2_PERFCOUNTER_HI =$D04A; + mmGRBM_SE3_PERFCOUNTER_LO =$D04B; + mmGRBM_SE3_PERFCOUNTER_HI =$D04C; + mmWD_PERFCOUNTER0_LO =$D080; + mmWD_PERFCOUNTER0_HI =$D081; + mmWD_PERFCOUNTER1_LO =$D082; + mmWD_PERFCOUNTER1_HI =$D083; + mmWD_PERFCOUNTER2_LO =$D084; + mmWD_PERFCOUNTER2_HI =$D085; + mmWD_PERFCOUNTER3_LO =$D086; + mmWD_PERFCOUNTER3_HI =$D087; + mmIA_PERFCOUNTER0_LO =$D088; + mmIA_PERFCOUNTER0_HI =$D089; + mmIA_PERFCOUNTER1_LO =$D08A; + mmIA_PERFCOUNTER1_HI =$D08B; + mmIA_PERFCOUNTER2_LO =$D08C; + mmIA_PERFCOUNTER2_HI =$D08D; + mmIA_PERFCOUNTER3_LO =$D08E; + mmIA_PERFCOUNTER3_HI =$D08F; + mmVGT_PERFCOUNTER0_LO =$D090; + mmVGT_PERFCOUNTER0_HI =$D091; + mmVGT_PERFCOUNTER1_LO =$D092; + mmVGT_PERFCOUNTER1_HI =$D093; + mmVGT_PERFCOUNTER2_LO =$D094; + mmVGT_PERFCOUNTER2_HI =$D095; + mmVGT_PERFCOUNTER3_LO =$D096; + mmVGT_PERFCOUNTER3_HI =$D097; + mmPA_SU_PERFCOUNTER0_LO =$D100; + mmPA_SU_PERFCOUNTER0_HI =$D101; + mmPA_SU_PERFCOUNTER1_LO =$D102; + mmPA_SU_PERFCOUNTER1_HI =$D103; + mmPA_SU_PERFCOUNTER2_LO =$D104; + mmPA_SU_PERFCOUNTER2_HI =$D105; + mmPA_SU_PERFCOUNTER3_LO =$D106; + mmPA_SU_PERFCOUNTER3_HI =$D107; + mmPA_SC_PERFCOUNTER0_LO =$D140; + mmPA_SC_PERFCOUNTER0_HI =$D141; + mmPA_SC_PERFCOUNTER1_LO =$D142; + mmPA_SC_PERFCOUNTER1_HI =$D143; + mmPA_SC_PERFCOUNTER2_LO =$D144; + mmPA_SC_PERFCOUNTER2_HI =$D145; + mmPA_SC_PERFCOUNTER3_LO =$D146; + mmPA_SC_PERFCOUNTER3_HI =$D147; + mmPA_SC_PERFCOUNTER4_LO =$D148; + mmPA_SC_PERFCOUNTER4_HI =$D149; + mmPA_SC_PERFCOUNTER5_LO =$D14A; + mmPA_SC_PERFCOUNTER5_HI =$D14B; + mmPA_SC_PERFCOUNTER6_LO =$D14C; + mmPA_SC_PERFCOUNTER6_HI =$D14D; + mmPA_SC_PERFCOUNTER7_LO =$D14E; + mmPA_SC_PERFCOUNTER7_HI =$D14F; + mmSPI_PERFCOUNTER0_HI =$D180; + mmSPI_PERFCOUNTER0_LO =$D181; + mmSPI_PERFCOUNTER1_HI =$D182; + mmSPI_PERFCOUNTER1_LO =$D183; + mmSPI_PERFCOUNTER2_HI =$D184; + mmSPI_PERFCOUNTER2_LO =$D185; + mmSPI_PERFCOUNTER3_HI =$D186; + mmSPI_PERFCOUNTER3_LO =$D187; + mmSPI_PERFCOUNTER4_HI =$D188; + mmSPI_PERFCOUNTER4_LO =$D189; + mmSPI_PERFCOUNTER5_HI =$D18A; + mmSPI_PERFCOUNTER5_LO =$D18B; + mmSQ_PERFCOUNTER0_LO =$D1C0; + mmSQ_PERFCOUNTER0_HI =$D1C1; + mmSQ_PERFCOUNTER1_LO =$D1C2; + mmSQ_PERFCOUNTER1_HI =$D1C3; + mmSQ_PERFCOUNTER2_LO =$D1C4; + mmSQ_PERFCOUNTER2_HI =$D1C5; + mmSQ_PERFCOUNTER3_LO =$D1C6; + mmSQ_PERFCOUNTER3_HI =$D1C7; + mmSQ_PERFCOUNTER4_LO =$D1C8; + mmSQ_PERFCOUNTER4_HI =$D1C9; + mmSQ_PERFCOUNTER5_LO =$D1CA; + mmSQ_PERFCOUNTER5_HI =$D1CB; + mmSQ_PERFCOUNTER6_LO =$D1CC; + mmSQ_PERFCOUNTER6_HI =$D1CD; + mmSQ_PERFCOUNTER7_LO =$D1CE; + mmSQ_PERFCOUNTER7_HI =$D1CF; + mmSQ_PERFCOUNTER8_LO =$D1D0; + mmSQ_PERFCOUNTER8_HI =$D1D1; + mmSQ_PERFCOUNTER9_LO =$D1D2; + mmSQ_PERFCOUNTER9_HI =$D1D3; + mmSQ_PERFCOUNTER10_LO =$D1D4; + mmSQ_PERFCOUNTER10_HI =$D1D5; + mmSQ_PERFCOUNTER11_LO =$D1D6; + mmSQ_PERFCOUNTER11_HI =$D1D7; + mmSQ_PERFCOUNTER12_LO =$D1D8; + mmSQ_PERFCOUNTER12_HI =$D1D9; + mmSQ_PERFCOUNTER13_LO =$D1DA; + mmSQ_PERFCOUNTER13_HI =$D1DB; + mmSQ_PERFCOUNTER14_LO =$D1DC; + mmSQ_PERFCOUNTER14_HI =$D1DD; + mmSQ_PERFCOUNTER15_LO =$D1DE; + mmSQ_PERFCOUNTER15_HI =$D1DF; + mmSX_PERFCOUNTER0_LO =$D240; + mmSX_PERFCOUNTER0_HI =$D241; + mmSX_PERFCOUNTER1_LO =$D242; + mmSX_PERFCOUNTER1_HI =$D243; + mmSX_PERFCOUNTER2_LO =$D244; + mmSX_PERFCOUNTER2_HI =$D245; + mmSX_PERFCOUNTER3_LO =$D246; + mmSX_PERFCOUNTER3_HI =$D247; + mmGDS_PERFCOUNTER0_LO =$D280; + mmGDS_PERFCOUNTER0_HI =$D281; + mmGDS_PERFCOUNTER1_LO =$D282; + mmGDS_PERFCOUNTER1_HI =$D283; + mmGDS_PERFCOUNTER2_LO =$D284; + mmGDS_PERFCOUNTER2_HI =$D285; + mmGDS_PERFCOUNTER3_LO =$D286; + mmGDS_PERFCOUNTER3_HI =$D287; + mmTA_PERFCOUNTER0_LO =$D2C0; + mmTA_PERFCOUNTER0_HI =$D2C1; + mmTA_PERFCOUNTER1_LO =$D2C2; + mmTA_PERFCOUNTER1_HI =$D2C3; + mmTD_PERFCOUNTER0_LO =$D300; + mmTD_PERFCOUNTER0_HI =$D301; + mmTD_PERFCOUNTER1_LO =$D302; + mmTD_PERFCOUNTER1_HI =$D303; + mmTCP_PERFCOUNTER0_LO =$D340; + mmTCP_PERFCOUNTER0_HI =$D341; + mmTCP_PERFCOUNTER1_LO =$D342; + mmTCP_PERFCOUNTER1_HI =$D343; + mmTCP_PERFCOUNTER2_LO =$D344; + mmTCP_PERFCOUNTER2_HI =$D345; + mmTCP_PERFCOUNTER3_LO =$D346; + mmTCP_PERFCOUNTER3_HI =$D347; + mmTCC_PERFCOUNTER0_LO =$D380; + mmTCC_PERFCOUNTER0_HI =$D381; + mmTCC_PERFCOUNTER1_LO =$D382; + mmTCC_PERFCOUNTER1_HI =$D383; + mmTCC_PERFCOUNTER2_LO =$D384; + mmTCC_PERFCOUNTER2_HI =$D385; + mmTCC_PERFCOUNTER3_LO =$D386; + mmTCC_PERFCOUNTER3_HI =$D387; + mmTCA_PERFCOUNTER0_LO =$D390; + mmTCA_PERFCOUNTER0_HI =$D391; + mmTCA_PERFCOUNTER1_LO =$D392; + mmTCA_PERFCOUNTER1_HI =$D393; + mmTCA_PERFCOUNTER2_LO =$D394; + mmTCA_PERFCOUNTER2_HI =$D395; + mmTCA_PERFCOUNTER3_LO =$D396; + mmTCA_PERFCOUNTER3_HI =$D397; + mmCB_PERFCOUNTER0_LO =$D406; + mmCB_PERFCOUNTER0_HI =$D407; + mmCB_PERFCOUNTER1_LO =$D408; + mmCB_PERFCOUNTER1_HI =$D409; + mmCB_PERFCOUNTER2_LO =$D40A; + mmCB_PERFCOUNTER2_HI =$D40B; + mmCB_PERFCOUNTER3_LO =$D40C; + mmCB_PERFCOUNTER3_HI =$D40D; + mmDB_PERFCOUNTER0_LO =$D440; + mmDB_PERFCOUNTER0_HI =$D441; + mmDB_PERFCOUNTER1_LO =$D442; + mmDB_PERFCOUNTER1_HI =$D443; + mmDB_PERFCOUNTER2_LO =$D444; + mmDB_PERFCOUNTER2_HI =$D445; + mmDB_PERFCOUNTER3_LO =$D446; + mmDB_PERFCOUNTER3_HI =$D447; + mmRLC_PERFCOUNTER0_LO =$D480; + mmRLC_PERFCOUNTER0_HI =$D481; + mmRLC_PERFCOUNTER1_LO =$D482; + mmRLC_PERFCOUNTER1_HI =$D483; + mmCPG_PERFCOUNTER1_SELECT =$D800; + mmCPG_PERFCOUNTER0_SELECT1 =$D801; + mmCPG_PERFCOUNTER0_SELECT =$D802; + mmCPC_PERFCOUNTER1_SELECT =$D803; + mmCPC_PERFCOUNTER0_SELECT1 =$D804; + mmCPF_PERFCOUNTER1_SELECT =$D805; + mmCPF_PERFCOUNTER0_SELECT1 =$D806; + mmCPF_PERFCOUNTER0_SELECT =$D807; + mmCP_PERFMON_CNTL =$D808; + mmCPC_PERFCOUNTER0_SELECT =$D809; + mmCP_DRAW_OBJECT =$D810; + mmCP_DRAW_OBJECT_COUNTER =$D811; + mmCP_DRAW_WINDOW_MASK_HI =$D812; + mmCP_DRAW_WINDOW_HI =$D813; + mmCP_DRAW_WINDOW_LO =$D814; + mmCP_DRAW_WINDOW_CNTL =$D815; + mmGRBM_PERFCOUNTER0_SELECT =$D840; + mmGRBM_PERFCOUNTER1_SELECT =$D841; + mmGRBM_SE0_PERFCOUNTER_SELECT =$D842; + mmGRBM_SE1_PERFCOUNTER_SELECT =$D843; + mmGRBM_SE2_PERFCOUNTER_SELECT =$D844; + mmGRBM_SE3_PERFCOUNTER_SELECT =$D845; + mmWD_PERFCOUNTER0_SELECT =$D880; + mmWD_PERFCOUNTER1_SELECT =$D881; + mmWD_PERFCOUNTER2_SELECT =$D882; + mmWD_PERFCOUNTER3_SELECT =$D883; + mmIA_PERFCOUNTER0_SELECT =$D884; + mmIA_PERFCOUNTER1_SELECT =$D885; + mmIA_PERFCOUNTER2_SELECT =$D886; + mmIA_PERFCOUNTER3_SELECT =$D887; + mmIA_PERFCOUNTER0_SELECT1 =$D888; + mmVGT_PERFCOUNTER0_SELECT =$D88C; + mmVGT_PERFCOUNTER1_SELECT =$D88D; + mmVGT_PERFCOUNTER2_SELECT =$D88E; + mmVGT_PERFCOUNTER3_SELECT =$D88F; + mmVGT_PERFCOUNTER0_SELECT1 =$D890; + mmVGT_PERFCOUNTER1_SELECT1 =$D891; + mmVGT_PERFCOUNTER_SEID_MASK =$D894; + mmPA_SU_PERFCOUNTER0_SELECT =$D900; + mmPA_SU_PERFCOUNTER0_SELECT1 =$D901; + mmPA_SU_PERFCOUNTER1_SELECT =$D902; + mmPA_SU_PERFCOUNTER1_SELECT1 =$D903; + mmPA_SU_PERFCOUNTER2_SELECT =$D904; + mmPA_SU_PERFCOUNTER3_SELECT =$D905; + mmPA_SC_PERFCOUNTER0_SELECT =$D940; + mmPA_SC_PERFCOUNTER0_SELECT1 =$D941; + mmPA_SC_PERFCOUNTER1_SELECT =$D942; + mmPA_SC_PERFCOUNTER2_SELECT =$D943; + mmPA_SC_PERFCOUNTER3_SELECT =$D944; + mmPA_SC_PERFCOUNTER4_SELECT =$D945; + mmPA_SC_PERFCOUNTER5_SELECT =$D946; + mmPA_SC_PERFCOUNTER6_SELECT =$D947; + mmPA_SC_PERFCOUNTER7_SELECT =$D948; + mmSPI_PERFCOUNTER0_SELECT =$D980; + mmSPI_PERFCOUNTER1_SELECT =$D981; + mmSPI_PERFCOUNTER2_SELECT =$D982; + mmSPI_PERFCOUNTER3_SELECT =$D983; + mmSPI_PERFCOUNTER0_SELECT1 =$D984; + mmSPI_PERFCOUNTER1_SELECT1 =$D985; + mmSPI_PERFCOUNTER2_SELECT1 =$D986; + mmSPI_PERFCOUNTER3_SELECT1 =$D987; + mmSPI_PERFCOUNTER4_SELECT =$D988; + mmSPI_PERFCOUNTER5_SELECT =$D989; + mmSPI_PERFCOUNTER_BINS =$D98A; + mmSQ_PERFCOUNTER0_SELECT =$D9C0; + mmSQ_PERFCOUNTER1_SELECT =$D9C1; + mmSQ_PERFCOUNTER2_SELECT =$D9C2; + mmSQ_PERFCOUNTER3_SELECT =$D9C3; + mmSQ_PERFCOUNTER4_SELECT =$D9C4; + mmSQ_PERFCOUNTER5_SELECT =$D9C5; + mmSQ_PERFCOUNTER6_SELECT =$D9C6; + mmSQ_PERFCOUNTER7_SELECT =$D9C7; + mmSQ_PERFCOUNTER8_SELECT =$D9C8; + mmSQ_PERFCOUNTER9_SELECT =$D9C9; + mmSQ_PERFCOUNTER10_SELECT =$D9CA; + mmSQ_PERFCOUNTER11_SELECT =$D9CB; + mmSQ_PERFCOUNTER12_SELECT =$D9CC; + mmSQ_PERFCOUNTER13_SELECT =$D9CD; + mmSQ_PERFCOUNTER14_SELECT =$D9CE; + mmSQ_PERFCOUNTER15_SELECT =$D9CF; + mmSQ_PERFCOUNTER_CTRL =$D9E0; + mmSQ_PERFCOUNTER_MASK =$D9E1; + mmSQ_PERFCOUNTER_CTRL2 =$D9E2; + mmSX_PERFCOUNTER0_SELECT =$DA40; + mmSX_PERFCOUNTER1_SELECT =$DA41; + mmSX_PERFCOUNTER2_SELECT =$DA42; + mmSX_PERFCOUNTER3_SELECT =$DA43; + mmSX_PERFCOUNTER0_SELECT1 =$DA44; + mmSX_PERFCOUNTER1_SELECT1 =$DA45; + mmGDS_PERFCOUNTER0_SELECT =$DA80; + mmGDS_PERFCOUNTER1_SELECT =$DA81; + mmGDS_PERFCOUNTER2_SELECT =$DA82; + mmGDS_PERFCOUNTER3_SELECT =$DA83; + mmGDS_PERFCOUNTER0_SELECT1 =$DA84; + mmTA_PERFCOUNTER0_SELECT =$DAC0; + mmTA_PERFCOUNTER0_SELECT1 =$DAC1; + mmTA_PERFCOUNTER1_SELECT =$DAC2; + mmTD_PERFCOUNTER0_SELECT =$DB00; + mmTD_PERFCOUNTER0_SELECT1 =$DB01; + mmTD_PERFCOUNTER1_SELECT =$DB02; + mmTCP_PERFCOUNTER0_SELECT =$DB40; + mmTCP_PERFCOUNTER0_SELECT1 =$DB41; + mmTCP_PERFCOUNTER1_SELECT =$DB42; + mmTCP_PERFCOUNTER1_SELECT1 =$DB43; + mmTCP_PERFCOUNTER2_SELECT =$DB44; + mmTCP_PERFCOUNTER3_SELECT =$DB45; + mmTCC_PERFCOUNTER0_SELECT =$DB80; + mmTCC_PERFCOUNTER0_SELECT1 =$DB81; + mmTCC_PERFCOUNTER1_SELECT =$DB82; + mmTCC_PERFCOUNTER1_SELECT1 =$DB83; + mmTCC_PERFCOUNTER2_SELECT =$DB84; + mmTCC_PERFCOUNTER3_SELECT =$DB85; + mmTCA_PERFCOUNTER0_SELECT =$DB90; + mmTCA_PERFCOUNTER0_SELECT1 =$DB91; + mmTCA_PERFCOUNTER1_SELECT =$DB92; + mmTCA_PERFCOUNTER1_SELECT1 =$DB93; + mmTCA_PERFCOUNTER2_SELECT =$DB94; + mmTCA_PERFCOUNTER3_SELECT =$DB95; + mmCB_PERFCOUNTER_FILTER =$DC00; + mmCB_PERFCOUNTER0_SELECT =$DC01; + mmCB_PERFCOUNTER0_SELECT1 =$DC02; + mmCB_PERFCOUNTER1_SELECT =$DC03; + mmCB_PERFCOUNTER2_SELECT =$DC04; + mmCB_PERFCOUNTER3_SELECT =$DC05; + mmDB_PERFCOUNTER0_SELECT =$DC40; + mmDB_PERFCOUNTER0_SELECT1 =$DC41; + mmDB_PERFCOUNTER1_SELECT =$DC42; + mmDB_PERFCOUNTER1_SELECT1 =$DC43; + mmDB_PERFCOUNTER2_SELECT =$DC44; + mmDB_PERFCOUNTER3_SELECT =$DC46; function getRegName(i:Word):RawByteString; @@ -2006,1999 +6440,6433 @@ implementation function getRegName(i:Word):RawByteString; begin case i of - mmGRBM_CNTL :Result:='mmGRBM_CNTL'; - mmGRBM_SKEW_CNTL :Result:='mmGRBM_SKEW_CNTL'; - mmGRBM_STATUS2 :Result:='mmGRBM_STATUS2'; - mmGRBM_PWR_CNTL :Result:='mmGRBM_PWR_CNTL'; - mmGRBM_STATUS :Result:='mmGRBM_STATUS'; - mmGRBM_STATUS_SE0 :Result:='mmGRBM_STATUS_SE0'; - mmGRBM_STATUS_SE1 :Result:='mmGRBM_STATUS_SE1'; - mmGRBM_SOFT_RESET :Result:='mmGRBM_SOFT_RESET'; - mmGRBM_DEBUG_CNTL :Result:='mmGRBM_DEBUG_CNTL'; - mmGRBM_DEBUG_DATA :Result:='mmGRBM_DEBUG_DATA'; - mmGRBM_GFX_CLKEN_CNTL :Result:='mmGRBM_GFX_CLKEN_CNTL'; - mmGRBM_WAIT_IDLE_CLOCKS :Result:='mmGRBM_WAIT_IDLE_CLOCKS'; - mmGRBM_STATUS_SE2 :Result:='mmGRBM_STATUS_SE2'; - mmGRBM_STATUS_SE3 :Result:='mmGRBM_STATUS_SE3'; - mmGRBM_DEBUG :Result:='mmGRBM_DEBUG'; - mmGRBM_DEBUG_SNAPSHOT :Result:='mmGRBM_DEBUG_SNAPSHOT'; - mmGRBM_READ_ERROR :Result:='mmGRBM_READ_ERROR'; - mmGRBM_READ_ERROR2 :Result:='mmGRBM_READ_ERROR2'; - mmGRBM_INT_CNTL :Result:='mmGRBM_INT_CNTL'; - mmGRBM_TRAP_OP :Result:='mmGRBM_TRAP_OP'; - mmGRBM_TRAP_ADDR :Result:='mmGRBM_TRAP_ADDR'; - mmGRBM_TRAP_ADDR_MSK :Result:='mmGRBM_TRAP_ADDR_MSK'; - mmGRBM_TRAP_WD :Result:='mmGRBM_TRAP_WD'; - mmGRBM_TRAP_WD_MSK :Result:='mmGRBM_TRAP_WD_MSK'; - mmGRBM_DSM_BYPASS :Result:='mmGRBM_DSM_BYPASS'; - mmGRBM_WRITE_ERROR :Result:='mmGRBM_WRITE_ERROR'; - mmGRBM_NOWHERE :Result:='mmGRBM_NOWHERE'; - mmGRBM_SCRATCH_REG0 :Result:='mmGRBM_SCRATCH_REG0'; - mmGRBM_SCRATCH_REG1 :Result:='mmGRBM_SCRATCH_REG1'; - mmGRBM_SCRATCH_REG2 :Result:='mmGRBM_SCRATCH_REG2'; - mmGRBM_SCRATCH_REG3 :Result:='mmGRBM_SCRATCH_REG3'; - mmGRBM_SCRATCH_REG4 :Result:='mmGRBM_SCRATCH_REG4'; - mmGRBM_SCRATCH_REG5 :Result:='mmGRBM_SCRATCH_REG5'; - mmGRBM_SCRATCH_REG6 :Result:='mmGRBM_SCRATCH_REG6'; - mmGRBM_SCRATCH_REG7 :Result:='mmGRBM_SCRATCH_REG7'; - mmCP_CPC_STATUS :Result:='mmCP_CPC_STATUS'; - mmCP_CPC_BUSY_STAT :Result:='mmCP_CPC_BUSY_STAT'; - mmCP_CPC_STALLED_STAT1 :Result:='mmCP_CPC_STALLED_STAT1'; - mmCP_CPF_STATUS :Result:='mmCP_CPF_STATUS'; - mmCP_CPF_BUSY_STAT :Result:='mmCP_CPF_BUSY_STAT'; - mmCP_CPF_STALLED_STAT1 :Result:='mmCP_CPF_STALLED_STAT1'; - mmCP_CPC_GRBM_FREE_COUNT :Result:='mmCP_CPC_GRBM_FREE_COUNT'; - mmCP_MEC_CNTL :Result:='mmCP_MEC_CNTL'; - mmCP_MEC_ME1_HEADER_DUMP :Result:='mmCP_MEC_ME1_HEADER_DUMP'; - mmCP_MEC_ME2_HEADER_DUMP :Result:='mmCP_MEC_ME2_HEADER_DUMP'; - mmCP_CPC_SCRATCH_INDEX :Result:='mmCP_CPC_SCRATCH_INDEX'; - mmCP_CPC_SCRATCH_DATA :Result:='mmCP_CPC_SCRATCH_DATA'; - mmCP_CPC_HALT_HYST_COUNT :Result:='mmCP_CPC_HALT_HYST_COUNT'; - mmCP_PRT_LOD_STATS_CNTL0 :Result:='mmCP_PRT_LOD_STATS_CNTL0'; - mmCP_PRT_LOD_STATS_CNTL1 :Result:='mmCP_PRT_LOD_STATS_CNTL1'; - mmCP_PRT_LOD_STATS_CNTL2 :Result:='mmCP_PRT_LOD_STATS_CNTL2'; - mmCP_CE_COMPARE_COUNT :Result:='mmCP_CE_COMPARE_COUNT'; - mmCP_CE_DE_COUNT :Result:='mmCP_CE_DE_COUNT'; - mmCP_DE_CE_COUNT :Result:='mmCP_DE_CE_COUNT'; - mmCP_DE_LAST_INVAL_COUNT :Result:='mmCP_DE_LAST_INVAL_COUNT'; - mmCP_DE_DE_COUNT :Result:='mmCP_DE_DE_COUNT'; - mmCP_STALLED_STAT3 :Result:='mmCP_STALLED_STAT3'; - mmCP_STALLED_STAT1 :Result:='mmCP_STALLED_STAT1'; - mmCP_STALLED_STAT2 :Result:='mmCP_STALLED_STAT2'; - mmCP_BUSY_STAT :Result:='mmCP_BUSY_STAT'; - mmCP_STAT :Result:='mmCP_STAT'; - mmCP_PFP_HEADER_DUMP :Result:='mmCP_PFP_HEADER_DUMP'; - mmCP_GRBM_FREE_COUNT :Result:='mmCP_GRBM_FREE_COUNT'; - mmCP_CE_HEADER_DUMP :Result:='mmCP_CE_HEADER_DUMP'; - mmCP_CSF_STAT :Result:='mmCP_CSF_STAT'; - mmCP_CSF_CNTL :Result:='mmCP_CSF_CNTL'; - mmCP_CNTX_STAT :Result:='mmCP_CNTX_STAT'; - mmCP_ROQ_THRESHOLDS :Result:='mmCP_ROQ_THRESHOLDS'; - mmCP_MEQ_STQ_THRESHOLD :Result:='mmCP_MEQ_STQ_THRESHOLD'; - mmCP_RB2_RPTR :Result:='mmCP_RB2_RPTR'; - mmCP_RB1_RPTR :Result:='mmCP_RB1_RPTR'; - mmCP_RB0_RPTR :Result:='mmCP_RB0_RPTR'; - mmCP_ROQ1_THRESHOLDS :Result:='mmCP_ROQ1_THRESHOLDS'; - mmCP_ROQ2_THRESHOLDS :Result:='mmCP_ROQ2_THRESHOLDS'; - mmCP_STQ_THRESHOLDS :Result:='mmCP_STQ_THRESHOLDS'; - mmCP_QUEUE_THRESHOLDS :Result:='mmCP_QUEUE_THRESHOLDS'; - mmCP_MEQ_THRESHOLDS :Result:='mmCP_MEQ_THRESHOLDS'; - mmCP_ROQ_AVAIL :Result:='mmCP_ROQ_AVAIL'; - mmCP_STQ_AVAIL :Result:='mmCP_STQ_AVAIL'; - mmCP_ROQ2_AVAIL :Result:='mmCP_ROQ2_AVAIL'; - mmCP_MEQ_AVAIL :Result:='mmCP_MEQ_AVAIL'; - mmCP_CMD_INDEX :Result:='mmCP_CMD_INDEX'; - mmCP_CMD_DATA :Result:='mmCP_CMD_DATA'; - mmCP_ROQ_RB_STAT :Result:='mmCP_ROQ_RB_STAT'; - mmCP_ROQ_IB1_STAT :Result:='mmCP_ROQ_IB1_STAT'; - mmCP_ROQ_IB2_STAT :Result:='mmCP_ROQ_IB2_STAT'; - mmCP_STQ_STAT :Result:='mmCP_STQ_STAT'; - mmCP_STQ_WR_STAT :Result:='mmCP_STQ_WR_STAT'; - mmCP_MEQ_STAT :Result:='mmCP_MEQ_STAT'; - mmCP_CEQ1_AVAIL :Result:='mmCP_CEQ1_AVAIL'; - mmCP_CEQ2_AVAIL :Result:='mmCP_CEQ2_AVAIL'; - mmCP_CE_ROQ_RB_STAT :Result:='mmCP_CE_ROQ_RB_STAT'; - mmCP_CE_ROQ_IB1_STAT :Result:='mmCP_CE_ROQ_IB1_STAT'; - mmCP_CE_ROQ_IB2_STAT :Result:='mmCP_CE_ROQ_IB2_STAT'; - mmCP_INT_STAT_DEBUG :Result:='mmCP_INT_STAT_DEBUG'; - mmVGT_VTX_VECT_EJECT_REG :Result:='mmVGT_VTX_VECT_EJECT_REG'; - mmVGT_DMA_DATA_FIFO_DEPTH :Result:='mmVGT_DMA_DATA_FIFO_DEPTH'; - mmVGT_DMA_REQ_FIFO_DEPTH :Result:='mmVGT_DMA_REQ_FIFO_DEPTH'; - mmVGT_DRAW_INIT_FIFO_DEPTH :Result:='mmVGT_DRAW_INIT_FIFO_DEPTH'; - mmVGT_LAST_COPY_STATE :Result:='mmVGT_LAST_COPY_STATE'; - mmVGT_CACHE_INVALIDATION :Result:='mmVGT_CACHE_INVALIDATION'; - mmVGT_RESET_DEBUG :Result:='mmVGT_RESET_DEBUG'; - mmVGT_STRMOUT_DELAY :Result:='mmVGT_STRMOUT_DELAY'; - mmVGT_FIFO_DEPTHS :Result:='mmVGT_FIFO_DEPTHS'; - mmVGT_GS_VERTEX_REUSE :Result:='mmVGT_GS_VERTEX_REUSE'; - mmVGT_MC_LAT_CNTL :Result:='mmVGT_MC_LAT_CNTL'; - mmIA_CNTL_STATUS :Result:='mmIA_CNTL_STATUS'; - mmVGT_DEBUG_CNTL :Result:='mmVGT_DEBUG_CNTL'; - mmVGT_DEBUG_DATA :Result:='mmVGT_DEBUG_DATA'; - mmIA_DEBUG_CNTL :Result:='mmIA_DEBUG_CNTL'; - mmIA_DEBUG_DATA :Result:='mmIA_DEBUG_DATA'; - mmVGT_CNTL_STATUS :Result:='mmVGT_CNTL_STATUS'; - mmWD_DEBUG_CNTL :Result:='mmWD_DEBUG_CNTL'; - mmWD_DEBUG_DATA :Result:='mmWD_DEBUG_DATA'; - mmWD_CNTL_STATUS :Result:='mmWD_CNTL_STATUS'; - mmWD_QOS :Result:='mmWD_QOS'; - mmVGT_SYS_CONFIG :Result:='mmVGT_SYS_CONFIG'; - mmVGT_VS_MAX_WAVE_ID :Result:='mmVGT_VS_MAX_WAVE_ID'; - mmVGT_DMA_PRIMITIVE_TYPE :Result:='mmVGT_DMA_PRIMITIVE_TYPE'; - mmVGT_DMA_CONTROL :Result:='mmVGT_DMA_CONTROL'; - mmVGT_DMA_LS_HS_CONFIG :Result:='mmVGT_DMA_LS_HS_CONFIG'; - mmPA_SU_DEBUG_CNTL :Result:='mmPA_SU_DEBUG_CNTL'; - mmPA_SU_DEBUG_DATA :Result:='mmPA_SU_DEBUG_DATA'; - mmPA_CL_CNTL_STATUS :Result:='mmPA_CL_CNTL_STATUS'; - mmPA_CL_ENHANCE :Result:='mmPA_CL_ENHANCE'; - mmPA_CL_RESET_DEBUG :Result:='mmPA_CL_RESET_DEBUG'; - mmPA_SU_CNTL_STATUS :Result:='mmPA_SU_CNTL_STATUS'; - mmPA_SC_FIFO_DEPTH_CNTL :Result:='mmPA_SC_FIFO_DEPTH_CNTL'; - mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK'; - mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK'; - mmPA_SC_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_TRAP_SCREEN_HV_LOCK'; - mmPA_SC_FORCE_EOV_MAX_CNTS :Result:='mmPA_SC_FORCE_EOV_MAX_CNTS'; - mmPA_SC_FIFO_SIZE :Result:='mmPA_SC_FIFO_SIZE'; - mmPA_SC_IF_FIFO_SIZE :Result:='mmPA_SC_IF_FIFO_SIZE'; - mmPA_SC_DEBUG_CNTL :Result:='mmPA_SC_DEBUG_CNTL'; - mmPA_SC_DEBUG_DATA :Result:='mmPA_SC_DEBUG_DATA'; - mmPA_SC_ENHANCE :Result:='mmPA_SC_ENHANCE'; - mmSQ_THREAD_TRACE_CNTR :Result:='mmSQ_THREAD_TRACE_CNTR'; - mmSQ_BUF_RSRC_WORD0 :Result:='mmSQ_BUF_RSRC_WORD0'; - mmSQ_BUF_RSRC_WORD1 :Result:='mmSQ_BUF_RSRC_WORD1'; - mmSQ_BUF_RSRC_WORD2 :Result:='mmSQ_BUF_RSRC_WORD2'; - mmSQ_BUF_RSRC_WORD3 :Result:='mmSQ_BUF_RSRC_WORD3'; - mmSQ_IMG_RSRC_WORD0 :Result:='mmSQ_IMG_RSRC_WORD0'; - mmSQ_IMG_RSRC_WORD1 :Result:='mmSQ_IMG_RSRC_WORD1'; - mmSQ_IMG_RSRC_WORD2 :Result:='mmSQ_IMG_RSRC_WORD2'; - mmSQ_IMG_RSRC_WORD3 :Result:='mmSQ_IMG_RSRC_WORD3'; - mmSQ_IMG_RSRC_WORD4 :Result:='mmSQ_IMG_RSRC_WORD4'; - mmSQ_IMG_RSRC_WORD5 :Result:='mmSQ_IMG_RSRC_WORD5'; - mmSQ_IMG_RSRC_WORD6 :Result:='mmSQ_IMG_RSRC_WORD6'; - mmSQ_IMG_RSRC_WORD7 :Result:='mmSQ_IMG_RSRC_WORD7'; - mmSQ_IMG_SAMP_WORD0 :Result:='mmSQ_IMG_SAMP_WORD0'; - mmSQ_IMG_SAMP_WORD1 :Result:='mmSQ_IMG_SAMP_WORD1'; - mmSQ_IMG_SAMP_WORD2 :Result:='mmSQ_IMG_SAMP_WORD2'; - mmSQ_IMG_SAMP_WORD3 :Result:='mmSQ_IMG_SAMP_WORD3'; - mmSX_DEBUG_BUSY :Result:='mmSX_DEBUG_BUSY'; - mmSX_DEBUG_BUSY_2 :Result:='mmSX_DEBUG_BUSY_2'; - mmSX_DEBUG_BUSY_3 :Result:='mmSX_DEBUG_BUSY_3'; - mmSX_DEBUG_BUSY_4 :Result:='mmSX_DEBUG_BUSY_4'; - mmSX_DEBUG_1 :Result:='mmSX_DEBUG_1'; - mmSPI_PS_MAX_WAVE_ID :Result:='mmSPI_PS_MAX_WAVE_ID'; - mmSPI_START_PHASE :Result:='mmSPI_START_PHASE'; - mmSPI_GFX_CNTL :Result:='mmSPI_GFX_CNTL'; - mmSPI_CONFIG_CNTL :Result:='mmSPI_CONFIG_CNTL'; - mmSPI_DEBUG_CNTL :Result:='mmSPI_DEBUG_CNTL'; - mmSPI_DEBUG_READ :Result:='mmSPI_DEBUG_READ'; - mmSPI_DSM_CNTL :Result:='mmSPI_DSM_CNTL'; - mmSPI_EDC_CNT :Result:='mmSPI_EDC_CNT'; - mmSPI_CONFIG_CNTL_1 :Result:='mmSPI_CONFIG_CNTL_1'; - mmSPI_DEBUG_BUSY :Result:='mmSPI_DEBUG_BUSY'; - mmSPI_CONFIG_CNTL_2 :Result:='mmSPI_CONFIG_CNTL_2'; - mmSPI_WF_LIFETIME_CNTL :Result:='mmSPI_WF_LIFETIME_CNTL'; - mmSPI_WF_LIFETIME_LIMIT_0 :Result:='mmSPI_WF_LIFETIME_LIMIT_0'; - mmSPI_WF_LIFETIME_LIMIT_1 :Result:='mmSPI_WF_LIFETIME_LIMIT_1'; - mmSPI_WF_LIFETIME_LIMIT_2 :Result:='mmSPI_WF_LIFETIME_LIMIT_2'; - mmSPI_WF_LIFETIME_LIMIT_3 :Result:='mmSPI_WF_LIFETIME_LIMIT_3'; - mmSPI_WF_LIFETIME_LIMIT_4 :Result:='mmSPI_WF_LIFETIME_LIMIT_4'; - mmSPI_WF_LIFETIME_LIMIT_5 :Result:='mmSPI_WF_LIFETIME_LIMIT_5'; - mmSPI_WF_LIFETIME_LIMIT_6 :Result:='mmSPI_WF_LIFETIME_LIMIT_6'; - mmSPI_WF_LIFETIME_LIMIT_7 :Result:='mmSPI_WF_LIFETIME_LIMIT_7'; - mmSPI_WF_LIFETIME_LIMIT_8 :Result:='mmSPI_WF_LIFETIME_LIMIT_8'; - mmSPI_WF_LIFETIME_LIMIT_9 :Result:='mmSPI_WF_LIFETIME_LIMIT_9'; - mmSPI_WF_LIFETIME_STATUS_0 :Result:='mmSPI_WF_LIFETIME_STATUS_0'; - mmSPI_WF_LIFETIME_STATUS_1 :Result:='mmSPI_WF_LIFETIME_STATUS_1'; - mmSPI_WF_LIFETIME_STATUS_2 :Result:='mmSPI_WF_LIFETIME_STATUS_2'; - mmSPI_WF_LIFETIME_STATUS_3 :Result:='mmSPI_WF_LIFETIME_STATUS_3'; - mmSPI_WF_LIFETIME_STATUS_4 :Result:='mmSPI_WF_LIFETIME_STATUS_4'; - mmSPI_WF_LIFETIME_STATUS_5 :Result:='mmSPI_WF_LIFETIME_STATUS_5'; - mmSPI_WF_LIFETIME_STATUS_6 :Result:='mmSPI_WF_LIFETIME_STATUS_6'; - mmSPI_WF_LIFETIME_STATUS_7 :Result:='mmSPI_WF_LIFETIME_STATUS_7'; - mmSPI_WF_LIFETIME_STATUS_8 :Result:='mmSPI_WF_LIFETIME_STATUS_8'; - mmSPI_WF_LIFETIME_STATUS_9 :Result:='mmSPI_WF_LIFETIME_STATUS_9'; - mmSPI_WF_LIFETIME_STATUS_10 :Result:='mmSPI_WF_LIFETIME_STATUS_10'; - mmSPI_WF_LIFETIME_STATUS_11 :Result:='mmSPI_WF_LIFETIME_STATUS_11'; - mmSPI_WF_LIFETIME_STATUS_12 :Result:='mmSPI_WF_LIFETIME_STATUS_12'; - mmSPI_WF_LIFETIME_STATUS_13 :Result:='mmSPI_WF_LIFETIME_STATUS_13'; - mmSPI_WF_LIFETIME_STATUS_14 :Result:='mmSPI_WF_LIFETIME_STATUS_14'; - mmSPI_WF_LIFETIME_STATUS_15 :Result:='mmSPI_WF_LIFETIME_STATUS_15'; - mmSPI_WF_LIFETIME_STATUS_16 :Result:='mmSPI_WF_LIFETIME_STATUS_16'; - mmSPI_WF_LIFETIME_STATUS_17 :Result:='mmSPI_WF_LIFETIME_STATUS_17'; - mmSPI_WF_LIFETIME_STATUS_18 :Result:='mmSPI_WF_LIFETIME_STATUS_18'; - mmSPI_WF_LIFETIME_STATUS_19 :Result:='mmSPI_WF_LIFETIME_STATUS_19'; - mmSPI_WF_LIFETIME_STATUS_20 :Result:='mmSPI_WF_LIFETIME_STATUS_20'; - mmSPI_WF_LIFETIME_DEBUG :Result:='mmSPI_WF_LIFETIME_DEBUG'; - mmSPI_SLAVE_DEBUG_BUSY :Result:='mmSPI_SLAVE_DEBUG_BUSY'; - mmSPI_LB_CTR_CTRL :Result:='mmSPI_LB_CTR_CTRL'; - mmSPI_LB_CU_MASK :Result:='mmSPI_LB_CU_MASK'; - mmSPI_LB_DATA_REG :Result:='mmSPI_LB_DATA_REG'; - mmSPI_PG_ENABLE_STATIC_CU_MASK :Result:='mmSPI_PG_ENABLE_STATIC_CU_MASK'; - mmSPI_GDS_CREDITS :Result:='mmSPI_GDS_CREDITS'; - mmSPI_SX_EXPORT_BUFFER_SIZES :Result:='mmSPI_SX_EXPORT_BUFFER_SIZES'; - mmSPI_SX_SCOREBOARD_BUFFER_SIZES :Result:='mmSPI_SX_SCOREBOARD_BUFFER_SIZES'; - mmSPI_CSQ_WF_ACTIVE_STATUS :Result:='mmSPI_CSQ_WF_ACTIVE_STATUS'; - mmSPI_CSQ_WF_ACTIVE_COUNT_0 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_0'; - mmSPI_CSQ_WF_ACTIVE_COUNT_1 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_1'; - mmSPI_CSQ_WF_ACTIVE_COUNT_2 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_2'; - mmSPI_CSQ_WF_ACTIVE_COUNT_3 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_3'; - mmSPI_CSQ_WF_ACTIVE_COUNT_4 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_4'; - mmSPI_CSQ_WF_ACTIVE_COUNT_5 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_5'; - mmSPI_CSQ_WF_ACTIVE_COUNT_6 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_6'; - mmSPI_CSQ_WF_ACTIVE_COUNT_7 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_7'; - mmSPI_P0_TRAP_SCREEN_PSBA_LO :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_LO'; - mmSPI_P0_TRAP_SCREEN_PSBA_HI :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_HI'; - mmSPI_P0_TRAP_SCREEN_PSMA_LO :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_LO'; - mmSPI_P0_TRAP_SCREEN_PSMA_HI :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_HI'; - mmSPI_P0_TRAP_SCREEN_GPR_MIN :Result:='mmSPI_P0_TRAP_SCREEN_GPR_MIN'; - mmSPI_P1_TRAP_SCREEN_PSBA_LO :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_LO'; - mmSPI_P1_TRAP_SCREEN_PSBA_HI :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_HI'; - mmSPI_P1_TRAP_SCREEN_PSMA_LO :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_LO'; - mmSPI_P1_TRAP_SCREEN_PSMA_HI :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_HI'; - mmSPI_P1_TRAP_SCREEN_GPR_MIN :Result:='mmSPI_P1_TRAP_SCREEN_GPR_MIN'; - mmTD_CNTL :Result:='mmTD_CNTL'; - mmTD_STATUS :Result:='mmTD_STATUS'; - mmTD_DEBUG_INDEX :Result:='mmTD_DEBUG_INDEX'; - mmTD_DEBUG_DATA :Result:='mmTD_DEBUG_DATA'; - mmTD_DSM_CNTL :Result:='mmTD_DSM_CNTL'; - mmTD_SCRATCH :Result:='mmTD_SCRATCH'; - mmTA_CNTL :Result:='mmTA_CNTL'; - mmTA_CNTL_AUX :Result:='mmTA_CNTL_AUX'; - mmTA_RESERVED_010C :Result:='mmTA_RESERVED_010C'; - mmTA_STATUS :Result:='mmTA_STATUS'; - mmTA_DEBUG_INDEX :Result:='mmTA_DEBUG_INDEX'; - mmTA_DEBUG_DATA :Result:='mmTA_DEBUG_DATA'; - mmTA_SCRATCH :Result:='mmTA_SCRATCH'; - mmGDS_CONFIG :Result:='mmGDS_CONFIG'; - mmGDS_CNTL_STATUS :Result:='mmGDS_CNTL_STATUS'; - mmGDS_ENHANCE2 :Result:='mmGDS_ENHANCE2'; - mmGDS_PROTECTION_FAULT :Result:='mmGDS_PROTECTION_FAULT'; - mmGDS_VM_PROTECTION_FAULT :Result:='mmGDS_VM_PROTECTION_FAULT'; - mmGDS_EDC_CNT :Result:='mmGDS_EDC_CNT'; - mmGDS_EDC_GRBM_CNT :Result:='mmGDS_EDC_GRBM_CNT'; - mmGDS_EDC_OA_DED :Result:='mmGDS_EDC_OA_DED'; - mmGDS_DEBUG_CNTL :Result:='mmGDS_DEBUG_CNTL'; - mmGDS_DEBUG_DATA :Result:='mmGDS_DEBUG_DATA'; - mmGDS_DSM_CNTL :Result:='mmGDS_DSM_CNTL'; - mmDB_DEBUG :Result:='mmDB_DEBUG'; - mmDB_DEBUG2 :Result:='mmDB_DEBUG2'; - mmDB_DEBUG3 :Result:='mmDB_DEBUG3'; - mmDB_DEBUG4 :Result:='mmDB_DEBUG4'; - mmDB_CREDIT_LIMIT :Result:='mmDB_CREDIT_LIMIT'; - mmDB_WATERMARKS :Result:='mmDB_WATERMARKS'; - mmDB_SUBTILE_CONTROL :Result:='mmDB_SUBTILE_CONTROL'; - mmDB_FREE_CACHELINES :Result:='mmDB_FREE_CACHELINES'; - mmDB_FIFO_DEPTH1 :Result:='mmDB_FIFO_DEPTH1'; - mmDB_FIFO_DEPTH2 :Result:='mmDB_FIFO_DEPTH2'; - mmDB_RING_CONTROL :Result:='mmDB_RING_CONTROL'; - mmDB_READ_DEBUG_0 :Result:='mmDB_READ_DEBUG_0'; - mmDB_READ_DEBUG_1 :Result:='mmDB_READ_DEBUG_1'; - mmDB_READ_DEBUG_2 :Result:='mmDB_READ_DEBUG_2'; - mmDB_READ_DEBUG_3 :Result:='mmDB_READ_DEBUG_3'; - mmDB_READ_DEBUG_4 :Result:='mmDB_READ_DEBUG_4'; - mmDB_READ_DEBUG_5 :Result:='mmDB_READ_DEBUG_5'; - mmDB_READ_DEBUG_6 :Result:='mmDB_READ_DEBUG_6'; - mmDB_READ_DEBUG_7 :Result:='mmDB_READ_DEBUG_7'; - mmDB_READ_DEBUG_8 :Result:='mmDB_READ_DEBUG_8'; - mmDB_READ_DEBUG_9 :Result:='mmDB_READ_DEBUG_9'; - mmDB_READ_DEBUG_A :Result:='mmDB_READ_DEBUG_A'; - mmDB_READ_DEBUG_B :Result:='mmDB_READ_DEBUG_B'; - mmDB_READ_DEBUG_C :Result:='mmDB_READ_DEBUG_C'; - mmDB_READ_DEBUG_D :Result:='mmDB_READ_DEBUG_D'; - mmDB_READ_DEBUG_E :Result:='mmDB_READ_DEBUG_E'; - mmDB_READ_DEBUG_F :Result:='mmDB_READ_DEBUG_F'; - mmCB_HW_CONTROL_3 :Result:='mmCB_HW_CONTROL_3'; - mmCB_HW_CONTROL :Result:='mmCB_HW_CONTROL'; - mmCB_HW_CONTROL_1 :Result:='mmCB_HW_CONTROL_1'; - mmCB_HW_CONTROL_2 :Result:='mmCB_HW_CONTROL_2'; - mmCB_DCC_CONFIG :Result:='mmCB_DCC_CONFIG'; - mmCB_DEBUG_BUS_1 :Result:='mmCB_DEBUG_BUS_1'; - mmCB_DEBUG_BUS_2 :Result:='mmCB_DEBUG_BUS_2'; - mmCB_DEBUG_BUS_13 :Result:='mmCB_DEBUG_BUS_13'; - mmCB_DEBUG_BUS_14 :Result:='mmCB_DEBUG_BUS_14'; - mmCB_DEBUG_BUS_15 :Result:='mmCB_DEBUG_BUS_15'; - mmCB_DEBUG_BUS_16 :Result:='mmCB_DEBUG_BUS_16'; - mmCB_DEBUG_BUS_17 :Result:='mmCB_DEBUG_BUS_17'; - mmCB_DEBUG_BUS_18 :Result:='mmCB_DEBUG_BUS_18'; - mmCB_DEBUG_BUS_19 :Result:='mmCB_DEBUG_BUS_19'; - mmCB_DEBUG_BUS_20 :Result:='mmCB_DEBUG_BUS_20'; - mmCB_DEBUG_BUS_21 :Result:='mmCB_DEBUG_BUS_21'; - mmCB_DEBUG_BUS_22 :Result:='mmCB_DEBUG_BUS_22'; - mmTCP_INVALIDATE :Result:='mmTCP_INVALIDATE'; - mmTCP_STATUS :Result:='mmTCP_STATUS'; - mmTCP_CNTL :Result:='mmTCP_CNTL'; - mmTCP_CHAN_STEER_LO :Result:='mmTCP_CHAN_STEER_LO'; - mmTCP_CHAN_STEER_HI :Result:='mmTCP_CHAN_STEER_HI'; - mmTCP_ADDR_CONFIG :Result:='mmTCP_ADDR_CONFIG'; - mmTCP_CREDIT :Result:='mmTCP_CREDIT'; - mmTCP_BUFFER_ADDR_HASH_CNTL :Result:='mmTCP_BUFFER_ADDR_HASH_CNTL'; - mmTCP_EDC_CNT :Result:='mmTCP_EDC_CNT'; - mmTCC_CTRL :Result:='mmTCC_CTRL'; - mmTCC_EDC_CNT :Result:='mmTCC_EDC_CNT'; - mmTCC_REDUNDANCY :Result:='mmTCC_REDUNDANCY'; - mmTCC_EXE_DISABLE :Result:='mmTCC_EXE_DISABLE'; - mmTCC_DSM_CNTL :Result:='mmTCC_DSM_CNTL'; - mmTCA_CTRL :Result:='mmTCA_CTRL'; - mmSPI_SHADER_TBA_LO_PS :Result:='mmSPI_SHADER_TBA_LO_PS'; - mmSPI_SHADER_TBA_HI_PS :Result:='mmSPI_SHADER_TBA_HI_PS'; - mmSPI_SHADER_TMA_LO_PS :Result:='mmSPI_SHADER_TMA_LO_PS'; - mmSPI_SHADER_TMA_HI_PS :Result:='mmSPI_SHADER_TMA_HI_PS'; - mmSPI_SHADER_PGM_RSRC3_PS :Result:='mmSPI_SHADER_PGM_RSRC3_PS'; - mmSPI_SHADER_PGM_LO_PS :Result:='mmSPI_SHADER_PGM_LO_PS'; - mmSPI_SHADER_PGM_HI_PS :Result:='mmSPI_SHADER_PGM_HI_PS'; - mmSPI_SHADER_PGM_RSRC1_PS :Result:='mmSPI_SHADER_PGM_RSRC1_PS'; - mmSPI_SHADER_PGM_RSRC2_PS :Result:='mmSPI_SHADER_PGM_RSRC2_PS'; - mmSPI_SHADER_USER_DATA_PS_0 :Result:='mmSPI_SHADER_USER_DATA_PS_0'; - mmSPI_SHADER_USER_DATA_PS_1 :Result:='mmSPI_SHADER_USER_DATA_PS_1'; - mmSPI_SHADER_USER_DATA_PS_2 :Result:='mmSPI_SHADER_USER_DATA_PS_2'; - mmSPI_SHADER_USER_DATA_PS_3 :Result:='mmSPI_SHADER_USER_DATA_PS_3'; - mmSPI_SHADER_USER_DATA_PS_4 :Result:='mmSPI_SHADER_USER_DATA_PS_4'; - mmSPI_SHADER_USER_DATA_PS_5 :Result:='mmSPI_SHADER_USER_DATA_PS_5'; - mmSPI_SHADER_USER_DATA_PS_6 :Result:='mmSPI_SHADER_USER_DATA_PS_6'; - mmSPI_SHADER_USER_DATA_PS_7 :Result:='mmSPI_SHADER_USER_DATA_PS_7'; - mmSPI_SHADER_USER_DATA_PS_8 :Result:='mmSPI_SHADER_USER_DATA_PS_8'; - mmSPI_SHADER_USER_DATA_PS_9 :Result:='mmSPI_SHADER_USER_DATA_PS_9'; - mmSPI_SHADER_USER_DATA_PS_10 :Result:='mmSPI_SHADER_USER_DATA_PS_10'; - mmSPI_SHADER_USER_DATA_PS_11 :Result:='mmSPI_SHADER_USER_DATA_PS_11'; - mmSPI_SHADER_USER_DATA_PS_12 :Result:='mmSPI_SHADER_USER_DATA_PS_12'; - mmSPI_SHADER_USER_DATA_PS_13 :Result:='mmSPI_SHADER_USER_DATA_PS_13'; - mmSPI_SHADER_USER_DATA_PS_14 :Result:='mmSPI_SHADER_USER_DATA_PS_14'; - mmSPI_SHADER_USER_DATA_PS_15 :Result:='mmSPI_SHADER_USER_DATA_PS_15'; - mmSPI_SHADER_TBA_LO_VS :Result:='mmSPI_SHADER_TBA_LO_VS'; - mmSPI_SHADER_TBA_HI_VS :Result:='mmSPI_SHADER_TBA_HI_VS'; - mmSPI_SHADER_TMA_LO_VS :Result:='mmSPI_SHADER_TMA_LO_VS'; - mmSPI_SHADER_TMA_HI_VS :Result:='mmSPI_SHADER_TMA_HI_VS'; - mmSPI_SHADER_PGM_RSRC3_VS :Result:='mmSPI_SHADER_PGM_RSRC3_VS'; - mmSPI_SHADER_LATE_ALLOC_VS :Result:='mmSPI_SHADER_LATE_ALLOC_VS'; - mmSPI_SHADER_PGM_LO_VS :Result:='mmSPI_SHADER_PGM_LO_VS'; - mmSPI_SHADER_PGM_HI_VS :Result:='mmSPI_SHADER_PGM_HI_VS'; - mmSPI_SHADER_PGM_RSRC1_VS :Result:='mmSPI_SHADER_PGM_RSRC1_VS'; - mmSPI_SHADER_PGM_RSRC2_VS :Result:='mmSPI_SHADER_PGM_RSRC2_VS'; - mmSPI_SHADER_USER_DATA_VS_0 :Result:='mmSPI_SHADER_USER_DATA_VS_0'; - mmSPI_SHADER_USER_DATA_VS_1 :Result:='mmSPI_SHADER_USER_DATA_VS_1'; - mmSPI_SHADER_USER_DATA_VS_2 :Result:='mmSPI_SHADER_USER_DATA_VS_2'; - mmSPI_SHADER_USER_DATA_VS_3 :Result:='mmSPI_SHADER_USER_DATA_VS_3'; - mmSPI_SHADER_USER_DATA_VS_4 :Result:='mmSPI_SHADER_USER_DATA_VS_4'; - mmSPI_SHADER_USER_DATA_VS_5 :Result:='mmSPI_SHADER_USER_DATA_VS_5'; - mmSPI_SHADER_USER_DATA_VS_6 :Result:='mmSPI_SHADER_USER_DATA_VS_6'; - mmSPI_SHADER_USER_DATA_VS_7 :Result:='mmSPI_SHADER_USER_DATA_VS_7'; - mmSPI_SHADER_USER_DATA_VS_8 :Result:='mmSPI_SHADER_USER_DATA_VS_8'; - mmSPI_SHADER_USER_DATA_VS_9 :Result:='mmSPI_SHADER_USER_DATA_VS_9'; - mmSPI_SHADER_USER_DATA_VS_10 :Result:='mmSPI_SHADER_USER_DATA_VS_10'; - mmSPI_SHADER_USER_DATA_VS_11 :Result:='mmSPI_SHADER_USER_DATA_VS_11'; - mmSPI_SHADER_USER_DATA_VS_12 :Result:='mmSPI_SHADER_USER_DATA_VS_12'; - mmSPI_SHADER_USER_DATA_VS_13 :Result:='mmSPI_SHADER_USER_DATA_VS_13'; - mmSPI_SHADER_USER_DATA_VS_14 :Result:='mmSPI_SHADER_USER_DATA_VS_14'; - mmSPI_SHADER_USER_DATA_VS_15 :Result:='mmSPI_SHADER_USER_DATA_VS_15'; - mmSPI_SHADER_PGM_RSRC2_ES_VS :Result:='mmSPI_SHADER_PGM_RSRC2_ES_VS'; - mmSPI_SHADER_PGM_RSRC2_LS_VS :Result:='mmSPI_SHADER_PGM_RSRC2_LS_VS'; - mmSPI_SHADER_TBA_LO_GS :Result:='mmSPI_SHADER_TBA_LO_GS'; - mmSPI_SHADER_TBA_HI_GS :Result:='mmSPI_SHADER_TBA_HI_GS'; - mmSPI_SHADER_TMA_LO_GS :Result:='mmSPI_SHADER_TMA_LO_GS'; - mmSPI_SHADER_TMA_HI_GS :Result:='mmSPI_SHADER_TMA_HI_GS'; - mmSPI_SHADER_PGM_RSRC3_GS :Result:='mmSPI_SHADER_PGM_RSRC3_GS'; - mmSPI_SHADER_PGM_LO_GS :Result:='mmSPI_SHADER_PGM_LO_GS'; - mmSPI_SHADER_PGM_HI_GS :Result:='mmSPI_SHADER_PGM_HI_GS'; - mmSPI_SHADER_PGM_RSRC1_GS :Result:='mmSPI_SHADER_PGM_RSRC1_GS'; - mmSPI_SHADER_PGM_RSRC2_GS :Result:='mmSPI_SHADER_PGM_RSRC2_GS'; - mmSPI_SHADER_USER_DATA_GS_0 :Result:='mmSPI_SHADER_USER_DATA_GS_0'; - mmSPI_SHADER_USER_DATA_GS_1 :Result:='mmSPI_SHADER_USER_DATA_GS_1'; - mmSPI_SHADER_USER_DATA_GS_2 :Result:='mmSPI_SHADER_USER_DATA_GS_2'; - mmSPI_SHADER_USER_DATA_GS_3 :Result:='mmSPI_SHADER_USER_DATA_GS_3'; - mmSPI_SHADER_USER_DATA_GS_4 :Result:='mmSPI_SHADER_USER_DATA_GS_4'; - mmSPI_SHADER_USER_DATA_GS_5 :Result:='mmSPI_SHADER_USER_DATA_GS_5'; - mmSPI_SHADER_USER_DATA_GS_6 :Result:='mmSPI_SHADER_USER_DATA_GS_6'; - mmSPI_SHADER_USER_DATA_GS_7 :Result:='mmSPI_SHADER_USER_DATA_GS_7'; - mmSPI_SHADER_USER_DATA_GS_8 :Result:='mmSPI_SHADER_USER_DATA_GS_8'; - mmSPI_SHADER_USER_DATA_GS_9 :Result:='mmSPI_SHADER_USER_DATA_GS_9'; - mmSPI_SHADER_USER_DATA_GS_10 :Result:='mmSPI_SHADER_USER_DATA_GS_10'; - mmSPI_SHADER_USER_DATA_GS_11 :Result:='mmSPI_SHADER_USER_DATA_GS_11'; - mmSPI_SHADER_USER_DATA_GS_12 :Result:='mmSPI_SHADER_USER_DATA_GS_12'; - mmSPI_SHADER_USER_DATA_GS_13 :Result:='mmSPI_SHADER_USER_DATA_GS_13'; - mmSPI_SHADER_USER_DATA_GS_14 :Result:='mmSPI_SHADER_USER_DATA_GS_14'; - mmSPI_SHADER_USER_DATA_GS_15 :Result:='mmSPI_SHADER_USER_DATA_GS_15'; - mmSPI_SHADER_PGM_RSRC2_ES_GS :Result:='mmSPI_SHADER_PGM_RSRC2_ES_GS'; - mmSPI_SHADER_TBA_LO_ES :Result:='mmSPI_SHADER_TBA_LO_ES'; - mmSPI_SHADER_TBA_HI_ES :Result:='mmSPI_SHADER_TBA_HI_ES'; - mmSPI_SHADER_TMA_LO_ES :Result:='mmSPI_SHADER_TMA_LO_ES'; - mmSPI_SHADER_TMA_HI_ES :Result:='mmSPI_SHADER_TMA_HI_ES'; - mmSPI_SHADER_PGM_RSRC3_ES :Result:='mmSPI_SHADER_PGM_RSRC3_ES'; - mmSPI_SHADER_PGM_LO_ES :Result:='mmSPI_SHADER_PGM_LO_ES'; - mmSPI_SHADER_PGM_HI_ES :Result:='mmSPI_SHADER_PGM_HI_ES'; - mmSPI_SHADER_PGM_RSRC1_ES :Result:='mmSPI_SHADER_PGM_RSRC1_ES'; - mmSPI_SHADER_PGM_RSRC2_ES :Result:='mmSPI_SHADER_PGM_RSRC2_ES'; - mmSPI_SHADER_USER_DATA_ES_0 :Result:='mmSPI_SHADER_USER_DATA_ES_0'; - mmSPI_SHADER_USER_DATA_ES_1 :Result:='mmSPI_SHADER_USER_DATA_ES_1'; - mmSPI_SHADER_USER_DATA_ES_2 :Result:='mmSPI_SHADER_USER_DATA_ES_2'; - mmSPI_SHADER_USER_DATA_ES_3 :Result:='mmSPI_SHADER_USER_DATA_ES_3'; - mmSPI_SHADER_USER_DATA_ES_4 :Result:='mmSPI_SHADER_USER_DATA_ES_4'; - mmSPI_SHADER_USER_DATA_ES_5 :Result:='mmSPI_SHADER_USER_DATA_ES_5'; - mmSPI_SHADER_USER_DATA_ES_6 :Result:='mmSPI_SHADER_USER_DATA_ES_6'; - mmSPI_SHADER_USER_DATA_ES_7 :Result:='mmSPI_SHADER_USER_DATA_ES_7'; - mmSPI_SHADER_USER_DATA_ES_8 :Result:='mmSPI_SHADER_USER_DATA_ES_8'; - mmSPI_SHADER_USER_DATA_ES_9 :Result:='mmSPI_SHADER_USER_DATA_ES_9'; - mmSPI_SHADER_USER_DATA_ES_10 :Result:='mmSPI_SHADER_USER_DATA_ES_10'; - mmSPI_SHADER_USER_DATA_ES_11 :Result:='mmSPI_SHADER_USER_DATA_ES_11'; - mmSPI_SHADER_USER_DATA_ES_12 :Result:='mmSPI_SHADER_USER_DATA_ES_12'; - mmSPI_SHADER_USER_DATA_ES_13 :Result:='mmSPI_SHADER_USER_DATA_ES_13'; - mmSPI_SHADER_USER_DATA_ES_14 :Result:='mmSPI_SHADER_USER_DATA_ES_14'; - mmSPI_SHADER_USER_DATA_ES_15 :Result:='mmSPI_SHADER_USER_DATA_ES_15'; - mmSPI_SHADER_PGM_RSRC2_LS_ES :Result:='mmSPI_SHADER_PGM_RSRC2_LS_ES'; - mmSPI_SHADER_TBA_LO_HS :Result:='mmSPI_SHADER_TBA_LO_HS'; - mmSPI_SHADER_TBA_HI_HS :Result:='mmSPI_SHADER_TBA_HI_HS'; - mmSPI_SHADER_TMA_LO_HS :Result:='mmSPI_SHADER_TMA_LO_HS'; - mmSPI_SHADER_TMA_HI_HS :Result:='mmSPI_SHADER_TMA_HI_HS'; - mmSPI_SHADER_PGM_RSRC3_HS :Result:='mmSPI_SHADER_PGM_RSRC3_HS'; - mmSPI_SHADER_PGM_LO_HS :Result:='mmSPI_SHADER_PGM_LO_HS'; - mmSPI_SHADER_PGM_HI_HS :Result:='mmSPI_SHADER_PGM_HI_HS'; - mmSPI_SHADER_PGM_RSRC1_HS :Result:='mmSPI_SHADER_PGM_RSRC1_HS'; - mmSPI_SHADER_PGM_RSRC2_HS :Result:='mmSPI_SHADER_PGM_RSRC2_HS'; - mmSPI_SHADER_USER_DATA_HS_0 :Result:='mmSPI_SHADER_USER_DATA_HS_0'; - mmSPI_SHADER_USER_DATA_HS_1 :Result:='mmSPI_SHADER_USER_DATA_HS_1'; - mmSPI_SHADER_USER_DATA_HS_2 :Result:='mmSPI_SHADER_USER_DATA_HS_2'; - mmSPI_SHADER_USER_DATA_HS_3 :Result:='mmSPI_SHADER_USER_DATA_HS_3'; - mmSPI_SHADER_USER_DATA_HS_4 :Result:='mmSPI_SHADER_USER_DATA_HS_4'; - mmSPI_SHADER_USER_DATA_HS_5 :Result:='mmSPI_SHADER_USER_DATA_HS_5'; - mmSPI_SHADER_USER_DATA_HS_6 :Result:='mmSPI_SHADER_USER_DATA_HS_6'; - mmSPI_SHADER_USER_DATA_HS_7 :Result:='mmSPI_SHADER_USER_DATA_HS_7'; - mmSPI_SHADER_USER_DATA_HS_8 :Result:='mmSPI_SHADER_USER_DATA_HS_8'; - mmSPI_SHADER_USER_DATA_HS_9 :Result:='mmSPI_SHADER_USER_DATA_HS_9'; - mmSPI_SHADER_USER_DATA_HS_10 :Result:='mmSPI_SHADER_USER_DATA_HS_10'; - mmSPI_SHADER_USER_DATA_HS_11 :Result:='mmSPI_SHADER_USER_DATA_HS_11'; - mmSPI_SHADER_USER_DATA_HS_12 :Result:='mmSPI_SHADER_USER_DATA_HS_12'; - mmSPI_SHADER_USER_DATA_HS_13 :Result:='mmSPI_SHADER_USER_DATA_HS_13'; - mmSPI_SHADER_USER_DATA_HS_14 :Result:='mmSPI_SHADER_USER_DATA_HS_14'; - mmSPI_SHADER_USER_DATA_HS_15 :Result:='mmSPI_SHADER_USER_DATA_HS_15'; - mmSPI_SHADER_PGM_RSRC2_LS_HS :Result:='mmSPI_SHADER_PGM_RSRC2_LS_HS'; - mmSPI_SHADER_TBA_LO_LS :Result:='mmSPI_SHADER_TBA_LO_LS'; - mmSPI_SHADER_TBA_HI_LS :Result:='mmSPI_SHADER_TBA_HI_LS'; - mmSPI_SHADER_TMA_LO_LS :Result:='mmSPI_SHADER_TMA_LO_LS'; - mmSPI_SHADER_TMA_HI_LS :Result:='mmSPI_SHADER_TMA_HI_LS'; - mmSPI_SHADER_PGM_RSRC3_LS :Result:='mmSPI_SHADER_PGM_RSRC3_LS'; - mmSPI_SHADER_PGM_LO_LS :Result:='mmSPI_SHADER_PGM_LO_LS'; - mmSPI_SHADER_PGM_HI_LS :Result:='mmSPI_SHADER_PGM_HI_LS'; - mmSPI_SHADER_PGM_RSRC1_LS :Result:='mmSPI_SHADER_PGM_RSRC1_LS'; - mmSPI_SHADER_PGM_RSRC2_LS :Result:='mmSPI_SHADER_PGM_RSRC2_LS'; - mmSPI_SHADER_USER_DATA_LS_0 :Result:='mmSPI_SHADER_USER_DATA_LS_0'; - mmSPI_SHADER_USER_DATA_LS_1 :Result:='mmSPI_SHADER_USER_DATA_LS_1'; - mmSPI_SHADER_USER_DATA_LS_2 :Result:='mmSPI_SHADER_USER_DATA_LS_2'; - mmSPI_SHADER_USER_DATA_LS_3 :Result:='mmSPI_SHADER_USER_DATA_LS_3'; - mmSPI_SHADER_USER_DATA_LS_4 :Result:='mmSPI_SHADER_USER_DATA_LS_4'; - mmSPI_SHADER_USER_DATA_LS_5 :Result:='mmSPI_SHADER_USER_DATA_LS_5'; - mmSPI_SHADER_USER_DATA_LS_6 :Result:='mmSPI_SHADER_USER_DATA_LS_6'; - mmSPI_SHADER_USER_DATA_LS_7 :Result:='mmSPI_SHADER_USER_DATA_LS_7'; - mmSPI_SHADER_USER_DATA_LS_8 :Result:='mmSPI_SHADER_USER_DATA_LS_8'; - mmSPI_SHADER_USER_DATA_LS_9 :Result:='mmSPI_SHADER_USER_DATA_LS_9'; - mmSPI_SHADER_USER_DATA_LS_10 :Result:='mmSPI_SHADER_USER_DATA_LS_10'; - mmSPI_SHADER_USER_DATA_LS_11 :Result:='mmSPI_SHADER_USER_DATA_LS_11'; - mmSPI_SHADER_USER_DATA_LS_12 :Result:='mmSPI_SHADER_USER_DATA_LS_12'; - mmSPI_SHADER_USER_DATA_LS_13 :Result:='mmSPI_SHADER_USER_DATA_LS_13'; - mmSPI_SHADER_USER_DATA_LS_14 :Result:='mmSPI_SHADER_USER_DATA_LS_14'; - mmSPI_SHADER_USER_DATA_LS_15 :Result:='mmSPI_SHADER_USER_DATA_LS_15'; - mmCOMPUTE_DISPATCH_INITIATOR :Result:='mmCOMPUTE_DISPATCH_INITIATOR'; - mmCOMPUTE_DIM_X :Result:='mmCOMPUTE_DIM_X'; - mmCOMPUTE_DIM_Y :Result:='mmCOMPUTE_DIM_Y'; - mmCOMPUTE_DIM_Z :Result:='mmCOMPUTE_DIM_Z'; - mmCOMPUTE_START_X :Result:='mmCOMPUTE_START_X'; - mmCOMPUTE_START_Y :Result:='mmCOMPUTE_START_Y'; - mmCOMPUTE_START_Z :Result:='mmCOMPUTE_START_Z'; - mmCOMPUTE_NUM_THREAD_X :Result:='mmCOMPUTE_NUM_THREAD_X'; - mmCOMPUTE_NUM_THREAD_Y :Result:='mmCOMPUTE_NUM_THREAD_Y'; - mmCOMPUTE_NUM_THREAD_Z :Result:='mmCOMPUTE_NUM_THREAD_Z'; - mmCOMPUTE_PIPELINESTAT_ENABLE :Result:='mmCOMPUTE_PIPELINESTAT_ENABLE'; - mmCOMPUTE_PERFCOUNT_ENABLE :Result:='mmCOMPUTE_PERFCOUNT_ENABLE'; - mmCOMPUTE_PGM_LO :Result:='mmCOMPUTE_PGM_LO'; - mmCOMPUTE_PGM_HI :Result:='mmCOMPUTE_PGM_HI'; - mmCOMPUTE_TBA_LO :Result:='mmCOMPUTE_TBA_LO'; - mmCOMPUTE_TBA_HI :Result:='mmCOMPUTE_TBA_HI'; - mmCOMPUTE_TMA_LO :Result:='mmCOMPUTE_TMA_LO'; - mmCOMPUTE_TMA_HI :Result:='mmCOMPUTE_TMA_HI'; - mmCOMPUTE_PGM_RSRC1 :Result:='mmCOMPUTE_PGM_RSRC1'; - mmCOMPUTE_PGM_RSRC2 :Result:='mmCOMPUTE_PGM_RSRC2'; - mmCOMPUTE_VMID :Result:='mmCOMPUTE_VMID'; - mmCOMPUTE_RESOURCE_LIMITS :Result:='mmCOMPUTE_RESOURCE_LIMITS'; - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE0'; - mmCOMPUTE_STATIC_THREAD_MGMT_SE1 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE1'; - mmCOMPUTE_TMPRING_SIZE :Result:='mmCOMPUTE_TMPRING_SIZE'; - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE2'; - mmCOMPUTE_STATIC_THREAD_MGMT_SE3 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE3'; - mmCOMPUTE_RESTART_X :Result:='mmCOMPUTE_RESTART_X'; - mmCOMPUTE_RESTART_Y :Result:='mmCOMPUTE_RESTART_Y'; - mmCOMPUTE_RESTART_Z :Result:='mmCOMPUTE_RESTART_Z'; - mmCOMPUTE_THREAD_TRACE_ENABLE :Result:='mmCOMPUTE_THREAD_TRACE_ENABLE'; - mmCOMPUTE_MISC_RESERVED :Result:='mmCOMPUTE_MISC_RESERVED'; - mmCOMPUTE_DISPATCH_ID :Result:='mmCOMPUTE_DISPATCH_ID'; - mmCOMPUTE_THREADGROUP_ID :Result:='mmCOMPUTE_THREADGROUP_ID'; - mmCOMPUTE_RELAUNCH :Result:='mmCOMPUTE_RELAUNCH'; - mmCOMPUTE_WAVE_RESTORE_ADDR_LO :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_LO'; - mmCOMPUTE_WAVE_RESTORE_ADDR_HI :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_HI'; - mmCOMPUTE_WAVE_RESTORE_CONTROL :Result:='mmCOMPUTE_WAVE_RESTORE_CONTROL'; - mmCOMPUTE_USER_DATA_0 :Result:='mmCOMPUTE_USER_DATA_0'; - mmCOMPUTE_USER_DATA_1 :Result:='mmCOMPUTE_USER_DATA_1'; - mmCOMPUTE_USER_DATA_2 :Result:='mmCOMPUTE_USER_DATA_2'; - mmCOMPUTE_USER_DATA_3 :Result:='mmCOMPUTE_USER_DATA_3'; - mmCOMPUTE_USER_DATA_4 :Result:='mmCOMPUTE_USER_DATA_4'; - mmCOMPUTE_USER_DATA_5 :Result:='mmCOMPUTE_USER_DATA_5'; - mmCOMPUTE_USER_DATA_6 :Result:='mmCOMPUTE_USER_DATA_6'; - mmCOMPUTE_USER_DATA_7 :Result:='mmCOMPUTE_USER_DATA_7'; - mmCOMPUTE_USER_DATA_8 :Result:='mmCOMPUTE_USER_DATA_8'; - mmCOMPUTE_USER_DATA_9 :Result:='mmCOMPUTE_USER_DATA_9'; - mmCOMPUTE_USER_DATA_10 :Result:='mmCOMPUTE_USER_DATA_10'; - mmCOMPUTE_USER_DATA_11 :Result:='mmCOMPUTE_USER_DATA_11'; - mmCOMPUTE_USER_DATA_12 :Result:='mmCOMPUTE_USER_DATA_12'; - mmCOMPUTE_USER_DATA_13 :Result:='mmCOMPUTE_USER_DATA_13'; - mmCOMPUTE_USER_DATA_14 :Result:='mmCOMPUTE_USER_DATA_14'; - mmCOMPUTE_USER_DATA_15 :Result:='mmCOMPUTE_USER_DATA_15'; - mmCOMPUTE_NOWHERE :Result:='mmCOMPUTE_NOWHERE'; - mmCP_DFY_CNTL :Result:='mmCP_DFY_CNTL'; - mmCP_DFY_STAT :Result:='mmCP_DFY_STAT'; - mmCP_DFY_ADDR_HI :Result:='mmCP_DFY_ADDR_HI'; - mmCP_DFY_ADDR_LO :Result:='mmCP_DFY_ADDR_LO'; - mmCP_DFY_DATA_0 :Result:='mmCP_DFY_DATA_0'; - mmCP_DFY_DATA_1 :Result:='mmCP_DFY_DATA_1'; - mmCP_DFY_DATA_2 :Result:='mmCP_DFY_DATA_2'; - mmCP_DFY_DATA_3 :Result:='mmCP_DFY_DATA_3'; - mmCP_DFY_DATA_4 :Result:='mmCP_DFY_DATA_4'; - mmCP_DFY_DATA_5 :Result:='mmCP_DFY_DATA_5'; - mmCP_DFY_DATA_6 :Result:='mmCP_DFY_DATA_6'; - mmCP_DFY_DATA_7 :Result:='mmCP_DFY_DATA_7'; - mmCP_DFY_DATA_8 :Result:='mmCP_DFY_DATA_8'; - mmCP_DFY_DATA_9 :Result:='mmCP_DFY_DATA_9'; - mmCP_DFY_DATA_10 :Result:='mmCP_DFY_DATA_10'; - mmCP_DFY_DATA_11 :Result:='mmCP_DFY_DATA_11'; - mmCP_DFY_DATA_12 :Result:='mmCP_DFY_DATA_12'; - mmCP_DFY_DATA_13 :Result:='mmCP_DFY_DATA_13'; - mmCP_DFY_DATA_14 :Result:='mmCP_DFY_DATA_14'; - mmCP_DFY_DATA_15 :Result:='mmCP_DFY_DATA_15'; - mmCP_DFY_CMD :Result:='mmCP_DFY_CMD'; - mmCP_CPC_MGCG_SYNC_CNTL :Result:='mmCP_CPC_MGCG_SYNC_CNTL'; - mmCP_VIRT_STATUS :Result:='mmCP_VIRT_STATUS'; - mmCP_RB0_BASE :Result:='mmCP_RB0_BASE'; - mmCP_RB0_CNTL :Result:='mmCP_RB0_CNTL'; - mmCP_RB0_RPTR_ADDR :Result:='mmCP_RB0_RPTR_ADDR'; - mmCP_RB0_RPTR_ADDR_HI :Result:='mmCP_RB0_RPTR_ADDR_HI'; - mmCP_RB0_WPTR :Result:='mmCP_RB0_WPTR'; - mmCP_INT_CNTL :Result:='mmCP_INT_CNTL'; - mmCP_INT_STATUS :Result:='mmCP_INT_STATUS'; - mmCP_DEVICE_ID :Result:='mmCP_DEVICE_ID'; - mmCP_ME0_PIPE_PRIORITY_CNTS :Result:='mmCP_ME0_PIPE_PRIORITY_CNTS'; - mmCP_ME0_PIPE0_PRIORITY :Result:='mmCP_ME0_PIPE0_PRIORITY'; - mmCP_ME0_PIPE1_PRIORITY :Result:='mmCP_ME0_PIPE1_PRIORITY'; - mmCP_ME0_PIPE2_PRIORITY :Result:='mmCP_ME0_PIPE2_PRIORITY'; - mmCP_ENDIAN_SWAP :Result:='mmCP_ENDIAN_SWAP'; - mmCP_ME0_PIPE0_VMID :Result:='mmCP_ME0_PIPE0_VMID'; - mmCP_ME0_PIPE1_VMID :Result:='mmCP_ME0_PIPE1_VMID'; - mmCP_MEC_DOORBELL_RANGE_LOWER :Result:='mmCP_MEC_DOORBELL_RANGE_LOWER'; - mmCP_MEC_DOORBELL_RANGE_UPPER :Result:='mmCP_MEC_DOORBELL_RANGE_UPPER'; - mmCP_RB1_BASE :Result:='mmCP_RB1_BASE'; - mmCP_RB1_CNTL :Result:='mmCP_RB1_CNTL'; - mmCP_RB1_RPTR_ADDR :Result:='mmCP_RB1_RPTR_ADDR'; - mmCP_RB1_RPTR_ADDR_HI :Result:='mmCP_RB1_RPTR_ADDR_HI'; - mmCP_RB1_WPTR :Result:='mmCP_RB1_WPTR'; - mmCP_RB2_BASE :Result:='mmCP_RB2_BASE'; - mmCP_RB2_CNTL :Result:='mmCP_RB2_CNTL'; - mmCP_RB2_RPTR_ADDR :Result:='mmCP_RB2_RPTR_ADDR'; - mmCP_RB2_RPTR_ADDR_HI :Result:='mmCP_RB2_RPTR_ADDR_HI'; - mmCP_RB2_WPTR :Result:='mmCP_RB2_WPTR'; - mmCP_INT_CNTL_RING0 :Result:='mmCP_INT_CNTL_RING0'; - mmCP_INT_CNTL_RING1 :Result:='mmCP_INT_CNTL_RING1'; - mmCP_INT_CNTL_RING2 :Result:='mmCP_INT_CNTL_RING2'; - mmCP_INT_STATUS_RING0 :Result:='mmCP_INT_STATUS_RING0'; - mmCP_INT_STATUS_RING1 :Result:='mmCP_INT_STATUS_RING1'; - mmCP_INT_STATUS_RING2 :Result:='mmCP_INT_STATUS_RING2'; - mmCP_PWR_CNTL :Result:='mmCP_PWR_CNTL'; - mmCP_MEM_SLP_CNTL :Result:='mmCP_MEM_SLP_CNTL'; - mmCP_ECC_FIRSTOCCURRENCE :Result:='mmCP_ECC_FIRSTOCCURRENCE'; - mmCP_ECC_FIRSTOCCURRENCE_RING0 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING0'; - mmCP_ECC_FIRSTOCCURRENCE_RING1 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING1'; - mmCP_ECC_FIRSTOCCURRENCE_RING2 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING2'; - mmCP_DEBUG :Result:='mmCP_DEBUG'; - mmCP_PQ_WPTR_POLL_CNTL :Result:='mmCP_PQ_WPTR_POLL_CNTL'; - mmCP_PQ_WPTR_POLL_CNTL1 :Result:='mmCP_PQ_WPTR_POLL_CNTL1'; - mmCP_ME1_PIPE0_INT_CNTL :Result:='mmCP_ME1_PIPE0_INT_CNTL'; - mmCP_ME1_PIPE1_INT_CNTL :Result:='mmCP_ME1_PIPE1_INT_CNTL'; - mmCP_ME1_PIPE2_INT_CNTL :Result:='mmCP_ME1_PIPE2_INT_CNTL'; - mmCP_ME1_PIPE3_INT_CNTL :Result:='mmCP_ME1_PIPE3_INT_CNTL'; - mmCP_ME2_PIPE0_INT_CNTL :Result:='mmCP_ME2_PIPE0_INT_CNTL'; - mmCP_ME2_PIPE1_INT_CNTL :Result:='mmCP_ME2_PIPE1_INT_CNTL'; - mmCP_ME2_PIPE2_INT_CNTL :Result:='mmCP_ME2_PIPE2_INT_CNTL'; - mmCP_ME2_PIPE3_INT_CNTL :Result:='mmCP_ME2_PIPE3_INT_CNTL'; - mmCP_ME1_PIPE0_INT_STATUS :Result:='mmCP_ME1_PIPE0_INT_STATUS'; - mmCP_ME1_PIPE1_INT_STATUS :Result:='mmCP_ME1_PIPE1_INT_STATUS'; - mmCP_ME1_PIPE2_INT_STATUS :Result:='mmCP_ME1_PIPE2_INT_STATUS'; - mmCP_ME1_PIPE3_INT_STATUS :Result:='mmCP_ME1_PIPE3_INT_STATUS'; - mmCP_ME2_PIPE0_INT_STATUS :Result:='mmCP_ME2_PIPE0_INT_STATUS'; - mmCP_ME2_PIPE1_INT_STATUS :Result:='mmCP_ME2_PIPE1_INT_STATUS'; - mmCP_ME2_PIPE2_INT_STATUS :Result:='mmCP_ME2_PIPE2_INT_STATUS'; - mmCP_ME2_PIPE3_INT_STATUS :Result:='mmCP_ME2_PIPE3_INT_STATUS'; - mmCP_ME1_INT_STAT_DEBUG :Result:='mmCP_ME1_INT_STAT_DEBUG'; - mmCP_ME2_INT_STAT_DEBUG :Result:='mmCP_ME2_INT_STAT_DEBUG'; - mmCP_ME1_PIPE_PRIORITY_CNTS :Result:='mmCP_ME1_PIPE_PRIORITY_CNTS'; - mmCP_ME1_PIPE0_PRIORITY :Result:='mmCP_ME1_PIPE0_PRIORITY'; - mmCP_ME1_PIPE1_PRIORITY :Result:='mmCP_ME1_PIPE1_PRIORITY'; - mmCP_ME1_PIPE2_PRIORITY :Result:='mmCP_ME1_PIPE2_PRIORITY'; - mmCP_ME1_PIPE3_PRIORITY :Result:='mmCP_ME1_PIPE3_PRIORITY'; - mmCP_ME2_PIPE_PRIORITY_CNTS :Result:='mmCP_ME2_PIPE_PRIORITY_CNTS'; - mmCP_ME2_PIPE0_PRIORITY :Result:='mmCP_ME2_PIPE0_PRIORITY'; - mmCP_ME2_PIPE1_PRIORITY :Result:='mmCP_ME2_PIPE1_PRIORITY'; - mmCP_ME2_PIPE2_PRIORITY :Result:='mmCP_ME2_PIPE2_PRIORITY'; - mmCP_ME2_PIPE3_PRIORITY :Result:='mmCP_ME2_PIPE3_PRIORITY'; - mmCP_CE_PRGRM_CNTR_START :Result:='mmCP_CE_PRGRM_CNTR_START'; - mmCP_PFP_PRGRM_CNTR_START :Result:='mmCP_PFP_PRGRM_CNTR_START'; - mmCP_MEC1_PRGRM_CNTR_START :Result:='mmCP_MEC1_PRGRM_CNTR_START'; - mmCP_MEC2_PRGRM_CNTR_START :Result:='mmCP_MEC2_PRGRM_CNTR_START'; - mmCP_CE_INTR_ROUTINE_START :Result:='mmCP_CE_INTR_ROUTINE_START'; - mmCP_PFP_INTR_ROUTINE_START :Result:='mmCP_PFP_INTR_ROUTINE_START'; - mmCP_MEC1_INTR_ROUTINE_START :Result:='mmCP_MEC1_INTR_ROUTINE_START'; - mmCP_MEC2_INTR_ROUTINE_START :Result:='mmCP_MEC2_INTR_ROUTINE_START'; - mmCP_CONTEXT_CNTL :Result:='mmCP_CONTEXT_CNTL'; - mmCP_MAX_CONTEXT :Result:='mmCP_MAX_CONTEXT'; - mmCP_IQ_WAIT_TIME1 :Result:='mmCP_IQ_WAIT_TIME1'; - mmCP_IQ_WAIT_TIME2 :Result:='mmCP_IQ_WAIT_TIME2'; - mmCP_RB0_BASE_HI :Result:='mmCP_RB0_BASE_HI'; - mmCP_RB1_BASE_HI :Result:='mmCP_RB1_BASE_HI'; - mmCP_VMID_RESET :Result:='mmCP_VMID_RESET'; - mmCPC_INT_CNTL :Result:='mmCPC_INT_CNTL'; - mmCPC_INT_STATUS :Result:='mmCPC_INT_STATUS'; - mmCP_VMID_PREEMPT :Result:='mmCP_VMID_PREEMPT'; - mmCPC_INT_CNTX_ID :Result:='mmCPC_INT_CNTX_ID'; - mmCP_PQ_STATUS :Result:='mmCP_PQ_STATUS'; - mmCP_CPC_IC_BASE_LO :Result:='mmCP_CPC_IC_BASE_LO'; - mmCP_CPC_IC_BASE_HI :Result:='mmCP_CPC_IC_BASE_HI'; - mmCP_CPC_IC_BASE_CNTL :Result:='mmCP_CPC_IC_BASE_CNTL'; - mmCP_CPC_IC_OP_CNTL :Result:='mmCP_CPC_IC_OP_CNTL'; - mmCP_MEC1_F32_INT_DIS :Result:='mmCP_MEC1_F32_INT_DIS'; - mmCP_MEC2_F32_INT_DIS :Result:='mmCP_MEC2_F32_INT_DIS'; - mmCP_VMID_STATUS :Result:='mmCP_VMID_STATUS'; - mmSPI_ARB_PRIORITY :Result:='mmSPI_ARB_PRIORITY'; - mmSPI_ARB_CYCLES_0 :Result:='mmSPI_ARB_CYCLES_0'; - mmSPI_ARB_CYCLES_1 :Result:='mmSPI_ARB_CYCLES_1'; - mmSPI_CDBG_SYS_GFX :Result:='mmSPI_CDBG_SYS_GFX'; - mmSPI_CDBG_SYS_HP3D :Result:='mmSPI_CDBG_SYS_HP3D'; - mmSPI_CDBG_SYS_CS0 :Result:='mmSPI_CDBG_SYS_CS0'; - mmSPI_CDBG_SYS_CS1 :Result:='mmSPI_CDBG_SYS_CS1'; - mmSPI_WCL_PIPE_PERCENT_GFX :Result:='mmSPI_WCL_PIPE_PERCENT_GFX'; - mmSPI_WCL_PIPE_PERCENT_HP3D :Result:='mmSPI_WCL_PIPE_PERCENT_HP3D'; - mmSPI_WCL_PIPE_PERCENT_CS0 :Result:='mmSPI_WCL_PIPE_PERCENT_CS0'; - mmSPI_WCL_PIPE_PERCENT_CS1 :Result:='mmSPI_WCL_PIPE_PERCENT_CS1'; - mmSPI_WCL_PIPE_PERCENT_CS2 :Result:='mmSPI_WCL_PIPE_PERCENT_CS2'; - mmSPI_WCL_PIPE_PERCENT_CS3 :Result:='mmSPI_WCL_PIPE_PERCENT_CS3'; - mmSPI_WCL_PIPE_PERCENT_CS4 :Result:='mmSPI_WCL_PIPE_PERCENT_CS4'; - mmSPI_WCL_PIPE_PERCENT_CS5 :Result:='mmSPI_WCL_PIPE_PERCENT_CS5'; - mmSPI_WCL_PIPE_PERCENT_CS6 :Result:='mmSPI_WCL_PIPE_PERCENT_CS6'; - mmSPI_WCL_PIPE_PERCENT_CS7 :Result:='mmSPI_WCL_PIPE_PERCENT_CS7'; - mmSPI_GDBG_WAVE_CNTL :Result:='mmSPI_GDBG_WAVE_CNTL'; - mmSPI_GDBG_TRAP_CONFIG :Result:='mmSPI_GDBG_TRAP_CONFIG'; - mmSPI_GDBG_TRAP_MASK :Result:='mmSPI_GDBG_TRAP_MASK'; - mmSPI_GDBG_TBA_LO :Result:='mmSPI_GDBG_TBA_LO'; - mmSPI_GDBG_TBA_HI :Result:='mmSPI_GDBG_TBA_HI'; - mmSPI_GDBG_TMA_LO :Result:='mmSPI_GDBG_TMA_LO'; - mmSPI_GDBG_TMA_HI :Result:='mmSPI_GDBG_TMA_HI'; - mmSPI_GDBG_TRAP_DATA0 :Result:='mmSPI_GDBG_TRAP_DATA0'; - mmSPI_GDBG_TRAP_DATA1 :Result:='mmSPI_GDBG_TRAP_DATA1'; - mmSPI_RESET_DEBUG :Result:='mmSPI_RESET_DEBUG'; - mmSPI_COMPUTE_QUEUE_RESET :Result:='mmSPI_COMPUTE_QUEUE_RESET'; - mmSPI_RESOURCE_RESERVE_CU_0 :Result:='mmSPI_RESOURCE_RESERVE_CU_0'; - mmSPI_RESOURCE_RESERVE_CU_1 :Result:='mmSPI_RESOURCE_RESERVE_CU_1'; - mmSPI_RESOURCE_RESERVE_CU_2 :Result:='mmSPI_RESOURCE_RESERVE_CU_2'; - mmSPI_RESOURCE_RESERVE_CU_3 :Result:='mmSPI_RESOURCE_RESERVE_CU_3'; - mmSPI_RESOURCE_RESERVE_CU_4 :Result:='mmSPI_RESOURCE_RESERVE_CU_4'; - mmSPI_RESOURCE_RESERVE_CU_5 :Result:='mmSPI_RESOURCE_RESERVE_CU_5'; - mmSPI_RESOURCE_RESERVE_CU_6 :Result:='mmSPI_RESOURCE_RESERVE_CU_6'; - mmSPI_RESOURCE_RESERVE_CU_7 :Result:='mmSPI_RESOURCE_RESERVE_CU_7'; - mmSPI_RESOURCE_RESERVE_CU_8 :Result:='mmSPI_RESOURCE_RESERVE_CU_8'; - mmSPI_RESOURCE_RESERVE_CU_9 :Result:='mmSPI_RESOURCE_RESERVE_CU_9'; - mmSPI_RESOURCE_RESERVE_EN_CU_0 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_0'; - mmSPI_RESOURCE_RESERVE_EN_CU_1 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_1'; - mmSPI_RESOURCE_RESERVE_EN_CU_2 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_2'; - mmSPI_RESOURCE_RESERVE_EN_CU_3 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_3'; - mmSPI_RESOURCE_RESERVE_EN_CU_4 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_4'; - mmSPI_RESOURCE_RESERVE_EN_CU_5 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_5'; - mmSPI_RESOURCE_RESERVE_EN_CU_6 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_6'; - mmSPI_RESOURCE_RESERVE_EN_CU_7 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_7'; - mmSPI_RESOURCE_RESERVE_EN_CU_8 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_8'; - mmSPI_RESOURCE_RESERVE_EN_CU_9 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_9'; - mmSPI_RESOURCE_RESERVE_CU_10 :Result:='mmSPI_RESOURCE_RESERVE_CU_10'; - mmSPI_RESOURCE_RESERVE_CU_11 :Result:='mmSPI_RESOURCE_RESERVE_CU_11'; - mmSPI_RESOURCE_RESERVE_EN_CU_10 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_10'; - mmSPI_RESOURCE_RESERVE_EN_CU_11 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_11'; - mmSPI_RESOURCE_RESERVE_CU_12 :Result:='mmSPI_RESOURCE_RESERVE_CU_12'; - mmSPI_RESOURCE_RESERVE_CU_13 :Result:='mmSPI_RESOURCE_RESERVE_CU_13'; - mmSPI_RESOURCE_RESERVE_CU_14 :Result:='mmSPI_RESOURCE_RESERVE_CU_14'; - mmSPI_RESOURCE_RESERVE_CU_15 :Result:='mmSPI_RESOURCE_RESERVE_CU_15'; - mmSPI_RESOURCE_RESERVE_EN_CU_12 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_12'; - mmSPI_RESOURCE_RESERVE_EN_CU_13 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_13'; - mmSPI_RESOURCE_RESERVE_EN_CU_14 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_14'; - mmSPI_RESOURCE_RESERVE_EN_CU_15 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_15'; - mmSPI_COMPUTE_WF_CTX_SAVE :Result:='mmSPI_COMPUTE_WF_CTX_SAVE'; - mmCP_HPD_ROQ_OFFSETS :Result:='mmCP_HPD_ROQ_OFFSETS'; - mmCP_HPD_STATUS0 :Result:='mmCP_HPD_STATUS0'; - mmCP_MQD_BASE_ADDR :Result:='mmCP_MQD_BASE_ADDR'; - mmCP_MQD_BASE_ADDR_HI :Result:='mmCP_MQD_BASE_ADDR_HI'; - mmCP_HQD_ACTIVE :Result:='mmCP_HQD_ACTIVE'; - mmCP_HQD_VMID :Result:='mmCP_HQD_VMID'; - mmCP_HQD_PERSISTENT_STATE :Result:='mmCP_HQD_PERSISTENT_STATE'; - mmCP_HQD_PIPE_PRIORITY :Result:='mmCP_HQD_PIPE_PRIORITY'; - mmCP_HQD_QUEUE_PRIORITY :Result:='mmCP_HQD_QUEUE_PRIORITY'; - mmCP_HQD_QUANTUM :Result:='mmCP_HQD_QUANTUM'; - mmCP_HQD_PQ_BASE :Result:='mmCP_HQD_PQ_BASE'; - mmCP_HQD_PQ_BASE_HI :Result:='mmCP_HQD_PQ_BASE_HI'; - mmCP_HQD_PQ_RPTR :Result:='mmCP_HQD_PQ_RPTR'; - mmCP_HQD_PQ_RPTR_REPORT_ADDR :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR'; - mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI'; - mmCP_HQD_PQ_WPTR_POLL_ADDR :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR'; - mmCP_HQD_PQ_WPTR_POLL_ADDR_HI :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR_HI'; - mmCP_HQD_PQ_DOORBELL_CONTROL :Result:='mmCP_HQD_PQ_DOORBELL_CONTROL'; - mmCP_HQD_PQ_WPTR :Result:='mmCP_HQD_PQ_WPTR'; - mmCP_HQD_PQ_CONTROL :Result:='mmCP_HQD_PQ_CONTROL'; - mmCP_HQD_IB_BASE_ADDR :Result:='mmCP_HQD_IB_BASE_ADDR'; - mmCP_HQD_IB_BASE_ADDR_HI :Result:='mmCP_HQD_IB_BASE_ADDR_HI'; - mmCP_HQD_IB_RPTR :Result:='mmCP_HQD_IB_RPTR'; - mmCP_HQD_IB_CONTROL :Result:='mmCP_HQD_IB_CONTROL'; - mmCP_HQD_IQ_TIMER :Result:='mmCP_HQD_IQ_TIMER'; - mmCP_HQD_IQ_RPTR :Result:='mmCP_HQD_IQ_RPTR'; - mmCP_HQD_DEQUEUE_REQUEST :Result:='mmCP_HQD_DEQUEUE_REQUEST'; - mmCP_HQD_OFFLOAD :Result:='mmCP_HQD_OFFLOAD'; - mmCP_HQD_SEMA_CMD :Result:='mmCP_HQD_SEMA_CMD'; - mmCP_HQD_MSG_TYPE :Result:='mmCP_HQD_MSG_TYPE'; - mmCP_HQD_ATOMIC0_PREOP_LO :Result:='mmCP_HQD_ATOMIC0_PREOP_LO'; - mmCP_HQD_ATOMIC0_PREOP_HI :Result:='mmCP_HQD_ATOMIC0_PREOP_HI'; - mmCP_HQD_ATOMIC1_PREOP_LO :Result:='mmCP_HQD_ATOMIC1_PREOP_LO'; - mmCP_HQD_ATOMIC1_PREOP_HI :Result:='mmCP_HQD_ATOMIC1_PREOP_HI'; - mmCP_HQD_HQ_STATUS0 :Result:='mmCP_HQD_HQ_STATUS0'; - mmCP_HQD_HQ_CONTROL0 :Result:='mmCP_HQD_HQ_CONTROL0'; - mmCP_MQD_CONTROL :Result:='mmCP_MQD_CONTROL'; - mmCP_HQD_HQ_STATUS1 :Result:='mmCP_HQD_HQ_STATUS1'; - mmCP_HQD_HQ_CONTROL1 :Result:='mmCP_HQD_HQ_CONTROL1'; - mmCP_HQD_EOP_BASE_ADDR :Result:='mmCP_HQD_EOP_BASE_ADDR'; - mmCP_HQD_EOP_BASE_ADDR_HI :Result:='mmCP_HQD_EOP_BASE_ADDR_HI'; - mmCP_HQD_EOP_CONTROL :Result:='mmCP_HQD_EOP_CONTROL'; - mmCP_HQD_EOP_RPTR :Result:='mmCP_HQD_EOP_RPTR'; - mmCP_HQD_EOP_WPTR :Result:='mmCP_HQD_EOP_WPTR'; - mmCP_HQD_EOP_EVENTS :Result:='mmCP_HQD_EOP_EVENTS'; - mmCP_HQD_CTX_SAVE_BASE_ADDR_LO :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_LO'; - mmCP_HQD_CTX_SAVE_BASE_ADDR_HI :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_HI'; - mmCP_HQD_CTX_SAVE_CONTROL :Result:='mmCP_HQD_CTX_SAVE_CONTROL'; - mmCP_HQD_CNTL_STACK_OFFSET :Result:='mmCP_HQD_CNTL_STACK_OFFSET'; - mmCP_HQD_CNTL_STACK_SIZE :Result:='mmCP_HQD_CNTL_STACK_SIZE'; - mmCP_HQD_WG_STATE_OFFSET :Result:='mmCP_HQD_WG_STATE_OFFSET'; - mmCP_HQD_CTX_SAVE_SIZE :Result:='mmCP_HQD_CTX_SAVE_SIZE'; - mmCP_HQD_GDS_RESOURCE_STATE :Result:='mmCP_HQD_GDS_RESOURCE_STATE'; - mmCP_HQD_ERROR :Result:='mmCP_HQD_ERROR'; - mmCP_HQD_EOP_WPTR_MEM :Result:='mmCP_HQD_EOP_WPTR_MEM'; - mmCP_HQD_EOP_DONES :Result:='mmCP_HQD_EOP_DONES'; - mmTCP_WATCH0_ADDR_H :Result:='mmTCP_WATCH0_ADDR_H'; - mmTCP_WATCH0_ADDR_L :Result:='mmTCP_WATCH0_ADDR_L'; - mmTCP_WATCH0_CNTL :Result:='mmTCP_WATCH0_CNTL'; - mmTCP_WATCH1_ADDR_H :Result:='mmTCP_WATCH1_ADDR_H'; - mmTCP_WATCH1_ADDR_L :Result:='mmTCP_WATCH1_ADDR_L'; - mmTCP_WATCH1_CNTL :Result:='mmTCP_WATCH1_CNTL'; - mmTCP_WATCH2_ADDR_H :Result:='mmTCP_WATCH2_ADDR_H'; - mmTCP_WATCH2_ADDR_L :Result:='mmTCP_WATCH2_ADDR_L'; - mmTCP_WATCH2_CNTL :Result:='mmTCP_WATCH2_CNTL'; - mmTCP_WATCH3_ADDR_H :Result:='mmTCP_WATCH3_ADDR_H'; - mmTCP_WATCH3_ADDR_L :Result:='mmTCP_WATCH3_ADDR_L'; - mmTCP_WATCH3_CNTL :Result:='mmTCP_WATCH3_CNTL'; - mmTCP_GATCL1_CNTL :Result:='mmTCP_GATCL1_CNTL'; - mmTCP_ATC_EDC_GATCL1_CNT :Result:='mmTCP_ATC_EDC_GATCL1_CNT'; - mmTCP_GATCL1_DSM_CNTL :Result:='mmTCP_GATCL1_DSM_CNTL'; - mmTCP_DSM_CNTL :Result:='mmTCP_DSM_CNTL'; - mmTCP_CNTL2 :Result:='mmTCP_CNTL2'; - mmGDS_VMID0_BASE :Result:='mmGDS_VMID0_BASE'; - mmGDS_VMID0_SIZE :Result:='mmGDS_VMID0_SIZE'; - mmGDS_VMID1_BASE :Result:='mmGDS_VMID1_BASE'; - mmGDS_VMID1_SIZE :Result:='mmGDS_VMID1_SIZE'; - mmGDS_VMID2_BASE :Result:='mmGDS_VMID2_BASE'; - mmGDS_VMID2_SIZE :Result:='mmGDS_VMID2_SIZE'; - mmGDS_VMID3_BASE :Result:='mmGDS_VMID3_BASE'; - mmGDS_VMID3_SIZE :Result:='mmGDS_VMID3_SIZE'; - mmGDS_VMID4_BASE :Result:='mmGDS_VMID4_BASE'; - mmGDS_VMID4_SIZE :Result:='mmGDS_VMID4_SIZE'; - mmGDS_VMID5_BASE :Result:='mmGDS_VMID5_BASE'; - mmGDS_VMID5_SIZE :Result:='mmGDS_VMID5_SIZE'; - mmGDS_VMID6_BASE :Result:='mmGDS_VMID6_BASE'; - mmGDS_VMID6_SIZE :Result:='mmGDS_VMID6_SIZE'; - mmGDS_VMID7_BASE :Result:='mmGDS_VMID7_BASE'; - mmGDS_VMID7_SIZE :Result:='mmGDS_VMID7_SIZE'; - mmGDS_VMID8_BASE :Result:='mmGDS_VMID8_BASE'; - mmGDS_VMID8_SIZE :Result:='mmGDS_VMID8_SIZE'; - mmGDS_VMID9_BASE :Result:='mmGDS_VMID9_BASE'; - mmGDS_VMID9_SIZE :Result:='mmGDS_VMID9_SIZE'; - mmGDS_VMID10_BASE :Result:='mmGDS_VMID10_BASE'; - mmGDS_VMID10_SIZE :Result:='mmGDS_VMID10_SIZE'; - mmGDS_VMID11_BASE :Result:='mmGDS_VMID11_BASE'; - mmGDS_VMID11_SIZE :Result:='mmGDS_VMID11_SIZE'; - mmGDS_VMID12_BASE :Result:='mmGDS_VMID12_BASE'; - mmGDS_VMID12_SIZE :Result:='mmGDS_VMID12_SIZE'; - mmGDS_VMID13_BASE :Result:='mmGDS_VMID13_BASE'; - mmGDS_VMID13_SIZE :Result:='mmGDS_VMID13_SIZE'; - mmGDS_VMID14_BASE :Result:='mmGDS_VMID14_BASE'; - mmGDS_VMID14_SIZE :Result:='mmGDS_VMID14_SIZE'; - mmGDS_VMID15_BASE :Result:='mmGDS_VMID15_BASE'; - mmGDS_VMID15_SIZE :Result:='mmGDS_VMID15_SIZE'; - mmGDS_GWS_VMID0 :Result:='mmGDS_GWS_VMID0'; - mmGDS_GWS_VMID1 :Result:='mmGDS_GWS_VMID1'; - mmGDS_GWS_VMID2 :Result:='mmGDS_GWS_VMID2'; - mmGDS_GWS_VMID3 :Result:='mmGDS_GWS_VMID3'; - mmGDS_GWS_VMID4 :Result:='mmGDS_GWS_VMID4'; - mmGDS_GWS_VMID5 :Result:='mmGDS_GWS_VMID5'; - mmGDS_GWS_VMID6 :Result:='mmGDS_GWS_VMID6'; - mmGDS_GWS_VMID7 :Result:='mmGDS_GWS_VMID7'; - mmGDS_GWS_VMID8 :Result:='mmGDS_GWS_VMID8'; - mmGDS_GWS_VMID9 :Result:='mmGDS_GWS_VMID9'; - mmGDS_GWS_VMID10 :Result:='mmGDS_GWS_VMID10'; - mmGDS_GWS_VMID11 :Result:='mmGDS_GWS_VMID11'; - mmGDS_GWS_VMID12 :Result:='mmGDS_GWS_VMID12'; - mmGDS_GWS_VMID13 :Result:='mmGDS_GWS_VMID13'; - mmGDS_GWS_VMID14 :Result:='mmGDS_GWS_VMID14'; - mmGDS_GWS_VMID15 :Result:='mmGDS_GWS_VMID15'; - mmGDS_OA_VMID0 :Result:='mmGDS_OA_VMID0'; - mmGDS_OA_VMID1 :Result:='mmGDS_OA_VMID1'; - mmGDS_OA_VMID2 :Result:='mmGDS_OA_VMID2'; - mmGDS_OA_VMID3 :Result:='mmGDS_OA_VMID3'; - mmGDS_OA_VMID4 :Result:='mmGDS_OA_VMID4'; - mmGDS_OA_VMID5 :Result:='mmGDS_OA_VMID5'; - mmGDS_OA_VMID6 :Result:='mmGDS_OA_VMID6'; - mmGDS_OA_VMID7 :Result:='mmGDS_OA_VMID7'; - mmGDS_OA_VMID8 :Result:='mmGDS_OA_VMID8'; - mmGDS_OA_VMID9 :Result:='mmGDS_OA_VMID9'; - mmGDS_OA_VMID10 :Result:='mmGDS_OA_VMID10'; - mmGDS_OA_VMID11 :Result:='mmGDS_OA_VMID11'; - mmGDS_OA_VMID12 :Result:='mmGDS_OA_VMID12'; - mmGDS_OA_VMID13 :Result:='mmGDS_OA_VMID13'; - mmGDS_OA_VMID14 :Result:='mmGDS_OA_VMID14'; - mmGDS_OA_VMID15 :Result:='mmGDS_OA_VMID15'; - mmGDS_GWS_RESET0 :Result:='mmGDS_GWS_RESET0'; - mmGDS_GWS_RESET1 :Result:='mmGDS_GWS_RESET1'; - mmGDS_GWS_RESOURCE_RESET :Result:='mmGDS_GWS_RESOURCE_RESET'; - mmGDS_COMPUTE_MAX_WAVE_ID :Result:='mmGDS_COMPUTE_MAX_WAVE_ID'; - mmGDS_OA_RESET_MASK :Result:='mmGDS_OA_RESET_MASK'; - mmGDS_OA_RESET :Result:='mmGDS_OA_RESET'; - mmGDS_ENHANCE :Result:='mmGDS_ENHANCE'; - mmGDS_OA_CGPG_RESTORE :Result:='mmGDS_OA_CGPG_RESTORE'; - mmGDS_CS_CTXSW_STATUS :Result:='mmGDS_CS_CTXSW_STATUS'; - mmGDS_CS_CTXSW_CNT0 :Result:='mmGDS_CS_CTXSW_CNT0'; - mmGDS_CS_CTXSW_CNT1 :Result:='mmGDS_CS_CTXSW_CNT1'; - mmGDS_CS_CTXSW_CNT2 :Result:='mmGDS_CS_CTXSW_CNT2'; - mmGDS_CS_CTXSW_CNT3 :Result:='mmGDS_CS_CTXSW_CNT3'; - mmGDS_GFX_CTXSW_STATUS :Result:='mmGDS_GFX_CTXSW_STATUS'; - mmGDS_VS_CTXSW_CNT0 :Result:='mmGDS_VS_CTXSW_CNT0'; - mmGDS_VS_CTXSW_CNT1 :Result:='mmGDS_VS_CTXSW_CNT1'; - mmGDS_VS_CTXSW_CNT2 :Result:='mmGDS_VS_CTXSW_CNT2'; - mmGDS_VS_CTXSW_CNT3 :Result:='mmGDS_VS_CTXSW_CNT3'; - mmGDS_PS0_CTXSW_CNT0 :Result:='mmGDS_PS0_CTXSW_CNT0'; - mmGDS_PS0_CTXSW_CNT1 :Result:='mmGDS_PS0_CTXSW_CNT1'; - mmGDS_PS0_CTXSW_CNT2 :Result:='mmGDS_PS0_CTXSW_CNT2'; - mmGDS_PS0_CTXSW_CNT3 :Result:='mmGDS_PS0_CTXSW_CNT3'; - mmGDS_PS1_CTXSW_CNT0 :Result:='mmGDS_PS1_CTXSW_CNT0'; - mmGDS_PS1_CTXSW_CNT1 :Result:='mmGDS_PS1_CTXSW_CNT1'; - mmGDS_PS1_CTXSW_CNT2 :Result:='mmGDS_PS1_CTXSW_CNT2'; - mmGDS_PS1_CTXSW_CNT3 :Result:='mmGDS_PS1_CTXSW_CNT3'; - mmGDS_PS2_CTXSW_CNT0 :Result:='mmGDS_PS2_CTXSW_CNT0'; - mmGDS_PS2_CTXSW_CNT1 :Result:='mmGDS_PS2_CTXSW_CNT1'; - mmGDS_PS2_CTXSW_CNT2 :Result:='mmGDS_PS2_CTXSW_CNT2'; - mmGDS_PS2_CTXSW_CNT3 :Result:='mmGDS_PS2_CTXSW_CNT3'; - mmGDS_PS3_CTXSW_CNT0 :Result:='mmGDS_PS3_CTXSW_CNT0'; - mmGDS_PS3_CTXSW_CNT1 :Result:='mmGDS_PS3_CTXSW_CNT1'; - mmGDS_PS3_CTXSW_CNT2 :Result:='mmGDS_PS3_CTXSW_CNT2'; - mmGDS_PS3_CTXSW_CNT3 :Result:='mmGDS_PS3_CTXSW_CNT3'; - mmGDS_PS4_CTXSW_CNT0 :Result:='mmGDS_PS4_CTXSW_CNT0'; - mmGDS_PS4_CTXSW_CNT1 :Result:='mmGDS_PS4_CTXSW_CNT1'; - mmGDS_PS4_CTXSW_CNT2 :Result:='mmGDS_PS4_CTXSW_CNT2'; - mmGDS_PS4_CTXSW_CNT3 :Result:='mmGDS_PS4_CTXSW_CNT3'; - mmGDS_PS5_CTXSW_CNT0 :Result:='mmGDS_PS5_CTXSW_CNT0'; - mmGDS_PS5_CTXSW_CNT1 :Result:='mmGDS_PS5_CTXSW_CNT1'; - mmGDS_PS5_CTXSW_CNT2 :Result:='mmGDS_PS5_CTXSW_CNT2'; - mmGDS_PS5_CTXSW_CNT3 :Result:='mmGDS_PS5_CTXSW_CNT3'; - mmGDS_PS6_CTXSW_CNT0 :Result:='mmGDS_PS6_CTXSW_CNT0'; - mmGDS_PS6_CTXSW_CNT1 :Result:='mmGDS_PS6_CTXSW_CNT1'; - mmGDS_PS6_CTXSW_CNT2 :Result:='mmGDS_PS6_CTXSW_CNT2'; - mmGDS_PS6_CTXSW_CNT3 :Result:='mmGDS_PS6_CTXSW_CNT3'; - mmGDS_PS7_CTXSW_CNT0 :Result:='mmGDS_PS7_CTXSW_CNT0'; - mmGDS_PS7_CTXSW_CNT1 :Result:='mmGDS_PS7_CTXSW_CNT1'; - mmGDS_PS7_CTXSW_CNT2 :Result:='mmGDS_PS7_CTXSW_CNT2'; - mmGDS_PS7_CTXSW_CNT3 :Result:='mmGDS_PS7_CTXSW_CNT3'; - mmDB_RENDER_CONTROL :Result:='mmDB_RENDER_CONTROL'; - mmDB_COUNT_CONTROL :Result:='mmDB_COUNT_CONTROL'; - mmDB_DEPTH_VIEW :Result:='mmDB_DEPTH_VIEW'; - mmDB_RENDER_OVERRIDE :Result:='mmDB_RENDER_OVERRIDE'; - mmDB_RENDER_OVERRIDE2 :Result:='mmDB_RENDER_OVERRIDE2'; - mmDB_HTILE_DATA_BASE :Result:='mmDB_HTILE_DATA_BASE'; - mmDB_DEPTH_BOUNDS_MIN :Result:='mmDB_DEPTH_BOUNDS_MIN'; - mmDB_DEPTH_BOUNDS_MAX :Result:='mmDB_DEPTH_BOUNDS_MAX'; - mmDB_STENCIL_CLEAR :Result:='mmDB_STENCIL_CLEAR'; - mmDB_DEPTH_CLEAR :Result:='mmDB_DEPTH_CLEAR'; - mmPA_SC_SCREEN_SCISSOR_TL :Result:='mmPA_SC_SCREEN_SCISSOR_TL'; - mmPA_SC_SCREEN_SCISSOR_BR :Result:='mmPA_SC_SCREEN_SCISSOR_BR'; - mmDB_DEPTH_INFO :Result:='mmDB_DEPTH_INFO'; - mmDB_Z_INFO :Result:='mmDB_Z_INFO'; - mmDB_STENCIL_INFO :Result:='mmDB_STENCIL_INFO'; - mmDB_Z_READ_BASE :Result:='mmDB_Z_READ_BASE'; - mmDB_STENCIL_READ_BASE :Result:='mmDB_STENCIL_READ_BASE'; - mmDB_Z_WRITE_BASE :Result:='mmDB_Z_WRITE_BASE'; - mmDB_STENCIL_WRITE_BASE :Result:='mmDB_STENCIL_WRITE_BASE'; - mmDB_DEPTH_SIZE :Result:='mmDB_DEPTH_SIZE'; - mmDB_DEPTH_SLICE :Result:='mmDB_DEPTH_SLICE'; - mmTA_BC_BASE_ADDR :Result:='mmTA_BC_BASE_ADDR'; - mmTA_BC_BASE_ADDR_HI :Result:='mmTA_BC_BASE_ADDR_HI'; - mmPA_SC_WINDOW_OFFSET :Result:='mmPA_SC_WINDOW_OFFSET'; - mmPA_SC_WINDOW_SCISSOR_TL :Result:='mmPA_SC_WINDOW_SCISSOR_TL'; - mmPA_SC_WINDOW_SCISSOR_BR :Result:='mmPA_SC_WINDOW_SCISSOR_BR'; - mmPA_SC_CLIPRECT_RULE :Result:='mmPA_SC_CLIPRECT_RULE'; - mmPA_SC_CLIPRECT_0_TL :Result:='mmPA_SC_CLIPRECT_0_TL'; - mmPA_SC_CLIPRECT_0_BR :Result:='mmPA_SC_CLIPRECT_0_BR'; - mmPA_SC_CLIPRECT_1_TL :Result:='mmPA_SC_CLIPRECT_1_TL'; - mmPA_SC_CLIPRECT_1_BR :Result:='mmPA_SC_CLIPRECT_1_BR'; - mmPA_SC_CLIPRECT_2_TL :Result:='mmPA_SC_CLIPRECT_2_TL'; - mmPA_SC_CLIPRECT_2_BR :Result:='mmPA_SC_CLIPRECT_2_BR'; - mmPA_SC_CLIPRECT_3_TL :Result:='mmPA_SC_CLIPRECT_3_TL'; - mmPA_SC_CLIPRECT_3_BR :Result:='mmPA_SC_CLIPRECT_3_BR'; - mmPA_SC_EDGERULE :Result:='mmPA_SC_EDGERULE'; - mmPA_SU_HARDWARE_SCREEN_OFFSET :Result:='mmPA_SU_HARDWARE_SCREEN_OFFSET'; - mmCB_TARGET_MASK :Result:='mmCB_TARGET_MASK'; - mmCB_SHADER_MASK :Result:='mmCB_SHADER_MASK'; - mmPA_SC_GENERIC_SCISSOR_TL :Result:='mmPA_SC_GENERIC_SCISSOR_TL'; - mmPA_SC_GENERIC_SCISSOR_BR :Result:='mmPA_SC_GENERIC_SCISSOR_BR'; - mmPA_SC_VPORT_SCISSOR_0_TL :Result:='mmPA_SC_VPORT_SCISSOR_0_TL'; - mmPA_SC_VPORT_SCISSOR_0_BR :Result:='mmPA_SC_VPORT_SCISSOR_0_BR'; - mmPA_SC_VPORT_SCISSOR_1_TL :Result:='mmPA_SC_VPORT_SCISSOR_1_TL'; - mmPA_SC_VPORT_SCISSOR_1_BR :Result:='mmPA_SC_VPORT_SCISSOR_1_BR'; - mmPA_SC_VPORT_SCISSOR_2_TL :Result:='mmPA_SC_VPORT_SCISSOR_2_TL'; - mmPA_SC_VPORT_SCISSOR_2_BR :Result:='mmPA_SC_VPORT_SCISSOR_2_BR'; - mmPA_SC_VPORT_SCISSOR_3_TL :Result:='mmPA_SC_VPORT_SCISSOR_3_TL'; - mmPA_SC_VPORT_SCISSOR_3_BR :Result:='mmPA_SC_VPORT_SCISSOR_3_BR'; - mmPA_SC_VPORT_SCISSOR_4_TL :Result:='mmPA_SC_VPORT_SCISSOR_4_TL'; - mmPA_SC_VPORT_SCISSOR_4_BR :Result:='mmPA_SC_VPORT_SCISSOR_4_BR'; - mmPA_SC_VPORT_SCISSOR_5_TL :Result:='mmPA_SC_VPORT_SCISSOR_5_TL'; - mmPA_SC_VPORT_SCISSOR_5_BR :Result:='mmPA_SC_VPORT_SCISSOR_5_BR'; - mmPA_SC_VPORT_SCISSOR_6_TL :Result:='mmPA_SC_VPORT_SCISSOR_6_TL'; - mmPA_SC_VPORT_SCISSOR_6_BR :Result:='mmPA_SC_VPORT_SCISSOR_6_BR'; - mmPA_SC_VPORT_SCISSOR_7_TL :Result:='mmPA_SC_VPORT_SCISSOR_7_TL'; - mmPA_SC_VPORT_SCISSOR_7_BR :Result:='mmPA_SC_VPORT_SCISSOR_7_BR'; - mmPA_SC_VPORT_SCISSOR_8_TL :Result:='mmPA_SC_VPORT_SCISSOR_8_TL'; - mmPA_SC_VPORT_SCISSOR_8_BR :Result:='mmPA_SC_VPORT_SCISSOR_8_BR'; - mmPA_SC_VPORT_SCISSOR_9_TL :Result:='mmPA_SC_VPORT_SCISSOR_9_TL'; - mmPA_SC_VPORT_SCISSOR_9_BR :Result:='mmPA_SC_VPORT_SCISSOR_9_BR'; - mmPA_SC_VPORT_SCISSOR_10_TL :Result:='mmPA_SC_VPORT_SCISSOR_10_TL'; - mmPA_SC_VPORT_SCISSOR_10_BR :Result:='mmPA_SC_VPORT_SCISSOR_10_BR'; - mmPA_SC_VPORT_SCISSOR_11_TL :Result:='mmPA_SC_VPORT_SCISSOR_11_TL'; - mmPA_SC_VPORT_SCISSOR_11_BR :Result:='mmPA_SC_VPORT_SCISSOR_11_BR'; - mmPA_SC_VPORT_SCISSOR_12_TL :Result:='mmPA_SC_VPORT_SCISSOR_12_TL'; - mmPA_SC_VPORT_SCISSOR_12_BR :Result:='mmPA_SC_VPORT_SCISSOR_12_BR'; - mmPA_SC_VPORT_SCISSOR_13_TL :Result:='mmPA_SC_VPORT_SCISSOR_13_TL'; - mmPA_SC_VPORT_SCISSOR_13_BR :Result:='mmPA_SC_VPORT_SCISSOR_13_BR'; - mmPA_SC_VPORT_SCISSOR_14_TL :Result:='mmPA_SC_VPORT_SCISSOR_14_TL'; - mmPA_SC_VPORT_SCISSOR_14_BR :Result:='mmPA_SC_VPORT_SCISSOR_14_BR'; - mmPA_SC_VPORT_SCISSOR_15_TL :Result:='mmPA_SC_VPORT_SCISSOR_15_TL'; - mmPA_SC_VPORT_SCISSOR_15_BR :Result:='mmPA_SC_VPORT_SCISSOR_15_BR'; - mmPA_SC_VPORT_ZMIN_0 :Result:='mmPA_SC_VPORT_ZMIN_0'; - mmPA_SC_VPORT_ZMAX_0 :Result:='mmPA_SC_VPORT_ZMAX_0'; - mmPA_SC_VPORT_ZMIN_1 :Result:='mmPA_SC_VPORT_ZMIN_1'; - mmPA_SC_VPORT_ZMAX_1 :Result:='mmPA_SC_VPORT_ZMAX_1'; - mmPA_SC_VPORT_ZMIN_2 :Result:='mmPA_SC_VPORT_ZMIN_2'; - mmPA_SC_VPORT_ZMAX_2 :Result:='mmPA_SC_VPORT_ZMAX_2'; - mmPA_SC_VPORT_ZMIN_3 :Result:='mmPA_SC_VPORT_ZMIN_3'; - mmPA_SC_VPORT_ZMAX_3 :Result:='mmPA_SC_VPORT_ZMAX_3'; - mmPA_SC_VPORT_ZMIN_4 :Result:='mmPA_SC_VPORT_ZMIN_4'; - mmPA_SC_VPORT_ZMAX_4 :Result:='mmPA_SC_VPORT_ZMAX_4'; - mmPA_SC_VPORT_ZMIN_5 :Result:='mmPA_SC_VPORT_ZMIN_5'; - mmPA_SC_VPORT_ZMAX_5 :Result:='mmPA_SC_VPORT_ZMAX_5'; - mmPA_SC_VPORT_ZMIN_6 :Result:='mmPA_SC_VPORT_ZMIN_6'; - mmPA_SC_VPORT_ZMAX_6 :Result:='mmPA_SC_VPORT_ZMAX_6'; - mmPA_SC_VPORT_ZMIN_7 :Result:='mmPA_SC_VPORT_ZMIN_7'; - mmPA_SC_VPORT_ZMAX_7 :Result:='mmPA_SC_VPORT_ZMAX_7'; - mmPA_SC_VPORT_ZMIN_8 :Result:='mmPA_SC_VPORT_ZMIN_8'; - mmPA_SC_VPORT_ZMAX_8 :Result:='mmPA_SC_VPORT_ZMAX_8'; - mmPA_SC_VPORT_ZMIN_9 :Result:='mmPA_SC_VPORT_ZMIN_9'; - mmPA_SC_VPORT_ZMAX_9 :Result:='mmPA_SC_VPORT_ZMAX_9'; - mmPA_SC_VPORT_ZMIN_10 :Result:='mmPA_SC_VPORT_ZMIN_10'; - mmPA_SC_VPORT_ZMAX_10 :Result:='mmPA_SC_VPORT_ZMAX_10'; - mmPA_SC_VPORT_ZMIN_11 :Result:='mmPA_SC_VPORT_ZMIN_11'; - mmPA_SC_VPORT_ZMAX_11 :Result:='mmPA_SC_VPORT_ZMAX_11'; - mmPA_SC_VPORT_ZMIN_12 :Result:='mmPA_SC_VPORT_ZMIN_12'; - mmPA_SC_VPORT_ZMAX_12 :Result:='mmPA_SC_VPORT_ZMAX_12'; - mmPA_SC_VPORT_ZMIN_13 :Result:='mmPA_SC_VPORT_ZMIN_13'; - mmPA_SC_VPORT_ZMAX_13 :Result:='mmPA_SC_VPORT_ZMAX_13'; - mmPA_SC_VPORT_ZMIN_14 :Result:='mmPA_SC_VPORT_ZMIN_14'; - mmPA_SC_VPORT_ZMAX_14 :Result:='mmPA_SC_VPORT_ZMAX_14'; - mmPA_SC_VPORT_ZMIN_15 :Result:='mmPA_SC_VPORT_ZMIN_15'; - mmPA_SC_VPORT_ZMAX_15 :Result:='mmPA_SC_VPORT_ZMAX_15'; - mmPA_SC_RASTER_CONFIG :Result:='mmPA_SC_RASTER_CONFIG'; - mmPA_SC_RASTER_CONFIG_1 :Result:='mmPA_SC_RASTER_CONFIG_1'; - mmCP_PERFMON_CNTX_CNTL :Result:='mmCP_PERFMON_CNTX_CNTL'; - mmCP_PIPEID :Result:='mmCP_PIPEID'; - mmCP_VMID :Result:='mmCP_VMID'; - mmVGT_MAX_VTX_INDX :Result:='mmVGT_MAX_VTX_INDX'; - mmVGT_MIN_VTX_INDX :Result:='mmVGT_MIN_VTX_INDX'; - mmVGT_INDX_OFFSET :Result:='mmVGT_INDX_OFFSET'; - mmVGT_MULTI_PRIM_IB_RESET_INDX :Result:='mmVGT_MULTI_PRIM_IB_RESET_INDX'; - mmCB_BLEND_RED :Result:='mmCB_BLEND_RED'; - mmCB_BLEND_GREEN :Result:='mmCB_BLEND_GREEN'; - mmCB_BLEND_BLUE :Result:='mmCB_BLEND_BLUE'; - mmCB_BLEND_ALPHA :Result:='mmCB_BLEND_ALPHA'; - mmCB_DCC_CONTROL :Result:='mmCB_DCC_CONTROL'; - mmDB_STENCIL_CONTROL :Result:='mmDB_STENCIL_CONTROL'; - mmDB_STENCILREFMASK :Result:='mmDB_STENCILREFMASK'; - mmDB_STENCILREFMASK_BF :Result:='mmDB_STENCILREFMASK_BF'; - mmPA_CL_VPORT_XSCALE :Result:='mmPA_CL_VPORT_XSCALE'; - mmPA_CL_VPORT_XOFFSET :Result:='mmPA_CL_VPORT_XOFFSET'; - mmPA_CL_VPORT_YSCALE :Result:='mmPA_CL_VPORT_YSCALE'; - mmPA_CL_VPORT_YOFFSET :Result:='mmPA_CL_VPORT_YOFFSET'; - mmPA_CL_VPORT_ZSCALE :Result:='mmPA_CL_VPORT_ZSCALE'; - mmPA_CL_VPORT_ZOFFSET :Result:='mmPA_CL_VPORT_ZOFFSET'; - mmPA_CL_VPORT_XSCALE_1 :Result:='mmPA_CL_VPORT_XSCALE_1'; - mmPA_CL_VPORT_XOFFSET_1 :Result:='mmPA_CL_VPORT_XOFFSET_1'; - mmPA_CL_VPORT_YSCALE_1 :Result:='mmPA_CL_VPORT_YSCALE_1'; - mmPA_CL_VPORT_YOFFSET_1 :Result:='mmPA_CL_VPORT_YOFFSET_1'; - mmPA_CL_VPORT_ZSCALE_1 :Result:='mmPA_CL_VPORT_ZSCALE_1'; - mmPA_CL_VPORT_ZOFFSET_1 :Result:='mmPA_CL_VPORT_ZOFFSET_1'; - mmPA_CL_VPORT_XSCALE_2 :Result:='mmPA_CL_VPORT_XSCALE_2'; - mmPA_CL_VPORT_XOFFSET_2 :Result:='mmPA_CL_VPORT_XOFFSET_2'; - mmPA_CL_VPORT_YSCALE_2 :Result:='mmPA_CL_VPORT_YSCALE_2'; - mmPA_CL_VPORT_YOFFSET_2 :Result:='mmPA_CL_VPORT_YOFFSET_2'; - mmPA_CL_VPORT_ZSCALE_2 :Result:='mmPA_CL_VPORT_ZSCALE_2'; - mmPA_CL_VPORT_ZOFFSET_2 :Result:='mmPA_CL_VPORT_ZOFFSET_2'; - mmPA_CL_VPORT_XSCALE_3 :Result:='mmPA_CL_VPORT_XSCALE_3'; - mmPA_CL_VPORT_XOFFSET_3 :Result:='mmPA_CL_VPORT_XOFFSET_3'; - mmPA_CL_VPORT_YSCALE_3 :Result:='mmPA_CL_VPORT_YSCALE_3'; - mmPA_CL_VPORT_YOFFSET_3 :Result:='mmPA_CL_VPORT_YOFFSET_3'; - mmPA_CL_VPORT_ZSCALE_3 :Result:='mmPA_CL_VPORT_ZSCALE_3'; - mmPA_CL_VPORT_ZOFFSET_3 :Result:='mmPA_CL_VPORT_ZOFFSET_3'; - mmPA_CL_VPORT_XSCALE_4 :Result:='mmPA_CL_VPORT_XSCALE_4'; - mmPA_CL_VPORT_XOFFSET_4 :Result:='mmPA_CL_VPORT_XOFFSET_4'; - mmPA_CL_VPORT_YSCALE_4 :Result:='mmPA_CL_VPORT_YSCALE_4'; - mmPA_CL_VPORT_YOFFSET_4 :Result:='mmPA_CL_VPORT_YOFFSET_4'; - mmPA_CL_VPORT_ZSCALE_4 :Result:='mmPA_CL_VPORT_ZSCALE_4'; - mmPA_CL_VPORT_ZOFFSET_4 :Result:='mmPA_CL_VPORT_ZOFFSET_4'; - mmPA_CL_VPORT_XSCALE_5 :Result:='mmPA_CL_VPORT_XSCALE_5'; - mmPA_CL_VPORT_XOFFSET_5 :Result:='mmPA_CL_VPORT_XOFFSET_5'; - mmPA_CL_VPORT_YSCALE_5 :Result:='mmPA_CL_VPORT_YSCALE_5'; - mmPA_CL_VPORT_YOFFSET_5 :Result:='mmPA_CL_VPORT_YOFFSET_5'; - mmPA_CL_VPORT_ZSCALE_5 :Result:='mmPA_CL_VPORT_ZSCALE_5'; - mmPA_CL_VPORT_ZOFFSET_5 :Result:='mmPA_CL_VPORT_ZOFFSET_5'; - mmPA_CL_VPORT_XSCALE_6 :Result:='mmPA_CL_VPORT_XSCALE_6'; - mmPA_CL_VPORT_XOFFSET_6 :Result:='mmPA_CL_VPORT_XOFFSET_6'; - mmPA_CL_VPORT_YSCALE_6 :Result:='mmPA_CL_VPORT_YSCALE_6'; - mmPA_CL_VPORT_YOFFSET_6 :Result:='mmPA_CL_VPORT_YOFFSET_6'; - mmPA_CL_VPORT_ZSCALE_6 :Result:='mmPA_CL_VPORT_ZSCALE_6'; - mmPA_CL_VPORT_ZOFFSET_6 :Result:='mmPA_CL_VPORT_ZOFFSET_6'; - mmPA_CL_VPORT_XSCALE_7 :Result:='mmPA_CL_VPORT_XSCALE_7'; - mmPA_CL_VPORT_XOFFSET_7 :Result:='mmPA_CL_VPORT_XOFFSET_7'; - mmPA_CL_VPORT_YSCALE_7 :Result:='mmPA_CL_VPORT_YSCALE_7'; - mmPA_CL_VPORT_YOFFSET_7 :Result:='mmPA_CL_VPORT_YOFFSET_7'; - mmPA_CL_VPORT_ZSCALE_7 :Result:='mmPA_CL_VPORT_ZSCALE_7'; - mmPA_CL_VPORT_ZOFFSET_7 :Result:='mmPA_CL_VPORT_ZOFFSET_7'; - mmPA_CL_VPORT_XSCALE_8 :Result:='mmPA_CL_VPORT_XSCALE_8'; - mmPA_CL_VPORT_XOFFSET_8 :Result:='mmPA_CL_VPORT_XOFFSET_8'; - mmPA_CL_VPORT_YSCALE_8 :Result:='mmPA_CL_VPORT_YSCALE_8'; - mmPA_CL_VPORT_YOFFSET_8 :Result:='mmPA_CL_VPORT_YOFFSET_8'; - mmPA_CL_VPORT_ZSCALE_8 :Result:='mmPA_CL_VPORT_ZSCALE_8'; - mmPA_CL_VPORT_ZOFFSET_8 :Result:='mmPA_CL_VPORT_ZOFFSET_8'; - mmPA_CL_VPORT_XSCALE_9 :Result:='mmPA_CL_VPORT_XSCALE_9'; - mmPA_CL_VPORT_XOFFSET_9 :Result:='mmPA_CL_VPORT_XOFFSET_9'; - mmPA_CL_VPORT_YSCALE_9 :Result:='mmPA_CL_VPORT_YSCALE_9'; - mmPA_CL_VPORT_YOFFSET_9 :Result:='mmPA_CL_VPORT_YOFFSET_9'; - mmPA_CL_VPORT_ZSCALE_9 :Result:='mmPA_CL_VPORT_ZSCALE_9'; - mmPA_CL_VPORT_ZOFFSET_9 :Result:='mmPA_CL_VPORT_ZOFFSET_9'; - mmPA_CL_VPORT_XSCALE_10 :Result:='mmPA_CL_VPORT_XSCALE_10'; - mmPA_CL_VPORT_XOFFSET_10 :Result:='mmPA_CL_VPORT_XOFFSET_10'; - mmPA_CL_VPORT_YSCALE_10 :Result:='mmPA_CL_VPORT_YSCALE_10'; - mmPA_CL_VPORT_YOFFSET_10 :Result:='mmPA_CL_VPORT_YOFFSET_10'; - mmPA_CL_VPORT_ZSCALE_10 :Result:='mmPA_CL_VPORT_ZSCALE_10'; - mmPA_CL_VPORT_ZOFFSET_10 :Result:='mmPA_CL_VPORT_ZOFFSET_10'; - mmPA_CL_VPORT_XSCALE_11 :Result:='mmPA_CL_VPORT_XSCALE_11'; - mmPA_CL_VPORT_XOFFSET_11 :Result:='mmPA_CL_VPORT_XOFFSET_11'; - mmPA_CL_VPORT_YSCALE_11 :Result:='mmPA_CL_VPORT_YSCALE_11'; - mmPA_CL_VPORT_YOFFSET_11 :Result:='mmPA_CL_VPORT_YOFFSET_11'; - mmPA_CL_VPORT_ZSCALE_11 :Result:='mmPA_CL_VPORT_ZSCALE_11'; - mmPA_CL_VPORT_ZOFFSET_11 :Result:='mmPA_CL_VPORT_ZOFFSET_11'; - mmPA_CL_VPORT_XSCALE_12 :Result:='mmPA_CL_VPORT_XSCALE_12'; - mmPA_CL_VPORT_XOFFSET_12 :Result:='mmPA_CL_VPORT_XOFFSET_12'; - mmPA_CL_VPORT_YSCALE_12 :Result:='mmPA_CL_VPORT_YSCALE_12'; - mmPA_CL_VPORT_YOFFSET_12 :Result:='mmPA_CL_VPORT_YOFFSET_12'; - mmPA_CL_VPORT_ZSCALE_12 :Result:='mmPA_CL_VPORT_ZSCALE_12'; - mmPA_CL_VPORT_ZOFFSET_12 :Result:='mmPA_CL_VPORT_ZOFFSET_12'; - mmPA_CL_VPORT_XSCALE_13 :Result:='mmPA_CL_VPORT_XSCALE_13'; - mmPA_CL_VPORT_XOFFSET_13 :Result:='mmPA_CL_VPORT_XOFFSET_13'; - mmPA_CL_VPORT_YSCALE_13 :Result:='mmPA_CL_VPORT_YSCALE_13'; - mmPA_CL_VPORT_YOFFSET_13 :Result:='mmPA_CL_VPORT_YOFFSET_13'; - mmPA_CL_VPORT_ZSCALE_13 :Result:='mmPA_CL_VPORT_ZSCALE_13'; - mmPA_CL_VPORT_ZOFFSET_13 :Result:='mmPA_CL_VPORT_ZOFFSET_13'; - mmPA_CL_VPORT_XSCALE_14 :Result:='mmPA_CL_VPORT_XSCALE_14'; - mmPA_CL_VPORT_XOFFSET_14 :Result:='mmPA_CL_VPORT_XOFFSET_14'; - mmPA_CL_VPORT_YSCALE_14 :Result:='mmPA_CL_VPORT_YSCALE_14'; - mmPA_CL_VPORT_YOFFSET_14 :Result:='mmPA_CL_VPORT_YOFFSET_14'; - mmPA_CL_VPORT_ZSCALE_14 :Result:='mmPA_CL_VPORT_ZSCALE_14'; - mmPA_CL_VPORT_ZOFFSET_14 :Result:='mmPA_CL_VPORT_ZOFFSET_14'; - mmPA_CL_VPORT_XSCALE_15 :Result:='mmPA_CL_VPORT_XSCALE_15'; - mmPA_CL_VPORT_XOFFSET_15 :Result:='mmPA_CL_VPORT_XOFFSET_15'; - mmPA_CL_VPORT_YSCALE_15 :Result:='mmPA_CL_VPORT_YSCALE_15'; - mmPA_CL_VPORT_YOFFSET_15 :Result:='mmPA_CL_VPORT_YOFFSET_15'; - mmPA_CL_VPORT_ZSCALE_15 :Result:='mmPA_CL_VPORT_ZSCALE_15'; - mmPA_CL_VPORT_ZOFFSET_15 :Result:='mmPA_CL_VPORT_ZOFFSET_15'; - mmPA_CL_UCP_0_X :Result:='mmPA_CL_UCP_0_X'; - mmPA_CL_UCP_0_Y :Result:='mmPA_CL_UCP_0_Y'; - mmPA_CL_UCP_0_Z :Result:='mmPA_CL_UCP_0_Z'; - mmPA_CL_UCP_0_W :Result:='mmPA_CL_UCP_0_W'; - mmPA_CL_UCP_1_X :Result:='mmPA_CL_UCP_1_X'; - mmPA_CL_UCP_1_Y :Result:='mmPA_CL_UCP_1_Y'; - mmPA_CL_UCP_1_Z :Result:='mmPA_CL_UCP_1_Z'; - mmPA_CL_UCP_1_W :Result:='mmPA_CL_UCP_1_W'; - mmPA_CL_UCP_2_X :Result:='mmPA_CL_UCP_2_X'; - mmPA_CL_UCP_2_Y :Result:='mmPA_CL_UCP_2_Y'; - mmPA_CL_UCP_2_Z :Result:='mmPA_CL_UCP_2_Z'; - mmPA_CL_UCP_2_W :Result:='mmPA_CL_UCP_2_W'; - mmPA_CL_UCP_3_X :Result:='mmPA_CL_UCP_3_X'; - mmPA_CL_UCP_3_Y :Result:='mmPA_CL_UCP_3_Y'; - mmPA_CL_UCP_3_Z :Result:='mmPA_CL_UCP_3_Z'; - mmPA_CL_UCP_3_W :Result:='mmPA_CL_UCP_3_W'; - mmPA_CL_UCP_4_X :Result:='mmPA_CL_UCP_4_X'; - mmPA_CL_UCP_4_Y :Result:='mmPA_CL_UCP_4_Y'; - mmPA_CL_UCP_4_Z :Result:='mmPA_CL_UCP_4_Z'; - mmPA_CL_UCP_4_W :Result:='mmPA_CL_UCP_4_W'; - mmPA_CL_UCP_5_X :Result:='mmPA_CL_UCP_5_X'; - mmPA_CL_UCP_5_Y :Result:='mmPA_CL_UCP_5_Y'; - mmPA_CL_UCP_5_Z :Result:='mmPA_CL_UCP_5_Z'; - mmPA_CL_UCP_5_W :Result:='mmPA_CL_UCP_5_W'; - mmSPI_PS_INPUT_CNTL_0 :Result:='mmSPI_PS_INPUT_CNTL_0'; - mmSPI_PS_INPUT_CNTL_1 :Result:='mmSPI_PS_INPUT_CNTL_1'; - mmSPI_PS_INPUT_CNTL_2 :Result:='mmSPI_PS_INPUT_CNTL_2'; - mmSPI_PS_INPUT_CNTL_3 :Result:='mmSPI_PS_INPUT_CNTL_3'; - mmSPI_PS_INPUT_CNTL_4 :Result:='mmSPI_PS_INPUT_CNTL_4'; - mmSPI_PS_INPUT_CNTL_5 :Result:='mmSPI_PS_INPUT_CNTL_5'; - mmSPI_PS_INPUT_CNTL_6 :Result:='mmSPI_PS_INPUT_CNTL_6'; - mmSPI_PS_INPUT_CNTL_7 :Result:='mmSPI_PS_INPUT_CNTL_7'; - mmSPI_PS_INPUT_CNTL_8 :Result:='mmSPI_PS_INPUT_CNTL_8'; - mmSPI_PS_INPUT_CNTL_9 :Result:='mmSPI_PS_INPUT_CNTL_9'; - mmSPI_PS_INPUT_CNTL_10 :Result:='mmSPI_PS_INPUT_CNTL_10'; - mmSPI_PS_INPUT_CNTL_11 :Result:='mmSPI_PS_INPUT_CNTL_11'; - mmSPI_PS_INPUT_CNTL_12 :Result:='mmSPI_PS_INPUT_CNTL_12'; - mmSPI_PS_INPUT_CNTL_13 :Result:='mmSPI_PS_INPUT_CNTL_13'; - mmSPI_PS_INPUT_CNTL_14 :Result:='mmSPI_PS_INPUT_CNTL_14'; - mmSPI_PS_INPUT_CNTL_15 :Result:='mmSPI_PS_INPUT_CNTL_15'; - mmSPI_PS_INPUT_CNTL_16 :Result:='mmSPI_PS_INPUT_CNTL_16'; - mmSPI_PS_INPUT_CNTL_17 :Result:='mmSPI_PS_INPUT_CNTL_17'; - mmSPI_PS_INPUT_CNTL_18 :Result:='mmSPI_PS_INPUT_CNTL_18'; - mmSPI_PS_INPUT_CNTL_19 :Result:='mmSPI_PS_INPUT_CNTL_19'; - mmSPI_PS_INPUT_CNTL_20 :Result:='mmSPI_PS_INPUT_CNTL_20'; - mmSPI_PS_INPUT_CNTL_21 :Result:='mmSPI_PS_INPUT_CNTL_21'; - mmSPI_PS_INPUT_CNTL_22 :Result:='mmSPI_PS_INPUT_CNTL_22'; - mmSPI_PS_INPUT_CNTL_23 :Result:='mmSPI_PS_INPUT_CNTL_23'; - mmSPI_PS_INPUT_CNTL_24 :Result:='mmSPI_PS_INPUT_CNTL_24'; - mmSPI_PS_INPUT_CNTL_25 :Result:='mmSPI_PS_INPUT_CNTL_25'; - mmSPI_PS_INPUT_CNTL_26 :Result:='mmSPI_PS_INPUT_CNTL_26'; - mmSPI_PS_INPUT_CNTL_27 :Result:='mmSPI_PS_INPUT_CNTL_27'; - mmSPI_PS_INPUT_CNTL_28 :Result:='mmSPI_PS_INPUT_CNTL_28'; - mmSPI_PS_INPUT_CNTL_29 :Result:='mmSPI_PS_INPUT_CNTL_29'; - mmSPI_PS_INPUT_CNTL_30 :Result:='mmSPI_PS_INPUT_CNTL_30'; - mmSPI_PS_INPUT_CNTL_31 :Result:='mmSPI_PS_INPUT_CNTL_31'; - mmSPI_VS_OUT_CONFIG :Result:='mmSPI_VS_OUT_CONFIG'; - mmSPI_PS_INPUT_ENA :Result:='mmSPI_PS_INPUT_ENA'; - mmSPI_PS_INPUT_ADDR :Result:='mmSPI_PS_INPUT_ADDR'; - mmSPI_INTERP_CONTROL_0 :Result:='mmSPI_INTERP_CONTROL_0'; - mmSPI_PS_IN_CONTROL :Result:='mmSPI_PS_IN_CONTROL'; - mmSPI_BARYC_CNTL :Result:='mmSPI_BARYC_CNTL'; - mmSPI_TMPRING_SIZE :Result:='mmSPI_TMPRING_SIZE'; - mmSPI_SHADER_POS_FORMAT :Result:='mmSPI_SHADER_POS_FORMAT'; - mmSPI_SHADER_Z_FORMAT :Result:='mmSPI_SHADER_Z_FORMAT'; - mmSPI_SHADER_COL_FORMAT :Result:='mmSPI_SHADER_COL_FORMAT'; - mmSX_PS_DOWNCONVERT :Result:='mmSX_PS_DOWNCONVERT'; - mmSX_BLEND_OPT_EPSILON :Result:='mmSX_BLEND_OPT_EPSILON'; - mmSX_BLEND_OPT_CONTROL :Result:='mmSX_BLEND_OPT_CONTROL'; - mmSX_MRT0_BLEND_OPT :Result:='mmSX_MRT0_BLEND_OPT'; - mmSX_MRT1_BLEND_OPT :Result:='mmSX_MRT1_BLEND_OPT'; - mmSX_MRT2_BLEND_OPT :Result:='mmSX_MRT2_BLEND_OPT'; - mmSX_MRT3_BLEND_OPT :Result:='mmSX_MRT3_BLEND_OPT'; - mmSX_MRT4_BLEND_OPT :Result:='mmSX_MRT4_BLEND_OPT'; - mmSX_MRT5_BLEND_OPT :Result:='mmSX_MRT5_BLEND_OPT'; - mmSX_MRT6_BLEND_OPT :Result:='mmSX_MRT6_BLEND_OPT'; - mmSX_MRT7_BLEND_OPT :Result:='mmSX_MRT7_BLEND_OPT'; - mmCB_BLEND0_CONTROL :Result:='mmCB_BLEND0_CONTROL'; - mmCB_BLEND1_CONTROL :Result:='mmCB_BLEND1_CONTROL'; - mmCB_BLEND2_CONTROL :Result:='mmCB_BLEND2_CONTROL'; - mmCB_BLEND3_CONTROL :Result:='mmCB_BLEND3_CONTROL'; - mmCB_BLEND4_CONTROL :Result:='mmCB_BLEND4_CONTROL'; - mmCB_BLEND5_CONTROL :Result:='mmCB_BLEND5_CONTROL'; - mmCB_BLEND6_CONTROL :Result:='mmCB_BLEND6_CONTROL'; - mmCB_BLEND7_CONTROL :Result:='mmCB_BLEND7_CONTROL'; - mmPA_CL_POINT_X_RAD :Result:='mmPA_CL_POINT_X_RAD'; - mmPA_CL_POINT_Y_RAD :Result:='mmPA_CL_POINT_Y_RAD'; - mmPA_CL_POINT_SIZE :Result:='mmPA_CL_POINT_SIZE'; - mmPA_CL_POINT_CULL_RAD :Result:='mmPA_CL_POINT_CULL_RAD'; - mmVGT_DMA_BASE_HI :Result:='mmVGT_DMA_BASE_HI'; - mmVGT_DMA_BASE :Result:='mmVGT_DMA_BASE'; - mmVGT_DRAW_INITIATOR :Result:='mmVGT_DRAW_INITIATOR'; - mmVGT_IMMED_DATA :Result:='mmVGT_IMMED_DATA'; - mmVGT_EVENT_ADDRESS_REG :Result:='mmVGT_EVENT_ADDRESS_REG'; - mmDB_DEPTH_CONTROL :Result:='mmDB_DEPTH_CONTROL'; - mmDB_EQAA :Result:='mmDB_EQAA'; - mmCB_COLOR_CONTROL :Result:='mmCB_COLOR_CONTROL'; - mmDB_SHADER_CONTROL :Result:='mmDB_SHADER_CONTROL'; - mmPA_CL_CLIP_CNTL :Result:='mmPA_CL_CLIP_CNTL'; - mmPA_SU_SC_MODE_CNTL :Result:='mmPA_SU_SC_MODE_CNTL'; - mmPA_CL_VTE_CNTL :Result:='mmPA_CL_VTE_CNTL'; - mmPA_CL_VS_OUT_CNTL :Result:='mmPA_CL_VS_OUT_CNTL'; - mmPA_CL_NANINF_CNTL :Result:='mmPA_CL_NANINF_CNTL'; - mmPA_SU_LINE_STIPPLE_CNTL :Result:='mmPA_SU_LINE_STIPPLE_CNTL'; - mmPA_SU_LINE_STIPPLE_SCALE :Result:='mmPA_SU_LINE_STIPPLE_SCALE'; - mmPA_SU_PRIM_FILTER_CNTL :Result:='mmPA_SU_PRIM_FILTER_CNTL'; - mmPA_SU_POINT_SIZE :Result:='mmPA_SU_POINT_SIZE'; - mmPA_SU_POINT_MINMAX :Result:='mmPA_SU_POINT_MINMAX'; - mmPA_SU_LINE_CNTL :Result:='mmPA_SU_LINE_CNTL'; - mmPA_SC_LINE_STIPPLE :Result:='mmPA_SC_LINE_STIPPLE'; - mmVGT_OUTPUT_PATH_CNTL :Result:='mmVGT_OUTPUT_PATH_CNTL'; - mmVGT_HOS_CNTL :Result:='mmVGT_HOS_CNTL'; - mmVGT_HOS_MAX_TESS_LEVEL :Result:='mmVGT_HOS_MAX_TESS_LEVEL'; - mmVGT_HOS_MIN_TESS_LEVEL :Result:='mmVGT_HOS_MIN_TESS_LEVEL'; - mmVGT_HOS_REUSE_DEPTH :Result:='mmVGT_HOS_REUSE_DEPTH'; - mmVGT_GROUP_PRIM_TYPE :Result:='mmVGT_GROUP_PRIM_TYPE'; - mmVGT_GROUP_FIRST_DECR :Result:='mmVGT_GROUP_FIRST_DECR'; - mmVGT_GROUP_DECR :Result:='mmVGT_GROUP_DECR'; - mmVGT_GROUP_VECT_0_CNTL :Result:='mmVGT_GROUP_VECT_0_CNTL'; - mmVGT_GROUP_VECT_1_CNTL :Result:='mmVGT_GROUP_VECT_1_CNTL'; - mmVGT_GROUP_VECT_0_FMT_CNTL :Result:='mmVGT_GROUP_VECT_0_FMT_CNTL'; - mmVGT_GROUP_VECT_1_FMT_CNTL :Result:='mmVGT_GROUP_VECT_1_FMT_CNTL'; - mmVGT_GS_MODE :Result:='mmVGT_GS_MODE'; - mmVGT_GS_ONCHIP_CNTL :Result:='mmVGT_GS_ONCHIP_CNTL'; - mmPA_SC_MODE_CNTL_0 :Result:='mmPA_SC_MODE_CNTL_0'; - mmPA_SC_MODE_CNTL_1 :Result:='mmPA_SC_MODE_CNTL_1'; - mmVGT_ENHANCE :Result:='mmVGT_ENHANCE'; - mmVGT_GS_PER_ES :Result:='mmVGT_GS_PER_ES'; - mmVGT_ES_PER_GS :Result:='mmVGT_ES_PER_GS'; - mmVGT_GS_PER_VS :Result:='mmVGT_GS_PER_VS'; - mmVGT_GSVS_RING_OFFSET_1 :Result:='mmVGT_GSVS_RING_OFFSET_1'; - mmVGT_GSVS_RING_OFFSET_2 :Result:='mmVGT_GSVS_RING_OFFSET_2'; - mmVGT_GSVS_RING_OFFSET_3 :Result:='mmVGT_GSVS_RING_OFFSET_3'; - mmVGT_GS_OUT_PRIM_TYPE :Result:='mmVGT_GS_OUT_PRIM_TYPE'; - mmIA_ENHANCE :Result:='mmIA_ENHANCE'; - mmVGT_DMA_SIZE :Result:='mmVGT_DMA_SIZE'; - mmVGT_DMA_MAX_SIZE :Result:='mmVGT_DMA_MAX_SIZE'; - mmVGT_DMA_INDEX_TYPE :Result:='mmVGT_DMA_INDEX_TYPE'; - mmWD_ENHANCE :Result:='mmWD_ENHANCE'; - mmVGT_PRIMITIVEID_EN :Result:='mmVGT_PRIMITIVEID_EN'; - mmVGT_DMA_NUM_INSTANCES :Result:='mmVGT_DMA_NUM_INSTANCES'; - mmVGT_PRIMITIVEID_RESET :Result:='mmVGT_PRIMITIVEID_RESET'; - mmVGT_EVENT_INITIATOR :Result:='mmVGT_EVENT_INITIATOR'; - mmVGT_MULTI_PRIM_IB_RESET_EN :Result:='mmVGT_MULTI_PRIM_IB_RESET_EN'; - mmVGT_INSTANCE_STEP_RATE_0 :Result:='mmVGT_INSTANCE_STEP_RATE_0'; - mmVGT_INSTANCE_STEP_RATE_1 :Result:='mmVGT_INSTANCE_STEP_RATE_1'; - mmIA_MULTI_VGT_PARAM :Result:='mmIA_MULTI_VGT_PARAM'; - mmVGT_ESGS_RING_ITEMSIZE :Result:='mmVGT_ESGS_RING_ITEMSIZE'; - mmVGT_GSVS_RING_ITEMSIZE :Result:='mmVGT_GSVS_RING_ITEMSIZE'; - mmVGT_REUSE_OFF :Result:='mmVGT_REUSE_OFF'; - mmVGT_VTX_CNT_EN :Result:='mmVGT_VTX_CNT_EN'; - mmDB_HTILE_SURFACE :Result:='mmDB_HTILE_SURFACE'; - mmDB_SRESULTS_COMPARE_STATE0 :Result:='mmDB_SRESULTS_COMPARE_STATE0'; - mmDB_SRESULTS_COMPARE_STATE1 :Result:='mmDB_SRESULTS_COMPARE_STATE1'; - mmDB_PRELOAD_CONTROL :Result:='mmDB_PRELOAD_CONTROL'; - mmVGT_STRMOUT_BUFFER_SIZE_0 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_0'; - mmVGT_STRMOUT_VTX_STRIDE_0 :Result:='mmVGT_STRMOUT_VTX_STRIDE_0'; - mmVGT_STRMOUT_BUFFER_OFFSET_0 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_0'; - mmVGT_STRMOUT_BUFFER_SIZE_1 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_1'; - mmVGT_STRMOUT_VTX_STRIDE_1 :Result:='mmVGT_STRMOUT_VTX_STRIDE_1'; - mmVGT_STRMOUT_BUFFER_OFFSET_1 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_1'; - mmVGT_STRMOUT_BUFFER_SIZE_2 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_2'; - mmVGT_STRMOUT_VTX_STRIDE_2 :Result:='mmVGT_STRMOUT_VTX_STRIDE_2'; - mmVGT_STRMOUT_BUFFER_OFFSET_2 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_2'; - mmVGT_STRMOUT_BUFFER_SIZE_3 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_3'; - mmVGT_STRMOUT_VTX_STRIDE_3 :Result:='mmVGT_STRMOUT_VTX_STRIDE_3'; - mmVGT_STRMOUT_BUFFER_OFFSET_3 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_3'; - mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET'; - mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE:Result:='mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE'; - mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE'; - mmVGT_GS_MAX_VERT_OUT :Result:='mmVGT_GS_MAX_VERT_OUT'; - mmVGT_TESS_DISTRIBUTION :Result:='mmVGT_TESS_DISTRIBUTION'; - mmVGT_SHADER_STAGES_EN :Result:='mmVGT_SHADER_STAGES_EN'; - mmVGT_LS_HS_CONFIG :Result:='mmVGT_LS_HS_CONFIG'; - mmVGT_GS_VERT_ITEMSIZE :Result:='mmVGT_GS_VERT_ITEMSIZE'; - mmVGT_GS_VERT_ITEMSIZE_1 :Result:='mmVGT_GS_VERT_ITEMSIZE_1'; - mmVGT_GS_VERT_ITEMSIZE_2 :Result:='mmVGT_GS_VERT_ITEMSIZE_2'; - mmVGT_GS_VERT_ITEMSIZE_3 :Result:='mmVGT_GS_VERT_ITEMSIZE_3'; - mmVGT_TF_PARAM :Result:='mmVGT_TF_PARAM'; - mmDB_ALPHA_TO_MASK :Result:='mmDB_ALPHA_TO_MASK'; - mmVGT_DISPATCH_DRAW_INDEX :Result:='mmVGT_DISPATCH_DRAW_INDEX'; - mmPA_SU_POLY_OFFSET_DB_FMT_CNTL :Result:='mmPA_SU_POLY_OFFSET_DB_FMT_CNTL'; - mmPA_SU_POLY_OFFSET_CLAMP :Result:='mmPA_SU_POLY_OFFSET_CLAMP'; - mmPA_SU_POLY_OFFSET_FRONT_SCALE :Result:='mmPA_SU_POLY_OFFSET_FRONT_SCALE'; - mmPA_SU_POLY_OFFSET_FRONT_OFFSET :Result:='mmPA_SU_POLY_OFFSET_FRONT_OFFSET'; - mmPA_SU_POLY_OFFSET_BACK_SCALE :Result:='mmPA_SU_POLY_OFFSET_BACK_SCALE'; - mmPA_SU_POLY_OFFSET_BACK_OFFSET :Result:='mmPA_SU_POLY_OFFSET_BACK_OFFSET'; - mmVGT_GS_INSTANCE_CNT :Result:='mmVGT_GS_INSTANCE_CNT'; - mmVGT_STRMOUT_CONFIG :Result:='mmVGT_STRMOUT_CONFIG'; - mmVGT_STRMOUT_BUFFER_CONFIG :Result:='mmVGT_STRMOUT_BUFFER_CONFIG'; - mmPA_SC_CENTROID_PRIORITY_0 :Result:='mmPA_SC_CENTROID_PRIORITY_0'; - mmPA_SC_CENTROID_PRIORITY_1 :Result:='mmPA_SC_CENTROID_PRIORITY_1'; - mmPA_SC_LINE_CNTL :Result:='mmPA_SC_LINE_CNTL'; - mmPA_SC_AA_CONFIG :Result:='mmPA_SC_AA_CONFIG'; - mmPA_SU_VTX_CNTL :Result:='mmPA_SU_VTX_CNTL'; - mmPA_CL_GB_VERT_CLIP_ADJ :Result:='mmPA_CL_GB_VERT_CLIP_ADJ'; - mmPA_CL_GB_VERT_DISC_ADJ :Result:='mmPA_CL_GB_VERT_DISC_ADJ'; - mmPA_CL_GB_HORZ_CLIP_ADJ :Result:='mmPA_CL_GB_HORZ_CLIP_ADJ'; - mmPA_CL_GB_HORZ_DISC_ADJ :Result:='mmPA_CL_GB_HORZ_DISC_ADJ'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2'; - mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3'; - mmPA_SC_AA_MASK_X0Y0_X1Y0 :Result:='mmPA_SC_AA_MASK_X0Y0_X1Y0'; - mmPA_SC_AA_MASK_X0Y1_X1Y1 :Result:='mmPA_SC_AA_MASK_X0Y1_X1Y1'; - mmVGT_VERTEX_REUSE_BLOCK_CNTL :Result:='mmVGT_VERTEX_REUSE_BLOCK_CNTL'; - mmVGT_OUT_DEALLOC_CNTL :Result:='mmVGT_OUT_DEALLOC_CNTL'; - mmCB_COLOR0_BASE :Result:='mmCB_COLOR0_BASE'; - mmCB_COLOR0_PITCH :Result:='mmCB_COLOR0_PITCH'; - mmCB_COLOR0_SLICE :Result:='mmCB_COLOR0_SLICE'; - mmCB_COLOR0_VIEW :Result:='mmCB_COLOR0_VIEW'; - mmCB_COLOR0_INFO :Result:='mmCB_COLOR0_INFO'; - mmCB_COLOR0_ATTRIB :Result:='mmCB_COLOR0_ATTRIB'; - mmCB_COLOR0_DCC_CONTROL :Result:='mmCB_COLOR0_DCC_CONTROL'; - mmCB_COLOR0_CMASK :Result:='mmCB_COLOR0_CMASK'; - mmCB_COLOR0_CMASK_SLICE :Result:='mmCB_COLOR0_CMASK_SLICE'; - mmCB_COLOR0_FMASK :Result:='mmCB_COLOR0_FMASK'; - mmCB_COLOR0_FMASK_SLICE :Result:='mmCB_COLOR0_FMASK_SLICE'; - mmCB_COLOR0_CLEAR_WORD0 :Result:='mmCB_COLOR0_CLEAR_WORD0'; - mmCB_COLOR0_CLEAR_WORD1 :Result:='mmCB_COLOR0_CLEAR_WORD1'; - mmCB_COLOR0_DCC_BASE :Result:='mmCB_COLOR0_DCC_BASE'; - mmCB_COLOR1_BASE :Result:='mmCB_COLOR1_BASE'; - mmCB_COLOR1_PITCH :Result:='mmCB_COLOR1_PITCH'; - mmCB_COLOR1_SLICE :Result:='mmCB_COLOR1_SLICE'; - mmCB_COLOR1_VIEW :Result:='mmCB_COLOR1_VIEW'; - mmCB_COLOR1_INFO :Result:='mmCB_COLOR1_INFO'; - mmCB_COLOR1_ATTRIB :Result:='mmCB_COLOR1_ATTRIB'; - mmCB_COLOR1_DCC_CONTROL :Result:='mmCB_COLOR1_DCC_CONTROL'; - mmCB_COLOR1_CMASK :Result:='mmCB_COLOR1_CMASK'; - mmCB_COLOR1_CMASK_SLICE :Result:='mmCB_COLOR1_CMASK_SLICE'; - mmCB_COLOR1_FMASK :Result:='mmCB_COLOR1_FMASK'; - mmCB_COLOR1_FMASK_SLICE :Result:='mmCB_COLOR1_FMASK_SLICE'; - mmCB_COLOR1_CLEAR_WORD0 :Result:='mmCB_COLOR1_CLEAR_WORD0'; - mmCB_COLOR1_CLEAR_WORD1 :Result:='mmCB_COLOR1_CLEAR_WORD1'; - mmCB_COLOR1_DCC_BASE :Result:='mmCB_COLOR1_DCC_BASE'; - mmCB_COLOR2_BASE :Result:='mmCB_COLOR2_BASE'; - mmCB_COLOR2_PITCH :Result:='mmCB_COLOR2_PITCH'; - mmCB_COLOR2_SLICE :Result:='mmCB_COLOR2_SLICE'; - mmCB_COLOR2_VIEW :Result:='mmCB_COLOR2_VIEW'; - mmCB_COLOR2_INFO :Result:='mmCB_COLOR2_INFO'; - mmCB_COLOR2_ATTRIB :Result:='mmCB_COLOR2_ATTRIB'; - mmCB_COLOR2_DCC_CONTROL :Result:='mmCB_COLOR2_DCC_CONTROL'; - mmCB_COLOR2_CMASK :Result:='mmCB_COLOR2_CMASK'; - mmCB_COLOR2_CMASK_SLICE :Result:='mmCB_COLOR2_CMASK_SLICE'; - mmCB_COLOR2_FMASK :Result:='mmCB_COLOR2_FMASK'; - mmCB_COLOR2_FMASK_SLICE :Result:='mmCB_COLOR2_FMASK_SLICE'; - mmCB_COLOR2_CLEAR_WORD0 :Result:='mmCB_COLOR2_CLEAR_WORD0'; - mmCB_COLOR2_CLEAR_WORD1 :Result:='mmCB_COLOR2_CLEAR_WORD1'; - mmCB_COLOR2_DCC_BASE :Result:='mmCB_COLOR2_DCC_BASE'; - mmCB_COLOR3_BASE :Result:='mmCB_COLOR3_BASE'; - mmCB_COLOR3_PITCH :Result:='mmCB_COLOR3_PITCH'; - mmCB_COLOR3_SLICE :Result:='mmCB_COLOR3_SLICE'; - mmCB_COLOR3_VIEW :Result:='mmCB_COLOR3_VIEW'; - mmCB_COLOR3_INFO :Result:='mmCB_COLOR3_INFO'; - mmCB_COLOR3_ATTRIB :Result:='mmCB_COLOR3_ATTRIB'; - mmCB_COLOR3_DCC_CONTROL :Result:='mmCB_COLOR3_DCC_CONTROL'; - mmCB_COLOR3_CMASK :Result:='mmCB_COLOR3_CMASK'; - mmCB_COLOR3_CMASK_SLICE :Result:='mmCB_COLOR3_CMASK_SLICE'; - mmCB_COLOR3_FMASK :Result:='mmCB_COLOR3_FMASK'; - mmCB_COLOR3_FMASK_SLICE :Result:='mmCB_COLOR3_FMASK_SLICE'; - mmCB_COLOR3_CLEAR_WORD0 :Result:='mmCB_COLOR3_CLEAR_WORD0'; - mmCB_COLOR3_CLEAR_WORD1 :Result:='mmCB_COLOR3_CLEAR_WORD1'; - mmCB_COLOR3_DCC_BASE :Result:='mmCB_COLOR3_DCC_BASE'; - mmCB_COLOR4_BASE :Result:='mmCB_COLOR4_BASE'; - mmCB_COLOR4_PITCH :Result:='mmCB_COLOR4_PITCH'; - mmCB_COLOR4_SLICE :Result:='mmCB_COLOR4_SLICE'; - mmCB_COLOR4_VIEW :Result:='mmCB_COLOR4_VIEW'; - mmCB_COLOR4_INFO :Result:='mmCB_COLOR4_INFO'; - mmCB_COLOR4_ATTRIB :Result:='mmCB_COLOR4_ATTRIB'; - mmCB_COLOR4_DCC_CONTROL :Result:='mmCB_COLOR4_DCC_CONTROL'; - mmCB_COLOR4_CMASK :Result:='mmCB_COLOR4_CMASK'; - mmCB_COLOR4_CMASK_SLICE :Result:='mmCB_COLOR4_CMASK_SLICE'; - mmCB_COLOR4_FMASK :Result:='mmCB_COLOR4_FMASK'; - mmCB_COLOR4_FMASK_SLICE :Result:='mmCB_COLOR4_FMASK_SLICE'; - mmCB_COLOR4_CLEAR_WORD0 :Result:='mmCB_COLOR4_CLEAR_WORD0'; - mmCB_COLOR4_CLEAR_WORD1 :Result:='mmCB_COLOR4_CLEAR_WORD1'; - mmCB_COLOR4_DCC_BASE :Result:='mmCB_COLOR4_DCC_BASE'; - mmCB_COLOR5_BASE :Result:='mmCB_COLOR5_BASE'; - mmCB_COLOR5_PITCH :Result:='mmCB_COLOR5_PITCH'; - mmCB_COLOR5_SLICE :Result:='mmCB_COLOR5_SLICE'; - mmCB_COLOR5_VIEW :Result:='mmCB_COLOR5_VIEW'; - mmCB_COLOR5_INFO :Result:='mmCB_COLOR5_INFO'; - mmCB_COLOR5_ATTRIB :Result:='mmCB_COLOR5_ATTRIB'; - mmCB_COLOR5_DCC_CONTROL :Result:='mmCB_COLOR5_DCC_CONTROL'; - mmCB_COLOR5_CMASK :Result:='mmCB_COLOR5_CMASK'; - mmCB_COLOR5_CMASK_SLICE :Result:='mmCB_COLOR5_CMASK_SLICE'; - mmCB_COLOR5_FMASK :Result:='mmCB_COLOR5_FMASK'; - mmCB_COLOR5_FMASK_SLICE :Result:='mmCB_COLOR5_FMASK_SLICE'; - mmCB_COLOR5_CLEAR_WORD0 :Result:='mmCB_COLOR5_CLEAR_WORD0'; - mmCB_COLOR5_CLEAR_WORD1 :Result:='mmCB_COLOR5_CLEAR_WORD1'; - mmCB_COLOR5_DCC_BASE :Result:='mmCB_COLOR5_DCC_BASE'; - mmCB_COLOR6_BASE :Result:='mmCB_COLOR6_BASE'; - mmCB_COLOR6_PITCH :Result:='mmCB_COLOR6_PITCH'; - mmCB_COLOR6_SLICE :Result:='mmCB_COLOR6_SLICE'; - mmCB_COLOR6_VIEW :Result:='mmCB_COLOR6_VIEW'; - mmCB_COLOR6_INFO :Result:='mmCB_COLOR6_INFO'; - mmCB_COLOR6_ATTRIB :Result:='mmCB_COLOR6_ATTRIB'; - mmCB_COLOR6_DCC_CONTROL :Result:='mmCB_COLOR6_DCC_CONTROL'; - mmCB_COLOR6_CMASK :Result:='mmCB_COLOR6_CMASK'; - mmCB_COLOR6_CMASK_SLICE :Result:='mmCB_COLOR6_CMASK_SLICE'; - mmCB_COLOR6_FMASK :Result:='mmCB_COLOR6_FMASK'; - mmCB_COLOR6_FMASK_SLICE :Result:='mmCB_COLOR6_FMASK_SLICE'; - mmCB_COLOR6_CLEAR_WORD0 :Result:='mmCB_COLOR6_CLEAR_WORD0'; - mmCB_COLOR6_CLEAR_WORD1 :Result:='mmCB_COLOR6_CLEAR_WORD1'; - mmCB_COLOR6_DCC_BASE :Result:='mmCB_COLOR6_DCC_BASE'; - mmCB_COLOR7_BASE :Result:='mmCB_COLOR7_BASE'; - mmCB_COLOR7_PITCH :Result:='mmCB_COLOR7_PITCH'; - mmCB_COLOR7_SLICE :Result:='mmCB_COLOR7_SLICE'; - mmCB_COLOR7_VIEW :Result:='mmCB_COLOR7_VIEW'; - mmCB_COLOR7_INFO :Result:='mmCB_COLOR7_INFO'; - mmCB_COLOR7_ATTRIB :Result:='mmCB_COLOR7_ATTRIB'; - mmCB_COLOR7_DCC_CONTROL :Result:='mmCB_COLOR7_DCC_CONTROL'; - mmCB_COLOR7_CMASK :Result:='mmCB_COLOR7_CMASK'; - mmCB_COLOR7_CMASK_SLICE :Result:='mmCB_COLOR7_CMASK_SLICE'; - mmCB_COLOR7_FMASK :Result:='mmCB_COLOR7_FMASK'; - mmCB_COLOR7_FMASK_SLICE :Result:='mmCB_COLOR7_FMASK_SLICE'; - mmCB_COLOR7_CLEAR_WORD0 :Result:='mmCB_COLOR7_CLEAR_WORD0'; - mmCB_COLOR7_CLEAR_WORD1 :Result:='mmCB_COLOR7_CLEAR_WORD1'; - mmCB_COLOR7_DCC_BASE :Result:='mmCB_COLOR7_DCC_BASE'; - mmCP_EOP_DONE_ADDR_LO :Result:='mmCP_EOP_DONE_ADDR_LO'; - mmCP_EOP_DONE_ADDR_HI :Result:='mmCP_EOP_DONE_ADDR_HI'; - mmCP_EOP_DONE_DATA_LO :Result:='mmCP_EOP_DONE_DATA_LO'; - mmCP_EOP_DONE_DATA_HI :Result:='mmCP_EOP_DONE_DATA_HI'; - mmCP_EOP_LAST_FENCE_LO :Result:='mmCP_EOP_LAST_FENCE_LO'; - mmCP_EOP_LAST_FENCE_HI :Result:='mmCP_EOP_LAST_FENCE_HI'; - mmCP_STREAM_OUT_ADDR_LO :Result:='mmCP_STREAM_OUT_ADDR_LO'; - mmCP_STREAM_OUT_ADDR_HI :Result:='mmCP_STREAM_OUT_ADDR_HI'; - mmCP_NUM_PRIM_WRITTEN_COUNT0_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_LO'; - mmCP_NUM_PRIM_WRITTEN_COUNT0_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_HI'; - mmCP_NUM_PRIM_NEEDED_COUNT0_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_LO'; - mmCP_NUM_PRIM_NEEDED_COUNT0_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_HI'; - mmCP_NUM_PRIM_WRITTEN_COUNT1_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_LO'; - mmCP_NUM_PRIM_WRITTEN_COUNT1_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_HI'; - mmCP_NUM_PRIM_NEEDED_COUNT1_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_LO'; - mmCP_NUM_PRIM_NEEDED_COUNT1_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_HI'; - mmCP_NUM_PRIM_WRITTEN_COUNT2_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_LO'; - mmCP_NUM_PRIM_WRITTEN_COUNT2_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_HI'; - mmCP_NUM_PRIM_NEEDED_COUNT2_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_LO'; - mmCP_NUM_PRIM_NEEDED_COUNT2_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_HI'; - mmCP_NUM_PRIM_WRITTEN_COUNT3_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_LO'; - mmCP_NUM_PRIM_WRITTEN_COUNT3_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_HI'; - mmCP_NUM_PRIM_NEEDED_COUNT3_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_LO'; - mmCP_NUM_PRIM_NEEDED_COUNT3_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_HI'; - mmCP_PIPE_STATS_ADDR_LO :Result:='mmCP_PIPE_STATS_ADDR_LO'; - mmCP_PIPE_STATS_ADDR_HI :Result:='mmCP_PIPE_STATS_ADDR_HI'; - mmCP_VGT_IAVERT_COUNT_LO :Result:='mmCP_VGT_IAVERT_COUNT_LO'; - mmCP_VGT_IAVERT_COUNT_HI :Result:='mmCP_VGT_IAVERT_COUNT_HI'; - mmCP_VGT_IAPRIM_COUNT_LO :Result:='mmCP_VGT_IAPRIM_COUNT_LO'; - mmCP_VGT_IAPRIM_COUNT_HI :Result:='mmCP_VGT_IAPRIM_COUNT_HI'; - mmCP_VGT_GSPRIM_COUNT_LO :Result:='mmCP_VGT_GSPRIM_COUNT_LO'; - mmCP_VGT_GSPRIM_COUNT_HI :Result:='mmCP_VGT_GSPRIM_COUNT_HI'; - mmCP_VGT_VSINVOC_COUNT_LO :Result:='mmCP_VGT_VSINVOC_COUNT_LO'; - mmCP_VGT_VSINVOC_COUNT_HI :Result:='mmCP_VGT_VSINVOC_COUNT_HI'; - mmCP_VGT_GSINVOC_COUNT_LO :Result:='mmCP_VGT_GSINVOC_COUNT_LO'; - mmCP_VGT_GSINVOC_COUNT_HI :Result:='mmCP_VGT_GSINVOC_COUNT_HI'; - mmCP_VGT_HSINVOC_COUNT_LO :Result:='mmCP_VGT_HSINVOC_COUNT_LO'; - mmCP_VGT_HSINVOC_COUNT_HI :Result:='mmCP_VGT_HSINVOC_COUNT_HI'; - mmCP_VGT_DSINVOC_COUNT_LO :Result:='mmCP_VGT_DSINVOC_COUNT_LO'; - mmCP_VGT_DSINVOC_COUNT_HI :Result:='mmCP_VGT_DSINVOC_COUNT_HI'; - mmCP_PA_CINVOC_COUNT_LO :Result:='mmCP_PA_CINVOC_COUNT_LO'; - mmCP_PA_CINVOC_COUNT_HI :Result:='mmCP_PA_CINVOC_COUNT_HI'; - mmCP_PA_CPRIM_COUNT_LO :Result:='mmCP_PA_CPRIM_COUNT_LO'; - mmCP_PA_CPRIM_COUNT_HI :Result:='mmCP_PA_CPRIM_COUNT_HI'; - mmCP_SC_PSINVOC_COUNT0_LO :Result:='mmCP_SC_PSINVOC_COUNT0_LO'; - mmCP_SC_PSINVOC_COUNT0_HI :Result:='mmCP_SC_PSINVOC_COUNT0_HI'; - mmCP_SC_PSINVOC_COUNT1_LO :Result:='mmCP_SC_PSINVOC_COUNT1_LO'; - mmCP_SC_PSINVOC_COUNT1_HI :Result:='mmCP_SC_PSINVOC_COUNT1_HI'; - mmCP_VGT_CSINVOC_COUNT_LO :Result:='mmCP_VGT_CSINVOC_COUNT_LO'; - mmCP_VGT_CSINVOC_COUNT_HI :Result:='mmCP_VGT_CSINVOC_COUNT_HI'; - mmCP_PIPE_STATS_CONTROL :Result:='mmCP_PIPE_STATS_CONTROL'; - mmCP_STREAM_OUT_CONTROL :Result:='mmCP_STREAM_OUT_CONTROL'; - mmCP_STRMOUT_CNTL :Result:='mmCP_STRMOUT_CNTL'; - mmCP_PFP_ATOMIC_PREOP_LO :Result:='mmCP_PFP_ATOMIC_PREOP_LO'; - mmCP_PFP_ATOMIC_PREOP_HI :Result:='mmCP_PFP_ATOMIC_PREOP_HI'; - mmCP_PFP_GDS_ATOMIC0_PREOP_LO :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_LO'; - mmCP_PFP_GDS_ATOMIC0_PREOP_HI :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_HI'; - mmCP_PFP_GDS_ATOMIC1_PREOP_LO :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_LO'; - mmCP_PFP_GDS_ATOMIC1_PREOP_HI :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_HI'; - mmCP_APPEND_ADDR_LO :Result:='mmCP_APPEND_ADDR_LO'; - mmCP_APPEND_ADDR_HI :Result:='mmCP_APPEND_ADDR_HI'; - mmCP_APPEND_DATA :Result:='mmCP_APPEND_DATA'; - mmCP_APPEND_LAST_CS_FENCE :Result:='mmCP_APPEND_LAST_CS_FENCE'; - mmCP_APPEND_LAST_PS_FENCE :Result:='mmCP_APPEND_LAST_PS_FENCE'; - mmCP_ATOMIC_PREOP_LO :Result:='mmCP_ATOMIC_PREOP_LO'; - mmCP_ATOMIC_PREOP_HI :Result:='mmCP_ATOMIC_PREOP_HI'; - mmCP_GDS_ATOMIC0_PREOP_LO :Result:='mmCP_GDS_ATOMIC0_PREOP_LO'; - mmCP_GDS_ATOMIC0_PREOP_HI :Result:='mmCP_GDS_ATOMIC0_PREOP_HI'; - mmCP_GDS_ATOMIC1_PREOP_LO :Result:='mmCP_GDS_ATOMIC1_PREOP_LO'; - mmCP_GDS_ATOMIC1_PREOP_HI :Result:='mmCP_GDS_ATOMIC1_PREOP_HI'; - mmCP_SEM_WAIT_TIMER :Result:='mmCP_SEM_WAIT_TIMER'; - mmCP_SIG_SEM_ADDR_LO :Result:='mmCP_SIG_SEM_ADDR_LO'; - mmCP_SIG_SEM_ADDR_HI :Result:='mmCP_SIG_SEM_ADDR_HI'; - mmCP_WAIT_REG_MEM_TIMEOUT :Result:='mmCP_WAIT_REG_MEM_TIMEOUT'; - mmCP_WAIT_SEM_ADDR_LO :Result:='mmCP_WAIT_SEM_ADDR_LO'; - mmCP_WAIT_SEM_ADDR_HI :Result:='mmCP_WAIT_SEM_ADDR_HI'; - mmCP_DMA_PFP_CONTROL :Result:='mmCP_DMA_PFP_CONTROL'; - mmCP_DMA_ME_CONTROL :Result:='mmCP_DMA_ME_CONTROL'; - mmCP_COHER_BASE_HI :Result:='mmCP_COHER_BASE_HI'; - mmCP_COHER_START_DELAY :Result:='mmCP_COHER_START_DELAY'; - mmCP_COHER_CNTL :Result:='mmCP_COHER_CNTL'; - mmCP_COHER_SIZE :Result:='mmCP_COHER_SIZE'; - mmCP_COHER_BASE :Result:='mmCP_COHER_BASE'; - mmCP_COHER_STATUS :Result:='mmCP_COHER_STATUS'; - mmCP_DMA_ME_SRC_ADDR :Result:='mmCP_DMA_ME_SRC_ADDR'; - mmCP_DMA_ME_SRC_ADDR_HI :Result:='mmCP_DMA_ME_SRC_ADDR_HI'; - mmCP_DMA_ME_DST_ADDR :Result:='mmCP_DMA_ME_DST_ADDR'; - mmCP_DMA_ME_DST_ADDR_HI :Result:='mmCP_DMA_ME_DST_ADDR_HI'; - mmCP_DMA_ME_COMMAND :Result:='mmCP_DMA_ME_COMMAND'; - mmCP_DMA_PFP_SRC_ADDR :Result:='mmCP_DMA_PFP_SRC_ADDR'; - mmCP_DMA_PFP_SRC_ADDR_HI :Result:='mmCP_DMA_PFP_SRC_ADDR_HI'; - mmCP_DMA_PFP_DST_ADDR :Result:='mmCP_DMA_PFP_DST_ADDR'; - mmCP_DMA_PFP_DST_ADDR_HI :Result:='mmCP_DMA_PFP_DST_ADDR_HI'; - mmCP_DMA_PFP_COMMAND :Result:='mmCP_DMA_PFP_COMMAND'; - mmCP_DMA_CNTL :Result:='mmCP_DMA_CNTL'; - mmCP_DMA_READ_TAGS :Result:='mmCP_DMA_READ_TAGS'; - mmCP_COHER_SIZE_HI :Result:='mmCP_COHER_SIZE_HI'; - mmCP_PFP_IB_CONTROL :Result:='mmCP_PFP_IB_CONTROL'; - mmCP_PFP_LOAD_CONTROL :Result:='mmCP_PFP_LOAD_CONTROL'; - mmCP_SCRATCH_INDEX :Result:='mmCP_SCRATCH_INDEX'; - mmCP_SCRATCH_DATA :Result:='mmCP_SCRATCH_DATA'; - mmCP_IB1_OFFSET :Result:='mmCP_IB1_OFFSET'; - mmCP_IB2_OFFSET :Result:='mmCP_IB2_OFFSET'; - mmCP_IB1_PREAMBLE_BEGIN :Result:='mmCP_IB1_PREAMBLE_BEGIN'; - mmCP_IB1_PREAMBLE_END :Result:='mmCP_IB1_PREAMBLE_END'; - mmCP_IB2_PREAMBLE_BEGIN :Result:='mmCP_IB2_PREAMBLE_BEGIN'; - mmCP_IB2_PREAMBLE_END :Result:='mmCP_IB2_PREAMBLE_END'; - mmCP_CE_IB1_OFFSET :Result:='mmCP_CE_IB1_OFFSET'; - mmCP_CE_IB2_OFFSET :Result:='mmCP_CE_IB2_OFFSET'; - mmCP_CE_COUNTER :Result:='mmCP_CE_COUNTER'; - mmCP_CE_RB_OFFSET :Result:='mmCP_CE_RB_OFFSET'; - mmCP_CE_INIT_BASE_LO :Result:='mmCP_CE_INIT_BASE_LO'; - mmCP_CE_INIT_BASE_HI :Result:='mmCP_CE_INIT_BASE_HI'; - mmCP_CE_INIT_BUFSZ :Result:='mmCP_CE_INIT_BUFSZ'; - mmCP_CE_IB1_BASE_LO :Result:='mmCP_CE_IB1_BASE_LO'; - mmCP_CE_IB1_BASE_HI :Result:='mmCP_CE_IB1_BASE_HI'; - mmCP_CE_IB1_BUFSZ :Result:='mmCP_CE_IB1_BUFSZ'; - mmCP_CE_IB2_BASE_LO :Result:='mmCP_CE_IB2_BASE_LO'; - mmCP_CE_IB2_BASE_HI :Result:='mmCP_CE_IB2_BASE_HI'; - mmCP_CE_IB2_BUFSZ :Result:='mmCP_CE_IB2_BUFSZ'; - mmCP_IB1_BASE_LO :Result:='mmCP_IB1_BASE_LO'; - mmCP_IB1_BASE_HI :Result:='mmCP_IB1_BASE_HI'; - mmCP_IB1_BUFSZ :Result:='mmCP_IB1_BUFSZ'; - mmCP_IB2_BASE_LO :Result:='mmCP_IB2_BASE_LO'; - mmCP_IB2_BASE_HI :Result:='mmCP_IB2_BASE_HI'; - mmCP_IB2_BUFSZ :Result:='mmCP_IB2_BUFSZ'; - mmCP_ST_BASE_LO :Result:='mmCP_ST_BASE_LO'; - mmCP_ST_BASE_HI :Result:='mmCP_ST_BASE_HI'; - mmCP_ST_BUFSZ :Result:='mmCP_ST_BUFSZ'; - mmCP_EOP_DONE_EVENT_CNTL :Result:='mmCP_EOP_DONE_EVENT_CNTL'; - mmCP_EOP_DONE_DATA_CNTL :Result:='mmCP_EOP_DONE_DATA_CNTL'; - mmCP_EOP_DONE_CNTX_ID :Result:='mmCP_EOP_DONE_CNTX_ID'; - mmCP_PFP_COMPLETION_STATUS :Result:='mmCP_PFP_COMPLETION_STATUS'; - mmCP_CE_COMPLETION_STATUS :Result:='mmCP_CE_COMPLETION_STATUS'; - mmCP_PRED_NOT_VISIBLE :Result:='mmCP_PRED_NOT_VISIBLE'; - mmCP_PFP_METADATA_BASE_ADDR :Result:='mmCP_PFP_METADATA_BASE_ADDR'; - mmCP_PFP_METADATA_BASE_ADDR_HI :Result:='mmCP_PFP_METADATA_BASE_ADDR_HI'; - mmCP_CE_METADATA_BASE_ADDR :Result:='mmCP_CE_METADATA_BASE_ADDR'; - mmCP_CE_METADATA_BASE_ADDR_HI :Result:='mmCP_CE_METADATA_BASE_ADDR_HI'; - mmCP_DRAW_INDX_INDR_ADDR :Result:='mmCP_DRAW_INDX_INDR_ADDR'; - mmCP_DRAW_INDX_INDR_ADDR_HI :Result:='mmCP_DRAW_INDX_INDR_ADDR_HI'; - mmCP_DISPATCH_INDR_ADDR :Result:='mmCP_DISPATCH_INDR_ADDR'; - mmCP_DISPATCH_INDR_ADDR_HI :Result:='mmCP_DISPATCH_INDR_ADDR_HI'; - mmCP_INDEX_BASE_ADDR :Result:='mmCP_INDEX_BASE_ADDR'; - mmCP_INDEX_BASE_ADDR_HI :Result:='mmCP_INDEX_BASE_ADDR_HI'; - mmCP_INDEX_TYPE :Result:='mmCP_INDEX_TYPE'; - mmCP_GDS_BKUP_ADDR :Result:='mmCP_GDS_BKUP_ADDR'; - mmCP_GDS_BKUP_ADDR_HI :Result:='mmCP_GDS_BKUP_ADDR_HI'; - mmCP_SAMPLE_STATUS :Result:='mmCP_SAMPLE_STATUS'; - mmGRBM_GFX_INDEX :Result:='mmGRBM_GFX_INDEX'; - mmVGT_ESGS_RING_SIZE :Result:='mmVGT_ESGS_RING_SIZE'; - mmVGT_GSVS_RING_SIZE :Result:='mmVGT_GSVS_RING_SIZE'; - mmVGT_PRIMITIVE_TYPE :Result:='mmVGT_PRIMITIVE_TYPE'; - mmVGT_INDEX_TYPE :Result:='mmVGT_INDEX_TYPE'; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0'; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1'; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2'; - mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3'; - mmVGT_NUM_INDICES :Result:='mmVGT_NUM_INDICES'; - mmVGT_NUM_INSTANCES :Result:='mmVGT_NUM_INSTANCES'; - mmVGT_TF_RING_SIZE :Result:='mmVGT_TF_RING_SIZE'; - mmVGT_HS_OFFCHIP_PARAM :Result:='mmVGT_HS_OFFCHIP_PARAM'; - mmVGT_TF_MEMORY_BASE :Result:='mmVGT_TF_MEMORY_BASE'; - mmPA_SU_LINE_STIPPLE_VALUE :Result:='mmPA_SU_LINE_STIPPLE_VALUE'; - mmPA_SC_LINE_STIPPLE_STATE :Result:='mmPA_SC_LINE_STIPPLE_STATE'; - mmPA_SC_P3D_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_EN'; - mmPA_SC_P3D_TRAP_SCREEN_H :Result:='mmPA_SC_P3D_TRAP_SCREEN_H'; - mmPA_SC_P3D_TRAP_SCREEN_V :Result:='mmPA_SC_P3D_TRAP_SCREEN_V'; - mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE'; - mmPA_SC_P3D_TRAP_SCREEN_COUNT :Result:='mmPA_SC_P3D_TRAP_SCREEN_COUNT'; - mmPA_SC_HP3D_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_EN'; - mmPA_SC_HP3D_TRAP_SCREEN_H :Result:='mmPA_SC_HP3D_TRAP_SCREEN_H'; - mmPA_SC_HP3D_TRAP_SCREEN_V :Result:='mmPA_SC_HP3D_TRAP_SCREEN_V'; - mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE'; - mmPA_SC_HP3D_TRAP_SCREEN_COUNT :Result:='mmPA_SC_HP3D_TRAP_SCREEN_COUNT'; - mmPA_SC_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_TRAP_SCREEN_HV_EN'; - mmPA_SC_TRAP_SCREEN_H :Result:='mmPA_SC_TRAP_SCREEN_H'; - mmPA_SC_TRAP_SCREEN_V :Result:='mmPA_SC_TRAP_SCREEN_V'; - mmPA_SC_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_TRAP_SCREEN_OCCURRENCE'; - mmPA_SC_TRAP_SCREEN_COUNT :Result:='mmPA_SC_TRAP_SCREEN_COUNT'; - mmSQ_THREAD_TRACE_BASE :Result:='mmSQ_THREAD_TRACE_BASE'; - mmSQ_THREAD_TRACE_SIZE :Result:='mmSQ_THREAD_TRACE_SIZE'; - mmSQ_THREAD_TRACE_MASK :Result:='mmSQ_THREAD_TRACE_MASK'; - mmSQ_THREAD_TRACE_TOKEN_MASK :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK'; - mmSQ_THREAD_TRACE_PERF_MASK :Result:='mmSQ_THREAD_TRACE_PERF_MASK'; - mmSQ_THREAD_TRACE_CTRL :Result:='mmSQ_THREAD_TRACE_CTRL'; - mmSQ_THREAD_TRACE_MODE :Result:='mmSQ_THREAD_TRACE_MODE'; - mmSQ_THREAD_TRACE_BASE2 :Result:='mmSQ_THREAD_TRACE_BASE2'; - mmSQ_THREAD_TRACE_TOKEN_MASK2 :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK2'; - mmSQ_THREAD_TRACE_WPTR :Result:='mmSQ_THREAD_TRACE_WPTR'; - mmSQ_THREAD_TRACE_STATUS :Result:='mmSQ_THREAD_TRACE_STATUS'; - mmSQ_THREAD_TRACE_HIWATER :Result:='mmSQ_THREAD_TRACE_HIWATER'; - mmSQ_THREAD_TRACE_USERDATA_0 :Result:='mmSQ_THREAD_TRACE_USERDATA_0'; - mmSQ_THREAD_TRACE_USERDATA_1 :Result:='mmSQ_THREAD_TRACE_USERDATA_1'; - mmSQ_THREAD_TRACE_USERDATA_2 :Result:='mmSQ_THREAD_TRACE_USERDATA_2'; - mmSQ_THREAD_TRACE_USERDATA_3 :Result:='mmSQ_THREAD_TRACE_USERDATA_3'; - mmTA_CS_BC_BASE_ADDR :Result:='mmTA_CS_BC_BASE_ADDR'; - mmTA_CS_BC_BASE_ADDR_HI :Result:='mmTA_CS_BC_BASE_ADDR_HI'; - mmDB_OCCLUSION_COUNT0_LOW :Result:='mmDB_OCCLUSION_COUNT0_LOW'; - mmDB_OCCLUSION_COUNT0_HI :Result:='mmDB_OCCLUSION_COUNT0_HI'; - mmDB_OCCLUSION_COUNT1_LOW :Result:='mmDB_OCCLUSION_COUNT1_LOW'; - mmDB_OCCLUSION_COUNT1_HI :Result:='mmDB_OCCLUSION_COUNT1_HI'; - mmDB_OCCLUSION_COUNT2_LOW :Result:='mmDB_OCCLUSION_COUNT2_LOW'; - mmDB_OCCLUSION_COUNT2_HI :Result:='mmDB_OCCLUSION_COUNT2_HI'; - mmDB_OCCLUSION_COUNT3_LOW :Result:='mmDB_OCCLUSION_COUNT3_LOW'; - mmDB_OCCLUSION_COUNT3_HI :Result:='mmDB_OCCLUSION_COUNT3_HI'; - mmDB_ZPASS_COUNT_LOW :Result:='mmDB_ZPASS_COUNT_LOW'; - mmDB_ZPASS_COUNT_HI :Result:='mmDB_ZPASS_COUNT_HI'; - mmGDS_RD_ADDR :Result:='mmGDS_RD_ADDR'; - mmGDS_RD_DATA :Result:='mmGDS_RD_DATA'; - mmGDS_RD_BURST_ADDR :Result:='mmGDS_RD_BURST_ADDR'; - mmGDS_RD_BURST_COUNT :Result:='mmGDS_RD_BURST_COUNT'; - mmGDS_RD_BURST_DATA :Result:='mmGDS_RD_BURST_DATA'; - mmGDS_WR_ADDR :Result:='mmGDS_WR_ADDR'; - mmGDS_WR_DATA :Result:='mmGDS_WR_DATA'; - mmGDS_WR_BURST_ADDR :Result:='mmGDS_WR_BURST_ADDR'; - mmGDS_WR_BURST_DATA :Result:='mmGDS_WR_BURST_DATA'; - mmGDS_WRITE_COMPLETE :Result:='mmGDS_WRITE_COMPLETE'; - mmGDS_ATOM_CNTL :Result:='mmGDS_ATOM_CNTL'; - mmGDS_ATOM_COMPLETE :Result:='mmGDS_ATOM_COMPLETE'; - mmGDS_ATOM_BASE :Result:='mmGDS_ATOM_BASE'; - mmGDS_ATOM_SIZE :Result:='mmGDS_ATOM_SIZE'; - mmGDS_ATOM_OFFSET0 :Result:='mmGDS_ATOM_OFFSET0'; - mmGDS_ATOM_OFFSET1 :Result:='mmGDS_ATOM_OFFSET1'; - mmGDS_ATOM_DST :Result:='mmGDS_ATOM_DST'; - mmGDS_ATOM_OP :Result:='mmGDS_ATOM_OP'; - mmGDS_ATOM_SRC0 :Result:='mmGDS_ATOM_SRC0'; - mmGDS_ATOM_SRC0_U :Result:='mmGDS_ATOM_SRC0_U'; - mmGDS_ATOM_SRC1 :Result:='mmGDS_ATOM_SRC1'; - mmGDS_ATOM_SRC1_U :Result:='mmGDS_ATOM_SRC1_U'; - mmGDS_ATOM_READ0 :Result:='mmGDS_ATOM_READ0'; - mmGDS_ATOM_READ0_U :Result:='mmGDS_ATOM_READ0_U'; - mmGDS_ATOM_READ1 :Result:='mmGDS_ATOM_READ1'; - mmGDS_ATOM_READ1_U :Result:='mmGDS_ATOM_READ1_U'; - mmGDS_GWS_RESOURCE_CNTL :Result:='mmGDS_GWS_RESOURCE_CNTL'; - mmGDS_GWS_RESOURCE :Result:='mmGDS_GWS_RESOURCE'; - mmGDS_GWS_RESOURCE_CNT :Result:='mmGDS_GWS_RESOURCE_CNT'; - mmGDS_OA_CNTL :Result:='mmGDS_OA_CNTL'; - mmGDS_OA_COUNTER :Result:='mmGDS_OA_COUNTER'; - mmGDS_OA_ADDRESS :Result:='mmGDS_OA_ADDRESS'; - mmGDS_OA_INCDEC :Result:='mmGDS_OA_INCDEC'; - mmGDS_OA_RING_SIZE :Result:='mmGDS_OA_RING_SIZE'; - mmCPG_PERFCOUNTER1_LO :Result:='mmCPG_PERFCOUNTER1_LO'; - mmCPG_PERFCOUNTER1_HI :Result:='mmCPG_PERFCOUNTER1_HI'; - mmCPG_PERFCOUNTER0_LO :Result:='mmCPG_PERFCOUNTER0_LO'; - mmCPG_PERFCOUNTER0_HI :Result:='mmCPG_PERFCOUNTER0_HI'; - mmCPC_PERFCOUNTER1_LO :Result:='mmCPC_PERFCOUNTER1_LO'; - mmCPC_PERFCOUNTER1_HI :Result:='mmCPC_PERFCOUNTER1_HI'; - mmCPC_PERFCOUNTER0_LO :Result:='mmCPC_PERFCOUNTER0_LO'; - mmCPC_PERFCOUNTER0_HI :Result:='mmCPC_PERFCOUNTER0_HI'; - mmCPF_PERFCOUNTER1_LO :Result:='mmCPF_PERFCOUNTER1_LO'; - mmCPF_PERFCOUNTER1_HI :Result:='mmCPF_PERFCOUNTER1_HI'; - mmCPF_PERFCOUNTER0_LO :Result:='mmCPF_PERFCOUNTER0_LO'; - mmCPF_PERFCOUNTER0_HI :Result:='mmCPF_PERFCOUNTER0_HI'; - mmGRBM_PERFCOUNTER0_LO :Result:='mmGRBM_PERFCOUNTER0_LO'; - mmGRBM_PERFCOUNTER0_HI :Result:='mmGRBM_PERFCOUNTER0_HI'; - mmGRBM_PERFCOUNTER1_LO :Result:='mmGRBM_PERFCOUNTER1_LO'; - mmGRBM_PERFCOUNTER1_HI :Result:='mmGRBM_PERFCOUNTER1_HI'; - mmGRBM_SE0_PERFCOUNTER_LO :Result:='mmGRBM_SE0_PERFCOUNTER_LO'; - mmGRBM_SE0_PERFCOUNTER_HI :Result:='mmGRBM_SE0_PERFCOUNTER_HI'; - mmGRBM_SE1_PERFCOUNTER_LO :Result:='mmGRBM_SE1_PERFCOUNTER_LO'; - mmGRBM_SE1_PERFCOUNTER_HI :Result:='mmGRBM_SE1_PERFCOUNTER_HI'; - mmGRBM_SE2_PERFCOUNTER_LO :Result:='mmGRBM_SE2_PERFCOUNTER_LO'; - mmGRBM_SE2_PERFCOUNTER_HI :Result:='mmGRBM_SE2_PERFCOUNTER_HI'; - mmGRBM_SE3_PERFCOUNTER_LO :Result:='mmGRBM_SE3_PERFCOUNTER_LO'; - mmGRBM_SE3_PERFCOUNTER_HI :Result:='mmGRBM_SE3_PERFCOUNTER_HI'; - mmWD_PERFCOUNTER0_LO :Result:='mmWD_PERFCOUNTER0_LO'; - mmWD_PERFCOUNTER0_HI :Result:='mmWD_PERFCOUNTER0_HI'; - mmWD_PERFCOUNTER1_LO :Result:='mmWD_PERFCOUNTER1_LO'; - mmWD_PERFCOUNTER1_HI :Result:='mmWD_PERFCOUNTER1_HI'; - mmWD_PERFCOUNTER2_LO :Result:='mmWD_PERFCOUNTER2_LO'; - mmWD_PERFCOUNTER2_HI :Result:='mmWD_PERFCOUNTER2_HI'; - mmWD_PERFCOUNTER3_LO :Result:='mmWD_PERFCOUNTER3_LO'; - mmWD_PERFCOUNTER3_HI :Result:='mmWD_PERFCOUNTER3_HI'; - mmIA_PERFCOUNTER0_LO :Result:='mmIA_PERFCOUNTER0_LO'; - mmIA_PERFCOUNTER0_HI :Result:='mmIA_PERFCOUNTER0_HI'; - mmIA_PERFCOUNTER1_LO :Result:='mmIA_PERFCOUNTER1_LO'; - mmIA_PERFCOUNTER1_HI :Result:='mmIA_PERFCOUNTER1_HI'; - mmIA_PERFCOUNTER2_LO :Result:='mmIA_PERFCOUNTER2_LO'; - mmIA_PERFCOUNTER2_HI :Result:='mmIA_PERFCOUNTER2_HI'; - mmIA_PERFCOUNTER3_LO :Result:='mmIA_PERFCOUNTER3_LO'; - mmIA_PERFCOUNTER3_HI :Result:='mmIA_PERFCOUNTER3_HI'; - mmVGT_PERFCOUNTER0_LO :Result:='mmVGT_PERFCOUNTER0_LO'; - mmVGT_PERFCOUNTER0_HI :Result:='mmVGT_PERFCOUNTER0_HI'; - mmVGT_PERFCOUNTER1_LO :Result:='mmVGT_PERFCOUNTER1_LO'; - mmVGT_PERFCOUNTER1_HI :Result:='mmVGT_PERFCOUNTER1_HI'; - mmVGT_PERFCOUNTER2_LO :Result:='mmVGT_PERFCOUNTER2_LO'; - mmVGT_PERFCOUNTER2_HI :Result:='mmVGT_PERFCOUNTER2_HI'; - mmVGT_PERFCOUNTER3_LO :Result:='mmVGT_PERFCOUNTER3_LO'; - mmVGT_PERFCOUNTER3_HI :Result:='mmVGT_PERFCOUNTER3_HI'; - mmPA_SU_PERFCOUNTER0_LO :Result:='mmPA_SU_PERFCOUNTER0_LO'; - mmPA_SU_PERFCOUNTER0_HI :Result:='mmPA_SU_PERFCOUNTER0_HI'; - mmPA_SU_PERFCOUNTER1_LO :Result:='mmPA_SU_PERFCOUNTER1_LO'; - mmPA_SU_PERFCOUNTER1_HI :Result:='mmPA_SU_PERFCOUNTER1_HI'; - mmPA_SU_PERFCOUNTER2_LO :Result:='mmPA_SU_PERFCOUNTER2_LO'; - mmPA_SU_PERFCOUNTER2_HI :Result:='mmPA_SU_PERFCOUNTER2_HI'; - mmPA_SU_PERFCOUNTER3_LO :Result:='mmPA_SU_PERFCOUNTER3_LO'; - mmPA_SU_PERFCOUNTER3_HI :Result:='mmPA_SU_PERFCOUNTER3_HI'; - mmPA_SC_PERFCOUNTER0_LO :Result:='mmPA_SC_PERFCOUNTER0_LO'; - mmPA_SC_PERFCOUNTER0_HI :Result:='mmPA_SC_PERFCOUNTER0_HI'; - mmPA_SC_PERFCOUNTER1_LO :Result:='mmPA_SC_PERFCOUNTER1_LO'; - mmPA_SC_PERFCOUNTER1_HI :Result:='mmPA_SC_PERFCOUNTER1_HI'; - mmPA_SC_PERFCOUNTER2_LO :Result:='mmPA_SC_PERFCOUNTER2_LO'; - mmPA_SC_PERFCOUNTER2_HI :Result:='mmPA_SC_PERFCOUNTER2_HI'; - mmPA_SC_PERFCOUNTER3_LO :Result:='mmPA_SC_PERFCOUNTER3_LO'; - mmPA_SC_PERFCOUNTER3_HI :Result:='mmPA_SC_PERFCOUNTER3_HI'; - mmPA_SC_PERFCOUNTER4_LO :Result:='mmPA_SC_PERFCOUNTER4_LO'; - mmPA_SC_PERFCOUNTER4_HI :Result:='mmPA_SC_PERFCOUNTER4_HI'; - mmPA_SC_PERFCOUNTER5_LO :Result:='mmPA_SC_PERFCOUNTER5_LO'; - mmPA_SC_PERFCOUNTER5_HI :Result:='mmPA_SC_PERFCOUNTER5_HI'; - mmPA_SC_PERFCOUNTER6_LO :Result:='mmPA_SC_PERFCOUNTER6_LO'; - mmPA_SC_PERFCOUNTER6_HI :Result:='mmPA_SC_PERFCOUNTER6_HI'; - mmPA_SC_PERFCOUNTER7_LO :Result:='mmPA_SC_PERFCOUNTER7_LO'; - mmPA_SC_PERFCOUNTER7_HI :Result:='mmPA_SC_PERFCOUNTER7_HI'; - mmSPI_PERFCOUNTER0_HI :Result:='mmSPI_PERFCOUNTER0_HI'; - mmSPI_PERFCOUNTER0_LO :Result:='mmSPI_PERFCOUNTER0_LO'; - mmSPI_PERFCOUNTER1_HI :Result:='mmSPI_PERFCOUNTER1_HI'; - mmSPI_PERFCOUNTER1_LO :Result:='mmSPI_PERFCOUNTER1_LO'; - mmSPI_PERFCOUNTER2_HI :Result:='mmSPI_PERFCOUNTER2_HI'; - mmSPI_PERFCOUNTER2_LO :Result:='mmSPI_PERFCOUNTER2_LO'; - mmSPI_PERFCOUNTER3_HI :Result:='mmSPI_PERFCOUNTER3_HI'; - mmSPI_PERFCOUNTER3_LO :Result:='mmSPI_PERFCOUNTER3_LO'; - mmSPI_PERFCOUNTER4_HI :Result:='mmSPI_PERFCOUNTER4_HI'; - mmSPI_PERFCOUNTER4_LO :Result:='mmSPI_PERFCOUNTER4_LO'; - mmSPI_PERFCOUNTER5_HI :Result:='mmSPI_PERFCOUNTER5_HI'; - mmSPI_PERFCOUNTER5_LO :Result:='mmSPI_PERFCOUNTER5_LO'; - mmSQ_PERFCOUNTER0_LO :Result:='mmSQ_PERFCOUNTER0_LO'; - mmSQ_PERFCOUNTER0_HI :Result:='mmSQ_PERFCOUNTER0_HI'; - mmSQ_PERFCOUNTER1_LO :Result:='mmSQ_PERFCOUNTER1_LO'; - mmSQ_PERFCOUNTER1_HI :Result:='mmSQ_PERFCOUNTER1_HI'; - mmSQ_PERFCOUNTER2_LO :Result:='mmSQ_PERFCOUNTER2_LO'; - mmSQ_PERFCOUNTER2_HI :Result:='mmSQ_PERFCOUNTER2_HI'; - mmSQ_PERFCOUNTER3_LO :Result:='mmSQ_PERFCOUNTER3_LO'; - mmSQ_PERFCOUNTER3_HI :Result:='mmSQ_PERFCOUNTER3_HI'; - mmSQ_PERFCOUNTER4_LO :Result:='mmSQ_PERFCOUNTER4_LO'; - mmSQ_PERFCOUNTER4_HI :Result:='mmSQ_PERFCOUNTER4_HI'; - mmSQ_PERFCOUNTER5_LO :Result:='mmSQ_PERFCOUNTER5_LO'; - mmSQ_PERFCOUNTER5_HI :Result:='mmSQ_PERFCOUNTER5_HI'; - mmSQ_PERFCOUNTER6_LO :Result:='mmSQ_PERFCOUNTER6_LO'; - mmSQ_PERFCOUNTER6_HI :Result:='mmSQ_PERFCOUNTER6_HI'; - mmSQ_PERFCOUNTER7_LO :Result:='mmSQ_PERFCOUNTER7_LO'; - mmSQ_PERFCOUNTER7_HI :Result:='mmSQ_PERFCOUNTER7_HI'; - mmSQ_PERFCOUNTER8_LO :Result:='mmSQ_PERFCOUNTER8_LO'; - mmSQ_PERFCOUNTER8_HI :Result:='mmSQ_PERFCOUNTER8_HI'; - mmSQ_PERFCOUNTER9_LO :Result:='mmSQ_PERFCOUNTER9_LO'; - mmSQ_PERFCOUNTER9_HI :Result:='mmSQ_PERFCOUNTER9_HI'; - mmSQ_PERFCOUNTER10_LO :Result:='mmSQ_PERFCOUNTER10_LO'; - mmSQ_PERFCOUNTER10_HI :Result:='mmSQ_PERFCOUNTER10_HI'; - mmSQ_PERFCOUNTER11_LO :Result:='mmSQ_PERFCOUNTER11_LO'; - mmSQ_PERFCOUNTER11_HI :Result:='mmSQ_PERFCOUNTER11_HI'; - mmSQ_PERFCOUNTER12_LO :Result:='mmSQ_PERFCOUNTER12_LO'; - mmSQ_PERFCOUNTER12_HI :Result:='mmSQ_PERFCOUNTER12_HI'; - mmSQ_PERFCOUNTER13_LO :Result:='mmSQ_PERFCOUNTER13_LO'; - mmSQ_PERFCOUNTER13_HI :Result:='mmSQ_PERFCOUNTER13_HI'; - mmSQ_PERFCOUNTER14_LO :Result:='mmSQ_PERFCOUNTER14_LO'; - mmSQ_PERFCOUNTER14_HI :Result:='mmSQ_PERFCOUNTER14_HI'; - mmSQ_PERFCOUNTER15_LO :Result:='mmSQ_PERFCOUNTER15_LO'; - mmSQ_PERFCOUNTER15_HI :Result:='mmSQ_PERFCOUNTER15_HI'; - mmSX_PERFCOUNTER0_LO :Result:='mmSX_PERFCOUNTER0_LO'; - mmSX_PERFCOUNTER0_HI :Result:='mmSX_PERFCOUNTER0_HI'; - mmSX_PERFCOUNTER1_LO :Result:='mmSX_PERFCOUNTER1_LO'; - mmSX_PERFCOUNTER1_HI :Result:='mmSX_PERFCOUNTER1_HI'; - mmSX_PERFCOUNTER2_LO :Result:='mmSX_PERFCOUNTER2_LO'; - mmSX_PERFCOUNTER2_HI :Result:='mmSX_PERFCOUNTER2_HI'; - mmSX_PERFCOUNTER3_LO :Result:='mmSX_PERFCOUNTER3_LO'; - mmSX_PERFCOUNTER3_HI :Result:='mmSX_PERFCOUNTER3_HI'; - mmGDS_PERFCOUNTER0_LO :Result:='mmGDS_PERFCOUNTER0_LO'; - mmGDS_PERFCOUNTER0_HI :Result:='mmGDS_PERFCOUNTER0_HI'; - mmGDS_PERFCOUNTER1_LO :Result:='mmGDS_PERFCOUNTER1_LO'; - mmGDS_PERFCOUNTER1_HI :Result:='mmGDS_PERFCOUNTER1_HI'; - mmGDS_PERFCOUNTER2_LO :Result:='mmGDS_PERFCOUNTER2_LO'; - mmGDS_PERFCOUNTER2_HI :Result:='mmGDS_PERFCOUNTER2_HI'; - mmGDS_PERFCOUNTER3_LO :Result:='mmGDS_PERFCOUNTER3_LO'; - mmGDS_PERFCOUNTER3_HI :Result:='mmGDS_PERFCOUNTER3_HI'; - mmTA_PERFCOUNTER0_LO :Result:='mmTA_PERFCOUNTER0_LO'; - mmTA_PERFCOUNTER0_HI :Result:='mmTA_PERFCOUNTER0_HI'; - mmTA_PERFCOUNTER1_LO :Result:='mmTA_PERFCOUNTER1_LO'; - mmTA_PERFCOUNTER1_HI :Result:='mmTA_PERFCOUNTER1_HI'; - mmTD_PERFCOUNTER0_LO :Result:='mmTD_PERFCOUNTER0_LO'; - mmTD_PERFCOUNTER0_HI :Result:='mmTD_PERFCOUNTER0_HI'; - mmTD_PERFCOUNTER1_LO :Result:='mmTD_PERFCOUNTER1_LO'; - mmTD_PERFCOUNTER1_HI :Result:='mmTD_PERFCOUNTER1_HI'; - mmTCP_PERFCOUNTER0_LO :Result:='mmTCP_PERFCOUNTER0_LO'; - mmTCP_PERFCOUNTER0_HI :Result:='mmTCP_PERFCOUNTER0_HI'; - mmTCP_PERFCOUNTER1_LO :Result:='mmTCP_PERFCOUNTER1_LO'; - mmTCP_PERFCOUNTER1_HI :Result:='mmTCP_PERFCOUNTER1_HI'; - mmTCP_PERFCOUNTER2_LO :Result:='mmTCP_PERFCOUNTER2_LO'; - mmTCP_PERFCOUNTER2_HI :Result:='mmTCP_PERFCOUNTER2_HI'; - mmTCP_PERFCOUNTER3_LO :Result:='mmTCP_PERFCOUNTER3_LO'; - mmTCP_PERFCOUNTER3_HI :Result:='mmTCP_PERFCOUNTER3_HI'; - mmTCC_PERFCOUNTER0_LO :Result:='mmTCC_PERFCOUNTER0_LO'; - mmTCC_PERFCOUNTER0_HI :Result:='mmTCC_PERFCOUNTER0_HI'; - mmTCC_PERFCOUNTER1_LO :Result:='mmTCC_PERFCOUNTER1_LO'; - mmTCC_PERFCOUNTER1_HI :Result:='mmTCC_PERFCOUNTER1_HI'; - mmTCC_PERFCOUNTER2_LO :Result:='mmTCC_PERFCOUNTER2_LO'; - mmTCC_PERFCOUNTER2_HI :Result:='mmTCC_PERFCOUNTER2_HI'; - mmTCC_PERFCOUNTER3_LO :Result:='mmTCC_PERFCOUNTER3_LO'; - mmTCC_PERFCOUNTER3_HI :Result:='mmTCC_PERFCOUNTER3_HI'; - mmTCA_PERFCOUNTER0_LO :Result:='mmTCA_PERFCOUNTER0_LO'; - mmTCA_PERFCOUNTER0_HI :Result:='mmTCA_PERFCOUNTER0_HI'; - mmTCA_PERFCOUNTER1_LO :Result:='mmTCA_PERFCOUNTER1_LO'; - mmTCA_PERFCOUNTER1_HI :Result:='mmTCA_PERFCOUNTER1_HI'; - mmTCA_PERFCOUNTER2_LO :Result:='mmTCA_PERFCOUNTER2_LO'; - mmTCA_PERFCOUNTER2_HI :Result:='mmTCA_PERFCOUNTER2_HI'; - mmTCA_PERFCOUNTER3_LO :Result:='mmTCA_PERFCOUNTER3_LO'; - mmTCA_PERFCOUNTER3_HI :Result:='mmTCA_PERFCOUNTER3_HI'; - mmCB_PERFCOUNTER0_LO :Result:='mmCB_PERFCOUNTER0_LO'; - mmCB_PERFCOUNTER0_HI :Result:='mmCB_PERFCOUNTER0_HI'; - mmCB_PERFCOUNTER1_LO :Result:='mmCB_PERFCOUNTER1_LO'; - mmCB_PERFCOUNTER1_HI :Result:='mmCB_PERFCOUNTER1_HI'; - mmCB_PERFCOUNTER2_LO :Result:='mmCB_PERFCOUNTER2_LO'; - mmCB_PERFCOUNTER2_HI :Result:='mmCB_PERFCOUNTER2_HI'; - mmCB_PERFCOUNTER3_LO :Result:='mmCB_PERFCOUNTER3_LO'; - mmCB_PERFCOUNTER3_HI :Result:='mmCB_PERFCOUNTER3_HI'; - mmDB_PERFCOUNTER0_LO :Result:='mmDB_PERFCOUNTER0_LO'; - mmDB_PERFCOUNTER0_HI :Result:='mmDB_PERFCOUNTER0_HI'; - mmDB_PERFCOUNTER1_LO :Result:='mmDB_PERFCOUNTER1_LO'; - mmDB_PERFCOUNTER1_HI :Result:='mmDB_PERFCOUNTER1_HI'; - mmDB_PERFCOUNTER2_LO :Result:='mmDB_PERFCOUNTER2_LO'; - mmDB_PERFCOUNTER2_HI :Result:='mmDB_PERFCOUNTER2_HI'; - mmDB_PERFCOUNTER3_LO :Result:='mmDB_PERFCOUNTER3_LO'; - mmDB_PERFCOUNTER3_HI :Result:='mmDB_PERFCOUNTER3_HI'; - mmCPG_PERFCOUNTER1_SELECT :Result:='mmCPG_PERFCOUNTER1_SELECT'; - mmCPG_PERFCOUNTER0_SELECT1 :Result:='mmCPG_PERFCOUNTER0_SELECT1'; - mmCPG_PERFCOUNTER0_SELECT :Result:='mmCPG_PERFCOUNTER0_SELECT'; - mmCPC_PERFCOUNTER1_SELECT :Result:='mmCPC_PERFCOUNTER1_SELECT'; - mmCPC_PERFCOUNTER0_SELECT1 :Result:='mmCPC_PERFCOUNTER0_SELECT1'; - mmCPF_PERFCOUNTER1_SELECT :Result:='mmCPF_PERFCOUNTER1_SELECT'; - mmCPF_PERFCOUNTER0_SELECT1 :Result:='mmCPF_PERFCOUNTER0_SELECT1'; - mmCPF_PERFCOUNTER0_SELECT :Result:='mmCPF_PERFCOUNTER0_SELECT'; - mmCP_PERFMON_CNTL :Result:='mmCP_PERFMON_CNTL'; - mmCPC_PERFCOUNTER0_SELECT :Result:='mmCPC_PERFCOUNTER0_SELECT'; - mmCP_DRAW_OBJECT :Result:='mmCP_DRAW_OBJECT'; - mmCP_DRAW_OBJECT_COUNTER :Result:='mmCP_DRAW_OBJECT_COUNTER'; - mmCP_DRAW_WINDOW_MASK_HI :Result:='mmCP_DRAW_WINDOW_MASK_HI'; - mmCP_DRAW_WINDOW_HI :Result:='mmCP_DRAW_WINDOW_HI'; - mmCP_DRAW_WINDOW_LO :Result:='mmCP_DRAW_WINDOW_LO'; - mmCP_DRAW_WINDOW_CNTL :Result:='mmCP_DRAW_WINDOW_CNTL'; - mmGRBM_PERFCOUNTER0_SELECT :Result:='mmGRBM_PERFCOUNTER0_SELECT'; - mmGRBM_PERFCOUNTER1_SELECT :Result:='mmGRBM_PERFCOUNTER1_SELECT'; - mmGRBM_SE0_PERFCOUNTER_SELECT :Result:='mmGRBM_SE0_PERFCOUNTER_SELECT'; - mmGRBM_SE1_PERFCOUNTER_SELECT :Result:='mmGRBM_SE1_PERFCOUNTER_SELECT'; - mmGRBM_SE2_PERFCOUNTER_SELECT :Result:='mmGRBM_SE2_PERFCOUNTER_SELECT'; - mmGRBM_SE3_PERFCOUNTER_SELECT :Result:='mmGRBM_SE3_PERFCOUNTER_SELECT'; - mmWD_PERFCOUNTER0_SELECT :Result:='mmWD_PERFCOUNTER0_SELECT'; - mmWD_PERFCOUNTER1_SELECT :Result:='mmWD_PERFCOUNTER1_SELECT'; - mmWD_PERFCOUNTER2_SELECT :Result:='mmWD_PERFCOUNTER2_SELECT'; - mmWD_PERFCOUNTER3_SELECT :Result:='mmWD_PERFCOUNTER3_SELECT'; - mmIA_PERFCOUNTER0_SELECT :Result:='mmIA_PERFCOUNTER0_SELECT'; - mmIA_PERFCOUNTER1_SELECT :Result:='mmIA_PERFCOUNTER1_SELECT'; - mmIA_PERFCOUNTER2_SELECT :Result:='mmIA_PERFCOUNTER2_SELECT'; - mmIA_PERFCOUNTER3_SELECT :Result:='mmIA_PERFCOUNTER3_SELECT'; - mmIA_PERFCOUNTER0_SELECT1 :Result:='mmIA_PERFCOUNTER0_SELECT1'; - mmVGT_PERFCOUNTER0_SELECT :Result:='mmVGT_PERFCOUNTER0_SELECT'; - mmVGT_PERFCOUNTER1_SELECT :Result:='mmVGT_PERFCOUNTER1_SELECT'; - mmVGT_PERFCOUNTER2_SELECT :Result:='mmVGT_PERFCOUNTER2_SELECT'; - mmVGT_PERFCOUNTER3_SELECT :Result:='mmVGT_PERFCOUNTER3_SELECT'; - mmVGT_PERFCOUNTER0_SELECT1 :Result:='mmVGT_PERFCOUNTER0_SELECT1'; - mmVGT_PERFCOUNTER1_SELECT1 :Result:='mmVGT_PERFCOUNTER1_SELECT1'; - mmVGT_PERFCOUNTER_SEID_MASK :Result:='mmVGT_PERFCOUNTER_SEID_MASK'; - mmPA_SU_PERFCOUNTER0_SELECT :Result:='mmPA_SU_PERFCOUNTER0_SELECT'; - mmPA_SU_PERFCOUNTER0_SELECT1 :Result:='mmPA_SU_PERFCOUNTER0_SELECT1'; - mmPA_SU_PERFCOUNTER1_SELECT :Result:='mmPA_SU_PERFCOUNTER1_SELECT'; - mmPA_SU_PERFCOUNTER1_SELECT1 :Result:='mmPA_SU_PERFCOUNTER1_SELECT1'; - mmPA_SU_PERFCOUNTER2_SELECT :Result:='mmPA_SU_PERFCOUNTER2_SELECT'; - mmPA_SU_PERFCOUNTER3_SELECT :Result:='mmPA_SU_PERFCOUNTER3_SELECT'; - mmPA_SC_PERFCOUNTER0_SELECT :Result:='mmPA_SC_PERFCOUNTER0_SELECT'; - mmPA_SC_PERFCOUNTER0_SELECT1 :Result:='mmPA_SC_PERFCOUNTER0_SELECT1'; - mmPA_SC_PERFCOUNTER1_SELECT :Result:='mmPA_SC_PERFCOUNTER1_SELECT'; - mmPA_SC_PERFCOUNTER2_SELECT :Result:='mmPA_SC_PERFCOUNTER2_SELECT'; - mmPA_SC_PERFCOUNTER3_SELECT :Result:='mmPA_SC_PERFCOUNTER3_SELECT'; - mmPA_SC_PERFCOUNTER4_SELECT :Result:='mmPA_SC_PERFCOUNTER4_SELECT'; - mmPA_SC_PERFCOUNTER5_SELECT :Result:='mmPA_SC_PERFCOUNTER5_SELECT'; - mmPA_SC_PERFCOUNTER6_SELECT :Result:='mmPA_SC_PERFCOUNTER6_SELECT'; - mmPA_SC_PERFCOUNTER7_SELECT :Result:='mmPA_SC_PERFCOUNTER7_SELECT'; - mmSPI_PERFCOUNTER0_SELECT :Result:='mmSPI_PERFCOUNTER0_SELECT'; - mmSPI_PERFCOUNTER1_SELECT :Result:='mmSPI_PERFCOUNTER1_SELECT'; - mmSPI_PERFCOUNTER2_SELECT :Result:='mmSPI_PERFCOUNTER2_SELECT'; - mmSPI_PERFCOUNTER3_SELECT :Result:='mmSPI_PERFCOUNTER3_SELECT'; - mmSPI_PERFCOUNTER0_SELECT1 :Result:='mmSPI_PERFCOUNTER0_SELECT1'; - mmSPI_PERFCOUNTER1_SELECT1 :Result:='mmSPI_PERFCOUNTER1_SELECT1'; - mmSPI_PERFCOUNTER2_SELECT1 :Result:='mmSPI_PERFCOUNTER2_SELECT1'; - mmSPI_PERFCOUNTER3_SELECT1 :Result:='mmSPI_PERFCOUNTER3_SELECT1'; - mmSPI_PERFCOUNTER4_SELECT :Result:='mmSPI_PERFCOUNTER4_SELECT'; - mmSPI_PERFCOUNTER5_SELECT :Result:='mmSPI_PERFCOUNTER5_SELECT'; - mmSPI_PERFCOUNTER_BINS :Result:='mmSPI_PERFCOUNTER_BINS'; - mmSQ_PERFCOUNTER0_SELECT :Result:='mmSQ_PERFCOUNTER0_SELECT'; - mmSQ_PERFCOUNTER1_SELECT :Result:='mmSQ_PERFCOUNTER1_SELECT'; - mmSQ_PERFCOUNTER2_SELECT :Result:='mmSQ_PERFCOUNTER2_SELECT'; - mmSQ_PERFCOUNTER3_SELECT :Result:='mmSQ_PERFCOUNTER3_SELECT'; - mmSQ_PERFCOUNTER4_SELECT :Result:='mmSQ_PERFCOUNTER4_SELECT'; - mmSQ_PERFCOUNTER5_SELECT :Result:='mmSQ_PERFCOUNTER5_SELECT'; - mmSQ_PERFCOUNTER6_SELECT :Result:='mmSQ_PERFCOUNTER6_SELECT'; - mmSQ_PERFCOUNTER7_SELECT :Result:='mmSQ_PERFCOUNTER7_SELECT'; - mmSQ_PERFCOUNTER8_SELECT :Result:='mmSQ_PERFCOUNTER8_SELECT'; - mmSQ_PERFCOUNTER9_SELECT :Result:='mmSQ_PERFCOUNTER9_SELECT'; - mmSQ_PERFCOUNTER10_SELECT :Result:='mmSQ_PERFCOUNTER10_SELECT'; - mmSQ_PERFCOUNTER11_SELECT :Result:='mmSQ_PERFCOUNTER11_SELECT'; - mmSQ_PERFCOUNTER12_SELECT :Result:='mmSQ_PERFCOUNTER12_SELECT'; - mmSQ_PERFCOUNTER13_SELECT :Result:='mmSQ_PERFCOUNTER13_SELECT'; - mmSQ_PERFCOUNTER14_SELECT :Result:='mmSQ_PERFCOUNTER14_SELECT'; - mmSQ_PERFCOUNTER15_SELECT :Result:='mmSQ_PERFCOUNTER15_SELECT'; - mmSQ_PERFCOUNTER_CTRL :Result:='mmSQ_PERFCOUNTER_CTRL'; - mmSQ_PERFCOUNTER_MASK :Result:='mmSQ_PERFCOUNTER_MASK'; - mmSQ_PERFCOUNTER_CTRL2 :Result:='mmSQ_PERFCOUNTER_CTRL2'; - mmSX_PERFCOUNTER0_SELECT :Result:='mmSX_PERFCOUNTER0_SELECT'; - mmSX_PERFCOUNTER1_SELECT :Result:='mmSX_PERFCOUNTER1_SELECT'; - mmSX_PERFCOUNTER2_SELECT :Result:='mmSX_PERFCOUNTER2_SELECT'; - mmSX_PERFCOUNTER3_SELECT :Result:='mmSX_PERFCOUNTER3_SELECT'; - mmSX_PERFCOUNTER0_SELECT1 :Result:='mmSX_PERFCOUNTER0_SELECT1'; - mmSX_PERFCOUNTER1_SELECT1 :Result:='mmSX_PERFCOUNTER1_SELECT1'; - mmGDS_PERFCOUNTER0_SELECT :Result:='mmGDS_PERFCOUNTER0_SELECT'; - mmGDS_PERFCOUNTER1_SELECT :Result:='mmGDS_PERFCOUNTER1_SELECT'; - mmGDS_PERFCOUNTER2_SELECT :Result:='mmGDS_PERFCOUNTER2_SELECT'; - mmGDS_PERFCOUNTER3_SELECT :Result:='mmGDS_PERFCOUNTER3_SELECT'; - mmGDS_PERFCOUNTER0_SELECT1 :Result:='mmGDS_PERFCOUNTER0_SELECT1'; - mmTA_PERFCOUNTER0_SELECT :Result:='mmTA_PERFCOUNTER0_SELECT'; - mmTA_PERFCOUNTER0_SELECT1 :Result:='mmTA_PERFCOUNTER0_SELECT1'; - mmTA_PERFCOUNTER1_SELECT :Result:='mmTA_PERFCOUNTER1_SELECT'; - mmTD_PERFCOUNTER0_SELECT :Result:='mmTD_PERFCOUNTER0_SELECT'; - mmTD_PERFCOUNTER0_SELECT1 :Result:='mmTD_PERFCOUNTER0_SELECT1'; - mmTD_PERFCOUNTER1_SELECT :Result:='mmTD_PERFCOUNTER1_SELECT'; - mmTCP_PERFCOUNTER0_SELECT :Result:='mmTCP_PERFCOUNTER0_SELECT'; - mmTCP_PERFCOUNTER0_SELECT1 :Result:='mmTCP_PERFCOUNTER0_SELECT1'; - mmTCP_PERFCOUNTER1_SELECT :Result:='mmTCP_PERFCOUNTER1_SELECT'; - mmTCP_PERFCOUNTER1_SELECT1 :Result:='mmTCP_PERFCOUNTER1_SELECT1'; - mmTCP_PERFCOUNTER2_SELECT :Result:='mmTCP_PERFCOUNTER2_SELECT'; - mmTCP_PERFCOUNTER3_SELECT :Result:='mmTCP_PERFCOUNTER3_SELECT'; - mmTCC_PERFCOUNTER0_SELECT :Result:='mmTCC_PERFCOUNTER0_SELECT'; - mmTCC_PERFCOUNTER0_SELECT1 :Result:='mmTCC_PERFCOUNTER0_SELECT1'; - mmTCC_PERFCOUNTER1_SELECT :Result:='mmTCC_PERFCOUNTER1_SELECT'; - mmTCC_PERFCOUNTER1_SELECT1 :Result:='mmTCC_PERFCOUNTER1_SELECT1'; - mmTCC_PERFCOUNTER2_SELECT :Result:='mmTCC_PERFCOUNTER2_SELECT'; - mmTCC_PERFCOUNTER3_SELECT :Result:='mmTCC_PERFCOUNTER3_SELECT'; - mmTCA_PERFCOUNTER0_SELECT :Result:='mmTCA_PERFCOUNTER0_SELECT'; - mmTCA_PERFCOUNTER0_SELECT1 :Result:='mmTCA_PERFCOUNTER0_SELECT1'; - mmTCA_PERFCOUNTER1_SELECT :Result:='mmTCA_PERFCOUNTER1_SELECT'; - mmTCA_PERFCOUNTER1_SELECT1 :Result:='mmTCA_PERFCOUNTER1_SELECT1'; - mmTCA_PERFCOUNTER2_SELECT :Result:='mmTCA_PERFCOUNTER2_SELECT'; - mmTCA_PERFCOUNTER3_SELECT :Result:='mmTCA_PERFCOUNTER3_SELECT'; - mmCB_PERFCOUNTER_FILTER :Result:='mmCB_PERFCOUNTER_FILTER'; - mmCB_PERFCOUNTER0_SELECT :Result:='mmCB_PERFCOUNTER0_SELECT'; - mmCB_PERFCOUNTER0_SELECT1 :Result:='mmCB_PERFCOUNTER0_SELECT1'; - mmCB_PERFCOUNTER1_SELECT :Result:='mmCB_PERFCOUNTER1_SELECT'; - mmCB_PERFCOUNTER2_SELECT :Result:='mmCB_PERFCOUNTER2_SELECT'; - mmCB_PERFCOUNTER3_SELECT :Result:='mmCB_PERFCOUNTER3_SELECT'; - mmDB_PERFCOUNTER0_SELECT :Result:='mmDB_PERFCOUNTER0_SELECT'; - mmDB_PERFCOUNTER0_SELECT1 :Result:='mmDB_PERFCOUNTER0_SELECT1'; - mmDB_PERFCOUNTER1_SELECT :Result:='mmDB_PERFCOUNTER1_SELECT'; - mmDB_PERFCOUNTER1_SELECT1 :Result:='mmDB_PERFCOUNTER1_SELECT1'; - mmDB_PERFCOUNTER2_SELECT :Result:='mmDB_PERFCOUNTER2_SELECT'; - mmDB_PERFCOUNTER3_SELECT :Result:='mmDB_PERFCOUNTER3_SELECT'; + mmGRBM_CNTL :Result:='mmGRBM_CNTL'; + mmGRBM_SKEW_CNTL :Result:='mmGRBM_SKEW_CNTL'; + mmGRBM_STATUS2 :Result:='mmGRBM_STATUS2'; + mmGRBM_PWR_CNTL :Result:='mmGRBM_PWR_CNTL'; + mmGRBM_STATUS :Result:='mmGRBM_STATUS'; + mmGRBM_STATUS_SE0 :Result:='mmGRBM_STATUS_SE0'; + mmGRBM_STATUS_SE1 :Result:='mmGRBM_STATUS_SE1'; + mmGRBM_SOFT_RESET :Result:='mmGRBM_SOFT_RESET'; + mmGRBM_DEBUG_CNTL :Result:='mmGRBM_DEBUG_CNTL'; + mmGRBM_DEBUG_DATA :Result:='mmGRBM_DEBUG_DATA'; + mmGRBM_GFX_CLKEN_CNTL :Result:='mmGRBM_GFX_CLKEN_CNTL'; + mmGRBM_WAIT_IDLE_CLOCKS :Result:='mmGRBM_WAIT_IDLE_CLOCKS'; + mmGRBM_STATUS_SE2 :Result:='mmGRBM_STATUS_SE2'; + mmGRBM_STATUS_SE3 :Result:='mmGRBM_STATUS_SE3'; + mmGRBM_DEBUG :Result:='mmGRBM_DEBUG'; + mmGRBM_DEBUG_SNAPSHOT :Result:='mmGRBM_DEBUG_SNAPSHOT'; + mmGRBM_READ_ERROR :Result:='mmGRBM_READ_ERROR'; + mmGRBM_READ_ERROR2 :Result:='mmGRBM_READ_ERROR2'; + mmGRBM_INT_CNTL :Result:='mmGRBM_INT_CNTL'; + mmGRBM_TRAP_OP :Result:='mmGRBM_TRAP_OP'; + mmGRBM_TRAP_ADDR :Result:='mmGRBM_TRAP_ADDR'; + mmGRBM_TRAP_ADDR_MSK :Result:='mmGRBM_TRAP_ADDR_MSK'; + mmGRBM_TRAP_WD :Result:='mmGRBM_TRAP_WD'; + mmGRBM_TRAP_WD_MSK :Result:='mmGRBM_TRAP_WD_MSK'; + mmGRBM_DSM_BYPASS :Result:='mmGRBM_DSM_BYPASS'; + mmGRBM_WRITE_ERROR :Result:='mmGRBM_WRITE_ERROR'; + mmDEBUG_INDEX :Result:='mmDEBUG_INDEX'; + mmDEBUG_DATA :Result:='mmDEBUG_DATA'; + mmGRBM_NOWHERE :Result:='mmGRBM_NOWHERE'; + mmGRBM_SCRATCH_REG0 :Result:='mmGRBM_SCRATCH_REG0'; + mmGRBM_SCRATCH_REG1 :Result:='mmGRBM_SCRATCH_REG1'; + mmGRBM_SCRATCH_REG2 :Result:='mmGRBM_SCRATCH_REG2'; + mmGRBM_SCRATCH_REG3 :Result:='mmGRBM_SCRATCH_REG3'; + mmGRBM_SCRATCH_REG4 :Result:='mmGRBM_SCRATCH_REG4'; + mmGRBM_SCRATCH_REG5 :Result:='mmGRBM_SCRATCH_REG5'; + mmGRBM_SCRATCH_REG6 :Result:='mmGRBM_SCRATCH_REG6'; + mmGRBM_SCRATCH_REG7 :Result:='mmGRBM_SCRATCH_REG7'; + mmCP_CPC_STATUS :Result:='mmCP_CPC_STATUS'; + mmCP_CPC_BUSY_STAT :Result:='mmCP_CPC_BUSY_STAT'; + mmCP_CPC_STALLED_STAT1 :Result:='mmCP_CPC_STALLED_STAT1'; + mmCP_CPF_STATUS :Result:='mmCP_CPF_STATUS'; + mmCP_CPF_BUSY_STAT :Result:='mmCP_CPF_BUSY_STAT'; + mmCP_CPF_STALLED_STAT1 :Result:='mmCP_CPF_STALLED_STAT1'; + mmCP_CPC_GRBM_FREE_COUNT :Result:='mmCP_CPC_GRBM_FREE_COUNT'; + mmCP_MEC_CNTL :Result:='mmCP_MEC_CNTL'; + mmCP_MEC_ME1_HEADER_DUMP :Result:='mmCP_MEC_ME1_HEADER_DUMP'; + mmCP_MEC_ME2_HEADER_DUMP :Result:='mmCP_MEC_ME2_HEADER_DUMP'; + mmCP_CPC_SCRATCH_INDEX :Result:='mmCP_CPC_SCRATCH_INDEX'; + mmCP_CPC_SCRATCH_DATA :Result:='mmCP_CPC_SCRATCH_DATA'; + mmCP_CPC_HALT_HYST_COUNT :Result:='mmCP_CPC_HALT_HYST_COUNT'; + mmCP_PRT_LOD_STATS_CNTL0 :Result:='mmCP_PRT_LOD_STATS_CNTL0'; + mmCP_PRT_LOD_STATS_CNTL1 :Result:='mmCP_PRT_LOD_STATS_CNTL1'; + mmCP_PRT_LOD_STATS_CNTL2 :Result:='mmCP_PRT_LOD_STATS_CNTL2'; + mmCP_CE_COMPARE_COUNT :Result:='mmCP_CE_COMPARE_COUNT'; + mmCP_CE_DE_COUNT :Result:='mmCP_CE_DE_COUNT'; + mmCP_DE_CE_COUNT :Result:='mmCP_DE_CE_COUNT'; + mmCP_DE_LAST_INVAL_COUNT :Result:='mmCP_DE_LAST_INVAL_COUNT'; + mmCP_DE_DE_COUNT :Result:='mmCP_DE_DE_COUNT'; + mmCP_STALLED_STAT3 :Result:='mmCP_STALLED_STAT3'; + mmCP_STALLED_STAT1 :Result:='mmCP_STALLED_STAT1'; + mmCP_STALLED_STAT2 :Result:='mmCP_STALLED_STAT2'; + mmCP_BUSY_STAT :Result:='mmCP_BUSY_STAT'; + mmCP_STAT :Result:='mmCP_STAT'; + mmCP_ME_HEADER_DUMP :Result:='mmCP_ME_HEADER_DUMP'; + mmCP_PFP_HEADER_DUMP :Result:='mmCP_PFP_HEADER_DUMP'; + mmCP_GRBM_FREE_COUNT :Result:='mmCP_GRBM_FREE_COUNT'; + mmCP_CE_HEADER_DUMP :Result:='mmCP_CE_HEADER_DUMP'; + mmCP_CSF_STAT :Result:='mmCP_CSF_STAT'; + mmCP_CSF_CNTL :Result:='mmCP_CSF_CNTL'; + mmCP_ME_CNTL :Result:='mmCP_ME_CNTL'; + mmCP_CNTX_STAT :Result:='mmCP_CNTX_STAT'; + mmCP_ME_PREEMPTION :Result:='mmCP_ME_PREEMPTION'; + mmCP_ROQ_THRESHOLDS :Result:='mmCP_ROQ_THRESHOLDS'; + mmCP_MEQ_STQ_THRESHOLD :Result:='mmCP_MEQ_STQ_THRESHOLD'; + mmCP_RB2_RPTR :Result:='mmCP_RB2_RPTR'; + mmCP_RB1_RPTR :Result:='mmCP_RB1_RPTR'; + mmCP_RB0_RPTR :Result:='mmCP_RB0_RPTR'; + mmCP_RB_WPTR_DELAY :Result:='mmCP_RB_WPTR_DELAY'; + mmCP_RB_WPTR_POLL_CNTL :Result:='mmCP_RB_WPTR_POLL_CNTL'; + mmCP_ROQ1_THRESHOLDS :Result:='mmCP_ROQ1_THRESHOLDS'; + mmCP_ROQ2_THRESHOLDS :Result:='mmCP_ROQ2_THRESHOLDS'; + mmCP_STQ_THRESHOLDS :Result:='mmCP_STQ_THRESHOLDS'; + mmCP_QUEUE_THRESHOLDS :Result:='mmCP_QUEUE_THRESHOLDS'; + mmCP_MEQ_THRESHOLDS :Result:='mmCP_MEQ_THRESHOLDS'; + mmCP_ROQ_AVAIL :Result:='mmCP_ROQ_AVAIL'; + mmCP_STQ_AVAIL :Result:='mmCP_STQ_AVAIL'; + mmCP_ROQ2_AVAIL :Result:='mmCP_ROQ2_AVAIL'; + mmCP_MEQ_AVAIL :Result:='mmCP_MEQ_AVAIL'; + mmCP_CMD_INDEX :Result:='mmCP_CMD_INDEX'; + mmCP_CMD_DATA :Result:='mmCP_CMD_DATA'; + mmCP_ROQ_RB_STAT :Result:='mmCP_ROQ_RB_STAT'; + mmCP_ROQ_IB1_STAT :Result:='mmCP_ROQ_IB1_STAT'; + mmCP_ROQ_IB2_STAT :Result:='mmCP_ROQ_IB2_STAT'; + mmCP_STQ_STAT :Result:='mmCP_STQ_STAT'; + mmCP_STQ_WR_STAT :Result:='mmCP_STQ_WR_STAT'; + mmCP_MEQ_STAT :Result:='mmCP_MEQ_STAT'; + mmCP_CEQ1_AVAIL :Result:='mmCP_CEQ1_AVAIL'; + mmCP_CEQ2_AVAIL :Result:='mmCP_CEQ2_AVAIL'; + mmCP_CE_ROQ_RB_STAT :Result:='mmCP_CE_ROQ_RB_STAT'; + mmCP_CE_ROQ_IB1_STAT :Result:='mmCP_CE_ROQ_IB1_STAT'; + mmCP_CE_ROQ_IB2_STAT :Result:='mmCP_CE_ROQ_IB2_STAT'; + mmCP_INT_STAT_DEBUG :Result:='mmCP_INT_STAT_DEBUG'; + mmCP_PERFCOUNTER_SELECT :Result:='mmCP_PERFCOUNTER_SELECT'; + mmCP_PERFCOUNTER_LO :Result:='mmCP_PERFCOUNTER_LO'; + mmCP_PERFCOUNTER_HI :Result:='mmCP_PERFCOUNTER_HI'; + mmVGT_VTX_VECT_EJECT_REG :Result:='mmVGT_VTX_VECT_EJECT_REG'; + mmVGT_DMA_DATA_FIFO_DEPTH :Result:='mmVGT_DMA_DATA_FIFO_DEPTH'; + mmVGT_DMA_REQ_FIFO_DEPTH :Result:='mmVGT_DMA_REQ_FIFO_DEPTH'; + mmVGT_DRAW_INIT_FIFO_DEPTH :Result:='mmVGT_DRAW_INIT_FIFO_DEPTH'; + mmVGT_LAST_COPY_STATE :Result:='mmVGT_LAST_COPY_STATE'; + mmVGT_CACHE_INVALIDATION :Result:='mmVGT_CACHE_INVALIDATION'; + mmVGT_RESET_DEBUG :Result:='mmVGT_RESET_DEBUG'; + mmVGT_STRMOUT_DELAY :Result:='mmVGT_STRMOUT_DELAY'; + mmVGT_FIFO_DEPTHS :Result:='mmVGT_FIFO_DEPTHS'; + mmVGT_GS_VERTEX_REUSE :Result:='mmVGT_GS_VERTEX_REUSE'; + mmVGT_MC_LAT_CNTL :Result:='mmVGT_MC_LAT_CNTL'; + mmIA_CNTL_STATUS :Result:='mmIA_CNTL_STATUS'; + mmVGT_DEBUG_CNTL :Result:='mmVGT_DEBUG_CNTL'; + mmVGT_DEBUG_DATA :Result:='mmVGT_DEBUG_DATA'; + mmIA_DEBUG_CNTL :Result:='mmIA_DEBUG_CNTL'; + mmIA_DEBUG_DATA :Result:='mmIA_DEBUG_DATA'; + mmVGT_CNTL_STATUS :Result:='mmVGT_CNTL_STATUS'; + mmWD_DEBUG_CNTL :Result:='mmWD_DEBUG_CNTL'; + mmWD_DEBUG_DATA :Result:='mmWD_DEBUG_DATA'; + mmWD_CNTL_STATUS :Result:='mmWD_CNTL_STATUS'; + mmCC_GC_PRIM_CONFIG :Result:='mmCC_GC_PRIM_CONFIG'; + mmGC_USER_PRIM_CONFIG :Result:='mmGC_USER_PRIM_CONFIG'; + mmWD_QOS :Result:='mmWD_QOS'; + mmCGTT_VGT_CLK_CTRL :Result:='mmCGTT_VGT_CLK_CTRL'; + mmCGTT_IA_CLK_CTRL :Result:='mmCGTT_IA_CLK_CTRL'; + mmVGT_SYS_CONFIG :Result:='mmVGT_SYS_CONFIG'; + mmVGT_VS_MAX_WAVE_ID :Result:='mmVGT_VS_MAX_WAVE_ID'; + mmGFX_PIPE_CONTROL :Result:='mmGFX_PIPE_CONTROL'; + mmCC_GC_SHADER_ARRAY_CONFIG :Result:='mmCC_GC_SHADER_ARRAY_CONFIG'; + mmGC_USER_SHADER_ARRAY_CONFIG :Result:='mmGC_USER_SHADER_ARRAY_CONFIG'; + mmVGT_DMA_PRIMITIVE_TYPE :Result:='mmVGT_DMA_PRIMITIVE_TYPE'; + mmVGT_DMA_CONTROL :Result:='mmVGT_DMA_CONTROL'; + mmVGT_DMA_LS_HS_CONFIG :Result:='mmVGT_DMA_LS_HS_CONFIG'; + mmPA_SU_DEBUG_CNTL :Result:='mmPA_SU_DEBUG_CNTL'; + mmPA_SU_DEBUG_DATA :Result:='mmPA_SU_DEBUG_DATA'; + mmPA_CL_CNTL_STATUS :Result:='mmPA_CL_CNTL_STATUS'; + mmPA_CL_ENHANCE :Result:='mmPA_CL_ENHANCE'; + mmPA_CL_RESET_DEBUG :Result:='mmPA_CL_RESET_DEBUG'; + mmPA_SU_CNTL_STATUS :Result:='mmPA_SU_CNTL_STATUS'; + mmPA_SC_FIFO_DEPTH_CNTL :Result:='mmPA_SC_FIFO_DEPTH_CNTL'; + mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK'; + mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK'; + mmPA_SC_TRAP_SCREEN_HV_LOCK :Result:='mmPA_SC_TRAP_SCREEN_HV_LOCK'; + mmPA_SC_FORCE_EOV_MAX_CNTS :Result:='mmPA_SC_FORCE_EOV_MAX_CNTS'; + mmCGTT_SC_CLK_CTRL :Result:='mmCGTT_SC_CLK_CTRL'; + mmPA_SC_FIFO_SIZE :Result:='mmPA_SC_FIFO_SIZE'; + mmPA_SC_IF_FIFO_SIZE :Result:='mmPA_SC_IF_FIFO_SIZE'; + mmPA_SC_DEBUG_CNTL :Result:='mmPA_SC_DEBUG_CNTL'; + mmPA_SC_DEBUG_DATA :Result:='mmPA_SC_DEBUG_DATA'; + mmPA_SC_ENHANCE :Result:='mmPA_SC_ENHANCE'; + mmSQ_CONFIG :Result:='mmSQ_CONFIG'; + mmSQC_CONFIG :Result:='mmSQC_CONFIG'; + mmSQ_RANDOM_WAVE_PRI :Result:='mmSQ_RANDOM_WAVE_PRI'; + mmSQ_REG_CREDITS :Result:='mmSQ_REG_CREDITS'; + mmSQ_FIFO_SIZES :Result:='mmSQ_FIFO_SIZES'; + mmSQ_DSM_CNTL :Result:='mmSQ_DSM_CNTL'; + mmCC_SQC_BANK_DISABLE :Result:='mmCC_SQC_BANK_DISABLE'; + mmUSER_SQC_BANK_DISABLE :Result:='mmUSER_SQC_BANK_DISABLE'; + mmSQ_DEBUG_STS_GLOBAL :Result:='mmSQ_DEBUG_STS_GLOBAL'; + mmSH_MEM_BASES :Result:='mmSH_MEM_BASES'; + mmSH_MEM_APE1_BASE :Result:='mmSH_MEM_APE1_BASE'; + mmSH_MEM_APE1_LIMIT :Result:='mmSH_MEM_APE1_LIMIT'; + mmSH_MEM_CONFIG :Result:='mmSH_MEM_CONFIG'; + mmSQC_DSM_CNTL :Result:='mmSQC_DSM_CNTL'; + mmSQ_DEBUG_STS_GLOBAL2 :Result:='mmSQ_DEBUG_STS_GLOBAL2'; + mmSQ_DEBUG_STS_GLOBAL3 :Result:='mmSQ_DEBUG_STS_GLOBAL3'; + mmCC_GC_SHADER_RATE_CONFIG :Result:='mmCC_GC_SHADER_RATE_CONFIG'; + mmGC_USER_SHADER_RATE_CONFIG :Result:='mmGC_USER_SHADER_RATE_CONFIG'; + mmSQ_INTERRUPT_AUTO_MASK :Result:='mmSQ_INTERRUPT_AUTO_MASK'; + mmSQ_INTERRUPT_MSG_CTRL :Result:='mmSQ_INTERRUPT_MSG_CTRL'; + mmSQ_ALU_CLK_CTRL :Result:='mmSQ_ALU_CLK_CTRL'; + mmSQ_TEX_CLK_CTRL :Result:='mmSQ_TEX_CLK_CTRL'; + mmCGTT_SQ_CLK_CTRL :Result:='mmCGTT_SQ_CLK_CTRL'; + mmCGTT_SQG_CLK_CTRL :Result:='mmCGTT_SQG_CLK_CTRL'; + mmSQ_REG_TIMESTAMP :Result:='mmSQ_REG_TIMESTAMP'; + mmSQ_CMD_TIMESTAMP :Result:='mmSQ_CMD_TIMESTAMP'; + mmSQ_IND_INDEX :Result:='mmSQ_IND_INDEX'; + mmSQ_IND_DATA :Result:='mmSQ_IND_DATA'; + mmSQ_CMD :Result:='mmSQ_CMD'; + mmSQ_TIME_HI :Result:='mmSQ_TIME_HI'; + mmSQ_TIME_LO :Result:='mmSQ_TIME_LO'; + mmSQ_DS_0 :Result:='mmSQ_DS_0'; + mmSQ_THREAD_TRACE_CNTR :Result:='mmSQ_THREAD_TRACE_CNTR'; + mmSQ_POWER_THROTTLE :Result:='mmSQ_POWER_THROTTLE'; + mmSQ_POWER_THROTTLE2 :Result:='mmSQ_POWER_THROTTLE2'; + mmSQ_LB_CTR_CTRL :Result:='mmSQ_LB_CTR_CTRL'; + mmSQ_LB_DATA_ALU_CYCLES :Result:='mmSQ_LB_DATA_ALU_CYCLES'; + mmSQ_LB_DATA_TEX_CYCLES :Result:='mmSQ_LB_DATA_TEX_CYCLES'; + mmSQ_LB_DATA_ALU_STALLS :Result:='mmSQ_LB_DATA_ALU_STALLS'; + mmSQ_LB_DATA_TEX_STALLS :Result:='mmSQ_LB_DATA_TEX_STALLS'; + mmSQC_EDC_CNT :Result:='mmSQC_EDC_CNT'; + mmSQ_EDC_SEC_CNT :Result:='mmSQ_EDC_SEC_CNT'; + mmSQ_EDC_DED_CNT :Result:='mmSQ_EDC_DED_CNT'; + mmSQ_EDC_INFO :Result:='mmSQ_EDC_INFO'; + mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 :Result:='mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2'; + mmSQ_WREXEC_EXEC_HI :Result:='mmSQ_WREXEC_EXEC_HI'; + mmSQC_GATCL1_CNTL :Result:='mmSQC_GATCL1_CNTL'; + mmSQC_ATC_EDC_GATCL1_CNT :Result:='mmSQC_ATC_EDC_GATCL1_CNT'; + mmSQ_BUF_RSRC_WORD0 :Result:='mmSQ_BUF_RSRC_WORD0'; + mmSQ_BUF_RSRC_WORD1 :Result:='mmSQ_BUF_RSRC_WORD1'; + mmSQ_BUF_RSRC_WORD2 :Result:='mmSQ_BUF_RSRC_WORD2'; + mmSQ_BUF_RSRC_WORD3 :Result:='mmSQ_BUF_RSRC_WORD3'; + mmSQ_IMG_RSRC_WORD0 :Result:='mmSQ_IMG_RSRC_WORD0'; + mmSQ_IMG_RSRC_WORD1 :Result:='mmSQ_IMG_RSRC_WORD1'; + mmSQ_IMG_RSRC_WORD2 :Result:='mmSQ_IMG_RSRC_WORD2'; + mmSQ_IMG_RSRC_WORD3 :Result:='mmSQ_IMG_RSRC_WORD3'; + mmSQ_IMG_RSRC_WORD4 :Result:='mmSQ_IMG_RSRC_WORD4'; + mmSQ_IMG_RSRC_WORD5 :Result:='mmSQ_IMG_RSRC_WORD5'; + mmSQ_IMG_RSRC_WORD6 :Result:='mmSQ_IMG_RSRC_WORD6'; + mmSQ_IMG_RSRC_WORD7 :Result:='mmSQ_IMG_RSRC_WORD7'; + mmSQ_IMG_SAMP_WORD0 :Result:='mmSQ_IMG_SAMP_WORD0'; + mmSQ_IMG_SAMP_WORD1 :Result:='mmSQ_IMG_SAMP_WORD1'; + mmSQ_IMG_SAMP_WORD2 :Result:='mmSQ_IMG_SAMP_WORD2'; + mmSQ_IMG_SAMP_WORD3 :Result:='mmSQ_IMG_SAMP_WORD3'; + mmSQ_FLAT_SCRATCH_WORD0 :Result:='mmSQ_FLAT_SCRATCH_WORD0'; + mmSQ_FLAT_SCRATCH_WORD1 :Result:='mmSQ_FLAT_SCRATCH_WORD1'; + mmSQ_M0_GPR_IDX_WORD :Result:='mmSQ_M0_GPR_IDX_WORD'; + mmCGTT_SX_CLK_CTRL0 :Result:='mmCGTT_SX_CLK_CTRL0'; + mmCGTT_SX_CLK_CTRL1 :Result:='mmCGTT_SX_CLK_CTRL1'; + mmCGTT_SX_CLK_CTRL2 :Result:='mmCGTT_SX_CLK_CTRL2'; + mmCGTT_SX_CLK_CTRL3 :Result:='mmCGTT_SX_CLK_CTRL3'; + mmCGTT_SX_CLK_CTRL4 :Result:='mmCGTT_SX_CLK_CTRL4'; + mmSX_DEBUG_BUSY :Result:='mmSX_DEBUG_BUSY'; + mmSX_DEBUG_BUSY_2 :Result:='mmSX_DEBUG_BUSY_2'; + mmSX_DEBUG_BUSY_3 :Result:='mmSX_DEBUG_BUSY_3'; + mmSX_DEBUG_BUSY_4 :Result:='mmSX_DEBUG_BUSY_4'; + mmSX_DEBUG_1 :Result:='mmSX_DEBUG_1'; + mmSPI_PS_MAX_WAVE_ID :Result:='mmSPI_PS_MAX_WAVE_ID'; + mmSPI_START_PHASE :Result:='mmSPI_START_PHASE'; + mmSPI_GFX_CNTL :Result:='mmSPI_GFX_CNTL'; + mmSPI_CONFIG_CNTL :Result:='mmSPI_CONFIG_CNTL'; + mmSPI_DEBUG_CNTL :Result:='mmSPI_DEBUG_CNTL'; + mmSPI_DEBUG_READ :Result:='mmSPI_DEBUG_READ'; + mmSPI_DSM_CNTL :Result:='mmSPI_DSM_CNTL'; + mmSPI_EDC_CNT :Result:='mmSPI_EDC_CNT'; + mmSPI_CONFIG_CNTL_1 :Result:='mmSPI_CONFIG_CNTL_1'; + mmSPI_DEBUG_BUSY :Result:='mmSPI_DEBUG_BUSY'; + mmSPI_CONFIG_CNTL_2 :Result:='mmSPI_CONFIG_CNTL_2'; + mmCGTS_TCC_DISABLE :Result:='mmCGTS_TCC_DISABLE'; + mmCGTS_USER_TCC_DISABLE :Result:='mmCGTS_USER_TCC_DISABLE'; + mmCGTS_SM_CTRL_REG :Result:='mmCGTS_SM_CTRL_REG'; + mmCGTS_RD_CTRL_REG :Result:='mmCGTS_RD_CTRL_REG'; + mmCGTS_RD_REG :Result:='mmCGTS_RD_REG'; + mmCGTT_PC_CLK_CTRL :Result:='mmCGTT_PC_CLK_CTRL'; + mmCGTT_BCI_CLK_CTRL :Result:='mmCGTT_BCI_CLK_CTRL'; + mmSPI_WF_LIFETIME_CNTL :Result:='mmSPI_WF_LIFETIME_CNTL'; + mmSPI_WF_LIFETIME_LIMIT_0 :Result:='mmSPI_WF_LIFETIME_LIMIT_0'; + mmSPI_WF_LIFETIME_LIMIT_1 :Result:='mmSPI_WF_LIFETIME_LIMIT_1'; + mmSPI_WF_LIFETIME_LIMIT_2 :Result:='mmSPI_WF_LIFETIME_LIMIT_2'; + mmSPI_WF_LIFETIME_LIMIT_3 :Result:='mmSPI_WF_LIFETIME_LIMIT_3'; + mmSPI_WF_LIFETIME_LIMIT_4 :Result:='mmSPI_WF_LIFETIME_LIMIT_4'; + mmSPI_WF_LIFETIME_LIMIT_5 :Result:='mmSPI_WF_LIFETIME_LIMIT_5'; + mmSPI_WF_LIFETIME_LIMIT_6 :Result:='mmSPI_WF_LIFETIME_LIMIT_6'; + mmSPI_WF_LIFETIME_LIMIT_7 :Result:='mmSPI_WF_LIFETIME_LIMIT_7'; + mmSPI_WF_LIFETIME_LIMIT_8 :Result:='mmSPI_WF_LIFETIME_LIMIT_8'; + mmSPI_WF_LIFETIME_LIMIT_9 :Result:='mmSPI_WF_LIFETIME_LIMIT_9'; + mmSPI_WF_LIFETIME_STATUS_0 :Result:='mmSPI_WF_LIFETIME_STATUS_0'; + mmSPI_WF_LIFETIME_STATUS_1 :Result:='mmSPI_WF_LIFETIME_STATUS_1'; + mmSPI_WF_LIFETIME_STATUS_2 :Result:='mmSPI_WF_LIFETIME_STATUS_2'; + mmSPI_WF_LIFETIME_STATUS_3 :Result:='mmSPI_WF_LIFETIME_STATUS_3'; + mmSPI_WF_LIFETIME_STATUS_4 :Result:='mmSPI_WF_LIFETIME_STATUS_4'; + mmSPI_WF_LIFETIME_STATUS_5 :Result:='mmSPI_WF_LIFETIME_STATUS_5'; + mmSPI_WF_LIFETIME_STATUS_6 :Result:='mmSPI_WF_LIFETIME_STATUS_6'; + mmSPI_WF_LIFETIME_STATUS_7 :Result:='mmSPI_WF_LIFETIME_STATUS_7'; + mmSPI_WF_LIFETIME_STATUS_8 :Result:='mmSPI_WF_LIFETIME_STATUS_8'; + mmSPI_WF_LIFETIME_STATUS_9 :Result:='mmSPI_WF_LIFETIME_STATUS_9'; + mmSPI_WF_LIFETIME_STATUS_10 :Result:='mmSPI_WF_LIFETIME_STATUS_10'; + mmSPI_WF_LIFETIME_STATUS_11 :Result:='mmSPI_WF_LIFETIME_STATUS_11'; + mmSPI_WF_LIFETIME_STATUS_12 :Result:='mmSPI_WF_LIFETIME_STATUS_12'; + mmSPI_WF_LIFETIME_STATUS_13 :Result:='mmSPI_WF_LIFETIME_STATUS_13'; + mmSPI_WF_LIFETIME_STATUS_14 :Result:='mmSPI_WF_LIFETIME_STATUS_14'; + mmSPI_WF_LIFETIME_STATUS_15 :Result:='mmSPI_WF_LIFETIME_STATUS_15'; + mmSPI_WF_LIFETIME_STATUS_16 :Result:='mmSPI_WF_LIFETIME_STATUS_16'; + mmSPI_WF_LIFETIME_STATUS_17 :Result:='mmSPI_WF_LIFETIME_STATUS_17'; + mmSPI_WF_LIFETIME_STATUS_18 :Result:='mmSPI_WF_LIFETIME_STATUS_18'; + mmSPI_WF_LIFETIME_STATUS_19 :Result:='mmSPI_WF_LIFETIME_STATUS_19'; + mmSPI_WF_LIFETIME_STATUS_20 :Result:='mmSPI_WF_LIFETIME_STATUS_20'; + mmSPI_WF_LIFETIME_DEBUG :Result:='mmSPI_WF_LIFETIME_DEBUG'; + mmSPI_SLAVE_DEBUG_BUSY :Result:='mmSPI_SLAVE_DEBUG_BUSY'; + mmSPI_LB_CTR_CTRL :Result:='mmSPI_LB_CTR_CTRL'; + mmSPI_LB_CU_MASK :Result:='mmSPI_LB_CU_MASK'; + mmSPI_LB_DATA_REG :Result:='mmSPI_LB_DATA_REG'; + mmSPI_PG_ENABLE_STATIC_CU_MASK :Result:='mmSPI_PG_ENABLE_STATIC_CU_MASK'; + mmSPI_GDS_CREDITS :Result:='mmSPI_GDS_CREDITS'; + mmSPI_SX_EXPORT_BUFFER_SIZES :Result:='mmSPI_SX_EXPORT_BUFFER_SIZES'; + mmSPI_SX_SCOREBOARD_BUFFER_SIZES :Result:='mmSPI_SX_SCOREBOARD_BUFFER_SIZES'; + mmSPI_CSQ_WF_ACTIVE_STATUS :Result:='mmSPI_CSQ_WF_ACTIVE_STATUS'; + mmSPI_CSQ_WF_ACTIVE_COUNT_0 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_0'; + mmSPI_CSQ_WF_ACTIVE_COUNT_1 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_1'; + mmSPI_CSQ_WF_ACTIVE_COUNT_2 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_2'; + mmSPI_CSQ_WF_ACTIVE_COUNT_3 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_3'; + mmSPI_CSQ_WF_ACTIVE_COUNT_4 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_4'; + mmSPI_CSQ_WF_ACTIVE_COUNT_5 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_5'; + mmSPI_CSQ_WF_ACTIVE_COUNT_6 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_6'; + mmSPI_CSQ_WF_ACTIVE_COUNT_7 :Result:='mmSPI_CSQ_WF_ACTIVE_COUNT_7'; + mmBCI_DEBUG_READ :Result:='mmBCI_DEBUG_READ'; + mmSPI_P0_TRAP_SCREEN_PSBA_LO :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_LO'; + mmSPI_P0_TRAP_SCREEN_PSBA_HI :Result:='mmSPI_P0_TRAP_SCREEN_PSBA_HI'; + mmSPI_P0_TRAP_SCREEN_PSMA_LO :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_LO'; + mmSPI_P0_TRAP_SCREEN_PSMA_HI :Result:='mmSPI_P0_TRAP_SCREEN_PSMA_HI'; + mmSPI_P0_TRAP_SCREEN_GPR_MIN :Result:='mmSPI_P0_TRAP_SCREEN_GPR_MIN'; + mmSPI_P1_TRAP_SCREEN_PSBA_LO :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_LO'; + mmSPI_P1_TRAP_SCREEN_PSBA_HI :Result:='mmSPI_P1_TRAP_SCREEN_PSBA_HI'; + mmSPI_P1_TRAP_SCREEN_PSMA_LO :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_LO'; + mmSPI_P1_TRAP_SCREEN_PSMA_HI :Result:='mmSPI_P1_TRAP_SCREEN_PSMA_HI'; + mmSPI_P1_TRAP_SCREEN_GPR_MIN :Result:='mmSPI_P1_TRAP_SCREEN_GPR_MIN'; + mmTD_CNTL :Result:='mmTD_CNTL'; + mmTD_STATUS :Result:='mmTD_STATUS'; + mmTD_CGTT_CTRL :Result:='mmTD_CGTT_CTRL'; + mmTD_DEBUG_INDEX :Result:='mmTD_DEBUG_INDEX'; + mmTD_DEBUG_DATA :Result:='mmTD_DEBUG_DATA'; + mmTD_DSM_CNTL :Result:='mmTD_DSM_CNTL'; + mmTD_SCRATCH :Result:='mmTD_SCRATCH'; + mmTA_CNTL :Result:='mmTA_CNTL'; + mmTA_CNTL_AUX :Result:='mmTA_CNTL_AUX'; + mmTA_RESERVED_010C :Result:='mmTA_RESERVED_010C'; + mmTA_CGTT_CTRL :Result:='mmTA_CGTT_CTRL'; + mmTA_STATUS :Result:='mmTA_STATUS'; + mmTA_DEBUG_INDEX :Result:='mmTA_DEBUG_INDEX'; + mmTA_DEBUG_DATA :Result:='mmTA_DEBUG_DATA'; + mmTA_SCRATCH :Result:='mmTA_SCRATCH'; + mmSH_HIDDEN_PRIVATE_BASE_VMID :Result:='mmSH_HIDDEN_PRIVATE_BASE_VMID'; + mmSH_STATIC_MEM_CONFIG :Result:='mmSH_STATIC_MEM_CONFIG'; + mmGDS_CONFIG :Result:='mmGDS_CONFIG'; + mmGDS_CNTL_STATUS :Result:='mmGDS_CNTL_STATUS'; + mmGDS_ENHANCE2 :Result:='mmGDS_ENHANCE2'; + mmGDS_PROTECTION_FAULT :Result:='mmGDS_PROTECTION_FAULT'; + mmGDS_VM_PROTECTION_FAULT :Result:='mmGDS_VM_PROTECTION_FAULT'; + mmGDS_EDC_CNT :Result:='mmGDS_EDC_CNT'; + mmGDS_EDC_GRBM_CNT :Result:='mmGDS_EDC_GRBM_CNT'; + mmGDS_EDC_OA_DED :Result:='mmGDS_EDC_OA_DED'; + mmGDS_DEBUG_CNTL :Result:='mmGDS_DEBUG_CNTL'; + mmGDS_DEBUG_DATA :Result:='mmGDS_DEBUG_DATA'; + mmGDS_DSM_CNTL :Result:='mmGDS_DSM_CNTL'; + mmCGTT_GDS_CLK_CTRL :Result:='mmCGTT_GDS_CLK_CTRL'; + mmGDS_SECDED_CNT :Result:='mmGDS_SECDED_CNT'; + mmGDS_GRBM_SECDED_CNT :Result:='mmGDS_GRBM_SECDED_CNT'; + mmGDS_OA_DED :Result:='mmGDS_OA_DED'; + mmDB_DEBUG :Result:='mmDB_DEBUG'; + mmDB_DEBUG2 :Result:='mmDB_DEBUG2'; + mmDB_DEBUG3 :Result:='mmDB_DEBUG3'; + mmDB_DEBUG4 :Result:='mmDB_DEBUG4'; + mmDB_CREDIT_LIMIT :Result:='mmDB_CREDIT_LIMIT'; + mmDB_WATERMARKS :Result:='mmDB_WATERMARKS'; + mmDB_SUBTILE_CONTROL :Result:='mmDB_SUBTILE_CONTROL'; + mmDB_FREE_CACHELINES :Result:='mmDB_FREE_CACHELINES'; + mmDB_FIFO_DEPTH1 :Result:='mmDB_FIFO_DEPTH1'; + mmDB_FIFO_DEPTH2 :Result:='mmDB_FIFO_DEPTH2'; + mmDB_CGTT_CLK_CTRL_0 :Result:='mmDB_CGTT_CLK_CTRL_0'; + mmDB_RING_CONTROL :Result:='mmDB_RING_CONTROL'; + mmDB_READ_DEBUG_0 :Result:='mmDB_READ_DEBUG_0'; + mmDB_READ_DEBUG_1 :Result:='mmDB_READ_DEBUG_1'; + mmDB_READ_DEBUG_2 :Result:='mmDB_READ_DEBUG_2'; + mmDB_READ_DEBUG_3 :Result:='mmDB_READ_DEBUG_3'; + mmDB_READ_DEBUG_4 :Result:='mmDB_READ_DEBUG_4'; + mmDB_READ_DEBUG_5 :Result:='mmDB_READ_DEBUG_5'; + mmDB_READ_DEBUG_6 :Result:='mmDB_READ_DEBUG_6'; + mmDB_READ_DEBUG_7 :Result:='mmDB_READ_DEBUG_7'; + mmDB_READ_DEBUG_8 :Result:='mmDB_READ_DEBUG_8'; + mmDB_READ_DEBUG_9 :Result:='mmDB_READ_DEBUG_9'; + mmDB_READ_DEBUG_A :Result:='mmDB_READ_DEBUG_A'; + mmDB_READ_DEBUG_B :Result:='mmDB_READ_DEBUG_B'; + mmDB_READ_DEBUG_C :Result:='mmDB_READ_DEBUG_C'; + mmDB_READ_DEBUG_D :Result:='mmDB_READ_DEBUG_D'; + mmDB_READ_DEBUG_E :Result:='mmDB_READ_DEBUG_E'; + mmDB_READ_DEBUG_F :Result:='mmDB_READ_DEBUG_F'; + mmCC_RB_REDUNDANCY :Result:='mmCC_RB_REDUNDANCY'; + mmCC_RB_BACKEND_DISABLE :Result:='mmCC_RB_BACKEND_DISABLE'; + mmGB_ADDR_CONFIG :Result:='mmGB_ADDR_CONFIG'; + mmGB_BACKEND_MAP :Result:='mmGB_BACKEND_MAP'; + mmGB_GPU_ID :Result:='mmGB_GPU_ID'; + mmCC_RB_DAISY_CHAIN :Result:='mmCC_RB_DAISY_CHAIN'; + mmGB_TILE_MODE0 :Result:='mmGB_TILE_MODE0'; + mmGB_TILE_MODE1 :Result:='mmGB_TILE_MODE1'; + mmGB_TILE_MODE2 :Result:='mmGB_TILE_MODE2'; + mmGB_TILE_MODE3 :Result:='mmGB_TILE_MODE3'; + mmGB_TILE_MODE4 :Result:='mmGB_TILE_MODE4'; + mmGB_TILE_MODE5 :Result:='mmGB_TILE_MODE5'; + mmGB_TILE_MODE6 :Result:='mmGB_TILE_MODE6'; + mmGB_TILE_MODE7 :Result:='mmGB_TILE_MODE7'; + mmGB_TILE_MODE8 :Result:='mmGB_TILE_MODE8'; + mmGB_TILE_MODE9 :Result:='mmGB_TILE_MODE9'; + mmGB_TILE_MODE10 :Result:='mmGB_TILE_MODE10'; + mmGB_TILE_MODE11 :Result:='mmGB_TILE_MODE11'; + mmGB_TILE_MODE12 :Result:='mmGB_TILE_MODE12'; + mmGB_TILE_MODE13 :Result:='mmGB_TILE_MODE13'; + mmGB_TILE_MODE14 :Result:='mmGB_TILE_MODE14'; + mmGB_TILE_MODE15 :Result:='mmGB_TILE_MODE15'; + mmGB_TILE_MODE16 :Result:='mmGB_TILE_MODE16'; + mmGB_TILE_MODE17 :Result:='mmGB_TILE_MODE17'; + mmGB_TILE_MODE18 :Result:='mmGB_TILE_MODE18'; + mmGB_TILE_MODE19 :Result:='mmGB_TILE_MODE19'; + mmGB_TILE_MODE20 :Result:='mmGB_TILE_MODE20'; + mmGB_TILE_MODE21 :Result:='mmGB_TILE_MODE21'; + mmGB_TILE_MODE22 :Result:='mmGB_TILE_MODE22'; + mmGB_TILE_MODE23 :Result:='mmGB_TILE_MODE23'; + mmGB_TILE_MODE24 :Result:='mmGB_TILE_MODE24'; + mmGB_TILE_MODE25 :Result:='mmGB_TILE_MODE25'; + mmGB_TILE_MODE26 :Result:='mmGB_TILE_MODE26'; + mmGB_TILE_MODE27 :Result:='mmGB_TILE_MODE27'; + mmGB_TILE_MODE28 :Result:='mmGB_TILE_MODE28'; + mmGB_TILE_MODE29 :Result:='mmGB_TILE_MODE29'; + mmGB_TILE_MODE30 :Result:='mmGB_TILE_MODE30'; + mmGB_TILE_MODE31 :Result:='mmGB_TILE_MODE31'; + mmGB_MACROTILE_MODE0 :Result:='mmGB_MACROTILE_MODE0'; + mmGB_MACROTILE_MODE1 :Result:='mmGB_MACROTILE_MODE1'; + mmGB_MACROTILE_MODE2 :Result:='mmGB_MACROTILE_MODE2'; + mmGB_MACROTILE_MODE3 :Result:='mmGB_MACROTILE_MODE3'; + mmGB_MACROTILE_MODE4 :Result:='mmGB_MACROTILE_MODE4'; + mmGB_MACROTILE_MODE5 :Result:='mmGB_MACROTILE_MODE5'; + mmGB_MACROTILE_MODE6 :Result:='mmGB_MACROTILE_MODE6'; + mmGB_MACROTILE_MODE7 :Result:='mmGB_MACROTILE_MODE7'; + mmGB_MACROTILE_MODE8 :Result:='mmGB_MACROTILE_MODE8'; + mmGB_MACROTILE_MODE9 :Result:='mmGB_MACROTILE_MODE9'; + mmGB_MACROTILE_MODE10 :Result:='mmGB_MACROTILE_MODE10'; + mmGB_MACROTILE_MODE11 :Result:='mmGB_MACROTILE_MODE11'; + mmGB_MACROTILE_MODE12 :Result:='mmGB_MACROTILE_MODE12'; + mmGB_MACROTILE_MODE13 :Result:='mmGB_MACROTILE_MODE13'; + mmGB_MACROTILE_MODE14 :Result:='mmGB_MACROTILE_MODE14'; + mmGB_MACROTILE_MODE15 :Result:='mmGB_MACROTILE_MODE15'; + mmCB_HW_CONTROL_3 :Result:='mmCB_HW_CONTROL_3'; + mmCB_HW_CONTROL :Result:='mmCB_HW_CONTROL'; + mmCB_HW_CONTROL_1 :Result:='mmCB_HW_CONTROL_1'; + mmCB_HW_CONTROL_2 :Result:='mmCB_HW_CONTROL_2'; + mmCB_DCC_CONFIG :Result:='mmCB_DCC_CONFIG'; + mmCB_PERFCOUNTER0_SELECT0 :Result:='mmCB_PERFCOUNTER0_SELECT0'; + mmCB_PERFCOUNTER1_SELECT0 :Result:='mmCB_PERFCOUNTER1_SELECT0'; + mmCB_PERFCOUNTER1_SELECT1 :Result:='mmCB_PERFCOUNTER1_SELECT1'; + mmCB_PERFCOUNTER2_SELECT0 :Result:='mmCB_PERFCOUNTER2_SELECT0'; + mmCB_PERFCOUNTER2_SELECT1 :Result:='mmCB_PERFCOUNTER2_SELECT1'; + mmCB_PERFCOUNTER3_SELECT0 :Result:='mmCB_PERFCOUNTER3_SELECT0'; + mmCB_PERFCOUNTER3_SELECT1 :Result:='mmCB_PERFCOUNTER3_SELECT1'; + mmCB_CGTT_SCLK_CTRL :Result:='mmCB_CGTT_SCLK_CTRL'; + mmCB_DEBUG_BUS_1 :Result:='mmCB_DEBUG_BUS_1'; + mmCB_DEBUG_BUS_2 :Result:='mmCB_DEBUG_BUS_2'; + mmCB_DEBUG_BUS_13 :Result:='mmCB_DEBUG_BUS_13'; + mmCB_DEBUG_BUS_14 :Result:='mmCB_DEBUG_BUS_14'; + mmCB_DEBUG_BUS_15 :Result:='mmCB_DEBUG_BUS_15'; + mmCB_DEBUG_BUS_16 :Result:='mmCB_DEBUG_BUS_16'; + mmCB_DEBUG_BUS_17 :Result:='mmCB_DEBUG_BUS_17'; + mmCB_DEBUG_BUS_18 :Result:='mmCB_DEBUG_BUS_18'; + mmCB_DEBUG_BUS_19 :Result:='mmCB_DEBUG_BUS_19'; + mmCB_DEBUG_BUS_20 :Result:='mmCB_DEBUG_BUS_20'; + mmCB_DEBUG_BUS_21 :Result:='mmCB_DEBUG_BUS_21'; + mmCB_DEBUG_BUS_22 :Result:='mmCB_DEBUG_BUS_22'; + mmGC_USER_RB_REDUNDANCY :Result:='mmGC_USER_RB_REDUNDANCY'; + mmGC_USER_RB_BACKEND_DISABLE :Result:='mmGC_USER_RB_BACKEND_DISABLE'; + mmTCP_INVALIDATE :Result:='mmTCP_INVALIDATE'; + mmTCP_STATUS :Result:='mmTCP_STATUS'; + mmTCP_CNTL :Result:='mmTCP_CNTL'; + mmTCP_CHAN_STEER_LO :Result:='mmTCP_CHAN_STEER_LO'; + mmTCP_CHAN_STEER_HI :Result:='mmTCP_CHAN_STEER_HI'; + mmTCP_ADDR_CONFIG :Result:='mmTCP_ADDR_CONFIG'; + mmTCP_CREDIT :Result:='mmTCP_CREDIT'; + mmCGTT_TCP_CLK_CTRL :Result:='mmCGTT_TCP_CLK_CTRL'; + mmTCP_BUFFER_ADDR_HASH_CNTL :Result:='mmTCP_BUFFER_ADDR_HASH_CNTL'; + mmTCP_EDC_CNT :Result:='mmTCP_EDC_CNT'; + mmTC_CFG_L1_LOAD_POLICY0 :Result:='mmTC_CFG_L1_LOAD_POLICY0'; + mmTC_CFG_L1_LOAD_POLICY1 :Result:='mmTC_CFG_L1_LOAD_POLICY1'; + mmTC_CFG_L1_STORE_POLICY :Result:='mmTC_CFG_L1_STORE_POLICY'; + mmTC_CFG_L2_LOAD_POLICY0 :Result:='mmTC_CFG_L2_LOAD_POLICY0'; + mmTC_CFG_L2_LOAD_POLICY1 :Result:='mmTC_CFG_L2_LOAD_POLICY1'; + mmTC_CFG_L2_STORE_POLICY0 :Result:='mmTC_CFG_L2_STORE_POLICY0'; + mmTC_CFG_L2_STORE_POLICY1 :Result:='mmTC_CFG_L2_STORE_POLICY1'; + mmTC_CFG_L2_ATOMIC_POLICY :Result:='mmTC_CFG_L2_ATOMIC_POLICY'; + mmTC_CFG_L1_VOLATILE :Result:='mmTC_CFG_L1_VOLATILE'; + mmTC_CFG_L2_VOLATILE :Result:='mmTC_CFG_L2_VOLATILE'; + mmCGTT_TCI_CLK_CTRL :Result:='mmCGTT_TCI_CLK_CTRL'; + mmTCI_STATUS :Result:='mmTCI_STATUS'; + mmTCI_CNTL_1 :Result:='mmTCI_CNTL_1'; + mmTCI_CNTL_2 :Result:='mmTCI_CNTL_2'; + mmTCC_CTRL :Result:='mmTCC_CTRL'; + mmTCC_CGTT_SCLK_CTRL :Result:='mmTCC_CGTT_SCLK_CTRL'; + mmTCC_EDC_CNT :Result:='mmTCC_EDC_CNT'; + mmTCC_REDUNDANCY :Result:='mmTCC_REDUNDANCY'; + mmTCC_EXE_DISABLE :Result:='mmTCC_EXE_DISABLE'; + mmTCC_DSM_CNTL :Result:='mmTCC_DSM_CNTL'; + mmTCA_CTRL :Result:='mmTCA_CTRL'; + mmTCA_CGTT_SCLK_CTRL :Result:='mmTCA_CGTT_SCLK_CTRL'; + mmSPI_SHADER_TBA_LO_PS :Result:='mmSPI_SHADER_TBA_LO_PS'; + mmSPI_SHADER_TBA_HI_PS :Result:='mmSPI_SHADER_TBA_HI_PS'; + mmSPI_SHADER_TMA_LO_PS :Result:='mmSPI_SHADER_TMA_LO_PS'; + mmSPI_SHADER_TMA_HI_PS :Result:='mmSPI_SHADER_TMA_HI_PS'; + mmSPI_SHADER_PGM_RSRC3_PS :Result:='mmSPI_SHADER_PGM_RSRC3_PS'; + mmSPI_SHADER_PGM_LO_PS :Result:='mmSPI_SHADER_PGM_LO_PS'; + mmSPI_SHADER_PGM_HI_PS :Result:='mmSPI_SHADER_PGM_HI_PS'; + mmSPI_SHADER_PGM_RSRC1_PS :Result:='mmSPI_SHADER_PGM_RSRC1_PS'; + mmSPI_SHADER_PGM_RSRC2_PS :Result:='mmSPI_SHADER_PGM_RSRC2_PS'; + mmSPI_SHADER_USER_DATA_PS_0 :Result:='mmSPI_SHADER_USER_DATA_PS_0'; + mmSPI_SHADER_USER_DATA_PS_1 :Result:='mmSPI_SHADER_USER_DATA_PS_1'; + mmSPI_SHADER_USER_DATA_PS_2 :Result:='mmSPI_SHADER_USER_DATA_PS_2'; + mmSPI_SHADER_USER_DATA_PS_3 :Result:='mmSPI_SHADER_USER_DATA_PS_3'; + mmSPI_SHADER_USER_DATA_PS_4 :Result:='mmSPI_SHADER_USER_DATA_PS_4'; + mmSPI_SHADER_USER_DATA_PS_5 :Result:='mmSPI_SHADER_USER_DATA_PS_5'; + mmSPI_SHADER_USER_DATA_PS_6 :Result:='mmSPI_SHADER_USER_DATA_PS_6'; + mmSPI_SHADER_USER_DATA_PS_7 :Result:='mmSPI_SHADER_USER_DATA_PS_7'; + mmSPI_SHADER_USER_DATA_PS_8 :Result:='mmSPI_SHADER_USER_DATA_PS_8'; + mmSPI_SHADER_USER_DATA_PS_9 :Result:='mmSPI_SHADER_USER_DATA_PS_9'; + mmSPI_SHADER_USER_DATA_PS_10 :Result:='mmSPI_SHADER_USER_DATA_PS_10'; + mmSPI_SHADER_USER_DATA_PS_11 :Result:='mmSPI_SHADER_USER_DATA_PS_11'; + mmSPI_SHADER_USER_DATA_PS_12 :Result:='mmSPI_SHADER_USER_DATA_PS_12'; + mmSPI_SHADER_USER_DATA_PS_13 :Result:='mmSPI_SHADER_USER_DATA_PS_13'; + mmSPI_SHADER_USER_DATA_PS_14 :Result:='mmSPI_SHADER_USER_DATA_PS_14'; + mmSPI_SHADER_USER_DATA_PS_15 :Result:='mmSPI_SHADER_USER_DATA_PS_15'; + mmSPI_SHADER_TBA_LO_VS :Result:='mmSPI_SHADER_TBA_LO_VS'; + mmSPI_SHADER_TBA_HI_VS :Result:='mmSPI_SHADER_TBA_HI_VS'; + mmSPI_SHADER_TMA_LO_VS :Result:='mmSPI_SHADER_TMA_LO_VS'; + mmSPI_SHADER_TMA_HI_VS :Result:='mmSPI_SHADER_TMA_HI_VS'; + mmSPI_SHADER_PGM_RSRC3_VS :Result:='mmSPI_SHADER_PGM_RSRC3_VS'; + mmSPI_SHADER_LATE_ALLOC_VS :Result:='mmSPI_SHADER_LATE_ALLOC_VS'; + mmSPI_SHADER_PGM_LO_VS :Result:='mmSPI_SHADER_PGM_LO_VS'; + mmSPI_SHADER_PGM_HI_VS :Result:='mmSPI_SHADER_PGM_HI_VS'; + mmSPI_SHADER_PGM_RSRC1_VS :Result:='mmSPI_SHADER_PGM_RSRC1_VS'; + mmSPI_SHADER_PGM_RSRC2_VS :Result:='mmSPI_SHADER_PGM_RSRC2_VS'; + mmSPI_SHADER_USER_DATA_VS_0 :Result:='mmSPI_SHADER_USER_DATA_VS_0'; + mmSPI_SHADER_USER_DATA_VS_1 :Result:='mmSPI_SHADER_USER_DATA_VS_1'; + mmSPI_SHADER_USER_DATA_VS_2 :Result:='mmSPI_SHADER_USER_DATA_VS_2'; + mmSPI_SHADER_USER_DATA_VS_3 :Result:='mmSPI_SHADER_USER_DATA_VS_3'; + mmSPI_SHADER_USER_DATA_VS_4 :Result:='mmSPI_SHADER_USER_DATA_VS_4'; + mmSPI_SHADER_USER_DATA_VS_5 :Result:='mmSPI_SHADER_USER_DATA_VS_5'; + mmSPI_SHADER_USER_DATA_VS_6 :Result:='mmSPI_SHADER_USER_DATA_VS_6'; + mmSPI_SHADER_USER_DATA_VS_7 :Result:='mmSPI_SHADER_USER_DATA_VS_7'; + mmSPI_SHADER_USER_DATA_VS_8 :Result:='mmSPI_SHADER_USER_DATA_VS_8'; + mmSPI_SHADER_USER_DATA_VS_9 :Result:='mmSPI_SHADER_USER_DATA_VS_9'; + mmSPI_SHADER_USER_DATA_VS_10 :Result:='mmSPI_SHADER_USER_DATA_VS_10'; + mmSPI_SHADER_USER_DATA_VS_11 :Result:='mmSPI_SHADER_USER_DATA_VS_11'; + mmSPI_SHADER_USER_DATA_VS_12 :Result:='mmSPI_SHADER_USER_DATA_VS_12'; + mmSPI_SHADER_USER_DATA_VS_13 :Result:='mmSPI_SHADER_USER_DATA_VS_13'; + mmSPI_SHADER_USER_DATA_VS_14 :Result:='mmSPI_SHADER_USER_DATA_VS_14'; + mmSPI_SHADER_USER_DATA_VS_15 :Result:='mmSPI_SHADER_USER_DATA_VS_15'; + mmSPI_SHADER_PGM_RSRC2_ES_VS :Result:='mmSPI_SHADER_PGM_RSRC2_ES_VS'; + mmSPI_SHADER_PGM_RSRC2_LS_VS :Result:='mmSPI_SHADER_PGM_RSRC2_LS_VS'; + mmSPI_SHADER_TBA_LO_GS :Result:='mmSPI_SHADER_TBA_LO_GS'; + mmSPI_SHADER_TBA_HI_GS :Result:='mmSPI_SHADER_TBA_HI_GS'; + mmSPI_SHADER_TMA_LO_GS :Result:='mmSPI_SHADER_TMA_LO_GS'; + mmSPI_SHADER_TMA_HI_GS :Result:='mmSPI_SHADER_TMA_HI_GS'; + mmSPI_SHADER_PGM_RSRC3_GS :Result:='mmSPI_SHADER_PGM_RSRC3_GS'; + mmSPI_SHADER_PGM_LO_GS :Result:='mmSPI_SHADER_PGM_LO_GS'; + mmSPI_SHADER_PGM_HI_GS :Result:='mmSPI_SHADER_PGM_HI_GS'; + mmSPI_SHADER_PGM_RSRC1_GS :Result:='mmSPI_SHADER_PGM_RSRC1_GS'; + mmSPI_SHADER_PGM_RSRC2_GS :Result:='mmSPI_SHADER_PGM_RSRC2_GS'; + mmSPI_SHADER_USER_DATA_GS_0 :Result:='mmSPI_SHADER_USER_DATA_GS_0'; + mmSPI_SHADER_USER_DATA_GS_1 :Result:='mmSPI_SHADER_USER_DATA_GS_1'; + mmSPI_SHADER_USER_DATA_GS_2 :Result:='mmSPI_SHADER_USER_DATA_GS_2'; + mmSPI_SHADER_USER_DATA_GS_3 :Result:='mmSPI_SHADER_USER_DATA_GS_3'; + mmSPI_SHADER_USER_DATA_GS_4 :Result:='mmSPI_SHADER_USER_DATA_GS_4'; + mmSPI_SHADER_USER_DATA_GS_5 :Result:='mmSPI_SHADER_USER_DATA_GS_5'; + mmSPI_SHADER_USER_DATA_GS_6 :Result:='mmSPI_SHADER_USER_DATA_GS_6'; + mmSPI_SHADER_USER_DATA_GS_7 :Result:='mmSPI_SHADER_USER_DATA_GS_7'; + mmSPI_SHADER_USER_DATA_GS_8 :Result:='mmSPI_SHADER_USER_DATA_GS_8'; + mmSPI_SHADER_USER_DATA_GS_9 :Result:='mmSPI_SHADER_USER_DATA_GS_9'; + mmSPI_SHADER_USER_DATA_GS_10 :Result:='mmSPI_SHADER_USER_DATA_GS_10'; + mmSPI_SHADER_USER_DATA_GS_11 :Result:='mmSPI_SHADER_USER_DATA_GS_11'; + mmSPI_SHADER_USER_DATA_GS_12 :Result:='mmSPI_SHADER_USER_DATA_GS_12'; + mmSPI_SHADER_USER_DATA_GS_13 :Result:='mmSPI_SHADER_USER_DATA_GS_13'; + mmSPI_SHADER_USER_DATA_GS_14 :Result:='mmSPI_SHADER_USER_DATA_GS_14'; + mmSPI_SHADER_USER_DATA_GS_15 :Result:='mmSPI_SHADER_USER_DATA_GS_15'; + mmSPI_SHADER_PGM_RSRC2_ES_GS :Result:='mmSPI_SHADER_PGM_RSRC2_ES_GS'; + mmSPI_SHADER_TBA_LO_ES :Result:='mmSPI_SHADER_TBA_LO_ES'; + mmSPI_SHADER_TBA_HI_ES :Result:='mmSPI_SHADER_TBA_HI_ES'; + mmSPI_SHADER_TMA_LO_ES :Result:='mmSPI_SHADER_TMA_LO_ES'; + mmSPI_SHADER_TMA_HI_ES :Result:='mmSPI_SHADER_TMA_HI_ES'; + mmSPI_SHADER_PGM_RSRC3_ES :Result:='mmSPI_SHADER_PGM_RSRC3_ES'; + mmSPI_SHADER_PGM_LO_ES :Result:='mmSPI_SHADER_PGM_LO_ES'; + mmSPI_SHADER_PGM_HI_ES :Result:='mmSPI_SHADER_PGM_HI_ES'; + mmSPI_SHADER_PGM_RSRC1_ES :Result:='mmSPI_SHADER_PGM_RSRC1_ES'; + mmSPI_SHADER_PGM_RSRC2_ES :Result:='mmSPI_SHADER_PGM_RSRC2_ES'; + mmSPI_SHADER_USER_DATA_ES_0 :Result:='mmSPI_SHADER_USER_DATA_ES_0'; + mmSPI_SHADER_USER_DATA_ES_1 :Result:='mmSPI_SHADER_USER_DATA_ES_1'; + mmSPI_SHADER_USER_DATA_ES_2 :Result:='mmSPI_SHADER_USER_DATA_ES_2'; + mmSPI_SHADER_USER_DATA_ES_3 :Result:='mmSPI_SHADER_USER_DATA_ES_3'; + mmSPI_SHADER_USER_DATA_ES_4 :Result:='mmSPI_SHADER_USER_DATA_ES_4'; + mmSPI_SHADER_USER_DATA_ES_5 :Result:='mmSPI_SHADER_USER_DATA_ES_5'; + mmSPI_SHADER_USER_DATA_ES_6 :Result:='mmSPI_SHADER_USER_DATA_ES_6'; + mmSPI_SHADER_USER_DATA_ES_7 :Result:='mmSPI_SHADER_USER_DATA_ES_7'; + mmSPI_SHADER_USER_DATA_ES_8 :Result:='mmSPI_SHADER_USER_DATA_ES_8'; + mmSPI_SHADER_USER_DATA_ES_9 :Result:='mmSPI_SHADER_USER_DATA_ES_9'; + mmSPI_SHADER_USER_DATA_ES_10 :Result:='mmSPI_SHADER_USER_DATA_ES_10'; + mmSPI_SHADER_USER_DATA_ES_11 :Result:='mmSPI_SHADER_USER_DATA_ES_11'; + mmSPI_SHADER_USER_DATA_ES_12 :Result:='mmSPI_SHADER_USER_DATA_ES_12'; + mmSPI_SHADER_USER_DATA_ES_13 :Result:='mmSPI_SHADER_USER_DATA_ES_13'; + mmSPI_SHADER_USER_DATA_ES_14 :Result:='mmSPI_SHADER_USER_DATA_ES_14'; + mmSPI_SHADER_USER_DATA_ES_15 :Result:='mmSPI_SHADER_USER_DATA_ES_15'; + mmSPI_SHADER_PGM_RSRC2_LS_ES :Result:='mmSPI_SHADER_PGM_RSRC2_LS_ES'; + mmSPI_SHADER_TBA_LO_HS :Result:='mmSPI_SHADER_TBA_LO_HS'; + mmSPI_SHADER_TBA_HI_HS :Result:='mmSPI_SHADER_TBA_HI_HS'; + mmSPI_SHADER_TMA_LO_HS :Result:='mmSPI_SHADER_TMA_LO_HS'; + mmSPI_SHADER_TMA_HI_HS :Result:='mmSPI_SHADER_TMA_HI_HS'; + mmSPI_SHADER_PGM_RSRC3_HS :Result:='mmSPI_SHADER_PGM_RSRC3_HS'; + mmSPI_SHADER_PGM_LO_HS :Result:='mmSPI_SHADER_PGM_LO_HS'; + mmSPI_SHADER_PGM_HI_HS :Result:='mmSPI_SHADER_PGM_HI_HS'; + mmSPI_SHADER_PGM_RSRC1_HS :Result:='mmSPI_SHADER_PGM_RSRC1_HS'; + mmSPI_SHADER_PGM_RSRC2_HS :Result:='mmSPI_SHADER_PGM_RSRC2_HS'; + mmSPI_SHADER_USER_DATA_HS_0 :Result:='mmSPI_SHADER_USER_DATA_HS_0'; + mmSPI_SHADER_USER_DATA_HS_1 :Result:='mmSPI_SHADER_USER_DATA_HS_1'; + mmSPI_SHADER_USER_DATA_HS_2 :Result:='mmSPI_SHADER_USER_DATA_HS_2'; + mmSPI_SHADER_USER_DATA_HS_3 :Result:='mmSPI_SHADER_USER_DATA_HS_3'; + mmSPI_SHADER_USER_DATA_HS_4 :Result:='mmSPI_SHADER_USER_DATA_HS_4'; + mmSPI_SHADER_USER_DATA_HS_5 :Result:='mmSPI_SHADER_USER_DATA_HS_5'; + mmSPI_SHADER_USER_DATA_HS_6 :Result:='mmSPI_SHADER_USER_DATA_HS_6'; + mmSPI_SHADER_USER_DATA_HS_7 :Result:='mmSPI_SHADER_USER_DATA_HS_7'; + mmSPI_SHADER_USER_DATA_HS_8 :Result:='mmSPI_SHADER_USER_DATA_HS_8'; + mmSPI_SHADER_USER_DATA_HS_9 :Result:='mmSPI_SHADER_USER_DATA_HS_9'; + mmSPI_SHADER_USER_DATA_HS_10 :Result:='mmSPI_SHADER_USER_DATA_HS_10'; + mmSPI_SHADER_USER_DATA_HS_11 :Result:='mmSPI_SHADER_USER_DATA_HS_11'; + mmSPI_SHADER_USER_DATA_HS_12 :Result:='mmSPI_SHADER_USER_DATA_HS_12'; + mmSPI_SHADER_USER_DATA_HS_13 :Result:='mmSPI_SHADER_USER_DATA_HS_13'; + mmSPI_SHADER_USER_DATA_HS_14 :Result:='mmSPI_SHADER_USER_DATA_HS_14'; + mmSPI_SHADER_USER_DATA_HS_15 :Result:='mmSPI_SHADER_USER_DATA_HS_15'; + mmSPI_SHADER_PGM_RSRC2_LS_HS :Result:='mmSPI_SHADER_PGM_RSRC2_LS_HS'; + mmSPI_SHADER_TBA_LO_LS :Result:='mmSPI_SHADER_TBA_LO_LS'; + mmSPI_SHADER_TBA_HI_LS :Result:='mmSPI_SHADER_TBA_HI_LS'; + mmSPI_SHADER_TMA_LO_LS :Result:='mmSPI_SHADER_TMA_LO_LS'; + mmSPI_SHADER_TMA_HI_LS :Result:='mmSPI_SHADER_TMA_HI_LS'; + mmSPI_SHADER_PGM_RSRC3_LS :Result:='mmSPI_SHADER_PGM_RSRC3_LS'; + mmSPI_SHADER_PGM_LO_LS :Result:='mmSPI_SHADER_PGM_LO_LS'; + mmSPI_SHADER_PGM_HI_LS :Result:='mmSPI_SHADER_PGM_HI_LS'; + mmSPI_SHADER_PGM_RSRC1_LS :Result:='mmSPI_SHADER_PGM_RSRC1_LS'; + mmSPI_SHADER_PGM_RSRC2_LS :Result:='mmSPI_SHADER_PGM_RSRC2_LS'; + mmSPI_SHADER_USER_DATA_LS_0 :Result:='mmSPI_SHADER_USER_DATA_LS_0'; + mmSPI_SHADER_USER_DATA_LS_1 :Result:='mmSPI_SHADER_USER_DATA_LS_1'; + mmSPI_SHADER_USER_DATA_LS_2 :Result:='mmSPI_SHADER_USER_DATA_LS_2'; + mmSPI_SHADER_USER_DATA_LS_3 :Result:='mmSPI_SHADER_USER_DATA_LS_3'; + mmSPI_SHADER_USER_DATA_LS_4 :Result:='mmSPI_SHADER_USER_DATA_LS_4'; + mmSPI_SHADER_USER_DATA_LS_5 :Result:='mmSPI_SHADER_USER_DATA_LS_5'; + mmSPI_SHADER_USER_DATA_LS_6 :Result:='mmSPI_SHADER_USER_DATA_LS_6'; + mmSPI_SHADER_USER_DATA_LS_7 :Result:='mmSPI_SHADER_USER_DATA_LS_7'; + mmSPI_SHADER_USER_DATA_LS_8 :Result:='mmSPI_SHADER_USER_DATA_LS_8'; + mmSPI_SHADER_USER_DATA_LS_9 :Result:='mmSPI_SHADER_USER_DATA_LS_9'; + mmSPI_SHADER_USER_DATA_LS_10 :Result:='mmSPI_SHADER_USER_DATA_LS_10'; + mmSPI_SHADER_USER_DATA_LS_11 :Result:='mmSPI_SHADER_USER_DATA_LS_11'; + mmSPI_SHADER_USER_DATA_LS_12 :Result:='mmSPI_SHADER_USER_DATA_LS_12'; + mmSPI_SHADER_USER_DATA_LS_13 :Result:='mmSPI_SHADER_USER_DATA_LS_13'; + mmSPI_SHADER_USER_DATA_LS_14 :Result:='mmSPI_SHADER_USER_DATA_LS_14'; + mmSPI_SHADER_USER_DATA_LS_15 :Result:='mmSPI_SHADER_USER_DATA_LS_15'; + mmCOMPUTE_DISPATCH_INITIATOR :Result:='mmCOMPUTE_DISPATCH_INITIATOR'; + mmCOMPUTE_DIM_X :Result:='mmCOMPUTE_DIM_X'; + mmCOMPUTE_DIM_Y :Result:='mmCOMPUTE_DIM_Y'; + mmCOMPUTE_DIM_Z :Result:='mmCOMPUTE_DIM_Z'; + mmCOMPUTE_START_X :Result:='mmCOMPUTE_START_X'; + mmCOMPUTE_START_Y :Result:='mmCOMPUTE_START_Y'; + mmCOMPUTE_START_Z :Result:='mmCOMPUTE_START_Z'; + mmCOMPUTE_NUM_THREAD_X :Result:='mmCOMPUTE_NUM_THREAD_X'; + mmCOMPUTE_NUM_THREAD_Y :Result:='mmCOMPUTE_NUM_THREAD_Y'; + mmCOMPUTE_NUM_THREAD_Z :Result:='mmCOMPUTE_NUM_THREAD_Z'; + mmCOMPUTE_PIPELINESTAT_ENABLE :Result:='mmCOMPUTE_PIPELINESTAT_ENABLE'; + mmCOMPUTE_PERFCOUNT_ENABLE :Result:='mmCOMPUTE_PERFCOUNT_ENABLE'; + mmCOMPUTE_PGM_LO :Result:='mmCOMPUTE_PGM_LO'; + mmCOMPUTE_PGM_HI :Result:='mmCOMPUTE_PGM_HI'; + mmCOMPUTE_TBA_LO :Result:='mmCOMPUTE_TBA_LO'; + mmCOMPUTE_TBA_HI :Result:='mmCOMPUTE_TBA_HI'; + mmCOMPUTE_TMA_LO :Result:='mmCOMPUTE_TMA_LO'; + mmCOMPUTE_TMA_HI :Result:='mmCOMPUTE_TMA_HI'; + mmCOMPUTE_PGM_RSRC1 :Result:='mmCOMPUTE_PGM_RSRC1'; + mmCOMPUTE_PGM_RSRC2 :Result:='mmCOMPUTE_PGM_RSRC2'; + mmCOMPUTE_VMID :Result:='mmCOMPUTE_VMID'; + mmCOMPUTE_RESOURCE_LIMITS :Result:='mmCOMPUTE_RESOURCE_LIMITS'; + mmCOMPUTE_STATIC_THREAD_MGMT_SE0 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE0'; + mmCOMPUTE_STATIC_THREAD_MGMT_SE1 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE1'; + mmCOMPUTE_TMPRING_SIZE :Result:='mmCOMPUTE_TMPRING_SIZE'; + mmCOMPUTE_STATIC_THREAD_MGMT_SE2 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE2'; + mmCOMPUTE_STATIC_THREAD_MGMT_SE3 :Result:='mmCOMPUTE_STATIC_THREAD_MGMT_SE3'; + mmCOMPUTE_RESTART_X :Result:='mmCOMPUTE_RESTART_X'; + mmCOMPUTE_RESTART_Y :Result:='mmCOMPUTE_RESTART_Y'; + mmCOMPUTE_RESTART_Z :Result:='mmCOMPUTE_RESTART_Z'; + mmCOMPUTE_THREAD_TRACE_ENABLE :Result:='mmCOMPUTE_THREAD_TRACE_ENABLE'; + mmCOMPUTE_MISC_RESERVED :Result:='mmCOMPUTE_MISC_RESERVED'; + mmCOMPUTE_DISPATCH_ID :Result:='mmCOMPUTE_DISPATCH_ID'; + mmCOMPUTE_THREADGROUP_ID :Result:='mmCOMPUTE_THREADGROUP_ID'; + mmCOMPUTE_RELAUNCH :Result:='mmCOMPUTE_RELAUNCH'; + mmCOMPUTE_WAVE_RESTORE_ADDR_LO :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_LO'; + mmCOMPUTE_WAVE_RESTORE_ADDR_HI :Result:='mmCOMPUTE_WAVE_RESTORE_ADDR_HI'; + mmCOMPUTE_WAVE_RESTORE_CONTROL :Result:='mmCOMPUTE_WAVE_RESTORE_CONTROL'; + mmCOMPUTE_USER_DATA_0 :Result:='mmCOMPUTE_USER_DATA_0'; + mmCOMPUTE_USER_DATA_1 :Result:='mmCOMPUTE_USER_DATA_1'; + mmCOMPUTE_USER_DATA_2 :Result:='mmCOMPUTE_USER_DATA_2'; + mmCOMPUTE_USER_DATA_3 :Result:='mmCOMPUTE_USER_DATA_3'; + mmCOMPUTE_USER_DATA_4 :Result:='mmCOMPUTE_USER_DATA_4'; + mmCOMPUTE_USER_DATA_5 :Result:='mmCOMPUTE_USER_DATA_5'; + mmCOMPUTE_USER_DATA_6 :Result:='mmCOMPUTE_USER_DATA_6'; + mmCOMPUTE_USER_DATA_7 :Result:='mmCOMPUTE_USER_DATA_7'; + mmCOMPUTE_USER_DATA_8 :Result:='mmCOMPUTE_USER_DATA_8'; + mmCOMPUTE_USER_DATA_9 :Result:='mmCOMPUTE_USER_DATA_9'; + mmCOMPUTE_USER_DATA_10 :Result:='mmCOMPUTE_USER_DATA_10'; + mmCOMPUTE_USER_DATA_11 :Result:='mmCOMPUTE_USER_DATA_11'; + mmCOMPUTE_USER_DATA_12 :Result:='mmCOMPUTE_USER_DATA_12'; + mmCOMPUTE_USER_DATA_13 :Result:='mmCOMPUTE_USER_DATA_13'; + mmCOMPUTE_USER_DATA_14 :Result:='mmCOMPUTE_USER_DATA_14'; + mmCOMPUTE_USER_DATA_15 :Result:='mmCOMPUTE_USER_DATA_15'; + mmCOMPUTE_NOWHERE :Result:='mmCOMPUTE_NOWHERE'; + mmCP_DFY_CNTL :Result:='mmCP_DFY_CNTL'; + mmCP_DFY_STAT :Result:='mmCP_DFY_STAT'; + mmCP_DFY_ADDR_HI :Result:='mmCP_DFY_ADDR_HI'; + mmCP_DFY_ADDR_LO :Result:='mmCP_DFY_ADDR_LO'; + mmCP_DFY_DATA_0 :Result:='mmCP_DFY_DATA_0'; + mmCP_DFY_DATA_1 :Result:='mmCP_DFY_DATA_1'; + mmCP_DFY_DATA_2 :Result:='mmCP_DFY_DATA_2'; + mmCP_DFY_DATA_3 :Result:='mmCP_DFY_DATA_3'; + mmCP_DFY_DATA_4 :Result:='mmCP_DFY_DATA_4'; + mmCP_DFY_DATA_5 :Result:='mmCP_DFY_DATA_5'; + mmCP_DFY_DATA_6 :Result:='mmCP_DFY_DATA_6'; + mmCP_DFY_DATA_7 :Result:='mmCP_DFY_DATA_7'; + mmCP_DFY_DATA_8 :Result:='mmCP_DFY_DATA_8'; + mmCP_DFY_DATA_9 :Result:='mmCP_DFY_DATA_9'; + mmCP_DFY_DATA_10 :Result:='mmCP_DFY_DATA_10'; + mmCP_DFY_DATA_11 :Result:='mmCP_DFY_DATA_11'; + mmCP_DFY_DATA_12 :Result:='mmCP_DFY_DATA_12'; + mmCP_DFY_DATA_13 :Result:='mmCP_DFY_DATA_13'; + mmCP_DFY_DATA_14 :Result:='mmCP_DFY_DATA_14'; + mmCP_DFY_DATA_15 :Result:='mmCP_DFY_DATA_15'; + mmCP_DFY_CMD :Result:='mmCP_DFY_CMD'; + mmCP_CPC_MGCG_SYNC_CNTL :Result:='mmCP_CPC_MGCG_SYNC_CNTL'; + mmCP_VIRT_STATUS :Result:='mmCP_VIRT_STATUS'; + mmCP_RB0_BASE :Result:='mmCP_RB0_BASE'; + mmCP_RB0_CNTL :Result:='mmCP_RB0_CNTL'; + mmCP_RB_RPTR_WR :Result:='mmCP_RB_RPTR_WR'; + mmCP_RB0_RPTR_ADDR :Result:='mmCP_RB0_RPTR_ADDR'; + mmCP_RB0_RPTR_ADDR_HI :Result:='mmCP_RB0_RPTR_ADDR_HI'; + mmCP_RB0_WPTR :Result:='mmCP_RB0_WPTR'; + mmCP_RB_WPTR_POLL_ADDR_LO :Result:='mmCP_RB_WPTR_POLL_ADDR_LO'; + mmCP_RB_WPTR_POLL_ADDR_HI :Result:='mmCP_RB_WPTR_POLL_ADDR_HI'; + mmCP_INT_CNTL :Result:='mmCP_INT_CNTL'; + mmCP_INT_STATUS :Result:='mmCP_INT_STATUS'; + mmCP_DEVICE_ID :Result:='mmCP_DEVICE_ID'; + mmCP_ME0_PIPE_PRIORITY_CNTS :Result:='mmCP_ME0_PIPE_PRIORITY_CNTS'; + mmCP_ME0_PIPE0_PRIORITY :Result:='mmCP_ME0_PIPE0_PRIORITY'; + mmCP_ME0_PIPE1_PRIORITY :Result:='mmCP_ME0_PIPE1_PRIORITY'; + mmCP_ME0_PIPE2_PRIORITY :Result:='mmCP_ME0_PIPE2_PRIORITY'; + mmCP_ENDIAN_SWAP :Result:='mmCP_ENDIAN_SWAP'; + mmCP_RB_VMID :Result:='mmCP_RB_VMID'; + mmCP_ME0_PIPE0_VMID :Result:='mmCP_ME0_PIPE0_VMID'; + mmCP_ME0_PIPE1_VMID :Result:='mmCP_ME0_PIPE1_VMID'; + mmCP_RB_DOORBELL_CONTROL :Result:='mmCP_RB_DOORBELL_CONTROL'; + mmCP_RB_DOORBELL_RANGE_LOWER :Result:='mmCP_RB_DOORBELL_RANGE_LOWER'; + mmCP_RB_DOORBELL_RANGE_UPPER :Result:='mmCP_RB_DOORBELL_RANGE_UPPER'; + mmCP_MEC_DOORBELL_RANGE_LOWER :Result:='mmCP_MEC_DOORBELL_RANGE_LOWER'; + mmCP_MEC_DOORBELL_RANGE_UPPER :Result:='mmCP_MEC_DOORBELL_RANGE_UPPER'; + mmCP_RB1_BASE :Result:='mmCP_RB1_BASE'; + mmCP_RB1_CNTL :Result:='mmCP_RB1_CNTL'; + mmCP_RB1_RPTR_ADDR :Result:='mmCP_RB1_RPTR_ADDR'; + mmCP_RB1_RPTR_ADDR_HI :Result:='mmCP_RB1_RPTR_ADDR_HI'; + mmCP_RB1_WPTR :Result:='mmCP_RB1_WPTR'; + mmCP_RB2_BASE :Result:='mmCP_RB2_BASE'; + mmCP_RB2_CNTL :Result:='mmCP_RB2_CNTL'; + mmCP_RB2_RPTR_ADDR :Result:='mmCP_RB2_RPTR_ADDR'; + mmCP_RB2_RPTR_ADDR_HI :Result:='mmCP_RB2_RPTR_ADDR_HI'; + mmCP_RB2_WPTR :Result:='mmCP_RB2_WPTR'; + mmCP_INT_CNTL_RING0 :Result:='mmCP_INT_CNTL_RING0'; + mmCP_INT_CNTL_RING1 :Result:='mmCP_INT_CNTL_RING1'; + mmCP_INT_CNTL_RING2 :Result:='mmCP_INT_CNTL_RING2'; + mmCP_INT_STATUS_RING0 :Result:='mmCP_INT_STATUS_RING0'; + mmCP_INT_STATUS_RING1 :Result:='mmCP_INT_STATUS_RING1'; + mmCP_INT_STATUS_RING2 :Result:='mmCP_INT_STATUS_RING2'; + mmCP_PWR_CNTL :Result:='mmCP_PWR_CNTL'; + mmCP_MEM_SLP_CNTL :Result:='mmCP_MEM_SLP_CNTL'; + mmCP_ECC_FIRSTOCCURRENCE :Result:='mmCP_ECC_FIRSTOCCURRENCE'; + mmCP_ECC_FIRSTOCCURRENCE_RING0 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING0'; + mmCP_ECC_FIRSTOCCURRENCE_RING1 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING1'; + mmCP_ECC_FIRSTOCCURRENCE_RING2 :Result:='mmCP_ECC_FIRSTOCCURRENCE_RING2'; + mmGB_EDC_MODE :Result:='mmGB_EDC_MODE'; + mmCP_DEBUG :Result:='mmCP_DEBUG'; + mmCP_PQ_WPTR_POLL_CNTL :Result:='mmCP_PQ_WPTR_POLL_CNTL'; + mmCP_PQ_WPTR_POLL_CNTL1 :Result:='mmCP_PQ_WPTR_POLL_CNTL1'; + mmCP_ME1_PIPE0_INT_CNTL :Result:='mmCP_ME1_PIPE0_INT_CNTL'; + mmCP_ME1_PIPE1_INT_CNTL :Result:='mmCP_ME1_PIPE1_INT_CNTL'; + mmCP_ME1_PIPE2_INT_CNTL :Result:='mmCP_ME1_PIPE2_INT_CNTL'; + mmCP_ME1_PIPE3_INT_CNTL :Result:='mmCP_ME1_PIPE3_INT_CNTL'; + mmCP_ME2_PIPE0_INT_CNTL :Result:='mmCP_ME2_PIPE0_INT_CNTL'; + mmCP_ME2_PIPE1_INT_CNTL :Result:='mmCP_ME2_PIPE1_INT_CNTL'; + mmCP_ME2_PIPE2_INT_CNTL :Result:='mmCP_ME2_PIPE2_INT_CNTL'; + mmCP_ME2_PIPE3_INT_CNTL :Result:='mmCP_ME2_PIPE3_INT_CNTL'; + mmCP_ME1_PIPE0_INT_STATUS :Result:='mmCP_ME1_PIPE0_INT_STATUS'; + mmCP_ME1_PIPE1_INT_STATUS :Result:='mmCP_ME1_PIPE1_INT_STATUS'; + mmCP_ME1_PIPE2_INT_STATUS :Result:='mmCP_ME1_PIPE2_INT_STATUS'; + mmCP_ME1_PIPE3_INT_STATUS :Result:='mmCP_ME1_PIPE3_INT_STATUS'; + mmCP_ME2_PIPE0_INT_STATUS :Result:='mmCP_ME2_PIPE0_INT_STATUS'; + mmCP_ME2_PIPE1_INT_STATUS :Result:='mmCP_ME2_PIPE1_INT_STATUS'; + mmCP_ME2_PIPE2_INT_STATUS :Result:='mmCP_ME2_PIPE2_INT_STATUS'; + mmCP_ME2_PIPE3_INT_STATUS :Result:='mmCP_ME2_PIPE3_INT_STATUS'; + mmCP_ME1_INT_STAT_DEBUG :Result:='mmCP_ME1_INT_STAT_DEBUG'; + mmCP_ME2_INT_STAT_DEBUG :Result:='mmCP_ME2_INT_STAT_DEBUG'; + mmCC_GC_EDC_CONFIG :Result:='mmCC_GC_EDC_CONFIG'; + mmCP_ME1_PIPE_PRIORITY_CNTS :Result:='mmCP_ME1_PIPE_PRIORITY_CNTS'; + mmCP_ME1_PIPE0_PRIORITY :Result:='mmCP_ME1_PIPE0_PRIORITY'; + mmCP_ME1_PIPE1_PRIORITY :Result:='mmCP_ME1_PIPE1_PRIORITY'; + mmCP_ME1_PIPE2_PRIORITY :Result:='mmCP_ME1_PIPE2_PRIORITY'; + mmCP_ME1_PIPE3_PRIORITY :Result:='mmCP_ME1_PIPE3_PRIORITY'; + mmCP_ME2_PIPE_PRIORITY_CNTS :Result:='mmCP_ME2_PIPE_PRIORITY_CNTS'; + mmCP_ME2_PIPE0_PRIORITY :Result:='mmCP_ME2_PIPE0_PRIORITY'; + mmCP_ME2_PIPE1_PRIORITY :Result:='mmCP_ME2_PIPE1_PRIORITY'; + mmCP_ME2_PIPE2_PRIORITY :Result:='mmCP_ME2_PIPE2_PRIORITY'; + mmCP_ME2_PIPE3_PRIORITY :Result:='mmCP_ME2_PIPE3_PRIORITY'; + mmCP_CE_PRGRM_CNTR_START :Result:='mmCP_CE_PRGRM_CNTR_START'; + mmCP_PFP_PRGRM_CNTR_START :Result:='mmCP_PFP_PRGRM_CNTR_START'; + mmCP_ME_PRGRM_CNTR_START :Result:='mmCP_ME_PRGRM_CNTR_START'; + mmCP_MEC1_PRGRM_CNTR_START :Result:='mmCP_MEC1_PRGRM_CNTR_START'; + mmCP_MEC2_PRGRM_CNTR_START :Result:='mmCP_MEC2_PRGRM_CNTR_START'; + mmCP_CE_INTR_ROUTINE_START :Result:='mmCP_CE_INTR_ROUTINE_START'; + mmCP_PFP_INTR_ROUTINE_START :Result:='mmCP_PFP_INTR_ROUTINE_START'; + mmCP_ME_INTR_ROUTINE_START :Result:='mmCP_ME_INTR_ROUTINE_START'; + mmCP_MEC1_INTR_ROUTINE_START :Result:='mmCP_MEC1_INTR_ROUTINE_START'; + mmCP_MEC2_INTR_ROUTINE_START :Result:='mmCP_MEC2_INTR_ROUTINE_START'; + mmCP_CONTEXT_CNTL :Result:='mmCP_CONTEXT_CNTL'; + mmCP_MAX_CONTEXT :Result:='mmCP_MAX_CONTEXT'; + mmCP_IQ_WAIT_TIME1 :Result:='mmCP_IQ_WAIT_TIME1'; + mmCP_IQ_WAIT_TIME2 :Result:='mmCP_IQ_WAIT_TIME2'; + mmCP_RB0_BASE_HI :Result:='mmCP_RB0_BASE_HI'; + mmCP_RB1_BASE_HI :Result:='mmCP_RB1_BASE_HI'; + mmCP_VMID_RESET :Result:='mmCP_VMID_RESET'; + mmCPC_INT_CNTL :Result:='mmCPC_INT_CNTL'; + mmCPC_INT_STATUS :Result:='mmCPC_INT_STATUS'; + mmCP_VMID_PREEMPT :Result:='mmCP_VMID_PREEMPT'; + mmCPC_INT_CNTX_ID :Result:='mmCPC_INT_CNTX_ID'; + mmCP_PQ_STATUS :Result:='mmCP_PQ_STATUS'; + mmCP_CPC_IC_BASE_LO :Result:='mmCP_CPC_IC_BASE_LO'; + mmCP_CPC_IC_BASE_HI :Result:='mmCP_CPC_IC_BASE_HI'; + mmCP_CPC_IC_BASE_CNTL :Result:='mmCP_CPC_IC_BASE_CNTL'; + mmCP_CPC_IC_OP_CNTL :Result:='mmCP_CPC_IC_OP_CNTL'; + mmCP_MEC1_F32_INT_DIS :Result:='mmCP_MEC1_F32_INT_DIS'; + mmCP_MEC2_F32_INT_DIS :Result:='mmCP_MEC2_F32_INT_DIS'; + mmCP_VMID_STATUS :Result:='mmCP_VMID_STATUS'; + mmRLC_LB_CNTL :Result:='mmRLC_LB_CNTL'; + mmRLC_SAVE_AND_RESTORE_BASE :Result:='mmRLC_SAVE_AND_RESTORE_BASE'; + mmRLC_LB_CNTR_MAX :Result:='mmRLC_LB_CNTR_MAX'; + mmRLC_LB_CNTR_INIT :Result:='mmRLC_LB_CNTR_INIT'; + mmRLC_DRIVER_CPDMA_STATUS :Result:='mmRLC_DRIVER_CPDMA_STATUS'; + mmRLC_DEBUG_SELECT :Result:='mmRLC_DEBUG_SELECT'; + mmRLC_DEBUG :Result:='mmRLC_DEBUG'; + mmRLC_GPU_CLOCK_COUNT_LSB :Result:='mmRLC_GPU_CLOCK_COUNT_LSB'; + mmRLC_GPU_CLOCK_COUNT_MSB :Result:='mmRLC_GPU_CLOCK_COUNT_MSB'; + mmRLC_CAPTURE_GPU_CLOCK_COUNT :Result:='mmRLC_CAPTURE_GPU_CLOCK_COUNT'; + mmRLC_MC_CNTL :Result:='mmRLC_MC_CNTL'; + mmRLC_UCODE_CNTL :Result:='mmRLC_UCODE_CNTL'; + mmRLC_STAT :Result:='mmRLC_STAT'; + mmRLC_GPU_CLOCK_32_RES_SEL :Result:='mmRLC_GPU_CLOCK_32_RES_SEL'; + mmRLC_GPU_CLOCK_32 :Result:='mmRLC_GPU_CLOCK_32'; + mmRLC_SOFT_RESET_GPU :Result:='mmRLC_SOFT_RESET_GPU'; + mmRLC_PG_CNTL :Result:='mmRLC_PG_CNTL'; + mmRLC_MEM_SLP_CNTL :Result:='mmRLC_MEM_SLP_CNTL'; + mmRLC_PERFMON_CNTL :Result:='mmRLC_PERFMON_CNTL'; + mmRLC_PERFCOUNTER0_SELECT :Result:='mmRLC_PERFCOUNTER0_SELECT'; + mmRLC_PERFCOUNTER1_SELECT :Result:='mmRLC_PERFCOUNTER1_SELECT'; + mmCGTT_RLC_CLK_CTRL :Result:='mmCGTT_RLC_CLK_CTRL'; + mmRLC_LOAD_BALANCE_CNTR :Result:='mmRLC_LOAD_BALANCE_CNTR'; + mmRLC_CGTT_MGCG_OVERRIDE :Result:='mmRLC_CGTT_MGCG_OVERRIDE'; + mmRLC_CGCG_CGLS_CTRL :Result:='mmRLC_CGCG_CGLS_CTRL'; + mmRLC_CGCG_RAMP_CTRL :Result:='mmRLC_CGCG_RAMP_CTRL'; + mmRLC_DYN_PG_STATUS :Result:='mmRLC_DYN_PG_STATUS'; + mmRLC_DYN_PG_REQUEST :Result:='mmRLC_DYN_PG_REQUEST'; + mmRLC_CU_STATUS :Result:='mmRLC_CU_STATUS'; + mmRLC_LB_INIT_CU_MASK :Result:='mmRLC_LB_INIT_CU_MASK'; + mmRLC_LB_ALWAYS_ACTIVE_CU_MASK :Result:='mmRLC_LB_ALWAYS_ACTIVE_CU_MASK'; + mmRLC_LB_PARAMS :Result:='mmRLC_LB_PARAMS'; + mmRLC_THREAD1_DELAY :Result:='mmRLC_THREAD1_DELAY'; + mmRLC_PG_ALWAYS_ON_CU_MASK :Result:='mmRLC_PG_ALWAYS_ON_CU_MASK'; + mmRLC_MAX_PG_CU :Result:='mmRLC_MAX_PG_CU'; + mmRLC_AUTO_PG_CTRL :Result:='mmRLC_AUTO_PG_CTRL'; + mmRLC_SMU_GRBM_REG_SAVE_CTRL :Result:='mmRLC_SMU_GRBM_REG_SAVE_CTRL'; + mmRLC_SMU_PG_CTRL :Result:='mmRLC_SMU_PG_CTRL'; + mmRLC_SMU_PG_WAKE_UP_CTRL :Result:='mmRLC_SMU_PG_WAKE_UP_CTRL'; + mmRLC_SERDES_RD_MASTER_INDEX :Result:='mmRLC_SERDES_RD_MASTER_INDEX'; + mmRLC_SERDES_RD_DATA_0 :Result:='mmRLC_SERDES_RD_DATA_0'; + mmRLC_SERDES_RD_DATA_1 :Result:='mmRLC_SERDES_RD_DATA_1'; + mmRLC_SERDES_RD_DATA_2 :Result:='mmRLC_SERDES_RD_DATA_2'; + mmRLC_SERDES_WR_CTRL :Result:='mmRLC_SERDES_WR_CTRL'; + mmRLC_SERDES_WR_DATA :Result:='mmRLC_SERDES_WR_DATA'; + mmSPI_ARB_PRIORITY :Result:='mmSPI_ARB_PRIORITY'; + mmSPI_ARB_CYCLES_0 :Result:='mmSPI_ARB_CYCLES_0'; + mmSPI_ARB_CYCLES_1 :Result:='mmSPI_ARB_CYCLES_1'; + mmSPI_CDBG_SYS_GFX :Result:='mmSPI_CDBG_SYS_GFX'; + mmSPI_CDBG_SYS_HP3D :Result:='mmSPI_CDBG_SYS_HP3D'; + mmSPI_CDBG_SYS_CS0 :Result:='mmSPI_CDBG_SYS_CS0'; + mmSPI_CDBG_SYS_CS1 :Result:='mmSPI_CDBG_SYS_CS1'; + mmSPI_WCL_PIPE_PERCENT_GFX :Result:='mmSPI_WCL_PIPE_PERCENT_GFX'; + mmSPI_WCL_PIPE_PERCENT_HP3D :Result:='mmSPI_WCL_PIPE_PERCENT_HP3D'; + mmSPI_WCL_PIPE_PERCENT_CS0 :Result:='mmSPI_WCL_PIPE_PERCENT_CS0'; + mmSPI_WCL_PIPE_PERCENT_CS1 :Result:='mmSPI_WCL_PIPE_PERCENT_CS1'; + mmSPI_WCL_PIPE_PERCENT_CS2 :Result:='mmSPI_WCL_PIPE_PERCENT_CS2'; + mmSPI_WCL_PIPE_PERCENT_CS3 :Result:='mmSPI_WCL_PIPE_PERCENT_CS3'; + mmSPI_WCL_PIPE_PERCENT_CS4 :Result:='mmSPI_WCL_PIPE_PERCENT_CS4'; + mmSPI_WCL_PIPE_PERCENT_CS5 :Result:='mmSPI_WCL_PIPE_PERCENT_CS5'; + mmSPI_WCL_PIPE_PERCENT_CS6 :Result:='mmSPI_WCL_PIPE_PERCENT_CS6'; + mmSPI_WCL_PIPE_PERCENT_CS7 :Result:='mmSPI_WCL_PIPE_PERCENT_CS7'; + mmSPI_GDBG_WAVE_CNTL :Result:='mmSPI_GDBG_WAVE_CNTL'; + mmSPI_GDBG_TRAP_CONFIG :Result:='mmSPI_GDBG_TRAP_CONFIG'; + mmSPI_GDBG_TRAP_MASK :Result:='mmSPI_GDBG_TRAP_MASK'; + mmSPI_GDBG_TBA_LO :Result:='mmSPI_GDBG_TBA_LO'; + mmSPI_GDBG_TBA_HI :Result:='mmSPI_GDBG_TBA_HI'; + mmSPI_GDBG_TMA_LO :Result:='mmSPI_GDBG_TMA_LO'; + mmSPI_GDBG_TMA_HI :Result:='mmSPI_GDBG_TMA_HI'; + mmSPI_GDBG_TRAP_DATA0 :Result:='mmSPI_GDBG_TRAP_DATA0'; + mmSPI_GDBG_TRAP_DATA1 :Result:='mmSPI_GDBG_TRAP_DATA1'; + mmSPI_RESET_DEBUG :Result:='mmSPI_RESET_DEBUG'; + mmSPI_COMPUTE_QUEUE_RESET :Result:='mmSPI_COMPUTE_QUEUE_RESET'; + mmSPI_RESOURCE_RESERVE_CU_0 :Result:='mmSPI_RESOURCE_RESERVE_CU_0'; + mmSPI_RESOURCE_RESERVE_CU_1 :Result:='mmSPI_RESOURCE_RESERVE_CU_1'; + mmSPI_RESOURCE_RESERVE_CU_2 :Result:='mmSPI_RESOURCE_RESERVE_CU_2'; + mmSPI_RESOURCE_RESERVE_CU_3 :Result:='mmSPI_RESOURCE_RESERVE_CU_3'; + mmSPI_RESOURCE_RESERVE_CU_4 :Result:='mmSPI_RESOURCE_RESERVE_CU_4'; + mmSPI_RESOURCE_RESERVE_CU_5 :Result:='mmSPI_RESOURCE_RESERVE_CU_5'; + mmSPI_RESOURCE_RESERVE_CU_6 :Result:='mmSPI_RESOURCE_RESERVE_CU_6'; + mmSPI_RESOURCE_RESERVE_CU_7 :Result:='mmSPI_RESOURCE_RESERVE_CU_7'; + mmSPI_RESOURCE_RESERVE_CU_8 :Result:='mmSPI_RESOURCE_RESERVE_CU_8'; + mmSPI_RESOURCE_RESERVE_CU_9 :Result:='mmSPI_RESOURCE_RESERVE_CU_9'; + mmSPI_RESOURCE_RESERVE_EN_CU_0 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_0'; + mmSPI_RESOURCE_RESERVE_EN_CU_1 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_1'; + mmSPI_RESOURCE_RESERVE_EN_CU_2 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_2'; + mmSPI_RESOURCE_RESERVE_EN_CU_3 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_3'; + mmSPI_RESOURCE_RESERVE_EN_CU_4 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_4'; + mmSPI_RESOURCE_RESERVE_EN_CU_5 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_5'; + mmSPI_RESOURCE_RESERVE_EN_CU_6 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_6'; + mmSPI_RESOURCE_RESERVE_EN_CU_7 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_7'; + mmSPI_RESOURCE_RESERVE_EN_CU_8 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_8'; + mmSPI_RESOURCE_RESERVE_EN_CU_9 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_9'; + mmSPI_RESOURCE_RESERVE_CU_10 :Result:='mmSPI_RESOURCE_RESERVE_CU_10'; + mmSPI_RESOURCE_RESERVE_CU_11 :Result:='mmSPI_RESOURCE_RESERVE_CU_11'; + mmSPI_RESOURCE_RESERVE_EN_CU_10 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_10'; + mmSPI_RESOURCE_RESERVE_EN_CU_11 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_11'; + mmSPI_RESOURCE_RESERVE_CU_12 :Result:='mmSPI_RESOURCE_RESERVE_CU_12'; + mmSPI_RESOURCE_RESERVE_CU_13 :Result:='mmSPI_RESOURCE_RESERVE_CU_13'; + mmSPI_RESOURCE_RESERVE_CU_14 :Result:='mmSPI_RESOURCE_RESERVE_CU_14'; + mmSPI_RESOURCE_RESERVE_CU_15 :Result:='mmSPI_RESOURCE_RESERVE_CU_15'; + mmSPI_RESOURCE_RESERVE_EN_CU_12 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_12'; + mmSPI_RESOURCE_RESERVE_EN_CU_13 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_13'; + mmSPI_RESOURCE_RESERVE_EN_CU_14 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_14'; + mmSPI_RESOURCE_RESERVE_EN_CU_15 :Result:='mmSPI_RESOURCE_RESERVE_EN_CU_15'; + mmSPI_COMPUTE_WF_CTX_SAVE :Result:='mmSPI_COMPUTE_WF_CTX_SAVE'; + mmCP_HPD_ROQ_OFFSETS :Result:='mmCP_HPD_ROQ_OFFSETS'; + mmCP_HPD_STATUS0 :Result:='mmCP_HPD_STATUS0'; + mmCP_MQD_BASE_ADDR :Result:='mmCP_MQD_BASE_ADDR'; + mmCP_MQD_BASE_ADDR_HI :Result:='mmCP_MQD_BASE_ADDR_HI'; + mmCP_HQD_ACTIVE :Result:='mmCP_HQD_ACTIVE'; + mmCP_HQD_VMID :Result:='mmCP_HQD_VMID'; + mmCP_HQD_PERSISTENT_STATE :Result:='mmCP_HQD_PERSISTENT_STATE'; + mmCP_HQD_PIPE_PRIORITY :Result:='mmCP_HQD_PIPE_PRIORITY'; + mmCP_HQD_QUEUE_PRIORITY :Result:='mmCP_HQD_QUEUE_PRIORITY'; + mmCP_HQD_QUANTUM :Result:='mmCP_HQD_QUANTUM'; + mmCP_HQD_PQ_BASE :Result:='mmCP_HQD_PQ_BASE'; + mmCP_HQD_PQ_BASE_HI :Result:='mmCP_HQD_PQ_BASE_HI'; + mmCP_HQD_PQ_RPTR :Result:='mmCP_HQD_PQ_RPTR'; + mmCP_HQD_PQ_RPTR_REPORT_ADDR :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR'; + mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI :Result:='mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI'; + mmCP_HQD_PQ_WPTR_POLL_ADDR :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR'; + mmCP_HQD_PQ_WPTR_POLL_ADDR_HI :Result:='mmCP_HQD_PQ_WPTR_POLL_ADDR_HI'; + mmCP_HQD_PQ_DOORBELL_CONTROL :Result:='mmCP_HQD_PQ_DOORBELL_CONTROL'; + mmCP_HQD_PQ_WPTR :Result:='mmCP_HQD_PQ_WPTR'; + mmCP_HQD_PQ_CONTROL :Result:='mmCP_HQD_PQ_CONTROL'; + mmCP_HQD_IB_BASE_ADDR :Result:='mmCP_HQD_IB_BASE_ADDR'; + mmCP_HQD_IB_BASE_ADDR_HI :Result:='mmCP_HQD_IB_BASE_ADDR_HI'; + mmCP_HQD_IB_RPTR :Result:='mmCP_HQD_IB_RPTR'; + mmCP_HQD_IB_CONTROL :Result:='mmCP_HQD_IB_CONTROL'; + mmCP_HQD_IQ_TIMER :Result:='mmCP_HQD_IQ_TIMER'; + mmCP_HQD_IQ_RPTR :Result:='mmCP_HQD_IQ_RPTR'; + mmCP_HQD_DEQUEUE_REQUEST :Result:='mmCP_HQD_DEQUEUE_REQUEST'; + mmCP_HQD_DMA_OFFLOAD :Result:='mmCP_HQD_DMA_OFFLOAD'; + mmCP_HQD_SEMA_CMD :Result:='mmCP_HQD_SEMA_CMD'; + mmCP_HQD_MSG_TYPE :Result:='mmCP_HQD_MSG_TYPE'; + mmCP_HQD_ATOMIC0_PREOP_LO :Result:='mmCP_HQD_ATOMIC0_PREOP_LO'; + mmCP_HQD_ATOMIC0_PREOP_HI :Result:='mmCP_HQD_ATOMIC0_PREOP_HI'; + mmCP_HQD_ATOMIC1_PREOP_LO :Result:='mmCP_HQD_ATOMIC1_PREOP_LO'; + mmCP_HQD_ATOMIC1_PREOP_HI :Result:='mmCP_HQD_ATOMIC1_PREOP_HI'; + mmCP_HQD_HQ_SCHEDULER0 :Result:='mmCP_HQD_HQ_SCHEDULER0'; + mmCP_HQD_HQ_SCHEDULER1 :Result:='mmCP_HQD_HQ_SCHEDULER1'; + mmCP_MQD_CONTROL :Result:='mmCP_MQD_CONTROL'; + mmCP_HQD_HQ_STATUS1 :Result:='mmCP_HQD_HQ_STATUS1'; + mmCP_HQD_HQ_CONTROL1 :Result:='mmCP_HQD_HQ_CONTROL1'; + mmCP_HQD_EOP_BASE_ADDR :Result:='mmCP_HQD_EOP_BASE_ADDR'; + mmCP_HQD_EOP_BASE_ADDR_HI :Result:='mmCP_HQD_EOP_BASE_ADDR_HI'; + mmCP_HQD_EOP_CONTROL :Result:='mmCP_HQD_EOP_CONTROL'; + mmCP_HQD_EOP_RPTR :Result:='mmCP_HQD_EOP_RPTR'; + mmCP_HQD_EOP_WPTR :Result:='mmCP_HQD_EOP_WPTR'; + mmCP_HQD_EOP_EVENTS :Result:='mmCP_HQD_EOP_EVENTS'; + mmCP_HQD_CTX_SAVE_BASE_ADDR_LO :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_LO'; + mmCP_HQD_CTX_SAVE_BASE_ADDR_HI :Result:='mmCP_HQD_CTX_SAVE_BASE_ADDR_HI'; + mmCP_HQD_CTX_SAVE_CONTROL :Result:='mmCP_HQD_CTX_SAVE_CONTROL'; + mmCP_HQD_CNTL_STACK_OFFSET :Result:='mmCP_HQD_CNTL_STACK_OFFSET'; + mmCP_HQD_CNTL_STACK_SIZE :Result:='mmCP_HQD_CNTL_STACK_SIZE'; + mmCP_HQD_WG_STATE_OFFSET :Result:='mmCP_HQD_WG_STATE_OFFSET'; + mmCP_HQD_CTX_SAVE_SIZE :Result:='mmCP_HQD_CTX_SAVE_SIZE'; + mmCP_HQD_GDS_RESOURCE_STATE :Result:='mmCP_HQD_GDS_RESOURCE_STATE'; + mmCP_HQD_ERROR :Result:='mmCP_HQD_ERROR'; + mmCP_HQD_EOP_WPTR_MEM :Result:='mmCP_HQD_EOP_WPTR_MEM'; + mmCP_HQD_EOP_DONES :Result:='mmCP_HQD_EOP_DONES'; + mmDIDT_IND_INDEX :Result:='mmDIDT_IND_INDEX'; + mmDIDT_IND_DATA :Result:='mmDIDT_IND_DATA'; + mmGC_CAC_CGTT_CLK_CTRL :Result:='mmGC_CAC_CGTT_CLK_CTRL'; + mmSE_CAC_CGTT_CLK_CTRL :Result:='mmSE_CAC_CGTT_CLK_CTRL'; + mmGC_CAC_LKG_AGGR_LOWER :Result:='mmGC_CAC_LKG_AGGR_LOWER'; + mmGC_CAC_LKG_AGGR_UPPER :Result:='mmGC_CAC_LKG_AGGR_UPPER'; + mmTCP_WATCH0_ADDR_H :Result:='mmTCP_WATCH0_ADDR_H'; + mmTCP_WATCH0_ADDR_L :Result:='mmTCP_WATCH0_ADDR_L'; + mmTCP_WATCH0_CNTL :Result:='mmTCP_WATCH0_CNTL'; + mmTCP_WATCH1_ADDR_H :Result:='mmTCP_WATCH1_ADDR_H'; + mmTCP_WATCH1_ADDR_L :Result:='mmTCP_WATCH1_ADDR_L'; + mmTCP_WATCH1_CNTL :Result:='mmTCP_WATCH1_CNTL'; + mmTCP_WATCH2_ADDR_H :Result:='mmTCP_WATCH2_ADDR_H'; + mmTCP_WATCH2_ADDR_L :Result:='mmTCP_WATCH2_ADDR_L'; + mmTCP_WATCH2_CNTL :Result:='mmTCP_WATCH2_CNTL'; + mmTCP_WATCH3_ADDR_H :Result:='mmTCP_WATCH3_ADDR_H'; + mmTCP_WATCH3_ADDR_L :Result:='mmTCP_WATCH3_ADDR_L'; + mmTCP_WATCH3_CNTL :Result:='mmTCP_WATCH3_CNTL'; + mmTCP_GATCL1_CNTL :Result:='mmTCP_GATCL1_CNTL'; + mmTCP_ATC_EDC_GATCL1_CNT :Result:='mmTCP_ATC_EDC_GATCL1_CNT'; + mmTCP_GATCL1_DSM_CNTL :Result:='mmTCP_GATCL1_DSM_CNTL'; + mmTCP_DSM_CNTL :Result:='mmTCP_DSM_CNTL'; + mmTCP_CNTL2 :Result:='mmTCP_CNTL2'; + mmGDS_VMID0_BASE :Result:='mmGDS_VMID0_BASE'; + mmGDS_VMID0_SIZE :Result:='mmGDS_VMID0_SIZE'; + mmGDS_VMID1_BASE :Result:='mmGDS_VMID1_BASE'; + mmGDS_VMID1_SIZE :Result:='mmGDS_VMID1_SIZE'; + mmGDS_VMID2_BASE :Result:='mmGDS_VMID2_BASE'; + mmGDS_VMID2_SIZE :Result:='mmGDS_VMID2_SIZE'; + mmGDS_VMID3_BASE :Result:='mmGDS_VMID3_BASE'; + mmGDS_VMID3_SIZE :Result:='mmGDS_VMID3_SIZE'; + mmGDS_VMID4_BASE :Result:='mmGDS_VMID4_BASE'; + mmGDS_VMID4_SIZE :Result:='mmGDS_VMID4_SIZE'; + mmGDS_VMID5_BASE :Result:='mmGDS_VMID5_BASE'; + mmGDS_VMID5_SIZE :Result:='mmGDS_VMID5_SIZE'; + mmGDS_VMID6_BASE :Result:='mmGDS_VMID6_BASE'; + mmGDS_VMID6_SIZE :Result:='mmGDS_VMID6_SIZE'; + mmGDS_VMID7_BASE :Result:='mmGDS_VMID7_BASE'; + mmGDS_VMID7_SIZE :Result:='mmGDS_VMID7_SIZE'; + mmGDS_VMID8_BASE :Result:='mmGDS_VMID8_BASE'; + mmGDS_VMID8_SIZE :Result:='mmGDS_VMID8_SIZE'; + mmGDS_VMID9_BASE :Result:='mmGDS_VMID9_BASE'; + mmGDS_VMID9_SIZE :Result:='mmGDS_VMID9_SIZE'; + mmGDS_VMID10_BASE :Result:='mmGDS_VMID10_BASE'; + mmGDS_VMID10_SIZE :Result:='mmGDS_VMID10_SIZE'; + mmGDS_VMID11_BASE :Result:='mmGDS_VMID11_BASE'; + mmGDS_VMID11_SIZE :Result:='mmGDS_VMID11_SIZE'; + mmGDS_VMID12_BASE :Result:='mmGDS_VMID12_BASE'; + mmGDS_VMID12_SIZE :Result:='mmGDS_VMID12_SIZE'; + mmGDS_VMID13_BASE :Result:='mmGDS_VMID13_BASE'; + mmGDS_VMID13_SIZE :Result:='mmGDS_VMID13_SIZE'; + mmGDS_VMID14_BASE :Result:='mmGDS_VMID14_BASE'; + mmGDS_VMID14_SIZE :Result:='mmGDS_VMID14_SIZE'; + mmGDS_VMID15_BASE :Result:='mmGDS_VMID15_BASE'; + mmGDS_VMID15_SIZE :Result:='mmGDS_VMID15_SIZE'; + mmGDS_GWS_VMID0 :Result:='mmGDS_GWS_VMID0'; + mmGDS_GWS_VMID1 :Result:='mmGDS_GWS_VMID1'; + mmGDS_GWS_VMID2 :Result:='mmGDS_GWS_VMID2'; + mmGDS_GWS_VMID3 :Result:='mmGDS_GWS_VMID3'; + mmGDS_GWS_VMID4 :Result:='mmGDS_GWS_VMID4'; + mmGDS_GWS_VMID5 :Result:='mmGDS_GWS_VMID5'; + mmGDS_GWS_VMID6 :Result:='mmGDS_GWS_VMID6'; + mmGDS_GWS_VMID7 :Result:='mmGDS_GWS_VMID7'; + mmGDS_GWS_VMID8 :Result:='mmGDS_GWS_VMID8'; + mmGDS_GWS_VMID9 :Result:='mmGDS_GWS_VMID9'; + mmGDS_GWS_VMID10 :Result:='mmGDS_GWS_VMID10'; + mmGDS_GWS_VMID11 :Result:='mmGDS_GWS_VMID11'; + mmGDS_GWS_VMID12 :Result:='mmGDS_GWS_VMID12'; + mmGDS_GWS_VMID13 :Result:='mmGDS_GWS_VMID13'; + mmGDS_GWS_VMID14 :Result:='mmGDS_GWS_VMID14'; + mmGDS_GWS_VMID15 :Result:='mmGDS_GWS_VMID15'; + mmGDS_OA_VMID0 :Result:='mmGDS_OA_VMID0'; + mmGDS_OA_VMID1 :Result:='mmGDS_OA_VMID1'; + mmGDS_OA_VMID2 :Result:='mmGDS_OA_VMID2'; + mmGDS_OA_VMID3 :Result:='mmGDS_OA_VMID3'; + mmGDS_OA_VMID4 :Result:='mmGDS_OA_VMID4'; + mmGDS_OA_VMID5 :Result:='mmGDS_OA_VMID5'; + mmGDS_OA_VMID6 :Result:='mmGDS_OA_VMID6'; + mmGDS_OA_VMID7 :Result:='mmGDS_OA_VMID7'; + mmGDS_OA_VMID8 :Result:='mmGDS_OA_VMID8'; + mmGDS_OA_VMID9 :Result:='mmGDS_OA_VMID9'; + mmGDS_OA_VMID10 :Result:='mmGDS_OA_VMID10'; + mmGDS_OA_VMID11 :Result:='mmGDS_OA_VMID11'; + mmGDS_OA_VMID12 :Result:='mmGDS_OA_VMID12'; + mmGDS_OA_VMID13 :Result:='mmGDS_OA_VMID13'; + mmGDS_OA_VMID14 :Result:='mmGDS_OA_VMID14'; + mmGDS_OA_VMID15 :Result:='mmGDS_OA_VMID15'; + mmGDS_GWS_RESET0 :Result:='mmGDS_GWS_RESET0'; + mmGDS_GWS_RESET1 :Result:='mmGDS_GWS_RESET1'; + mmGDS_GWS_RESOURCE_RESET :Result:='mmGDS_GWS_RESOURCE_RESET'; + mmGDS_COMPUTE_MAX_WAVE_ID :Result:='mmGDS_COMPUTE_MAX_WAVE_ID'; + mmGDS_OA_RESET_MASK :Result:='mmGDS_OA_RESET_MASK'; + mmGDS_OA_RESET :Result:='mmGDS_OA_RESET'; + mmGDS_ENHANCE :Result:='mmGDS_ENHANCE'; + mmGDS_OA_CGPG_RESTORE :Result:='mmGDS_OA_CGPG_RESTORE'; + mmGDS_CS_CTXSW_STATUS :Result:='mmGDS_CS_CTXSW_STATUS'; + mmGDS_CS_CTXSW_CNT0 :Result:='mmGDS_CS_CTXSW_CNT0'; + mmGDS_CS_CTXSW_CNT1 :Result:='mmGDS_CS_CTXSW_CNT1'; + mmGDS_CS_CTXSW_CNT2 :Result:='mmGDS_CS_CTXSW_CNT2'; + mmGDS_CS_CTXSW_CNT3 :Result:='mmGDS_CS_CTXSW_CNT3'; + mmGDS_GFX_CTXSW_STATUS :Result:='mmGDS_GFX_CTXSW_STATUS'; + mmGDS_VS_CTXSW_CNT0 :Result:='mmGDS_VS_CTXSW_CNT0'; + mmGDS_VS_CTXSW_CNT1 :Result:='mmGDS_VS_CTXSW_CNT1'; + mmGDS_VS_CTXSW_CNT2 :Result:='mmGDS_VS_CTXSW_CNT2'; + mmGDS_VS_CTXSW_CNT3 :Result:='mmGDS_VS_CTXSW_CNT3'; + mmGDS_PS0_CTXSW_CNT0 :Result:='mmGDS_PS0_CTXSW_CNT0'; + mmGDS_PS0_CTXSW_CNT1 :Result:='mmGDS_PS0_CTXSW_CNT1'; + mmGDS_PS0_CTXSW_CNT2 :Result:='mmGDS_PS0_CTXSW_CNT2'; + mmGDS_PS0_CTXSW_CNT3 :Result:='mmGDS_PS0_CTXSW_CNT3'; + mmGDS_PS1_CTXSW_CNT0 :Result:='mmGDS_PS1_CTXSW_CNT0'; + mmGDS_PS1_CTXSW_CNT1 :Result:='mmGDS_PS1_CTXSW_CNT1'; + mmGDS_PS1_CTXSW_CNT2 :Result:='mmGDS_PS1_CTXSW_CNT2'; + mmGDS_PS1_CTXSW_CNT3 :Result:='mmGDS_PS1_CTXSW_CNT3'; + mmGDS_PS2_CTXSW_CNT0 :Result:='mmGDS_PS2_CTXSW_CNT0'; + mmGDS_PS2_CTXSW_CNT1 :Result:='mmGDS_PS2_CTXSW_CNT1'; + mmGDS_PS2_CTXSW_CNT2 :Result:='mmGDS_PS2_CTXSW_CNT2'; + mmGDS_PS2_CTXSW_CNT3 :Result:='mmGDS_PS2_CTXSW_CNT3'; + mmGDS_PS3_CTXSW_CNT0 :Result:='mmGDS_PS3_CTXSW_CNT0'; + mmGDS_PS3_CTXSW_CNT1 :Result:='mmGDS_PS3_CTXSW_CNT1'; + mmGDS_PS3_CTXSW_CNT2 :Result:='mmGDS_PS3_CTXSW_CNT2'; + mmGDS_PS3_CTXSW_CNT3 :Result:='mmGDS_PS3_CTXSW_CNT3'; + mmGDS_PS4_CTXSW_CNT0 :Result:='mmGDS_PS4_CTXSW_CNT0'; + mmGDS_PS4_CTXSW_CNT1 :Result:='mmGDS_PS4_CTXSW_CNT1'; + mmGDS_PS4_CTXSW_CNT2 :Result:='mmGDS_PS4_CTXSW_CNT2'; + mmGDS_PS4_CTXSW_CNT3 :Result:='mmGDS_PS4_CTXSW_CNT3'; + mmGDS_PS5_CTXSW_CNT0 :Result:='mmGDS_PS5_CTXSW_CNT0'; + mmGDS_PS5_CTXSW_CNT1 :Result:='mmGDS_PS5_CTXSW_CNT1'; + mmGDS_PS5_CTXSW_CNT2 :Result:='mmGDS_PS5_CTXSW_CNT2'; + mmGDS_PS5_CTXSW_CNT3 :Result:='mmGDS_PS5_CTXSW_CNT3'; + mmGDS_PS6_CTXSW_CNT0 :Result:='mmGDS_PS6_CTXSW_CNT0'; + mmGDS_PS6_CTXSW_CNT1 :Result:='mmGDS_PS6_CTXSW_CNT1'; + mmGDS_PS6_CTXSW_CNT2 :Result:='mmGDS_PS6_CTXSW_CNT2'; + mmGDS_PS6_CTXSW_CNT3 :Result:='mmGDS_PS6_CTXSW_CNT3'; + mmGDS_PS7_CTXSW_CNT0 :Result:='mmGDS_PS7_CTXSW_CNT0'; + mmGDS_PS7_CTXSW_CNT1 :Result:='mmGDS_PS7_CTXSW_CNT1'; + mmGDS_PS7_CTXSW_CNT2 :Result:='mmGDS_PS7_CTXSW_CNT2'; + mmGDS_PS7_CTXSW_CNT3 :Result:='mmGDS_PS7_CTXSW_CNT3'; + mmRAS_SIGNATURE_CONTROL :Result:='mmRAS_SIGNATURE_CONTROL'; + mmRAS_SIGNATURE_MASK :Result:='mmRAS_SIGNATURE_MASK'; + mmRAS_SX_SIGNATURE0 :Result:='mmRAS_SX_SIGNATURE0'; + mmRAS_SX_SIGNATURE1 :Result:='mmRAS_SX_SIGNATURE1'; + mmRAS_SX_SIGNATURE2 :Result:='mmRAS_SX_SIGNATURE2'; + mmRAS_SX_SIGNATURE3 :Result:='mmRAS_SX_SIGNATURE3'; + mmRAS_DB_SIGNATURE0 :Result:='mmRAS_DB_SIGNATURE0'; + mmRAS_PA_SIGNATURE0 :Result:='mmRAS_PA_SIGNATURE0'; + mmRAS_VGT_SIGNATURE0 :Result:='mmRAS_VGT_SIGNATURE0'; + mmRAS_SQ_SIGNATURE0 :Result:='mmRAS_SQ_SIGNATURE0'; + mmRAS_SC_SIGNATURE0 :Result:='mmRAS_SC_SIGNATURE0'; + mmRAS_SC_SIGNATURE1 :Result:='mmRAS_SC_SIGNATURE1'; + mmRAS_SC_SIGNATURE2 :Result:='mmRAS_SC_SIGNATURE2'; + mmRAS_SC_SIGNATURE3 :Result:='mmRAS_SC_SIGNATURE3'; + mmRAS_SC_SIGNATURE4 :Result:='mmRAS_SC_SIGNATURE4'; + mmRAS_SC_SIGNATURE5 :Result:='mmRAS_SC_SIGNATURE5'; + mmRAS_SC_SIGNATURE6 :Result:='mmRAS_SC_SIGNATURE6'; + mmRAS_SC_SIGNATURE7 :Result:='mmRAS_SC_SIGNATURE7'; + mmRAS_IA_SIGNATURE0 :Result:='mmRAS_IA_SIGNATURE0'; + mmRAS_IA_SIGNATURE1 :Result:='mmRAS_IA_SIGNATURE1'; + mmRAS_SPI_SIGNATURE0 :Result:='mmRAS_SPI_SIGNATURE0'; + mmRAS_SPI_SIGNATURE1 :Result:='mmRAS_SPI_SIGNATURE1'; + mmRAS_TA_SIGNATURE0 :Result:='mmRAS_TA_SIGNATURE0'; + mmRAS_TD_SIGNATURE0 :Result:='mmRAS_TD_SIGNATURE0'; + mmRAS_CB_SIGNATURE0 :Result:='mmRAS_CB_SIGNATURE0'; + mmRAS_BCI_SIGNATURE0 :Result:='mmRAS_BCI_SIGNATURE0'; + mmRAS_BCI_SIGNATURE1 :Result:='mmRAS_BCI_SIGNATURE1'; + mmRAS_TA_SIGNATURE1 :Result:='mmRAS_TA_SIGNATURE1'; + mmSDMA0_UCODE_ADDR :Result:='mmSDMA0_UCODE_ADDR'; + mmSDMA0_UCODE_DATA :Result:='mmSDMA0_UCODE_DATA'; + mmSDMA0_POWER_CNTL :Result:='mmSDMA0_POWER_CNTL'; + mmSDMA0_CLK_CTRL :Result:='mmSDMA0_CLK_CTRL'; + mmSDMA0_CNTL :Result:='mmSDMA0_CNTL'; + mmSDMA0_CHICKEN_BITS :Result:='mmSDMA0_CHICKEN_BITS'; + mmSDMA0_TILING_CONFIG :Result:='mmSDMA0_TILING_CONFIG'; + mmSDMA0_HASH :Result:='mmSDMA0_HASH'; + mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL :Result:='mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL'; + mmSDMA0_RB_RPTR_FETCH :Result:='mmSDMA0_RB_RPTR_FETCH'; + mmSDMA0_IB_OFFSET_FETCH :Result:='mmSDMA0_IB_OFFSET_FETCH'; + mmSDMA0_PROGRAM :Result:='mmSDMA0_PROGRAM'; + mmSDMA0_STATUS_REG :Result:='mmSDMA0_STATUS_REG'; + mmSDMA0_STATUS1_REG :Result:='mmSDMA0_STATUS1_REG'; + mmSDMA0_RD_BURST_CNTL :Result:='mmSDMA0_RD_BURST_CNTL'; + mmSDMA0_F32_CNTL :Result:='mmSDMA0_F32_CNTL'; + mmSDMA0_FREEZE :Result:='mmSDMA0_FREEZE'; + mmSDMA0_PHASE0_QUANTUM :Result:='mmSDMA0_PHASE0_QUANTUM'; + mmSDMA0_PHASE1_QUANTUM :Result:='mmSDMA0_PHASE1_QUANTUM'; + mmSDMA_POWER_GATING :Result:='mmSDMA_POWER_GATING'; + mmSDMA_PGFSM_CONFIG :Result:='mmSDMA_PGFSM_CONFIG'; + mmSDMA_PGFSM_WRITE :Result:='mmSDMA_PGFSM_WRITE'; + mmSDMA_PGFSM_READ :Result:='mmSDMA_PGFSM_READ'; + mmSDMA0_EDC_CONFIG :Result:='mmSDMA0_EDC_CONFIG'; + mmSDMA0_VM_CNTL :Result:='mmSDMA0_VM_CNTL'; + mmSDMA0_VM_CTX_LO :Result:='mmSDMA0_VM_CTX_LO'; + mmSDMA0_VM_CTX_HI :Result:='mmSDMA0_VM_CTX_HI'; + mmSDMA0_STATUS2_REG :Result:='mmSDMA0_STATUS2_REG'; + mmSDMA0_ACTIVE_FCN_ID :Result:='mmSDMA0_ACTIVE_FCN_ID'; + mmSDMA0_VM_CTX_CNTL :Result:='mmSDMA0_VM_CTX_CNTL'; + mmSDMA0_VIRT_RESET_REQ :Result:='mmSDMA0_VIRT_RESET_REQ'; + mmSDMA0_VF_ENABLE :Result:='mmSDMA0_VF_ENABLE'; + mmSDMA0_BA_THRESHOLD :Result:='mmSDMA0_BA_THRESHOLD'; + mmSDMA0_ID :Result:='mmSDMA0_ID'; + mmSDMA0_VERSION :Result:='mmSDMA0_VERSION'; + mmSDMA0_ATOMIC_CNTL :Result:='mmSDMA0_ATOMIC_CNTL'; + mmSDMA0_ATOMIC_PREOP_LO :Result:='mmSDMA0_ATOMIC_PREOP_LO'; + mmSDMA0_ATOMIC_PREOP_HI :Result:='mmSDMA0_ATOMIC_PREOP_HI'; + mmSDMA0_PERF_REG_TYPE0 :Result:='mmSDMA0_PERF_REG_TYPE0'; + mmSDMA0_CONTEXT_REG_TYPE0 :Result:='mmSDMA0_CONTEXT_REG_TYPE0'; + mmSDMA0_CONTEXT_REG_TYPE1 :Result:='mmSDMA0_CONTEXT_REG_TYPE1'; + mmSDMA0_CONTEXT_REG_TYPE2 :Result:='mmSDMA0_CONTEXT_REG_TYPE2'; + mmSDMA0_PUB_REG_TYPE0 :Result:='mmSDMA0_PUB_REG_TYPE0'; + mmSDMA0_PUB_REG_TYPE1 :Result:='mmSDMA0_PUB_REG_TYPE1'; + mmSDMA0_GFX_RB_CNTL :Result:='mmSDMA0_GFX_RB_CNTL'; + mmSDMA0_GFX_RB_BASE :Result:='mmSDMA0_GFX_RB_BASE'; + mmSDMA0_GFX_RB_BASE_HI :Result:='mmSDMA0_GFX_RB_BASE_HI'; + mmSDMA0_GFX_RB_RPTR :Result:='mmSDMA0_GFX_RB_RPTR'; + mmSDMA0_GFX_RB_WPTR :Result:='mmSDMA0_GFX_RB_WPTR'; + mmSDMA0_GFX_RB_WPTR_POLL_CNTL :Result:='mmSDMA0_GFX_RB_WPTR_POLL_CNTL'; + mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI'; + mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO'; + mmSDMA0_GFX_RB_RPTR_ADDR_HI :Result:='mmSDMA0_GFX_RB_RPTR_ADDR_HI'; + mmSDMA0_GFX_RB_RPTR_ADDR_LO :Result:='mmSDMA0_GFX_RB_RPTR_ADDR_LO'; + mmSDMA0_GFX_IB_CNTL :Result:='mmSDMA0_GFX_IB_CNTL'; + mmSDMA0_GFX_IB_RPTR :Result:='mmSDMA0_GFX_IB_RPTR'; + mmSDMA0_GFX_IB_OFFSET :Result:='mmSDMA0_GFX_IB_OFFSET'; + mmSDMA0_GFX_IB_BASE_LO :Result:='mmSDMA0_GFX_IB_BASE_LO'; + mmSDMA0_GFX_IB_BASE_HI :Result:='mmSDMA0_GFX_IB_BASE_HI'; + mmSDMA0_GFX_IB_SIZE :Result:='mmSDMA0_GFX_IB_SIZE'; + mmSDMA0_GFX_SKIP_CNTL :Result:='mmSDMA0_GFX_SKIP_CNTL'; + mmSDMA0_GFX_CONTEXT_STATUS :Result:='mmSDMA0_GFX_CONTEXT_STATUS'; + mmSDMA0_GFX_DOORBELL :Result:='mmSDMA0_GFX_DOORBELL'; + mmSDMA0_GFX_CONTEXT_CNTL :Result:='mmSDMA0_GFX_CONTEXT_CNTL'; + mmSDMA0_GFX_VIRTUAL_ADDR :Result:='mmSDMA0_GFX_VIRTUAL_ADDR'; + mmSDMA0_GFX_APE1_CNTL :Result:='mmSDMA0_GFX_APE1_CNTL'; + mmSDMA0_GFX_DOORBELL_LOG :Result:='mmSDMA0_GFX_DOORBELL_LOG'; + mmSDMA0_GFX_WATERMARK :Result:='mmSDMA0_GFX_WATERMARK'; + mmSDMA0_GFX_CSA_ADDR_LO :Result:='mmSDMA0_GFX_CSA_ADDR_LO'; + mmSDMA0_GFX_CSA_ADDR_HI :Result:='mmSDMA0_GFX_CSA_ADDR_HI'; + mmSDMA0_GFX_IB_SUB_REMAIN :Result:='mmSDMA0_GFX_IB_SUB_REMAIN'; + mmSDMA0_GFX_PREEMPT :Result:='mmSDMA0_GFX_PREEMPT'; + mmSDMA0_GFX_DUMMY_REG :Result:='mmSDMA0_GFX_DUMMY_REG'; + mmSDMA0_GFX_MIDCMD_DATA0 :Result:='mmSDMA0_GFX_MIDCMD_DATA0'; + mmSDMA0_GFX_MIDCMD_DATA1 :Result:='mmSDMA0_GFX_MIDCMD_DATA1'; + mmSDMA0_GFX_MIDCMD_DATA2 :Result:='mmSDMA0_GFX_MIDCMD_DATA2'; + mmSDMA0_GFX_MIDCMD_DATA3 :Result:='mmSDMA0_GFX_MIDCMD_DATA3'; + mmSDMA0_GFX_MIDCMD_DATA4 :Result:='mmSDMA0_GFX_MIDCMD_DATA4'; + mmSDMA0_GFX_MIDCMD_DATA5 :Result:='mmSDMA0_GFX_MIDCMD_DATA5'; + mmSDMA0_GFX_MIDCMD_CNTL :Result:='mmSDMA0_GFX_MIDCMD_CNTL'; + mmSDMA0_RLC0_RB_CNTL :Result:='mmSDMA0_RLC0_RB_CNTL'; + mmSDMA0_RLC0_RB_BASE :Result:='mmSDMA0_RLC0_RB_BASE'; + mmSDMA0_RLC0_RB_BASE_HI :Result:='mmSDMA0_RLC0_RB_BASE_HI'; + mmSDMA0_RLC0_RB_RPTR :Result:='mmSDMA0_RLC0_RB_RPTR'; + mmSDMA0_RLC0_RB_WPTR :Result:='mmSDMA0_RLC0_RB_WPTR'; + mmSDMA0_RLC0_RB_WPTR_POLL_CNTL :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_CNTL'; + mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI'; + mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO'; + mmSDMA0_RLC0_RB_RPTR_ADDR_HI :Result:='mmSDMA0_RLC0_RB_RPTR_ADDR_HI'; + mmSDMA0_RLC0_RB_RPTR_ADDR_LO :Result:='mmSDMA0_RLC0_RB_RPTR_ADDR_LO'; + mmSDMA0_RLC0_IB_CNTL :Result:='mmSDMA0_RLC0_IB_CNTL'; + mmSDMA0_RLC0_IB_RPTR :Result:='mmSDMA0_RLC0_IB_RPTR'; + mmSDMA0_RLC0_IB_OFFSET :Result:='mmSDMA0_RLC0_IB_OFFSET'; + mmSDMA0_RLC0_IB_BASE_LO :Result:='mmSDMA0_RLC0_IB_BASE_LO'; + mmSDMA0_RLC0_IB_BASE_HI :Result:='mmSDMA0_RLC0_IB_BASE_HI'; + mmSDMA0_RLC0_IB_SIZE :Result:='mmSDMA0_RLC0_IB_SIZE'; + mmSDMA0_RLC0_SKIP_CNTL :Result:='mmSDMA0_RLC0_SKIP_CNTL'; + mmSDMA0_RLC0_CONTEXT_STATUS :Result:='mmSDMA0_RLC0_CONTEXT_STATUS'; + mmSDMA0_RLC0_DOORBELL :Result:='mmSDMA0_RLC0_DOORBELL'; + mmSDMA0_RLC0_VIRTUAL_ADDR :Result:='mmSDMA0_RLC0_VIRTUAL_ADDR'; + mmSDMA0_RLC0_APE1_CNTL :Result:='mmSDMA0_RLC0_APE1_CNTL'; + mmSDMA0_RLC0_DOORBELL_LOG :Result:='mmSDMA0_RLC0_DOORBELL_LOG'; + mmSDMA0_RLC0_WATERMARK :Result:='mmSDMA0_RLC0_WATERMARK'; + mmSDMA0_RLC0_CSA_ADDR_LO :Result:='mmSDMA0_RLC0_CSA_ADDR_LO'; + mmSDMA0_RLC0_CSA_ADDR_HI :Result:='mmSDMA0_RLC0_CSA_ADDR_HI'; + mmSDMA0_RLC0_IB_SUB_REMAIN :Result:='mmSDMA0_RLC0_IB_SUB_REMAIN'; + mmSDMA0_RLC0_PREEMPT :Result:='mmSDMA0_RLC0_PREEMPT'; + mmSDMA0_RLC0_DUMMY_REG :Result:='mmSDMA0_RLC0_DUMMY_REG'; + mmSDMA0_RLC0_MIDCMD_DATA0 :Result:='mmSDMA0_RLC0_MIDCMD_DATA0'; + mmSDMA0_RLC0_MIDCMD_DATA1 :Result:='mmSDMA0_RLC0_MIDCMD_DATA1'; + mmSDMA0_RLC0_MIDCMD_DATA2 :Result:='mmSDMA0_RLC0_MIDCMD_DATA2'; + mmSDMA0_RLC0_MIDCMD_DATA3 :Result:='mmSDMA0_RLC0_MIDCMD_DATA3'; + mmSDMA0_RLC0_MIDCMD_DATA4 :Result:='mmSDMA0_RLC0_MIDCMD_DATA4'; + mmSDMA0_RLC0_MIDCMD_DATA5 :Result:='mmSDMA0_RLC0_MIDCMD_DATA5'; + mmSDMA0_RLC0_MIDCMD_CNTL :Result:='mmSDMA0_RLC0_MIDCMD_CNTL'; + mmSDMA0_RLC1_RB_CNTL :Result:='mmSDMA0_RLC1_RB_CNTL'; + mmSDMA0_RLC1_RB_BASE :Result:='mmSDMA0_RLC1_RB_BASE'; + mmSDMA0_RLC1_RB_BASE_HI :Result:='mmSDMA0_RLC1_RB_BASE_HI'; + mmSDMA0_RLC1_RB_RPTR :Result:='mmSDMA0_RLC1_RB_RPTR'; + mmSDMA0_RLC1_RB_WPTR :Result:='mmSDMA0_RLC1_RB_WPTR'; + mmSDMA0_RLC1_RB_WPTR_POLL_CNTL :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_CNTL'; + mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI'; + mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO'; + mmSDMA0_RLC1_RB_RPTR_ADDR_HI :Result:='mmSDMA0_RLC1_RB_RPTR_ADDR_HI'; + mmSDMA0_RLC1_RB_RPTR_ADDR_LO :Result:='mmSDMA0_RLC1_RB_RPTR_ADDR_LO'; + mmSDMA0_RLC1_IB_CNTL :Result:='mmSDMA0_RLC1_IB_CNTL'; + mmSDMA0_RLC1_IB_RPTR :Result:='mmSDMA0_RLC1_IB_RPTR'; + mmSDMA0_RLC1_IB_OFFSET :Result:='mmSDMA0_RLC1_IB_OFFSET'; + mmSDMA0_RLC1_IB_BASE_LO :Result:='mmSDMA0_RLC1_IB_BASE_LO'; + mmSDMA0_RLC1_IB_BASE_HI :Result:='mmSDMA0_RLC1_IB_BASE_HI'; + mmSDMA0_RLC1_IB_SIZE :Result:='mmSDMA0_RLC1_IB_SIZE'; + mmSDMA0_RLC1_SKIP_CNTL :Result:='mmSDMA0_RLC1_SKIP_CNTL'; + mmSDMA0_RLC1_CONTEXT_STATUS :Result:='mmSDMA0_RLC1_CONTEXT_STATUS'; + mmSDMA0_RLC1_DOORBELL :Result:='mmSDMA0_RLC1_DOORBELL'; + mmSDMA0_RLC1_VIRTUAL_ADDR :Result:='mmSDMA0_RLC1_VIRTUAL_ADDR'; + mmSDMA0_RLC1_APE1_CNTL :Result:='mmSDMA0_RLC1_APE1_CNTL'; + mmSDMA0_RLC1_DOORBELL_LOG :Result:='mmSDMA0_RLC1_DOORBELL_LOG'; + mmSDMA0_RLC1_WATERMARK :Result:='mmSDMA0_RLC1_WATERMARK'; + mmSDMA0_RLC1_CSA_ADDR_LO :Result:='mmSDMA0_RLC1_CSA_ADDR_LO'; + mmSDMA0_RLC1_CSA_ADDR_HI :Result:='mmSDMA0_RLC1_CSA_ADDR_HI'; + mmSDMA0_RLC1_IB_SUB_REMAIN :Result:='mmSDMA0_RLC1_IB_SUB_REMAIN'; + mmSDMA0_RLC1_PREEMPT :Result:='mmSDMA0_RLC1_PREEMPT'; + mmSDMA0_RLC1_DUMMY_REG :Result:='mmSDMA0_RLC1_DUMMY_REG'; + mmSDMA0_RLC1_MIDCMD_DATA0 :Result:='mmSDMA0_RLC1_MIDCMD_DATA0'; + mmSDMA0_RLC1_MIDCMD_DATA1 :Result:='mmSDMA0_RLC1_MIDCMD_DATA1'; + mmSDMA0_RLC1_MIDCMD_DATA2 :Result:='mmSDMA0_RLC1_MIDCMD_DATA2'; + mmSDMA0_RLC1_MIDCMD_DATA3 :Result:='mmSDMA0_RLC1_MIDCMD_DATA3'; + mmSDMA0_RLC1_MIDCMD_DATA4 :Result:='mmSDMA0_RLC1_MIDCMD_DATA4'; + mmSDMA0_RLC1_MIDCMD_DATA5 :Result:='mmSDMA0_RLC1_MIDCMD_DATA5'; + mmSDMA0_RLC1_MIDCMD_CNTL :Result:='mmSDMA0_RLC1_MIDCMD_CNTL'; + mmSDMA1_UCODE_ADDR :Result:='mmSDMA1_UCODE_ADDR'; + mmSDMA1_UCODE_DATA :Result:='mmSDMA1_UCODE_DATA'; + mmSDMA1_POWER_CNTL :Result:='mmSDMA1_POWER_CNTL'; + mmSDMA1_CLK_CTRL :Result:='mmSDMA1_CLK_CTRL'; + mmSDMA1_CNTL :Result:='mmSDMA1_CNTL'; + mmSDMA1_CHICKEN_BITS :Result:='mmSDMA1_CHICKEN_BITS'; + mmSDMA1_TILING_CONFIG :Result:='mmSDMA1_TILING_CONFIG'; + mmSDMA1_HASH :Result:='mmSDMA1_HASH'; + mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL :Result:='mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL'; + mmSDMA1_RB_RPTR_FETCH :Result:='mmSDMA1_RB_RPTR_FETCH'; + mmSDMA1_IB_OFFSET_FETCH :Result:='mmSDMA1_IB_OFFSET_FETCH'; + mmSDMA1_PROGRAM :Result:='mmSDMA1_PROGRAM'; + mmSDMA1_STATUS_REG :Result:='mmSDMA1_STATUS_REG'; + mmSDMA1_STATUS1_REG :Result:='mmSDMA1_STATUS1_REG'; + mmSDMA1_RD_BURST_CNTL :Result:='mmSDMA1_RD_BURST_CNTL'; + mmSDMA1_F32_CNTL :Result:='mmSDMA1_F32_CNTL'; + mmSDMA1_FREEZE :Result:='mmSDMA1_FREEZE'; + mmSDMA1_PHASE0_QUANTUM :Result:='mmSDMA1_PHASE0_QUANTUM'; + mmSDMA1_PHASE1_QUANTUM :Result:='mmSDMA1_PHASE1_QUANTUM'; + mmSDMA1_EDC_CONFIG :Result:='mmSDMA1_EDC_CONFIG'; + mmSDMA1_VM_CNTL :Result:='mmSDMA1_VM_CNTL'; + mmSDMA1_VM_CTX_LO :Result:='mmSDMA1_VM_CTX_LO'; + mmSDMA1_VM_CTX_HI :Result:='mmSDMA1_VM_CTX_HI'; + mmSDMA1_STATUS2_REG :Result:='mmSDMA1_STATUS2_REG'; + mmSDMA1_ACTIVE_FCN_ID :Result:='mmSDMA1_ACTIVE_FCN_ID'; + mmSDMA1_VM_CTX_CNTL :Result:='mmSDMA1_VM_CTX_CNTL'; + mmSDMA1_VIRT_RESET_REQ :Result:='mmSDMA1_VIRT_RESET_REQ'; + mmSDMA1_VF_ENABLE :Result:='mmSDMA1_VF_ENABLE'; + mmSDMA1_BA_THRESHOLD :Result:='mmSDMA1_BA_THRESHOLD'; + mmSDMA1_ID :Result:='mmSDMA1_ID'; + mmSDMA1_VERSION :Result:='mmSDMA1_VERSION'; + mmSDMA1_ATOMIC_CNTL :Result:='mmSDMA1_ATOMIC_CNTL'; + mmSDMA1_ATOMIC_PREOP_LO :Result:='mmSDMA1_ATOMIC_PREOP_LO'; + mmSDMA1_ATOMIC_PREOP_HI :Result:='mmSDMA1_ATOMIC_PREOP_HI'; + mmSDMA1_PERF_REG_TYPE0 :Result:='mmSDMA1_PERF_REG_TYPE0'; + mmSDMA1_CONTEXT_REG_TYPE0 :Result:='mmSDMA1_CONTEXT_REG_TYPE0'; + mmSDMA1_CONTEXT_REG_TYPE1 :Result:='mmSDMA1_CONTEXT_REG_TYPE1'; + mmSDMA1_CONTEXT_REG_TYPE2 :Result:='mmSDMA1_CONTEXT_REG_TYPE2'; + mmSDMA1_PUB_REG_TYPE0 :Result:='mmSDMA1_PUB_REG_TYPE0'; + mmSDMA1_PUB_REG_TYPE1 :Result:='mmSDMA1_PUB_REG_TYPE1'; + mmSDMA1_GFX_RB_CNTL :Result:='mmSDMA1_GFX_RB_CNTL'; + mmSDMA1_GFX_RB_BASE :Result:='mmSDMA1_GFX_RB_BASE'; + mmSDMA1_GFX_RB_BASE_HI :Result:='mmSDMA1_GFX_RB_BASE_HI'; + mmSDMA1_GFX_RB_RPTR :Result:='mmSDMA1_GFX_RB_RPTR'; + mmSDMA1_GFX_RB_WPTR :Result:='mmSDMA1_GFX_RB_WPTR'; + mmSDMA1_GFX_RB_WPTR_POLL_CNTL :Result:='mmSDMA1_GFX_RB_WPTR_POLL_CNTL'; + mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI'; + mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO'; + mmSDMA1_GFX_RB_RPTR_ADDR_HI :Result:='mmSDMA1_GFX_RB_RPTR_ADDR_HI'; + mmSDMA1_GFX_RB_RPTR_ADDR_LO :Result:='mmSDMA1_GFX_RB_RPTR_ADDR_LO'; + mmSDMA1_GFX_IB_CNTL :Result:='mmSDMA1_GFX_IB_CNTL'; + mmSDMA1_GFX_IB_RPTR :Result:='mmSDMA1_GFX_IB_RPTR'; + mmSDMA1_GFX_IB_OFFSET :Result:='mmSDMA1_GFX_IB_OFFSET'; + mmSDMA1_GFX_IB_BASE_LO :Result:='mmSDMA1_GFX_IB_BASE_LO'; + mmSDMA1_GFX_IB_BASE_HI :Result:='mmSDMA1_GFX_IB_BASE_HI'; + mmSDMA1_GFX_IB_SIZE :Result:='mmSDMA1_GFX_IB_SIZE'; + mmSDMA1_GFX_SKIP_CNTL :Result:='mmSDMA1_GFX_SKIP_CNTL'; + mmSDMA1_GFX_CONTEXT_STATUS :Result:='mmSDMA1_GFX_CONTEXT_STATUS'; + mmSDMA1_GFX_DOORBELL :Result:='mmSDMA1_GFX_DOORBELL'; + mmSDMA1_GFX_CONTEXT_CNTL :Result:='mmSDMA1_GFX_CONTEXT_CNTL'; + mmSDMA1_GFX_VIRTUAL_ADDR :Result:='mmSDMA1_GFX_VIRTUAL_ADDR'; + mmSDMA1_GFX_APE1_CNTL :Result:='mmSDMA1_GFX_APE1_CNTL'; + mmSDMA1_GFX_DOORBELL_LOG :Result:='mmSDMA1_GFX_DOORBELL_LOG'; + mmSDMA1_GFX_WATERMARK :Result:='mmSDMA1_GFX_WATERMARK'; + mmSDMA1_GFX_CSA_ADDR_LO :Result:='mmSDMA1_GFX_CSA_ADDR_LO'; + mmSDMA1_GFX_CSA_ADDR_HI :Result:='mmSDMA1_GFX_CSA_ADDR_HI'; + mmSDMA1_GFX_IB_SUB_REMAIN :Result:='mmSDMA1_GFX_IB_SUB_REMAIN'; + mmSDMA1_GFX_PREEMPT :Result:='mmSDMA1_GFX_PREEMPT'; + mmSDMA1_GFX_DUMMY_REG :Result:='mmSDMA1_GFX_DUMMY_REG'; + mmSDMA1_GFX_MIDCMD_DATA0 :Result:='mmSDMA1_GFX_MIDCMD_DATA0'; + mmSDMA1_GFX_MIDCMD_DATA1 :Result:='mmSDMA1_GFX_MIDCMD_DATA1'; + mmSDMA1_GFX_MIDCMD_DATA2 :Result:='mmSDMA1_GFX_MIDCMD_DATA2'; + mmSDMA1_GFX_MIDCMD_DATA3 :Result:='mmSDMA1_GFX_MIDCMD_DATA3'; + mmSDMA1_GFX_MIDCMD_DATA4 :Result:='mmSDMA1_GFX_MIDCMD_DATA4'; + mmSDMA1_GFX_MIDCMD_DATA5 :Result:='mmSDMA1_GFX_MIDCMD_DATA5'; + mmSDMA1_GFX_MIDCMD_CNTL :Result:='mmSDMA1_GFX_MIDCMD_CNTL'; + mmSDMA1_RLC0_RB_CNTL :Result:='mmSDMA1_RLC0_RB_CNTL'; + mmSDMA1_RLC0_RB_BASE :Result:='mmSDMA1_RLC0_RB_BASE'; + mmSDMA1_RLC0_RB_BASE_HI :Result:='mmSDMA1_RLC0_RB_BASE_HI'; + mmSDMA1_RLC0_RB_RPTR :Result:='mmSDMA1_RLC0_RB_RPTR'; + mmSDMA1_RLC0_RB_WPTR :Result:='mmSDMA1_RLC0_RB_WPTR'; + mmSDMA1_RLC0_RB_WPTR_POLL_CNTL :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_CNTL'; + mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI'; + mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO'; + mmSDMA1_RLC0_RB_RPTR_ADDR_HI :Result:='mmSDMA1_RLC0_RB_RPTR_ADDR_HI'; + mmSDMA1_RLC0_RB_RPTR_ADDR_LO :Result:='mmSDMA1_RLC0_RB_RPTR_ADDR_LO'; + mmSDMA1_RLC0_IB_CNTL :Result:='mmSDMA1_RLC0_IB_CNTL'; + mmSDMA1_RLC0_IB_RPTR :Result:='mmSDMA1_RLC0_IB_RPTR'; + mmSDMA1_RLC0_IB_OFFSET :Result:='mmSDMA1_RLC0_IB_OFFSET'; + mmSDMA1_RLC0_IB_BASE_LO :Result:='mmSDMA1_RLC0_IB_BASE_LO'; + mmSDMA1_RLC0_IB_BASE_HI :Result:='mmSDMA1_RLC0_IB_BASE_HI'; + mmSDMA1_RLC0_IB_SIZE :Result:='mmSDMA1_RLC0_IB_SIZE'; + mmSDMA1_RLC0_SKIP_CNTL :Result:='mmSDMA1_RLC0_SKIP_CNTL'; + mmSDMA1_RLC0_CONTEXT_STATUS :Result:='mmSDMA1_RLC0_CONTEXT_STATUS'; + mmSDMA1_RLC0_DOORBELL :Result:='mmSDMA1_RLC0_DOORBELL'; + mmSDMA1_RLC0_VIRTUAL_ADDR :Result:='mmSDMA1_RLC0_VIRTUAL_ADDR'; + mmSDMA1_RLC0_APE1_CNTL :Result:='mmSDMA1_RLC0_APE1_CNTL'; + mmSDMA1_RLC0_DOORBELL_LOG :Result:='mmSDMA1_RLC0_DOORBELL_LOG'; + mmSDMA1_RLC0_WATERMARK :Result:='mmSDMA1_RLC0_WATERMARK'; + mmSDMA1_RLC0_CSA_ADDR_LO :Result:='mmSDMA1_RLC0_CSA_ADDR_LO'; + mmSDMA1_RLC0_CSA_ADDR_HI :Result:='mmSDMA1_RLC0_CSA_ADDR_HI'; + mmSDMA1_RLC0_IB_SUB_REMAIN :Result:='mmSDMA1_RLC0_IB_SUB_REMAIN'; + mmSDMA1_RLC0_PREEMPT :Result:='mmSDMA1_RLC0_PREEMPT'; + mmSDMA1_RLC0_DUMMY_REG :Result:='mmSDMA1_RLC0_DUMMY_REG'; + mmSDMA1_RLC0_MIDCMD_DATA0 :Result:='mmSDMA1_RLC0_MIDCMD_DATA0'; + mmSDMA1_RLC0_MIDCMD_DATA1 :Result:='mmSDMA1_RLC0_MIDCMD_DATA1'; + mmSDMA1_RLC0_MIDCMD_DATA2 :Result:='mmSDMA1_RLC0_MIDCMD_DATA2'; + mmSDMA1_RLC0_MIDCMD_DATA3 :Result:='mmSDMA1_RLC0_MIDCMD_DATA3'; + mmSDMA1_RLC0_MIDCMD_DATA4 :Result:='mmSDMA1_RLC0_MIDCMD_DATA4'; + mmSDMA1_RLC0_MIDCMD_DATA5 :Result:='mmSDMA1_RLC0_MIDCMD_DATA5'; + mmSDMA1_RLC0_MIDCMD_CNTL :Result:='mmSDMA1_RLC0_MIDCMD_CNTL'; + mmSDMA1_RLC1_RB_CNTL :Result:='mmSDMA1_RLC1_RB_CNTL'; + mmSDMA1_RLC1_RB_BASE :Result:='mmSDMA1_RLC1_RB_BASE'; + mmSDMA1_RLC1_RB_BASE_HI :Result:='mmSDMA1_RLC1_RB_BASE_HI'; + mmSDMA1_RLC1_RB_RPTR :Result:='mmSDMA1_RLC1_RB_RPTR'; + mmSDMA1_RLC1_RB_WPTR :Result:='mmSDMA1_RLC1_RB_WPTR'; + mmSDMA1_RLC1_RB_WPTR_POLL_CNTL :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_CNTL'; + mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI'; + mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO :Result:='mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO'; + mmSDMA1_RLC1_RB_RPTR_ADDR_HI :Result:='mmSDMA1_RLC1_RB_RPTR_ADDR_HI'; + mmSDMA1_RLC1_RB_RPTR_ADDR_LO :Result:='mmSDMA1_RLC1_RB_RPTR_ADDR_LO'; + mmSDMA1_RLC1_IB_CNTL :Result:='mmSDMA1_RLC1_IB_CNTL'; + mmSDMA1_RLC1_IB_RPTR :Result:='mmSDMA1_RLC1_IB_RPTR'; + mmSDMA1_RLC1_IB_OFFSET :Result:='mmSDMA1_RLC1_IB_OFFSET'; + mmSDMA1_RLC1_IB_BASE_LO :Result:='mmSDMA1_RLC1_IB_BASE_LO'; + mmSDMA1_RLC1_IB_BASE_HI :Result:='mmSDMA1_RLC1_IB_BASE_HI'; + mmSDMA1_RLC1_IB_SIZE :Result:='mmSDMA1_RLC1_IB_SIZE'; + mmSDMA1_RLC1_SKIP_CNTL :Result:='mmSDMA1_RLC1_SKIP_CNTL'; + mmSDMA1_RLC1_CONTEXT_STATUS :Result:='mmSDMA1_RLC1_CONTEXT_STATUS'; + mmSDMA1_RLC1_DOORBELL :Result:='mmSDMA1_RLC1_DOORBELL'; + mmSDMA1_RLC1_VIRTUAL_ADDR :Result:='mmSDMA1_RLC1_VIRTUAL_ADDR'; + mmSDMA1_RLC1_APE1_CNTL :Result:='mmSDMA1_RLC1_APE1_CNTL'; + mmSDMA1_RLC1_DOORBELL_LOG :Result:='mmSDMA1_RLC1_DOORBELL_LOG'; + mmSDMA1_RLC1_WATERMARK :Result:='mmSDMA1_RLC1_WATERMARK'; + mmSDMA1_RLC1_CSA_ADDR_LO :Result:='mmSDMA1_RLC1_CSA_ADDR_LO'; + mmSDMA1_RLC1_CSA_ADDR_HI :Result:='mmSDMA1_RLC1_CSA_ADDR_HI'; + mmSDMA1_RLC1_IB_SUB_REMAIN :Result:='mmSDMA1_RLC1_IB_SUB_REMAIN'; + mmSDMA1_RLC1_PREEMPT :Result:='mmSDMA1_RLC1_PREEMPT'; + mmSDMA1_RLC1_DUMMY_REG :Result:='mmSDMA1_RLC1_DUMMY_REG'; + mmSDMA1_RLC1_MIDCMD_DATA0 :Result:='mmSDMA1_RLC1_MIDCMD_DATA0'; + mmSDMA1_RLC1_MIDCMD_DATA1 :Result:='mmSDMA1_RLC1_MIDCMD_DATA1'; + mmSDMA1_RLC1_MIDCMD_DATA2 :Result:='mmSDMA1_RLC1_MIDCMD_DATA2'; + mmSDMA1_RLC1_MIDCMD_DATA3 :Result:='mmSDMA1_RLC1_MIDCMD_DATA3'; + mmSDMA1_RLC1_MIDCMD_DATA4 :Result:='mmSDMA1_RLC1_MIDCMD_DATA4'; + mmSDMA1_RLC1_MIDCMD_DATA5 :Result:='mmSDMA1_RLC1_MIDCMD_DATA5'; + mmSDMA1_RLC1_MIDCMD_CNTL :Result:='mmSDMA1_RLC1_MIDCMD_CNTL'; + mmUVD_PGFSM_CONFIG :Result:='mmUVD_PGFSM_CONFIG'; + mmUVD_PGFSM_READ_TILE1 :Result:='mmUVD_PGFSM_READ_TILE1'; + mmUVD_PGFSM_READ_TILE2 :Result:='mmUVD_PGFSM_READ_TILE2'; + mmUVD_POWER_STATUS :Result:='mmUVD_POWER_STATUS'; + mmUVD_PGFSM_READ_TILE3 :Result:='mmUVD_PGFSM_READ_TILE3'; + mmUVD_PGFSM_READ_TILE4 :Result:='mmUVD_PGFSM_READ_TILE4'; + mmUVD_PGFSM_READ_TILE5 :Result:='mmUVD_PGFSM_READ_TILE5'; + mmUVD_PGFSM_READ_TILE6 :Result:='mmUVD_PGFSM_READ_TILE6'; + mmUVD_PGFSM_READ_TILE7 :Result:='mmUVD_PGFSM_READ_TILE7'; + mmUVD_MIF_CURR_ADDR_CONFIG :Result:='mmUVD_MIF_CURR_ADDR_CONFIG'; + mmUVD_MIF_REF_ADDR_CONFIG :Result:='mmUVD_MIF_REF_ADDR_CONFIG'; + mmUVD_MIF_RECON1_ADDR_CONFIG :Result:='mmUVD_MIF_RECON1_ADDR_CONFIG'; + mmUVD_JPEG_ADDR_CONFIG :Result:='mmUVD_JPEG_ADDR_CONFIG'; + mmUVD_SEMA_ADDR_LOW :Result:='mmUVD_SEMA_ADDR_LOW'; + mmUVD_SEMA_ADDR_HIGH :Result:='mmUVD_SEMA_ADDR_HIGH'; + mmUVD_SEMA_CMD :Result:='mmUVD_SEMA_CMD'; + mmUVD_GPCOM_VCPU_CMD :Result:='mmUVD_GPCOM_VCPU_CMD'; + mmUVD_GPCOM_VCPU_DATA0 :Result:='mmUVD_GPCOM_VCPU_DATA0'; + mmUVD_GPCOM_VCPU_DATA1 :Result:='mmUVD_GPCOM_VCPU_DATA1'; + mmUVD_ENGINE_CNTL :Result:='mmUVD_ENGINE_CNTL'; + mmUVD_UDEC_ADDR_CONFIG :Result:='mmUVD_UDEC_ADDR_CONFIG'; + mmUVD_UDEC_DB_ADDR_CONFIG :Result:='mmUVD_UDEC_DB_ADDR_CONFIG'; + mmUVD_UDEC_DBW_ADDR_CONFIG :Result:='mmUVD_UDEC_DBW_ADDR_CONFIG'; + mmUVD_SUVD_CGC_GATE :Result:='mmUVD_SUVD_CGC_GATE'; + mmUVD_SUVD_CGC_STATUS :Result:='mmUVD_SUVD_CGC_STATUS'; + mmUVD_SUVD_CGC_CTRL :Result:='mmUVD_SUVD_CGC_CTRL'; + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH :Result:='mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH'; + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW :Result:='mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW'; + mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH :Result:='mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH'; + mmUVD_LMI_RBC_IB_64BIT_BAR_LOW :Result:='mmUVD_LMI_RBC_IB_64BIT_BAR_LOW'; + mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH :Result:='mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH'; + mmUVD_LMI_RBC_RB_64BIT_BAR_LOW :Result:='mmUVD_LMI_RBC_RB_64BIT_BAR_LOW'; + mmUVD_SEMA_CNTL :Result:='mmUVD_SEMA_CNTL'; + mmUVD_LMI_EXT40_ADDR :Result:='mmUVD_LMI_EXT40_ADDR'; + mmUVD_CTX_INDEX :Result:='mmUVD_CTX_INDEX'; + mmUVD_CTX_DATA :Result:='mmUVD_CTX_DATA'; + mmUVD_CGC_GATE :Result:='mmUVD_CGC_GATE'; + mmUVD_CGC_STATUS :Result:='mmUVD_CGC_STATUS'; + mmUVD_CGC_CTRL :Result:='mmUVD_CGC_CTRL'; + mmUVD_CGC_UDEC_STATUS :Result:='mmUVD_CGC_UDEC_STATUS'; + mmUVD_LMI_CTRL2 :Result:='mmUVD_LMI_CTRL2'; + mmUVD_MASTINT_EN :Result:='mmUVD_MASTINT_EN'; + mmUVD_LMI_ADDR_EXT :Result:='mmUVD_LMI_ADDR_EXT'; + mmUVD_LMI_CTRL :Result:='mmUVD_LMI_CTRL'; + mmUVD_LMI_STATUS :Result:='mmUVD_LMI_STATUS'; + mmUVD_LMI_SWAP_CNTL :Result:='mmUVD_LMI_SWAP_CNTL'; + mmUVD_MP_SWAP_CNTL :Result:='mmUVD_MP_SWAP_CNTL'; + mmUVD_MPC_CNTL :Result:='mmUVD_MPC_CNTL'; + mmUVD_MPC_SET_MUXA0 :Result:='mmUVD_MPC_SET_MUXA0'; + mmUVD_MPC_SET_MUXA1 :Result:='mmUVD_MPC_SET_MUXA1'; + mmUVD_MPC_SET_MUXB0 :Result:='mmUVD_MPC_SET_MUXB0'; + mmUVD_MPC_SET_MUXB1 :Result:='mmUVD_MPC_SET_MUXB1'; + mmUVD_MPC_SET_MUX :Result:='mmUVD_MPC_SET_MUX'; + mmUVD_MPC_SET_ALU :Result:='mmUVD_MPC_SET_ALU'; + mmUVD_VCPU_CACHE_OFFSET0 :Result:='mmUVD_VCPU_CACHE_OFFSET0'; + mmUVD_VCPU_CACHE_SIZE0 :Result:='mmUVD_VCPU_CACHE_SIZE0'; + mmUVD_VCPU_CACHE_OFFSET1 :Result:='mmUVD_VCPU_CACHE_OFFSET1'; + mmUVD_VCPU_CACHE_SIZE1 :Result:='mmUVD_VCPU_CACHE_SIZE1'; + mmUVD_VCPU_CACHE_OFFSET2 :Result:='mmUVD_VCPU_CACHE_OFFSET2'; + mmUVD_VCPU_CACHE_SIZE2 :Result:='mmUVD_VCPU_CACHE_SIZE2'; + mmUVD_VCPU_CNTL :Result:='mmUVD_VCPU_CNTL'; + mmUVD_SOFT_RESET :Result:='mmUVD_SOFT_RESET'; + mmUVD_LMI_RBC_IB_VMID :Result:='mmUVD_LMI_RBC_IB_VMID'; + mmUVD_RBC_IB_SIZE :Result:='mmUVD_RBC_IB_SIZE'; + mmUVD_LMI_RBC_RB_VMID :Result:='mmUVD_LMI_RBC_RB_VMID'; + mmUVD_RBC_RB_RPTR :Result:='mmUVD_RBC_RB_RPTR'; + mmUVD_RBC_RB_WPTR :Result:='mmUVD_RBC_RB_WPTR'; + mmUVD_RBC_RB_CNTL :Result:='mmUVD_RBC_RB_CNTL'; + mmUVD_RBC_RB_RPTR_ADDR :Result:='mmUVD_RBC_RB_RPTR_ADDR'; + mmUVD_STATUS :Result:='mmUVD_STATUS'; + mmUVD_SEMA_TIMEOUT_STATUS :Result:='mmUVD_SEMA_TIMEOUT_STATUS'; + mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL :Result:='mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL'; + mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL :Result:='mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL'; + mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL :Result:='mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL'; + mmUVD_CONTEXT_ID :Result:='mmUVD_CONTEXT_ID'; + mmDCP3_GRPH_ENABLE :Result:='mmDCP3_GRPH_ENABLE'; + mmDCP3_GRPH_CONTROL :Result:='mmDCP3_GRPH_CONTROL'; + mmDCP3_GRPH_LUT_10BIT_BYPASS :Result:='mmDCP3_GRPH_LUT_10BIT_BYPASS'; + mmDCP3_GRPH_SWAP_CNTL :Result:='mmDCP3_GRPH_SWAP_CNTL'; + mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS :Result:='mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS'; + mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS :Result:='mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS'; + mmDCP3_GRPH_PITCH :Result:='mmDCP3_GRPH_PITCH'; + mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH'; + mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP3_GRPH_SURFACE_OFFSET_X :Result:='mmDCP3_GRPH_SURFACE_OFFSET_X'; + mmDCP3_GRPH_SURFACE_OFFSET_Y :Result:='mmDCP3_GRPH_SURFACE_OFFSET_Y'; + mmDCP3_GRPH_X_START :Result:='mmDCP3_GRPH_X_START'; + mmDCP3_GRPH_Y_START :Result:='mmDCP3_GRPH_Y_START'; + mmDCP3_GRPH_X_END :Result:='mmDCP3_GRPH_X_END'; + mmDCP3_GRPH_Y_END :Result:='mmDCP3_GRPH_Y_END'; + mmDCP3_INPUT_GAMMA_CONTROL :Result:='mmDCP3_INPUT_GAMMA_CONTROL'; + mmDCP3_GRPH_UPDATE :Result:='mmDCP3_GRPH_UPDATE'; + mmDCP3_GRPH_FLIP_CONTROL :Result:='mmDCP3_GRPH_FLIP_CONTROL'; + mmDCP3_GRPH_SURFACE_ADDRESS_INUSE :Result:='mmDCP3_GRPH_SURFACE_ADDRESS_INUSE'; + mmDCP3_GRPH_DFQ_CONTROL :Result:='mmDCP3_GRPH_DFQ_CONTROL'; + mmDCP3_GRPH_DFQ_STATUS :Result:='mmDCP3_GRPH_DFQ_STATUS'; + mmDCP3_GRPH_INTERRUPT_STATUS :Result:='mmDCP3_GRPH_INTERRUPT_STATUS'; + mmDCP3_GRPH_INTERRUPT_CONTROL :Result:='mmDCP3_GRPH_INTERRUPT_CONTROL'; + mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE :Result:='mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE'; + mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS :Result:='mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS'; + mmDCP3_GRPH_COMPRESS_PITCH :Result:='mmDCP3_GRPH_COMPRESS_PITCH'; + mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH'; + mmDCP3_OVL_ENABLE :Result:='mmDCP3_OVL_ENABLE'; + mmDCP3_OVL_CONTROL1 :Result:='mmDCP3_OVL_CONTROL1'; + mmDCP3_OVL_CONTROL2 :Result:='mmDCP3_OVL_CONTROL2'; + mmDCP3_OVL_SWAP_CNTL :Result:='mmDCP3_OVL_SWAP_CNTL'; + mmDCP3_OVL_SURFACE_ADDRESS :Result:='mmDCP3_OVL_SURFACE_ADDRESS'; + mmDCP3_OVL_PITCH :Result:='mmDCP3_OVL_PITCH'; + mmDCP3_OVL_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_OVL_SURFACE_ADDRESS_HIGH'; + mmDCP3_OVL_SURFACE_OFFSET_X :Result:='mmDCP3_OVL_SURFACE_OFFSET_X'; + mmDCP3_OVL_SURFACE_OFFSET_Y :Result:='mmDCP3_OVL_SURFACE_OFFSET_Y'; + mmDCP3_OVL_START :Result:='mmDCP3_OVL_START'; + mmDCP3_OVL_END :Result:='mmDCP3_OVL_END'; + mmDCP3_OVL_UPDATE :Result:='mmDCP3_OVL_UPDATE'; + mmDCP3_OVL_SURFACE_ADDRESS_INUSE :Result:='mmDCP3_OVL_SURFACE_ADDRESS_INUSE'; + mmDCP3_OVL_DFQ_CONTROL :Result:='mmDCP3_OVL_DFQ_CONTROL'; + mmDCP3_OVL_DFQ_STATUS :Result:='mmDCP3_OVL_DFQ_STATUS'; + mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE :Result:='mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE'; + mmDCP3_OVLSCL_EDGE_PIXEL_CNTL :Result:='mmDCP3_OVLSCL_EDGE_PIXEL_CNTL'; + mmDCP3_PRESCALE_GRPH_CONTROL :Result:='mmDCP3_PRESCALE_GRPH_CONTROL'; + mmDCP3_PRESCALE_VALUES_GRPH_R :Result:='mmDCP3_PRESCALE_VALUES_GRPH_R'; + mmDCP3_PRESCALE_VALUES_GRPH_G :Result:='mmDCP3_PRESCALE_VALUES_GRPH_G'; + mmDCP3_PRESCALE_VALUES_GRPH_B :Result:='mmDCP3_PRESCALE_VALUES_GRPH_B'; + mmDCP3_PRESCALE_OVL_CONTROL :Result:='mmDCP3_PRESCALE_OVL_CONTROL'; + mmDCP3_PRESCALE_VALUES_OVL_CB :Result:='mmDCP3_PRESCALE_VALUES_OVL_CB'; + mmDCP3_PRESCALE_VALUES_OVL_Y :Result:='mmDCP3_PRESCALE_VALUES_OVL_Y'; + mmDCP3_PRESCALE_VALUES_OVL_CR :Result:='mmDCP3_PRESCALE_VALUES_OVL_CR'; + mmDCP3_INPUT_CSC_CONTROL :Result:='mmDCP3_INPUT_CSC_CONTROL'; + mmDCP3_INPUT_CSC_C11_C12 :Result:='mmDCP3_INPUT_CSC_C11_C12'; + mmDCP3_INPUT_CSC_C13_C14 :Result:='mmDCP3_INPUT_CSC_C13_C14'; + mmDCP3_INPUT_CSC_C21_C22 :Result:='mmDCP3_INPUT_CSC_C21_C22'; + mmDCP3_INPUT_CSC_C23_C24 :Result:='mmDCP3_INPUT_CSC_C23_C24'; + mmDCP3_INPUT_CSC_C31_C32 :Result:='mmDCP3_INPUT_CSC_C31_C32'; + mmDCP3_INPUT_CSC_C33_C34 :Result:='mmDCP3_INPUT_CSC_C33_C34'; + mmDCP3_OUTPUT_CSC_CONTROL :Result:='mmDCP3_OUTPUT_CSC_CONTROL'; + mmDCP3_OUTPUT_CSC_C11_C12 :Result:='mmDCP3_OUTPUT_CSC_C11_C12'; + mmDCP3_OUTPUT_CSC_C13_C14 :Result:='mmDCP3_OUTPUT_CSC_C13_C14'; + mmDCP3_OUTPUT_CSC_C21_C22 :Result:='mmDCP3_OUTPUT_CSC_C21_C22'; + mmDCP3_OUTPUT_CSC_C23_C24 :Result:='mmDCP3_OUTPUT_CSC_C23_C24'; + mmDCP3_OUTPUT_CSC_C31_C32 :Result:='mmDCP3_OUTPUT_CSC_C31_C32'; + mmDCP3_OUTPUT_CSC_C33_C34 :Result:='mmDCP3_OUTPUT_CSC_C33_C34'; + mmDCP3_COMM_MATRIXA_TRANS_C11_C12 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C11_C12'; + mmDCP3_COMM_MATRIXA_TRANS_C13_C14 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C13_C14'; + mmDCP3_COMM_MATRIXA_TRANS_C21_C22 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C21_C22'; + mmDCP3_COMM_MATRIXA_TRANS_C23_C24 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C23_C24'; + mmDCP3_COMM_MATRIXA_TRANS_C31_C32 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C31_C32'; + mmDCP3_COMM_MATRIXA_TRANS_C33_C34 :Result:='mmDCP3_COMM_MATRIXA_TRANS_C33_C34'; + mmDCP3_COMM_MATRIXB_TRANS_C11_C12 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C11_C12'; + mmDCP3_COMM_MATRIXB_TRANS_C13_C14 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C13_C14'; + mmDCP3_COMM_MATRIXB_TRANS_C21_C22 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C21_C22'; + mmDCP3_COMM_MATRIXB_TRANS_C23_C24 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C23_C24'; + mmDCP3_COMM_MATRIXB_TRANS_C31_C32 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C31_C32'; + mmDCP3_COMM_MATRIXB_TRANS_C33_C34 :Result:='mmDCP3_COMM_MATRIXB_TRANS_C33_C34'; + mmDCP3_DENORM_CONTROL :Result:='mmDCP3_DENORM_CONTROL'; + mmDCP3_OUT_ROUND_CONTROL :Result:='mmDCP3_OUT_ROUND_CONTROL'; + mmDCP3_OUT_CLAMP_CONTROL_R_CR :Result:='mmDCP3_OUT_CLAMP_CONTROL_R_CR'; + mmDCP3_KEY_CONTROL :Result:='mmDCP3_KEY_CONTROL'; + mmDCP3_KEY_RANGE_ALPHA :Result:='mmDCP3_KEY_RANGE_ALPHA'; + mmDCP3_KEY_RANGE_RED :Result:='mmDCP3_KEY_RANGE_RED'; + mmDCP3_KEY_RANGE_GREEN :Result:='mmDCP3_KEY_RANGE_GREEN'; + mmDCP3_KEY_RANGE_BLUE :Result:='mmDCP3_KEY_RANGE_BLUE'; + mmDCP3_DEGAMMA_CONTROL :Result:='mmDCP3_DEGAMMA_CONTROL'; + mmDCP3_GAMUT_REMAP_CONTROL :Result:='mmDCP3_GAMUT_REMAP_CONTROL'; + mmDCP3_GAMUT_REMAP_C11_C12 :Result:='mmDCP3_GAMUT_REMAP_C11_C12'; + mmDCP3_GAMUT_REMAP_C13_C14 :Result:='mmDCP3_GAMUT_REMAP_C13_C14'; + mmDCP3_GAMUT_REMAP_C21_C22 :Result:='mmDCP3_GAMUT_REMAP_C21_C22'; + mmDCP3_GAMUT_REMAP_C23_C24 :Result:='mmDCP3_GAMUT_REMAP_C23_C24'; + mmDCP3_GAMUT_REMAP_C31_C32 :Result:='mmDCP3_GAMUT_REMAP_C31_C32'; + mmDCP3_GAMUT_REMAP_C33_C34 :Result:='mmDCP3_GAMUT_REMAP_C33_C34'; + mmDCP3_DCP_SPATIAL_DITHER_CNTL :Result:='mmDCP3_DCP_SPATIAL_DITHER_CNTL'; + mmDCP3_DCP_RANDOM_SEEDS :Result:='mmDCP3_DCP_RANDOM_SEEDS'; + mmDCP3_DCP_FP_CONVERTED_FIELD :Result:='mmDCP3_DCP_FP_CONVERTED_FIELD'; + mmDCP3_CUR_CONTROL :Result:='mmDCP3_CUR_CONTROL'; + mmDCP3_CUR_SURFACE_ADDRESS :Result:='mmDCP3_CUR_SURFACE_ADDRESS'; + mmDCP3_CUR_SIZE :Result:='mmDCP3_CUR_SIZE'; + mmDCP3_CUR_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_CUR_SURFACE_ADDRESS_HIGH'; + mmDCP3_CUR_POSITION :Result:='mmDCP3_CUR_POSITION'; + mmDCP3_CUR_HOT_SPOT :Result:='mmDCP3_CUR_HOT_SPOT'; + mmDCP3_CUR_COLOR1 :Result:='mmDCP3_CUR_COLOR1'; + mmDCP3_CUR_COLOR2 :Result:='mmDCP3_CUR_COLOR2'; + mmDCP3_CUR_UPDATE :Result:='mmDCP3_CUR_UPDATE'; + mmDCP3_CUR2_CONTROL :Result:='mmDCP3_CUR2_CONTROL'; + mmDCP3_CUR2_SURFACE_ADDRESS :Result:='mmDCP3_CUR2_SURFACE_ADDRESS'; + mmDCP3_CUR2_SIZE :Result:='mmDCP3_CUR2_SIZE'; + mmDCP3_CUR2_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_CUR2_SURFACE_ADDRESS_HIGH'; + mmDCP3_CUR2_POSITION :Result:='mmDCP3_CUR2_POSITION'; + mmDCP3_CUR2_HOT_SPOT :Result:='mmDCP3_CUR2_HOT_SPOT'; + mmDCP3_CUR2_COLOR1 :Result:='mmDCP3_CUR2_COLOR1'; + mmDCP3_CUR2_COLOR2 :Result:='mmDCP3_CUR2_COLOR2'; + mmDCP3_CUR2_UPDATE :Result:='mmDCP3_CUR2_UPDATE'; + mmDCP3_DC_LUT_RW_MODE :Result:='mmDCP3_DC_LUT_RW_MODE'; + mmDCP3_DC_LUT_RW_INDEX :Result:='mmDCP3_DC_LUT_RW_INDEX'; + mmDCP3_DC_LUT_SEQ_COLOR :Result:='mmDCP3_DC_LUT_SEQ_COLOR'; + mmDCP3_DC_LUT_PWL_DATA :Result:='mmDCP3_DC_LUT_PWL_DATA'; + mmDCP3_DC_LUT_30_COLOR :Result:='mmDCP3_DC_LUT_30_COLOR'; + mmDCP3_DC_LUT_VGA_ACCESS_ENABLE :Result:='mmDCP3_DC_LUT_VGA_ACCESS_ENABLE'; + mmDCP3_DC_LUT_WRITE_EN_MASK :Result:='mmDCP3_DC_LUT_WRITE_EN_MASK'; + mmDCP3_DC_LUT_AUTOFILL :Result:='mmDCP3_DC_LUT_AUTOFILL'; + mmDCP3_DC_LUT_CONTROL :Result:='mmDCP3_DC_LUT_CONTROL'; + mmDCP3_DC_LUT_BLACK_OFFSET_BLUE :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_BLUE'; + mmDCP3_DC_LUT_BLACK_OFFSET_GREEN :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_GREEN'; + mmDCP3_DC_LUT_BLACK_OFFSET_RED :Result:='mmDCP3_DC_LUT_BLACK_OFFSET_RED'; + mmDCP3_DC_LUT_WHITE_OFFSET_BLUE :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_BLUE'; + mmDCP3_DC_LUT_WHITE_OFFSET_GREEN :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_GREEN'; + mmDCP3_DC_LUT_WHITE_OFFSET_RED :Result:='mmDCP3_DC_LUT_WHITE_OFFSET_RED'; + mmDCP3_DCP_CRC_CONTROL :Result:='mmDCP3_DCP_CRC_CONTROL'; + mmDCP3_DCP_CRC_MASK :Result:='mmDCP3_DCP_CRC_MASK'; + mmDCP3_DCP_CRC_CURRENT :Result:='mmDCP3_DCP_CRC_CURRENT'; + mmDCP3_DCP_CRC_LAST :Result:='mmDCP3_DCP_CRC_LAST'; + mmDCP3_DCP_DEBUG :Result:='mmDCP3_DCP_DEBUG'; + mmDCP3_GRPH_FLIP_RATE_CNTL :Result:='mmDCP3_GRPH_FLIP_RATE_CNTL'; + mmDCP3_DCP_GSL_CONTROL :Result:='mmDCP3_DCP_GSL_CONTROL'; + mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK :Result:='mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK'; + mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS :Result:='mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS'; + mmDCP3_OVL_STEREOSYNC_FLIP :Result:='mmDCP3_OVL_STEREOSYNC_FLIP'; + mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP3_DCP_TEST_DEBUG_INDEX :Result:='mmDCP3_DCP_TEST_DEBUG_INDEX'; + mmDCP3_DCP_TEST_DEBUG_DATA :Result:='mmDCP3_DCP_TEST_DEBUG_DATA'; + mmDCP3_GRPH_STEREOSYNC_FLIP :Result:='mmDCP3_GRPH_STEREOSYNC_FLIP'; + mmDCP3_DCP_DEBUG2 :Result:='mmDCP3_DCP_DEBUG2'; + mmDCP3_CUR_REQUEST_FILTER_CNTL :Result:='mmDCP3_CUR_REQUEST_FILTER_CNTL'; + mmDCP3_CUR_STEREO_CONTROL :Result:='mmDCP3_CUR_STEREO_CONTROL'; + mmDCP3_CUR2_STEREO_CONTROL :Result:='mmDCP3_CUR2_STEREO_CONTROL'; + mmDCP3_OUT_CLAMP_CONTROL_G_Y :Result:='mmDCP3_OUT_CLAMP_CONTROL_G_Y'; + mmDCP3_OUT_CLAMP_CONTROL_B_CB :Result:='mmDCP3_OUT_CLAMP_CONTROL_B_CB'; + mmDCP3_HW_ROTATION :Result:='mmDCP3_HW_ROTATION'; + mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :Result:='mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL'; + mmDCP3_REGAMMA_CONTROL :Result:='mmDCP3_REGAMMA_CONTROL'; + mmDCP3_REGAMMA_LUT_INDEX :Result:='mmDCP3_REGAMMA_LUT_INDEX'; + mmDCP3_REGAMMA_LUT_DATA :Result:='mmDCP3_REGAMMA_LUT_DATA'; + mmDCP3_REGAMMA_LUT_WRITE_EN_MASK :Result:='mmDCP3_REGAMMA_LUT_WRITE_EN_MASK'; + mmDCP3_REGAMMA_CNTLA_START_CNTL :Result:='mmDCP3_REGAMMA_CNTLA_START_CNTL'; + mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL :Result:='mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL'; + mmDCP3_REGAMMA_CNTLA_END_CNTL1 :Result:='mmDCP3_REGAMMA_CNTLA_END_CNTL1'; + mmDCP3_REGAMMA_CNTLA_END_CNTL2 :Result:='mmDCP3_REGAMMA_CNTLA_END_CNTL2'; + mmDCP3_REGAMMA_CNTLA_REGION_0_1 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_0_1'; + mmDCP3_REGAMMA_CNTLA_REGION_2_3 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_2_3'; + mmDCP3_REGAMMA_CNTLA_REGION_4_5 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_4_5'; + mmDCP3_REGAMMA_CNTLA_REGION_6_7 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_6_7'; + mmDCP3_REGAMMA_CNTLA_REGION_8_9 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_8_9'; + mmDCP3_REGAMMA_CNTLA_REGION_10_11 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_10_11'; + mmDCP3_REGAMMA_CNTLA_REGION_12_13 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_12_13'; + mmDCP3_REGAMMA_CNTLA_REGION_14_15 :Result:='mmDCP3_REGAMMA_CNTLA_REGION_14_15'; + mmDCP3_REGAMMA_CNTLB_START_CNTL :Result:='mmDCP3_REGAMMA_CNTLB_START_CNTL'; + mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL :Result:='mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL'; + mmDCP3_REGAMMA_CNTLB_END_CNTL1 :Result:='mmDCP3_REGAMMA_CNTLB_END_CNTL1'; + mmDCP3_REGAMMA_CNTLB_END_CNTL2 :Result:='mmDCP3_REGAMMA_CNTLB_END_CNTL2'; + mmDCP3_REGAMMA_CNTLB_REGION_0_1 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_0_1'; + mmDCP3_REGAMMA_CNTLB_REGION_2_3 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_2_3'; + mmDCP3_REGAMMA_CNTLB_REGION_4_5 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_4_5'; + mmDCP3_REGAMMA_CNTLB_REGION_6_7 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_6_7'; + mmDCP3_REGAMMA_CNTLB_REGION_8_9 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_8_9'; + mmDCP3_REGAMMA_CNTLB_REGION_10_11 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_10_11'; + mmDCP3_REGAMMA_CNTLB_REGION_12_13 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_12_13'; + mmDCP3_REGAMMA_CNTLB_REGION_14_15 :Result:='mmDCP3_REGAMMA_CNTLB_REGION_14_15'; + mmDCP3_ALPHA_CONTROL :Result:='mmDCP3_ALPHA_CONTROL'; + mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :Result:='mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS'; + mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :Result:='mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH'; + mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :Result:='mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS'; + mmLB3_LB_DATA_FORMAT :Result:='mmLB3_LB_DATA_FORMAT'; + mmLB3_LB_MEMORY_CTRL :Result:='mmLB3_LB_MEMORY_CTRL'; + mmLB3_LB_MEMORY_SIZE_STATUS :Result:='mmLB3_LB_MEMORY_SIZE_STATUS'; + mmLB3_LB_DESKTOP_HEIGHT :Result:='mmLB3_LB_DESKTOP_HEIGHT'; + mmLB3_LB_VLINE_START_END :Result:='mmLB3_LB_VLINE_START_END'; + mmLB3_LB_VLINE2_START_END :Result:='mmLB3_LB_VLINE2_START_END'; + mmLB3_LB_V_COUNTER :Result:='mmLB3_LB_V_COUNTER'; + mmLB3_LB_SNAPSHOT_V_COUNTER :Result:='mmLB3_LB_SNAPSHOT_V_COUNTER'; + mmLB3_LB_INTERRUPT_MASK :Result:='mmLB3_LB_INTERRUPT_MASK'; + mmLB3_LB_VLINE_STATUS :Result:='mmLB3_LB_VLINE_STATUS'; + mmLB3_LB_VLINE2_STATUS :Result:='mmLB3_LB_VLINE2_STATUS'; + mmLB3_LB_VBLANK_STATUS :Result:='mmLB3_LB_VBLANK_STATUS'; + mmLB3_LB_SYNC_RESET_SEL :Result:='mmLB3_LB_SYNC_RESET_SEL'; + mmLB3_LB_BLACK_KEYER_R_CR :Result:='mmLB3_LB_BLACK_KEYER_R_CR'; + mmLB3_LB_BLACK_KEYER_G_Y :Result:='mmLB3_LB_BLACK_KEYER_G_Y'; + mmLB3_LB_BLACK_KEYER_B_CB :Result:='mmLB3_LB_BLACK_KEYER_B_CB'; + mmLB3_LB_KEYER_COLOR_CTRL :Result:='mmLB3_LB_KEYER_COLOR_CTRL'; + mmLB3_LB_KEYER_COLOR_R_CR :Result:='mmLB3_LB_KEYER_COLOR_R_CR'; + mmLB3_LB_KEYER_COLOR_G_Y :Result:='mmLB3_LB_KEYER_COLOR_G_Y'; + mmLB3_LB_KEYER_COLOR_B_CB :Result:='mmLB3_LB_KEYER_COLOR_B_CB'; + mmLB3_LB_KEYER_COLOR_REP_R_CR :Result:='mmLB3_LB_KEYER_COLOR_REP_R_CR'; + mmLB3_LB_KEYER_COLOR_REP_G_Y :Result:='mmLB3_LB_KEYER_COLOR_REP_G_Y'; + mmLB3_LB_KEYER_COLOR_REP_B_CB :Result:='mmLB3_LB_KEYER_COLOR_REP_B_CB'; + mmLB3_LB_BUFFER_LEVEL_STATUS :Result:='mmLB3_LB_BUFFER_LEVEL_STATUS'; + mmLB3_LB_BUFFER_URGENCY_CTRL :Result:='mmLB3_LB_BUFFER_URGENCY_CTRL'; + mmLB3_LB_BUFFER_URGENCY_STATUS :Result:='mmLB3_LB_BUFFER_URGENCY_STATUS'; + mmLB3_LB_BUFFER_STATUS :Result:='mmLB3_LB_BUFFER_STATUS'; + mmLB2_DC_MVP_LB_CONTROL :Result:='mmLB2_DC_MVP_LB_CONTROL'; + mmLB3_LB_NO_OUTSTANDING_REQ_STATUS :Result:='mmLB3_LB_NO_OUTSTANDING_REQ_STATUS'; + mmLB3_MVP_AFR_FLIP_MODE :Result:='mmLB3_MVP_AFR_FLIP_MODE'; + mmLB3_MVP_AFR_FLIP_FIFO_CNTL :Result:='mmLB3_MVP_AFR_FLIP_FIFO_CNTL'; + mmLB3_MVP_FLIP_LINE_NUM_INSERT :Result:='mmLB3_MVP_FLIP_LINE_NUM_INSERT'; + mmLB3_DC_MVP_LB_CONTROL :Result:='mmLB3_DC_MVP_LB_CONTROL'; + mmLB3_LB_DEBUG :Result:='mmLB3_LB_DEBUG'; + mmLB3_LB_DEBUG2 :Result:='mmLB3_LB_DEBUG2'; + mmLB3_LB_DEBUG3 :Result:='mmLB3_LB_DEBUG3'; + mmLB2_LB_DEBUG :Result:='mmLB2_LB_DEBUG'; + mmLB3_LB_TEST_DEBUG_INDEX :Result:='mmLB3_LB_TEST_DEBUG_INDEX'; + mmLB3_LB_TEST_DEBUG_DATA :Result:='mmLB3_LB_TEST_DEBUG_DATA'; + mmDCFE3_DCFE_CLOCK_CONTROL :Result:='mmDCFE3_DCFE_CLOCK_CONTROL'; + mmDCFE3_DCFE_SOFT_RESET :Result:='mmDCFE3_DCFE_SOFT_RESET'; + mmDCFE3_DCFE_DBG_CONFIG :Result:='mmDCFE3_DCFE_DBG_CONFIG'; + mmDC_PERFMON6_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON6_PERFCOUNTER_CNTL'; + mmDC_PERFMON6_PERFCOUNTER_STATE :Result:='mmDC_PERFMON6_PERFCOUNTER_STATE'; + mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON6_PERFMON_CNTL :Result:='mmDC_PERFMON6_PERFMON_CNTL'; + mmDC_PERFMON6_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON6_PERFMON_CVALUE_LOW'; + mmDC_PERFMON6_PERFMON_HI :Result:='mmDC_PERFMON6_PERFMON_HI'; + mmDC_PERFMON6_PERFMON_LOW :Result:='mmDC_PERFMON6_PERFMON_LOW'; + mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON6_PERFMON_CNTL2 :Result:='mmDC_PERFMON6_PERFMON_CNTL2'; + mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 :Result:='mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1'; + mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 :Result:='mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2'; + mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL :Result:='mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL'; + mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL :Result:='mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL'; + mmDMIF_PG3_DPG_PIPE_DPM_CONTROL :Result:='mmDMIF_PG3_DPG_PIPE_DPM_CONTROL'; + mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL :Result:='mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL'; + mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :Result:='mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL'; + mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :Result:='mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH'; + mmDMIF_PG3_DPG_TEST_DEBUG_INDEX :Result:='mmDMIF_PG3_DPG_TEST_DEBUG_INDEX'; + mmDMIF_PG3_DPG_TEST_DEBUG_DATA :Result:='mmDMIF_PG3_DPG_TEST_DEBUG_DATA'; + mmDMIF_PG3_DPG_REPEATER_PROGRAM :Result:='mmDMIF_PG3_DPG_REPEATER_PROGRAM'; + mmDMIF_PG3_DPG_HW_DEBUG_A :Result:='mmDMIF_PG3_DPG_HW_DEBUG_A'; + mmDMIF_PG3_DPG_HW_DEBUG_B :Result:='mmDMIF_PG3_DPG_HW_DEBUG_B'; + mmDMIF_PG3_DPG_HW_DEBUG_11 :Result:='mmDMIF_PG3_DPG_HW_DEBUG_11'; + mmSCL3_SCL_COEF_RAM_SELECT :Result:='mmSCL3_SCL_COEF_RAM_SELECT'; + mmSCL3_SCL_COEF_RAM_TAP_DATA :Result:='mmSCL3_SCL_COEF_RAM_TAP_DATA'; + mmSCL3_SCL_MODE :Result:='mmSCL3_SCL_MODE'; + mmSCL3_SCL_TAP_CONTROL :Result:='mmSCL3_SCL_TAP_CONTROL'; + mmSCL3_SCL_CONTROL :Result:='mmSCL3_SCL_CONTROL'; + mmSCL3_SCL_BYPASS_CONTROL :Result:='mmSCL3_SCL_BYPASS_CONTROL'; + mmSCL3_SCL_MANUAL_REPLICATE_CONTROL :Result:='mmSCL3_SCL_MANUAL_REPLICATE_CONTROL'; + mmSCL3_SCL_AUTOMATIC_MODE_CONTROL :Result:='mmSCL3_SCL_AUTOMATIC_MODE_CONTROL'; + mmSCL3_SCL_HORZ_FILTER_CONTROL :Result:='mmSCL3_SCL_HORZ_FILTER_CONTROL'; + mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO :Result:='mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO'; + mmSCL3_SCL_HORZ_FILTER_INIT :Result:='mmSCL3_SCL_HORZ_FILTER_INIT'; + mmSCL3_SCL_VERT_FILTER_CONTROL :Result:='mmSCL3_SCL_VERT_FILTER_CONTROL'; + mmSCL3_SCL_VERT_FILTER_SCALE_RATIO :Result:='mmSCL3_SCL_VERT_FILTER_SCALE_RATIO'; + mmSCL3_SCL_VERT_FILTER_INIT :Result:='mmSCL3_SCL_VERT_FILTER_INIT'; + mmSCL3_SCL_VERT_FILTER_INIT_BOT :Result:='mmSCL3_SCL_VERT_FILTER_INIT_BOT'; + mmSCL3_SCL_ROUND_OFFSET :Result:='mmSCL3_SCL_ROUND_OFFSET'; + mmSCL2_SCL_VERT_FILTER_INIT :Result:='mmSCL2_SCL_VERT_FILTER_INIT'; + mmSCL3_SCL_UPDATE :Result:='mmSCL3_SCL_UPDATE'; + mmSCL3_SCL_F_SHARP_CONTROL :Result:='mmSCL3_SCL_F_SHARP_CONTROL'; + mmSCL3_SCL_ALU_CONTROL :Result:='mmSCL3_SCL_ALU_CONTROL'; + mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS :Result:='mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS'; + mmSCL2_SCL_VERT_FILTER_INIT_BOT :Result:='mmSCL2_SCL_VERT_FILTER_INIT_BOT'; + mmSCL3_VIEWPORT_START_SECONDARY :Result:='mmSCL3_VIEWPORT_START_SECONDARY'; + mmSCL3_VIEWPORT_START :Result:='mmSCL3_VIEWPORT_START'; + mmSCL3_VIEWPORT_SIZE :Result:='mmSCL3_VIEWPORT_SIZE'; + mmSCL3_EXT_OVERSCAN_LEFT_RIGHT :Result:='mmSCL3_EXT_OVERSCAN_LEFT_RIGHT'; + mmSCL3_EXT_OVERSCAN_TOP_BOTTOM :Result:='mmSCL3_EXT_OVERSCAN_TOP_BOTTOM'; + mmSCL3_SCL_MODE_CHANGE_DET1 :Result:='mmSCL3_SCL_MODE_CHANGE_DET1'; + mmSCL3_SCL_MODE_CHANGE_DET2 :Result:='mmSCL3_SCL_MODE_CHANGE_DET2'; + mmSCL3_SCL_MODE_CHANGE_DET3 :Result:='mmSCL3_SCL_MODE_CHANGE_DET3'; + mmSCL3_SCL_MODE_CHANGE_MASK :Result:='mmSCL3_SCL_MODE_CHANGE_MASK'; + mmSCL3_SCL_DEBUG2 :Result:='mmSCL3_SCL_DEBUG2'; + mmSCL3_SCL_DEBUG :Result:='mmSCL3_SCL_DEBUG'; + mmSCL3_SCL_TEST_DEBUG_INDEX :Result:='mmSCL3_SCL_TEST_DEBUG_INDEX'; + mmSCL3_SCL_TEST_DEBUG_DATA :Result:='mmSCL3_SCL_TEST_DEBUG_DATA'; + mmBLND3_BLND_CONTROL :Result:='mmBLND3_BLND_CONTROL'; + mmBLND3_SM_CONTROL2 :Result:='mmBLND3_SM_CONTROL2'; + mmBLND3_BLND_CONTROL2 :Result:='mmBLND3_BLND_CONTROL2'; + mmBLND3_BLND_UPDATE :Result:='mmBLND3_BLND_UPDATE'; + mmBLND3_BLND_UNDERFLOW_INTERRUPT :Result:='mmBLND3_BLND_UNDERFLOW_INTERRUPT'; + mmBLND3_BLND_V_UPDATE_LOCK :Result:='mmBLND3_BLND_V_UPDATE_LOCK'; + mmBLND3_BLND_DEBUG :Result:='mmBLND3_BLND_DEBUG'; + mmBLND3_BLND_TEST_DEBUG_INDEX :Result:='mmBLND3_BLND_TEST_DEBUG_INDEX'; + mmBLND3_BLND_TEST_DEBUG_DATA :Result:='mmBLND3_BLND_TEST_DEBUG_DATA'; + mmBLND3_BLND_REG_UPDATE_STATUS :Result:='mmBLND3_BLND_REG_UPDATE_STATUS'; + mmCRTC3_CRTC_3D_STRUCTURE_CONTROL :Result:='mmCRTC3_CRTC_3D_STRUCTURE_CONTROL'; + mmCRTC3_CRTC_GSL_VSYNC_GAP :Result:='mmCRTC3_CRTC_GSL_VSYNC_GAP'; + mmCRTC3_CRTC_GSL_WINDOW :Result:='mmCRTC3_CRTC_GSL_WINDOW'; + mmCRTC3_CRTC_GSL_CONTROL :Result:='mmCRTC3_CRTC_GSL_CONTROL'; + mmCRTC3_CRTC_DCFE_CLOCK_CONTROL :Result:='mmCRTC3_CRTC_DCFE_CLOCK_CONTROL'; + mmCRTC3_CRTC_H_BLANK_EARLY_NUM :Result:='mmCRTC3_CRTC_H_BLANK_EARLY_NUM'; + mmCRTC3_DCFE_DBG_SEL :Result:='mmCRTC3_DCFE_DBG_SEL'; + mmCRTC3_DCFE_MEM_PWR_CTRL :Result:='mmCRTC3_DCFE_MEM_PWR_CTRL'; + mmCRTC3_CRTC_H_TOTAL :Result:='mmCRTC3_CRTC_H_TOTAL'; + mmCRTC3_CRTC_H_BLANK_START_END :Result:='mmCRTC3_CRTC_H_BLANK_START_END'; + mmCRTC3_CRTC_H_SYNC_A :Result:='mmCRTC3_CRTC_H_SYNC_A'; + mmCRTC3_CRTC_H_SYNC_A_CNTL :Result:='mmCRTC3_CRTC_H_SYNC_A_CNTL'; + mmCRTC3_CRTC_H_SYNC_B :Result:='mmCRTC3_CRTC_H_SYNC_B'; + mmCRTC3_CRTC_H_SYNC_B_CNTL :Result:='mmCRTC3_CRTC_H_SYNC_B_CNTL'; + mmCRTC3_CRTC_VBI_END :Result:='mmCRTC3_CRTC_VBI_END'; + mmCRTC3_CRTC_V_TOTAL :Result:='mmCRTC3_CRTC_V_TOTAL'; + mmCRTC3_CRTC_V_TOTAL_MIN :Result:='mmCRTC3_CRTC_V_TOTAL_MIN'; + mmCRTC3_CRTC_V_TOTAL_MAX :Result:='mmCRTC3_CRTC_V_TOTAL_MAX'; + mmCRTC3_CRTC_V_TOTAL_CONTROL :Result:='mmCRTC3_CRTC_V_TOTAL_CONTROL'; + mmCRTC3_CRTC_V_TOTAL_INT_STATUS :Result:='mmCRTC3_CRTC_V_TOTAL_INT_STATUS'; + mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS :Result:='mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS'; + mmCRTC3_CRTC_V_BLANK_START_END :Result:='mmCRTC3_CRTC_V_BLANK_START_END'; + mmCRTC3_CRTC_V_SYNC_A :Result:='mmCRTC3_CRTC_V_SYNC_A'; + mmCRTC3_CRTC_V_SYNC_A_CNTL :Result:='mmCRTC3_CRTC_V_SYNC_A_CNTL'; + mmCRTC3_CRTC_V_SYNC_B :Result:='mmCRTC3_CRTC_V_SYNC_B'; + mmCRTC3_CRTC_V_SYNC_B_CNTL :Result:='mmCRTC3_CRTC_V_SYNC_B_CNTL'; + mmCRTC3_CRTC_DTMTEST_CNTL :Result:='mmCRTC3_CRTC_DTMTEST_CNTL'; + mmCRTC3_CRTC_DTMTEST_STATUS_POSITION :Result:='mmCRTC3_CRTC_DTMTEST_STATUS_POSITION'; + mmCRTC3_CRTC_TRIGA_CNTL :Result:='mmCRTC3_CRTC_TRIGA_CNTL'; + mmCRTC3_CRTC_TRIGA_MANUAL_TRIG :Result:='mmCRTC3_CRTC_TRIGA_MANUAL_TRIG'; + mmCRTC3_CRTC_TRIGB_CNTL :Result:='mmCRTC3_CRTC_TRIGB_CNTL'; + mmCRTC3_CRTC_TRIGB_MANUAL_TRIG :Result:='mmCRTC3_CRTC_TRIGB_MANUAL_TRIG'; + mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL :Result:='mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL'; + mmCRTC3_CRTC_FLOW_CONTROL :Result:='mmCRTC3_CRTC_FLOW_CONTROL'; + mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE :Result:='mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE'; + mmCRTC3_CRTC_AVSYNC_COUNTER :Result:='mmCRTC3_CRTC_AVSYNC_COUNTER'; + mmCRTC3_CRTC_CONTROL :Result:='mmCRTC3_CRTC_CONTROL'; + mmCRTC3_CRTC_BLANK_CONTROL :Result:='mmCRTC3_CRTC_BLANK_CONTROL'; + mmCRTC3_CRTC_INTERLACE_CONTROL :Result:='mmCRTC3_CRTC_INTERLACE_CONTROL'; + mmCRTC3_CRTC_INTERLACE_STATUS :Result:='mmCRTC3_CRTC_INTERLACE_STATUS'; + mmCRTC3_CRTC_FIELD_INDICATION_CONTROL :Result:='mmCRTC3_CRTC_FIELD_INDICATION_CONTROL'; + mmCRTC3_CRTC_PIXEL_DATA_READBACK0 :Result:='mmCRTC3_CRTC_PIXEL_DATA_READBACK0'; + mmCRTC3_CRTC_PIXEL_DATA_READBACK1 :Result:='mmCRTC3_CRTC_PIXEL_DATA_READBACK1'; + mmCRTC3_CRTC_STATUS :Result:='mmCRTC3_CRTC_STATUS'; + mmCRTC3_CRTC_STATUS_POSITION :Result:='mmCRTC3_CRTC_STATUS_POSITION'; + mmCRTC3_CRTC_NOM_VERT_POSITION :Result:='mmCRTC3_CRTC_NOM_VERT_POSITION'; + mmCRTC3_CRTC_STATUS_FRAME_COUNT :Result:='mmCRTC3_CRTC_STATUS_FRAME_COUNT'; + mmCRTC3_CRTC_STATUS_VF_COUNT :Result:='mmCRTC3_CRTC_STATUS_VF_COUNT'; + mmCRTC3_CRTC_STATUS_HV_COUNT :Result:='mmCRTC3_CRTC_STATUS_HV_COUNT'; + mmCRTC3_CRTC_COUNT_CONTROL :Result:='mmCRTC3_CRTC_COUNT_CONTROL'; + mmCRTC3_CRTC_COUNT_RESET :Result:='mmCRTC3_CRTC_COUNT_RESET'; + mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :Result:='mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE'; + mmCRTC3_CRTC_VERT_SYNC_CONTROL :Result:='mmCRTC3_CRTC_VERT_SYNC_CONTROL'; + mmCRTC3_CRTC_STEREO_STATUS :Result:='mmCRTC3_CRTC_STEREO_STATUS'; + mmCRTC3_CRTC_STEREO_CONTROL :Result:='mmCRTC3_CRTC_STEREO_CONTROL'; + mmCRTC3_CRTC_SNAPSHOT_STATUS :Result:='mmCRTC3_CRTC_SNAPSHOT_STATUS'; + mmCRTC3_CRTC_SNAPSHOT_CONTROL :Result:='mmCRTC3_CRTC_SNAPSHOT_CONTROL'; + mmCRTC3_CRTC_SNAPSHOT_POSITION :Result:='mmCRTC3_CRTC_SNAPSHOT_POSITION'; + mmCRTC3_CRTC_SNAPSHOT_FRAME :Result:='mmCRTC3_CRTC_SNAPSHOT_FRAME'; + mmCRTC3_CRTC_START_LINE_CONTROL :Result:='mmCRTC3_CRTC_START_LINE_CONTROL'; + mmCRTC3_CRTC_INTERRUPT_CONTROL :Result:='mmCRTC3_CRTC_INTERRUPT_CONTROL'; + mmCRTC3_CRTC_UPDATE_LOCK :Result:='mmCRTC3_CRTC_UPDATE_LOCK'; + mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL :Result:='mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL'; + mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE :Result:='mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE'; + mmCRTC3_DCFE_MEM_PWR_CTRL2 :Result:='mmCRTC3_DCFE_MEM_PWR_CTRL2'; + mmCRTC3_DCFE_MEM_PWR_STATUS :Result:='mmCRTC3_DCFE_MEM_PWR_STATUS'; + mmCRTC3_CRTC_TEST_PATTERN_CONTROL :Result:='mmCRTC3_CRTC_TEST_PATTERN_CONTROL'; + mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS :Result:='mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS'; + mmCRTC3_CRTC_TEST_PATTERN_COLOR :Result:='mmCRTC3_CRTC_TEST_PATTERN_COLOR'; + mmCRTC3_MASTER_UPDATE_LOCK :Result:='mmCRTC3_MASTER_UPDATE_LOCK'; + mmCRTC3_MASTER_UPDATE_MODE :Result:='mmCRTC3_MASTER_UPDATE_MODE'; + mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT :Result:='mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT'; + mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :Result:='mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER'; + mmCRTC3_CRTC_MVP_STATUS :Result:='mmCRTC3_CRTC_MVP_STATUS'; + mmCRTC3_CRTC_MASTER_EN :Result:='mmCRTC3_CRTC_MASTER_EN'; + mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT :Result:='mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT'; + mmCRTC3_CRTC_V_UPDATE_INT_STATUS :Result:='mmCRTC3_CRTC_V_UPDATE_INT_STATUS'; + mmCRTC3_CRTC_TEST_DEBUG_INDEX :Result:='mmCRTC3_CRTC_TEST_DEBUG_INDEX'; + mmCRTC3_CRTC_TEST_DEBUG_DATA :Result:='mmCRTC3_CRTC_TEST_DEBUG_DATA'; + mmCRTC3_CRTC_OVERSCAN_COLOR :Result:='mmCRTC3_CRTC_OVERSCAN_COLOR'; + mmCRTC3_CRTC_OVERSCAN_COLOR_EXT :Result:='mmCRTC3_CRTC_OVERSCAN_COLOR_EXT'; + mmCRTC3_CRTC_BLANK_DATA_COLOR :Result:='mmCRTC3_CRTC_BLANK_DATA_COLOR'; + mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT :Result:='mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT'; + mmCRTC3_CRTC_BLACK_COLOR :Result:='mmCRTC3_CRTC_BLACK_COLOR'; + mmCRTC3_CRTC_BLACK_COLOR_EXT :Result:='mmCRTC3_CRTC_BLACK_COLOR_EXT'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION'; + mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL :Result:='mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL'; + mmCRTC3_CRTC_CRC_CNTL :Result:='mmCRTC3_CRTC_CRC_CNTL'; + mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL :Result:='mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL'; + mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL :Result:='mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL'; + mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL :Result:='mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL'; + mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL :Result:='mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL'; + mmCRTC3_CRTC_CRC0_DATA_RG :Result:='mmCRTC3_CRTC_CRC0_DATA_RG'; + mmCRTC3_CRTC_CRC0_DATA_B :Result:='mmCRTC3_CRTC_CRC0_DATA_B'; + mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL :Result:='mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL'; + mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL :Result:='mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL'; + mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL :Result:='mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL'; + mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL :Result:='mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL'; + mmCRTC3_CRTC_CRC1_DATA_RG :Result:='mmCRTC3_CRTC_CRC1_DATA_RG'; + mmCRTC3_CRTC_CRC1_DATA_B :Result:='mmCRTC3_CRTC_CRC1_DATA_B'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL'; + mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :Result:='mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL'; + mmCRTC3_CRTC_STATIC_SCREEN_CONTROL :Result:='mmCRTC3_CRTC_STATIC_SCREEN_CONTROL'; + mmFMT3_FMT_CLAMP_COMPONENT_R :Result:='mmFMT3_FMT_CLAMP_COMPONENT_R'; + mmFMT3_FMT_CLAMP_COMPONENT_G :Result:='mmFMT3_FMT_CLAMP_COMPONENT_G'; + mmFMT3_FMT_CLAMP_COMPONENT_B :Result:='mmFMT3_FMT_CLAMP_COMPONENT_B'; + mmFMT3_FMT_TEST_DEBUG_INDEX :Result:='mmFMT3_FMT_TEST_DEBUG_INDEX'; + mmFMT3_FMT_TEST_DEBUG_DATA :Result:='mmFMT3_FMT_TEST_DEBUG_DATA'; + mmFMT3_FMT_DYNAMIC_EXP_CNTL :Result:='mmFMT3_FMT_DYNAMIC_EXP_CNTL'; + mmFMT3_FMT_CONTROL :Result:='mmFMT3_FMT_CONTROL'; + mmFMT3_FMT_FORCE_OUTPUT_CNTL :Result:='mmFMT3_FMT_FORCE_OUTPUT_CNTL'; + mmFMT3_FMT_FORCE_DATA_0_1 :Result:='mmFMT3_FMT_FORCE_DATA_0_1'; + mmFMT3_FMT_FORCE_DATA_2_3 :Result:='mmFMT3_FMT_FORCE_DATA_2_3'; + mmFMT3_FMT_BIT_DEPTH_CONTROL :Result:='mmFMT3_FMT_BIT_DEPTH_CONTROL'; + mmFMT3_FMT_DITHER_RAND_R_SEED :Result:='mmFMT3_FMT_DITHER_RAND_R_SEED'; + mmFMT3_FMT_DITHER_RAND_G_SEED :Result:='mmFMT3_FMT_DITHER_RAND_G_SEED'; + mmFMT3_FMT_DITHER_RAND_B_SEED :Result:='mmFMT3_FMT_DITHER_RAND_B_SEED'; + mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL'; + mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX'; + mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX'; + mmFMT3_FMT_CLAMP_CNTL :Result:='mmFMT3_FMT_CLAMP_CNTL'; + mmFMT3_FMT_CRC_CNTL :Result:='mmFMT3_FMT_CRC_CNTL'; + mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK :Result:='mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK'; + mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK :Result:='mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK'; + mmFMT3_FMT_CRC_SIG_RED_GREEN :Result:='mmFMT3_FMT_CRC_SIG_RED_GREEN'; + mmFMT3_FMT_CRC_SIG_BLUE_CONTROL :Result:='mmFMT3_FMT_CRC_SIG_BLUE_CONTROL'; + mmFMT3_FMT_DEBUG_CNTL :Result:='mmFMT3_FMT_DEBUG_CNTL'; + mmDCP4_GRPH_ENABLE :Result:='mmDCP4_GRPH_ENABLE'; + mmDCP4_GRPH_CONTROL :Result:='mmDCP4_GRPH_CONTROL'; + mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS :Result:='mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS'; + mmDCP4_GRPH_PITCH :Result:='mmDCP4_GRPH_PITCH'; + mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH'; + mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP4_GRPH_SURFACE_OFFSET_X :Result:='mmDCP4_GRPH_SURFACE_OFFSET_X'; + mmDCP4_GRPH_SURFACE_OFFSET_Y :Result:='mmDCP4_GRPH_SURFACE_OFFSET_Y'; + mmDCP4_GRPH_X_START :Result:='mmDCP4_GRPH_X_START'; + mmDCP4_INPUT_GAMMA_CONTROL :Result:='mmDCP4_INPUT_GAMMA_CONTROL'; + mmDCP4_GRPH_UPDATE :Result:='mmDCP4_GRPH_UPDATE'; + mmDCP4_GRPH_FLIP_CONTROL :Result:='mmDCP4_GRPH_FLIP_CONTROL'; + mmDCP4_GRPH_SURFACE_ADDRESS_INUSE :Result:='mmDCP4_GRPH_SURFACE_ADDRESS_INUSE'; + mmDCP4_GRPH_DFQ_CONTROL :Result:='mmDCP4_GRPH_DFQ_CONTROL'; + mmDCP4_GRPH_DFQ_STATUS :Result:='mmDCP4_GRPH_DFQ_STATUS'; + mmDCP4_OVL_SURFACE_ADDRESS :Result:='mmDCP4_OVL_SURFACE_ADDRESS'; + mmDCP4_OVL_UPDATE :Result:='mmDCP4_OVL_UPDATE'; + mmDCP4_OVL_SURFACE_ADDRESS_INUSE :Result:='mmDCP4_OVL_SURFACE_ADDRESS_INUSE'; + mmDCP4_OVL_DFQ_CONTROL :Result:='mmDCP4_OVL_DFQ_CONTROL'; + mmDCP4_OVL_DFQ_STATUS :Result:='mmDCP4_OVL_DFQ_STATUS'; + mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE :Result:='mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE'; + mmDCP4_OVLSCL_EDGE_PIXEL_CNTL :Result:='mmDCP4_OVLSCL_EDGE_PIXEL_CNTL'; + mmDCP4_PRESCALE_GRPH_CONTROL :Result:='mmDCP4_PRESCALE_GRPH_CONTROL'; + mmDCP4_PRESCALE_VALUES_GRPH_R :Result:='mmDCP4_PRESCALE_VALUES_GRPH_R'; + mmDCP4_PRESCALE_VALUES_GRPH_G :Result:='mmDCP4_PRESCALE_VALUES_GRPH_G'; + mmDCP4_PRESCALE_VALUES_GRPH_B :Result:='mmDCP4_PRESCALE_VALUES_GRPH_B'; + mmDCP4_PRESCALE_OVL_CONTROL :Result:='mmDCP4_PRESCALE_OVL_CONTROL'; + mmDCP4_PRESCALE_VALUES_OVL_CB :Result:='mmDCP4_PRESCALE_VALUES_OVL_CB'; + mmDCP4_PRESCALE_VALUES_OVL_Y :Result:='mmDCP4_PRESCALE_VALUES_OVL_Y'; + mmDCP4_PRESCALE_VALUES_OVL_CR :Result:='mmDCP4_PRESCALE_VALUES_OVL_CR'; + mmDCP4_INPUT_CSC_CONTROL :Result:='mmDCP4_INPUT_CSC_CONTROL'; + mmDCP4_INPUT_CSC_C11_C12 :Result:='mmDCP4_INPUT_CSC_C11_C12'; + mmDCP4_INPUT_CSC_C13_C14 :Result:='mmDCP4_INPUT_CSC_C13_C14'; + mmDCP4_INPUT_CSC_C21_C22 :Result:='mmDCP4_INPUT_CSC_C21_C22'; + mmDCP4_INPUT_CSC_C23_C24 :Result:='mmDCP4_INPUT_CSC_C23_C24'; + mmDCP4_INPUT_CSC_C31_C32 :Result:='mmDCP4_INPUT_CSC_C31_C32'; + mmDCP4_INPUT_CSC_C33_C34 :Result:='mmDCP4_INPUT_CSC_C33_C34'; + mmDCP4_OUTPUT_CSC_CONTROL :Result:='mmDCP4_OUTPUT_CSC_CONTROL'; + mmDCP4_OUTPUT_CSC_C11_C12 :Result:='mmDCP4_OUTPUT_CSC_C11_C12'; + mmDCP4_OUTPUT_CSC_C13_C14 :Result:='mmDCP4_OUTPUT_CSC_C13_C14'; + mmDCP4_OUTPUT_CSC_C21_C22 :Result:='mmDCP4_OUTPUT_CSC_C21_C22'; + mmDCP4_OUTPUT_CSC_C23_C24 :Result:='mmDCP4_OUTPUT_CSC_C23_C24'; + mmDCP4_OUTPUT_CSC_C31_C32 :Result:='mmDCP4_OUTPUT_CSC_C31_C32'; + mmDCP4_OUTPUT_CSC_C33_C34 :Result:='mmDCP4_OUTPUT_CSC_C33_C34'; + mmDCP4_COMM_MATRIXA_TRANS_C11_C12 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C11_C12'; + mmDCP4_COMM_MATRIXA_TRANS_C13_C14 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C13_C14'; + mmDCP4_COMM_MATRIXA_TRANS_C21_C22 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C21_C22'; + mmDCP4_COMM_MATRIXA_TRANS_C23_C24 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C23_C24'; + mmDCP4_COMM_MATRIXA_TRANS_C31_C32 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C31_C32'; + mmDCP4_COMM_MATRIXA_TRANS_C33_C34 :Result:='mmDCP4_COMM_MATRIXA_TRANS_C33_C34'; + mmDCP4_COMM_MATRIXB_TRANS_C11_C12 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C11_C12'; + mmDCP4_COMM_MATRIXB_TRANS_C13_C14 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C13_C14'; + mmDCP4_COMM_MATRIXB_TRANS_C21_C22 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C21_C22'; + mmDCP4_COMM_MATRIXB_TRANS_C23_C24 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C23_C24'; + mmDCP4_COMM_MATRIXB_TRANS_C31_C32 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C31_C32'; + mmDCP4_COMM_MATRIXB_TRANS_C33_C34 :Result:='mmDCP4_COMM_MATRIXB_TRANS_C33_C34'; + mmDCP4_DENORM_CONTROL :Result:='mmDCP4_DENORM_CONTROL'; + mmDCP4_OUT_ROUND_CONTROL :Result:='mmDCP4_OUT_ROUND_CONTROL'; + mmDCP4_OUT_CLAMP_CONTROL_R_CR :Result:='mmDCP4_OUT_CLAMP_CONTROL_R_CR'; + mmDCP4_KEY_CONTROL :Result:='mmDCP4_KEY_CONTROL'; + mmDCP4_KEY_RANGE_ALPHA :Result:='mmDCP4_KEY_RANGE_ALPHA'; + mmDCP4_KEY_RANGE_RED :Result:='mmDCP4_KEY_RANGE_RED'; + mmDCP4_KEY_RANGE_GREEN :Result:='mmDCP4_KEY_RANGE_GREEN'; + mmDCP4_KEY_RANGE_BLUE :Result:='mmDCP4_KEY_RANGE_BLUE'; + mmDCP4_DEGAMMA_CONTROL :Result:='mmDCP4_DEGAMMA_CONTROL'; + mmDCP4_GAMUT_REMAP_CONTROL :Result:='mmDCP4_GAMUT_REMAP_CONTROL'; + mmDCP4_GAMUT_REMAP_C11_C12 :Result:='mmDCP4_GAMUT_REMAP_C11_C12'; + mmDCP4_GAMUT_REMAP_C13_C14 :Result:='mmDCP4_GAMUT_REMAP_C13_C14'; + mmDCP4_GAMUT_REMAP_C21_C22 :Result:='mmDCP4_GAMUT_REMAP_C21_C22'; + mmDCP4_GAMUT_REMAP_C23_C24 :Result:='mmDCP4_GAMUT_REMAP_C23_C24'; + mmDCP4_GAMUT_REMAP_C31_C32 :Result:='mmDCP4_GAMUT_REMAP_C31_C32'; + mmDCP4_GAMUT_REMAP_C33_C34 :Result:='mmDCP4_GAMUT_REMAP_C33_C34'; + mmDCP4_DCP_SPATIAL_DITHER_CNTL :Result:='mmDCP4_DCP_SPATIAL_DITHER_CNTL'; + mmDCP4_DCP_RANDOM_SEEDS :Result:='mmDCP4_DCP_RANDOM_SEEDS'; + mmDCP4_DCP_FP_CONVERTED_FIELD :Result:='mmDCP4_DCP_FP_CONVERTED_FIELD'; + mmDCP4_CUR_CONTROL :Result:='mmDCP4_CUR_CONTROL'; + mmDCP4_CUR_SURFACE_ADDRESS :Result:='mmDCP4_CUR_SURFACE_ADDRESS'; + mmDCP4_CUR_SIZE :Result:='mmDCP4_CUR_SIZE'; + mmDCP4_CUR_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_CUR_SURFACE_ADDRESS_HIGH'; + mmDCP4_CUR_POSITION :Result:='mmDCP4_CUR_POSITION'; + mmDCP4_CUR_HOT_SPOT :Result:='mmDCP4_CUR_HOT_SPOT'; + mmDCP4_CUR_COLOR1 :Result:='mmDCP4_CUR_COLOR1'; + mmDCP4_CUR_COLOR2 :Result:='mmDCP4_CUR_COLOR2'; + mmDCP4_CUR_UPDATE :Result:='mmDCP4_CUR_UPDATE'; + mmDCP4_CUR2_CONTROL :Result:='mmDCP4_CUR2_CONTROL'; + mmDCP4_CUR2_SURFACE_ADDRESS :Result:='mmDCP4_CUR2_SURFACE_ADDRESS'; + mmDCP4_CUR2_SIZE :Result:='mmDCP4_CUR2_SIZE'; + mmDCP4_CUR2_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_CUR2_SURFACE_ADDRESS_HIGH'; + mmDCP4_CUR2_POSITION :Result:='mmDCP4_CUR2_POSITION'; + mmDCP4_CUR2_HOT_SPOT :Result:='mmDCP4_CUR2_HOT_SPOT'; + mmDCP4_CUR2_COLOR1 :Result:='mmDCP4_CUR2_COLOR1'; + mmDCP4_CUR2_COLOR2 :Result:='mmDCP4_CUR2_COLOR2'; + mmDCP4_CUR2_UPDATE :Result:='mmDCP4_CUR2_UPDATE'; + mmDCP4_DC_LUT_RW_MODE :Result:='mmDCP4_DC_LUT_RW_MODE'; + mmDCP4_DC_LUT_RW_INDEX :Result:='mmDCP4_DC_LUT_RW_INDEX'; + mmDCP4_DC_LUT_SEQ_COLOR :Result:='mmDCP4_DC_LUT_SEQ_COLOR'; + mmDCP4_DC_LUT_PWL_DATA :Result:='mmDCP4_DC_LUT_PWL_DATA'; + mmDCP4_DC_LUT_VGA_ACCESS_ENABLE :Result:='mmDCP4_DC_LUT_VGA_ACCESS_ENABLE'; + mmDCP4_DC_LUT_WHITE_OFFSET_GREEN :Result:='mmDCP4_DC_LUT_WHITE_OFFSET_GREEN'; + mmDCP4_DCP_CRC_MASK :Result:='mmDCP4_DCP_CRC_MASK'; + mmDCP4_DCP_CRC_CURRENT :Result:='mmDCP4_DCP_CRC_CURRENT'; + mmDCP4_DCP_CRC_LAST :Result:='mmDCP4_DCP_CRC_LAST'; + mmDCP4_DCP_DEBUG :Result:='mmDCP4_DCP_DEBUG'; + mmDCP4_GRPH_FLIP_RATE_CNTL :Result:='mmDCP4_GRPH_FLIP_RATE_CNTL'; + mmDCP4_DCP_GSL_CONTROL :Result:='mmDCP4_DCP_GSL_CONTROL'; + mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK :Result:='mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK'; + mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS :Result:='mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS'; + mmDCP4_OVL_STEREOSYNC_FLIP :Result:='mmDCP4_OVL_STEREOSYNC_FLIP'; + mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP4_DCP_TEST_DEBUG_INDEX :Result:='mmDCP4_DCP_TEST_DEBUG_INDEX'; + mmDCP4_DCP_TEST_DEBUG_DATA :Result:='mmDCP4_DCP_TEST_DEBUG_DATA'; + mmDCP4_GRPH_STEREOSYNC_FLIP :Result:='mmDCP4_GRPH_STEREOSYNC_FLIP'; + mmDCP4_DCP_DEBUG2 :Result:='mmDCP4_DCP_DEBUG2'; + mmDCP4_CUR_REQUEST_FILTER_CNTL :Result:='mmDCP4_CUR_REQUEST_FILTER_CNTL'; + mmDCP4_CUR_STEREO_CONTROL :Result:='mmDCP4_CUR_STEREO_CONTROL'; + mmDCP4_CUR2_STEREO_CONTROL :Result:='mmDCP4_CUR2_STEREO_CONTROL'; + mmDCP4_OUT_CLAMP_CONTROL_G_Y :Result:='mmDCP4_OUT_CLAMP_CONTROL_G_Y'; + mmDCP4_OUT_CLAMP_CONTROL_B_CB :Result:='mmDCP4_OUT_CLAMP_CONTROL_B_CB'; + mmDCP4_HW_ROTATION :Result:='mmDCP4_HW_ROTATION'; + mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :Result:='mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL'; + mmDCP4_REGAMMA_CONTROL :Result:='mmDCP4_REGAMMA_CONTROL'; + mmDCP4_REGAMMA_LUT_INDEX :Result:='mmDCP4_REGAMMA_LUT_INDEX'; + mmDCP4_REGAMMA_LUT_DATA :Result:='mmDCP4_REGAMMA_LUT_DATA'; + mmDCP4_REGAMMA_LUT_WRITE_EN_MASK :Result:='mmDCP4_REGAMMA_LUT_WRITE_EN_MASK'; + mmDCP4_REGAMMA_CNTLA_START_CNTL :Result:='mmDCP4_REGAMMA_CNTLA_START_CNTL'; + mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL :Result:='mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL'; + mmDCP4_REGAMMA_CNTLA_END_CNTL1 :Result:='mmDCP4_REGAMMA_CNTLA_END_CNTL1'; + mmDCP4_REGAMMA_CNTLA_END_CNTL2 :Result:='mmDCP4_REGAMMA_CNTLA_END_CNTL2'; + mmDCP4_REGAMMA_CNTLA_REGION_0_1 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_0_1'; + mmDCP4_REGAMMA_CNTLA_REGION_2_3 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_2_3'; + mmDCP4_REGAMMA_CNTLA_REGION_4_5 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_4_5'; + mmDCP4_REGAMMA_CNTLA_REGION_6_7 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_6_7'; + mmDCP4_REGAMMA_CNTLA_REGION_8_9 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_8_9'; + mmDCP4_REGAMMA_CNTLA_REGION_10_11 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_10_11'; + mmDCP4_REGAMMA_CNTLA_REGION_12_13 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_12_13'; + mmDCP4_REGAMMA_CNTLA_REGION_14_15 :Result:='mmDCP4_REGAMMA_CNTLA_REGION_14_15'; + mmDCP4_REGAMMA_CNTLB_START_CNTL :Result:='mmDCP4_REGAMMA_CNTLB_START_CNTL'; + mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL :Result:='mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL'; + mmDCP4_REGAMMA_CNTLB_END_CNTL1 :Result:='mmDCP4_REGAMMA_CNTLB_END_CNTL1'; + mmDCP4_REGAMMA_CNTLB_END_CNTL2 :Result:='mmDCP4_REGAMMA_CNTLB_END_CNTL2'; + mmDCP4_REGAMMA_CNTLB_REGION_0_1 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_0_1'; + mmDCP4_REGAMMA_CNTLB_REGION_2_3 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_2_3'; + mmDCP4_REGAMMA_CNTLB_REGION_4_5 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_4_5'; + mmDCP4_REGAMMA_CNTLB_REGION_6_7 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_6_7'; + mmDCP4_REGAMMA_CNTLB_REGION_8_9 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_8_9'; + mmDCP4_REGAMMA_CNTLB_REGION_10_11 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_10_11'; + mmDCP4_REGAMMA_CNTLB_REGION_12_13 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_12_13'; + mmDCP4_REGAMMA_CNTLB_REGION_14_15 :Result:='mmDCP4_REGAMMA_CNTLB_REGION_14_15'; + mmDCP4_ALPHA_CONTROL :Result:='mmDCP4_ALPHA_CONTROL'; + mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :Result:='mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS'; + mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :Result:='mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH'; + mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :Result:='mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS'; + mmLB4_LB_DATA_FORMAT :Result:='mmLB4_LB_DATA_FORMAT'; + mmLB4_LB_MEMORY_CTRL :Result:='mmLB4_LB_MEMORY_CTRL'; + mmLB4_LB_MEMORY_SIZE_STATUS :Result:='mmLB4_LB_MEMORY_SIZE_STATUS'; + mmLB4_LB_DESKTOP_HEIGHT :Result:='mmLB4_LB_DESKTOP_HEIGHT'; + mmLB4_LB_VLINE_START_END :Result:='mmLB4_LB_VLINE_START_END'; + mmLB4_LB_VLINE2_START_END :Result:='mmLB4_LB_VLINE2_START_END'; + mmLB4_LB_V_COUNTER :Result:='mmLB4_LB_V_COUNTER'; + mmLB4_LB_SNAPSHOT_V_COUNTER :Result:='mmLB4_LB_SNAPSHOT_V_COUNTER'; + mmLB4_LB_INTERRUPT_MASK :Result:='mmLB4_LB_INTERRUPT_MASK'; + mmLB4_LB_VLINE_STATUS :Result:='mmLB4_LB_VLINE_STATUS'; + mmLB4_LB_VLINE2_STATUS :Result:='mmLB4_LB_VLINE2_STATUS'; + mmLB4_LB_VBLANK_STATUS :Result:='mmLB4_LB_VBLANK_STATUS'; + mmLB4_LB_SYNC_RESET_SEL :Result:='mmLB4_LB_SYNC_RESET_SEL'; + mmLB4_LB_BLACK_KEYER_R_CR :Result:='mmLB4_LB_BLACK_KEYER_R_CR'; + mmLB4_LB_BLACK_KEYER_G_Y :Result:='mmLB4_LB_BLACK_KEYER_G_Y'; + mmLB4_LB_BLACK_KEYER_B_CB :Result:='mmLB4_LB_BLACK_KEYER_B_CB'; + mmLB4_LB_KEYER_COLOR_CTRL :Result:='mmLB4_LB_KEYER_COLOR_CTRL'; + mmLB4_LB_KEYER_COLOR_R_CR :Result:='mmLB4_LB_KEYER_COLOR_R_CR'; + mmLB4_LB_KEYER_COLOR_G_Y :Result:='mmLB4_LB_KEYER_COLOR_G_Y'; + mmLB4_LB_KEYER_COLOR_B_CB :Result:='mmLB4_LB_KEYER_COLOR_B_CB'; + mmLB4_LB_KEYER_COLOR_REP_R_CR :Result:='mmLB4_LB_KEYER_COLOR_REP_R_CR'; + mmLB4_LB_KEYER_COLOR_REP_G_Y :Result:='mmLB4_LB_KEYER_COLOR_REP_G_Y'; + mmLB4_LB_KEYER_COLOR_REP_B_CB :Result:='mmLB4_LB_KEYER_COLOR_REP_B_CB'; + mmLB4_LB_BUFFER_LEVEL_STATUS :Result:='mmLB4_LB_BUFFER_LEVEL_STATUS'; + mmLB4_LB_BUFFER_URGENCY_CTRL :Result:='mmLB4_LB_BUFFER_URGENCY_CTRL'; + mmLB4_LB_BUFFER_URGENCY_STATUS :Result:='mmLB4_LB_BUFFER_URGENCY_STATUS'; + mmLB4_LB_BUFFER_STATUS :Result:='mmLB4_LB_BUFFER_STATUS'; + mmLB4_LB_NO_OUTSTANDING_REQ_STATUS :Result:='mmLB4_LB_NO_OUTSTANDING_REQ_STATUS'; + mmLB4_MVP_AFR_FLIP_MODE :Result:='mmLB4_MVP_AFR_FLIP_MODE'; + mmLB4_MVP_AFR_FLIP_FIFO_CNTL :Result:='mmLB4_MVP_AFR_FLIP_FIFO_CNTL'; + mmLB4_MVP_FLIP_LINE_NUM_INSERT :Result:='mmLB4_MVP_FLIP_LINE_NUM_INSERT'; + mmLB4_DC_MVP_LB_CONTROL :Result:='mmLB4_DC_MVP_LB_CONTROL'; + mmLB4_LB_DEBUG :Result:='mmLB4_LB_DEBUG'; + mmLB4_LB_DEBUG2 :Result:='mmLB4_LB_DEBUG2'; + mmLB4_LB_DEBUG3 :Result:='mmLB4_LB_DEBUG3'; + mmLB4_LB_TEST_DEBUG_INDEX :Result:='mmLB4_LB_TEST_DEBUG_INDEX'; + mmLB4_LB_TEST_DEBUG_DATA :Result:='mmLB4_LB_TEST_DEBUG_DATA'; + mmDCFE4_DCFE_CLOCK_CONTROL :Result:='mmDCFE4_DCFE_CLOCK_CONTROL'; + mmDCFE4_DCFE_SOFT_RESET :Result:='mmDCFE4_DCFE_SOFT_RESET'; + mmDCFE4_DCFE_DBG_CONFIG :Result:='mmDCFE4_DCFE_DBG_CONFIG'; + mmDC_PERFMON7_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON7_PERFCOUNTER_CNTL'; + mmDC_PERFMON7_PERFCOUNTER_STATE :Result:='mmDC_PERFMON7_PERFCOUNTER_STATE'; + mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON7_PERFMON_CNTL :Result:='mmDC_PERFMON7_PERFMON_CNTL'; + mmDC_PERFMON7_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON7_PERFMON_CVALUE_LOW'; + mmDC_PERFMON7_PERFMON_HI :Result:='mmDC_PERFMON7_PERFMON_HI'; + mmDC_PERFMON7_PERFMON_LOW :Result:='mmDC_PERFMON7_PERFMON_LOW'; + mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON7_PERFMON_CNTL2 :Result:='mmDC_PERFMON7_PERFMON_CNTL2'; + mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 :Result:='mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1'; + mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 :Result:='mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2'; + mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL :Result:='mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL'; + mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL :Result:='mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL'; + mmDMIF_PG4_DPG_PIPE_DPM_CONTROL :Result:='mmDMIF_PG4_DPG_PIPE_DPM_CONTROL'; + mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL :Result:='mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL'; + mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :Result:='mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL'; + mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :Result:='mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH'; + mmDMIF_PG4_DPG_TEST_DEBUG_INDEX :Result:='mmDMIF_PG4_DPG_TEST_DEBUG_INDEX'; + mmDMIF_PG4_DPG_TEST_DEBUG_DATA :Result:='mmDMIF_PG4_DPG_TEST_DEBUG_DATA'; + mmDMIF_PG4_DPG_REPEATER_PROGRAM :Result:='mmDMIF_PG4_DPG_REPEATER_PROGRAM'; + mmDMIF_PG4_DPG_HW_DEBUG_A :Result:='mmDMIF_PG4_DPG_HW_DEBUG_A'; + mmDMIF_PG4_DPG_HW_DEBUG_B :Result:='mmDMIF_PG4_DPG_HW_DEBUG_B'; + mmDMIF_PG4_DPG_HW_DEBUG_11 :Result:='mmDMIF_PG4_DPG_HW_DEBUG_11'; + mmSCL4_SCL_COEF_RAM_SELECT :Result:='mmSCL4_SCL_COEF_RAM_SELECT'; + mmSCL4_SCL_COEF_RAM_TAP_DATA :Result:='mmSCL4_SCL_COEF_RAM_TAP_DATA'; + mmSCL4_SCL_MODE :Result:='mmSCL4_SCL_MODE'; + mmSCL4_SCL_TAP_CONTROL :Result:='mmSCL4_SCL_TAP_CONTROL'; + mmSCL4_SCL_CONTROL :Result:='mmSCL4_SCL_CONTROL'; + mmSCL4_SCL_BYPASS_CONTROL :Result:='mmSCL4_SCL_BYPASS_CONTROL'; + mmSCL4_SCL_MANUAL_REPLICATE_CONTROL :Result:='mmSCL4_SCL_MANUAL_REPLICATE_CONTROL'; + mmSCL4_SCL_AUTOMATIC_MODE_CONTROL :Result:='mmSCL4_SCL_AUTOMATIC_MODE_CONTROL'; + mmSCL4_SCL_HORZ_FILTER_CONTROL :Result:='mmSCL4_SCL_HORZ_FILTER_CONTROL'; + mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO :Result:='mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO'; + mmSCL4_SCL_HORZ_FILTER_INIT :Result:='mmSCL4_SCL_HORZ_FILTER_INIT'; + mmSCL4_SCL_VERT_FILTER_CONTROL :Result:='mmSCL4_SCL_VERT_FILTER_CONTROL'; + mmSCL4_SCL_VERT_FILTER_SCALE_RATIO :Result:='mmSCL4_SCL_VERT_FILTER_SCALE_RATIO'; + mmSCL4_SCL_VERT_FILTER_INIT :Result:='mmSCL4_SCL_VERT_FILTER_INIT'; + mmSCL4_SCL_VERT_FILTER_INIT_BOT :Result:='mmSCL4_SCL_VERT_FILTER_INIT_BOT'; + mmSCL4_SCL_ROUND_OFFSET :Result:='mmSCL4_SCL_ROUND_OFFSET'; + mmSCL4_SCL_UPDATE :Result:='mmSCL4_SCL_UPDATE'; + mmSCL4_SCL_F_SHARP_CONTROL :Result:='mmSCL4_SCL_F_SHARP_CONTROL'; + mmSCL4_SCL_ALU_CONTROL :Result:='mmSCL4_SCL_ALU_CONTROL'; + mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS :Result:='mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS'; + mmSCL4_VIEWPORT_START_SECONDARY :Result:='mmSCL4_VIEWPORT_START_SECONDARY'; + mmSCL4_VIEWPORT_START :Result:='mmSCL4_VIEWPORT_START'; + mmSCL4_VIEWPORT_SIZE :Result:='mmSCL4_VIEWPORT_SIZE'; + mmSCL4_EXT_OVERSCAN_LEFT_RIGHT :Result:='mmSCL4_EXT_OVERSCAN_LEFT_RIGHT'; + mmSCL4_EXT_OVERSCAN_TOP_BOTTOM :Result:='mmSCL4_EXT_OVERSCAN_TOP_BOTTOM'; + mmSCL4_SCL_MODE_CHANGE_DET1 :Result:='mmSCL4_SCL_MODE_CHANGE_DET1'; + mmSCL4_SCL_MODE_CHANGE_DET2 :Result:='mmSCL4_SCL_MODE_CHANGE_DET2'; + mmSCL4_SCL_MODE_CHANGE_DET3 :Result:='mmSCL4_SCL_MODE_CHANGE_DET3'; + mmSCL4_SCL_MODE_CHANGE_MASK :Result:='mmSCL4_SCL_MODE_CHANGE_MASK'; + mmSCL4_SCL_DEBUG2 :Result:='mmSCL4_SCL_DEBUG2'; + mmSCL4_SCL_DEBUG :Result:='mmSCL4_SCL_DEBUG'; + mmSCL4_SCL_TEST_DEBUG_INDEX :Result:='mmSCL4_SCL_TEST_DEBUG_INDEX'; + mmSCL4_SCL_TEST_DEBUG_DATA :Result:='mmSCL4_SCL_TEST_DEBUG_DATA'; + mmBLND4_BLND_CONTROL :Result:='mmBLND4_BLND_CONTROL'; + mmBLND4_SM_CONTROL2 :Result:='mmBLND4_SM_CONTROL2'; + mmBLND4_BLND_CONTROL2 :Result:='mmBLND4_BLND_CONTROL2'; + mmBLND4_BLND_UPDATE :Result:='mmBLND4_BLND_UPDATE'; + mmBLND4_BLND_UNDERFLOW_INTERRUPT :Result:='mmBLND4_BLND_UNDERFLOW_INTERRUPT'; + mmBLND4_BLND_V_UPDATE_LOCK :Result:='mmBLND4_BLND_V_UPDATE_LOCK'; + mmBLND4_BLND_DEBUG :Result:='mmBLND4_BLND_DEBUG'; + mmBLND4_BLND_TEST_DEBUG_INDEX :Result:='mmBLND4_BLND_TEST_DEBUG_INDEX'; + mmBLND4_BLND_TEST_DEBUG_DATA :Result:='mmBLND4_BLND_TEST_DEBUG_DATA'; + mmBLND4_BLND_REG_UPDATE_STATUS :Result:='mmBLND4_BLND_REG_UPDATE_STATUS'; + mmCRTC4_CRTC_3D_STRUCTURE_CONTROL :Result:='mmCRTC4_CRTC_3D_STRUCTURE_CONTROL'; + mmCRTC4_CRTC_GSL_VSYNC_GAP :Result:='mmCRTC4_CRTC_GSL_VSYNC_GAP'; + mmCRTC4_CRTC_GSL_WINDOW :Result:='mmCRTC4_CRTC_GSL_WINDOW'; + mmCRTC4_CRTC_GSL_CONTROL :Result:='mmCRTC4_CRTC_GSL_CONTROL'; + mmCRTC4_CRTC_DCFE_CLOCK_CONTROL :Result:='mmCRTC4_CRTC_DCFE_CLOCK_CONTROL'; + mmCRTC4_CRTC_H_BLANK_EARLY_NUM :Result:='mmCRTC4_CRTC_H_BLANK_EARLY_NUM'; + mmCRTC4_DCFE_DBG_SEL :Result:='mmCRTC4_DCFE_DBG_SEL'; + mmCRTC4_DCFE_MEM_PWR_CTRL :Result:='mmCRTC4_DCFE_MEM_PWR_CTRL'; + mmCRTC4_CRTC_V_TOTAL_CONTROL :Result:='mmCRTC4_CRTC_V_TOTAL_CONTROL'; + mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS :Result:='mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS'; + mmCRTC4_CRTC_V_SYNC_A :Result:='mmCRTC4_CRTC_V_SYNC_A'; + mmCRTC4_CRTC_V_SYNC_A_CNTL :Result:='mmCRTC4_CRTC_V_SYNC_A_CNTL'; + mmCRTC4_CRTC_V_SYNC_B :Result:='mmCRTC4_CRTC_V_SYNC_B'; + mmCRTC4_CRTC_DTMTEST_CNTL :Result:='mmCRTC4_CRTC_DTMTEST_CNTL'; + mmCRTC4_CRTC_DTMTEST_STATUS_POSITION :Result:='mmCRTC4_CRTC_DTMTEST_STATUS_POSITION'; + mmCRTC4_CRTC_TRIGA_CNTL :Result:='mmCRTC4_CRTC_TRIGA_CNTL'; + mmCRTC4_CRTC_TRIGB_MANUAL_TRIG :Result:='mmCRTC4_CRTC_TRIGB_MANUAL_TRIG'; + mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL :Result:='mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL'; + mmCRTC4_CRTC_FLOW_CONTROL :Result:='mmCRTC4_CRTC_FLOW_CONTROL'; + mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE :Result:='mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE'; + mmCRTC4_CRTC_AVSYNC_COUNTER :Result:='mmCRTC4_CRTC_AVSYNC_COUNTER'; + mmCRTC4_CRTC_CONTROL :Result:='mmCRTC4_CRTC_CONTROL'; + mmCRTC4_CRTC_BLANK_CONTROL :Result:='mmCRTC4_CRTC_BLANK_CONTROL'; + mmCRTC4_CRTC_INTERLACE_CONTROL :Result:='mmCRTC4_CRTC_INTERLACE_CONTROL'; + mmCRTC4_CRTC_INTERLACE_STATUS :Result:='mmCRTC4_CRTC_INTERLACE_STATUS'; + mmCRTC4_CRTC_FIELD_INDICATION_CONTROL :Result:='mmCRTC4_CRTC_FIELD_INDICATION_CONTROL'; + mmCRTC4_CRTC_PIXEL_DATA_READBACK0 :Result:='mmCRTC4_CRTC_PIXEL_DATA_READBACK0'; + mmCRTC4_CRTC_PIXEL_DATA_READBACK1 :Result:='mmCRTC4_CRTC_PIXEL_DATA_READBACK1'; + mmCRTC4_CRTC_STATUS :Result:='mmCRTC4_CRTC_STATUS'; + mmCRTC4_CRTC_STATUS_POSITION :Result:='mmCRTC4_CRTC_STATUS_POSITION'; + mmCRTC4_CRTC_NOM_VERT_POSITION :Result:='mmCRTC4_CRTC_NOM_VERT_POSITION'; + mmCRTC4_CRTC_STATUS_FRAME_COUNT :Result:='mmCRTC4_CRTC_STATUS_FRAME_COUNT'; + mmCRTC4_CRTC_STATUS_VF_COUNT :Result:='mmCRTC4_CRTC_STATUS_VF_COUNT'; + mmCRTC4_CRTC_STATUS_HV_COUNT :Result:='mmCRTC4_CRTC_STATUS_HV_COUNT'; + mmCRTC4_CRTC_COUNT_CONTROL :Result:='mmCRTC4_CRTC_COUNT_CONTROL'; + mmCRTC4_CRTC_COUNT_RESET :Result:='mmCRTC4_CRTC_COUNT_RESET'; + mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :Result:='mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE'; + mmCRTC4_CRTC_VERT_SYNC_CONTROL :Result:='mmCRTC4_CRTC_VERT_SYNC_CONTROL'; + mmCRTC4_CRTC_STEREO_STATUS :Result:='mmCRTC4_CRTC_STEREO_STATUS'; + mmCRTC4_CRTC_STEREO_CONTROL :Result:='mmCRTC4_CRTC_STEREO_CONTROL'; + mmCRTC4_CRTC_SNAPSHOT_STATUS :Result:='mmCRTC4_CRTC_SNAPSHOT_STATUS'; + mmCRTC4_CRTC_SNAPSHOT_CONTROL :Result:='mmCRTC4_CRTC_SNAPSHOT_CONTROL'; + mmCRTC4_CRTC_SNAPSHOT_POSITION :Result:='mmCRTC4_CRTC_SNAPSHOT_POSITION'; + mmCRTC4_CRTC_SNAPSHOT_FRAME :Result:='mmCRTC4_CRTC_SNAPSHOT_FRAME'; + mmCRTC4_CRTC_START_LINE_CONTROL :Result:='mmCRTC4_CRTC_START_LINE_CONTROL'; + mmCRTC4_CRTC_INTERRUPT_CONTROL :Result:='mmCRTC4_CRTC_INTERRUPT_CONTROL'; + mmCRTC4_CRTC_UPDATE_LOCK :Result:='mmCRTC4_CRTC_UPDATE_LOCK'; + mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL :Result:='mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL'; + mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE :Result:='mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE'; + mmCRTC4_DCFE_MEM_PWR_CTRL2 :Result:='mmCRTC4_DCFE_MEM_PWR_CTRL2'; + mmCRTC4_DCFE_MEM_PWR_STATUS :Result:='mmCRTC4_DCFE_MEM_PWR_STATUS'; + mmCRTC4_CRTC_TEST_PATTERN_CONTROL :Result:='mmCRTC4_CRTC_TEST_PATTERN_CONTROL'; + mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS :Result:='mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS'; + mmCRTC4_CRTC_TEST_PATTERN_COLOR :Result:='mmCRTC4_CRTC_TEST_PATTERN_COLOR'; + mmCRTC4_MASTER_UPDATE_LOCK :Result:='mmCRTC4_MASTER_UPDATE_LOCK'; + mmCRTC4_MASTER_UPDATE_MODE :Result:='mmCRTC4_MASTER_UPDATE_MODE'; + mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT :Result:='mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT'; + mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :Result:='mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER'; + mmCRTC4_CRTC_MVP_STATUS :Result:='mmCRTC4_CRTC_MVP_STATUS'; + mmCRTC4_CRTC_MASTER_EN :Result:='mmCRTC4_CRTC_MASTER_EN'; + mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT :Result:='mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT'; + mmCRTC4_CRTC_V_UPDATE_INT_STATUS :Result:='mmCRTC4_CRTC_V_UPDATE_INT_STATUS'; + mmCRTC4_CRTC_TEST_DEBUG_INDEX :Result:='mmCRTC4_CRTC_TEST_DEBUG_INDEX'; + mmCRTC4_CRTC_TEST_DEBUG_DATA :Result:='mmCRTC4_CRTC_TEST_DEBUG_DATA'; + mmCRTC4_CRTC_OVERSCAN_COLOR :Result:='mmCRTC4_CRTC_OVERSCAN_COLOR'; + mmCRTC4_CRTC_OVERSCAN_COLOR_EXT :Result:='mmCRTC4_CRTC_OVERSCAN_COLOR_EXT'; + mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT :Result:='mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT'; + mmCRTC4_CRTC_BLACK_COLOR :Result:='mmCRTC4_CRTC_BLACK_COLOR'; + mmCRTC4_CRTC_BLACK_COLOR_EXT :Result:='mmCRTC4_CRTC_BLACK_COLOR_EXT'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION'; + mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL :Result:='mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL'; + mmCRTC4_CRTC_CRC_CNTL :Result:='mmCRTC4_CRTC_CRC_CNTL'; + mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL :Result:='mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL'; + mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL :Result:='mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL'; + mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL :Result:='mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL'; + mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL :Result:='mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL'; + mmCRTC4_CRTC_CRC0_DATA_RG :Result:='mmCRTC4_CRTC_CRC0_DATA_RG'; + mmCRTC4_CRTC_CRC0_DATA_B :Result:='mmCRTC4_CRTC_CRC0_DATA_B'; + mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL :Result:='mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL'; + mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL :Result:='mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL'; + mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL :Result:='mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL'; + mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL :Result:='mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL'; + mmCRTC4_CRTC_CRC1_DATA_RG :Result:='mmCRTC4_CRTC_CRC1_DATA_RG'; + mmCRTC4_CRTC_CRC1_DATA_B :Result:='mmCRTC4_CRTC_CRC1_DATA_B'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL'; + mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :Result:='mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL'; + mmCRTC4_CRTC_STATIC_SCREEN_CONTROL :Result:='mmCRTC4_CRTC_STATIC_SCREEN_CONTROL'; + mmFMT4_FMT_CLAMP_COMPONENT_R :Result:='mmFMT4_FMT_CLAMP_COMPONENT_R'; + mmFMT4_FMT_CLAMP_COMPONENT_G :Result:='mmFMT4_FMT_CLAMP_COMPONENT_G'; + mmFMT4_FMT_CLAMP_COMPONENT_B :Result:='mmFMT4_FMT_CLAMP_COMPONENT_B'; + mmFMT4_FMT_TEST_DEBUG_INDEX :Result:='mmFMT4_FMT_TEST_DEBUG_INDEX'; + mmFMT4_FMT_TEST_DEBUG_DATA :Result:='mmFMT4_FMT_TEST_DEBUG_DATA'; + mmFMT4_FMT_DYNAMIC_EXP_CNTL :Result:='mmFMT4_FMT_DYNAMIC_EXP_CNTL'; + mmFMT4_FMT_CONTROL :Result:='mmFMT4_FMT_CONTROL'; + mmFMT4_FMT_FORCE_OUTPUT_CNTL :Result:='mmFMT4_FMT_FORCE_OUTPUT_CNTL'; + mmFMT4_FMT_FORCE_DATA_0_1 :Result:='mmFMT4_FMT_FORCE_DATA_0_1'; + mmFMT4_FMT_FORCE_DATA_2_3 :Result:='mmFMT4_FMT_FORCE_DATA_2_3'; + mmFMT4_FMT_BIT_DEPTH_CONTROL :Result:='mmFMT4_FMT_BIT_DEPTH_CONTROL'; + mmFMT4_FMT_DITHER_RAND_R_SEED :Result:='mmFMT4_FMT_DITHER_RAND_R_SEED'; + mmFMT4_FMT_DITHER_RAND_G_SEED :Result:='mmFMT4_FMT_DITHER_RAND_G_SEED'; + mmFMT4_FMT_DITHER_RAND_B_SEED :Result:='mmFMT4_FMT_DITHER_RAND_B_SEED'; + mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL'; + mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX'; + mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX'; + mmFMT4_FMT_CLAMP_CNTL :Result:='mmFMT4_FMT_CLAMP_CNTL'; + mmFMT4_FMT_CRC_CNTL :Result:='mmFMT4_FMT_CRC_CNTL'; + mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK :Result:='mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK'; + mmFMT4_FMT_CRC_SIG_RED_GREEN :Result:='mmFMT4_FMT_CRC_SIG_RED_GREEN'; + mmDCP5_GRPH_ENABLE :Result:='mmDCP5_GRPH_ENABLE'; + mmDCP5_GRPH_CONTROL :Result:='mmDCP5_GRPH_CONTROL'; + mmDCP5_GRPH_LUT_10BIT_BYPASS :Result:='mmDCP5_GRPH_LUT_10BIT_BYPASS'; + mmDCP5_GRPH_SWAP_CNTL :Result:='mmDCP5_GRPH_SWAP_CNTL'; + mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS :Result:='mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS'; + mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS :Result:='mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS'; + mmDCP5_GRPH_PITCH :Result:='mmDCP5_GRPH_PITCH'; + mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH'; + mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP5_GRPH_SURFACE_OFFSET_X :Result:='mmDCP5_GRPH_SURFACE_OFFSET_X'; + mmDCP5_GRPH_SURFACE_OFFSET_Y :Result:='mmDCP5_GRPH_SURFACE_OFFSET_Y'; + mmDCP5_GRPH_X_START :Result:='mmDCP5_GRPH_X_START'; + mmDCP5_GRPH_Y_START :Result:='mmDCP5_GRPH_Y_START'; + mmDCP5_GRPH_X_END :Result:='mmDCP5_GRPH_X_END'; + mmDCP5_GRPH_Y_END :Result:='mmDCP5_GRPH_Y_END'; + mmDCP5_INPUT_GAMMA_CONTROL :Result:='mmDCP5_INPUT_GAMMA_CONTROL'; + mmDCP5_GRPH_UPDATE :Result:='mmDCP5_GRPH_UPDATE'; + mmDCP5_GRPH_FLIP_CONTROL :Result:='mmDCP5_GRPH_FLIP_CONTROL'; + mmDCP5_GRPH_SURFACE_ADDRESS_INUSE :Result:='mmDCP5_GRPH_SURFACE_ADDRESS_INUSE'; + mmDCP5_GRPH_DFQ_CONTROL :Result:='mmDCP5_GRPH_DFQ_CONTROL'; + mmDCP5_GRPH_DFQ_STATUS :Result:='mmDCP5_GRPH_DFQ_STATUS'; + mmDCP5_GRPH_INTERRUPT_STATUS :Result:='mmDCP5_GRPH_INTERRUPT_STATUS'; + mmDCP5_GRPH_INTERRUPT_CONTROL :Result:='mmDCP5_GRPH_INTERRUPT_CONTROL'; + mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE :Result:='mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE'; + mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS :Result:='mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS'; + mmDCP5_GRPH_COMPRESS_PITCH :Result:='mmDCP5_GRPH_COMPRESS_PITCH'; + mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH'; + mmDCP5_OVL_ENABLE :Result:='mmDCP5_OVL_ENABLE'; + mmDCP5_OVL_CONTROL1 :Result:='mmDCP5_OVL_CONTROL1'; + mmDCP5_OVL_CONTROL2 :Result:='mmDCP5_OVL_CONTROL2'; + mmDCP5_OVL_SWAP_CNTL :Result:='mmDCP5_OVL_SWAP_CNTL'; + mmDCP5_OVL_SURFACE_ADDRESS :Result:='mmDCP5_OVL_SURFACE_ADDRESS'; + mmDCP5_OVL_PITCH :Result:='mmDCP5_OVL_PITCH'; + mmDCP5_OVL_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_OVL_SURFACE_ADDRESS_HIGH'; + mmDCP5_OVL_SURFACE_OFFSET_X :Result:='mmDCP5_OVL_SURFACE_OFFSET_X'; + mmDCP5_OVL_SURFACE_OFFSET_Y :Result:='mmDCP5_OVL_SURFACE_OFFSET_Y'; + mmDCP5_OVL_START :Result:='mmDCP5_OVL_START'; + mmDCP5_OVL_END :Result:='mmDCP5_OVL_END'; + mmDCP5_OVL_UPDATE :Result:='mmDCP5_OVL_UPDATE'; + mmDCP5_OVL_SURFACE_ADDRESS_INUSE :Result:='mmDCP5_OVL_SURFACE_ADDRESS_INUSE'; + mmDCP5_OVL_DFQ_CONTROL :Result:='mmDCP5_OVL_DFQ_CONTROL'; + mmDCP5_OVL_DFQ_STATUS :Result:='mmDCP5_OVL_DFQ_STATUS'; + mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE :Result:='mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE'; + mmDCP5_OVLSCL_EDGE_PIXEL_CNTL :Result:='mmDCP5_OVLSCL_EDGE_PIXEL_CNTL'; + mmDCP5_PRESCALE_GRPH_CONTROL :Result:='mmDCP5_PRESCALE_GRPH_CONTROL'; + mmDCP5_PRESCALE_VALUES_GRPH_R :Result:='mmDCP5_PRESCALE_VALUES_GRPH_R'; + mmDCP5_PRESCALE_VALUES_GRPH_G :Result:='mmDCP5_PRESCALE_VALUES_GRPH_G'; + mmDCP5_PRESCALE_VALUES_GRPH_B :Result:='mmDCP5_PRESCALE_VALUES_GRPH_B'; + mmDCP5_PRESCALE_OVL_CONTROL :Result:='mmDCP5_PRESCALE_OVL_CONTROL'; + mmDCP5_PRESCALE_VALUES_OVL_CB :Result:='mmDCP5_PRESCALE_VALUES_OVL_CB'; + mmDCP5_PRESCALE_VALUES_OVL_Y :Result:='mmDCP5_PRESCALE_VALUES_OVL_Y'; + mmDCP5_PRESCALE_VALUES_OVL_CR :Result:='mmDCP5_PRESCALE_VALUES_OVL_CR'; + mmDCP5_INPUT_CSC_CONTROL :Result:='mmDCP5_INPUT_CSC_CONTROL'; + mmDCP5_INPUT_CSC_C11_C12 :Result:='mmDCP5_INPUT_CSC_C11_C12'; + mmDCP5_INPUT_CSC_C13_C14 :Result:='mmDCP5_INPUT_CSC_C13_C14'; + mmDCP5_INPUT_CSC_C21_C22 :Result:='mmDCP5_INPUT_CSC_C21_C22'; + mmDCP5_INPUT_CSC_C23_C24 :Result:='mmDCP5_INPUT_CSC_C23_C24'; + mmDCP5_INPUT_CSC_C31_C32 :Result:='mmDCP5_INPUT_CSC_C31_C32'; + mmDCP5_INPUT_CSC_C33_C34 :Result:='mmDCP5_INPUT_CSC_C33_C34'; + mmDCP5_OUTPUT_CSC_CONTROL :Result:='mmDCP5_OUTPUT_CSC_CONTROL'; + mmDCP5_OUTPUT_CSC_C11_C12 :Result:='mmDCP5_OUTPUT_CSC_C11_C12'; + mmDCP5_OUTPUT_CSC_C13_C14 :Result:='mmDCP5_OUTPUT_CSC_C13_C14'; + mmDCP5_OUTPUT_CSC_C21_C22 :Result:='mmDCP5_OUTPUT_CSC_C21_C22'; + mmDCP5_OUTPUT_CSC_C23_C24 :Result:='mmDCP5_OUTPUT_CSC_C23_C24'; + mmDCP5_OUTPUT_CSC_C31_C32 :Result:='mmDCP5_OUTPUT_CSC_C31_C32'; + mmDCP5_OUTPUT_CSC_C33_C34 :Result:='mmDCP5_OUTPUT_CSC_C33_C34'; + mmDCP5_COMM_MATRIXA_TRANS_C11_C12 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C11_C12'; + mmDCP5_COMM_MATRIXA_TRANS_C13_C14 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C13_C14'; + mmDCP5_COMM_MATRIXA_TRANS_C21_C22 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C21_C22'; + mmDCP5_COMM_MATRIXA_TRANS_C23_C24 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C23_C24'; + mmDCP5_COMM_MATRIXA_TRANS_C31_C32 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C31_C32'; + mmDCP5_COMM_MATRIXA_TRANS_C33_C34 :Result:='mmDCP5_COMM_MATRIXA_TRANS_C33_C34'; + mmDCP5_COMM_MATRIXB_TRANS_C11_C12 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C11_C12'; + mmDCP5_COMM_MATRIXB_TRANS_C13_C14 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C13_C14'; + mmDCP5_COMM_MATRIXB_TRANS_C21_C22 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C21_C22'; + mmDCP5_COMM_MATRIXB_TRANS_C23_C24 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C23_C24'; + mmDCP5_COMM_MATRIXB_TRANS_C31_C32 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C31_C32'; + mmDCP5_COMM_MATRIXB_TRANS_C33_C34 :Result:='mmDCP5_COMM_MATRIXB_TRANS_C33_C34'; + mmDCP5_DENORM_CONTROL :Result:='mmDCP5_DENORM_CONTROL'; + mmDCP5_OUT_ROUND_CONTROL :Result:='mmDCP5_OUT_ROUND_CONTROL'; + mmDCP5_OUT_CLAMP_CONTROL_R_CR :Result:='mmDCP5_OUT_CLAMP_CONTROL_R_CR'; + mmDCP5_KEY_CONTROL :Result:='mmDCP5_KEY_CONTROL'; + mmDCP5_KEY_RANGE_ALPHA :Result:='mmDCP5_KEY_RANGE_ALPHA'; + mmDCP5_KEY_RANGE_RED :Result:='mmDCP5_KEY_RANGE_RED'; + mmDCP5_KEY_RANGE_GREEN :Result:='mmDCP5_KEY_RANGE_GREEN'; + mmDCP5_KEY_RANGE_BLUE :Result:='mmDCP5_KEY_RANGE_BLUE'; + mmDCP5_DEGAMMA_CONTROL :Result:='mmDCP5_DEGAMMA_CONTROL'; + mmDCP5_GAMUT_REMAP_CONTROL :Result:='mmDCP5_GAMUT_REMAP_CONTROL'; + mmDCP5_GAMUT_REMAP_C11_C12 :Result:='mmDCP5_GAMUT_REMAP_C11_C12'; + mmDCP5_GAMUT_REMAP_C13_C14 :Result:='mmDCP5_GAMUT_REMAP_C13_C14'; + mmDCP5_GAMUT_REMAP_C21_C22 :Result:='mmDCP5_GAMUT_REMAP_C21_C22'; + mmDCP5_GAMUT_REMAP_C23_C24 :Result:='mmDCP5_GAMUT_REMAP_C23_C24'; + mmDCP5_GAMUT_REMAP_C31_C32 :Result:='mmDCP5_GAMUT_REMAP_C31_C32'; + mmDCP5_GAMUT_REMAP_C33_C34 :Result:='mmDCP5_GAMUT_REMAP_C33_C34'; + mmDCP5_DCP_SPATIAL_DITHER_CNTL :Result:='mmDCP5_DCP_SPATIAL_DITHER_CNTL'; + mmDCP5_DCP_RANDOM_SEEDS :Result:='mmDCP5_DCP_RANDOM_SEEDS'; + mmDCP5_DCP_FP_CONVERTED_FIELD :Result:='mmDCP5_DCP_FP_CONVERTED_FIELD'; + mmDCP5_CUR_CONTROL :Result:='mmDCP5_CUR_CONTROL'; + mmDCP5_CUR_SURFACE_ADDRESS :Result:='mmDCP5_CUR_SURFACE_ADDRESS'; + mmDCP5_CUR_SIZE :Result:='mmDCP5_CUR_SIZE'; + mmDCP5_CUR_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_CUR_SURFACE_ADDRESS_HIGH'; + mmDCP5_CUR_POSITION :Result:='mmDCP5_CUR_POSITION'; + mmDCP5_CUR_HOT_SPOT :Result:='mmDCP5_CUR_HOT_SPOT'; + mmDCP5_CUR_COLOR1 :Result:='mmDCP5_CUR_COLOR1'; + mmDCP5_CUR_COLOR2 :Result:='mmDCP5_CUR_COLOR2'; + mmDCP5_CUR_UPDATE :Result:='mmDCP5_CUR_UPDATE'; + mmDCP5_CUR2_CONTROL :Result:='mmDCP5_CUR2_CONTROL'; + mmDCP5_CUR2_SURFACE_ADDRESS :Result:='mmDCP5_CUR2_SURFACE_ADDRESS'; + mmDCP5_CUR2_SIZE :Result:='mmDCP5_CUR2_SIZE'; + mmDCP5_CUR2_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_CUR2_SURFACE_ADDRESS_HIGH'; + mmDCP5_CUR2_POSITION :Result:='mmDCP5_CUR2_POSITION'; + mmDCP5_CUR2_HOT_SPOT :Result:='mmDCP5_CUR2_HOT_SPOT'; + mmDCP5_CUR2_COLOR1 :Result:='mmDCP5_CUR2_COLOR1'; + mmDCP5_CUR2_COLOR2 :Result:='mmDCP5_CUR2_COLOR2'; + mmDCP5_CUR2_UPDATE :Result:='mmDCP5_CUR2_UPDATE'; + mmDCP5_DC_LUT_RW_MODE :Result:='mmDCP5_DC_LUT_RW_MODE'; + mmDCP5_DC_LUT_RW_INDEX :Result:='mmDCP5_DC_LUT_RW_INDEX'; + mmDCP5_DC_LUT_SEQ_COLOR :Result:='mmDCP5_DC_LUT_SEQ_COLOR'; + mmDCP5_DC_LUT_PWL_DATA :Result:='mmDCP5_DC_LUT_PWL_DATA'; + mmDCP5_DC_LUT_30_COLOR :Result:='mmDCP5_DC_LUT_30_COLOR'; + mmDCP5_DC_LUT_VGA_ACCESS_ENABLE :Result:='mmDCP5_DC_LUT_VGA_ACCESS_ENABLE'; + mmDCP5_DC_LUT_WRITE_EN_MASK :Result:='mmDCP5_DC_LUT_WRITE_EN_MASK'; + mmDCP5_DC_LUT_AUTOFILL :Result:='mmDCP5_DC_LUT_AUTOFILL'; + mmDCP5_DC_LUT_CONTROL :Result:='mmDCP5_DC_LUT_CONTROL'; + mmDCP5_DC_LUT_BLACK_OFFSET_BLUE :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_BLUE'; + mmDCP5_DC_LUT_BLACK_OFFSET_GREEN :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_GREEN'; + mmDCP5_DC_LUT_BLACK_OFFSET_RED :Result:='mmDCP5_DC_LUT_BLACK_OFFSET_RED'; + mmDCP5_DC_LUT_WHITE_OFFSET_BLUE :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_BLUE'; + mmDCP5_DC_LUT_WHITE_OFFSET_GREEN :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_GREEN'; + mmDCP5_DC_LUT_WHITE_OFFSET_RED :Result:='mmDCP5_DC_LUT_WHITE_OFFSET_RED'; + mmDCP5_DCP_CRC_CONTROL :Result:='mmDCP5_DCP_CRC_CONTROL'; + mmDCP5_DCP_CRC_MASK :Result:='mmDCP5_DCP_CRC_MASK'; + mmDCP5_DCP_CRC_CURRENT :Result:='mmDCP5_DCP_CRC_CURRENT'; + mmDCP5_DCP_CRC_LAST :Result:='mmDCP5_DCP_CRC_LAST'; + mmDCP5_DCP_DEBUG :Result:='mmDCP5_DCP_DEBUG'; + mmDCP5_GRPH_FLIP_RATE_CNTL :Result:='mmDCP5_GRPH_FLIP_RATE_CNTL'; + mmDCP5_DCP_GSL_CONTROL :Result:='mmDCP5_DCP_GSL_CONTROL'; + mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK :Result:='mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK'; + mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS :Result:='mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS'; + mmDCP5_OVL_STEREOSYNC_FLIP :Result:='mmDCP5_OVL_STEREOSYNC_FLIP'; + mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH'; + mmDCP5_DCP_TEST_DEBUG_INDEX :Result:='mmDCP5_DCP_TEST_DEBUG_INDEX'; + mmDCP5_DCP_TEST_DEBUG_DATA :Result:='mmDCP5_DCP_TEST_DEBUG_DATA'; + mmDCP5_GRPH_STEREOSYNC_FLIP :Result:='mmDCP5_GRPH_STEREOSYNC_FLIP'; + mmDCP5_DCP_DEBUG2 :Result:='mmDCP5_DCP_DEBUG2'; + mmDCP5_CUR_REQUEST_FILTER_CNTL :Result:='mmDCP5_CUR_REQUEST_FILTER_CNTL'; + mmDCP5_CUR_STEREO_CONTROL :Result:='mmDCP5_CUR_STEREO_CONTROL'; + mmDCP5_CUR2_STEREO_CONTROL :Result:='mmDCP5_CUR2_STEREO_CONTROL'; + mmDCP5_OUT_CLAMP_CONTROL_G_Y :Result:='mmDCP5_OUT_CLAMP_CONTROL_G_Y'; + mmDCP5_OUT_CLAMP_CONTROL_B_CB :Result:='mmDCP5_OUT_CLAMP_CONTROL_B_CB'; + mmDCP5_HW_ROTATION :Result:='mmDCP5_HW_ROTATION'; + mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL :Result:='mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL'; + mmDCP5_REGAMMA_CONTROL :Result:='mmDCP5_REGAMMA_CONTROL'; + mmDCP5_REGAMMA_LUT_INDEX :Result:='mmDCP5_REGAMMA_LUT_INDEX'; + mmDCP5_REGAMMA_LUT_DATA :Result:='mmDCP5_REGAMMA_LUT_DATA'; + mmDCP5_REGAMMA_LUT_WRITE_EN_MASK :Result:='mmDCP5_REGAMMA_LUT_WRITE_EN_MASK'; + mmDCP5_REGAMMA_CNTLA_START_CNTL :Result:='mmDCP5_REGAMMA_CNTLA_START_CNTL'; + mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL :Result:='mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL'; + mmDCP5_REGAMMA_CNTLA_END_CNTL1 :Result:='mmDCP5_REGAMMA_CNTLA_END_CNTL1'; + mmDCP5_REGAMMA_CNTLA_END_CNTL2 :Result:='mmDCP5_REGAMMA_CNTLA_END_CNTL2'; + mmDCP5_REGAMMA_CNTLA_REGION_0_1 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_0_1'; + mmDCP5_REGAMMA_CNTLA_REGION_2_3 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_2_3'; + mmDCP5_REGAMMA_CNTLA_REGION_4_5 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_4_5'; + mmDCP5_REGAMMA_CNTLA_REGION_6_7 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_6_7'; + mmDCP5_REGAMMA_CNTLA_REGION_8_9 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_8_9'; + mmDCP5_REGAMMA_CNTLA_REGION_10_11 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_10_11'; + mmDCP5_REGAMMA_CNTLA_REGION_12_13 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_12_13'; + mmDCP5_REGAMMA_CNTLA_REGION_14_15 :Result:='mmDCP5_REGAMMA_CNTLA_REGION_14_15'; + mmDCP5_REGAMMA_CNTLB_START_CNTL :Result:='mmDCP5_REGAMMA_CNTLB_START_CNTL'; + mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL :Result:='mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL'; + mmDCP5_REGAMMA_CNTLB_END_CNTL1 :Result:='mmDCP5_REGAMMA_CNTLB_END_CNTL1'; + mmDCP5_REGAMMA_CNTLB_END_CNTL2 :Result:='mmDCP5_REGAMMA_CNTLB_END_CNTL2'; + mmDCP5_REGAMMA_CNTLB_REGION_0_1 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_0_1'; + mmDCP5_REGAMMA_CNTLB_REGION_2_3 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_2_3'; + mmDCP5_REGAMMA_CNTLB_REGION_4_5 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_4_5'; + mmDCP5_REGAMMA_CNTLB_REGION_6_7 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_6_7'; + mmDCP5_REGAMMA_CNTLB_REGION_8_9 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_8_9'; + mmDCP5_REGAMMA_CNTLB_REGION_10_11 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_10_11'; + mmDCP5_REGAMMA_CNTLB_REGION_12_13 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_12_13'; + mmDCP5_REGAMMA_CNTLB_REGION_14_15 :Result:='mmDCP5_REGAMMA_CNTLB_REGION_14_15'; + mmDCP5_ALPHA_CONTROL :Result:='mmDCP5_ALPHA_CONTROL'; + mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS :Result:='mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS'; + mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH :Result:='mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH'; + mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS :Result:='mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS'; + mmLB5_LB_DATA_FORMAT :Result:='mmLB5_LB_DATA_FORMAT'; + mmLB5_LB_MEMORY_CTRL :Result:='mmLB5_LB_MEMORY_CTRL'; + mmLB5_LB_MEMORY_SIZE_STATUS :Result:='mmLB5_LB_MEMORY_SIZE_STATUS'; + mmLB5_LB_DESKTOP_HEIGHT :Result:='mmLB5_LB_DESKTOP_HEIGHT'; + mmLB5_LB_VLINE_START_END :Result:='mmLB5_LB_VLINE_START_END'; + mmLB5_LB_VLINE2_START_END :Result:='mmLB5_LB_VLINE2_START_END'; + mmLB5_LB_V_COUNTER :Result:='mmLB5_LB_V_COUNTER'; + mmLB5_LB_SNAPSHOT_V_COUNTER :Result:='mmLB5_LB_SNAPSHOT_V_COUNTER'; + mmLB5_LB_INTERRUPT_MASK :Result:='mmLB5_LB_INTERRUPT_MASK'; + mmLB5_LB_VLINE_STATUS :Result:='mmLB5_LB_VLINE_STATUS'; + mmLB5_LB_VLINE2_STATUS :Result:='mmLB5_LB_VLINE2_STATUS'; + mmLB5_LB_VBLANK_STATUS :Result:='mmLB5_LB_VBLANK_STATUS'; + mmLB5_LB_SYNC_RESET_SEL :Result:='mmLB5_LB_SYNC_RESET_SEL'; + mmLB5_LB_BLACK_KEYER_R_CR :Result:='mmLB5_LB_BLACK_KEYER_R_CR'; + mmLB5_LB_BLACK_KEYER_G_Y :Result:='mmLB5_LB_BLACK_KEYER_G_Y'; + mmLB5_LB_BLACK_KEYER_B_CB :Result:='mmLB5_LB_BLACK_KEYER_B_CB'; + mmLB5_LB_KEYER_COLOR_CTRL :Result:='mmLB5_LB_KEYER_COLOR_CTRL'; + mmLB5_LB_KEYER_COLOR_R_CR :Result:='mmLB5_LB_KEYER_COLOR_R_CR'; + mmLB5_LB_KEYER_COLOR_G_Y :Result:='mmLB5_LB_KEYER_COLOR_G_Y'; + mmLB5_LB_KEYER_COLOR_B_CB :Result:='mmLB5_LB_KEYER_COLOR_B_CB'; + mmLB5_LB_KEYER_COLOR_REP_R_CR :Result:='mmLB5_LB_KEYER_COLOR_REP_R_CR'; + mmLB5_LB_KEYER_COLOR_REP_G_Y :Result:='mmLB5_LB_KEYER_COLOR_REP_G_Y'; + mmLB5_LB_KEYER_COLOR_REP_B_CB :Result:='mmLB5_LB_KEYER_COLOR_REP_B_CB'; + mmLB5_LB_BUFFER_LEVEL_STATUS :Result:='mmLB5_LB_BUFFER_LEVEL_STATUS'; + mmLB5_LB_BUFFER_URGENCY_CTRL :Result:='mmLB5_LB_BUFFER_URGENCY_CTRL'; + mmLB5_LB_BUFFER_URGENCY_STATUS :Result:='mmLB5_LB_BUFFER_URGENCY_STATUS'; + mmLB5_LB_BUFFER_STATUS :Result:='mmLB5_LB_BUFFER_STATUS'; + mmLB5_LB_NO_OUTSTANDING_REQ_STATUS :Result:='mmLB5_LB_NO_OUTSTANDING_REQ_STATUS'; + mmLB5_MVP_AFR_FLIP_MODE :Result:='mmLB5_MVP_AFR_FLIP_MODE'; + mmLB5_MVP_AFR_FLIP_FIFO_CNTL :Result:='mmLB5_MVP_AFR_FLIP_FIFO_CNTL'; + mmLB5_MVP_FLIP_LINE_NUM_INSERT :Result:='mmLB5_MVP_FLIP_LINE_NUM_INSERT'; + mmLB5_DC_MVP_LB_CONTROL :Result:='mmLB5_DC_MVP_LB_CONTROL'; + mmLB5_LB_DEBUG :Result:='mmLB5_LB_DEBUG'; + mmLB5_LB_DEBUG2 :Result:='mmLB5_LB_DEBUG2'; + mmLB5_LB_DEBUG3 :Result:='mmLB5_LB_DEBUG3'; + mmLB5_LB_TEST_DEBUG_INDEX :Result:='mmLB5_LB_TEST_DEBUG_INDEX'; + mmLB5_LB_TEST_DEBUG_DATA :Result:='mmLB5_LB_TEST_DEBUG_DATA'; + mmDCFE5_DCFE_CLOCK_CONTROL :Result:='mmDCFE5_DCFE_CLOCK_CONTROL'; + mmDCFE5_DCFE_SOFT_RESET :Result:='mmDCFE5_DCFE_SOFT_RESET'; + mmDCFE5_DCFE_DBG_CONFIG :Result:='mmDCFE5_DCFE_DBG_CONFIG'; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL'; + mmDC_PERFMON8_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON8_PERFCOUNTER_CNTL'; + mmDC_PERFMON8_PERFCOUNTER_STATE :Result:='mmDC_PERFMON8_PERFCOUNTER_STATE'; + mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON8_PERFMON_CNTL :Result:='mmDC_PERFMON8_PERFMON_CNTL'; + mmDC_PERFMON8_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON8_PERFMON_CVALUE_LOW'; + mmDC_PERFMON8_PERFMON_HI :Result:='mmDC_PERFMON8_PERFMON_HI'; + mmDC_PERFMON8_PERFMON_LOW :Result:='mmDC_PERFMON8_PERFMON_LOW'; + mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON8_PERFMON_CNTL2 :Result:='mmDC_PERFMON8_PERFMON_CNTL2'; + mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 :Result:='mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1'; + mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 :Result:='mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2'; + mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL :Result:='mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL'; + mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL :Result:='mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL'; + mmDMIF_PG5_DPG_PIPE_DPM_CONTROL :Result:='mmDMIF_PG5_DPG_PIPE_DPM_CONTROL'; + mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL :Result:='mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL'; + mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :Result:='mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL'; + mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :Result:='mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH'; + mmDMIF_PG5_DPG_TEST_DEBUG_INDEX :Result:='mmDMIF_PG5_DPG_TEST_DEBUG_INDEX'; + mmDMIF_PG5_DPG_TEST_DEBUG_DATA :Result:='mmDMIF_PG5_DPG_TEST_DEBUG_DATA'; + mmDMIF_PG5_DPG_REPEATER_PROGRAM :Result:='mmDMIF_PG5_DPG_REPEATER_PROGRAM'; + mmDMIF_PG5_DPG_HW_DEBUG_A :Result:='mmDMIF_PG5_DPG_HW_DEBUG_A'; + mmDMIF_PG5_DPG_HW_DEBUG_B :Result:='mmDMIF_PG5_DPG_HW_DEBUG_B'; + mmDMIF_PG5_DPG_HW_DEBUG_11 :Result:='mmDMIF_PG5_DPG_HW_DEBUG_11'; + mmSCL5_SCL_COEF_RAM_SELECT :Result:='mmSCL5_SCL_COEF_RAM_SELECT'; + mmSCL5_SCL_COEF_RAM_TAP_DATA :Result:='mmSCL5_SCL_COEF_RAM_TAP_DATA'; + mmSCL5_SCL_MODE :Result:='mmSCL5_SCL_MODE'; + mmSCL5_SCL_TAP_CONTROL :Result:='mmSCL5_SCL_TAP_CONTROL'; + mmSCL5_SCL_CONTROL :Result:='mmSCL5_SCL_CONTROL'; + mmSCL5_SCL_BYPASS_CONTROL :Result:='mmSCL5_SCL_BYPASS_CONTROL'; + mmSCL5_SCL_MANUAL_REPLICATE_CONTROL :Result:='mmSCL5_SCL_MANUAL_REPLICATE_CONTROL'; + mmSCL5_SCL_AUTOMATIC_MODE_CONTROL :Result:='mmSCL5_SCL_AUTOMATIC_MODE_CONTROL'; + mmSCL5_SCL_HORZ_FILTER_CONTROL :Result:='mmSCL5_SCL_HORZ_FILTER_CONTROL'; + mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO :Result:='mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO'; + mmSCL5_SCL_HORZ_FILTER_INIT :Result:='mmSCL5_SCL_HORZ_FILTER_INIT'; + mmSCL5_SCL_VERT_FILTER_CONTROL :Result:='mmSCL5_SCL_VERT_FILTER_CONTROL'; + mmSCL5_SCL_VERT_FILTER_SCALE_RATIO :Result:='mmSCL5_SCL_VERT_FILTER_SCALE_RATIO'; + mmSCL5_SCL_VERT_FILTER_INIT :Result:='mmSCL5_SCL_VERT_FILTER_INIT'; + mmSCL5_SCL_VERT_FILTER_INIT_BOT :Result:='mmSCL5_SCL_VERT_FILTER_INIT_BOT'; + mmSCL5_SCL_ROUND_OFFSET :Result:='mmSCL5_SCL_ROUND_OFFSET'; + mmSCL5_SCL_UPDATE :Result:='mmSCL5_SCL_UPDATE'; + mmSCL5_SCL_F_SHARP_CONTROL :Result:='mmSCL5_SCL_F_SHARP_CONTROL'; + mmSCL5_SCL_ALU_CONTROL :Result:='mmSCL5_SCL_ALU_CONTROL'; + mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS :Result:='mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS'; + mmSCL5_VIEWPORT_START_SECONDARY :Result:='mmSCL5_VIEWPORT_START_SECONDARY'; + mmSCL5_VIEWPORT_START :Result:='mmSCL5_VIEWPORT_START'; + mmSCL5_VIEWPORT_SIZE :Result:='mmSCL5_VIEWPORT_SIZE'; + mmSCL5_EXT_OVERSCAN_LEFT_RIGHT :Result:='mmSCL5_EXT_OVERSCAN_LEFT_RIGHT'; + mmSCL5_EXT_OVERSCAN_TOP_BOTTOM :Result:='mmSCL5_EXT_OVERSCAN_TOP_BOTTOM'; + mmSCL5_SCL_MODE_CHANGE_DET1 :Result:='mmSCL5_SCL_MODE_CHANGE_DET1'; + mmSCL5_SCL_MODE_CHANGE_DET2 :Result:='mmSCL5_SCL_MODE_CHANGE_DET2'; + mmSCL5_SCL_MODE_CHANGE_DET3 :Result:='mmSCL5_SCL_MODE_CHANGE_DET3'; + mmSCL5_SCL_MODE_CHANGE_MASK :Result:='mmSCL5_SCL_MODE_CHANGE_MASK'; + mmSCL5_SCL_DEBUG2 :Result:='mmSCL5_SCL_DEBUG2'; + mmSCL5_SCL_DEBUG :Result:='mmSCL5_SCL_DEBUG'; + mmSCL5_SCL_TEST_DEBUG_INDEX :Result:='mmSCL5_SCL_TEST_DEBUG_INDEX'; + mmSCL5_SCL_TEST_DEBUG_DATA :Result:='mmSCL5_SCL_TEST_DEBUG_DATA'; + mmBLND5_BLND_CONTROL :Result:='mmBLND5_BLND_CONTROL'; + mmBLND5_SM_CONTROL2 :Result:='mmBLND5_SM_CONTROL2'; + mmBLND5_BLND_CONTROL2 :Result:='mmBLND5_BLND_CONTROL2'; + mmBLND5_BLND_UPDATE :Result:='mmBLND5_BLND_UPDATE'; + mmBLND5_BLND_UNDERFLOW_INTERRUPT :Result:='mmBLND5_BLND_UNDERFLOW_INTERRUPT'; + mmBLND5_BLND_V_UPDATE_LOCK :Result:='mmBLND5_BLND_V_UPDATE_LOCK'; + mmBLND5_BLND_DEBUG :Result:='mmBLND5_BLND_DEBUG'; + mmBLND5_BLND_TEST_DEBUG_INDEX :Result:='mmBLND5_BLND_TEST_DEBUG_INDEX'; + mmBLND5_BLND_TEST_DEBUG_DATA :Result:='mmBLND5_BLND_TEST_DEBUG_DATA'; + mmBLND5_BLND_REG_UPDATE_STATUS :Result:='mmBLND5_BLND_REG_UPDATE_STATUS'; + mmCRTC5_CRTC_3D_STRUCTURE_CONTROL :Result:='mmCRTC5_CRTC_3D_STRUCTURE_CONTROL'; + mmCRTC5_CRTC_GSL_VSYNC_GAP :Result:='mmCRTC5_CRTC_GSL_VSYNC_GAP'; + mmCRTC5_CRTC_GSL_WINDOW :Result:='mmCRTC5_CRTC_GSL_WINDOW'; + mmCRTC5_CRTC_GSL_CONTROL :Result:='mmCRTC5_CRTC_GSL_CONTROL'; + mmCRTC5_CRTC_DCFE_CLOCK_CONTROL :Result:='mmCRTC5_CRTC_DCFE_CLOCK_CONTROL'; + mmCRTC5_CRTC_H_BLANK_EARLY_NUM :Result:='mmCRTC5_CRTC_H_BLANK_EARLY_NUM'; + mmCRTC5_DCFE_DBG_SEL :Result:='mmCRTC5_DCFE_DBG_SEL'; + mmCRTC5_DCFE_MEM_PWR_CTRL :Result:='mmCRTC5_DCFE_MEM_PWR_CTRL'; + mmCRTC5_CRTC_H_SYNC_B_CNTL :Result:='mmCRTC5_CRTC_H_SYNC_B_CNTL'; + mmCRTC5_CRTC_V_TOTAL_MIN :Result:='mmCRTC5_CRTC_V_TOTAL_MIN'; + mmCRTC5_CRTC_V_TOTAL_MAX :Result:='mmCRTC5_CRTC_V_TOTAL_MAX'; + mmCRTC5_CRTC_V_TOTAL_CONTROL :Result:='mmCRTC5_CRTC_V_TOTAL_CONTROL'; + mmCRTC5_CRTC_V_TOTAL_INT_STATUS :Result:='mmCRTC5_CRTC_V_TOTAL_INT_STATUS'; + mmCRTC5_CRTC_V_BLANK_START_END :Result:='mmCRTC5_CRTC_V_BLANK_START_END'; + mmCRTC5_CRTC_V_SYNC_A :Result:='mmCRTC5_CRTC_V_SYNC_A'; + mmCRTC5_CRTC_V_SYNC_A_CNTL :Result:='mmCRTC5_CRTC_V_SYNC_A_CNTL'; + mmCRTC5_CRTC_V_SYNC_B :Result:='mmCRTC5_CRTC_V_SYNC_B'; + mmCRTC5_CRTC_V_SYNC_B_CNTL :Result:='mmCRTC5_CRTC_V_SYNC_B_CNTL'; + mmCRTC5_CRTC_DTMTEST_CNTL :Result:='mmCRTC5_CRTC_DTMTEST_CNTL'; + mmCRTC5_CRTC_DTMTEST_STATUS_POSITION :Result:='mmCRTC5_CRTC_DTMTEST_STATUS_POSITION'; + mmCRTC5_CRTC_TRIGA_CNTL :Result:='mmCRTC5_CRTC_TRIGA_CNTL'; + mmCRTC5_CRTC_TRIGA_MANUAL_TRIG :Result:='mmCRTC5_CRTC_TRIGA_MANUAL_TRIG'; + mmCRTC5_CRTC_TRIGB_CNTL :Result:='mmCRTC5_CRTC_TRIGB_CNTL'; + mmCRTC5_CRTC_TRIGB_MANUAL_TRIG :Result:='mmCRTC5_CRTC_TRIGB_MANUAL_TRIG'; + mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL :Result:='mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL'; + mmCRTC5_CRTC_FLOW_CONTROL :Result:='mmCRTC5_CRTC_FLOW_CONTROL'; + mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE :Result:='mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE'; + mmCRTC5_CRTC_AVSYNC_COUNTER :Result:='mmCRTC5_CRTC_AVSYNC_COUNTER'; + mmCRTC5_CRTC_CONTROL :Result:='mmCRTC5_CRTC_CONTROL'; + mmCRTC5_CRTC_BLANK_CONTROL :Result:='mmCRTC5_CRTC_BLANK_CONTROL'; + mmCRTC5_CRTC_INTERLACE_CONTROL :Result:='mmCRTC5_CRTC_INTERLACE_CONTROL'; + mmCRTC5_CRTC_INTERLACE_STATUS :Result:='mmCRTC5_CRTC_INTERLACE_STATUS'; + mmCRTC5_CRTC_FIELD_INDICATION_CONTROL :Result:='mmCRTC5_CRTC_FIELD_INDICATION_CONTROL'; + mmCRTC5_CRTC_PIXEL_DATA_READBACK0 :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK0'; + mmCRTC5_CRTC_PIXEL_DATA_READBACK1 :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK1'; + mmCRTC5_CRTC_STATUS :Result:='mmCRTC5_CRTC_STATUS'; + mmCRTC5_CRTC_STATUS_POSITION :Result:='mmCRTC5_CRTC_STATUS_POSITION'; + mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :Result:='mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE'; + mmCRTC5_CRTC_VERT_SYNC_CONTROL :Result:='mmCRTC5_CRTC_VERT_SYNC_CONTROL'; + mmCRTC5_CRTC_STEREO_STATUS :Result:='mmCRTC5_CRTC_STEREO_STATUS'; + mmCRTC5_CRTC_STEREO_CONTROL :Result:='mmCRTC5_CRTC_STEREO_CONTROL'; + mmCRTC5_CRTC_SNAPSHOT_STATUS :Result:='mmCRTC5_CRTC_SNAPSHOT_STATUS'; + mmCRTC5_CRTC_SNAPSHOT_CONTROL :Result:='mmCRTC5_CRTC_SNAPSHOT_CONTROL'; + mmCRTC5_CRTC_SNAPSHOT_POSITION :Result:='mmCRTC5_CRTC_SNAPSHOT_POSITION'; + mmCRTC5_CRTC_SNAPSHOT_FRAME :Result:='mmCRTC5_CRTC_SNAPSHOT_FRAME'; + mmCRTC5_CRTC_START_LINE_CONTROL :Result:='mmCRTC5_CRTC_START_LINE_CONTROL'; + mmCRTC5_CRTC_INTERRUPT_CONTROL :Result:='mmCRTC5_CRTC_INTERRUPT_CONTROL'; + mmCRTC5_CRTC_UPDATE_LOCK :Result:='mmCRTC5_CRTC_UPDATE_LOCK'; + mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL :Result:='mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL'; + mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE :Result:='mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE'; + mmCRTC5_DCFE_MEM_PWR_CTRL2 :Result:='mmCRTC5_DCFE_MEM_PWR_CTRL2'; + mmCRTC5_DCFE_MEM_PWR_STATUS :Result:='mmCRTC5_DCFE_MEM_PWR_STATUS'; + mmCRTC5_CRTC_TEST_PATTERN_CONTROL :Result:='mmCRTC5_CRTC_TEST_PATTERN_CONTROL'; + mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS :Result:='mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS'; + mmCRTC5_CRTC_TEST_PATTERN_COLOR :Result:='mmCRTC5_CRTC_TEST_PATTERN_COLOR'; + mmCRTC5_MASTER_UPDATE_LOCK :Result:='mmCRTC5_MASTER_UPDATE_LOCK'; + mmCRTC5_MASTER_UPDATE_MODE :Result:='mmCRTC5_MASTER_UPDATE_MODE'; + mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT :Result:='mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT'; + mmCRTC5_CRTC_TEST_DEBUG_INDEX :Result:='mmCRTC5_CRTC_TEST_DEBUG_INDEX'; + mmCRTC5_CRTC_TEST_DEBUG_DATA :Result:='mmCRTC5_CRTC_TEST_DEBUG_DATA'; + mmCRTC5_CRTC_OVERSCAN_COLOR :Result:='mmCRTC5_CRTC_OVERSCAN_COLOR'; + mmCRTC5_CRTC_OVERSCAN_COLOR_EXT :Result:='mmCRTC5_CRTC_OVERSCAN_COLOR_EXT'; + mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT :Result:='mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT'; + mmCRTC5_CRTC_BLACK_COLOR :Result:='mmCRTC5_CRTC_BLACK_COLOR'; + mmCRTC5_CRTC_BLACK_COLOR_EXT :Result:='mmCRTC5_CRTC_BLACK_COLOR_EXT'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION'; + mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL :Result:='mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL'; + mmCRTC5_CRTC_CRC_CNTL :Result:='mmCRTC5_CRTC_CRC_CNTL'; + mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL :Result:='mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL'; + mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL :Result:='mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL'; + mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL :Result:='mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL'; + mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL :Result:='mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL'; + mmCRTC5_CRTC_CRC0_DATA_RG :Result:='mmCRTC5_CRTC_CRC0_DATA_RG'; + mmCRTC5_CRTC_CRC0_DATA_B :Result:='mmCRTC5_CRTC_CRC0_DATA_B'; + mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL :Result:='mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL'; + mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL :Result:='mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL'; + mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL :Result:='mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL'; + mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL :Result:='mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL'; + mmCRTC5_CRTC_CRC1_DATA_RG :Result:='mmCRTC5_CRTC_CRC1_DATA_RG'; + mmCRTC5_CRTC_CRC1_DATA_B :Result:='mmCRTC5_CRTC_CRC1_DATA_B'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL'; + mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :Result:='mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL'; + mmCRTC5_CRTC_STATIC_SCREEN_CONTROL :Result:='mmCRTC5_CRTC_STATIC_SCREEN_CONTROL'; + mmFMT5_FMT_CLAMP_COMPONENT_R :Result:='mmFMT5_FMT_CLAMP_COMPONENT_R'; + mmFMT5_FMT_CLAMP_COMPONENT_G :Result:='mmFMT5_FMT_CLAMP_COMPONENT_G'; + mmFMT5_FMT_CLAMP_COMPONENT_B :Result:='mmFMT5_FMT_CLAMP_COMPONENT_B'; + mmFMT5_FMT_TEST_DEBUG_INDEX :Result:='mmFMT5_FMT_TEST_DEBUG_INDEX'; + mmFMT5_FMT_TEST_DEBUG_DATA :Result:='mmFMT5_FMT_TEST_DEBUG_DATA'; + mmFMT5_FMT_DYNAMIC_EXP_CNTL :Result:='mmFMT5_FMT_DYNAMIC_EXP_CNTL'; + mmFMT5_FMT_CONTROL :Result:='mmFMT5_FMT_CONTROL'; + mmFMT5_FMT_FORCE_OUTPUT_CNTL :Result:='mmFMT5_FMT_FORCE_OUTPUT_CNTL'; + mmFMT5_FMT_FORCE_DATA_0_1 :Result:='mmFMT5_FMT_FORCE_DATA_0_1'; + mmFMT5_FMT_FORCE_DATA_2_3 :Result:='mmFMT5_FMT_FORCE_DATA_2_3'; + mmFMT5_FMT_BIT_DEPTH_CONTROL :Result:='mmFMT5_FMT_BIT_DEPTH_CONTROL'; + mmFMT5_FMT_DITHER_RAND_R_SEED :Result:='mmFMT5_FMT_DITHER_RAND_R_SEED'; + mmFMT5_FMT_DITHER_RAND_G_SEED :Result:='mmFMT5_FMT_DITHER_RAND_G_SEED'; + mmFMT5_FMT_DITHER_RAND_B_SEED :Result:='mmFMT5_FMT_DITHER_RAND_B_SEED'; + mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL'; + mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX'; + mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX :Result:='mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX'; + mmFMT5_FMT_CLAMP_CNTL :Result:='mmFMT5_FMT_CLAMP_CNTL'; + mmFMT5_FMT_CRC_CNTL :Result:='mmFMT5_FMT_CRC_CNTL'; + mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK :Result:='mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK'; + mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK :Result:='mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK'; + mmFMT5_FMT_CRC_SIG_RED_GREEN :Result:='mmFMT5_FMT_CRC_SIG_RED_GREEN'; + mmFMT5_FMT_CRC_SIG_BLUE_CONTROL :Result:='mmFMT5_FMT_CRC_SIG_BLUE_CONTROL'; + mmFMT5_FMT_DEBUG_CNTL :Result:='mmFMT5_FMT_DEBUG_CNTL'; + mmUNP_GRPH_ENABLE :Result:='mmUNP_GRPH_ENABLE'; + mmUNP_GRPH_CONTROL :Result:='mmUNP_GRPH_CONTROL'; + mmUNP_GRPH_CONTROL_EXP :Result:='mmUNP_GRPH_CONTROL_EXP'; + mmUNP_GRPH_SWAP_CNTL :Result:='mmUNP_GRPH_SWAP_CNTL'; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L'; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C'; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L'; + mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C :Result:='mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C'; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L'; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C'; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L'; + mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C :Result:='mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C'; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L'; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C'; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L'; + mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C :Result:='mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C'; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L'; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C'; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L'; + mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C :Result:='mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C'; + mmUNP_GRPH_PITCH_L :Result:='mmUNP_GRPH_PITCH_L'; + mmUNP_GRPH_PITCH_C :Result:='mmUNP_GRPH_PITCH_C'; + mmUNP_GRPH_SURFACE_OFFSET_X_L :Result:='mmUNP_GRPH_SURFACE_OFFSET_X_L'; + mmUNP_GRPH_SURFACE_OFFSET_X_C :Result:='mmUNP_GRPH_SURFACE_OFFSET_X_C'; + mmUNP_GRPH_SURFACE_OFFSET_Y_L :Result:='mmUNP_GRPH_SURFACE_OFFSET_Y_L'; + mmUNP_GRPH_SURFACE_OFFSET_Y_C :Result:='mmUNP_GRPH_SURFACE_OFFSET_Y_C'; + mmUNP_GRPH_X_START_L :Result:='mmUNP_GRPH_X_START_L'; + mmUNP_GRPH_X_START_C :Result:='mmUNP_GRPH_X_START_C'; + mmUNP_GRPH_Y_START_L :Result:='mmUNP_GRPH_Y_START_L'; + mmUNP_GRPH_Y_START_C :Result:='mmUNP_GRPH_Y_START_C'; + mmUNP_GRPH_X_END_L :Result:='mmUNP_GRPH_X_END_L'; + mmUNP_GRPH_X_END_C :Result:='mmUNP_GRPH_X_END_C'; + mmUNP_GRPH_Y_END_L :Result:='mmUNP_GRPH_Y_END_L'; + mmUNP_GRPH_Y_END_C :Result:='mmUNP_GRPH_Y_END_C'; + mmUNP_GRPH_UPDATE :Result:='mmUNP_GRPH_UPDATE'; + mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L :Result:='mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L'; + mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C :Result:='mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C'; + mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L :Result:='mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L'; + mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C :Result:='mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C'; + mmUNP_GRPH_DFQ_CONTROL :Result:='mmUNP_GRPH_DFQ_CONTROL'; + mmUNP_GRPH_DFQ_STATUS :Result:='mmUNP_GRPH_DFQ_STATUS'; + mmUNP_GRPH_INTERRUPT_STATUS :Result:='mmUNP_GRPH_INTERRUPT_STATUS'; + mmUNP_GRPH_INTERRUPT_CONTROL :Result:='mmUNP_GRPH_INTERRUPT_CONTROL'; + mmUNP_GRPH_STEREOSYNC_FLIP :Result:='mmUNP_GRPH_STEREOSYNC_FLIP'; + mmUNP_GRPH_FLIP_RATE_CNTL :Result:='mmUNP_GRPH_FLIP_RATE_CNTL'; + mmUNP_CRC_CONTROL :Result:='mmUNP_CRC_CONTROL'; + mmUNP_CRC_MASK :Result:='mmUNP_CRC_MASK'; + mmUNP_CRC_CURRENT :Result:='mmUNP_CRC_CURRENT'; + mmUNP_CRC_LAST :Result:='mmUNP_CRC_LAST'; + mmUNP_LB_DATA_GAP_BETWEEN_CHUNK :Result:='mmUNP_LB_DATA_GAP_BETWEEN_CHUNK'; + mmUNP_HW_ROTATION :Result:='mmUNP_HW_ROTATION'; + mmUNP_DEBUG :Result:='mmUNP_DEBUG'; + mmUNP_DEBUG2 :Result:='mmUNP_DEBUG2'; + mmUNP_TEST_DEBUG_INDEX :Result:='mmUNP_TEST_DEBUG_INDEX'; + mmUNP_TEST_DEBUG_DATA :Result:='mmUNP_TEST_DEBUG_DATA'; + mmLBV_DATA_FORMAT :Result:='mmLBV_DATA_FORMAT'; + mmLBV_MEMORY_CTRL :Result:='mmLBV_MEMORY_CTRL'; + mmLBV_MEMORY_SIZE_STATUS :Result:='mmLBV_MEMORY_SIZE_STATUS'; + mmLBV_DESKTOP_HEIGHT :Result:='mmLBV_DESKTOP_HEIGHT'; + mmLBV_VLINE_START_END :Result:='mmLBV_VLINE_START_END'; + mmLBV_VLINE2_START_END :Result:='mmLBV_VLINE2_START_END'; + mmLBV_V_COUNTER :Result:='mmLBV_V_COUNTER'; + mmLBV_SNAPSHOT_V_COUNTER :Result:='mmLBV_SNAPSHOT_V_COUNTER'; + mmLBV_V_COUNTER_CHROMA :Result:='mmLBV_V_COUNTER_CHROMA'; + mmLBV_SNAPSHOT_V_COUNTER_CHROMA :Result:='mmLBV_SNAPSHOT_V_COUNTER_CHROMA'; + mmLBV_INTERRUPT_MASK :Result:='mmLBV_INTERRUPT_MASK'; + mmLBV_VLINE_STATUS :Result:='mmLBV_VLINE_STATUS'; + mmLBV_VLINE2_STATUS :Result:='mmLBV_VLINE2_STATUS'; + mmLBV_VBLANK_STATUS :Result:='mmLBV_VBLANK_STATUS'; + mmLBV_SYNC_RESET_SEL :Result:='mmLBV_SYNC_RESET_SEL'; + mmLBV_BLACK_KEYER_R_CR :Result:='mmLBV_BLACK_KEYER_R_CR'; + mmLBV_BLACK_KEYER_G_Y :Result:='mmLBV_BLACK_KEYER_G_Y'; + mmLBV_BLACK_KEYER_B_CB :Result:='mmLBV_BLACK_KEYER_B_CB'; + mmLBV_KEYER_COLOR_CTRL :Result:='mmLBV_KEYER_COLOR_CTRL'; + mmLBV_KEYER_COLOR_R_CR :Result:='mmLBV_KEYER_COLOR_R_CR'; + mmLBV_KEYER_COLOR_G_Y :Result:='mmLBV_KEYER_COLOR_G_Y'; + mmLBV_KEYER_COLOR_B_CB :Result:='mmLBV_KEYER_COLOR_B_CB'; + mmLBV_KEYER_COLOR_REP_R_CR :Result:='mmLBV_KEYER_COLOR_REP_R_CR'; + mmLBV_KEYER_COLOR_REP_G_Y :Result:='mmLBV_KEYER_COLOR_REP_G_Y'; + mmLBV_KEYER_COLOR_REP_B_CB :Result:='mmLBV_KEYER_COLOR_REP_B_CB'; + mmLBV_BUFFER_LEVEL_STATUS :Result:='mmLBV_BUFFER_LEVEL_STATUS'; + mmLBV_BUFFER_URGENCY_CTRL :Result:='mmLBV_BUFFER_URGENCY_CTRL'; + mmLBV_BUFFER_URGENCY_STATUS :Result:='mmLBV_BUFFER_URGENCY_STATUS'; + mmLBV_BUFFER_STATUS :Result:='mmLBV_BUFFER_STATUS'; + mmLBV_NO_OUTSTANDING_REQ_STATUS :Result:='mmLBV_NO_OUTSTANDING_REQ_STATUS'; + mmLBV_DEBUG :Result:='mmLBV_DEBUG'; + mmLBV_DEBUG2 :Result:='mmLBV_DEBUG2'; + mmLBV_DEBUG3 :Result:='mmLBV_DEBUG3'; + mmLBV_TEST_DEBUG_INDEX :Result:='mmLBV_TEST_DEBUG_INDEX'; + mmLBV_TEST_DEBUG_DATA :Result:='mmLBV_TEST_DEBUG_DATA'; + mmSCLV_COEF_RAM_SELECT :Result:='mmSCLV_COEF_RAM_SELECT'; + mmSCLV_COEF_RAM_TAP_DATA :Result:='mmSCLV_COEF_RAM_TAP_DATA'; + mmSCLV_MODE :Result:='mmSCLV_MODE'; + mmSCLV_TAP_CONTROL :Result:='mmSCLV_TAP_CONTROL'; + mmSCLV_CONTROL :Result:='mmSCLV_CONTROL'; + mmSCLV_MANUAL_REPLICATE_CONTROL :Result:='mmSCLV_MANUAL_REPLICATE_CONTROL'; + mmSCLV_AUTOMATIC_MODE_CONTROL :Result:='mmSCLV_AUTOMATIC_MODE_CONTROL'; + mmSCLV_HORZ_FILTER_CONTROL :Result:='mmSCLV_HORZ_FILTER_CONTROL'; + mmSCLV_HORZ_FILTER_SCALE_RATIO :Result:='mmSCLV_HORZ_FILTER_SCALE_RATIO'; + mmSCLV_HORZ_FILTER_INIT :Result:='mmSCLV_HORZ_FILTER_INIT'; + mmSCLV_HORZ_FILTER_SCALE_RATIO_C :Result:='mmSCLV_HORZ_FILTER_SCALE_RATIO_C'; + mmSCLV_HORZ_FILTER_INIT_C :Result:='mmSCLV_HORZ_FILTER_INIT_C'; + mmSCLV_VERT_FILTER_CONTROL :Result:='mmSCLV_VERT_FILTER_CONTROL'; + mmSCLV_VERT_FILTER_SCALE_RATIO :Result:='mmSCLV_VERT_FILTER_SCALE_RATIO'; + mmSCLV_VERT_FILTER_INIT :Result:='mmSCLV_VERT_FILTER_INIT'; + mmSCLV_VERT_FILTER_INIT_BOT :Result:='mmSCLV_VERT_FILTER_INIT_BOT'; + mmSCLV_VERT_FILTER_SCALE_RATIO_C :Result:='mmSCLV_VERT_FILTER_SCALE_RATIO_C'; + mmSCLV_VERT_FILTER_INIT_C :Result:='mmSCLV_VERT_FILTER_INIT_C'; + mmSCLV_VERT_FILTER_INIT_BOT_C :Result:='mmSCLV_VERT_FILTER_INIT_BOT_C'; + mmSCLV_ROUND_OFFSET :Result:='mmSCLV_ROUND_OFFSET'; + mmSCLV_UPDATE :Result:='mmSCLV_UPDATE'; + mmSCLV_ALU_CONTROL :Result:='mmSCLV_ALU_CONTROL'; + mmSCLV_VIEWPORT_START :Result:='mmSCLV_VIEWPORT_START'; + mmSCLV_VIEWPORT_START_SECONDARY :Result:='mmSCLV_VIEWPORT_START_SECONDARY'; + mmSCLV_VIEWPORT_SIZE :Result:='mmSCLV_VIEWPORT_SIZE'; + mmSCLV_VIEWPORT_START_C :Result:='mmSCLV_VIEWPORT_START_C'; + mmSCLV_VIEWPORT_START_SECONDARY_C :Result:='mmSCLV_VIEWPORT_START_SECONDARY_C'; + mmSCLV_VIEWPORT_SIZE_C :Result:='mmSCLV_VIEWPORT_SIZE_C'; + mmSCLV_EXT_OVERSCAN_LEFT_RIGHT :Result:='mmSCLV_EXT_OVERSCAN_LEFT_RIGHT'; + mmSCLV_EXT_OVERSCAN_TOP_BOTTOM :Result:='mmSCLV_EXT_OVERSCAN_TOP_BOTTOM'; + mmSCLV_MODE_CHANGE_DET1 :Result:='mmSCLV_MODE_CHANGE_DET1'; + mmSCLV_MODE_CHANGE_DET2 :Result:='mmSCLV_MODE_CHANGE_DET2'; + mmSCLV_MODE_CHANGE_DET3 :Result:='mmSCLV_MODE_CHANGE_DET3'; + mmSCLV_MODE_CHANGE_MASK :Result:='mmSCLV_MODE_CHANGE_MASK'; + mmSCLV_DEBUG2 :Result:='mmSCLV_DEBUG2'; + mmSCLV_DEBUG :Result:='mmSCLV_DEBUG'; + mmSCLV_TEST_DEBUG_INDEX :Result:='mmSCLV_TEST_DEBUG_INDEX'; + mmSCLV_TEST_DEBUG_DATA :Result:='mmSCLV_TEST_DEBUG_DATA'; + mmCOL_MAN_UPDATE :Result:='mmCOL_MAN_UPDATE'; + mmCOL_MAN_INPUT_CSC_CONTROL :Result:='mmCOL_MAN_INPUT_CSC_CONTROL'; + mmINPUT_CSC_C11_C12_A :Result:='mmINPUT_CSC_C11_C12_A'; + mmINPUT_CSC_C13_C14_A :Result:='mmINPUT_CSC_C13_C14_A'; + mmINPUT_CSC_C21_C22_A :Result:='mmINPUT_CSC_C21_C22_A'; + mmINPUT_CSC_C23_C24_A :Result:='mmINPUT_CSC_C23_C24_A'; + mmINPUT_CSC_C31_C32_A :Result:='mmINPUT_CSC_C31_C32_A'; + mmINPUT_CSC_C33_C34_A :Result:='mmINPUT_CSC_C33_C34_A'; + mmINPUT_CSC_C11_C12_B :Result:='mmINPUT_CSC_C11_C12_B'; + mmINPUT_CSC_C13_C14_B :Result:='mmINPUT_CSC_C13_C14_B'; + mmINPUT_CSC_C21_C22_B :Result:='mmINPUT_CSC_C21_C22_B'; + mmINPUT_CSC_C23_C24_B :Result:='mmINPUT_CSC_C23_C24_B'; + mmINPUT_CSC_C31_C32_B :Result:='mmINPUT_CSC_C31_C32_B'; + mmINPUT_CSC_C33_C34_B :Result:='mmINPUT_CSC_C33_C34_B'; + mmPRESCALE_CONTROL :Result:='mmPRESCALE_CONTROL'; + mmPRESCALE_VALUES_R :Result:='mmPRESCALE_VALUES_R'; + mmPRESCALE_VALUES_G :Result:='mmPRESCALE_VALUES_G'; + mmPRESCALE_VALUES_B :Result:='mmPRESCALE_VALUES_B'; + mmCOL_MAN_OUTPUT_CSC_CONTROL :Result:='mmCOL_MAN_OUTPUT_CSC_CONTROL'; + mmOUTPUT_CSC_C11_C12_A :Result:='mmOUTPUT_CSC_C11_C12_A'; + mmOUTPUT_CSC_C13_C14_A :Result:='mmOUTPUT_CSC_C13_C14_A'; + mmOUTPUT_CSC_C21_C22_A :Result:='mmOUTPUT_CSC_C21_C22_A'; + mmOUTPUT_CSC_C23_C24_A :Result:='mmOUTPUT_CSC_C23_C24_A'; + mmOUTPUT_CSC_C31_C32_A :Result:='mmOUTPUT_CSC_C31_C32_A'; + mmOUTPUT_CSC_C33_C34_A :Result:='mmOUTPUT_CSC_C33_C34_A'; + mmOUTPUT_CSC_C11_C12_B :Result:='mmOUTPUT_CSC_C11_C12_B'; + mmOUTPUT_CSC_C13_C14_B :Result:='mmOUTPUT_CSC_C13_C14_B'; + mmOUTPUT_CSC_C21_C22_B :Result:='mmOUTPUT_CSC_C21_C22_B'; + mmOUTPUT_CSC_C23_C24_B :Result:='mmOUTPUT_CSC_C23_C24_B'; + mmOUTPUT_CSC_C31_C32_B :Result:='mmOUTPUT_CSC_C31_C32_B'; + mmOUTPUT_CSC_C33_C34_B :Result:='mmOUTPUT_CSC_C33_C34_B'; + mmDENORM_CLAMP_CONTROL :Result:='mmDENORM_CLAMP_CONTROL'; + mmDENORM_CLAMP_RANGE_R_CR :Result:='mmDENORM_CLAMP_RANGE_R_CR'; + mmDENORM_CLAMP_RANGE_G_Y :Result:='mmDENORM_CLAMP_RANGE_G_Y'; + mmDENORM_CLAMP_RANGE_B_CB :Result:='mmDENORM_CLAMP_RANGE_B_CB'; + mmCOL_MAN_FP_CONVERTED_FIELD :Result:='mmCOL_MAN_FP_CONVERTED_FIELD'; + mmGAMMA_CORR_CONTROL :Result:='mmGAMMA_CORR_CONTROL'; + mmGAMMA_CORR_LUT_INDEX :Result:='mmGAMMA_CORR_LUT_INDEX'; + mmGAMMA_CORR_LUT_DATA :Result:='mmGAMMA_CORR_LUT_DATA'; + mmGAMMA_CORR_LUT_WRITE_EN_MASK :Result:='mmGAMMA_CORR_LUT_WRITE_EN_MASK'; + mmGAMMA_CORR_CNTLA_START_CNTL :Result:='mmGAMMA_CORR_CNTLA_START_CNTL'; + mmGAMMA_CORR_CNTLA_SLOPE_CNTL :Result:='mmGAMMA_CORR_CNTLA_SLOPE_CNTL'; + mmGAMMA_CORR_CNTLA_END_CNTL1 :Result:='mmGAMMA_CORR_CNTLA_END_CNTL1'; + mmGAMMA_CORR_CNTLA_END_CNTL2 :Result:='mmGAMMA_CORR_CNTLA_END_CNTL2'; + mmGAMMA_CORR_CNTLA_REGION_0_1 :Result:='mmGAMMA_CORR_CNTLA_REGION_0_1'; + mmGAMMA_CORR_CNTLA_REGION_2_3 :Result:='mmGAMMA_CORR_CNTLA_REGION_2_3'; + mmGAMMA_CORR_CNTLA_REGION_4_5 :Result:='mmGAMMA_CORR_CNTLA_REGION_4_5'; + mmGAMMA_CORR_CNTLA_REGION_6_7 :Result:='mmGAMMA_CORR_CNTLA_REGION_6_7'; + mmGAMMA_CORR_CNTLA_REGION_8_9 :Result:='mmGAMMA_CORR_CNTLA_REGION_8_9'; + mmGAMMA_CORR_CNTLA_REGION_10_11 :Result:='mmGAMMA_CORR_CNTLA_REGION_10_11'; + mmGAMMA_CORR_CNTLA_REGION_12_13 :Result:='mmGAMMA_CORR_CNTLA_REGION_12_13'; + mmGAMMA_CORR_CNTLA_REGION_14_15 :Result:='mmGAMMA_CORR_CNTLA_REGION_14_15'; + mmGAMMA_CORR_CNTLB_START_CNTL :Result:='mmGAMMA_CORR_CNTLB_START_CNTL'; + mmGAMMA_CORR_CNTLB_SLOPE_CNTL :Result:='mmGAMMA_CORR_CNTLB_SLOPE_CNTL'; + mmGAMMA_CORR_CNTLB_END_CNTL1 :Result:='mmGAMMA_CORR_CNTLB_END_CNTL1'; + mmGAMMA_CORR_CNTLB_END_CNTL2 :Result:='mmGAMMA_CORR_CNTLB_END_CNTL2'; + mmGAMMA_CORR_CNTLB_REGION_0_1 :Result:='mmGAMMA_CORR_CNTLB_REGION_0_1'; + mmGAMMA_CORR_CNTLB_REGION_2_3 :Result:='mmGAMMA_CORR_CNTLB_REGION_2_3'; + mmGAMMA_CORR_CNTLB_REGION_4_5 :Result:='mmGAMMA_CORR_CNTLB_REGION_4_5'; + mmGAMMA_CORR_CNTLB_REGION_6_7 :Result:='mmGAMMA_CORR_CNTLB_REGION_6_7'; + mmGAMMA_CORR_CNTLB_REGION_8_9 :Result:='mmGAMMA_CORR_CNTLB_REGION_8_9'; + mmGAMMA_CORR_CNTLB_REGION_10_11 :Result:='mmGAMMA_CORR_CNTLB_REGION_10_11'; + mmGAMMA_CORR_CNTLB_REGION_12_13 :Result:='mmGAMMA_CORR_CNTLB_REGION_12_13'; + mmGAMMA_CORR_CNTLB_REGION_14_15 :Result:='mmGAMMA_CORR_CNTLB_REGION_14_15'; + mmCOL_MAN_TEST_DEBUG_INDEX :Result:='mmCOL_MAN_TEST_DEBUG_INDEX'; + mmCOL_MAN_TEST_DEBUG_DATA :Result:='mmCOL_MAN_TEST_DEBUG_DATA'; + mmCOL_MAN_DEBUG_CONTROL :Result:='mmCOL_MAN_DEBUG_CONTROL'; + mmDCFEV_CLOCK_CONTROL :Result:='mmDCFEV_CLOCK_CONTROL'; + mmDCFEV_SOFT_RESET :Result:='mmDCFEV_SOFT_RESET'; + mmDCFEV_DMIFV_CLOCK_CONTROL :Result:='mmDCFEV_DMIFV_CLOCK_CONTROL'; + mmDCFEV_DBG_CONFIG :Result:='mmDCFEV_DBG_CONFIG'; + mmDCFEV_DMIFV_MEM_PWR_CTRL :Result:='mmDCFEV_DMIFV_MEM_PWR_CTRL'; + mmDCFEV_DMIFV_MEM_PWR_STATUS :Result:='mmDCFEV_DMIFV_MEM_PWR_STATUS'; + mmDC_PERFMON11_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON11_PERFCOUNTER_CNTL'; + mmDC_PERFMON11_PERFCOUNTER_STATE :Result:='mmDC_PERFMON11_PERFCOUNTER_STATE'; + mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON11_PERFMON_CNTL :Result:='mmDC_PERFMON11_PERFMON_CNTL'; + mmDC_PERFMON11_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON11_PERFMON_CVALUE_LOW'; + mmDC_PERFMON11_PERFMON_HI :Result:='mmDC_PERFMON11_PERFMON_HI'; + mmDC_PERFMON11_PERFMON_LOW :Result:='mmDC_PERFMON11_PERFMON_LOW'; + mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON11_PERFMON_CNTL2 :Result:='mmDC_PERFMON11_PERFMON_CNTL2'; + mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 :Result:='mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1'; + mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 :Result:='mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2'; + mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL :Result:='mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL'; + mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL :Result:='mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL'; + mmDMIF_PG6_DPG_PIPE_DPM_CONTROL :Result:='mmDMIF_PG6_DPG_PIPE_DPM_CONTROL'; + mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL :Result:='mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL'; + mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL :Result:='mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL'; + mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH :Result:='mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH'; + mmDMIF_PG6_DPG_TEST_DEBUG_INDEX :Result:='mmDMIF_PG6_DPG_TEST_DEBUG_INDEX'; + mmDMIF_PG6_DPG_TEST_DEBUG_DATA :Result:='mmDMIF_PG6_DPG_TEST_DEBUG_DATA'; + mmDMIF_PG6_DPG_REPEATER_PROGRAM :Result:='mmDMIF_PG6_DPG_REPEATER_PROGRAM'; + mmDMIF_PG6_DPG_HW_DEBUG_A :Result:='mmDMIF_PG6_DPG_HW_DEBUG_A'; + mmDMIF_PG6_DPG_HW_DEBUG_B :Result:='mmDMIF_PG6_DPG_HW_DEBUG_B'; + mmDMIF_PG6_DPG_HW_DEBUG_11 :Result:='mmDMIF_PG6_DPG_HW_DEBUG_11'; + mmBLND6_BLND_CONTROL :Result:='mmBLND6_BLND_CONTROL'; + mmBLND6_SM_CONTROL2 :Result:='mmBLND6_SM_CONTROL2'; + mmBLND6_BLND_CONTROL2 :Result:='mmBLND6_BLND_CONTROL2'; + mmBLND6_BLND_UPDATE :Result:='mmBLND6_BLND_UPDATE'; + mmBLND6_BLND_UNDERFLOW_INTERRUPT :Result:='mmBLND6_BLND_UNDERFLOW_INTERRUPT'; + mmBLND6_BLND_V_UPDATE_LOCK :Result:='mmBLND6_BLND_V_UPDATE_LOCK'; + mmBLND6_BLND_DEBUG :Result:='mmBLND6_BLND_DEBUG'; + mmBLND6_BLND_TEST_DEBUG_INDEX :Result:='mmBLND6_BLND_TEST_DEBUG_INDEX'; + mmBLND6_BLND_TEST_DEBUG_DATA :Result:='mmBLND6_BLND_TEST_DEBUG_DATA'; + mmBLND6_BLND_REG_UPDATE_STATUS :Result:='mmBLND6_BLND_REG_UPDATE_STATUS'; + mmCRTC6_CRTC_3D_STRUCTURE_CONTROL :Result:='mmCRTC6_CRTC_3D_STRUCTURE_CONTROL'; + mmCRTC6_CRTC_GSL_VSYNC_GAP :Result:='mmCRTC6_CRTC_GSL_VSYNC_GAP'; + mmCRTC6_CRTC_GSL_WINDOW :Result:='mmCRTC6_CRTC_GSL_WINDOW'; + mmCRTC6_CRTC_GSL_CONTROL :Result:='mmCRTC6_CRTC_GSL_CONTROL'; + mmCRTC6_CRTC_DCFE_CLOCK_CONTROL :Result:='mmCRTC6_CRTC_DCFE_CLOCK_CONTROL'; + mmCRTC6_CRTC_H_BLANK_EARLY_NUM :Result:='mmCRTC6_CRTC_H_BLANK_EARLY_NUM'; + mmCRTC6_DCFE_DBG_SEL :Result:='mmCRTC6_DCFE_DBG_SEL'; + mmCRTC6_DCFE_MEM_PWR_CTRL :Result:='mmCRTC6_DCFE_MEM_PWR_CTRL'; + mmCRTC6_CRTC_H_TOTAL :Result:='mmCRTC6_CRTC_H_TOTAL'; + mmCRTC6_CRTC_H_BLANK_START_END :Result:='mmCRTC6_CRTC_H_BLANK_START_END'; + mmCRTC6_CRTC_H_SYNC_A :Result:='mmCRTC6_CRTC_H_SYNC_A'; + mmCRTC6_CRTC_H_SYNC_A_CNTL :Result:='mmCRTC6_CRTC_H_SYNC_A_CNTL'; + mmCRTC6_CRTC_H_SYNC_B :Result:='mmCRTC6_CRTC_H_SYNC_B'; + mmCRTC6_CRTC_H_SYNC_B_CNTL :Result:='mmCRTC6_CRTC_H_SYNC_B_CNTL'; + mmCRTC6_CRTC_VBI_END :Result:='mmCRTC6_CRTC_VBI_END'; + mmCRTC6_CRTC_V_TOTAL :Result:='mmCRTC6_CRTC_V_TOTAL'; + mmCRTC6_CRTC_V_TOTAL_MIN :Result:='mmCRTC6_CRTC_V_TOTAL_MIN'; + mmCRTC6_CRTC_V_TOTAL_MAX :Result:='mmCRTC6_CRTC_V_TOTAL_MAX'; + mmCRTC6_CRTC_V_TOTAL_CONTROL :Result:='mmCRTC6_CRTC_V_TOTAL_CONTROL'; + mmCRTC6_CRTC_V_TOTAL_INT_STATUS :Result:='mmCRTC6_CRTC_V_TOTAL_INT_STATUS'; + mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS :Result:='mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS'; + mmCRTC6_CRTC_V_BLANK_START_END :Result:='mmCRTC6_CRTC_V_BLANK_START_END'; + mmCRTC6_CRTC_V_SYNC_A :Result:='mmCRTC6_CRTC_V_SYNC_A'; + mmCRTC6_CRTC_V_SYNC_A_CNTL :Result:='mmCRTC6_CRTC_V_SYNC_A_CNTL'; + mmCRTC6_CRTC_V_SYNC_B :Result:='mmCRTC6_CRTC_V_SYNC_B'; + mmCRTC6_CRTC_V_SYNC_B_CNTL :Result:='mmCRTC6_CRTC_V_SYNC_B_CNTL'; + mmCRTC6_CRTC_DTMTEST_CNTL :Result:='mmCRTC6_CRTC_DTMTEST_CNTL'; + mmCRTC6_CRTC_DTMTEST_STATUS_POSITION :Result:='mmCRTC6_CRTC_DTMTEST_STATUS_POSITION'; + mmCRTC6_CRTC_TRIGA_CNTL :Result:='mmCRTC6_CRTC_TRIGA_CNTL'; + mmCRTC6_CRTC_TRIGA_MANUAL_TRIG :Result:='mmCRTC6_CRTC_TRIGA_MANUAL_TRIG'; + mmCRTC6_CRTC_TRIGB_CNTL :Result:='mmCRTC6_CRTC_TRIGB_CNTL'; + mmCRTC6_CRTC_TRIGB_MANUAL_TRIG :Result:='mmCRTC6_CRTC_TRIGB_MANUAL_TRIG'; + mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL :Result:='mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL'; + mmCRTC6_CRTC_FLOW_CONTROL :Result:='mmCRTC6_CRTC_FLOW_CONTROL'; + mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE :Result:='mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE'; + mmCRTC6_CRTC_AVSYNC_COUNTER :Result:='mmCRTC6_CRTC_AVSYNC_COUNTER'; + mmCRTC6_CRTC_CONTROL :Result:='mmCRTC6_CRTC_CONTROL'; + mmCRTC6_CRTC_BLANK_CONTROL :Result:='mmCRTC6_CRTC_BLANK_CONTROL'; + mmCRTC6_CRTC_INTERLACE_CONTROL :Result:='mmCRTC6_CRTC_INTERLACE_CONTROL'; + mmCRTC6_CRTC_INTERLACE_STATUS :Result:='mmCRTC6_CRTC_INTERLACE_STATUS'; + mmCRTC6_CRTC_FIELD_INDICATION_CONTROL :Result:='mmCRTC6_CRTC_FIELD_INDICATION_CONTROL'; + mmCRTC6_CRTC_PIXEL_DATA_READBACK0 :Result:='mmCRTC6_CRTC_PIXEL_DATA_READBACK0'; + mmCRTC6_CRTC_PIXEL_DATA_READBACK1 :Result:='mmCRTC6_CRTC_PIXEL_DATA_READBACK1'; + mmCRTC6_CRTC_STATUS :Result:='mmCRTC6_CRTC_STATUS'; + mmCRTC6_CRTC_STATUS_POSITION :Result:='mmCRTC6_CRTC_STATUS_POSITION'; + mmCRTC6_CRTC_NOM_VERT_POSITION :Result:='mmCRTC6_CRTC_NOM_VERT_POSITION'; + mmCRTC6_CRTC_STATUS_FRAME_COUNT :Result:='mmCRTC6_CRTC_STATUS_FRAME_COUNT'; + mmCRTC6_CRTC_STATUS_VF_COUNT :Result:='mmCRTC6_CRTC_STATUS_VF_COUNT'; + mmCRTC6_CRTC_STATUS_HV_COUNT :Result:='mmCRTC6_CRTC_STATUS_HV_COUNT'; + mmCRTC6_CRTC_COUNT_CONTROL :Result:='mmCRTC6_CRTC_COUNT_CONTROL'; + mmCRTC6_CRTC_COUNT_RESET :Result:='mmCRTC6_CRTC_COUNT_RESET'; + mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE :Result:='mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE'; + mmCRTC6_CRTC_VERT_SYNC_CONTROL :Result:='mmCRTC6_CRTC_VERT_SYNC_CONTROL'; + mmCRTC6_CRTC_STEREO_STATUS :Result:='mmCRTC6_CRTC_STEREO_STATUS'; + mmCRTC6_CRTC_STEREO_CONTROL :Result:='mmCRTC6_CRTC_STEREO_CONTROL'; + mmCRTC6_CRTC_SNAPSHOT_STATUS :Result:='mmCRTC6_CRTC_SNAPSHOT_STATUS'; + mmCRTC6_CRTC_SNAPSHOT_CONTROL :Result:='mmCRTC6_CRTC_SNAPSHOT_CONTROL'; + mmCRTC6_CRTC_SNAPSHOT_POSITION :Result:='mmCRTC6_CRTC_SNAPSHOT_POSITION'; + mmCRTC6_CRTC_SNAPSHOT_FRAME :Result:='mmCRTC6_CRTC_SNAPSHOT_FRAME'; + mmCRTC6_CRTC_START_LINE_CONTROL :Result:='mmCRTC6_CRTC_START_LINE_CONTROL'; + mmCRTC6_CRTC_INTERRUPT_CONTROL :Result:='mmCRTC6_CRTC_INTERRUPT_CONTROL'; + mmCRTC6_CRTC_UPDATE_LOCK :Result:='mmCRTC6_CRTC_UPDATE_LOCK'; + mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL :Result:='mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL'; + mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE :Result:='mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE'; + mmCRTC6_DCFE_MEM_PWR_CTRL2 :Result:='mmCRTC6_DCFE_MEM_PWR_CTRL2'; + mmCRTC6_DCFE_MEM_PWR_STATUS :Result:='mmCRTC6_DCFE_MEM_PWR_STATUS'; + mmCRTC6_CRTC_TEST_PATTERN_CONTROL :Result:='mmCRTC6_CRTC_TEST_PATTERN_CONTROL'; + mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS :Result:='mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS'; + mmCRTC6_CRTC_TEST_PATTERN_COLOR :Result:='mmCRTC6_CRTC_TEST_PATTERN_COLOR'; + mmCRTC6_MASTER_UPDATE_LOCK :Result:='mmCRTC6_MASTER_UPDATE_LOCK'; + mmCRTC6_MASTER_UPDATE_MODE :Result:='mmCRTC6_MASTER_UPDATE_MODE'; + mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT :Result:='mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT'; + mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER :Result:='mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER'; + mmCRTC6_CRTC_MVP_STATUS :Result:='mmCRTC6_CRTC_MVP_STATUS'; + mmCRTC6_CRTC_MASTER_EN :Result:='mmCRTC6_CRTC_MASTER_EN'; + mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT :Result:='mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT'; + mmCRTC6_CRTC_V_UPDATE_INT_STATUS :Result:='mmCRTC6_CRTC_V_UPDATE_INT_STATUS'; + mmCRTC6_CRTC_TEST_DEBUG_INDEX :Result:='mmCRTC6_CRTC_TEST_DEBUG_INDEX'; + mmCRTC6_CRTC_TEST_DEBUG_DATA :Result:='mmCRTC6_CRTC_TEST_DEBUG_DATA'; + mmCRTC6_CRTC_OVERSCAN_COLOR :Result:='mmCRTC6_CRTC_OVERSCAN_COLOR'; + mmCRTC6_CRTC_OVERSCAN_COLOR_EXT :Result:='mmCRTC6_CRTC_OVERSCAN_COLOR_EXT'; + mmCRTC6_CRTC_BLANK_DATA_COLOR :Result:='mmCRTC6_CRTC_BLANK_DATA_COLOR'; + mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT :Result:='mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT'; + mmCRTC6_CRTC_BLACK_COLOR :Result:='mmCRTC6_CRTC_BLACK_COLOR'; + mmCRTC6_CRTC_BLACK_COLOR_EXT :Result:='mmCRTC6_CRTC_BLACK_COLOR_EXT'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION'; + mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL :Result:='mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL'; + mmCRTC6_CRTC_CRC_CNTL :Result:='mmCRTC6_CRTC_CRC_CNTL'; + mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL :Result:='mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL'; + mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL :Result:='mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL'; + mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL :Result:='mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL'; + mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL :Result:='mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL'; + mmCRTC6_CRTC_CRC0_DATA_RG :Result:='mmCRTC6_CRTC_CRC0_DATA_RG'; + mmCRTC6_CRTC_CRC0_DATA_B :Result:='mmCRTC6_CRTC_CRC0_DATA_B'; + mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL :Result:='mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL'; + mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL :Result:='mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL'; + mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL :Result:='mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL'; + mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL :Result:='mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL'; + mmCRTC6_CRTC_CRC1_DATA_RG :Result:='mmCRTC6_CRTC_CRC1_DATA_RG'; + mmCRTC6_CRTC_CRC1_DATA_B :Result:='mmCRTC6_CRTC_CRC1_DATA_B'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL'; + mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL :Result:='mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL'; + mmCRTC6_CRTC_STATIC_SCREEN_CONTROL :Result:='mmCRTC6_CRTC_STATIC_SCREEN_CONTROL'; + mmDC_GENERICA :Result:='mmDC_GENERICA'; + mmDC_GENERICB :Result:='mmDC_GENERICB'; + mmDC_PAD_EXTERN_SIG :Result:='mmDC_PAD_EXTERN_SIG'; + mmDC_REF_CLK_CNTL :Result:='mmDC_REF_CLK_CNTL'; + mmDC_GPIO_DEBUG :Result:='mmDC_GPIO_DEBUG'; + mmUNIPHYA_LINK_CNTL :Result:='mmUNIPHYA_LINK_CNTL'; + mmUNIPHYA_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYA_CHANNEL_XBAR_CNTL'; + mmUNIPHYB_LINK_CNTL :Result:='mmUNIPHYB_LINK_CNTL'; + mmUNIPHYB_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYB_CHANNEL_XBAR_CNTL'; + mmUNIPHYC_LINK_CNTL :Result:='mmUNIPHYC_LINK_CNTL'; + mmUNIPHYC_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYC_CHANNEL_XBAR_CNTL'; + mmUNIPHYD_LINK_CNTL :Result:='mmUNIPHYD_LINK_CNTL'; + mmUNIPHYD_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYD_CHANNEL_XBAR_CNTL'; + mmUNIPHYE_LINK_CNTL :Result:='mmUNIPHYE_LINK_CNTL'; + mmUNIPHYE_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYE_CHANNEL_XBAR_CNTL'; + mmUNIPHYF_LINK_CNTL :Result:='mmUNIPHYF_LINK_CNTL'; + mmUNIPHYF_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYF_CHANNEL_XBAR_CNTL'; + mmUNIPHYG_LINK_CNTL :Result:='mmUNIPHYG_LINK_CNTL'; + mmUNIPHYG_CHANNEL_XBAR_CNTL :Result:='mmUNIPHYG_CHANNEL_XBAR_CNTL'; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL'; + mmDCIO_WRCMD_DELAY :Result:='mmDCIO_WRCMD_DELAY'; + mmDC_PINSTRAPS :Result:='mmDC_PINSTRAPS'; + mmDC_DVODATA_CONFIG :Result:='mmDC_DVODATA_CONFIG'; + mmLVTMA_PWRSEQ_CNTL :Result:='mmLVTMA_PWRSEQ_CNTL'; + mmLVTMA_PWRSEQ_STATE :Result:='mmLVTMA_PWRSEQ_STATE'; + mmLVTMA_PWRSEQ_REF_DIV :Result:='mmLVTMA_PWRSEQ_REF_DIV'; + mmLVTMA_PWRSEQ_DELAY1 :Result:='mmLVTMA_PWRSEQ_DELAY1'; + mmLVTMA_PWRSEQ_DELAY2 :Result:='mmLVTMA_PWRSEQ_DELAY2'; + mmBL_PWM_CNTL :Result:='mmBL_PWM_CNTL'; + mmBL_PWM_CNTL2 :Result:='mmBL_PWM_CNTL2'; + mmBL_PWM_PERIOD_CNTL :Result:='mmBL_PWM_PERIOD_CNTL'; + mmBL_PWM_GRP1_REG_LOCK :Result:='mmBL_PWM_GRP1_REG_LOCK'; + mmDCIO_GSL_GENLK_PAD_CNTL :Result:='mmDCIO_GSL_GENLK_PAD_CNTL'; + mmDCIO_GSL_SWAPLOCK_PAD_CNTL :Result:='mmDCIO_GSL_SWAPLOCK_PAD_CNTL'; + mmDCIO_GSL0_CNTL :Result:='mmDCIO_GSL0_CNTL'; + mmDCIO_GSL1_CNTL :Result:='mmDCIO_GSL1_CNTL'; + mmDCIO_GSL2_CNTL :Result:='mmDCIO_GSL2_CNTL'; + mmDC_GPU_TIMER_START_POSITION_V_UPDATE :Result:='mmDC_GPU_TIMER_START_POSITION_V_UPDATE'; + mmDC_GPU_TIMER_START_POSITION_P_FLIP :Result:='mmDC_GPU_TIMER_START_POSITION_P_FLIP'; + mmDC_GPU_TIMER_READ :Result:='mmDC_GPU_TIMER_READ'; + mmDC_GPU_TIMER_READ_CNTL :Result:='mmDC_GPU_TIMER_READ_CNTL'; + mmDCIO_CLOCK_CNTL :Result:='mmDCIO_CLOCK_CNTL'; + mmDCIO_DEBUG :Result:='mmDCIO_DEBUG'; + mmDCO_DCFE_EXT_VSYNC_CNTL :Result:='mmDCO_DCFE_EXT_VSYNC_CNTL'; + mmDCIO_TEST_DEBUG_INDEX :Result:='mmDCIO_TEST_DEBUG_INDEX'; + mmDCIO_TEST_DEBUG_DATA :Result:='mmDCIO_TEST_DEBUG_DATA'; + mmDBG_OUT_CNTL :Result:='mmDBG_OUT_CNTL'; + mmDCIO_DEBUG_CONFIG :Result:='mmDCIO_DEBUG_CONFIG'; + mmDCIO_SOFT_RESET :Result:='mmDCIO_SOFT_RESET'; + mmDCIO_DPHY_SEL :Result:='mmDCIO_DPHY_SEL'; + mmUNIPHY_IMPCAL_LINKA :Result:='mmUNIPHY_IMPCAL_LINKA'; + mmUNIPHY_IMPCAL_LINKB :Result:='mmUNIPHY_IMPCAL_LINKB'; + mmUNIPHY_IMPCAL_PERIOD :Result:='mmUNIPHY_IMPCAL_PERIOD'; + mmAUXP_IMPCAL :Result:='mmAUXP_IMPCAL'; + mmAUXN_IMPCAL :Result:='mmAUXN_IMPCAL'; + mmDCIO_IMPCAL_CNTL :Result:='mmDCIO_IMPCAL_CNTL'; + mmUNIPHY_IMPCAL_PSW_AB :Result:='mmUNIPHY_IMPCAL_PSW_AB'; + mmUNIPHY_IMPCAL_LINKC :Result:='mmUNIPHY_IMPCAL_LINKC'; + mmUNIPHY_IMPCAL_LINKD :Result:='mmUNIPHY_IMPCAL_LINKD'; + mmDCIO_IMPCAL_CNTL_CD :Result:='mmDCIO_IMPCAL_CNTL_CD'; + mmUNIPHY_IMPCAL_PSW_CD :Result:='mmUNIPHY_IMPCAL_PSW_CD'; + mmUNIPHY_IMPCAL_LINKE :Result:='mmUNIPHY_IMPCAL_LINKE'; + mmUNIPHY_IMPCAL_LINKF :Result:='mmUNIPHY_IMPCAL_LINKF'; + mmDCIO_IMPCAL_CNTL_EF :Result:='mmDCIO_IMPCAL_CNTL_EF'; + mmUNIPHY_IMPCAL_PSW_EF :Result:='mmUNIPHY_IMPCAL_PSW_EF'; + mmDC_GPIO_GENERIC_MASK :Result:='mmDC_GPIO_GENERIC_MASK'; + mmDC_GPIO_GENERIC_A :Result:='mmDC_GPIO_GENERIC_A'; + mmDC_GPIO_GENERIC_EN :Result:='mmDC_GPIO_GENERIC_EN'; + mmDC_GPIO_GENERIC_Y :Result:='mmDC_GPIO_GENERIC_Y'; + mmDC_GPIO_DVODATA_MASK :Result:='mmDC_GPIO_DVODATA_MASK'; + mmDC_GPIO_DVODATA_A :Result:='mmDC_GPIO_DVODATA_A'; + mmDC_GPIO_DVODATA_EN :Result:='mmDC_GPIO_DVODATA_EN'; + mmDC_GPIO_DVODATA_Y :Result:='mmDC_GPIO_DVODATA_Y'; + mmDC_GPIO_DDC1_MASK :Result:='mmDC_GPIO_DDC1_MASK'; + mmDC_GPIO_DDC1_A :Result:='mmDC_GPIO_DDC1_A'; + mmDC_GPIO_DDC1_EN :Result:='mmDC_GPIO_DDC1_EN'; + mmDC_GPIO_DDC1_Y :Result:='mmDC_GPIO_DDC1_Y'; + mmDC_GPIO_DDC2_MASK :Result:='mmDC_GPIO_DDC2_MASK'; + mmDC_GPIO_DDC2_A :Result:='mmDC_GPIO_DDC2_A'; + mmDC_GPIO_DDC2_EN :Result:='mmDC_GPIO_DDC2_EN'; + mmDC_GPIO_DDC2_Y :Result:='mmDC_GPIO_DDC2_Y'; + mmDC_GPIO_DDC3_MASK :Result:='mmDC_GPIO_DDC3_MASK'; + mmDC_GPIO_DDC3_A :Result:='mmDC_GPIO_DDC3_A'; + mmDC_GPIO_DDC3_EN :Result:='mmDC_GPIO_DDC3_EN'; + mmDC_GPIO_DDC3_Y :Result:='mmDC_GPIO_DDC3_Y'; + mmDC_GPIO_DDC4_MASK :Result:='mmDC_GPIO_DDC4_MASK'; + mmDC_GPIO_DDC4_A :Result:='mmDC_GPIO_DDC4_A'; + mmDC_GPIO_DDC4_EN :Result:='mmDC_GPIO_DDC4_EN'; + mmDC_GPIO_DDC4_Y :Result:='mmDC_GPIO_DDC4_Y'; + mmDC_GPIO_DDC5_MASK :Result:='mmDC_GPIO_DDC5_MASK'; + mmDC_GPIO_DDC5_A :Result:='mmDC_GPIO_DDC5_A'; + mmDC_GPIO_DDC5_EN :Result:='mmDC_GPIO_DDC5_EN'; + mmDC_GPIO_DDC5_Y :Result:='mmDC_GPIO_DDC5_Y'; + mmDC_GPIO_DDC6_MASK :Result:='mmDC_GPIO_DDC6_MASK'; + mmDC_GPIO_DDC6_A :Result:='mmDC_GPIO_DDC6_A'; + mmDC_GPIO_DDC6_EN :Result:='mmDC_GPIO_DDC6_EN'; + mmDC_GPIO_DDC6_Y :Result:='mmDC_GPIO_DDC6_Y'; + mmDC_GPIO_DDCVGA_MASK :Result:='mmDC_GPIO_DDCVGA_MASK'; + mmDC_GPIO_DDCVGA_A :Result:='mmDC_GPIO_DDCVGA_A'; + mmDC_GPIO_DDCVGA_EN :Result:='mmDC_GPIO_DDCVGA_EN'; + mmDC_GPIO_DDCVGA_Y :Result:='mmDC_GPIO_DDCVGA_Y'; + mmDC_GPIO_SYNCA_MASK :Result:='mmDC_GPIO_SYNCA_MASK'; + mmDC_GPIO_SYNCA_A :Result:='mmDC_GPIO_SYNCA_A'; + mmDC_GPIO_SYNCA_EN :Result:='mmDC_GPIO_SYNCA_EN'; + mmDC_GPIO_SYNCA_Y :Result:='mmDC_GPIO_SYNCA_Y'; + mmDC_GPIO_GENLK_MASK :Result:='mmDC_GPIO_GENLK_MASK'; + mmDC_GPIO_GENLK_A :Result:='mmDC_GPIO_GENLK_A'; + mmDC_GPIO_GENLK_EN :Result:='mmDC_GPIO_GENLK_EN'; + mmDC_GPIO_GENLK_Y :Result:='mmDC_GPIO_GENLK_Y'; + mmDC_GPIO_HPD_MASK :Result:='mmDC_GPIO_HPD_MASK'; + mmDC_GPIO_HPD_A :Result:='mmDC_GPIO_HPD_A'; + mmDC_GPIO_HPD_EN :Result:='mmDC_GPIO_HPD_EN'; + mmDC_GPIO_HPD_Y :Result:='mmDC_GPIO_HPD_Y'; + mmDC_GPIO_PWRSEQ_MASK :Result:='mmDC_GPIO_PWRSEQ_MASK'; + mmDC_GPIO_PWRSEQ_A :Result:='mmDC_GPIO_PWRSEQ_A'; + mmDC_GPIO_PWRSEQ_EN :Result:='mmDC_GPIO_PWRSEQ_EN'; + mmDC_GPIO_PWRSEQ_Y :Result:='mmDC_GPIO_PWRSEQ_Y'; + mmDC_GPIO_PAD_STRENGTH_1 :Result:='mmDC_GPIO_PAD_STRENGTH_1'; + mmDC_GPIO_PAD_STRENGTH_2 :Result:='mmDC_GPIO_PAD_STRENGTH_2'; + mmPHY_AUX_CNTL :Result:='mmPHY_AUX_CNTL'; + mmDC_GPIO_I2CPAD_MASK :Result:='mmDC_GPIO_I2CPAD_MASK'; + mmDC_GPIO_I2CPAD_A :Result:='mmDC_GPIO_I2CPAD_A'; + mmDC_GPIO_I2CPAD_EN :Result:='mmDC_GPIO_I2CPAD_EN'; + mmDC_GPIO_I2CPAD_Y :Result:='mmDC_GPIO_I2CPAD_Y'; + mmDC_GPIO_I2CPAD_STRENGTH :Result:='mmDC_GPIO_I2CPAD_STRENGTH'; + mmDVO_STRENGTH_CONTROL :Result:='mmDVO_STRENGTH_CONTROL'; + mmDVO_VREF_CONTROL :Result:='mmDVO_VREF_CONTROL'; + mmDVO_SKEW_ADJUST :Result:='mmDVO_SKEW_ADJUST'; + mmDAC_MACRO_CNTL_RESERVED0 :Result:='mmDAC_MACRO_CNTL_RESERVED0'; + mmBPHYC_DAC_MACRO_CNTL :Result:='mmBPHYC_DAC_MACRO_CNTL'; + mmBPHYC_DAC_AUTO_CALIB_CONTROL :Result:='mmBPHYC_DAC_AUTO_CALIB_CONTROL'; + mmDAC_MACRO_CNTL_RESERVED3 :Result:='mmDAC_MACRO_CNTL_RESERVED3'; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY0_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY0_UNIPHY_DEBUG'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY1_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY1_UNIPHY_DEBUG'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY2_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY2_UNIPHY_DEBUG'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY3_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY3_UNIPHY_DEBUG'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY4_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY4_UNIPHY_DEBUG'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY5_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY5_UNIPHY_DEBUG'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31'; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1'; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2'; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3'; + mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 :Result:='mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4'; + mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL :Result:='mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL'; + mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV'; + mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1'; + mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2'; + mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE'; + mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL :Result:='mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL'; + mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION :Result:='mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION'; + mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT :Result:='mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT'; + mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL :Result:='mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL'; + mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 :Result:='mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19'; + mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL :Result:='mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL'; + mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED :Result:='mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED'; + mmBPHYC_UNIPHY6_UNIPHY_DEBUG :Result:='mmBPHYC_UNIPHY6_UNIPHY_DEBUG'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30'; + mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 :Result:='mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31'; + mmDIG0_DIG_FE_CNTL :Result:='mmDIG0_DIG_FE_CNTL'; + mmDIG0_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG0_DIG_OUTPUT_CRC_CNTL'; + mmDIG0_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG0_DIG_OUTPUT_CRC_RESULT'; + mmDIG0_DIG_CLOCK_PATTERN :Result:='mmDIG0_DIG_CLOCK_PATTERN'; + mmDIG0_DIG_TEST_PATTERN :Result:='mmDIG0_DIG_TEST_PATTERN'; + mmDIG0_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG0_DIG_RANDOM_PATTERN_SEED'; + mmDIG0_DIG_FIFO_STATUS :Result:='mmDIG0_DIG_FIFO_STATUS'; + mmDIG0_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG0_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG0_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG0_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG0_HDMI_CONTROL :Result:='mmDIG0_HDMI_CONTROL'; + mmDIG0_HDMI_STATUS :Result:='mmDIG0_HDMI_STATUS'; + mmDIG0_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG0_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG0_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG0_HDMI_ACR_PACKET_CONTROL'; + mmDIG0_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG0_HDMI_VBI_PACKET_CONTROL'; + mmDIG0_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG0_HDMI_INFOFRAME_CONTROL0'; + mmDIG0_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG0_HDMI_INFOFRAME_CONTROL1'; + mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG0_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG0_HDMI_GC :Result:='mmDIG0_HDMI_GC'; + mmAFMT_AUDIO_PACKET_CONTROL2 :Result:='mmAFMT_AUDIO_PACKET_CONTROL2'; + mmAFMT_ISRC1_0 :Result:='mmAFMT_ISRC1_0'; + mmAFMT_ISRC1_1 :Result:='mmAFMT_ISRC1_1'; + mmAFMT_ISRC1_2 :Result:='mmAFMT_ISRC1_2'; + mmAFMT_ISRC1_3 :Result:='mmAFMT_ISRC1_3'; + mmAFMT_ISRC1_4 :Result:='mmAFMT_ISRC1_4'; + mmAFMT_ISRC2_0 :Result:='mmAFMT_ISRC2_0'; + mmAFMT_ISRC2_1 :Result:='mmAFMT_ISRC2_1'; + mmAFMT_ISRC2_2 :Result:='mmAFMT_ISRC2_2'; + mmAFMT_ISRC2_3 :Result:='mmAFMT_ISRC2_3'; + mmAFMT_AVI_INFO0 :Result:='mmAFMT_AVI_INFO0'; + mmAFMT_AVI_INFO1 :Result:='mmAFMT_AVI_INFO1'; + mmAFMT_AVI_INFO2 :Result:='mmAFMT_AVI_INFO2'; + mmAFMT_AVI_INFO3 :Result:='mmAFMT_AVI_INFO3'; + mmAFMT_MPEG_INFO0 :Result:='mmAFMT_MPEG_INFO0'; + mmAFMT_MPEG_INFO1 :Result:='mmAFMT_MPEG_INFO1'; + mmAFMT_GENERIC_HDR :Result:='mmAFMT_GENERIC_HDR'; + mmAFMT_GENERIC_0 :Result:='mmAFMT_GENERIC_0'; + mmAFMT_GENERIC_1 :Result:='mmAFMT_GENERIC_1'; + mmAFMT_GENERIC_2 :Result:='mmAFMT_GENERIC_2'; + mmAFMT_GENERIC_3 :Result:='mmAFMT_GENERIC_3'; + mmAFMT_GENERIC_4 :Result:='mmAFMT_GENERIC_4'; + mmAFMT_GENERIC_5 :Result:='mmAFMT_GENERIC_5'; + mmAFMT_GENERIC_6 :Result:='mmAFMT_GENERIC_6'; + mmAFMT_GENERIC_7 :Result:='mmAFMT_GENERIC_7'; + mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG0_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG0_HDMI_ACR_32_0 :Result:='mmDIG0_HDMI_ACR_32_0'; + mmDIG0_HDMI_ACR_32_1 :Result:='mmDIG0_HDMI_ACR_32_1'; + mmDIG0_HDMI_ACR_44_0 :Result:='mmDIG0_HDMI_ACR_44_0'; + mmDIG0_HDMI_ACR_44_1 :Result:='mmDIG0_HDMI_ACR_44_1'; + mmDIG0_HDMI_ACR_48_0 :Result:='mmDIG0_HDMI_ACR_48_0'; + mmDIG0_HDMI_ACR_48_1 :Result:='mmDIG0_HDMI_ACR_48_1'; + mmDIG0_HDMI_ACR_STATUS_0 :Result:='mmDIG0_HDMI_ACR_STATUS_0'; + mmDIG0_HDMI_ACR_STATUS_1 :Result:='mmDIG0_HDMI_ACR_STATUS_1'; + mmAFMT_AUDIO_INFO0 :Result:='mmAFMT_AUDIO_INFO0'; + mmAFMT_AUDIO_INFO1 :Result:='mmAFMT_AUDIO_INFO1'; + mmAFMT_60958_0 :Result:='mmAFMT_60958_0'; + mmAFMT_60958_1 :Result:='mmAFMT_60958_1'; + mmAFMT_AUDIO_CRC_CONTROL :Result:='mmAFMT_AUDIO_CRC_CONTROL'; + mmAFMT_RAMP_CONTROL0 :Result:='mmAFMT_RAMP_CONTROL0'; + mmAFMT_RAMP_CONTROL1 :Result:='mmAFMT_RAMP_CONTROL1'; + mmAFMT_RAMP_CONTROL2 :Result:='mmAFMT_RAMP_CONTROL2'; + mmAFMT_RAMP_CONTROL3 :Result:='mmAFMT_RAMP_CONTROL3'; + mmAFMT_60958_2 :Result:='mmAFMT_60958_2'; + mmAFMT_AUDIO_CRC_RESULT :Result:='mmAFMT_AUDIO_CRC_RESULT'; + mmAFMT_STATUS :Result:='mmAFMT_STATUS'; + mmAFMT_AUDIO_PACKET_CONTROL :Result:='mmAFMT_AUDIO_PACKET_CONTROL'; + mmAFMT_VBI_PACKET_CONTROL :Result:='mmAFMT_VBI_PACKET_CONTROL'; + mmAFMT_INFOFRAME_CONTROL0 :Result:='mmAFMT_INFOFRAME_CONTROL0'; + mmAFMT_AUDIO_SRC_CONTROL :Result:='mmAFMT_AUDIO_SRC_CONTROL'; + mmAFMT_AUDIO_DBG_DTO_CNTL :Result:='mmAFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG0_DIG_BE_CNTL :Result:='mmDIG0_DIG_BE_CNTL'; + mmDIG0_DIG_BE_EN_CNTL :Result:='mmDIG0_DIG_BE_EN_CNTL'; + mmDIG0_TMDS_CNTL :Result:='mmDIG0_TMDS_CNTL'; + mmDIG0_TMDS_CONTROL_CHAR :Result:='mmDIG0_TMDS_CONTROL_CHAR'; + mmDIG0_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG0_TMDS_CONTROL0_FEEDBACK'; + mmDIG0_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG0_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG0_TMDS_DEBUG :Result:='mmDIG0_TMDS_DEBUG'; + mmDIG0_TMDS_CTL_BITS :Result:='mmDIG0_TMDS_CTL_BITS'; + mmDIG0_TMDS_DCBALANCER_CONTROL :Result:='mmDIG0_TMDS_DCBALANCER_CONTROL'; + mmDIG0_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG0_TMDS_CTL0_1_GEN_CNTL'; + mmDIG0_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG0_TMDS_CTL2_3_GEN_CNTL'; + mmDIG0_LVDS_DATA_CNTL :Result:='mmDIG0_LVDS_DATA_CNTL'; + mmDIG0_DIG_LANE_ENABLE :Result:='mmDIG0_DIG_LANE_ENABLE'; + mmDIG0_DIG_TEST_DEBUG_INDEX :Result:='mmDIG0_DIG_TEST_DEBUG_INDEX'; + mmDIG0_DIG_TEST_DEBUG_DATA :Result:='mmDIG0_DIG_TEST_DEBUG_DATA'; + mmDIG0_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG0_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG0_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG0_DIG_FE_TEST_DEBUG_DATA'; + mmCRTC5_CRTC_PIXEL_DATA_READBACK :Result:='mmCRTC5_CRTC_PIXEL_DATA_READBACK'; + mmDP0_DP_LINK_CNTL :Result:='mmDP0_DP_LINK_CNTL'; + mmDP0_DP_PIXEL_FORMAT :Result:='mmDP0_DP_PIXEL_FORMAT'; + mmDP0_DP_MSA_COLORIMETRY :Result:='mmDP0_DP_MSA_COLORIMETRY'; + mmDP0_DP_CONFIG :Result:='mmDP0_DP_CONFIG'; + mmDP0_DP_VID_STREAM_CNTL :Result:='mmDP0_DP_VID_STREAM_CNTL'; + mmDP0_DP_STEER_FIFO :Result:='mmDP0_DP_STEER_FIFO'; + mmDP0_DP_MSA_MISC :Result:='mmDP0_DP_MSA_MISC'; + mmDP0_DP_VID_TIMING :Result:='mmDP0_DP_VID_TIMING'; + mmDP0_DP_VID_N :Result:='mmDP0_DP_VID_N'; + mmDP0_DP_VID_M :Result:='mmDP0_DP_VID_M'; + mmDP0_DP_LINK_FRAMING_CNTL :Result:='mmDP0_DP_LINK_FRAMING_CNTL'; + mmDP0_DP_HBR2_EYE_PATTERN :Result:='mmDP0_DP_HBR2_EYE_PATTERN'; + mmDP0_DP_VID_MSA_VBID :Result:='mmDP0_DP_VID_MSA_VBID'; + mmDP0_DP_VID_INTERRUPT_CNTL :Result:='mmDP0_DP_VID_INTERRUPT_CNTL'; + mmDP0_DP_DPHY_CNTL :Result:='mmDP0_DP_DPHY_CNTL'; + mmDP0_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP0_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP0_DP_DPHY_SYM0 :Result:='mmDP0_DP_DPHY_SYM0'; + mmDP0_DP_DPHY_SYM1 :Result:='mmDP0_DP_DPHY_SYM1'; + mmDP0_DP_DPHY_SYM2 :Result:='mmDP0_DP_DPHY_SYM2'; + mmDP0_DP_DPHY_8B10B_CNTL :Result:='mmDP0_DP_DPHY_8B10B_CNTL'; + mmDP0_DP_DPHY_PRBS_CNTL :Result:='mmDP0_DP_DPHY_PRBS_CNTL'; + mmDP0_DP_DPHY_CRC_EN :Result:='mmDP0_DP_DPHY_CRC_EN'; + mmDP0_DP_DPHY_CRC_CNTL :Result:='mmDP0_DP_DPHY_CRC_CNTL'; + mmDP0_DP_DPHY_CRC_RESULT :Result:='mmDP0_DP_DPHY_CRC_RESULT'; + mmDP0_DP_DPHY_CRC_MST_CNTL :Result:='mmDP0_DP_DPHY_CRC_MST_CNTL'; + mmDP0_DP_DPHY_CRC_MST_STATUS :Result:='mmDP0_DP_DPHY_CRC_MST_STATUS'; + mmDP0_DP_DPHY_FAST_TRAINING :Result:='mmDP0_DP_DPHY_FAST_TRAINING'; + mmDP0_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP0_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP0_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP0_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP0_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP0_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP0_DP_SEC_CNTL :Result:='mmDP0_DP_SEC_CNTL'; + mmDP0_DP_SEC_CNTL1 :Result:='mmDP0_DP_SEC_CNTL1'; + mmDP0_DP_SEC_FRAMING1 :Result:='mmDP0_DP_SEC_FRAMING1'; + mmDP0_DP_SEC_FRAMING2 :Result:='mmDP0_DP_SEC_FRAMING2'; + mmDP0_DP_SEC_FRAMING3 :Result:='mmDP0_DP_SEC_FRAMING3'; + mmDP0_DP_SEC_FRAMING4 :Result:='mmDP0_DP_SEC_FRAMING4'; + mmDP0_DP_SEC_AUD_N :Result:='mmDP0_DP_SEC_AUD_N'; + mmDP0_DP_SEC_AUD_N_READBACK :Result:='mmDP0_DP_SEC_AUD_N_READBACK'; + mmDP0_DP_SEC_AUD_M :Result:='mmDP0_DP_SEC_AUD_M'; + mmDP0_DP_SEC_AUD_M_READBACK :Result:='mmDP0_DP_SEC_AUD_M_READBACK'; + mmDP0_DP_SEC_TIMESTAMP :Result:='mmDP0_DP_SEC_TIMESTAMP'; + mmDP0_DP_SEC_PACKET_CNTL :Result:='mmDP0_DP_SEC_PACKET_CNTL'; + mmDP0_DP_MSE_RATE_CNTL :Result:='mmDP0_DP_MSE_RATE_CNTL'; + mmDP0_DP_MSE_RATE_UPDATE :Result:='mmDP0_DP_MSE_RATE_UPDATE'; + mmDP0_DP_MSE_SAT0 :Result:='mmDP0_DP_MSE_SAT0'; + mmDP0_DP_MSE_SAT1 :Result:='mmDP0_DP_MSE_SAT1'; + mmDP0_DP_MSE_SAT2 :Result:='mmDP0_DP_MSE_SAT2'; + mmDP0_DP_MSE_SAT_UPDATE :Result:='mmDP0_DP_MSE_SAT_UPDATE'; + mmDP0_DP_MSE_LINK_TIMING :Result:='mmDP0_DP_MSE_LINK_TIMING'; + mmDP0_DP_MSE_MISC_CNTL :Result:='mmDP0_DP_MSE_MISC_CNTL'; + mmDP0_DP_TEST_DEBUG_INDEX :Result:='mmDP0_DP_TEST_DEBUG_INDEX'; + mmDP0_DP_TEST_DEBUG_DATA :Result:='mmDP0_DP_TEST_DEBUG_DATA'; + mmDP0_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP0_DP_FE_TEST_DEBUG_INDEX'; + mmDP0_DP_FE_TEST_DEBUG_DATA :Result:='mmDP0_DP_FE_TEST_DEBUG_DATA'; + mmDIG1_DIG_FE_CNTL :Result:='mmDIG1_DIG_FE_CNTL'; + mmDIG1_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG1_DIG_OUTPUT_CRC_CNTL'; + mmDIG1_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG1_DIG_OUTPUT_CRC_RESULT'; + mmDIG1_DIG_CLOCK_PATTERN :Result:='mmDIG1_DIG_CLOCK_PATTERN'; + mmDIG1_DIG_TEST_PATTERN :Result:='mmDIG1_DIG_TEST_PATTERN'; + mmDIG1_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG1_DIG_RANDOM_PATTERN_SEED'; + mmDIG1_DIG_FIFO_STATUS :Result:='mmDIG1_DIG_FIFO_STATUS'; + mmDIG1_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG1_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG1_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG1_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG1_HDMI_CONTROL :Result:='mmDIG1_HDMI_CONTROL'; + mmDIG1_HDMI_STATUS :Result:='mmDIG1_HDMI_STATUS'; + mmDIG1_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG1_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG1_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG1_HDMI_ACR_PACKET_CONTROL'; + mmDIG1_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG1_HDMI_VBI_PACKET_CONTROL'; + mmDIG1_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG1_HDMI_INFOFRAME_CONTROL0'; + mmDIG1_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG1_HDMI_INFOFRAME_CONTROL1'; + mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG1_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG1_HDMI_GC :Result:='mmDIG1_HDMI_GC'; + mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG1_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG1_AFMT_ISRC1_0 :Result:='mmDIG1_AFMT_ISRC1_0'; + mmDIG1_AFMT_ISRC1_1 :Result:='mmDIG1_AFMT_ISRC1_1'; + mmDIG1_AFMT_ISRC1_2 :Result:='mmDIG1_AFMT_ISRC1_2'; + mmDIG1_AFMT_ISRC1_3 :Result:='mmDIG1_AFMT_ISRC1_3'; + mmDIG1_AFMT_ISRC1_4 :Result:='mmDIG1_AFMT_ISRC1_4'; + mmDIG1_AFMT_ISRC2_0 :Result:='mmDIG1_AFMT_ISRC2_0'; + mmDIG1_AFMT_ISRC2_1 :Result:='mmDIG1_AFMT_ISRC2_1'; + mmDIG1_AFMT_ISRC2_2 :Result:='mmDIG1_AFMT_ISRC2_2'; + mmDIG1_AFMT_ISRC2_3 :Result:='mmDIG1_AFMT_ISRC2_3'; + mmDIG1_AFMT_AVI_INFO0 :Result:='mmDIG1_AFMT_AVI_INFO0'; + mmDIG1_AFMT_AVI_INFO1 :Result:='mmDIG1_AFMT_AVI_INFO1'; + mmDIG1_AFMT_AVI_INFO2 :Result:='mmDIG1_AFMT_AVI_INFO2'; + mmDIG1_AFMT_AVI_INFO3 :Result:='mmDIG1_AFMT_AVI_INFO3'; + mmDIG1_AFMT_MPEG_INFO0 :Result:='mmDIG1_AFMT_MPEG_INFO0'; + mmDIG1_AFMT_MPEG_INFO1 :Result:='mmDIG1_AFMT_MPEG_INFO1'; + mmDIG1_AFMT_GENERIC_HDR :Result:='mmDIG1_AFMT_GENERIC_HDR'; + mmDIG1_AFMT_GENERIC_0 :Result:='mmDIG1_AFMT_GENERIC_0'; + mmDIG1_AFMT_GENERIC_1 :Result:='mmDIG1_AFMT_GENERIC_1'; + mmDIG1_AFMT_GENERIC_2 :Result:='mmDIG1_AFMT_GENERIC_2'; + mmDIG1_AFMT_GENERIC_3 :Result:='mmDIG1_AFMT_GENERIC_3'; + mmDIG1_AFMT_GENERIC_4 :Result:='mmDIG1_AFMT_GENERIC_4'; + mmDIG1_AFMT_GENERIC_5 :Result:='mmDIG1_AFMT_GENERIC_5'; + mmDIG1_AFMT_GENERIC_6 :Result:='mmDIG1_AFMT_GENERIC_6'; + mmDIG1_AFMT_GENERIC_7 :Result:='mmDIG1_AFMT_GENERIC_7'; + mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG1_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG1_HDMI_ACR_32_0 :Result:='mmDIG1_HDMI_ACR_32_0'; + mmDIG1_HDMI_ACR_32_1 :Result:='mmDIG1_HDMI_ACR_32_1'; + mmDIG1_HDMI_ACR_44_0 :Result:='mmDIG1_HDMI_ACR_44_0'; + mmDIG1_HDMI_ACR_44_1 :Result:='mmDIG1_HDMI_ACR_44_1'; + mmDIG1_HDMI_ACR_48_0 :Result:='mmDIG1_HDMI_ACR_48_0'; + mmDIG1_HDMI_ACR_48_1 :Result:='mmDIG1_HDMI_ACR_48_1'; + mmDIG1_HDMI_ACR_STATUS_0 :Result:='mmDIG1_HDMI_ACR_STATUS_0'; + mmDIG1_HDMI_ACR_STATUS_1 :Result:='mmDIG1_HDMI_ACR_STATUS_1'; + mmDIG1_AFMT_AUDIO_INFO0 :Result:='mmDIG1_AFMT_AUDIO_INFO0'; + mmDIG1_AFMT_AUDIO_INFO1 :Result:='mmDIG1_AFMT_AUDIO_INFO1'; + mmDIG1_AFMT_60958_0 :Result:='mmDIG1_AFMT_60958_0'; + mmDIG1_AFMT_60958_1 :Result:='mmDIG1_AFMT_60958_1'; + mmDIG1_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG1_AFMT_AUDIO_CRC_CONTROL'; + mmDIG1_AFMT_RAMP_CONTROL0 :Result:='mmDIG1_AFMT_RAMP_CONTROL0'; + mmDIG1_AFMT_RAMP_CONTROL1 :Result:='mmDIG1_AFMT_RAMP_CONTROL1'; + mmDIG1_AFMT_RAMP_CONTROL2 :Result:='mmDIG1_AFMT_RAMP_CONTROL2'; + mmDIG1_AFMT_RAMP_CONTROL3 :Result:='mmDIG1_AFMT_RAMP_CONTROL3'; + mmDIG1_AFMT_60958_2 :Result:='mmDIG1_AFMT_60958_2'; + mmDIG1_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG1_AFMT_AUDIO_CRC_RESULT'; + mmDIG1_AFMT_STATUS :Result:='mmDIG1_AFMT_STATUS'; + mmDIG1_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG1_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG1_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG1_AFMT_VBI_PACKET_CONTROL'; + mmDIG1_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG1_AFMT_INFOFRAME_CONTROL0'; + mmDIG1_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG1_AFMT_AUDIO_SRC_CONTROL'; + mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG1_DIG_BE_CNTL :Result:='mmDIG1_DIG_BE_CNTL'; + mmDIG1_DIG_BE_EN_CNTL :Result:='mmDIG1_DIG_BE_EN_CNTL'; + mmDIG1_TMDS_CNTL :Result:='mmDIG1_TMDS_CNTL'; + mmDIG1_TMDS_CONTROL_CHAR :Result:='mmDIG1_TMDS_CONTROL_CHAR'; + mmDIG1_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG1_TMDS_CONTROL0_FEEDBACK'; + mmDIG1_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG1_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG1_TMDS_DEBUG :Result:='mmDIG1_TMDS_DEBUG'; + mmDIG1_TMDS_CTL_BITS :Result:='mmDIG1_TMDS_CTL_BITS'; + mmDIG1_TMDS_DCBALANCER_CONTROL :Result:='mmDIG1_TMDS_DCBALANCER_CONTROL'; + mmDIG1_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG1_TMDS_CTL0_1_GEN_CNTL'; + mmDIG1_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG1_TMDS_CTL2_3_GEN_CNTL'; + mmDIG1_LVDS_DATA_CNTL :Result:='mmDIG1_LVDS_DATA_CNTL'; + mmDIG1_DIG_LANE_ENABLE :Result:='mmDIG1_DIG_LANE_ENABLE'; + mmDIG1_DIG_TEST_DEBUG_INDEX :Result:='mmDIG1_DIG_TEST_DEBUG_INDEX'; + mmDIG1_DIG_TEST_DEBUG_DATA :Result:='mmDIG1_DIG_TEST_DEBUG_DATA'; + mmDIG1_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG1_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG1_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG1_DIG_FE_TEST_DEBUG_DATA'; + mmDP1_DP_LINK_CNTL :Result:='mmDP1_DP_LINK_CNTL'; + mmDP1_DP_PIXEL_FORMAT :Result:='mmDP1_DP_PIXEL_FORMAT'; + mmDP1_DP_MSA_COLORIMETRY :Result:='mmDP1_DP_MSA_COLORIMETRY'; + mmDP1_DP_CONFIG :Result:='mmDP1_DP_CONFIG'; + mmDP1_DP_VID_STREAM_CNTL :Result:='mmDP1_DP_VID_STREAM_CNTL'; + mmDP1_DP_STEER_FIFO :Result:='mmDP1_DP_STEER_FIFO'; + mmDP1_DP_MSA_MISC :Result:='mmDP1_DP_MSA_MISC'; + mmDP1_DP_VID_TIMING :Result:='mmDP1_DP_VID_TIMING'; + mmDP1_DP_VID_N :Result:='mmDP1_DP_VID_N'; + mmDP1_DP_VID_M :Result:='mmDP1_DP_VID_M'; + mmDP1_DP_LINK_FRAMING_CNTL :Result:='mmDP1_DP_LINK_FRAMING_CNTL'; + mmDP1_DP_HBR2_EYE_PATTERN :Result:='mmDP1_DP_HBR2_EYE_PATTERN'; + mmDP1_DP_VID_MSA_VBID :Result:='mmDP1_DP_VID_MSA_VBID'; + mmDP1_DP_VID_INTERRUPT_CNTL :Result:='mmDP1_DP_VID_INTERRUPT_CNTL'; + mmDP1_DP_DPHY_CNTL :Result:='mmDP1_DP_DPHY_CNTL'; + mmDP1_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP1_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP1_DP_DPHY_SYM0 :Result:='mmDP1_DP_DPHY_SYM0'; + mmDP1_DP_DPHY_SYM1 :Result:='mmDP1_DP_DPHY_SYM1'; + mmDP1_DP_DPHY_SYM2 :Result:='mmDP1_DP_DPHY_SYM2'; + mmDP1_DP_DPHY_8B10B_CNTL :Result:='mmDP1_DP_DPHY_8B10B_CNTL'; + mmDP1_DP_DPHY_PRBS_CNTL :Result:='mmDP1_DP_DPHY_PRBS_CNTL'; + mmDP1_DP_DPHY_CRC_EN :Result:='mmDP1_DP_DPHY_CRC_EN'; + mmDP1_DP_DPHY_CRC_CNTL :Result:='mmDP1_DP_DPHY_CRC_CNTL'; + mmDP1_DP_DPHY_CRC_RESULT :Result:='mmDP1_DP_DPHY_CRC_RESULT'; + mmDP1_DP_DPHY_CRC_MST_CNTL :Result:='mmDP1_DP_DPHY_CRC_MST_CNTL'; + mmDP1_DP_DPHY_CRC_MST_STATUS :Result:='mmDP1_DP_DPHY_CRC_MST_STATUS'; + mmDP1_DP_DPHY_FAST_TRAINING :Result:='mmDP1_DP_DPHY_FAST_TRAINING'; + mmDP1_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP1_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP1_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP1_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP1_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP1_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP1_DP_SEC_CNTL :Result:='mmDP1_DP_SEC_CNTL'; + mmDP1_DP_SEC_CNTL1 :Result:='mmDP1_DP_SEC_CNTL1'; + mmDP1_DP_SEC_FRAMING1 :Result:='mmDP1_DP_SEC_FRAMING1'; + mmDP1_DP_SEC_FRAMING2 :Result:='mmDP1_DP_SEC_FRAMING2'; + mmDP1_DP_SEC_FRAMING3 :Result:='mmDP1_DP_SEC_FRAMING3'; + mmDP1_DP_SEC_FRAMING4 :Result:='mmDP1_DP_SEC_FRAMING4'; + mmDP1_DP_SEC_AUD_N :Result:='mmDP1_DP_SEC_AUD_N'; + mmDP1_DP_SEC_AUD_N_READBACK :Result:='mmDP1_DP_SEC_AUD_N_READBACK'; + mmDP1_DP_SEC_AUD_M :Result:='mmDP1_DP_SEC_AUD_M'; + mmDP1_DP_SEC_AUD_M_READBACK :Result:='mmDP1_DP_SEC_AUD_M_READBACK'; + mmDP1_DP_SEC_TIMESTAMP :Result:='mmDP1_DP_SEC_TIMESTAMP'; + mmDP1_DP_SEC_PACKET_CNTL :Result:='mmDP1_DP_SEC_PACKET_CNTL'; + mmDP1_DP_MSE_RATE_CNTL :Result:='mmDP1_DP_MSE_RATE_CNTL'; + mmDP1_DP_MSE_RATE_UPDATE :Result:='mmDP1_DP_MSE_RATE_UPDATE'; + mmDP1_DP_MSE_SAT0 :Result:='mmDP1_DP_MSE_SAT0'; + mmDP1_DP_MSE_SAT1 :Result:='mmDP1_DP_MSE_SAT1'; + mmDP1_DP_MSE_SAT2 :Result:='mmDP1_DP_MSE_SAT2'; + mmDP1_DP_MSE_SAT_UPDATE :Result:='mmDP1_DP_MSE_SAT_UPDATE'; + mmDP1_DP_MSE_LINK_TIMING :Result:='mmDP1_DP_MSE_LINK_TIMING'; + mmDP1_DP_MSE_MISC_CNTL :Result:='mmDP1_DP_MSE_MISC_CNTL'; + mmDP1_DP_TEST_DEBUG_INDEX :Result:='mmDP1_DP_TEST_DEBUG_INDEX'; + mmDP1_DP_TEST_DEBUG_DATA :Result:='mmDP1_DP_TEST_DEBUG_DATA'; + mmDP1_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP1_DP_FE_TEST_DEBUG_INDEX'; + mmDP1_DP_FE_TEST_DEBUG_DATA :Result:='mmDP1_DP_FE_TEST_DEBUG_DATA'; + mmDIG2_DIG_FE_CNTL :Result:='mmDIG2_DIG_FE_CNTL'; + mmDIG2_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG2_DIG_OUTPUT_CRC_CNTL'; + mmDIG2_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG2_DIG_OUTPUT_CRC_RESULT'; + mmDIG2_DIG_CLOCK_PATTERN :Result:='mmDIG2_DIG_CLOCK_PATTERN'; + mmDIG2_DIG_TEST_PATTERN :Result:='mmDIG2_DIG_TEST_PATTERN'; + mmDIG2_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG2_DIG_RANDOM_PATTERN_SEED'; + mmDIG2_DIG_FIFO_STATUS :Result:='mmDIG2_DIG_FIFO_STATUS'; + mmDIG2_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG2_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG2_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG2_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG2_HDMI_CONTROL :Result:='mmDIG2_HDMI_CONTROL'; + mmDIG2_HDMI_STATUS :Result:='mmDIG2_HDMI_STATUS'; + mmDIG2_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG2_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG2_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG2_HDMI_ACR_PACKET_CONTROL'; + mmDIG2_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG2_HDMI_VBI_PACKET_CONTROL'; + mmDIG2_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG2_HDMI_INFOFRAME_CONTROL0'; + mmDIG2_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG2_HDMI_INFOFRAME_CONTROL1'; + mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG2_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG2_HDMI_GC :Result:='mmDIG2_HDMI_GC'; + mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG2_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG2_AFMT_ISRC1_0 :Result:='mmDIG2_AFMT_ISRC1_0'; + mmDIG2_AFMT_ISRC1_1 :Result:='mmDIG2_AFMT_ISRC1_1'; + mmDIG2_AFMT_ISRC1_2 :Result:='mmDIG2_AFMT_ISRC1_2'; + mmDIG2_AFMT_ISRC1_3 :Result:='mmDIG2_AFMT_ISRC1_3'; + mmDIG2_AFMT_ISRC1_4 :Result:='mmDIG2_AFMT_ISRC1_4'; + mmDIG2_AFMT_ISRC2_0 :Result:='mmDIG2_AFMT_ISRC2_0'; + mmDIG2_AFMT_ISRC2_1 :Result:='mmDIG2_AFMT_ISRC2_1'; + mmDIG2_AFMT_ISRC2_2 :Result:='mmDIG2_AFMT_ISRC2_2'; + mmDIG2_AFMT_ISRC2_3 :Result:='mmDIG2_AFMT_ISRC2_3'; + mmDIG2_AFMT_AVI_INFO0 :Result:='mmDIG2_AFMT_AVI_INFO0'; + mmDIG2_AFMT_AVI_INFO1 :Result:='mmDIG2_AFMT_AVI_INFO1'; + mmDIG2_AFMT_AVI_INFO2 :Result:='mmDIG2_AFMT_AVI_INFO2'; + mmDIG2_AFMT_AVI_INFO3 :Result:='mmDIG2_AFMT_AVI_INFO3'; + mmDIG2_AFMT_MPEG_INFO0 :Result:='mmDIG2_AFMT_MPEG_INFO0'; + mmDIG2_AFMT_MPEG_INFO1 :Result:='mmDIG2_AFMT_MPEG_INFO1'; + mmDIG2_AFMT_GENERIC_HDR :Result:='mmDIG2_AFMT_GENERIC_HDR'; + mmDIG2_AFMT_GENERIC_0 :Result:='mmDIG2_AFMT_GENERIC_0'; + mmDIG2_AFMT_GENERIC_1 :Result:='mmDIG2_AFMT_GENERIC_1'; + mmDIG2_AFMT_GENERIC_2 :Result:='mmDIG2_AFMT_GENERIC_2'; + mmDIG2_AFMT_GENERIC_3 :Result:='mmDIG2_AFMT_GENERIC_3'; + mmDIG2_AFMT_GENERIC_4 :Result:='mmDIG2_AFMT_GENERIC_4'; + mmDIG2_AFMT_GENERIC_5 :Result:='mmDIG2_AFMT_GENERIC_5'; + mmDIG2_AFMT_GENERIC_6 :Result:='mmDIG2_AFMT_GENERIC_6'; + mmDIG2_AFMT_GENERIC_7 :Result:='mmDIG2_AFMT_GENERIC_7'; + mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG2_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG2_HDMI_ACR_32_0 :Result:='mmDIG2_HDMI_ACR_32_0'; + mmDIG2_HDMI_ACR_32_1 :Result:='mmDIG2_HDMI_ACR_32_1'; + mmDIG2_HDMI_ACR_44_0 :Result:='mmDIG2_HDMI_ACR_44_0'; + mmDIG2_HDMI_ACR_44_1 :Result:='mmDIG2_HDMI_ACR_44_1'; + mmDIG2_HDMI_ACR_48_0 :Result:='mmDIG2_HDMI_ACR_48_0'; + mmDIG2_HDMI_ACR_48_1 :Result:='mmDIG2_HDMI_ACR_48_1'; + mmDIG2_HDMI_ACR_STATUS_0 :Result:='mmDIG2_HDMI_ACR_STATUS_0'; + mmDIG2_HDMI_ACR_STATUS_1 :Result:='mmDIG2_HDMI_ACR_STATUS_1'; + mmDIG2_AFMT_AUDIO_INFO0 :Result:='mmDIG2_AFMT_AUDIO_INFO0'; + mmDIG2_AFMT_AUDIO_INFO1 :Result:='mmDIG2_AFMT_AUDIO_INFO1'; + mmDIG2_AFMT_60958_0 :Result:='mmDIG2_AFMT_60958_0'; + mmDIG2_AFMT_60958_1 :Result:='mmDIG2_AFMT_60958_1'; + mmDIG2_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG2_AFMT_AUDIO_CRC_CONTROL'; + mmDIG2_AFMT_RAMP_CONTROL0 :Result:='mmDIG2_AFMT_RAMP_CONTROL0'; + mmDIG2_AFMT_RAMP_CONTROL1 :Result:='mmDIG2_AFMT_RAMP_CONTROL1'; + mmDIG2_AFMT_RAMP_CONTROL2 :Result:='mmDIG2_AFMT_RAMP_CONTROL2'; + mmDIG2_AFMT_RAMP_CONTROL3 :Result:='mmDIG2_AFMT_RAMP_CONTROL3'; + mmDIG2_AFMT_60958_2 :Result:='mmDIG2_AFMT_60958_2'; + mmDIG2_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG2_AFMT_AUDIO_CRC_RESULT'; + mmDIG2_AFMT_STATUS :Result:='mmDIG2_AFMT_STATUS'; + mmDIG2_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG2_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG2_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG2_AFMT_VBI_PACKET_CONTROL'; + mmDIG2_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG2_AFMT_INFOFRAME_CONTROL0'; + mmDIG2_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG2_AFMT_AUDIO_SRC_CONTROL'; + mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG2_DIG_BE_CNTL :Result:='mmDIG2_DIG_BE_CNTL'; + mmDIG2_DIG_BE_EN_CNTL :Result:='mmDIG2_DIG_BE_EN_CNTL'; + mmDIG2_TMDS_CNTL :Result:='mmDIG2_TMDS_CNTL'; + mmDIG2_TMDS_CONTROL_CHAR :Result:='mmDIG2_TMDS_CONTROL_CHAR'; + mmDIG2_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG2_TMDS_CONTROL0_FEEDBACK'; + mmDIG2_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG2_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG2_TMDS_DEBUG :Result:='mmDIG2_TMDS_DEBUG'; + mmDIG2_TMDS_CTL_BITS :Result:='mmDIG2_TMDS_CTL_BITS'; + mmDIG2_TMDS_DCBALANCER_CONTROL :Result:='mmDIG2_TMDS_DCBALANCER_CONTROL'; + mmDIG2_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG2_TMDS_CTL0_1_GEN_CNTL'; + mmDIG2_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG2_TMDS_CTL2_3_GEN_CNTL'; + mmDIG2_LVDS_DATA_CNTL :Result:='mmDIG2_LVDS_DATA_CNTL'; + mmDIG2_DIG_LANE_ENABLE :Result:='mmDIG2_DIG_LANE_ENABLE'; + mmDIG2_DIG_TEST_DEBUG_INDEX :Result:='mmDIG2_DIG_TEST_DEBUG_INDEX'; + mmDIG2_DIG_TEST_DEBUG_DATA :Result:='mmDIG2_DIG_TEST_DEBUG_DATA'; + mmDIG2_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG2_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG2_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG2_DIG_FE_TEST_DEBUG_DATA'; + mmDP2_DP_LINK_CNTL :Result:='mmDP2_DP_LINK_CNTL'; + mmDP2_DP_PIXEL_FORMAT :Result:='mmDP2_DP_PIXEL_FORMAT'; + mmDP2_DP_MSA_COLORIMETRY :Result:='mmDP2_DP_MSA_COLORIMETRY'; + mmDP2_DP_CONFIG :Result:='mmDP2_DP_CONFIG'; + mmDP2_DP_VID_STREAM_CNTL :Result:='mmDP2_DP_VID_STREAM_CNTL'; + mmDP2_DP_STEER_FIFO :Result:='mmDP2_DP_STEER_FIFO'; + mmDP2_DP_MSA_MISC :Result:='mmDP2_DP_MSA_MISC'; + mmDP2_DP_VID_TIMING :Result:='mmDP2_DP_VID_TIMING'; + mmDP2_DP_VID_N :Result:='mmDP2_DP_VID_N'; + mmDP2_DP_VID_M :Result:='mmDP2_DP_VID_M'; + mmDP2_DP_LINK_FRAMING_CNTL :Result:='mmDP2_DP_LINK_FRAMING_CNTL'; + mmDP2_DP_HBR2_EYE_PATTERN :Result:='mmDP2_DP_HBR2_EYE_PATTERN'; + mmDP2_DP_VID_MSA_VBID :Result:='mmDP2_DP_VID_MSA_VBID'; + mmDP2_DP_VID_INTERRUPT_CNTL :Result:='mmDP2_DP_VID_INTERRUPT_CNTL'; + mmDP2_DP_DPHY_CNTL :Result:='mmDP2_DP_DPHY_CNTL'; + mmDP2_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP2_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP2_DP_DPHY_SYM0 :Result:='mmDP2_DP_DPHY_SYM0'; + mmDP2_DP_DPHY_SYM1 :Result:='mmDP2_DP_DPHY_SYM1'; + mmDP2_DP_DPHY_SYM2 :Result:='mmDP2_DP_DPHY_SYM2'; + mmDP2_DP_DPHY_8B10B_CNTL :Result:='mmDP2_DP_DPHY_8B10B_CNTL'; + mmDP2_DP_DPHY_PRBS_CNTL :Result:='mmDP2_DP_DPHY_PRBS_CNTL'; + mmDP2_DP_DPHY_CRC_EN :Result:='mmDP2_DP_DPHY_CRC_EN'; + mmDP2_DP_DPHY_CRC_CNTL :Result:='mmDP2_DP_DPHY_CRC_CNTL'; + mmDP2_DP_DPHY_CRC_RESULT :Result:='mmDP2_DP_DPHY_CRC_RESULT'; + mmDP2_DP_DPHY_CRC_MST_CNTL :Result:='mmDP2_DP_DPHY_CRC_MST_CNTL'; + mmDP2_DP_DPHY_CRC_MST_STATUS :Result:='mmDP2_DP_DPHY_CRC_MST_STATUS'; + mmDP2_DP_DPHY_FAST_TRAINING :Result:='mmDP2_DP_DPHY_FAST_TRAINING'; + mmDP2_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP2_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP2_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP2_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP2_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP2_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP2_DP_SEC_CNTL :Result:='mmDP2_DP_SEC_CNTL'; + mmDP2_DP_SEC_CNTL1 :Result:='mmDP2_DP_SEC_CNTL1'; + mmDP2_DP_SEC_FRAMING1 :Result:='mmDP2_DP_SEC_FRAMING1'; + mmDP2_DP_SEC_FRAMING2 :Result:='mmDP2_DP_SEC_FRAMING2'; + mmDP2_DP_SEC_FRAMING3 :Result:='mmDP2_DP_SEC_FRAMING3'; + mmDP2_DP_SEC_FRAMING4 :Result:='mmDP2_DP_SEC_FRAMING4'; + mmDP2_DP_SEC_AUD_N :Result:='mmDP2_DP_SEC_AUD_N'; + mmDP2_DP_SEC_AUD_N_READBACK :Result:='mmDP2_DP_SEC_AUD_N_READBACK'; + mmDP2_DP_SEC_AUD_M :Result:='mmDP2_DP_SEC_AUD_M'; + mmDP2_DP_SEC_AUD_M_READBACK :Result:='mmDP2_DP_SEC_AUD_M_READBACK'; + mmDP2_DP_SEC_TIMESTAMP :Result:='mmDP2_DP_SEC_TIMESTAMP'; + mmDP2_DP_SEC_PACKET_CNTL :Result:='mmDP2_DP_SEC_PACKET_CNTL'; + mmDP2_DP_MSE_RATE_CNTL :Result:='mmDP2_DP_MSE_RATE_CNTL'; + mmDP2_DP_MSE_RATE_UPDATE :Result:='mmDP2_DP_MSE_RATE_UPDATE'; + mmDP2_DP_MSE_SAT0 :Result:='mmDP2_DP_MSE_SAT0'; + mmDP2_DP_MSE_SAT1 :Result:='mmDP2_DP_MSE_SAT1'; + mmDP2_DP_MSE_SAT2 :Result:='mmDP2_DP_MSE_SAT2'; + mmDP2_DP_MSE_SAT_UPDATE :Result:='mmDP2_DP_MSE_SAT_UPDATE'; + mmDP2_DP_MSE_LINK_TIMING :Result:='mmDP2_DP_MSE_LINK_TIMING'; + mmDP2_DP_MSE_MISC_CNTL :Result:='mmDP2_DP_MSE_MISC_CNTL'; + mmDP2_DP_TEST_DEBUG_INDEX :Result:='mmDP2_DP_TEST_DEBUG_INDEX'; + mmDP2_DP_TEST_DEBUG_DATA :Result:='mmDP2_DP_TEST_DEBUG_DATA'; + mmDP2_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP2_DP_FE_TEST_DEBUG_INDEX'; + mmDP2_DP_FE_TEST_DEBUG_DATA :Result:='mmDP2_DP_FE_TEST_DEBUG_DATA'; + mmDIG3_DIG_FE_CNTL :Result:='mmDIG3_DIG_FE_CNTL'; + mmDIG3_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG3_DIG_OUTPUT_CRC_CNTL'; + mmDIG3_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG3_DIG_OUTPUT_CRC_RESULT'; + mmDIG3_DIG_CLOCK_PATTERN :Result:='mmDIG3_DIG_CLOCK_PATTERN'; + mmDIG3_DIG_TEST_PATTERN :Result:='mmDIG3_DIG_TEST_PATTERN'; + mmDIG3_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG3_DIG_RANDOM_PATTERN_SEED'; + mmDIG3_DIG_FIFO_STATUS :Result:='mmDIG3_DIG_FIFO_STATUS'; + mmDIG3_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG3_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG3_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG3_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG3_HDMI_CONTROL :Result:='mmDIG3_HDMI_CONTROL'; + mmDIG3_HDMI_STATUS :Result:='mmDIG3_HDMI_STATUS'; + mmDIG3_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG3_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG3_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG3_HDMI_ACR_PACKET_CONTROL'; + mmDIG3_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG3_HDMI_VBI_PACKET_CONTROL'; + mmDIG3_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG3_HDMI_INFOFRAME_CONTROL0'; + mmDIG3_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG3_HDMI_INFOFRAME_CONTROL1'; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG3_HDMI_GC :Result:='mmDIG3_HDMI_GC'; + mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG3_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG3_AFMT_ISRC1_0 :Result:='mmDIG3_AFMT_ISRC1_0'; + mmDIG3_AFMT_ISRC1_1 :Result:='mmDIG3_AFMT_ISRC1_1'; + mmDIG3_AFMT_ISRC1_2 :Result:='mmDIG3_AFMT_ISRC1_2'; + mmDIG3_AFMT_ISRC1_3 :Result:='mmDIG3_AFMT_ISRC1_3'; + mmDIG3_AFMT_ISRC1_4 :Result:='mmDIG3_AFMT_ISRC1_4'; + mmDIG3_AFMT_ISRC2_0 :Result:='mmDIG3_AFMT_ISRC2_0'; + mmDIG3_AFMT_ISRC2_1 :Result:='mmDIG3_AFMT_ISRC2_1'; + mmDIG3_AFMT_ISRC2_2 :Result:='mmDIG3_AFMT_ISRC2_2'; + mmDIG3_AFMT_ISRC2_3 :Result:='mmDIG3_AFMT_ISRC2_3'; + mmDIG3_AFMT_AVI_INFO0 :Result:='mmDIG3_AFMT_AVI_INFO0'; + mmDIG3_AFMT_AVI_INFO1 :Result:='mmDIG3_AFMT_AVI_INFO1'; + mmDIG3_AFMT_AVI_INFO2 :Result:='mmDIG3_AFMT_AVI_INFO2'; + mmDIG3_AFMT_AVI_INFO3 :Result:='mmDIG3_AFMT_AVI_INFO3'; + mmDIG3_AFMT_MPEG_INFO0 :Result:='mmDIG3_AFMT_MPEG_INFO0'; + mmDIG3_AFMT_MPEG_INFO1 :Result:='mmDIG3_AFMT_MPEG_INFO1'; + mmDIG3_AFMT_GENERIC_HDR :Result:='mmDIG3_AFMT_GENERIC_HDR'; + mmDIG3_AFMT_GENERIC_0 :Result:='mmDIG3_AFMT_GENERIC_0'; + mmDIG3_AFMT_GENERIC_1 :Result:='mmDIG3_AFMT_GENERIC_1'; + mmDIG3_AFMT_GENERIC_2 :Result:='mmDIG3_AFMT_GENERIC_2'; + mmDIG3_AFMT_GENERIC_3 :Result:='mmDIG3_AFMT_GENERIC_3'; + mmDIG3_AFMT_GENERIC_4 :Result:='mmDIG3_AFMT_GENERIC_4'; + mmDIG3_AFMT_GENERIC_5 :Result:='mmDIG3_AFMT_GENERIC_5'; + mmDIG3_AFMT_GENERIC_6 :Result:='mmDIG3_AFMT_GENERIC_6'; + mmDIG3_AFMT_GENERIC_7 :Result:='mmDIG3_AFMT_GENERIC_7'; + mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG3_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG3_HDMI_ACR_32_0 :Result:='mmDIG3_HDMI_ACR_32_0'; + mmDIG3_HDMI_ACR_32_1 :Result:='mmDIG3_HDMI_ACR_32_1'; + mmDIG3_HDMI_ACR_44_0 :Result:='mmDIG3_HDMI_ACR_44_0'; + mmDIG3_HDMI_ACR_44_1 :Result:='mmDIG3_HDMI_ACR_44_1'; + mmDIG3_HDMI_ACR_48_0 :Result:='mmDIG3_HDMI_ACR_48_0'; + mmDIG3_HDMI_ACR_48_1 :Result:='mmDIG3_HDMI_ACR_48_1'; + mmDIG3_HDMI_ACR_STATUS_0 :Result:='mmDIG3_HDMI_ACR_STATUS_0'; + mmDIG3_HDMI_ACR_STATUS_1 :Result:='mmDIG3_HDMI_ACR_STATUS_1'; + mmDIG3_AFMT_AUDIO_INFO0 :Result:='mmDIG3_AFMT_AUDIO_INFO0'; + mmDIG3_AFMT_AUDIO_INFO1 :Result:='mmDIG3_AFMT_AUDIO_INFO1'; + mmDIG3_AFMT_60958_0 :Result:='mmDIG3_AFMT_60958_0'; + mmDIG3_AFMT_60958_1 :Result:='mmDIG3_AFMT_60958_1'; + mmDIG3_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG3_AFMT_AUDIO_CRC_CONTROL'; + mmDIG3_AFMT_RAMP_CONTROL0 :Result:='mmDIG3_AFMT_RAMP_CONTROL0'; + mmDIG3_AFMT_RAMP_CONTROL1 :Result:='mmDIG3_AFMT_RAMP_CONTROL1'; + mmDIG3_AFMT_RAMP_CONTROL2 :Result:='mmDIG3_AFMT_RAMP_CONTROL2'; + mmDIG3_AFMT_RAMP_CONTROL3 :Result:='mmDIG3_AFMT_RAMP_CONTROL3'; + mmDIG3_AFMT_60958_2 :Result:='mmDIG3_AFMT_60958_2'; + mmDIG3_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG3_AFMT_AUDIO_CRC_RESULT'; + mmDIG3_AFMT_STATUS :Result:='mmDIG3_AFMT_STATUS'; + mmDIG3_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG3_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG3_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG3_AFMT_VBI_PACKET_CONTROL'; + mmDIG3_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG3_AFMT_INFOFRAME_CONTROL0'; + mmDIG3_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG3_AFMT_AUDIO_SRC_CONTROL'; + mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG3_DIG_BE_CNTL :Result:='mmDIG3_DIG_BE_CNTL'; + mmDIG3_DIG_BE_EN_CNTL :Result:='mmDIG3_DIG_BE_EN_CNTL'; + mmDIG3_TMDS_CNTL :Result:='mmDIG3_TMDS_CNTL'; + mmDIG3_TMDS_CONTROL_CHAR :Result:='mmDIG3_TMDS_CONTROL_CHAR'; + mmDIG3_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG3_TMDS_CONTROL0_FEEDBACK'; + mmDIG3_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG3_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG3_TMDS_DEBUG :Result:='mmDIG3_TMDS_DEBUG'; + mmDIG3_TMDS_CTL_BITS :Result:='mmDIG3_TMDS_CTL_BITS'; + mmDIG3_TMDS_DCBALANCER_CONTROL :Result:='mmDIG3_TMDS_DCBALANCER_CONTROL'; + mmDIG3_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG3_TMDS_CTL0_1_GEN_CNTL'; + mmDIG3_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG3_TMDS_CTL2_3_GEN_CNTL'; + mmDIG3_LVDS_DATA_CNTL :Result:='mmDIG3_LVDS_DATA_CNTL'; + mmDIG3_DIG_LANE_ENABLE :Result:='mmDIG3_DIG_LANE_ENABLE'; + mmDIG3_DIG_TEST_DEBUG_INDEX :Result:='mmDIG3_DIG_TEST_DEBUG_INDEX'; + mmDIG3_DIG_TEST_DEBUG_DATA :Result:='mmDIG3_DIG_TEST_DEBUG_DATA'; + mmDIG3_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG3_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG3_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG3_DIG_FE_TEST_DEBUG_DATA'; + mmDP3_DP_LINK_CNTL :Result:='mmDP3_DP_LINK_CNTL'; + mmDP3_DP_PIXEL_FORMAT :Result:='mmDP3_DP_PIXEL_FORMAT'; + mmDP3_DP_MSA_COLORIMETRY :Result:='mmDP3_DP_MSA_COLORIMETRY'; + mmDP3_DP_CONFIG :Result:='mmDP3_DP_CONFIG'; + mmDP3_DP_VID_STREAM_CNTL :Result:='mmDP3_DP_VID_STREAM_CNTL'; + mmDP3_DP_STEER_FIFO :Result:='mmDP3_DP_STEER_FIFO'; + mmDP3_DP_MSA_MISC :Result:='mmDP3_DP_MSA_MISC'; + mmDP3_DP_VID_TIMING :Result:='mmDP3_DP_VID_TIMING'; + mmDP3_DP_VID_N :Result:='mmDP3_DP_VID_N'; + mmDP3_DP_VID_M :Result:='mmDP3_DP_VID_M'; + mmDP3_DP_LINK_FRAMING_CNTL :Result:='mmDP3_DP_LINK_FRAMING_CNTL'; + mmDP3_DP_HBR2_EYE_PATTERN :Result:='mmDP3_DP_HBR2_EYE_PATTERN'; + mmDP3_DP_VID_MSA_VBID :Result:='mmDP3_DP_VID_MSA_VBID'; + mmDP3_DP_VID_INTERRUPT_CNTL :Result:='mmDP3_DP_VID_INTERRUPT_CNTL'; + mmDP3_DP_DPHY_CNTL :Result:='mmDP3_DP_DPHY_CNTL'; + mmDP3_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP3_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP3_DP_DPHY_SYM0 :Result:='mmDP3_DP_DPHY_SYM0'; + mmDP3_DP_DPHY_SYM1 :Result:='mmDP3_DP_DPHY_SYM1'; + mmDP3_DP_DPHY_SYM2 :Result:='mmDP3_DP_DPHY_SYM2'; + mmDP3_DP_DPHY_8B10B_CNTL :Result:='mmDP3_DP_DPHY_8B10B_CNTL'; + mmDP3_DP_DPHY_PRBS_CNTL :Result:='mmDP3_DP_DPHY_PRBS_CNTL'; + mmDP3_DP_DPHY_CRC_EN :Result:='mmDP3_DP_DPHY_CRC_EN'; + mmDP3_DP_DPHY_CRC_CNTL :Result:='mmDP3_DP_DPHY_CRC_CNTL'; + mmDP3_DP_DPHY_CRC_RESULT :Result:='mmDP3_DP_DPHY_CRC_RESULT'; + mmDP3_DP_DPHY_CRC_MST_CNTL :Result:='mmDP3_DP_DPHY_CRC_MST_CNTL'; + mmDP3_DP_DPHY_CRC_MST_STATUS :Result:='mmDP3_DP_DPHY_CRC_MST_STATUS'; + mmDP3_DP_DPHY_FAST_TRAINING :Result:='mmDP3_DP_DPHY_FAST_TRAINING'; + mmDP3_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP3_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP3_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP3_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP3_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP3_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP3_DP_SEC_CNTL :Result:='mmDP3_DP_SEC_CNTL'; + mmDP3_DP_SEC_CNTL1 :Result:='mmDP3_DP_SEC_CNTL1'; + mmDP3_DP_SEC_FRAMING1 :Result:='mmDP3_DP_SEC_FRAMING1'; + mmDP3_DP_SEC_FRAMING2 :Result:='mmDP3_DP_SEC_FRAMING2'; + mmDP3_DP_SEC_FRAMING3 :Result:='mmDP3_DP_SEC_FRAMING3'; + mmDP3_DP_SEC_FRAMING4 :Result:='mmDP3_DP_SEC_FRAMING4'; + mmDP3_DP_SEC_AUD_N :Result:='mmDP3_DP_SEC_AUD_N'; + mmDP3_DP_SEC_AUD_N_READBACK :Result:='mmDP3_DP_SEC_AUD_N_READBACK'; + mmDP3_DP_SEC_AUD_M :Result:='mmDP3_DP_SEC_AUD_M'; + mmDP3_DP_SEC_AUD_M_READBACK :Result:='mmDP3_DP_SEC_AUD_M_READBACK'; + mmDP3_DP_SEC_TIMESTAMP :Result:='mmDP3_DP_SEC_TIMESTAMP'; + mmDP3_DP_SEC_PACKET_CNTL :Result:='mmDP3_DP_SEC_PACKET_CNTL'; + mmDP3_DP_MSE_RATE_CNTL :Result:='mmDP3_DP_MSE_RATE_CNTL'; + mmDP3_DP_MSE_RATE_UPDATE :Result:='mmDP3_DP_MSE_RATE_UPDATE'; + mmDP3_DP_MSE_SAT0 :Result:='mmDP3_DP_MSE_SAT0'; + mmDP3_DP_MSE_SAT1 :Result:='mmDP3_DP_MSE_SAT1'; + mmDP3_DP_MSE_SAT2 :Result:='mmDP3_DP_MSE_SAT2'; + mmDP3_DP_MSE_SAT_UPDATE :Result:='mmDP3_DP_MSE_SAT_UPDATE'; + mmDP3_DP_MSE_LINK_TIMING :Result:='mmDP3_DP_MSE_LINK_TIMING'; + mmDP3_DP_MSE_MISC_CNTL :Result:='mmDP3_DP_MSE_MISC_CNTL'; + mmDP3_DP_TEST_DEBUG_INDEX :Result:='mmDP3_DP_TEST_DEBUG_INDEX'; + mmDP3_DP_TEST_DEBUG_DATA :Result:='mmDP3_DP_TEST_DEBUG_DATA'; + mmDP3_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP3_DP_FE_TEST_DEBUG_INDEX'; + mmDP3_DP_FE_TEST_DEBUG_DATA :Result:='mmDP3_DP_FE_TEST_DEBUG_DATA'; + mmDIG4_DIG_FE_CNTL :Result:='mmDIG4_DIG_FE_CNTL'; + mmDIG4_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG4_DIG_OUTPUT_CRC_CNTL'; + mmDIG4_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG4_DIG_OUTPUT_CRC_RESULT'; + mmDIG4_DIG_CLOCK_PATTERN :Result:='mmDIG4_DIG_CLOCK_PATTERN'; + mmDIG4_DIG_TEST_PATTERN :Result:='mmDIG4_DIG_TEST_PATTERN'; + mmDIG4_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG4_DIG_RANDOM_PATTERN_SEED'; + mmDIG4_DIG_FIFO_STATUS :Result:='mmDIG4_DIG_FIFO_STATUS'; + mmDIG4_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG4_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG4_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG4_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG4_HDMI_CONTROL :Result:='mmDIG4_HDMI_CONTROL'; + mmDIG4_HDMI_STATUS :Result:='mmDIG4_HDMI_STATUS'; + mmDIG4_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG4_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG4_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG4_HDMI_ACR_PACKET_CONTROL'; + mmDIG4_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG4_HDMI_VBI_PACKET_CONTROL'; + mmDIG4_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG4_HDMI_INFOFRAME_CONTROL0'; + mmDIG4_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG4_HDMI_INFOFRAME_CONTROL1'; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG4_HDMI_GC :Result:='mmDIG4_HDMI_GC'; + mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG4_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG4_AFMT_ISRC1_0 :Result:='mmDIG4_AFMT_ISRC1_0'; + mmDIG4_AFMT_ISRC1_1 :Result:='mmDIG4_AFMT_ISRC1_1'; + mmDIG4_AFMT_ISRC1_2 :Result:='mmDIG4_AFMT_ISRC1_2'; + mmDIG4_AFMT_ISRC1_3 :Result:='mmDIG4_AFMT_ISRC1_3'; + mmDIG4_AFMT_ISRC1_4 :Result:='mmDIG4_AFMT_ISRC1_4'; + mmDIG4_AFMT_ISRC2_0 :Result:='mmDIG4_AFMT_ISRC2_0'; + mmDIG4_AFMT_ISRC2_1 :Result:='mmDIG4_AFMT_ISRC2_1'; + mmDIG4_AFMT_ISRC2_2 :Result:='mmDIG4_AFMT_ISRC2_2'; + mmDIG4_AFMT_ISRC2_3 :Result:='mmDIG4_AFMT_ISRC2_3'; + mmDIG4_AFMT_AVI_INFO0 :Result:='mmDIG4_AFMT_AVI_INFO0'; + mmDIG4_AFMT_AVI_INFO1 :Result:='mmDIG4_AFMT_AVI_INFO1'; + mmDIG4_AFMT_AVI_INFO2 :Result:='mmDIG4_AFMT_AVI_INFO2'; + mmDIG4_AFMT_AVI_INFO3 :Result:='mmDIG4_AFMT_AVI_INFO3'; + mmDIG4_AFMT_MPEG_INFO0 :Result:='mmDIG4_AFMT_MPEG_INFO0'; + mmDIG4_AFMT_MPEG_INFO1 :Result:='mmDIG4_AFMT_MPEG_INFO1'; + mmDIG4_AFMT_GENERIC_HDR :Result:='mmDIG4_AFMT_GENERIC_HDR'; + mmDIG4_AFMT_GENERIC_0 :Result:='mmDIG4_AFMT_GENERIC_0'; + mmDIG4_AFMT_GENERIC_1 :Result:='mmDIG4_AFMT_GENERIC_1'; + mmDIG4_AFMT_GENERIC_2 :Result:='mmDIG4_AFMT_GENERIC_2'; + mmDIG4_AFMT_GENERIC_3 :Result:='mmDIG4_AFMT_GENERIC_3'; + mmDIG4_AFMT_GENERIC_4 :Result:='mmDIG4_AFMT_GENERIC_4'; + mmDIG4_AFMT_GENERIC_5 :Result:='mmDIG4_AFMT_GENERIC_5'; + mmDIG4_AFMT_GENERIC_6 :Result:='mmDIG4_AFMT_GENERIC_6'; + mmDIG4_AFMT_GENERIC_7 :Result:='mmDIG4_AFMT_GENERIC_7'; + mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG4_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG4_HDMI_ACR_32_0 :Result:='mmDIG4_HDMI_ACR_32_0'; + mmDIG4_HDMI_ACR_32_1 :Result:='mmDIG4_HDMI_ACR_32_1'; + mmDIG4_HDMI_ACR_44_0 :Result:='mmDIG4_HDMI_ACR_44_0'; + mmDIG4_HDMI_ACR_44_1 :Result:='mmDIG4_HDMI_ACR_44_1'; + mmDIG4_HDMI_ACR_48_0 :Result:='mmDIG4_HDMI_ACR_48_0'; + mmDIG4_HDMI_ACR_48_1 :Result:='mmDIG4_HDMI_ACR_48_1'; + mmDIG4_HDMI_ACR_STATUS_0 :Result:='mmDIG4_HDMI_ACR_STATUS_0'; + mmDIG4_HDMI_ACR_STATUS_1 :Result:='mmDIG4_HDMI_ACR_STATUS_1'; + mmDIG4_AFMT_AUDIO_INFO0 :Result:='mmDIG4_AFMT_AUDIO_INFO0'; + mmDIG4_AFMT_AUDIO_INFO1 :Result:='mmDIG4_AFMT_AUDIO_INFO1'; + mmDIG4_AFMT_60958_0 :Result:='mmDIG4_AFMT_60958_0'; + mmDIG4_AFMT_60958_1 :Result:='mmDIG4_AFMT_60958_1'; + mmDIG4_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG4_AFMT_AUDIO_CRC_CONTROL'; + mmDIG4_AFMT_RAMP_CONTROL0 :Result:='mmDIG4_AFMT_RAMP_CONTROL0'; + mmDIG4_AFMT_RAMP_CONTROL1 :Result:='mmDIG4_AFMT_RAMP_CONTROL1'; + mmDIG4_AFMT_RAMP_CONTROL2 :Result:='mmDIG4_AFMT_RAMP_CONTROL2'; + mmDIG4_AFMT_RAMP_CONTROL3 :Result:='mmDIG4_AFMT_RAMP_CONTROL3'; + mmDIG4_AFMT_60958_2 :Result:='mmDIG4_AFMT_60958_2'; + mmDIG4_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG4_AFMT_AUDIO_CRC_RESULT'; + mmDIG4_AFMT_STATUS :Result:='mmDIG4_AFMT_STATUS'; + mmDIG4_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG4_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG4_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG4_AFMT_VBI_PACKET_CONTROL'; + mmDIG4_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG4_AFMT_INFOFRAME_CONTROL0'; + mmDIG4_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG4_AFMT_AUDIO_SRC_CONTROL'; + mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG4_DIG_BE_CNTL :Result:='mmDIG4_DIG_BE_CNTL'; + mmDIG4_DIG_BE_EN_CNTL :Result:='mmDIG4_DIG_BE_EN_CNTL'; + mmDIG4_TMDS_CNTL :Result:='mmDIG4_TMDS_CNTL'; + mmDIG4_TMDS_CONTROL_CHAR :Result:='mmDIG4_TMDS_CONTROL_CHAR'; + mmDIG4_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG4_TMDS_CONTROL0_FEEDBACK'; + mmDIG4_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG4_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG4_TMDS_DEBUG :Result:='mmDIG4_TMDS_DEBUG'; + mmDIG4_TMDS_CTL_BITS :Result:='mmDIG4_TMDS_CTL_BITS'; + mmDIG4_TMDS_DCBALANCER_CONTROL :Result:='mmDIG4_TMDS_DCBALANCER_CONTROL'; + mmDIG4_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG4_TMDS_CTL0_1_GEN_CNTL'; + mmDIG4_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG4_TMDS_CTL2_3_GEN_CNTL'; + mmDIG4_LVDS_DATA_CNTL :Result:='mmDIG4_LVDS_DATA_CNTL'; + mmDIG4_DIG_LANE_ENABLE :Result:='mmDIG4_DIG_LANE_ENABLE'; + mmDIG4_DIG_TEST_DEBUG_INDEX :Result:='mmDIG4_DIG_TEST_DEBUG_INDEX'; + mmDIG4_DIG_TEST_DEBUG_DATA :Result:='mmDIG4_DIG_TEST_DEBUG_DATA'; + mmDIG4_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG4_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG4_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG4_DIG_FE_TEST_DEBUG_DATA'; + mmDP4_DP_LINK_CNTL :Result:='mmDP4_DP_LINK_CNTL'; + mmDP4_DP_PIXEL_FORMAT :Result:='mmDP4_DP_PIXEL_FORMAT'; + mmDP4_DP_MSA_COLORIMETRY :Result:='mmDP4_DP_MSA_COLORIMETRY'; + mmDP4_DP_CONFIG :Result:='mmDP4_DP_CONFIG'; + mmDP4_DP_VID_STREAM_CNTL :Result:='mmDP4_DP_VID_STREAM_CNTL'; + mmDP4_DP_STEER_FIFO :Result:='mmDP4_DP_STEER_FIFO'; + mmDP4_DP_MSA_MISC :Result:='mmDP4_DP_MSA_MISC'; + mmDP4_DP_VID_TIMING :Result:='mmDP4_DP_VID_TIMING'; + mmDP4_DP_VID_N :Result:='mmDP4_DP_VID_N'; + mmDP4_DP_VID_M :Result:='mmDP4_DP_VID_M'; + mmDP4_DP_LINK_FRAMING_CNTL :Result:='mmDP4_DP_LINK_FRAMING_CNTL'; + mmDP4_DP_HBR2_EYE_PATTERN :Result:='mmDP4_DP_HBR2_EYE_PATTERN'; + mmDP4_DP_VID_MSA_VBID :Result:='mmDP4_DP_VID_MSA_VBID'; + mmDP4_DP_VID_INTERRUPT_CNTL :Result:='mmDP4_DP_VID_INTERRUPT_CNTL'; + mmDP4_DP_DPHY_CNTL :Result:='mmDP4_DP_DPHY_CNTL'; + mmDP4_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP4_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP4_DP_DPHY_SYM0 :Result:='mmDP4_DP_DPHY_SYM0'; + mmDP4_DP_DPHY_SYM1 :Result:='mmDP4_DP_DPHY_SYM1'; + mmDP4_DP_DPHY_SYM2 :Result:='mmDP4_DP_DPHY_SYM2'; + mmDP4_DP_DPHY_8B10B_CNTL :Result:='mmDP4_DP_DPHY_8B10B_CNTL'; + mmDP4_DP_DPHY_PRBS_CNTL :Result:='mmDP4_DP_DPHY_PRBS_CNTL'; + mmDP4_DP_DPHY_CRC_EN :Result:='mmDP4_DP_DPHY_CRC_EN'; + mmDP4_DP_DPHY_CRC_CNTL :Result:='mmDP4_DP_DPHY_CRC_CNTL'; + mmDP4_DP_DPHY_CRC_RESULT :Result:='mmDP4_DP_DPHY_CRC_RESULT'; + mmDP4_DP_DPHY_CRC_MST_CNTL :Result:='mmDP4_DP_DPHY_CRC_MST_CNTL'; + mmDP4_DP_DPHY_CRC_MST_STATUS :Result:='mmDP4_DP_DPHY_CRC_MST_STATUS'; + mmDP4_DP_DPHY_FAST_TRAINING :Result:='mmDP4_DP_DPHY_FAST_TRAINING'; + mmDP4_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP4_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP4_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP4_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP4_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP4_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP4_DP_SEC_CNTL :Result:='mmDP4_DP_SEC_CNTL'; + mmDP4_DP_SEC_CNTL1 :Result:='mmDP4_DP_SEC_CNTL1'; + mmDP4_DP_SEC_FRAMING1 :Result:='mmDP4_DP_SEC_FRAMING1'; + mmDP4_DP_SEC_FRAMING2 :Result:='mmDP4_DP_SEC_FRAMING2'; + mmDP4_DP_SEC_FRAMING3 :Result:='mmDP4_DP_SEC_FRAMING3'; + mmDP4_DP_SEC_FRAMING4 :Result:='mmDP4_DP_SEC_FRAMING4'; + mmDP4_DP_SEC_AUD_N :Result:='mmDP4_DP_SEC_AUD_N'; + mmDP4_DP_SEC_AUD_N_READBACK :Result:='mmDP4_DP_SEC_AUD_N_READBACK'; + mmDP4_DP_SEC_AUD_M :Result:='mmDP4_DP_SEC_AUD_M'; + mmDP4_DP_SEC_AUD_M_READBACK :Result:='mmDP4_DP_SEC_AUD_M_READBACK'; + mmDP4_DP_SEC_TIMESTAMP :Result:='mmDP4_DP_SEC_TIMESTAMP'; + mmDP4_DP_SEC_PACKET_CNTL :Result:='mmDP4_DP_SEC_PACKET_CNTL'; + mmDP4_DP_MSE_RATE_CNTL :Result:='mmDP4_DP_MSE_RATE_CNTL'; + mmDP4_DP_MSE_RATE_UPDATE :Result:='mmDP4_DP_MSE_RATE_UPDATE'; + mmDP4_DP_MSE_SAT0 :Result:='mmDP4_DP_MSE_SAT0'; + mmDP4_DP_MSE_SAT1 :Result:='mmDP4_DP_MSE_SAT1'; + mmDP4_DP_MSE_SAT2 :Result:='mmDP4_DP_MSE_SAT2'; + mmDP4_DP_MSE_SAT_UPDATE :Result:='mmDP4_DP_MSE_SAT_UPDATE'; + mmDP4_DP_MSE_LINK_TIMING :Result:='mmDP4_DP_MSE_LINK_TIMING'; + mmDP4_DP_MSE_MISC_CNTL :Result:='mmDP4_DP_MSE_MISC_CNTL'; + mmDP4_DP_TEST_DEBUG_INDEX :Result:='mmDP4_DP_TEST_DEBUG_INDEX'; + mmDP4_DP_TEST_DEBUG_DATA :Result:='mmDP4_DP_TEST_DEBUG_DATA'; + mmDP4_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP4_DP_FE_TEST_DEBUG_INDEX'; + mmDP4_DP_FE_TEST_DEBUG_DATA :Result:='mmDP4_DP_FE_TEST_DEBUG_DATA'; + mmDIG5_DIG_FE_CNTL :Result:='mmDIG5_DIG_FE_CNTL'; + mmDIG5_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG5_DIG_OUTPUT_CRC_CNTL'; + mmDIG5_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG5_DIG_OUTPUT_CRC_RESULT'; + mmDIG5_DIG_CLOCK_PATTERN :Result:='mmDIG5_DIG_CLOCK_PATTERN'; + mmDIG5_DIG_TEST_PATTERN :Result:='mmDIG5_DIG_TEST_PATTERN'; + mmDIG5_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG5_DIG_RANDOM_PATTERN_SEED'; + mmDIG5_DIG_FIFO_STATUS :Result:='mmDIG5_DIG_FIFO_STATUS'; + mmDIG5_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG5_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG5_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG5_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG5_HDMI_CONTROL :Result:='mmDIG5_HDMI_CONTROL'; + mmDIG5_HDMI_STATUS :Result:='mmDIG5_HDMI_STATUS'; + mmDIG5_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG5_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG5_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG5_HDMI_ACR_PACKET_CONTROL'; + mmDIG5_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG5_HDMI_VBI_PACKET_CONTROL'; + mmDIG5_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG5_HDMI_INFOFRAME_CONTROL0'; + mmDIG5_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG5_HDMI_INFOFRAME_CONTROL1'; + mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG5_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG5_HDMI_GC :Result:='mmDIG5_HDMI_GC'; + mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG5_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG5_AFMT_ISRC1_0 :Result:='mmDIG5_AFMT_ISRC1_0'; + mmDIG5_AFMT_ISRC1_1 :Result:='mmDIG5_AFMT_ISRC1_1'; + mmDIG5_AFMT_ISRC1_2 :Result:='mmDIG5_AFMT_ISRC1_2'; + mmDIG5_AFMT_ISRC1_3 :Result:='mmDIG5_AFMT_ISRC1_3'; + mmDIG5_AFMT_ISRC1_4 :Result:='mmDIG5_AFMT_ISRC1_4'; + mmDIG5_AFMT_ISRC2_0 :Result:='mmDIG5_AFMT_ISRC2_0'; + mmDIG5_AFMT_ISRC2_1 :Result:='mmDIG5_AFMT_ISRC2_1'; + mmDIG5_AFMT_ISRC2_2 :Result:='mmDIG5_AFMT_ISRC2_2'; + mmDIG5_AFMT_ISRC2_3 :Result:='mmDIG5_AFMT_ISRC2_3'; + mmDIG5_AFMT_AVI_INFO0 :Result:='mmDIG5_AFMT_AVI_INFO0'; + mmDIG5_AFMT_AVI_INFO1 :Result:='mmDIG5_AFMT_AVI_INFO1'; + mmDIG5_AFMT_AVI_INFO2 :Result:='mmDIG5_AFMT_AVI_INFO2'; + mmDIG5_AFMT_AVI_INFO3 :Result:='mmDIG5_AFMT_AVI_INFO3'; + mmDIG5_AFMT_MPEG_INFO0 :Result:='mmDIG5_AFMT_MPEG_INFO0'; + mmDIG5_AFMT_MPEG_INFO1 :Result:='mmDIG5_AFMT_MPEG_INFO1'; + mmDIG5_AFMT_GENERIC_HDR :Result:='mmDIG5_AFMT_GENERIC_HDR'; + mmDIG5_AFMT_GENERIC_0 :Result:='mmDIG5_AFMT_GENERIC_0'; + mmDIG5_AFMT_GENERIC_1 :Result:='mmDIG5_AFMT_GENERIC_1'; + mmDIG5_AFMT_GENERIC_2 :Result:='mmDIG5_AFMT_GENERIC_2'; + mmDIG5_AFMT_GENERIC_3 :Result:='mmDIG5_AFMT_GENERIC_3'; + mmDIG5_AFMT_GENERIC_4 :Result:='mmDIG5_AFMT_GENERIC_4'; + mmDIG5_AFMT_GENERIC_5 :Result:='mmDIG5_AFMT_GENERIC_5'; + mmDIG5_AFMT_GENERIC_6 :Result:='mmDIG5_AFMT_GENERIC_6'; + mmDIG5_AFMT_GENERIC_7 :Result:='mmDIG5_AFMT_GENERIC_7'; + mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG5_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG5_HDMI_ACR_32_0 :Result:='mmDIG5_HDMI_ACR_32_0'; + mmDIG5_HDMI_ACR_32_1 :Result:='mmDIG5_HDMI_ACR_32_1'; + mmDIG5_HDMI_ACR_44_0 :Result:='mmDIG5_HDMI_ACR_44_0'; + mmDIG5_HDMI_ACR_44_1 :Result:='mmDIG5_HDMI_ACR_44_1'; + mmDIG5_HDMI_ACR_48_0 :Result:='mmDIG5_HDMI_ACR_48_0'; + mmDIG5_HDMI_ACR_48_1 :Result:='mmDIG5_HDMI_ACR_48_1'; + mmDIG5_HDMI_ACR_STATUS_0 :Result:='mmDIG5_HDMI_ACR_STATUS_0'; + mmDIG5_HDMI_ACR_STATUS_1 :Result:='mmDIG5_HDMI_ACR_STATUS_1'; + mmDIG5_AFMT_AUDIO_INFO0 :Result:='mmDIG5_AFMT_AUDIO_INFO0'; + mmDIG5_AFMT_AUDIO_INFO1 :Result:='mmDIG5_AFMT_AUDIO_INFO1'; + mmDIG5_AFMT_60958_0 :Result:='mmDIG5_AFMT_60958_0'; + mmDIG5_AFMT_60958_1 :Result:='mmDIG5_AFMT_60958_1'; + mmDIG5_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG5_AFMT_AUDIO_CRC_CONTROL'; + mmDIG5_AFMT_RAMP_CONTROL0 :Result:='mmDIG5_AFMT_RAMP_CONTROL0'; + mmDIG5_AFMT_RAMP_CONTROL1 :Result:='mmDIG5_AFMT_RAMP_CONTROL1'; + mmDIG5_AFMT_RAMP_CONTROL2 :Result:='mmDIG5_AFMT_RAMP_CONTROL2'; + mmDIG5_AFMT_RAMP_CONTROL3 :Result:='mmDIG5_AFMT_RAMP_CONTROL3'; + mmDIG5_AFMT_60958_2 :Result:='mmDIG5_AFMT_60958_2'; + mmDIG5_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG5_AFMT_AUDIO_CRC_RESULT'; + mmDIG5_AFMT_STATUS :Result:='mmDIG5_AFMT_STATUS'; + mmDIG5_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG5_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG5_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG5_AFMT_VBI_PACKET_CONTROL'; + mmDIG5_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG5_AFMT_INFOFRAME_CONTROL0'; + mmDIG5_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG5_AFMT_AUDIO_SRC_CONTROL'; + mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG5_DIG_BE_CNTL :Result:='mmDIG5_DIG_BE_CNTL'; + mmDIG5_DIG_BE_EN_CNTL :Result:='mmDIG5_DIG_BE_EN_CNTL'; + mmDIG5_TMDS_CNTL :Result:='mmDIG5_TMDS_CNTL'; + mmDIG5_TMDS_CONTROL_CHAR :Result:='mmDIG5_TMDS_CONTROL_CHAR'; + mmDIG5_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG5_TMDS_CONTROL0_FEEDBACK'; + mmDIG5_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG5_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG5_TMDS_DEBUG :Result:='mmDIG5_TMDS_DEBUG'; + mmDIG5_TMDS_CTL_BITS :Result:='mmDIG5_TMDS_CTL_BITS'; + mmDIG5_TMDS_DCBALANCER_CONTROL :Result:='mmDIG5_TMDS_DCBALANCER_CONTROL'; + mmDIG5_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG5_TMDS_CTL0_1_GEN_CNTL'; + mmDIG5_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG5_TMDS_CTL2_3_GEN_CNTL'; + mmDIG5_LVDS_DATA_CNTL :Result:='mmDIG5_LVDS_DATA_CNTL'; + mmDIG5_DIG_LANE_ENABLE :Result:='mmDIG5_DIG_LANE_ENABLE'; + mmDIG5_DIG_TEST_DEBUG_INDEX :Result:='mmDIG5_DIG_TEST_DEBUG_INDEX'; + mmDIG5_DIG_TEST_DEBUG_DATA :Result:='mmDIG5_DIG_TEST_DEBUG_DATA'; + mmDIG5_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG5_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG5_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG5_DIG_FE_TEST_DEBUG_DATA'; + mmDP5_DP_LINK_CNTL :Result:='mmDP5_DP_LINK_CNTL'; + mmDP5_DP_PIXEL_FORMAT :Result:='mmDP5_DP_PIXEL_FORMAT'; + mmDP5_DP_MSA_COLORIMETRY :Result:='mmDP5_DP_MSA_COLORIMETRY'; + mmDP5_DP_CONFIG :Result:='mmDP5_DP_CONFIG'; + mmDP5_DP_VID_STREAM_CNTL :Result:='mmDP5_DP_VID_STREAM_CNTL'; + mmDP5_DP_STEER_FIFO :Result:='mmDP5_DP_STEER_FIFO'; + mmDP5_DP_MSA_MISC :Result:='mmDP5_DP_MSA_MISC'; + mmDP5_DP_VID_TIMING :Result:='mmDP5_DP_VID_TIMING'; + mmDP5_DP_VID_N :Result:='mmDP5_DP_VID_N'; + mmDP5_DP_VID_M :Result:='mmDP5_DP_VID_M'; + mmDP5_DP_LINK_FRAMING_CNTL :Result:='mmDP5_DP_LINK_FRAMING_CNTL'; + mmDP5_DP_HBR2_EYE_PATTERN :Result:='mmDP5_DP_HBR2_EYE_PATTERN'; + mmDP5_DP_VID_MSA_VBID :Result:='mmDP5_DP_VID_MSA_VBID'; + mmDP5_DP_VID_INTERRUPT_CNTL :Result:='mmDP5_DP_VID_INTERRUPT_CNTL'; + mmDP5_DP_DPHY_CNTL :Result:='mmDP5_DP_DPHY_CNTL'; + mmDP5_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP5_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP5_DP_DPHY_SYM0 :Result:='mmDP5_DP_DPHY_SYM0'; + mmDP5_DP_DPHY_SYM1 :Result:='mmDP5_DP_DPHY_SYM1'; + mmDP5_DP_DPHY_SYM2 :Result:='mmDP5_DP_DPHY_SYM2'; + mmDP5_DP_DPHY_8B10B_CNTL :Result:='mmDP5_DP_DPHY_8B10B_CNTL'; + mmDP5_DP_DPHY_PRBS_CNTL :Result:='mmDP5_DP_DPHY_PRBS_CNTL'; + mmDP5_DP_DPHY_CRC_EN :Result:='mmDP5_DP_DPHY_CRC_EN'; + mmDP5_DP_DPHY_CRC_CNTL :Result:='mmDP5_DP_DPHY_CRC_CNTL'; + mmDP5_DP_DPHY_CRC_RESULT :Result:='mmDP5_DP_DPHY_CRC_RESULT'; + mmDP5_DP_DPHY_CRC_MST_CNTL :Result:='mmDP5_DP_DPHY_CRC_MST_CNTL'; + mmDP5_DP_DPHY_CRC_MST_STATUS :Result:='mmDP5_DP_DPHY_CRC_MST_STATUS'; + mmDP5_DP_DPHY_FAST_TRAINING :Result:='mmDP5_DP_DPHY_FAST_TRAINING'; + mmDP5_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP5_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP5_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP5_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP5_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP5_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP5_DP_SEC_CNTL :Result:='mmDP5_DP_SEC_CNTL'; + mmDP5_DP_SEC_CNTL1 :Result:='mmDP5_DP_SEC_CNTL1'; + mmDP5_DP_SEC_FRAMING1 :Result:='mmDP5_DP_SEC_FRAMING1'; + mmDP5_DP_SEC_FRAMING2 :Result:='mmDP5_DP_SEC_FRAMING2'; + mmDP5_DP_SEC_FRAMING3 :Result:='mmDP5_DP_SEC_FRAMING3'; + mmDP5_DP_SEC_FRAMING4 :Result:='mmDP5_DP_SEC_FRAMING4'; + mmDP5_DP_SEC_AUD_N :Result:='mmDP5_DP_SEC_AUD_N'; + mmDP5_DP_SEC_AUD_N_READBACK :Result:='mmDP5_DP_SEC_AUD_N_READBACK'; + mmDP5_DP_SEC_AUD_M :Result:='mmDP5_DP_SEC_AUD_M'; + mmDP5_DP_SEC_AUD_M_READBACK :Result:='mmDP5_DP_SEC_AUD_M_READBACK'; + mmDP5_DP_SEC_TIMESTAMP :Result:='mmDP5_DP_SEC_TIMESTAMP'; + mmDP5_DP_SEC_PACKET_CNTL :Result:='mmDP5_DP_SEC_PACKET_CNTL'; + mmDP5_DP_MSE_RATE_CNTL :Result:='mmDP5_DP_MSE_RATE_CNTL'; + mmDP5_DP_MSE_RATE_UPDATE :Result:='mmDP5_DP_MSE_RATE_UPDATE'; + mmDP5_DP_MSE_SAT0 :Result:='mmDP5_DP_MSE_SAT0'; + mmDP5_DP_MSE_SAT1 :Result:='mmDP5_DP_MSE_SAT1'; + mmDP5_DP_MSE_SAT2 :Result:='mmDP5_DP_MSE_SAT2'; + mmDP5_DP_MSE_SAT_UPDATE :Result:='mmDP5_DP_MSE_SAT_UPDATE'; + mmDP5_DP_MSE_LINK_TIMING :Result:='mmDP5_DP_MSE_LINK_TIMING'; + mmDP5_DP_MSE_MISC_CNTL :Result:='mmDP5_DP_MSE_MISC_CNTL'; + mmDP5_DP_TEST_DEBUG_INDEX :Result:='mmDP5_DP_TEST_DEBUG_INDEX'; + mmDP5_DP_TEST_DEBUG_DATA :Result:='mmDP5_DP_TEST_DEBUG_DATA'; + mmDP5_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP5_DP_FE_TEST_DEBUG_INDEX'; + mmDP5_DP_FE_TEST_DEBUG_DATA :Result:='mmDP5_DP_FE_TEST_DEBUG_DATA'; + mmDIG6_DIG_FE_CNTL :Result:='mmDIG6_DIG_FE_CNTL'; + mmDIG6_DIG_OUTPUT_CRC_CNTL :Result:='mmDIG6_DIG_OUTPUT_CRC_CNTL'; + mmDIG6_DIG_OUTPUT_CRC_RESULT :Result:='mmDIG6_DIG_OUTPUT_CRC_RESULT'; + mmDIG6_DIG_CLOCK_PATTERN :Result:='mmDIG6_DIG_CLOCK_PATTERN'; + mmDIG6_DIG_TEST_PATTERN :Result:='mmDIG6_DIG_TEST_PATTERN'; + mmDIG6_DIG_RANDOM_PATTERN_SEED :Result:='mmDIG6_DIG_RANDOM_PATTERN_SEED'; + mmDIG6_DIG_FIFO_STATUS :Result:='mmDIG6_DIG_FIFO_STATUS'; + mmDIG6_DIG_DISPCLK_SWITCH_CNTL :Result:='mmDIG6_DIG_DISPCLK_SWITCH_CNTL'; + mmDIG6_DIG_DISPCLK_SWITCH_STATUS :Result:='mmDIG6_DIG_DISPCLK_SWITCH_STATUS'; + mmDIG6_HDMI_CONTROL :Result:='mmDIG6_HDMI_CONTROL'; + mmDIG6_HDMI_STATUS :Result:='mmDIG6_HDMI_STATUS'; + mmDIG6_HDMI_AUDIO_PACKET_CONTROL :Result:='mmDIG6_HDMI_AUDIO_PACKET_CONTROL'; + mmDIG6_HDMI_ACR_PACKET_CONTROL :Result:='mmDIG6_HDMI_ACR_PACKET_CONTROL'; + mmDIG6_HDMI_VBI_PACKET_CONTROL :Result:='mmDIG6_HDMI_VBI_PACKET_CONTROL'; + mmDIG6_HDMI_INFOFRAME_CONTROL0 :Result:='mmDIG6_HDMI_INFOFRAME_CONTROL0'; + mmDIG6_HDMI_INFOFRAME_CONTROL1 :Result:='mmDIG6_HDMI_INFOFRAME_CONTROL1'; + mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 :Result:='mmDIG6_HDMI_GENERIC_PACKET_CONTROL0'; + mmDIG6_HDMI_GC :Result:='mmDIG6_HDMI_GC'; + mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 :Result:='mmDIG6_AFMT_AUDIO_PACKET_CONTROL2'; + mmDIG6_AFMT_ISRC1_0 :Result:='mmDIG6_AFMT_ISRC1_0'; + mmDIG6_AFMT_ISRC1_1 :Result:='mmDIG6_AFMT_ISRC1_1'; + mmDIG6_AFMT_ISRC1_2 :Result:='mmDIG6_AFMT_ISRC1_2'; + mmDIG6_AFMT_ISRC1_3 :Result:='mmDIG6_AFMT_ISRC1_3'; + mmDIG6_AFMT_ISRC1_4 :Result:='mmDIG6_AFMT_ISRC1_4'; + mmDIG6_AFMT_ISRC2_0 :Result:='mmDIG6_AFMT_ISRC2_0'; + mmDIG6_AFMT_ISRC2_1 :Result:='mmDIG6_AFMT_ISRC2_1'; + mmDIG6_AFMT_ISRC2_2 :Result:='mmDIG6_AFMT_ISRC2_2'; + mmDIG6_AFMT_ISRC2_3 :Result:='mmDIG6_AFMT_ISRC2_3'; + mmDIG6_AFMT_AVI_INFO0 :Result:='mmDIG6_AFMT_AVI_INFO0'; + mmDIG6_AFMT_AVI_INFO1 :Result:='mmDIG6_AFMT_AVI_INFO1'; + mmDIG6_AFMT_AVI_INFO2 :Result:='mmDIG6_AFMT_AVI_INFO2'; + mmDIG6_AFMT_AVI_INFO3 :Result:='mmDIG6_AFMT_AVI_INFO3'; + mmDIG6_AFMT_MPEG_INFO0 :Result:='mmDIG6_AFMT_MPEG_INFO0'; + mmDIG6_AFMT_MPEG_INFO1 :Result:='mmDIG6_AFMT_MPEG_INFO1'; + mmDIG6_AFMT_GENERIC_HDR :Result:='mmDIG6_AFMT_GENERIC_HDR'; + mmDIG6_AFMT_GENERIC_0 :Result:='mmDIG6_AFMT_GENERIC_0'; + mmDIG6_AFMT_GENERIC_1 :Result:='mmDIG6_AFMT_GENERIC_1'; + mmDIG6_AFMT_GENERIC_2 :Result:='mmDIG6_AFMT_GENERIC_2'; + mmDIG6_AFMT_GENERIC_3 :Result:='mmDIG6_AFMT_GENERIC_3'; + mmDIG6_AFMT_GENERIC_4 :Result:='mmDIG6_AFMT_GENERIC_4'; + mmDIG6_AFMT_GENERIC_5 :Result:='mmDIG6_AFMT_GENERIC_5'; + mmDIG6_AFMT_GENERIC_6 :Result:='mmDIG6_AFMT_GENERIC_6'; + mmDIG6_AFMT_GENERIC_7 :Result:='mmDIG6_AFMT_GENERIC_7'; + mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 :Result:='mmDIG6_HDMI_GENERIC_PACKET_CONTROL1'; + mmDIG6_HDMI_ACR_32_0 :Result:='mmDIG6_HDMI_ACR_32_0'; + mmDIG6_HDMI_ACR_32_1 :Result:='mmDIG6_HDMI_ACR_32_1'; + mmDIG6_HDMI_ACR_44_0 :Result:='mmDIG6_HDMI_ACR_44_0'; + mmDIG6_HDMI_ACR_44_1 :Result:='mmDIG6_HDMI_ACR_44_1'; + mmDIG6_HDMI_ACR_48_0 :Result:='mmDIG6_HDMI_ACR_48_0'; + mmDIG6_HDMI_ACR_48_1 :Result:='mmDIG6_HDMI_ACR_48_1'; + mmDIG6_HDMI_ACR_STATUS_0 :Result:='mmDIG6_HDMI_ACR_STATUS_0'; + mmDIG6_HDMI_ACR_STATUS_1 :Result:='mmDIG6_HDMI_ACR_STATUS_1'; + mmDIG6_AFMT_AUDIO_INFO0 :Result:='mmDIG6_AFMT_AUDIO_INFO0'; + mmDIG6_AFMT_AUDIO_INFO1 :Result:='mmDIG6_AFMT_AUDIO_INFO1'; + mmDIG6_AFMT_60958_0 :Result:='mmDIG6_AFMT_60958_0'; + mmDIG6_AFMT_60958_1 :Result:='mmDIG6_AFMT_60958_1'; + mmDIG6_AFMT_AUDIO_CRC_CONTROL :Result:='mmDIG6_AFMT_AUDIO_CRC_CONTROL'; + mmDIG6_AFMT_RAMP_CONTROL0 :Result:='mmDIG6_AFMT_RAMP_CONTROL0'; + mmDIG6_AFMT_RAMP_CONTROL1 :Result:='mmDIG6_AFMT_RAMP_CONTROL1'; + mmDIG6_AFMT_RAMP_CONTROL2 :Result:='mmDIG6_AFMT_RAMP_CONTROL2'; + mmDIG6_AFMT_RAMP_CONTROL3 :Result:='mmDIG6_AFMT_RAMP_CONTROL3'; + mmDIG6_AFMT_60958_2 :Result:='mmDIG6_AFMT_60958_2'; + mmDIG6_AFMT_AUDIO_CRC_RESULT :Result:='mmDIG6_AFMT_AUDIO_CRC_RESULT'; + mmDIG6_AFMT_STATUS :Result:='mmDIG6_AFMT_STATUS'; + mmDIG6_AFMT_AUDIO_PACKET_CONTROL :Result:='mmDIG6_AFMT_AUDIO_PACKET_CONTROL'; + mmDIG6_AFMT_VBI_PACKET_CONTROL :Result:='mmDIG6_AFMT_VBI_PACKET_CONTROL'; + mmDIG6_AFMT_INFOFRAME_CONTROL0 :Result:='mmDIG6_AFMT_INFOFRAME_CONTROL0'; + mmDIG6_AFMT_AUDIO_SRC_CONTROL :Result:='mmDIG6_AFMT_AUDIO_SRC_CONTROL'; + mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL :Result:='mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL'; + mmDIG6_DIG_BE_CNTL :Result:='mmDIG6_DIG_BE_CNTL'; + mmDIG6_DIG_BE_EN_CNTL :Result:='mmDIG6_DIG_BE_EN_CNTL'; + mmDIG6_TMDS_CNTL :Result:='mmDIG6_TMDS_CNTL'; + mmDIG6_TMDS_CONTROL_CHAR :Result:='mmDIG6_TMDS_CONTROL_CHAR'; + mmDIG6_TMDS_CONTROL0_FEEDBACK :Result:='mmDIG6_TMDS_CONTROL0_FEEDBACK'; + mmDIG6_TMDS_STEREOSYNC_CTL_SEL :Result:='mmDIG6_TMDS_STEREOSYNC_CTL_SEL'; + mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 :Result:='mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1'; + mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 :Result:='mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3'; + mmDIG6_TMDS_DEBUG :Result:='mmDIG6_TMDS_DEBUG'; + mmDIG6_TMDS_CTL_BITS :Result:='mmDIG6_TMDS_CTL_BITS'; + mmDIG6_TMDS_DCBALANCER_CONTROL :Result:='mmDIG6_TMDS_DCBALANCER_CONTROL'; + mmDIG6_TMDS_CTL0_1_GEN_CNTL :Result:='mmDIG6_TMDS_CTL0_1_GEN_CNTL'; + mmDIG6_TMDS_CTL2_3_GEN_CNTL :Result:='mmDIG6_TMDS_CTL2_3_GEN_CNTL'; + mmDIG6_LVDS_DATA_CNTL :Result:='mmDIG6_LVDS_DATA_CNTL'; + mmDIG6_DIG_LANE_ENABLE :Result:='mmDIG6_DIG_LANE_ENABLE'; + mmDIG6_DIG_TEST_DEBUG_INDEX :Result:='mmDIG6_DIG_TEST_DEBUG_INDEX'; + mmDIG6_DIG_TEST_DEBUG_DATA :Result:='mmDIG6_DIG_TEST_DEBUG_DATA'; + mmDIG6_DIG_FE_TEST_DEBUG_INDEX :Result:='mmDIG6_DIG_FE_TEST_DEBUG_INDEX'; + mmDIG6_DIG_FE_TEST_DEBUG_DATA :Result:='mmDIG6_DIG_FE_TEST_DEBUG_DATA'; + mmDP6_DP_LINK_CNTL :Result:='mmDP6_DP_LINK_CNTL'; + mmDP6_DP_PIXEL_FORMAT :Result:='mmDP6_DP_PIXEL_FORMAT'; + mmDP6_DP_MSA_COLORIMETRY :Result:='mmDP6_DP_MSA_COLORIMETRY'; + mmDP6_DP_CONFIG :Result:='mmDP6_DP_CONFIG'; + mmDP6_DP_VID_STREAM_CNTL :Result:='mmDP6_DP_VID_STREAM_CNTL'; + mmDP6_DP_STEER_FIFO :Result:='mmDP6_DP_STEER_FIFO'; + mmDP6_DP_MSA_MISC :Result:='mmDP6_DP_MSA_MISC'; + mmDP6_DP_VID_TIMING :Result:='mmDP6_DP_VID_TIMING'; + mmDP6_DP_VID_N :Result:='mmDP6_DP_VID_N'; + mmDP6_DP_VID_M :Result:='mmDP6_DP_VID_M'; + mmDP6_DP_LINK_FRAMING_CNTL :Result:='mmDP6_DP_LINK_FRAMING_CNTL'; + mmDP6_DP_HBR2_EYE_PATTERN :Result:='mmDP6_DP_HBR2_EYE_PATTERN'; + mmDP6_DP_VID_MSA_VBID :Result:='mmDP6_DP_VID_MSA_VBID'; + mmDP6_DP_VID_INTERRUPT_CNTL :Result:='mmDP6_DP_VID_INTERRUPT_CNTL'; + mmDP6_DP_DPHY_CNTL :Result:='mmDP6_DP_DPHY_CNTL'; + mmDP6_DP_DPHY_TRAINING_PATTERN_SEL :Result:='mmDP6_DP_DPHY_TRAINING_PATTERN_SEL'; + mmDP6_DP_DPHY_SYM0 :Result:='mmDP6_DP_DPHY_SYM0'; + mmDP6_DP_DPHY_SYM1 :Result:='mmDP6_DP_DPHY_SYM1'; + mmDP6_DP_DPHY_SYM2 :Result:='mmDP6_DP_DPHY_SYM2'; + mmDP6_DP_DPHY_8B10B_CNTL :Result:='mmDP6_DP_DPHY_8B10B_CNTL'; + mmDP6_DP_DPHY_PRBS_CNTL :Result:='mmDP6_DP_DPHY_PRBS_CNTL'; + mmDP6_DP_DPHY_CRC_EN :Result:='mmDP6_DP_DPHY_CRC_EN'; + mmDP6_DP_DPHY_CRC_CNTL :Result:='mmDP6_DP_DPHY_CRC_CNTL'; + mmDP6_DP_DPHY_CRC_RESULT :Result:='mmDP6_DP_DPHY_CRC_RESULT'; + mmDP6_DP_DPHY_CRC_MST_CNTL :Result:='mmDP6_DP_DPHY_CRC_MST_CNTL'; + mmDP6_DP_DPHY_CRC_MST_STATUS :Result:='mmDP6_DP_DPHY_CRC_MST_STATUS'; + mmDP6_DP_DPHY_FAST_TRAINING :Result:='mmDP6_DP_DPHY_FAST_TRAINING'; + mmDP6_DP_DPHY_FAST_TRAINING_STATUS :Result:='mmDP6_DP_DPHY_FAST_TRAINING_STATUS'; + mmDP6_DP_MSA_V_TIMING_OVERRIDE1 :Result:='mmDP6_DP_MSA_V_TIMING_OVERRIDE1'; + mmDP6_DP_MSA_V_TIMING_OVERRIDE2 :Result:='mmDP6_DP_MSA_V_TIMING_OVERRIDE2'; + mmDP6_DP_SEC_CNTL :Result:='mmDP6_DP_SEC_CNTL'; + mmDP6_DP_SEC_CNTL1 :Result:='mmDP6_DP_SEC_CNTL1'; + mmDP6_DP_SEC_FRAMING1 :Result:='mmDP6_DP_SEC_FRAMING1'; + mmDP6_DP_SEC_FRAMING2 :Result:='mmDP6_DP_SEC_FRAMING2'; + mmDP6_DP_SEC_FRAMING3 :Result:='mmDP6_DP_SEC_FRAMING3'; + mmDP6_DP_SEC_FRAMING4 :Result:='mmDP6_DP_SEC_FRAMING4'; + mmDP6_DP_SEC_AUD_N :Result:='mmDP6_DP_SEC_AUD_N'; + mmDP6_DP_SEC_AUD_N_READBACK :Result:='mmDP6_DP_SEC_AUD_N_READBACK'; + mmDP6_DP_SEC_AUD_M :Result:='mmDP6_DP_SEC_AUD_M'; + mmDP6_DP_SEC_AUD_M_READBACK :Result:='mmDP6_DP_SEC_AUD_M_READBACK'; + mmDP6_DP_SEC_TIMESTAMP :Result:='mmDP6_DP_SEC_TIMESTAMP'; + mmDP6_DP_SEC_PACKET_CNTL :Result:='mmDP6_DP_SEC_PACKET_CNTL'; + mmDP6_DP_MSE_RATE_CNTL :Result:='mmDP6_DP_MSE_RATE_CNTL'; + mmDP6_DP_MSE_RATE_UPDATE :Result:='mmDP6_DP_MSE_RATE_UPDATE'; + mmDP6_DP_MSE_SAT0 :Result:='mmDP6_DP_MSE_SAT0'; + mmDP6_DP_MSE_SAT1 :Result:='mmDP6_DP_MSE_SAT1'; + mmDP6_DP_MSE_SAT2 :Result:='mmDP6_DP_MSE_SAT2'; + mmDP6_DP_MSE_SAT_UPDATE :Result:='mmDP6_DP_MSE_SAT_UPDATE'; + mmDP6_DP_MSE_LINK_TIMING :Result:='mmDP6_DP_MSE_LINK_TIMING'; + mmDP6_DP_MSE_MISC_CNTL :Result:='mmDP6_DP_MSE_MISC_CNTL'; + mmDP6_DP_TEST_DEBUG_INDEX :Result:='mmDP6_DP_TEST_DEBUG_INDEX'; + mmDP6_DP_TEST_DEBUG_DATA :Result:='mmDP6_DP_TEST_DEBUG_DATA'; + mmDP6_DP_FE_TEST_DEBUG_INDEX :Result:='mmDP6_DP_FE_TEST_DEBUG_INDEX'; + mmDP6_DP_FE_TEST_DEBUG_DATA :Result:='mmDP6_DP_FE_TEST_DEBUG_DATA'; + mmDC_PERFMON10_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON10_PERFCOUNTER_CNTL'; + mmDC_PERFMON10_PERFCOUNTER_STATE :Result:='mmDC_PERFMON10_PERFCOUNTER_STATE'; + mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON10_PERFMON_CNTL :Result:='mmDC_PERFMON10_PERFMON_CNTL'; + mmDC_PERFMON10_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON10_PERFMON_CVALUE_LOW'; + mmDC_PERFMON10_PERFMON_HI :Result:='mmDC_PERFMON10_PERFMON_HI'; + mmDC_PERFMON10_PERFMON_LOW :Result:='mmDC_PERFMON10_PERFMON_LOW'; + mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON10_PERFMON_CNTL2 :Result:='mmDC_PERFMON10_PERFMON_CNTL2'; + mmAZF0STREAM8_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM8_AZALIA_STREAM_INDEX'; + mmAZF0STREAM8_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM8_AZALIA_STREAM_DATA'; + mmAZF0STREAM9_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM9_AZALIA_STREAM_INDEX'; + mmAZF0STREAM9_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM9_AZALIA_STREAM_DATA'; + mmAZF0STREAM10_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM10_AZALIA_STREAM_INDEX'; + mmAZF0STREAM10_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM10_AZALIA_STREAM_DATA'; + mmAZF0STREAM11_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM11_AZALIA_STREAM_INDEX'; + mmAZF0STREAM11_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM11_AZALIA_STREAM_DATA'; + mmAZF0STREAM12_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM12_AZALIA_STREAM_INDEX'; + mmAZF0STREAM12_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM12_AZALIA_STREAM_DATA'; + mmAZF0STREAM13_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM13_AZALIA_STREAM_INDEX'; + mmAZF0STREAM13_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM13_AZALIA_STREAM_DATA'; + mmAZF0STREAM14_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM14_AZALIA_STREAM_INDEX'; + mmAZF0STREAM14_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM14_AZALIA_STREAM_DATA'; + mmAZF0STREAM15_AZALIA_STREAM_INDEX :Result:='mmAZF0STREAM15_AZALIA_STREAM_INDEX'; + mmAZF0STREAM15_AZALIA_STREAM_DATA :Result:='mmAZF0STREAM15_AZALIA_STREAM_DATA'; + mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX :Result:='mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX:Result:='mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX'; + mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA :Result:='mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA'; + mmDCRX_PHY_MACRO_CNTL_RESERVED0 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED0'; + mmDCRX_PHY_MACRO_CNTL_RESERVED1 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED1'; + mmDCRX_PHY_MACRO_CNTL_RESERVED2 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED2'; + mmDCRX_PHY_MACRO_CNTL_RESERVED3 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED3'; + mmDCRX_PHY_MACRO_CNTL_RESERVED4 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED4'; + mmDCRX_PHY_MACRO_CNTL_RESERVED5 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED5'; + mmDCRX_PHY_MACRO_CNTL_RESERVED6 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED6'; + mmDCRX_PHY_MACRO_CNTL_RESERVED7 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED7'; + mmDCRX_PHY_MACRO_CNTL_RESERVED8 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED8'; + mmDCRX_PHY_MACRO_CNTL_RESERVED9 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED9'; + mmDCRX_PHY_MACRO_CNTL_RESERVED10 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED10'; + mmDCRX_PHY_MACRO_CNTL_RESERVED11 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED11'; + mmDCRX_PHY_MACRO_CNTL_RESERVED12 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED12'; + mmDCRX_PHY_MACRO_CNTL_RESERVED13 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED13'; + mmDCRX_PHY_MACRO_CNTL_RESERVED14 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED14'; + mmDCRX_PHY_MACRO_CNTL_RESERVED15 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED15'; + mmDCRX_PHY_MACRO_CNTL_RESERVED16 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED16'; + mmDCRX_PHY_MACRO_CNTL_RESERVED17 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED17'; + mmDCRX_PHY_MACRO_CNTL_RESERVED18 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED18'; + mmDCRX_PHY_MACRO_CNTL_RESERVED19 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED19'; + mmDCRX_PHY_MACRO_CNTL_RESERVED20 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED20'; + mmDCRX_PHY_MACRO_CNTL_RESERVED21 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED21'; + mmDCRX_PHY_MACRO_CNTL_RESERVED22 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED22'; + mmDCRX_PHY_MACRO_CNTL_RESERVED23 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED23'; + mmDCRX_PHY_MACRO_CNTL_RESERVED24 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED24'; + mmDCRX_PHY_MACRO_CNTL_RESERVED25 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED25'; + mmDCRX_PHY_MACRO_CNTL_RESERVED26 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED26'; + mmDCRX_PHY_MACRO_CNTL_RESERVED27 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED27'; + mmDCRX_PHY_MACRO_CNTL_RESERVED28 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED28'; + mmDCRX_PHY_MACRO_CNTL_RESERVED29 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED29'; + mmDCRX_PHY_MACRO_CNTL_RESERVED30 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED30'; + mmDCRX_PHY_MACRO_CNTL_RESERVED31 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED31'; + mmDCRX_PHY_MACRO_CNTL_RESERVED32 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED32'; + mmDCRX_PHY_MACRO_CNTL_RESERVED33 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED33'; + mmDCRX_PHY_MACRO_CNTL_RESERVED34 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED34'; + mmDCRX_PHY_MACRO_CNTL_RESERVED35 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED35'; + mmDCRX_PHY_MACRO_CNTL_RESERVED36 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED36'; + mmDCRX_PHY_MACRO_CNTL_RESERVED37 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED37'; + mmDCRX_PHY_MACRO_CNTL_RESERVED38 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED38'; + mmDCRX_PHY_MACRO_CNTL_RESERVED39 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED39'; + mmDCRX_PHY_MACRO_CNTL_RESERVED40 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED40'; + mmDCRX_PHY_MACRO_CNTL_RESERVED41 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED41'; + mmDCRX_PHY_MACRO_CNTL_RESERVED42 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED42'; + mmDCRX_PHY_MACRO_CNTL_RESERVED43 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED43'; + mmDCRX_PHY_MACRO_CNTL_RESERVED44 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED44'; + mmDCRX_PHY_MACRO_CNTL_RESERVED45 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED45'; + mmDCRX_PHY_MACRO_CNTL_RESERVED46 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED46'; + mmDCRX_PHY_MACRO_CNTL_RESERVED47 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED47'; + mmDCRX_PHY_MACRO_CNTL_RESERVED48 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED48'; + mmDCRX_PHY_MACRO_CNTL_RESERVED49 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED49'; + mmDCRX_PHY_MACRO_CNTL_RESERVED50 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED50'; + mmDCRX_PHY_MACRO_CNTL_RESERVED51 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED51'; + mmDCRX_PHY_MACRO_CNTL_RESERVED52 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED52'; + mmDCRX_PHY_MACRO_CNTL_RESERVED53 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED53'; + mmDCRX_PHY_MACRO_CNTL_RESERVED54 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED54'; + mmDCRX_PHY_MACRO_CNTL_RESERVED55 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED55'; + mmDCRX_PHY_MACRO_CNTL_RESERVED56 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED56'; + mmDCRX_PHY_MACRO_CNTL_RESERVED57 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED57'; + mmDCRX_PHY_MACRO_CNTL_RESERVED58 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED58'; + mmDCRX_PHY_MACRO_CNTL_RESERVED59 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED59'; + mmDCRX_PHY_MACRO_CNTL_RESERVED60 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED60'; + mmDCRX_PHY_MACRO_CNTL_RESERVED61 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED61'; + mmDCRX_PHY_MACRO_CNTL_RESERVED62 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED62'; + mmDCRX_PHY_MACRO_CNTL_RESERVED63 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED63'; + mmDCRX_PHY_MACRO_CNTL_RESERVED64 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED64'; + mmDCRX_PHY_MACRO_CNTL_RESERVED65 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED65'; + mmDCRX_PHY_MACRO_CNTL_RESERVED66 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED66'; + mmDCRX_PHY_MACRO_CNTL_RESERVED67 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED67'; + mmDCRX_PHY_MACRO_CNTL_RESERVED68 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED68'; + mmDCRX_PHY_MACRO_CNTL_RESERVED69 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED69'; + mmDCRX_PHY_MACRO_CNTL_RESERVED70 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED70'; + mmDCRX_PHY_MACRO_CNTL_RESERVED71 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED71'; + mmDCRX_PHY_MACRO_CNTL_RESERVED72 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED72'; + mmDCRX_PHY_MACRO_CNTL_RESERVED73 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED73'; + mmDCRX_PHY_MACRO_CNTL_RESERVED74 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED74'; + mmDCRX_PHY_MACRO_CNTL_RESERVED75 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED75'; + mmDCRX_PHY_MACRO_CNTL_RESERVED76 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED76'; + mmDCRX_PHY_MACRO_CNTL_RESERVED77 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED77'; + mmDCRX_PHY_MACRO_CNTL_RESERVED78 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED78'; + mmDCRX_PHY_MACRO_CNTL_RESERVED79 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED79'; + mmDCRX_PHY_MACRO_CNTL_RESERVED80 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED80'; + mmDCRX_PHY_MACRO_CNTL_RESERVED81 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED81'; + mmDCRX_PHY_MACRO_CNTL_RESERVED82 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED82'; + mmDCRX_PHY_MACRO_CNTL_RESERVED83 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED83'; + mmDCRX_PHY_MACRO_CNTL_RESERVED84 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED84'; + mmDCRX_PHY_MACRO_CNTL_RESERVED85 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED85'; + mmDCRX_PHY_MACRO_CNTL_RESERVED86 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED86'; + mmDCRX_PHY_MACRO_CNTL_RESERVED87 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED87'; + mmDCRX_PHY_MACRO_CNTL_RESERVED88 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED88'; + mmDCRX_PHY_MACRO_CNTL_RESERVED89 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED89'; + mmDCRX_PHY_MACRO_CNTL_RESERVED90 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED90'; + mmDCRX_PHY_MACRO_CNTL_RESERVED91 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED91'; + mmDCRX_PHY_MACRO_CNTL_RESERVED92 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED92'; + mmDCRX_PHY_MACRO_CNTL_RESERVED93 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED93'; + mmDCRX_PHY_MACRO_CNTL_RESERVED94 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED94'; + mmDCRX_PHY_MACRO_CNTL_RESERVED95 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED95'; + mmDCRX_PHY_MACRO_CNTL_RESERVED96 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED96'; + mmDCRX_PHY_MACRO_CNTL_RESERVED97 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED97'; + mmDCRX_PHY_MACRO_CNTL_RESERVED98 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED98'; + mmDCRX_PHY_MACRO_CNTL_RESERVED99 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED99'; + mmDCRX_PHY_MACRO_CNTL_RESERVED100 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED100'; + mmDCRX_PHY_MACRO_CNTL_RESERVED101 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED101'; + mmDCRX_PHY_MACRO_CNTL_RESERVED102 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED102'; + mmDCRX_PHY_MACRO_CNTL_RESERVED103 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED103'; + mmDCRX_PHY_MACRO_CNTL_RESERVED104 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED104'; + mmDCRX_PHY_MACRO_CNTL_RESERVED105 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED105'; + mmDCRX_PHY_MACRO_CNTL_RESERVED106 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED106'; + mmDCRX_PHY_MACRO_CNTL_RESERVED107 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED107'; + mmDCRX_PHY_MACRO_CNTL_RESERVED108 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED108'; + mmDCRX_PHY_MACRO_CNTL_RESERVED109 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED109'; + mmDCRX_PHY_MACRO_CNTL_RESERVED110 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED110'; + mmDCRX_PHY_MACRO_CNTL_RESERVED111 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED111'; + mmDCRX_PHY_MACRO_CNTL_RESERVED112 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED112'; + mmDCRX_PHY_MACRO_CNTL_RESERVED113 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED113'; + mmDCRX_PHY_MACRO_CNTL_RESERVED114 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED114'; + mmDCRX_PHY_MACRO_CNTL_RESERVED115 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED115'; + mmDCRX_PHY_MACRO_CNTL_RESERVED116 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED116'; + mmDCRX_PHY_MACRO_CNTL_RESERVED117 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED117'; + mmDCRX_PHY_MACRO_CNTL_RESERVED118 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED118'; + mmDCRX_PHY_MACRO_CNTL_RESERVED119 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED119'; + mmDCRX_PHY_MACRO_CNTL_RESERVED120 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED120'; + mmDCRX_PHY_MACRO_CNTL_RESERVED121 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED121'; + mmDCRX_PHY_MACRO_CNTL_RESERVED122 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED122'; + mmDCRX_PHY_MACRO_CNTL_RESERVED123 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED123'; + mmDCRX_PHY_MACRO_CNTL_RESERVED124 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED124'; + mmDCRX_PHY_MACRO_CNTL_RESERVED125 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED125'; + mmDCRX_PHY_MACRO_CNTL_RESERVED126 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED126'; + mmDCRX_PHY_MACRO_CNTL_RESERVED127 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED127'; + mmDCRX_PHY_MACRO_CNTL_RESERVED128 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED128'; + mmDCRX_PHY_MACRO_CNTL_RESERVED129 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED129'; + mmDCRX_PHY_MACRO_CNTL_RESERVED130 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED130'; + mmDCRX_PHY_MACRO_CNTL_RESERVED131 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED131'; + mmDCRX_PHY_MACRO_CNTL_RESERVED132 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED132'; + mmDCRX_PHY_MACRO_CNTL_RESERVED133 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED133'; + mmDCRX_PHY_MACRO_CNTL_RESERVED134 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED134'; + mmDCRX_PHY_MACRO_CNTL_RESERVED135 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED135'; + mmDCRX_PHY_MACRO_CNTL_RESERVED136 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED136'; + mmDCRX_PHY_MACRO_CNTL_RESERVED137 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED137'; + mmDCRX_PHY_MACRO_CNTL_RESERVED138 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED138'; + mmDCRX_PHY_MACRO_CNTL_RESERVED139 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED139'; + mmDCRX_PHY_MACRO_CNTL_RESERVED140 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED140'; + mmDCRX_PHY_MACRO_CNTL_RESERVED141 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED141'; + mmDCRX_PHY_MACRO_CNTL_RESERVED142 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED142'; + mmDCRX_PHY_MACRO_CNTL_RESERVED143 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED143'; + mmDCRX_PHY_MACRO_CNTL_RESERVED144 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED144'; + mmDCRX_PHY_MACRO_CNTL_RESERVED145 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED145'; + mmDCRX_PHY_MACRO_CNTL_RESERVED146 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED146'; + mmDCRX_PHY_MACRO_CNTL_RESERVED147 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED147'; + mmDCRX_PHY_MACRO_CNTL_RESERVED148 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED148'; + mmDCRX_PHY_MACRO_CNTL_RESERVED149 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED149'; + mmDCRX_PHY_MACRO_CNTL_RESERVED150 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED150'; + mmDCRX_PHY_MACRO_CNTL_RESERVED151 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED151'; + mmDCRX_PHY_MACRO_CNTL_RESERVED152 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED152'; + mmDCRX_PHY_MACRO_CNTL_RESERVED153 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED153'; + mmDCRX_PHY_MACRO_CNTL_RESERVED154 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED154'; + mmDCRX_PHY_MACRO_CNTL_RESERVED155 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED155'; + mmDCRX_PHY_MACRO_CNTL_RESERVED156 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED156'; + mmDCRX_PHY_MACRO_CNTL_RESERVED157 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED157'; + mmDCRX_PHY_MACRO_CNTL_RESERVED158 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED158'; + mmDCRX_PHY_MACRO_CNTL_RESERVED159 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED159'; + mmDCRX_PHY_MACRO_CNTL_RESERVED160 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED160'; + mmDCRX_PHY_MACRO_CNTL_RESERVED161 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED161'; + mmDCRX_PHY_MACRO_CNTL_RESERVED162 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED162'; + mmDCRX_PHY_MACRO_CNTL_RESERVED163 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED163'; + mmDCRX_PHY_MACRO_CNTL_RESERVED164 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED164'; + mmDCRX_PHY_MACRO_CNTL_RESERVED165 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED165'; + mmDCRX_PHY_MACRO_CNTL_RESERVED166 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED166'; + mmDCRX_PHY_MACRO_CNTL_RESERVED167 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED167'; + mmDCRX_PHY_MACRO_CNTL_RESERVED168 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED168'; + mmDCRX_PHY_MACRO_CNTL_RESERVED169 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED169'; + mmDCRX_PHY_MACRO_CNTL_RESERVED170 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED170'; + mmDCRX_PHY_MACRO_CNTL_RESERVED171 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED171'; + mmDCRX_PHY_MACRO_CNTL_RESERVED172 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED172'; + mmDCRX_PHY_MACRO_CNTL_RESERVED173 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED173'; + mmDCRX_PHY_MACRO_CNTL_RESERVED174 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED174'; + mmDCRX_PHY_MACRO_CNTL_RESERVED175 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED175'; + mmDCRX_PHY_MACRO_CNTL_RESERVED176 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED176'; + mmDCRX_PHY_MACRO_CNTL_RESERVED177 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED177'; + mmDCRX_PHY_MACRO_CNTL_RESERVED178 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED178'; + mmDCRX_PHY_MACRO_CNTL_RESERVED179 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED179'; + mmDCRX_PHY_MACRO_CNTL_RESERVED180 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED180'; + mmDCRX_PHY_MACRO_CNTL_RESERVED181 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED181'; + mmDCRX_PHY_MACRO_CNTL_RESERVED182 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED182'; + mmDCRX_PHY_MACRO_CNTL_RESERVED183 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED183'; + mmDCRX_PHY_MACRO_CNTL_RESERVED184 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED184'; + mmDCRX_PHY_MACRO_CNTL_RESERVED185 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED185'; + mmDCRX_PHY_MACRO_CNTL_RESERVED186 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED186'; + mmDCRX_PHY_MACRO_CNTL_RESERVED187 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED187'; + mmDCRX_PHY_MACRO_CNTL_RESERVED188 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED188'; + mmDCRX_PHY_MACRO_CNTL_RESERVED189 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED189'; + mmDCRX_PHY_MACRO_CNTL_RESERVED190 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED190'; + mmDCRX_PHY_MACRO_CNTL_RESERVED191 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED191'; + mmDCRX_PHY_MACRO_CNTL_RESERVED192 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED192'; + mmDCRX_PHY_MACRO_CNTL_RESERVED193 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED193'; + mmDCRX_PHY_MACRO_CNTL_RESERVED194 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED194'; + mmDCRX_PHY_MACRO_CNTL_RESERVED195 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED195'; + mmDCRX_PHY_MACRO_CNTL_RESERVED196 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED196'; + mmDCRX_PHY_MACRO_CNTL_RESERVED197 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED197'; + mmDCRX_PHY_MACRO_CNTL_RESERVED198 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED198'; + mmDCRX_PHY_MACRO_CNTL_RESERVED199 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED199'; + mmDCRX_PHY_MACRO_CNTL_RESERVED200 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED200'; + mmDCRX_PHY_MACRO_CNTL_RESERVED201 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED201'; + mmDCRX_PHY_MACRO_CNTL_RESERVED202 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED202'; + mmDCRX_PHY_MACRO_CNTL_RESERVED203 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED203'; + mmDCRX_PHY_MACRO_CNTL_RESERVED204 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED204'; + mmDCRX_PHY_MACRO_CNTL_RESERVED205 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED205'; + mmDCRX_PHY_MACRO_CNTL_RESERVED206 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED206'; + mmDCRX_PHY_MACRO_CNTL_RESERVED207 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED207'; + mmDCRX_PHY_MACRO_CNTL_RESERVED208 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED208'; + mmDCRX_PHY_MACRO_CNTL_RESERVED209 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED209'; + mmDCRX_PHY_MACRO_CNTL_RESERVED210 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED210'; + mmDCRX_PHY_MACRO_CNTL_RESERVED211 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED211'; + mmDCRX_PHY_MACRO_CNTL_RESERVED212 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED212'; + mmDCRX_PHY_MACRO_CNTL_RESERVED213 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED213'; + mmDCRX_PHY_MACRO_CNTL_RESERVED214 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED214'; + mmDCRX_PHY_MACRO_CNTL_RESERVED215 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED215'; + mmDCRX_PHY_MACRO_CNTL_RESERVED216 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED216'; + mmDCRX_PHY_MACRO_CNTL_RESERVED217 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED217'; + mmDCRX_PHY_MACRO_CNTL_RESERVED218 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED218'; + mmDCRX_PHY_MACRO_CNTL_RESERVED219 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED219'; + mmDCRX_PHY_MACRO_CNTL_RESERVED220 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED220'; + mmDCRX_PHY_MACRO_CNTL_RESERVED221 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED221'; + mmDCRX_PHY_MACRO_CNTL_RESERVED222 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED222'; + mmDCRX_PHY_MACRO_CNTL_RESERVED223 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED223'; + mmDCRX_PHY_MACRO_CNTL_RESERVED224 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED224'; + mmDCRX_PHY_MACRO_CNTL_RESERVED225 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED225'; + mmDCRX_PHY_MACRO_CNTL_RESERVED226 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED226'; + mmDCRX_PHY_MACRO_CNTL_RESERVED227 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED227'; + mmDCRX_PHY_MACRO_CNTL_RESERVED228 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED228'; + mmDCRX_PHY_MACRO_CNTL_RESERVED229 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED229'; + mmDCRX_PHY_MACRO_CNTL_RESERVED230 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED230'; + mmDCRX_PHY_MACRO_CNTL_RESERVED231 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED231'; + mmDCRX_PHY_MACRO_CNTL_RESERVED232 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED232'; + mmDCRX_PHY_MACRO_CNTL_RESERVED233 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED233'; + mmDCRX_PHY_MACRO_CNTL_RESERVED234 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED234'; + mmDCRX_PHY_MACRO_CNTL_RESERVED235 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED235'; + mmDCRX_PHY_MACRO_CNTL_RESERVED236 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED236'; + mmDCRX_PHY_MACRO_CNTL_RESERVED237 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED237'; + mmDCRX_PHY_MACRO_CNTL_RESERVED238 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED238'; + mmDCRX_PHY_MACRO_CNTL_RESERVED239 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED239'; + mmDCRX_PHY_MACRO_CNTL_RESERVED240 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED240'; + mmDCRX_PHY_MACRO_CNTL_RESERVED241 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED241'; + mmDCRX_PHY_MACRO_CNTL_RESERVED242 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED242'; + mmDCRX_PHY_MACRO_CNTL_RESERVED243 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED243'; + mmDCRX_PHY_MACRO_CNTL_RESERVED244 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED244'; + mmDCRX_PHY_MACRO_CNTL_RESERVED245 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED245'; + mmDCRX_PHY_MACRO_CNTL_RESERVED246 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED246'; + mmDCRX_PHY_MACRO_CNTL_RESERVED247 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED247'; + mmDCRX_PHY_MACRO_CNTL_RESERVED248 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED248'; + mmDCRX_PHY_MACRO_CNTL_RESERVED249 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED249'; + mmDCRX_PHY_MACRO_CNTL_RESERVED250 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED250'; + mmDCRX_PHY_MACRO_CNTL_RESERVED251 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED251'; + mmDCRX_PHY_MACRO_CNTL_RESERVED252 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED252'; + mmDCRX_PHY_MACRO_CNTL_RESERVED253 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED253'; + mmDCRX_PHY_MACRO_CNTL_RESERVED254 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED254'; + mmDCRX_PHY_MACRO_CNTL_RESERVED255 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED255'; + mmDCRX_PHY_MACRO_CNTL_RESERVED256 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED256'; + mmDCRX_PHY_MACRO_CNTL_RESERVED257 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED257'; + mmDCRX_PHY_MACRO_CNTL_RESERVED258 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED258'; + mmDCRX_PHY_MACRO_CNTL_RESERVED259 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED259'; + mmDCRX_PHY_MACRO_CNTL_RESERVED260 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED260'; + mmDCRX_PHY_MACRO_CNTL_RESERVED261 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED261'; + mmDCRX_PHY_MACRO_CNTL_RESERVED262 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED262'; + mmDCRX_PHY_MACRO_CNTL_RESERVED263 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED263'; + mmDCRX_PHY_MACRO_CNTL_RESERVED264 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED264'; + mmDCRX_PHY_MACRO_CNTL_RESERVED265 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED265'; + mmDCRX_PHY_MACRO_CNTL_RESERVED266 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED266'; + mmDCRX_PHY_MACRO_CNTL_RESERVED267 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED267'; + mmDCRX_PHY_MACRO_CNTL_RESERVED268 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED268'; + mmDCRX_PHY_MACRO_CNTL_RESERVED269 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED269'; + mmDCRX_PHY_MACRO_CNTL_RESERVED270 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED270'; + mmDCRX_PHY_MACRO_CNTL_RESERVED271 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED271'; + mmDCRX_PHY_MACRO_CNTL_RESERVED272 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED272'; + mmDCRX_PHY_MACRO_CNTL_RESERVED273 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED273'; + mmDCRX_PHY_MACRO_CNTL_RESERVED274 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED274'; + mmDCRX_PHY_MACRO_CNTL_RESERVED275 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED275'; + mmDCRX_PHY_MACRO_CNTL_RESERVED276 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED276'; + mmDCRX_PHY_MACRO_CNTL_RESERVED277 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED277'; + mmDCRX_PHY_MACRO_CNTL_RESERVED278 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED278'; + mmDCRX_PHY_MACRO_CNTL_RESERVED279 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED279'; + mmDCRX_PHY_MACRO_CNTL_RESERVED280 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED280'; + mmDCRX_PHY_MACRO_CNTL_RESERVED281 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED281'; + mmDCRX_PHY_MACRO_CNTL_RESERVED282 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED282'; + mmDCRX_PHY_MACRO_CNTL_RESERVED283 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED283'; + mmDCRX_PHY_MACRO_CNTL_RESERVED284 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED284'; + mmDCRX_PHY_MACRO_CNTL_RESERVED285 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED285'; + mmDCRX_PHY_MACRO_CNTL_RESERVED286 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED286'; + mmDCRX_PHY_MACRO_CNTL_RESERVED287 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED287'; + mmDCRX_PHY_MACRO_CNTL_RESERVED288 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED288'; + mmDCRX_PHY_MACRO_CNTL_RESERVED289 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED289'; + mmDCRX_PHY_MACRO_CNTL_RESERVED290 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED290'; + mmDCRX_PHY_MACRO_CNTL_RESERVED291 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED291'; + mmDCRX_PHY_MACRO_CNTL_RESERVED292 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED292'; + mmDCRX_PHY_MACRO_CNTL_RESERVED293 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED293'; + mmDCRX_PHY_MACRO_CNTL_RESERVED294 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED294'; + mmDCRX_PHY_MACRO_CNTL_RESERVED295 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED295'; + mmDCRX_PHY_MACRO_CNTL_RESERVED296 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED296'; + mmDCRX_PHY_MACRO_CNTL_RESERVED297 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED297'; + mmDCRX_PHY_MACRO_CNTL_RESERVED298 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED298'; + mmDCRX_PHY_MACRO_CNTL_RESERVED299 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED299'; + mmDCRX_PHY_MACRO_CNTL_RESERVED300 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED300'; + mmDCRX_PHY_MACRO_CNTL_RESERVED301 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED301'; + mmDCRX_PHY_MACRO_CNTL_RESERVED302 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED302'; + mmDCRX_PHY_MACRO_CNTL_RESERVED303 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED303'; + mmDCRX_PHY_MACRO_CNTL_RESERVED304 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED304'; + mmDCRX_PHY_MACRO_CNTL_RESERVED305 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED305'; + mmDCRX_PHY_MACRO_CNTL_RESERVED306 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED306'; + mmDCRX_PHY_MACRO_CNTL_RESERVED307 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED307'; + mmDCRX_PHY_MACRO_CNTL_RESERVED308 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED308'; + mmDCRX_PHY_MACRO_CNTL_RESERVED309 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED309'; + mmDCRX_PHY_MACRO_CNTL_RESERVED310 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED310'; + mmDCRX_PHY_MACRO_CNTL_RESERVED311 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED311'; + mmDCRX_PHY_MACRO_CNTL_RESERVED312 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED312'; + mmDCRX_PHY_MACRO_CNTL_RESERVED313 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED313'; + mmDCRX_PHY_MACRO_CNTL_RESERVED314 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED314'; + mmDCRX_PHY_MACRO_CNTL_RESERVED315 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED315'; + mmDCRX_PHY_MACRO_CNTL_RESERVED316 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED316'; + mmDCRX_PHY_MACRO_CNTL_RESERVED317 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED317'; + mmDCRX_PHY_MACRO_CNTL_RESERVED318 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED318'; + mmDCRX_PHY_MACRO_CNTL_RESERVED319 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED319'; + mmDCRX_PHY_MACRO_CNTL_RESERVED320 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED320'; + mmDCRX_PHY_MACRO_CNTL_RESERVED321 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED321'; + mmDCRX_PHY_MACRO_CNTL_RESERVED322 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED322'; + mmDCRX_PHY_MACRO_CNTL_RESERVED323 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED323'; + mmDCRX_PHY_MACRO_CNTL_RESERVED324 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED324'; + mmDCRX_PHY_MACRO_CNTL_RESERVED325 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED325'; + mmDCRX_PHY_MACRO_CNTL_RESERVED326 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED326'; + mmDCRX_PHY_MACRO_CNTL_RESERVED327 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED327'; + mmDCRX_PHY_MACRO_CNTL_RESERVED328 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED328'; + mmDCRX_PHY_MACRO_CNTL_RESERVED329 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED329'; + mmDCRX_PHY_MACRO_CNTL_RESERVED330 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED330'; + mmDCRX_PHY_MACRO_CNTL_RESERVED331 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED331'; + mmDCRX_PHY_MACRO_CNTL_RESERVED332 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED332'; + mmDCRX_PHY_MACRO_CNTL_RESERVED333 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED333'; + mmDCRX_PHY_MACRO_CNTL_RESERVED334 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED334'; + mmDCRX_PHY_MACRO_CNTL_RESERVED335 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED335'; + mmDCRX_PHY_MACRO_CNTL_RESERVED336 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED336'; + mmDCRX_PHY_MACRO_CNTL_RESERVED337 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED337'; + mmDCRX_PHY_MACRO_CNTL_RESERVED338 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED338'; + mmDCRX_PHY_MACRO_CNTL_RESERVED339 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED339'; + mmDCRX_PHY_MACRO_CNTL_RESERVED340 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED340'; + mmDCRX_PHY_MACRO_CNTL_RESERVED341 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED341'; + mmDCRX_PHY_MACRO_CNTL_RESERVED342 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED342'; + mmDCRX_PHY_MACRO_CNTL_RESERVED343 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED343'; + mmDCRX_PHY_MACRO_CNTL_RESERVED344 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED344'; + mmDCRX_PHY_MACRO_CNTL_RESERVED345 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED345'; + mmDCRX_PHY_MACRO_CNTL_RESERVED346 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED346'; + mmDCRX_PHY_MACRO_CNTL_RESERVED347 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED347'; + mmDCRX_PHY_MACRO_CNTL_RESERVED348 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED348'; + mmDCRX_PHY_MACRO_CNTL_RESERVED349 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED349'; + mmDCRX_PHY_MACRO_CNTL_RESERVED350 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED350'; + mmDCRX_PHY_MACRO_CNTL_RESERVED351 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED351'; + mmDCRX_PHY_MACRO_CNTL_RESERVED352 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED352'; + mmDCRX_PHY_MACRO_CNTL_RESERVED353 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED353'; + mmDCRX_PHY_MACRO_CNTL_RESERVED354 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED354'; + mmDCRX_PHY_MACRO_CNTL_RESERVED355 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED355'; + mmDCRX_PHY_MACRO_CNTL_RESERVED356 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED356'; + mmDCRX_PHY_MACRO_CNTL_RESERVED357 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED357'; + mmDCRX_PHY_MACRO_CNTL_RESERVED358 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED358'; + mmDCRX_PHY_MACRO_CNTL_RESERVED359 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED359'; + mmDCRX_PHY_MACRO_CNTL_RESERVED360 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED360'; + mmDCRX_PHY_MACRO_CNTL_RESERVED361 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED361'; + mmDCRX_PHY_MACRO_CNTL_RESERVED362 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED362'; + mmDCRX_PHY_MACRO_CNTL_RESERVED363 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED363'; + mmDCRX_PHY_MACRO_CNTL_RESERVED364 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED364'; + mmDCRX_PHY_MACRO_CNTL_RESERVED365 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED365'; + mmDCRX_PHY_MACRO_CNTL_RESERVED366 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED366'; + mmDCRX_PHY_MACRO_CNTL_RESERVED367 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED367'; + mmDCRX_PHY_MACRO_CNTL_RESERVED368 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED368'; + mmDCRX_PHY_MACRO_CNTL_RESERVED369 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED369'; + mmDCRX_PHY_MACRO_CNTL_RESERVED370 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED370'; + mmDCRX_PHY_MACRO_CNTL_RESERVED371 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED371'; + mmDCRX_PHY_MACRO_CNTL_RESERVED372 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED372'; + mmDCRX_PHY_MACRO_CNTL_RESERVED373 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED373'; + mmDCRX_PHY_MACRO_CNTL_RESERVED374 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED374'; + mmDCRX_PHY_MACRO_CNTL_RESERVED375 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED375'; + mmDCRX_PHY_MACRO_CNTL_RESERVED376 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED376'; + mmDCRX_PHY_MACRO_CNTL_RESERVED377 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED377'; + mmDCRX_PHY_MACRO_CNTL_RESERVED378 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED378'; + mmDCRX_PHY_MACRO_CNTL_RESERVED379 :Result:='mmDCRX_PHY_MACRO_CNTL_RESERVED379'; + mmAUX_CONTROL :Result:='mmAUX_CONTROL'; + mmAUX_SW_CONTROL :Result:='mmAUX_SW_CONTROL'; + mmAUX_ARB_CONTROL :Result:='mmAUX_ARB_CONTROL'; + mmAUX_INTERRUPT_CONTROL :Result:='mmAUX_INTERRUPT_CONTROL'; + mmAUX_SW_STATUS :Result:='mmAUX_SW_STATUS'; + mmAUX_LS_STATUS :Result:='mmAUX_LS_STATUS'; + mmAUX_SW_DATA :Result:='mmAUX_SW_DATA'; + mmAUX_LS_DATA :Result:='mmAUX_LS_DATA'; + mmAUX_DPHY_TX_REF_CONTROL :Result:='mmAUX_DPHY_TX_REF_CONTROL'; + mmAUX_DPHY_TX_CONTROL :Result:='mmAUX_DPHY_TX_CONTROL'; + mmAUX_DPHY_RX_CONTROL0 :Result:='mmAUX_DPHY_RX_CONTROL0'; + mmAUX_DPHY_RX_CONTROL1 :Result:='mmAUX_DPHY_RX_CONTROL1'; + mmAUX_DPHY_TX_STATUS :Result:='mmAUX_DPHY_TX_STATUS'; + mmAUX_DPHY_RX_STATUS :Result:='mmAUX_DPHY_RX_STATUS'; + mmAUX_GTC_SYNC_CONTROL :Result:='mmAUX_GTC_SYNC_CONTROL'; + mmAUX_GTC_SYNC_ERROR_CONTROL :Result:='mmAUX_GTC_SYNC_ERROR_CONTROL'; + mmAUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmAUX_GTC_SYNC_CONTROLLER_STATUS'; + mmAUX_GTC_SYNC_STATUS :Result:='mmAUX_GTC_SYNC_STATUS'; + mmAUX_GTC_SYNC_DATA :Result:='mmAUX_GTC_SYNC_DATA'; + mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmAUX_TEST_DEBUG_INDEX :Result:='mmAUX_TEST_DEBUG_INDEX'; + mmAUX_TEST_DEBUG_DATA :Result:='mmAUX_TEST_DEBUG_DATA'; + mmDP_AUX1_AUX_CONTROL :Result:='mmDP_AUX1_AUX_CONTROL'; + mmDP_AUX1_AUX_SW_CONTROL :Result:='mmDP_AUX1_AUX_SW_CONTROL'; + mmDP_AUX1_AUX_ARB_CONTROL :Result:='mmDP_AUX1_AUX_ARB_CONTROL'; + mmDP_AUX1_AUX_INTERRUPT_CONTROL :Result:='mmDP_AUX1_AUX_INTERRUPT_CONTROL'; + mmDP_AUX1_AUX_SW_STATUS :Result:='mmDP_AUX1_AUX_SW_STATUS'; + mmDP_AUX1_AUX_LS_STATUS :Result:='mmDP_AUX1_AUX_LS_STATUS'; + mmDP_AUX1_AUX_SW_DATA :Result:='mmDP_AUX1_AUX_SW_DATA'; + mmDP_AUX1_AUX_LS_DATA :Result:='mmDP_AUX1_AUX_LS_DATA'; + mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL :Result:='mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL'; + mmDP_AUX1_AUX_DPHY_TX_CONTROL :Result:='mmDP_AUX1_AUX_DPHY_TX_CONTROL'; + mmDP_AUX1_AUX_DPHY_RX_CONTROL0 :Result:='mmDP_AUX1_AUX_DPHY_RX_CONTROL0'; + mmDP_AUX1_AUX_DPHY_RX_CONTROL1 :Result:='mmDP_AUX1_AUX_DPHY_RX_CONTROL1'; + mmDP_AUX1_AUX_DPHY_TX_STATUS :Result:='mmDP_AUX1_AUX_DPHY_TX_STATUS'; + mmDP_AUX1_AUX_DPHY_RX_STATUS :Result:='mmDP_AUX1_AUX_DPHY_RX_STATUS'; + mmDP_AUX1_AUX_GTC_SYNC_CONTROL :Result:='mmDP_AUX1_AUX_GTC_SYNC_CONTROL'; + mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL :Result:='mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL'; + mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS'; + mmDP_AUX1_AUX_GTC_SYNC_STATUS :Result:='mmDP_AUX1_AUX_GTC_SYNC_STATUS'; + mmDP_AUX1_AUX_GTC_SYNC_DATA :Result:='mmDP_AUX1_AUX_GTC_SYNC_DATA'; + mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmDP_AUX1_AUX_TEST_DEBUG_INDEX :Result:='mmDP_AUX1_AUX_TEST_DEBUG_INDEX'; + mmDP_AUX1_AUX_TEST_DEBUG_DATA :Result:='mmDP_AUX1_AUX_TEST_DEBUG_DATA'; + mmDP_AUX2_AUX_CONTROL :Result:='mmDP_AUX2_AUX_CONTROL'; + mmDP_AUX2_AUX_SW_CONTROL :Result:='mmDP_AUX2_AUX_SW_CONTROL'; + mmDP_AUX2_AUX_ARB_CONTROL :Result:='mmDP_AUX2_AUX_ARB_CONTROL'; + mmDP_AUX2_AUX_INTERRUPT_CONTROL :Result:='mmDP_AUX2_AUX_INTERRUPT_CONTROL'; + mmDP_AUX2_AUX_SW_STATUS :Result:='mmDP_AUX2_AUX_SW_STATUS'; + mmDP_AUX2_AUX_LS_STATUS :Result:='mmDP_AUX2_AUX_LS_STATUS'; + mmDP_AUX2_AUX_SW_DATA :Result:='mmDP_AUX2_AUX_SW_DATA'; + mmDP_AUX2_AUX_LS_DATA :Result:='mmDP_AUX2_AUX_LS_DATA'; + mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL :Result:='mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL'; + mmDP_AUX2_AUX_DPHY_TX_CONTROL :Result:='mmDP_AUX2_AUX_DPHY_TX_CONTROL'; + mmDP_AUX2_AUX_DPHY_RX_CONTROL0 :Result:='mmDP_AUX2_AUX_DPHY_RX_CONTROL0'; + mmDP_AUX2_AUX_DPHY_RX_CONTROL1 :Result:='mmDP_AUX2_AUX_DPHY_RX_CONTROL1'; + mmDP_AUX2_AUX_DPHY_TX_STATUS :Result:='mmDP_AUX2_AUX_DPHY_TX_STATUS'; + mmDP_AUX2_AUX_DPHY_RX_STATUS :Result:='mmDP_AUX2_AUX_DPHY_RX_STATUS'; + mmDP_AUX2_AUX_GTC_SYNC_CONTROL :Result:='mmDP_AUX2_AUX_GTC_SYNC_CONTROL'; + mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL :Result:='mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL'; + mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS'; + mmDP_AUX2_AUX_GTC_SYNC_STATUS :Result:='mmDP_AUX2_AUX_GTC_SYNC_STATUS'; + mmDP_AUX2_AUX_GTC_SYNC_DATA :Result:='mmDP_AUX2_AUX_GTC_SYNC_DATA'; + mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmDP_AUX2_AUX_TEST_DEBUG_INDEX :Result:='mmDP_AUX2_AUX_TEST_DEBUG_INDEX'; + mmDP_AUX2_AUX_TEST_DEBUG_DATA :Result:='mmDP_AUX2_AUX_TEST_DEBUG_DATA'; + mmDP_AUX3_AUX_CONTROL :Result:='mmDP_AUX3_AUX_CONTROL'; + mmDP_AUX3_AUX_SW_CONTROL :Result:='mmDP_AUX3_AUX_SW_CONTROL'; + mmDP_AUX3_AUX_ARB_CONTROL :Result:='mmDP_AUX3_AUX_ARB_CONTROL'; + mmDP_AUX3_AUX_INTERRUPT_CONTROL :Result:='mmDP_AUX3_AUX_INTERRUPT_CONTROL'; + mmDP_AUX3_AUX_SW_STATUS :Result:='mmDP_AUX3_AUX_SW_STATUS'; + mmDP_AUX3_AUX_LS_STATUS :Result:='mmDP_AUX3_AUX_LS_STATUS'; + mmDP_AUX3_AUX_SW_DATA :Result:='mmDP_AUX3_AUX_SW_DATA'; + mmDP_AUX3_AUX_LS_DATA :Result:='mmDP_AUX3_AUX_LS_DATA'; + mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL :Result:='mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL'; + mmDP_AUX3_AUX_DPHY_TX_CONTROL :Result:='mmDP_AUX3_AUX_DPHY_TX_CONTROL'; + mmDP_AUX3_AUX_DPHY_RX_CONTROL0 :Result:='mmDP_AUX3_AUX_DPHY_RX_CONTROL0'; + mmDP_AUX3_AUX_DPHY_RX_CONTROL1 :Result:='mmDP_AUX3_AUX_DPHY_RX_CONTROL1'; + mmDP_AUX3_AUX_DPHY_TX_STATUS :Result:='mmDP_AUX3_AUX_DPHY_TX_STATUS'; + mmDP_AUX3_AUX_DPHY_RX_STATUS :Result:='mmDP_AUX3_AUX_DPHY_RX_STATUS'; + mmDP_AUX3_AUX_GTC_SYNC_CONTROL :Result:='mmDP_AUX3_AUX_GTC_SYNC_CONTROL'; + mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL :Result:='mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL'; + mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS'; + mmDP_AUX3_AUX_GTC_SYNC_STATUS :Result:='mmDP_AUX3_AUX_GTC_SYNC_STATUS'; + mmDP_AUX3_AUX_GTC_SYNC_DATA :Result:='mmDP_AUX3_AUX_GTC_SYNC_DATA'; + mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmDP_AUX3_AUX_TEST_DEBUG_INDEX :Result:='mmDP_AUX3_AUX_TEST_DEBUG_INDEX'; + mmDP_AUX3_AUX_TEST_DEBUG_DATA :Result:='mmDP_AUX3_AUX_TEST_DEBUG_DATA'; + mmDP_AUX4_AUX_CONTROL :Result:='mmDP_AUX4_AUX_CONTROL'; + mmDP_AUX4_AUX_SW_CONTROL :Result:='mmDP_AUX4_AUX_SW_CONTROL'; + mmDP_AUX4_AUX_ARB_CONTROL :Result:='mmDP_AUX4_AUX_ARB_CONTROL'; + mmDP_AUX4_AUX_INTERRUPT_CONTROL :Result:='mmDP_AUX4_AUX_INTERRUPT_CONTROL'; + mmDP_AUX4_AUX_SW_STATUS :Result:='mmDP_AUX4_AUX_SW_STATUS'; + mmDP_AUX4_AUX_LS_STATUS :Result:='mmDP_AUX4_AUX_LS_STATUS'; + mmDP_AUX4_AUX_SW_DATA :Result:='mmDP_AUX4_AUX_SW_DATA'; + mmDP_AUX4_AUX_LS_DATA :Result:='mmDP_AUX4_AUX_LS_DATA'; + mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL :Result:='mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL'; + mmDP_AUX4_AUX_DPHY_TX_CONTROL :Result:='mmDP_AUX4_AUX_DPHY_TX_CONTROL'; + mmDP_AUX4_AUX_DPHY_RX_CONTROL0 :Result:='mmDP_AUX4_AUX_DPHY_RX_CONTROL0'; + mmDP_AUX4_AUX_DPHY_RX_CONTROL1 :Result:='mmDP_AUX4_AUX_DPHY_RX_CONTROL1'; + mmDP_AUX4_AUX_DPHY_TX_STATUS :Result:='mmDP_AUX4_AUX_DPHY_TX_STATUS'; + mmDP_AUX4_AUX_DPHY_RX_STATUS :Result:='mmDP_AUX4_AUX_DPHY_RX_STATUS'; + mmDP_AUX4_AUX_GTC_SYNC_CONTROL :Result:='mmDP_AUX4_AUX_GTC_SYNC_CONTROL'; + mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL :Result:='mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL'; + mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS'; + mmDP_AUX4_AUX_GTC_SYNC_STATUS :Result:='mmDP_AUX4_AUX_GTC_SYNC_STATUS'; + mmDP_AUX4_AUX_GTC_SYNC_DATA :Result:='mmDP_AUX4_AUX_GTC_SYNC_DATA'; + mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmDP_AUX4_AUX_TEST_DEBUG_INDEX :Result:='mmDP_AUX4_AUX_TEST_DEBUG_INDEX'; + mmDP_AUX4_AUX_TEST_DEBUG_DATA :Result:='mmDP_AUX4_AUX_TEST_DEBUG_DATA'; + mmDP_AUX5_AUX_CONTROL :Result:='mmDP_AUX5_AUX_CONTROL'; + mmDP_AUX5_AUX_SW_CONTROL :Result:='mmDP_AUX5_AUX_SW_CONTROL'; + mmDP_AUX5_AUX_ARB_CONTROL :Result:='mmDP_AUX5_AUX_ARB_CONTROL'; + mmDP_AUX5_AUX_INTERRUPT_CONTROL :Result:='mmDP_AUX5_AUX_INTERRUPT_CONTROL'; + mmDP_AUX5_AUX_SW_STATUS :Result:='mmDP_AUX5_AUX_SW_STATUS'; + mmDP_AUX5_AUX_LS_STATUS :Result:='mmDP_AUX5_AUX_LS_STATUS'; + mmDP_AUX5_AUX_SW_DATA :Result:='mmDP_AUX5_AUX_SW_DATA'; + mmDP_AUX5_AUX_LS_DATA :Result:='mmDP_AUX5_AUX_LS_DATA'; + mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL :Result:='mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL'; + mmDP_AUX5_AUX_DPHY_TX_CONTROL :Result:='mmDP_AUX5_AUX_DPHY_TX_CONTROL'; + mmDP_AUX5_AUX_DPHY_RX_CONTROL0 :Result:='mmDP_AUX5_AUX_DPHY_RX_CONTROL0'; + mmDP_AUX5_AUX_DPHY_RX_CONTROL1 :Result:='mmDP_AUX5_AUX_DPHY_RX_CONTROL1'; + mmDP_AUX5_AUX_DPHY_TX_STATUS :Result:='mmDP_AUX5_AUX_DPHY_TX_STATUS'; + mmDP_AUX5_AUX_DPHY_RX_STATUS :Result:='mmDP_AUX5_AUX_DPHY_RX_STATUS'; + mmDP_AUX5_AUX_GTC_SYNC_CONTROL :Result:='mmDP_AUX5_AUX_GTC_SYNC_CONTROL'; + mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL :Result:='mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL'; + mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS :Result:='mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS'; + mmDP_AUX5_AUX_GTC_SYNC_STATUS :Result:='mmDP_AUX5_AUX_GTC_SYNC_STATUS'; + mmDP_AUX5_AUX_GTC_SYNC_DATA :Result:='mmDP_AUX5_AUX_GTC_SYNC_DATA'; + mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE :Result:='mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE'; + mmDP_AUX5_AUX_TEST_DEBUG_INDEX :Result:='mmDP_AUX5_AUX_TEST_DEBUG_INDEX'; + mmDP_AUX5_AUX_TEST_DEBUG_DATA :Result:='mmDP_AUX5_AUX_TEST_DEBUG_DATA'; + mmDPHY_MACRO_CNTL_RESERVED0 :Result:='mmDPHY_MACRO_CNTL_RESERVED0'; + mmDPHY_MACRO_CNTL_RESERVED1 :Result:='mmDPHY_MACRO_CNTL_RESERVED1'; + mmDPHY_MACRO_CNTL_RESERVED2 :Result:='mmDPHY_MACRO_CNTL_RESERVED2'; + mmDPHY_MACRO_CNTL_RESERVED3 :Result:='mmDPHY_MACRO_CNTL_RESERVED3'; + mmDPHY_MACRO_CNTL_RESERVED4 :Result:='mmDPHY_MACRO_CNTL_RESERVED4'; + mmDPHY_MACRO_CNTL_RESERVED5 :Result:='mmDPHY_MACRO_CNTL_RESERVED5'; + mmDPHY_MACRO_CNTL_RESERVED6 :Result:='mmDPHY_MACRO_CNTL_RESERVED6'; + mmDPHY_MACRO_CNTL_RESERVED7 :Result:='mmDPHY_MACRO_CNTL_RESERVED7'; + mmDPHY_MACRO_CNTL_RESERVED8 :Result:='mmDPHY_MACRO_CNTL_RESERVED8'; + mmDPHY_MACRO_CNTL_RESERVED9 :Result:='mmDPHY_MACRO_CNTL_RESERVED9'; + mmDPHY_MACRO_CNTL_RESERVED10 :Result:='mmDPHY_MACRO_CNTL_RESERVED10'; + mmDPHY_MACRO_CNTL_RESERVED11 :Result:='mmDPHY_MACRO_CNTL_RESERVED11'; + mmDPHY_MACRO_CNTL_RESERVED12 :Result:='mmDPHY_MACRO_CNTL_RESERVED12'; + mmDPHY_MACRO_CNTL_RESERVED13 :Result:='mmDPHY_MACRO_CNTL_RESERVED13'; + mmDPHY_MACRO_CNTL_RESERVED14 :Result:='mmDPHY_MACRO_CNTL_RESERVED14'; + mmDPHY_MACRO_CNTL_RESERVED15 :Result:='mmDPHY_MACRO_CNTL_RESERVED15'; + mmDPHY_MACRO_CNTL_RESERVED16 :Result:='mmDPHY_MACRO_CNTL_RESERVED16'; + mmDPHY_MACRO_CNTL_RESERVED17 :Result:='mmDPHY_MACRO_CNTL_RESERVED17'; + mmDPHY_MACRO_CNTL_RESERVED18 :Result:='mmDPHY_MACRO_CNTL_RESERVED18'; + mmDPHY_MACRO_CNTL_RESERVED19 :Result:='mmDPHY_MACRO_CNTL_RESERVED19'; + mmDPHY_MACRO_CNTL_RESERVED20 :Result:='mmDPHY_MACRO_CNTL_RESERVED20'; + mmDPHY_MACRO_CNTL_RESERVED21 :Result:='mmDPHY_MACRO_CNTL_RESERVED21'; + mmDPHY_MACRO_CNTL_RESERVED22 :Result:='mmDPHY_MACRO_CNTL_RESERVED22'; + mmDPHY_MACRO_CNTL_RESERVED23 :Result:='mmDPHY_MACRO_CNTL_RESERVED23'; + mmDPHY_MACRO_CNTL_RESERVED24 :Result:='mmDPHY_MACRO_CNTL_RESERVED24'; + mmDPHY_MACRO_CNTL_RESERVED25 :Result:='mmDPHY_MACRO_CNTL_RESERVED25'; + mmDPHY_MACRO_CNTL_RESERVED26 :Result:='mmDPHY_MACRO_CNTL_RESERVED26'; + mmDPHY_MACRO_CNTL_RESERVED27 :Result:='mmDPHY_MACRO_CNTL_RESERVED27'; + mmDPHY_MACRO_CNTL_RESERVED28 :Result:='mmDPHY_MACRO_CNTL_RESERVED28'; + mmDPHY_MACRO_CNTL_RESERVED29 :Result:='mmDPHY_MACRO_CNTL_RESERVED29'; + mmDPHY_MACRO_CNTL_RESERVED30 :Result:='mmDPHY_MACRO_CNTL_RESERVED30'; + mmDPHY_MACRO_CNTL_RESERVED31 :Result:='mmDPHY_MACRO_CNTL_RESERVED31'; + mmDPHY_MACRO_CNTL_RESERVED32 :Result:='mmDPHY_MACRO_CNTL_RESERVED32'; + mmDPHY_MACRO_CNTL_RESERVED33 :Result:='mmDPHY_MACRO_CNTL_RESERVED33'; + mmDPHY_MACRO_CNTL_RESERVED34 :Result:='mmDPHY_MACRO_CNTL_RESERVED34'; + mmDPHY_MACRO_CNTL_RESERVED35 :Result:='mmDPHY_MACRO_CNTL_RESERVED35'; + mmDPHY_MACRO_CNTL_RESERVED36 :Result:='mmDPHY_MACRO_CNTL_RESERVED36'; + mmDPHY_MACRO_CNTL_RESERVED37 :Result:='mmDPHY_MACRO_CNTL_RESERVED37'; + mmDPHY_MACRO_CNTL_RESERVED38 :Result:='mmDPHY_MACRO_CNTL_RESERVED38'; + mmDPHY_MACRO_CNTL_RESERVED39 :Result:='mmDPHY_MACRO_CNTL_RESERVED39'; + mmDPHY_MACRO_CNTL_RESERVED40 :Result:='mmDPHY_MACRO_CNTL_RESERVED40'; + mmDPHY_MACRO_CNTL_RESERVED41 :Result:='mmDPHY_MACRO_CNTL_RESERVED41'; + mmDPHY_MACRO_CNTL_RESERVED42 :Result:='mmDPHY_MACRO_CNTL_RESERVED42'; + mmDPHY_MACRO_CNTL_RESERVED43 :Result:='mmDPHY_MACRO_CNTL_RESERVED43'; + mmDPHY_MACRO_CNTL_RESERVED44 :Result:='mmDPHY_MACRO_CNTL_RESERVED44'; + mmDPHY_MACRO_CNTL_RESERVED45 :Result:='mmDPHY_MACRO_CNTL_RESERVED45'; + mmDPHY_MACRO_CNTL_RESERVED46 :Result:='mmDPHY_MACRO_CNTL_RESERVED46'; + mmDPHY_MACRO_CNTL_RESERVED47 :Result:='mmDPHY_MACRO_CNTL_RESERVED47'; + mmDPHY_MACRO_CNTL_RESERVED48 :Result:='mmDPHY_MACRO_CNTL_RESERVED48'; + mmDPHY_MACRO_CNTL_RESERVED49 :Result:='mmDPHY_MACRO_CNTL_RESERVED49'; + mmDPHY_MACRO_CNTL_RESERVED50 :Result:='mmDPHY_MACRO_CNTL_RESERVED50'; + mmDPHY_MACRO_CNTL_RESERVED51 :Result:='mmDPHY_MACRO_CNTL_RESERVED51'; + mmDPHY_MACRO_CNTL_RESERVED52 :Result:='mmDPHY_MACRO_CNTL_RESERVED52'; + mmDPHY_MACRO_CNTL_RESERVED53 :Result:='mmDPHY_MACRO_CNTL_RESERVED53'; + mmDPHY_MACRO_CNTL_RESERVED54 :Result:='mmDPHY_MACRO_CNTL_RESERVED54'; + mmDPHY_MACRO_CNTL_RESERVED55 :Result:='mmDPHY_MACRO_CNTL_RESERVED55'; + mmDPHY_MACRO_CNTL_RESERVED56 :Result:='mmDPHY_MACRO_CNTL_RESERVED56'; + mmDPHY_MACRO_CNTL_RESERVED57 :Result:='mmDPHY_MACRO_CNTL_RESERVED57'; + mmDPHY_MACRO_CNTL_RESERVED58 :Result:='mmDPHY_MACRO_CNTL_RESERVED58'; + mmDPHY_MACRO_CNTL_RESERVED59 :Result:='mmDPHY_MACRO_CNTL_RESERVED59'; + mmDPHY_MACRO_CNTL_RESERVED60 :Result:='mmDPHY_MACRO_CNTL_RESERVED60'; + mmDPHY_MACRO_CNTL_RESERVED61 :Result:='mmDPHY_MACRO_CNTL_RESERVED61'; + mmDPHY_MACRO_CNTL_RESERVED62 :Result:='mmDPHY_MACRO_CNTL_RESERVED62'; + mmDPHY_MACRO_CNTL_RESERVED63 :Result:='mmDPHY_MACRO_CNTL_RESERVED63'; + mmWB_ENABLE :Result:='mmWB_ENABLE'; + mmWB_EC_CONFIG :Result:='mmWB_EC_CONFIG'; + mmCNV_MODE :Result:='mmCNV_MODE'; + mmCNV_WINDOW_START :Result:='mmCNV_WINDOW_START'; + mmCNV_WINDOW_SIZE :Result:='mmCNV_WINDOW_SIZE'; + mmCNV_UPDATE :Result:='mmCNV_UPDATE'; + mmCNV_SOURCE_SIZE :Result:='mmCNV_SOURCE_SIZE'; + mmCNV_CSC_CONTROL :Result:='mmCNV_CSC_CONTROL'; + mmCNV_CSC_C11_C12 :Result:='mmCNV_CSC_C11_C12'; + mmCNV_CSC_C13_C14 :Result:='mmCNV_CSC_C13_C14'; + mmCNV_CSC_C21_C22 :Result:='mmCNV_CSC_C21_C22'; + mmCNV_CSC_C23_C24 :Result:='mmCNV_CSC_C23_C24'; + mmCNV_CSC_C31_C32 :Result:='mmCNV_CSC_C31_C32'; + mmCNV_CSC_C33_C34 :Result:='mmCNV_CSC_C33_C34'; + mmCNV_CSC_ROUND_OFFSET_R :Result:='mmCNV_CSC_ROUND_OFFSET_R'; + mmCNV_CSC_ROUND_OFFSET_G :Result:='mmCNV_CSC_ROUND_OFFSET_G'; + mmCNV_CSC_ROUND_OFFSET_B :Result:='mmCNV_CSC_ROUND_OFFSET_B'; + mmCNV_CSC_CLAMP_R :Result:='mmCNV_CSC_CLAMP_R'; + mmCNV_CSC_CLAMP_G :Result:='mmCNV_CSC_CLAMP_G'; + mmCNV_CSC_CLAMP_B :Result:='mmCNV_CSC_CLAMP_B'; + mmCNV_TEST_CNTL :Result:='mmCNV_TEST_CNTL'; + mmCNV_TEST_CRC_RED :Result:='mmCNV_TEST_CRC_RED'; + mmCNV_TEST_CRC_GREEN :Result:='mmCNV_TEST_CRC_GREEN'; + mmCNV_TEST_CRC_BLUE :Result:='mmCNV_TEST_CRC_BLUE'; + mmWB_DEBUG_CTRL :Result:='mmWB_DEBUG_CTRL'; + mmWB_DBG_MODE :Result:='mmWB_DBG_MODE'; + mmWB_HW_DEBUG :Result:='mmWB_HW_DEBUG'; + mmCNV_INPUT_SELECT :Result:='mmCNV_INPUT_SELECT'; + mmCNV_TEST_DEBUG_INDEX :Result:='mmCNV_TEST_DEBUG_INDEX'; + mmCNV_TEST_DEBUG_DATA :Result:='mmCNV_TEST_DEBUG_DATA'; + mmWB_SOFT_RESET :Result:='mmWB_SOFT_RESET'; + mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL'; + mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R'; + mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS'; + mmMCIF_WB0_MCIF_WB_BUF_PITCH :Result:='mmMCIF_WB0_MCIF_WB_BUF_PITCH'; + mmMCIF_WB0_MCIF_WB_BUF_1_STATUS :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_STATUS'; + mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2'; + mmMCIF_WB0_MCIF_WB_BUF_2_STATUS :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_STATUS'; + mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2'; + mmMCIF_WB0_MCIF_WB_BUF_3_STATUS :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_STATUS'; + mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2'; + mmMCIF_WB0_MCIF_WB_BUF_4_STATUS :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_STATUS'; + mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2'; + mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL :Result:='mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL'; + mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK :Result:='mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK'; + mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX :Result:='mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX'; + mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA :Result:='mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA'; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y'; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C'; + mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y'; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C'; + mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y'; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C'; + mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y'; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C'; + mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET :Result:='mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET'; + mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL :Result:='mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL'; + mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL :Result:='mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL'; + mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL'; + mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R'; + mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS'; + mmMCIF_WB1_MCIF_WB_BUF_PITCH :Result:='mmMCIF_WB1_MCIF_WB_BUF_PITCH'; + mmMCIF_WB1_MCIF_WB_BUF_1_STATUS :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_STATUS'; + mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2'; + mmMCIF_WB1_MCIF_WB_BUF_2_STATUS :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_STATUS'; + mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2'; + mmMCIF_WB1_MCIF_WB_BUF_3_STATUS :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_STATUS'; + mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2'; + mmMCIF_WB1_MCIF_WB_BUF_4_STATUS :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_STATUS'; + mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2'; + mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL :Result:='mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL'; + mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK :Result:='mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK'; + mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX :Result:='mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX'; + mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA :Result:='mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA'; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y'; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C'; + mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y'; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C'; + mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y'; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C'; + mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y'; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C'; + mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET :Result:='mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET'; + mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL :Result:='mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL'; + mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL :Result:='mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL'; + mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL'; + mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R'; + mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS'; + mmMCIF_WB2_MCIF_WB_BUF_PITCH :Result:='mmMCIF_WB2_MCIF_WB_BUF_PITCH'; + mmMCIF_WB2_MCIF_WB_BUF_1_STATUS :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_STATUS'; + mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2'; + mmMCIF_WB2_MCIF_WB_BUF_2_STATUS :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_STATUS'; + mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2'; + mmMCIF_WB2_MCIF_WB_BUF_3_STATUS :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_STATUS'; + mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2'; + mmMCIF_WB2_MCIF_WB_BUF_4_STATUS :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_STATUS'; + mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2'; + mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL :Result:='mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL'; + mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK :Result:='mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK'; + mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX :Result:='mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX'; + mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA :Result:='mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA'; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y'; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C'; + mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y'; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C'; + mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y'; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C'; + mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y'; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C'; + mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET :Result:='mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET'; + mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL :Result:='mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL'; + mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL :Result:='mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL'; + mmDC_PERFMON9_PERFCOUNTER_CNTL :Result:='mmDC_PERFMON9_PERFCOUNTER_CNTL'; + mmDC_PERFMON9_PERFCOUNTER_STATE :Result:='mmDC_PERFMON9_PERFCOUNTER_STATE'; + mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC :Result:='mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC'; + mmDC_PERFMON9_PERFMON_CNTL :Result:='mmDC_PERFMON9_PERFMON_CNTL'; + mmDC_PERFMON9_PERFMON_CVALUE_LOW :Result:='mmDC_PERFMON9_PERFMON_CVALUE_LOW'; + mmDC_PERFMON9_PERFMON_HI :Result:='mmDC_PERFMON9_PERFMON_HI'; + mmDC_PERFMON9_PERFMON_LOW :Result:='mmDC_PERFMON9_PERFMON_LOW'; + mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX :Result:='mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX'; + mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA :Result:='mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA'; + mmDC_PERFMON9_PERFMON_CNTL2 :Result:='mmDC_PERFMON9_PERFMON_CNTL2'; + mmCPLL_MACRO_CNTL_RESERVED0 :Result:='mmCPLL_MACRO_CNTL_RESERVED0'; + mmCPLL_MACRO_CNTL_RESERVED1 :Result:='mmCPLL_MACRO_CNTL_RESERVED1'; + mmCPLL_MACRO_CNTL_RESERVED2 :Result:='mmCPLL_MACRO_CNTL_RESERVED2'; + mmCPLL_MACRO_CNTL_RESERVED3 :Result:='mmCPLL_MACRO_CNTL_RESERVED3'; + mmCPLL_MACRO_CNTL_RESERVED4 :Result:='mmCPLL_MACRO_CNTL_RESERVED4'; + mmCPLL_MACRO_CNTL_RESERVED5 :Result:='mmCPLL_MACRO_CNTL_RESERVED5'; + mmCPLL_MACRO_CNTL_RESERVED6 :Result:='mmCPLL_MACRO_CNTL_RESERVED6'; + mmCPLL_MACRO_CNTL_RESERVED7 :Result:='mmCPLL_MACRO_CNTL_RESERVED7'; + mmCPLL_MACRO_CNTL_RESERVED8 :Result:='mmCPLL_MACRO_CNTL_RESERVED8'; + mmCPLL_MACRO_CNTL_RESERVED9 :Result:='mmCPLL_MACRO_CNTL_RESERVED9'; + mmCPLL_MACRO_CNTL_RESERVED10 :Result:='mmCPLL_MACRO_CNTL_RESERVED10'; + mmCPLL_MACRO_CNTL_RESERVED11 :Result:='mmCPLL_MACRO_CNTL_RESERVED11'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10'; + mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 :Result:='mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10'; + mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 :Result:='mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10'; + mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 :Result:='mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11'; + mmSRBM_PERFMON_CNTL :Result:='mmSRBM_PERFMON_CNTL'; + mmSRBM_PERFCOUNTER0_SELECT :Result:='mmSRBM_PERFCOUNTER0_SELECT'; + mmSRBM_PERFCOUNTER1_SELECT :Result:='mmSRBM_PERFCOUNTER1_SELECT'; + mmSRBM_PERFCOUNTER0_LO :Result:='mmSRBM_PERFCOUNTER0_LO'; + mmSRBM_PERFCOUNTER0_HI :Result:='mmSRBM_PERFCOUNTER0_HI'; + mmSRBM_PERFCOUNTER1_LO :Result:='mmSRBM_PERFCOUNTER1_LO'; + mmSRBM_PERFCOUNTER1_HI :Result:='mmSRBM_PERFCOUNTER1_HI'; + mmVCE_STATUS :Result:='mmVCE_STATUS'; + mmVCE_VCPU_CNTL :Result:='mmVCE_VCPU_CNTL'; + mmVCE_VCPU_CACHE_OFFSET0 :Result:='mmVCE_VCPU_CACHE_OFFSET0'; + mmVCE_VCPU_CACHE_SIZE0 :Result:='mmVCE_VCPU_CACHE_SIZE0'; + mmVCE_VCPU_CACHE_OFFSET1 :Result:='mmVCE_VCPU_CACHE_OFFSET1'; + mmVCE_VCPU_CACHE_SIZE1 :Result:='mmVCE_VCPU_CACHE_SIZE1'; + mmVCE_VCPU_CACHE_OFFSET2 :Result:='mmVCE_VCPU_CACHE_OFFSET2'; + mmVCE_VCPU_CACHE_SIZE2 :Result:='mmVCE_VCPU_CACHE_SIZE2'; + mmVCE_SOFT_RESET :Result:='mmVCE_SOFT_RESET'; + mmVCE_RB_BASE_LO2 :Result:='mmVCE_RB_BASE_LO2'; + mmVCE_RB_BASE_HI2 :Result:='mmVCE_RB_BASE_HI2'; + mmVCE_RB_SIZE2 :Result:='mmVCE_RB_SIZE2'; + mmVCE_RB_RPTR2 :Result:='mmVCE_RB_RPTR2'; + mmVCE_RB_WPTR2 :Result:='mmVCE_RB_WPTR2'; + mmVCE_RB_BASE_LO :Result:='mmVCE_RB_BASE_LO'; + mmVCE_RB_BASE_HI :Result:='mmVCE_RB_BASE_HI'; + mmVCE_RB_SIZE :Result:='mmVCE_RB_SIZE'; + mmVCE_RB_RPTR :Result:='mmVCE_RB_RPTR'; + mmVCE_RB_WPTR :Result:='mmVCE_RB_WPTR'; + mmVCE_RB_ARB_CTRL :Result:='mmVCE_RB_ARB_CTRL'; + mmVCE_RB_BASE_LO3 :Result:='mmVCE_RB_BASE_LO3'; + mmVCE_RB_BASE_HI3 :Result:='mmVCE_RB_BASE_HI3'; + mmVCE_RB_SIZE3 :Result:='mmVCE_RB_SIZE3'; + mmVCE_RB_RPTR3 :Result:='mmVCE_RB_RPTR3'; + mmVCE_RB_WPTR3 :Result:='mmVCE_RB_WPTR3'; + mmVCE_UENC_DMA_DCLK_CTRL :Result:='mmVCE_UENC_DMA_DCLK_CTRL'; + mmVCE_SYS_INT_EN :Result:='mmVCE_SYS_INT_EN'; + mmVCE_SYS_INT_ACK :Result:='mmVCE_SYS_INT_ACK'; + mmVCE_LMI_VCPU_CACHE_40BIT_BAR :Result:='mmVCE_LMI_VCPU_CACHE_40BIT_BAR'; + mmVCE_LMI_CTRL2 :Result:='mmVCE_LMI_CTRL2'; + mmVCE_LMI_SWAP_CNTL3 :Result:='mmVCE_LMI_SWAP_CNTL3'; + mmVCE_LMI_CTRL :Result:='mmVCE_LMI_CTRL'; + mmVCE_LMI_SWAP_CNTL :Result:='mmVCE_LMI_SWAP_CNTL'; + mmVCE_LMI_SWAP_CNTL1 :Result:='mmVCE_LMI_SWAP_CNTL1'; + mmVCE_LMI_SWAP_CNTL2 :Result:='mmVCE_LMI_SWAP_CNTL2'; + mmVCE_LMI_CACHE_CTRL :Result:='mmVCE_LMI_CACHE_CTRL'; + mmSAM_IH_EXT_ERR_INTR :Result:='mmSAM_IH_EXT_ERR_INTR'; + mmSAM_IH_EXT_ERR_INTR_STATUS :Result:='mmSAM_IH_EXT_ERR_INTR_STATUS'; + mmSDMA0_PERFMON_CNTL :Result:='mmSDMA0_PERFMON_CNTL'; + mmSDMA0_PERFCOUNTER0_RESULT :Result:='mmSDMA0_PERFCOUNTER0_RESULT'; + mmSDMA0_PERFCOUNTER1_RESULT :Result:='mmSDMA0_PERFCOUNTER1_RESULT'; + mmSDMA1_PERFMON_CNTL :Result:='mmSDMA1_PERFMON_CNTL'; + mmSDMA1_PERFCOUNTER0_RESULT :Result:='mmSDMA1_PERFCOUNTER0_RESULT'; + mmSDMA1_PERFCOUNTER1_RESULT :Result:='mmSDMA1_PERFCOUNTER1_RESULT'; + mmDB_RENDER_CONTROL :Result:='mmDB_RENDER_CONTROL'; + mmDB_COUNT_CONTROL :Result:='mmDB_COUNT_CONTROL'; + mmDB_DEPTH_VIEW :Result:='mmDB_DEPTH_VIEW'; + mmDB_RENDER_OVERRIDE :Result:='mmDB_RENDER_OVERRIDE'; + mmDB_RENDER_OVERRIDE2 :Result:='mmDB_RENDER_OVERRIDE2'; + mmDB_HTILE_DATA_BASE :Result:='mmDB_HTILE_DATA_BASE'; + mmDB_DEPTH_BOUNDS_MIN :Result:='mmDB_DEPTH_BOUNDS_MIN'; + mmDB_DEPTH_BOUNDS_MAX :Result:='mmDB_DEPTH_BOUNDS_MAX'; + mmDB_STENCIL_CLEAR :Result:='mmDB_STENCIL_CLEAR'; + mmDB_DEPTH_CLEAR :Result:='mmDB_DEPTH_CLEAR'; + mmPA_SC_SCREEN_SCISSOR_TL :Result:='mmPA_SC_SCREEN_SCISSOR_TL'; + mmPA_SC_SCREEN_SCISSOR_BR :Result:='mmPA_SC_SCREEN_SCISSOR_BR'; + mmDB_DEPTH_INFO :Result:='mmDB_DEPTH_INFO'; + mmDB_Z_INFO :Result:='mmDB_Z_INFO'; + mmDB_STENCIL_INFO :Result:='mmDB_STENCIL_INFO'; + mmDB_Z_READ_BASE :Result:='mmDB_Z_READ_BASE'; + mmDB_STENCIL_READ_BASE :Result:='mmDB_STENCIL_READ_BASE'; + mmDB_Z_WRITE_BASE :Result:='mmDB_Z_WRITE_BASE'; + mmDB_STENCIL_WRITE_BASE :Result:='mmDB_STENCIL_WRITE_BASE'; + mmDB_DEPTH_SIZE :Result:='mmDB_DEPTH_SIZE'; + mmDB_DEPTH_SLICE :Result:='mmDB_DEPTH_SLICE'; + mmTA_BC_BASE_ADDR :Result:='mmTA_BC_BASE_ADDR'; + mmTA_BC_BASE_ADDR_HI :Result:='mmTA_BC_BASE_ADDR_HI'; + mmCOHER_DEST_BASE_HI_0 :Result:='mmCOHER_DEST_BASE_HI_0'; + mmCOHER_DEST_BASE_HI_1 :Result:='mmCOHER_DEST_BASE_HI_1'; + mmCOHER_DEST_BASE_HI_2 :Result:='mmCOHER_DEST_BASE_HI_2'; + mmCOHER_DEST_BASE_HI_3 :Result:='mmCOHER_DEST_BASE_HI_3'; + mmCOHER_DEST_BASE_2 :Result:='mmCOHER_DEST_BASE_2'; + mmCOHER_DEST_BASE_3 :Result:='mmCOHER_DEST_BASE_3'; + mmPA_SC_WINDOW_OFFSET :Result:='mmPA_SC_WINDOW_OFFSET'; + mmPA_SC_WINDOW_SCISSOR_TL :Result:='mmPA_SC_WINDOW_SCISSOR_TL'; + mmPA_SC_WINDOW_SCISSOR_BR :Result:='mmPA_SC_WINDOW_SCISSOR_BR'; + mmPA_SC_CLIPRECT_RULE :Result:='mmPA_SC_CLIPRECT_RULE'; + mmPA_SC_CLIPRECT_0_TL :Result:='mmPA_SC_CLIPRECT_0_TL'; + mmPA_SC_CLIPRECT_0_BR :Result:='mmPA_SC_CLIPRECT_0_BR'; + mmPA_SC_CLIPRECT_1_TL :Result:='mmPA_SC_CLIPRECT_1_TL'; + mmPA_SC_CLIPRECT_1_BR :Result:='mmPA_SC_CLIPRECT_1_BR'; + mmPA_SC_CLIPRECT_2_TL :Result:='mmPA_SC_CLIPRECT_2_TL'; + mmPA_SC_CLIPRECT_2_BR :Result:='mmPA_SC_CLIPRECT_2_BR'; + mmPA_SC_CLIPRECT_3_TL :Result:='mmPA_SC_CLIPRECT_3_TL'; + mmPA_SC_CLIPRECT_3_BR :Result:='mmPA_SC_CLIPRECT_3_BR'; + mmPA_SC_EDGERULE :Result:='mmPA_SC_EDGERULE'; + mmPA_SU_HARDWARE_SCREEN_OFFSET :Result:='mmPA_SU_HARDWARE_SCREEN_OFFSET'; + mmCB_TARGET_MASK :Result:='mmCB_TARGET_MASK'; + mmCB_SHADER_MASK :Result:='mmCB_SHADER_MASK'; + mmPA_SC_GENERIC_SCISSOR_TL :Result:='mmPA_SC_GENERIC_SCISSOR_TL'; + mmPA_SC_GENERIC_SCISSOR_BR :Result:='mmPA_SC_GENERIC_SCISSOR_BR'; + mmCOHER_DEST_BASE_0 :Result:='mmCOHER_DEST_BASE_0'; + mmCOHER_DEST_BASE_1 :Result:='mmCOHER_DEST_BASE_1'; + mmPA_SC_VPORT_SCISSOR_0_TL :Result:='mmPA_SC_VPORT_SCISSOR_0_TL'; + mmPA_SC_VPORT_SCISSOR_0_BR :Result:='mmPA_SC_VPORT_SCISSOR_0_BR'; + mmPA_SC_VPORT_SCISSOR_1_TL :Result:='mmPA_SC_VPORT_SCISSOR_1_TL'; + mmPA_SC_VPORT_SCISSOR_1_BR :Result:='mmPA_SC_VPORT_SCISSOR_1_BR'; + mmPA_SC_VPORT_SCISSOR_2_TL :Result:='mmPA_SC_VPORT_SCISSOR_2_TL'; + mmPA_SC_VPORT_SCISSOR_2_BR :Result:='mmPA_SC_VPORT_SCISSOR_2_BR'; + mmPA_SC_VPORT_SCISSOR_3_TL :Result:='mmPA_SC_VPORT_SCISSOR_3_TL'; + mmPA_SC_VPORT_SCISSOR_3_BR :Result:='mmPA_SC_VPORT_SCISSOR_3_BR'; + mmPA_SC_VPORT_SCISSOR_4_TL :Result:='mmPA_SC_VPORT_SCISSOR_4_TL'; + mmPA_SC_VPORT_SCISSOR_4_BR :Result:='mmPA_SC_VPORT_SCISSOR_4_BR'; + mmPA_SC_VPORT_SCISSOR_5_TL :Result:='mmPA_SC_VPORT_SCISSOR_5_TL'; + mmPA_SC_VPORT_SCISSOR_5_BR :Result:='mmPA_SC_VPORT_SCISSOR_5_BR'; + mmPA_SC_VPORT_SCISSOR_6_TL :Result:='mmPA_SC_VPORT_SCISSOR_6_TL'; + mmPA_SC_VPORT_SCISSOR_6_BR :Result:='mmPA_SC_VPORT_SCISSOR_6_BR'; + mmPA_SC_VPORT_SCISSOR_7_TL :Result:='mmPA_SC_VPORT_SCISSOR_7_TL'; + mmPA_SC_VPORT_SCISSOR_7_BR :Result:='mmPA_SC_VPORT_SCISSOR_7_BR'; + mmPA_SC_VPORT_SCISSOR_8_TL :Result:='mmPA_SC_VPORT_SCISSOR_8_TL'; + mmPA_SC_VPORT_SCISSOR_8_BR :Result:='mmPA_SC_VPORT_SCISSOR_8_BR'; + mmPA_SC_VPORT_SCISSOR_9_TL :Result:='mmPA_SC_VPORT_SCISSOR_9_TL'; + mmPA_SC_VPORT_SCISSOR_9_BR :Result:='mmPA_SC_VPORT_SCISSOR_9_BR'; + mmPA_SC_VPORT_SCISSOR_10_TL :Result:='mmPA_SC_VPORT_SCISSOR_10_TL'; + mmPA_SC_VPORT_SCISSOR_10_BR :Result:='mmPA_SC_VPORT_SCISSOR_10_BR'; + mmPA_SC_VPORT_SCISSOR_11_TL :Result:='mmPA_SC_VPORT_SCISSOR_11_TL'; + mmPA_SC_VPORT_SCISSOR_11_BR :Result:='mmPA_SC_VPORT_SCISSOR_11_BR'; + mmPA_SC_VPORT_SCISSOR_12_TL :Result:='mmPA_SC_VPORT_SCISSOR_12_TL'; + mmPA_SC_VPORT_SCISSOR_12_BR :Result:='mmPA_SC_VPORT_SCISSOR_12_BR'; + mmPA_SC_VPORT_SCISSOR_13_TL :Result:='mmPA_SC_VPORT_SCISSOR_13_TL'; + mmPA_SC_VPORT_SCISSOR_13_BR :Result:='mmPA_SC_VPORT_SCISSOR_13_BR'; + mmPA_SC_VPORT_SCISSOR_14_TL :Result:='mmPA_SC_VPORT_SCISSOR_14_TL'; + mmPA_SC_VPORT_SCISSOR_14_BR :Result:='mmPA_SC_VPORT_SCISSOR_14_BR'; + mmPA_SC_VPORT_SCISSOR_15_TL :Result:='mmPA_SC_VPORT_SCISSOR_15_TL'; + mmPA_SC_VPORT_SCISSOR_15_BR :Result:='mmPA_SC_VPORT_SCISSOR_15_BR'; + mmPA_SC_VPORT_ZMIN_0 :Result:='mmPA_SC_VPORT_ZMIN_0'; + mmPA_SC_VPORT_ZMAX_0 :Result:='mmPA_SC_VPORT_ZMAX_0'; + mmPA_SC_VPORT_ZMIN_1 :Result:='mmPA_SC_VPORT_ZMIN_1'; + mmPA_SC_VPORT_ZMAX_1 :Result:='mmPA_SC_VPORT_ZMAX_1'; + mmPA_SC_VPORT_ZMIN_2 :Result:='mmPA_SC_VPORT_ZMIN_2'; + mmPA_SC_VPORT_ZMAX_2 :Result:='mmPA_SC_VPORT_ZMAX_2'; + mmPA_SC_VPORT_ZMIN_3 :Result:='mmPA_SC_VPORT_ZMIN_3'; + mmPA_SC_VPORT_ZMAX_3 :Result:='mmPA_SC_VPORT_ZMAX_3'; + mmPA_SC_VPORT_ZMIN_4 :Result:='mmPA_SC_VPORT_ZMIN_4'; + mmPA_SC_VPORT_ZMAX_4 :Result:='mmPA_SC_VPORT_ZMAX_4'; + mmPA_SC_VPORT_ZMIN_5 :Result:='mmPA_SC_VPORT_ZMIN_5'; + mmPA_SC_VPORT_ZMAX_5 :Result:='mmPA_SC_VPORT_ZMAX_5'; + mmPA_SC_VPORT_ZMIN_6 :Result:='mmPA_SC_VPORT_ZMIN_6'; + mmPA_SC_VPORT_ZMAX_6 :Result:='mmPA_SC_VPORT_ZMAX_6'; + mmPA_SC_VPORT_ZMIN_7 :Result:='mmPA_SC_VPORT_ZMIN_7'; + mmPA_SC_VPORT_ZMAX_7 :Result:='mmPA_SC_VPORT_ZMAX_7'; + mmPA_SC_VPORT_ZMIN_8 :Result:='mmPA_SC_VPORT_ZMIN_8'; + mmPA_SC_VPORT_ZMAX_8 :Result:='mmPA_SC_VPORT_ZMAX_8'; + mmPA_SC_VPORT_ZMIN_9 :Result:='mmPA_SC_VPORT_ZMIN_9'; + mmPA_SC_VPORT_ZMAX_9 :Result:='mmPA_SC_VPORT_ZMAX_9'; + mmPA_SC_VPORT_ZMIN_10 :Result:='mmPA_SC_VPORT_ZMIN_10'; + mmPA_SC_VPORT_ZMAX_10 :Result:='mmPA_SC_VPORT_ZMAX_10'; + mmPA_SC_VPORT_ZMIN_11 :Result:='mmPA_SC_VPORT_ZMIN_11'; + mmPA_SC_VPORT_ZMAX_11 :Result:='mmPA_SC_VPORT_ZMAX_11'; + mmPA_SC_VPORT_ZMIN_12 :Result:='mmPA_SC_VPORT_ZMIN_12'; + mmPA_SC_VPORT_ZMAX_12 :Result:='mmPA_SC_VPORT_ZMAX_12'; + mmPA_SC_VPORT_ZMIN_13 :Result:='mmPA_SC_VPORT_ZMIN_13'; + mmPA_SC_VPORT_ZMAX_13 :Result:='mmPA_SC_VPORT_ZMAX_13'; + mmPA_SC_VPORT_ZMIN_14 :Result:='mmPA_SC_VPORT_ZMIN_14'; + mmPA_SC_VPORT_ZMAX_14 :Result:='mmPA_SC_VPORT_ZMAX_14'; + mmPA_SC_VPORT_ZMIN_15 :Result:='mmPA_SC_VPORT_ZMIN_15'; + mmPA_SC_VPORT_ZMAX_15 :Result:='mmPA_SC_VPORT_ZMAX_15'; + mmPA_SC_RASTER_CONFIG :Result:='mmPA_SC_RASTER_CONFIG'; + mmPA_SC_RASTER_CONFIG_1 :Result:='mmPA_SC_RASTER_CONFIG_1'; + mmCP_PERFMON_CNTX_CNTL :Result:='mmCP_PERFMON_CNTX_CNTL'; + mmCP_PIPEID :Result:='mmCP_PIPEID'; + mmCP_VMID :Result:='mmCP_VMID'; + mmVGT_MAX_VTX_INDX :Result:='mmVGT_MAX_VTX_INDX'; + mmVGT_MIN_VTX_INDX :Result:='mmVGT_MIN_VTX_INDX'; + mmVGT_INDX_OFFSET :Result:='mmVGT_INDX_OFFSET'; + mmVGT_MULTI_PRIM_IB_RESET_INDX :Result:='mmVGT_MULTI_PRIM_IB_RESET_INDX'; + mmCB_BLEND_RED :Result:='mmCB_BLEND_RED'; + mmCB_BLEND_GREEN :Result:='mmCB_BLEND_GREEN'; + mmCB_BLEND_BLUE :Result:='mmCB_BLEND_BLUE'; + mmCB_BLEND_ALPHA :Result:='mmCB_BLEND_ALPHA'; + mmCB_DCC_CONTROL :Result:='mmCB_DCC_CONTROL'; + mmDB_STENCIL_CONTROL :Result:='mmDB_STENCIL_CONTROL'; + mmDB_STENCILREFMASK :Result:='mmDB_STENCILREFMASK'; + mmDB_STENCILREFMASK_BF :Result:='mmDB_STENCILREFMASK_BF'; + mmPA_CL_VPORT_XSCALE :Result:='mmPA_CL_VPORT_XSCALE'; + mmPA_CL_VPORT_XOFFSET :Result:='mmPA_CL_VPORT_XOFFSET'; + mmPA_CL_VPORT_YSCALE :Result:='mmPA_CL_VPORT_YSCALE'; + mmPA_CL_VPORT_YOFFSET :Result:='mmPA_CL_VPORT_YOFFSET'; + mmPA_CL_VPORT_ZSCALE :Result:='mmPA_CL_VPORT_ZSCALE'; + mmPA_CL_VPORT_ZOFFSET :Result:='mmPA_CL_VPORT_ZOFFSET'; + mmPA_CL_VPORT_XSCALE_1 :Result:='mmPA_CL_VPORT_XSCALE_1'; + mmPA_CL_VPORT_XOFFSET_1 :Result:='mmPA_CL_VPORT_XOFFSET_1'; + mmPA_CL_VPORT_YSCALE_1 :Result:='mmPA_CL_VPORT_YSCALE_1'; + mmPA_CL_VPORT_YOFFSET_1 :Result:='mmPA_CL_VPORT_YOFFSET_1'; + mmPA_CL_VPORT_ZSCALE_1 :Result:='mmPA_CL_VPORT_ZSCALE_1'; + mmPA_CL_VPORT_ZOFFSET_1 :Result:='mmPA_CL_VPORT_ZOFFSET_1'; + mmPA_CL_VPORT_XSCALE_2 :Result:='mmPA_CL_VPORT_XSCALE_2'; + mmPA_CL_VPORT_XOFFSET_2 :Result:='mmPA_CL_VPORT_XOFFSET_2'; + mmPA_CL_VPORT_YSCALE_2 :Result:='mmPA_CL_VPORT_YSCALE_2'; + mmPA_CL_VPORT_YOFFSET_2 :Result:='mmPA_CL_VPORT_YOFFSET_2'; + mmPA_CL_VPORT_ZSCALE_2 :Result:='mmPA_CL_VPORT_ZSCALE_2'; + mmPA_CL_VPORT_ZOFFSET_2 :Result:='mmPA_CL_VPORT_ZOFFSET_2'; + mmPA_CL_VPORT_XSCALE_3 :Result:='mmPA_CL_VPORT_XSCALE_3'; + mmPA_CL_VPORT_XOFFSET_3 :Result:='mmPA_CL_VPORT_XOFFSET_3'; + mmPA_CL_VPORT_YSCALE_3 :Result:='mmPA_CL_VPORT_YSCALE_3'; + mmPA_CL_VPORT_YOFFSET_3 :Result:='mmPA_CL_VPORT_YOFFSET_3'; + mmPA_CL_VPORT_ZSCALE_3 :Result:='mmPA_CL_VPORT_ZSCALE_3'; + mmPA_CL_VPORT_ZOFFSET_3 :Result:='mmPA_CL_VPORT_ZOFFSET_3'; + mmPA_CL_VPORT_XSCALE_4 :Result:='mmPA_CL_VPORT_XSCALE_4'; + mmPA_CL_VPORT_XOFFSET_4 :Result:='mmPA_CL_VPORT_XOFFSET_4'; + mmPA_CL_VPORT_YSCALE_4 :Result:='mmPA_CL_VPORT_YSCALE_4'; + mmPA_CL_VPORT_YOFFSET_4 :Result:='mmPA_CL_VPORT_YOFFSET_4'; + mmPA_CL_VPORT_ZSCALE_4 :Result:='mmPA_CL_VPORT_ZSCALE_4'; + mmPA_CL_VPORT_ZOFFSET_4 :Result:='mmPA_CL_VPORT_ZOFFSET_4'; + mmPA_CL_VPORT_XSCALE_5 :Result:='mmPA_CL_VPORT_XSCALE_5'; + mmPA_CL_VPORT_XOFFSET_5 :Result:='mmPA_CL_VPORT_XOFFSET_5'; + mmPA_CL_VPORT_YSCALE_5 :Result:='mmPA_CL_VPORT_YSCALE_5'; + mmPA_CL_VPORT_YOFFSET_5 :Result:='mmPA_CL_VPORT_YOFFSET_5'; + mmPA_CL_VPORT_ZSCALE_5 :Result:='mmPA_CL_VPORT_ZSCALE_5'; + mmPA_CL_VPORT_ZOFFSET_5 :Result:='mmPA_CL_VPORT_ZOFFSET_5'; + mmPA_CL_VPORT_XSCALE_6 :Result:='mmPA_CL_VPORT_XSCALE_6'; + mmPA_CL_VPORT_XOFFSET_6 :Result:='mmPA_CL_VPORT_XOFFSET_6'; + mmPA_CL_VPORT_YSCALE_6 :Result:='mmPA_CL_VPORT_YSCALE_6'; + mmPA_CL_VPORT_YOFFSET_6 :Result:='mmPA_CL_VPORT_YOFFSET_6'; + mmPA_CL_VPORT_ZSCALE_6 :Result:='mmPA_CL_VPORT_ZSCALE_6'; + mmPA_CL_VPORT_ZOFFSET_6 :Result:='mmPA_CL_VPORT_ZOFFSET_6'; + mmPA_CL_VPORT_XSCALE_7 :Result:='mmPA_CL_VPORT_XSCALE_7'; + mmPA_CL_VPORT_XOFFSET_7 :Result:='mmPA_CL_VPORT_XOFFSET_7'; + mmPA_CL_VPORT_YSCALE_7 :Result:='mmPA_CL_VPORT_YSCALE_7'; + mmPA_CL_VPORT_YOFFSET_7 :Result:='mmPA_CL_VPORT_YOFFSET_7'; + mmPA_CL_VPORT_ZSCALE_7 :Result:='mmPA_CL_VPORT_ZSCALE_7'; + mmPA_CL_VPORT_ZOFFSET_7 :Result:='mmPA_CL_VPORT_ZOFFSET_7'; + mmPA_CL_VPORT_XSCALE_8 :Result:='mmPA_CL_VPORT_XSCALE_8'; + mmPA_CL_VPORT_XOFFSET_8 :Result:='mmPA_CL_VPORT_XOFFSET_8'; + mmPA_CL_VPORT_YSCALE_8 :Result:='mmPA_CL_VPORT_YSCALE_8'; + mmPA_CL_VPORT_YOFFSET_8 :Result:='mmPA_CL_VPORT_YOFFSET_8'; + mmPA_CL_VPORT_ZSCALE_8 :Result:='mmPA_CL_VPORT_ZSCALE_8'; + mmPA_CL_VPORT_ZOFFSET_8 :Result:='mmPA_CL_VPORT_ZOFFSET_8'; + mmPA_CL_VPORT_XSCALE_9 :Result:='mmPA_CL_VPORT_XSCALE_9'; + mmPA_CL_VPORT_XOFFSET_9 :Result:='mmPA_CL_VPORT_XOFFSET_9'; + mmPA_CL_VPORT_YSCALE_9 :Result:='mmPA_CL_VPORT_YSCALE_9'; + mmPA_CL_VPORT_YOFFSET_9 :Result:='mmPA_CL_VPORT_YOFFSET_9'; + mmPA_CL_VPORT_ZSCALE_9 :Result:='mmPA_CL_VPORT_ZSCALE_9'; + mmPA_CL_VPORT_ZOFFSET_9 :Result:='mmPA_CL_VPORT_ZOFFSET_9'; + mmPA_CL_VPORT_XSCALE_10 :Result:='mmPA_CL_VPORT_XSCALE_10'; + mmPA_CL_VPORT_XOFFSET_10 :Result:='mmPA_CL_VPORT_XOFFSET_10'; + mmPA_CL_VPORT_YSCALE_10 :Result:='mmPA_CL_VPORT_YSCALE_10'; + mmPA_CL_VPORT_YOFFSET_10 :Result:='mmPA_CL_VPORT_YOFFSET_10'; + mmPA_CL_VPORT_ZSCALE_10 :Result:='mmPA_CL_VPORT_ZSCALE_10'; + mmPA_CL_VPORT_ZOFFSET_10 :Result:='mmPA_CL_VPORT_ZOFFSET_10'; + mmPA_CL_VPORT_XSCALE_11 :Result:='mmPA_CL_VPORT_XSCALE_11'; + mmPA_CL_VPORT_XOFFSET_11 :Result:='mmPA_CL_VPORT_XOFFSET_11'; + mmPA_CL_VPORT_YSCALE_11 :Result:='mmPA_CL_VPORT_YSCALE_11'; + mmPA_CL_VPORT_YOFFSET_11 :Result:='mmPA_CL_VPORT_YOFFSET_11'; + mmPA_CL_VPORT_ZSCALE_11 :Result:='mmPA_CL_VPORT_ZSCALE_11'; + mmPA_CL_VPORT_ZOFFSET_11 :Result:='mmPA_CL_VPORT_ZOFFSET_11'; + mmPA_CL_VPORT_XSCALE_12 :Result:='mmPA_CL_VPORT_XSCALE_12'; + mmPA_CL_VPORT_XOFFSET_12 :Result:='mmPA_CL_VPORT_XOFFSET_12'; + mmPA_CL_VPORT_YSCALE_12 :Result:='mmPA_CL_VPORT_YSCALE_12'; + mmPA_CL_VPORT_YOFFSET_12 :Result:='mmPA_CL_VPORT_YOFFSET_12'; + mmPA_CL_VPORT_ZSCALE_12 :Result:='mmPA_CL_VPORT_ZSCALE_12'; + mmPA_CL_VPORT_ZOFFSET_12 :Result:='mmPA_CL_VPORT_ZOFFSET_12'; + mmPA_CL_VPORT_XSCALE_13 :Result:='mmPA_CL_VPORT_XSCALE_13'; + mmPA_CL_VPORT_XOFFSET_13 :Result:='mmPA_CL_VPORT_XOFFSET_13'; + mmPA_CL_VPORT_YSCALE_13 :Result:='mmPA_CL_VPORT_YSCALE_13'; + mmPA_CL_VPORT_YOFFSET_13 :Result:='mmPA_CL_VPORT_YOFFSET_13'; + mmPA_CL_VPORT_ZSCALE_13 :Result:='mmPA_CL_VPORT_ZSCALE_13'; + mmPA_CL_VPORT_ZOFFSET_13 :Result:='mmPA_CL_VPORT_ZOFFSET_13'; + mmPA_CL_VPORT_XSCALE_14 :Result:='mmPA_CL_VPORT_XSCALE_14'; + mmPA_CL_VPORT_XOFFSET_14 :Result:='mmPA_CL_VPORT_XOFFSET_14'; + mmPA_CL_VPORT_YSCALE_14 :Result:='mmPA_CL_VPORT_YSCALE_14'; + mmPA_CL_VPORT_YOFFSET_14 :Result:='mmPA_CL_VPORT_YOFFSET_14'; + mmPA_CL_VPORT_ZSCALE_14 :Result:='mmPA_CL_VPORT_ZSCALE_14'; + mmPA_CL_VPORT_ZOFFSET_14 :Result:='mmPA_CL_VPORT_ZOFFSET_14'; + mmPA_CL_VPORT_XSCALE_15 :Result:='mmPA_CL_VPORT_XSCALE_15'; + mmPA_CL_VPORT_XOFFSET_15 :Result:='mmPA_CL_VPORT_XOFFSET_15'; + mmPA_CL_VPORT_YSCALE_15 :Result:='mmPA_CL_VPORT_YSCALE_15'; + mmPA_CL_VPORT_YOFFSET_15 :Result:='mmPA_CL_VPORT_YOFFSET_15'; + mmPA_CL_VPORT_ZSCALE_15 :Result:='mmPA_CL_VPORT_ZSCALE_15'; + mmPA_CL_VPORT_ZOFFSET_15 :Result:='mmPA_CL_VPORT_ZOFFSET_15'; + mmPA_CL_UCP_0_X :Result:='mmPA_CL_UCP_0_X'; + mmPA_CL_UCP_0_Y :Result:='mmPA_CL_UCP_0_Y'; + mmPA_CL_UCP_0_Z :Result:='mmPA_CL_UCP_0_Z'; + mmPA_CL_UCP_0_W :Result:='mmPA_CL_UCP_0_W'; + mmPA_CL_UCP_1_X :Result:='mmPA_CL_UCP_1_X'; + mmPA_CL_UCP_1_Y :Result:='mmPA_CL_UCP_1_Y'; + mmPA_CL_UCP_1_Z :Result:='mmPA_CL_UCP_1_Z'; + mmPA_CL_UCP_1_W :Result:='mmPA_CL_UCP_1_W'; + mmPA_CL_UCP_2_X :Result:='mmPA_CL_UCP_2_X'; + mmPA_CL_UCP_2_Y :Result:='mmPA_CL_UCP_2_Y'; + mmPA_CL_UCP_2_Z :Result:='mmPA_CL_UCP_2_Z'; + mmPA_CL_UCP_2_W :Result:='mmPA_CL_UCP_2_W'; + mmPA_CL_UCP_3_X :Result:='mmPA_CL_UCP_3_X'; + mmPA_CL_UCP_3_Y :Result:='mmPA_CL_UCP_3_Y'; + mmPA_CL_UCP_3_Z :Result:='mmPA_CL_UCP_3_Z'; + mmPA_CL_UCP_3_W :Result:='mmPA_CL_UCP_3_W'; + mmPA_CL_UCP_4_X :Result:='mmPA_CL_UCP_4_X'; + mmPA_CL_UCP_4_Y :Result:='mmPA_CL_UCP_4_Y'; + mmPA_CL_UCP_4_Z :Result:='mmPA_CL_UCP_4_Z'; + mmPA_CL_UCP_4_W :Result:='mmPA_CL_UCP_4_W'; + mmPA_CL_UCP_5_X :Result:='mmPA_CL_UCP_5_X'; + mmPA_CL_UCP_5_Y :Result:='mmPA_CL_UCP_5_Y'; + mmPA_CL_UCP_5_Z :Result:='mmPA_CL_UCP_5_Z'; + mmPA_CL_UCP_5_W :Result:='mmPA_CL_UCP_5_W'; + mmSPI_PS_INPUT_CNTL_0 :Result:='mmSPI_PS_INPUT_CNTL_0'; + mmSPI_PS_INPUT_CNTL_1 :Result:='mmSPI_PS_INPUT_CNTL_1'; + mmSPI_PS_INPUT_CNTL_2 :Result:='mmSPI_PS_INPUT_CNTL_2'; + mmSPI_PS_INPUT_CNTL_3 :Result:='mmSPI_PS_INPUT_CNTL_3'; + mmSPI_PS_INPUT_CNTL_4 :Result:='mmSPI_PS_INPUT_CNTL_4'; + mmSPI_PS_INPUT_CNTL_5 :Result:='mmSPI_PS_INPUT_CNTL_5'; + mmSPI_PS_INPUT_CNTL_6 :Result:='mmSPI_PS_INPUT_CNTL_6'; + mmSPI_PS_INPUT_CNTL_7 :Result:='mmSPI_PS_INPUT_CNTL_7'; + mmSPI_PS_INPUT_CNTL_8 :Result:='mmSPI_PS_INPUT_CNTL_8'; + mmSPI_PS_INPUT_CNTL_9 :Result:='mmSPI_PS_INPUT_CNTL_9'; + mmSPI_PS_INPUT_CNTL_10 :Result:='mmSPI_PS_INPUT_CNTL_10'; + mmSPI_PS_INPUT_CNTL_11 :Result:='mmSPI_PS_INPUT_CNTL_11'; + mmSPI_PS_INPUT_CNTL_12 :Result:='mmSPI_PS_INPUT_CNTL_12'; + mmSPI_PS_INPUT_CNTL_13 :Result:='mmSPI_PS_INPUT_CNTL_13'; + mmSPI_PS_INPUT_CNTL_14 :Result:='mmSPI_PS_INPUT_CNTL_14'; + mmSPI_PS_INPUT_CNTL_15 :Result:='mmSPI_PS_INPUT_CNTL_15'; + mmSPI_PS_INPUT_CNTL_16 :Result:='mmSPI_PS_INPUT_CNTL_16'; + mmSPI_PS_INPUT_CNTL_17 :Result:='mmSPI_PS_INPUT_CNTL_17'; + mmSPI_PS_INPUT_CNTL_18 :Result:='mmSPI_PS_INPUT_CNTL_18'; + mmSPI_PS_INPUT_CNTL_19 :Result:='mmSPI_PS_INPUT_CNTL_19'; + mmSPI_PS_INPUT_CNTL_20 :Result:='mmSPI_PS_INPUT_CNTL_20'; + mmSPI_PS_INPUT_CNTL_21 :Result:='mmSPI_PS_INPUT_CNTL_21'; + mmSPI_PS_INPUT_CNTL_22 :Result:='mmSPI_PS_INPUT_CNTL_22'; + mmSPI_PS_INPUT_CNTL_23 :Result:='mmSPI_PS_INPUT_CNTL_23'; + mmSPI_PS_INPUT_CNTL_24 :Result:='mmSPI_PS_INPUT_CNTL_24'; + mmSPI_PS_INPUT_CNTL_25 :Result:='mmSPI_PS_INPUT_CNTL_25'; + mmSPI_PS_INPUT_CNTL_26 :Result:='mmSPI_PS_INPUT_CNTL_26'; + mmSPI_PS_INPUT_CNTL_27 :Result:='mmSPI_PS_INPUT_CNTL_27'; + mmSPI_PS_INPUT_CNTL_28 :Result:='mmSPI_PS_INPUT_CNTL_28'; + mmSPI_PS_INPUT_CNTL_29 :Result:='mmSPI_PS_INPUT_CNTL_29'; + mmSPI_PS_INPUT_CNTL_30 :Result:='mmSPI_PS_INPUT_CNTL_30'; + mmSPI_PS_INPUT_CNTL_31 :Result:='mmSPI_PS_INPUT_CNTL_31'; + mmSPI_VS_OUT_CONFIG :Result:='mmSPI_VS_OUT_CONFIG'; + mmSPI_PS_INPUT_ENA :Result:='mmSPI_PS_INPUT_ENA'; + mmSPI_PS_INPUT_ADDR :Result:='mmSPI_PS_INPUT_ADDR'; + mmSPI_INTERP_CONTROL_0 :Result:='mmSPI_INTERP_CONTROL_0'; + mmSPI_PS_IN_CONTROL :Result:='mmSPI_PS_IN_CONTROL'; + mmSPI_BARYC_CNTL :Result:='mmSPI_BARYC_CNTL'; + mmSPI_TMPRING_SIZE :Result:='mmSPI_TMPRING_SIZE'; + mmSPI_SHADER_POS_FORMAT :Result:='mmSPI_SHADER_POS_FORMAT'; + mmSPI_SHADER_Z_FORMAT :Result:='mmSPI_SHADER_Z_FORMAT'; + mmSPI_SHADER_COL_FORMAT :Result:='mmSPI_SHADER_COL_FORMAT'; + mmSX_PS_DOWNCONVERT :Result:='mmSX_PS_DOWNCONVERT'; + mmSX_BLEND_OPT_EPSILON :Result:='mmSX_BLEND_OPT_EPSILON'; + mmSX_BLEND_OPT_CONTROL :Result:='mmSX_BLEND_OPT_CONTROL'; + mmSX_MRT0_BLEND_OPT :Result:='mmSX_MRT0_BLEND_OPT'; + mmSX_MRT1_BLEND_OPT :Result:='mmSX_MRT1_BLEND_OPT'; + mmSX_MRT2_BLEND_OPT :Result:='mmSX_MRT2_BLEND_OPT'; + mmSX_MRT3_BLEND_OPT :Result:='mmSX_MRT3_BLEND_OPT'; + mmSX_MRT4_BLEND_OPT :Result:='mmSX_MRT4_BLEND_OPT'; + mmSX_MRT5_BLEND_OPT :Result:='mmSX_MRT5_BLEND_OPT'; + mmSX_MRT6_BLEND_OPT :Result:='mmSX_MRT6_BLEND_OPT'; + mmSX_MRT7_BLEND_OPT :Result:='mmSX_MRT7_BLEND_OPT'; + mmCB_BLEND0_CONTROL :Result:='mmCB_BLEND0_CONTROL'; + mmCB_BLEND1_CONTROL :Result:='mmCB_BLEND1_CONTROL'; + mmCB_BLEND2_CONTROL :Result:='mmCB_BLEND2_CONTROL'; + mmCB_BLEND3_CONTROL :Result:='mmCB_BLEND3_CONTROL'; + mmCB_BLEND4_CONTROL :Result:='mmCB_BLEND4_CONTROL'; + mmCB_BLEND5_CONTROL :Result:='mmCB_BLEND5_CONTROL'; + mmCB_BLEND6_CONTROL :Result:='mmCB_BLEND6_CONTROL'; + mmCB_BLEND7_CONTROL :Result:='mmCB_BLEND7_CONTROL'; + mmCS_COPY_STATE :Result:='mmCS_COPY_STATE'; + mmGFX_COPY_STATE :Result:='mmGFX_COPY_STATE'; + mmPA_CL_POINT_X_RAD :Result:='mmPA_CL_POINT_X_RAD'; + mmPA_CL_POINT_Y_RAD :Result:='mmPA_CL_POINT_Y_RAD'; + mmPA_CL_POINT_SIZE :Result:='mmPA_CL_POINT_SIZE'; + mmPA_CL_POINT_CULL_RAD :Result:='mmPA_CL_POINT_CULL_RAD'; + mmVGT_DMA_BASE_HI :Result:='mmVGT_DMA_BASE_HI'; + mmVGT_DMA_BASE :Result:='mmVGT_DMA_BASE'; + mmVGT_DRAW_INITIATOR :Result:='mmVGT_DRAW_INITIATOR'; + mmVGT_IMMED_DATA :Result:='mmVGT_IMMED_DATA'; + mmVGT_EVENT_ADDRESS_REG :Result:='mmVGT_EVENT_ADDRESS_REG'; + mmDB_DEPTH_CONTROL :Result:='mmDB_DEPTH_CONTROL'; + mmDB_EQAA :Result:='mmDB_EQAA'; + mmCB_COLOR_CONTROL :Result:='mmCB_COLOR_CONTROL'; + mmDB_SHADER_CONTROL :Result:='mmDB_SHADER_CONTROL'; + mmPA_CL_CLIP_CNTL :Result:='mmPA_CL_CLIP_CNTL'; + mmPA_SU_SC_MODE_CNTL :Result:='mmPA_SU_SC_MODE_CNTL'; + mmPA_CL_VTE_CNTL :Result:='mmPA_CL_VTE_CNTL'; + mmPA_CL_VS_OUT_CNTL :Result:='mmPA_CL_VS_OUT_CNTL'; + mmPA_CL_NANINF_CNTL :Result:='mmPA_CL_NANINF_CNTL'; + mmPA_SU_LINE_STIPPLE_CNTL :Result:='mmPA_SU_LINE_STIPPLE_CNTL'; + mmPA_SU_LINE_STIPPLE_SCALE :Result:='mmPA_SU_LINE_STIPPLE_SCALE'; + mmPA_SU_PRIM_FILTER_CNTL :Result:='mmPA_SU_PRIM_FILTER_CNTL'; + mmPA_SU_POINT_SIZE :Result:='mmPA_SU_POINT_SIZE'; + mmPA_SU_POINT_MINMAX :Result:='mmPA_SU_POINT_MINMAX'; + mmPA_SU_LINE_CNTL :Result:='mmPA_SU_LINE_CNTL'; + mmPA_SC_LINE_STIPPLE :Result:='mmPA_SC_LINE_STIPPLE'; + mmVGT_OUTPUT_PATH_CNTL :Result:='mmVGT_OUTPUT_PATH_CNTL'; + mmVGT_HOS_CNTL :Result:='mmVGT_HOS_CNTL'; + mmVGT_HOS_MAX_TESS_LEVEL :Result:='mmVGT_HOS_MAX_TESS_LEVEL'; + mmVGT_HOS_MIN_TESS_LEVEL :Result:='mmVGT_HOS_MIN_TESS_LEVEL'; + mmVGT_HOS_REUSE_DEPTH :Result:='mmVGT_HOS_REUSE_DEPTH'; + mmVGT_GROUP_PRIM_TYPE :Result:='mmVGT_GROUP_PRIM_TYPE'; + mmVGT_GROUP_FIRST_DECR :Result:='mmVGT_GROUP_FIRST_DECR'; + mmVGT_GROUP_DECR :Result:='mmVGT_GROUP_DECR'; + mmVGT_GROUP_VECT_0_CNTL :Result:='mmVGT_GROUP_VECT_0_CNTL'; + mmVGT_GROUP_VECT_1_CNTL :Result:='mmVGT_GROUP_VECT_1_CNTL'; + mmVGT_GROUP_VECT_0_FMT_CNTL :Result:='mmVGT_GROUP_VECT_0_FMT_CNTL'; + mmVGT_GROUP_VECT_1_FMT_CNTL :Result:='mmVGT_GROUP_VECT_1_FMT_CNTL'; + mmVGT_GS_MODE :Result:='mmVGT_GS_MODE'; + mmVGT_GS_ONCHIP_CNTL :Result:='mmVGT_GS_ONCHIP_CNTL'; + mmPA_SC_MODE_CNTL_0 :Result:='mmPA_SC_MODE_CNTL_0'; + mmPA_SC_MODE_CNTL_1 :Result:='mmPA_SC_MODE_CNTL_1'; + mmVGT_ENHANCE :Result:='mmVGT_ENHANCE'; + mmVGT_GS_PER_ES :Result:='mmVGT_GS_PER_ES'; + mmVGT_ES_PER_GS :Result:='mmVGT_ES_PER_GS'; + mmVGT_GS_PER_VS :Result:='mmVGT_GS_PER_VS'; + mmVGT_GSVS_RING_OFFSET_1 :Result:='mmVGT_GSVS_RING_OFFSET_1'; + mmVGT_GSVS_RING_OFFSET_2 :Result:='mmVGT_GSVS_RING_OFFSET_2'; + mmVGT_GSVS_RING_OFFSET_3 :Result:='mmVGT_GSVS_RING_OFFSET_3'; + mmVGT_GS_OUT_PRIM_TYPE :Result:='mmVGT_GS_OUT_PRIM_TYPE'; + mmIA_ENHANCE :Result:='mmIA_ENHANCE'; + mmVGT_DMA_SIZE :Result:='mmVGT_DMA_SIZE'; + mmVGT_DMA_MAX_SIZE :Result:='mmVGT_DMA_MAX_SIZE'; + mmVGT_DMA_INDEX_TYPE :Result:='mmVGT_DMA_INDEX_TYPE'; + mmWD_ENHANCE :Result:='mmWD_ENHANCE'; + mmVGT_PRIMITIVEID_EN :Result:='mmVGT_PRIMITIVEID_EN'; + mmVGT_DMA_NUM_INSTANCES :Result:='mmVGT_DMA_NUM_INSTANCES'; + mmVGT_PRIMITIVEID_RESET :Result:='mmVGT_PRIMITIVEID_RESET'; + mmVGT_EVENT_INITIATOR :Result:='mmVGT_EVENT_INITIATOR'; + mmVGT_MULTI_PRIM_IB_RESET_EN :Result:='mmVGT_MULTI_PRIM_IB_RESET_EN'; + mmVGT_INSTANCE_STEP_RATE_0 :Result:='mmVGT_INSTANCE_STEP_RATE_0'; + mmVGT_INSTANCE_STEP_RATE_1 :Result:='mmVGT_INSTANCE_STEP_RATE_1'; + mmIA_MULTI_VGT_PARAM :Result:='mmIA_MULTI_VGT_PARAM'; + mmVGT_ESGS_RING_ITEMSIZE :Result:='mmVGT_ESGS_RING_ITEMSIZE'; + mmVGT_GSVS_RING_ITEMSIZE :Result:='mmVGT_GSVS_RING_ITEMSIZE'; + mmVGT_REUSE_OFF :Result:='mmVGT_REUSE_OFF'; + mmVGT_VTX_CNT_EN :Result:='mmVGT_VTX_CNT_EN'; + mmDB_HTILE_SURFACE :Result:='mmDB_HTILE_SURFACE'; + mmDB_SRESULTS_COMPARE_STATE0 :Result:='mmDB_SRESULTS_COMPARE_STATE0'; + mmDB_SRESULTS_COMPARE_STATE1 :Result:='mmDB_SRESULTS_COMPARE_STATE1'; + mmDB_PRELOAD_CONTROL :Result:='mmDB_PRELOAD_CONTROL'; + mmVGT_STRMOUT_BUFFER_SIZE_0 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_0'; + mmVGT_STRMOUT_VTX_STRIDE_0 :Result:='mmVGT_STRMOUT_VTX_STRIDE_0'; + mmVGT_STRMOUT_BUFFER_OFFSET_0 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_0'; + mmVGT_STRMOUT_BUFFER_SIZE_1 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_1'; + mmVGT_STRMOUT_VTX_STRIDE_1 :Result:='mmVGT_STRMOUT_VTX_STRIDE_1'; + mmVGT_STRMOUT_BUFFER_OFFSET_1 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_1'; + mmVGT_STRMOUT_BUFFER_SIZE_2 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_2'; + mmVGT_STRMOUT_VTX_STRIDE_2 :Result:='mmVGT_STRMOUT_VTX_STRIDE_2'; + mmVGT_STRMOUT_BUFFER_OFFSET_2 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_2'; + mmVGT_STRMOUT_BUFFER_SIZE_3 :Result:='mmVGT_STRMOUT_BUFFER_SIZE_3'; + mmVGT_STRMOUT_VTX_STRIDE_3 :Result:='mmVGT_STRMOUT_VTX_STRIDE_3'; + mmVGT_STRMOUT_BUFFER_OFFSET_3 :Result:='mmVGT_STRMOUT_BUFFER_OFFSET_3'; + mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET'; + mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE'; + mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE :Result:='mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE'; + mmVGT_GS_MAX_VERT_OUT :Result:='mmVGT_GS_MAX_VERT_OUT'; + mmVGT_TESS_DISTRIBUTION :Result:='mmVGT_TESS_DISTRIBUTION'; + mmVGT_SHADER_STAGES_EN :Result:='mmVGT_SHADER_STAGES_EN'; + mmVGT_LS_HS_CONFIG :Result:='mmVGT_LS_HS_CONFIG'; + mmVGT_GS_VERT_ITEMSIZE :Result:='mmVGT_GS_VERT_ITEMSIZE'; + mmVGT_GS_VERT_ITEMSIZE_1 :Result:='mmVGT_GS_VERT_ITEMSIZE_1'; + mmVGT_GS_VERT_ITEMSIZE_2 :Result:='mmVGT_GS_VERT_ITEMSIZE_2'; + mmVGT_GS_VERT_ITEMSIZE_3 :Result:='mmVGT_GS_VERT_ITEMSIZE_3'; + mmVGT_TF_PARAM :Result:='mmVGT_TF_PARAM'; + mmDB_ALPHA_TO_MASK :Result:='mmDB_ALPHA_TO_MASK'; + mmVGT_DISPATCH_DRAW_INDEX :Result:='mmVGT_DISPATCH_DRAW_INDEX'; + mmPA_SU_POLY_OFFSET_DB_FMT_CNTL :Result:='mmPA_SU_POLY_OFFSET_DB_FMT_CNTL'; + mmPA_SU_POLY_OFFSET_CLAMP :Result:='mmPA_SU_POLY_OFFSET_CLAMP'; + mmPA_SU_POLY_OFFSET_FRONT_SCALE :Result:='mmPA_SU_POLY_OFFSET_FRONT_SCALE'; + mmPA_SU_POLY_OFFSET_FRONT_OFFSET :Result:='mmPA_SU_POLY_OFFSET_FRONT_OFFSET'; + mmPA_SU_POLY_OFFSET_BACK_SCALE :Result:='mmPA_SU_POLY_OFFSET_BACK_SCALE'; + mmPA_SU_POLY_OFFSET_BACK_OFFSET :Result:='mmPA_SU_POLY_OFFSET_BACK_OFFSET'; + mmVGT_GS_INSTANCE_CNT :Result:='mmVGT_GS_INSTANCE_CNT'; + mmVGT_STRMOUT_CONFIG :Result:='mmVGT_STRMOUT_CONFIG'; + mmVGT_STRMOUT_BUFFER_CONFIG :Result:='mmVGT_STRMOUT_BUFFER_CONFIG'; + mmPA_SC_CENTROID_PRIORITY_0 :Result:='mmPA_SC_CENTROID_PRIORITY_0'; + mmPA_SC_CENTROID_PRIORITY_1 :Result:='mmPA_SC_CENTROID_PRIORITY_1'; + mmPA_SC_LINE_CNTL :Result:='mmPA_SC_LINE_CNTL'; + mmPA_SC_AA_CONFIG :Result:='mmPA_SC_AA_CONFIG'; + mmPA_SU_VTX_CNTL :Result:='mmPA_SU_VTX_CNTL'; + mmPA_CL_GB_VERT_CLIP_ADJ :Result:='mmPA_CL_GB_VERT_CLIP_ADJ'; + mmPA_CL_GB_VERT_DISC_ADJ :Result:='mmPA_CL_GB_VERT_DISC_ADJ'; + mmPA_CL_GB_HORZ_CLIP_ADJ :Result:='mmPA_CL_GB_HORZ_CLIP_ADJ'; + mmPA_CL_GB_HORZ_DISC_ADJ :Result:='mmPA_CL_GB_HORZ_DISC_ADJ'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2'; + mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 :Result:='mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3'; + mmPA_SC_AA_MASK_X0Y0_X1Y0 :Result:='mmPA_SC_AA_MASK_X0Y0_X1Y0'; + mmPA_SC_AA_MASK_X0Y1_X1Y1 :Result:='mmPA_SC_AA_MASK_X0Y1_X1Y1'; + mmVGT_VERTEX_REUSE_BLOCK_CNTL :Result:='mmVGT_VERTEX_REUSE_BLOCK_CNTL'; + mmVGT_OUT_DEALLOC_CNTL :Result:='mmVGT_OUT_DEALLOC_CNTL'; + mmCB_COLOR0_BASE :Result:='mmCB_COLOR0_BASE'; + mmCB_COLOR0_PITCH :Result:='mmCB_COLOR0_PITCH'; + mmCB_COLOR0_SLICE :Result:='mmCB_COLOR0_SLICE'; + mmCB_COLOR0_VIEW :Result:='mmCB_COLOR0_VIEW'; + mmCB_COLOR0_INFO :Result:='mmCB_COLOR0_INFO'; + mmCB_COLOR0_ATTRIB :Result:='mmCB_COLOR0_ATTRIB'; + mmCB_COLOR0_DCC_CONTROL :Result:='mmCB_COLOR0_DCC_CONTROL'; + mmCB_COLOR0_CMASK :Result:='mmCB_COLOR0_CMASK'; + mmCB_COLOR0_CMASK_SLICE :Result:='mmCB_COLOR0_CMASK_SLICE'; + mmCB_COLOR0_FMASK :Result:='mmCB_COLOR0_FMASK'; + mmCB_COLOR0_FMASK_SLICE :Result:='mmCB_COLOR0_FMASK_SLICE'; + mmCB_COLOR0_CLEAR_WORD0 :Result:='mmCB_COLOR0_CLEAR_WORD0'; + mmCB_COLOR0_CLEAR_WORD1 :Result:='mmCB_COLOR0_CLEAR_WORD1'; + mmCB_COLOR0_DCC_BASE :Result:='mmCB_COLOR0_DCC_BASE'; + mmCB_COLOR1_BASE :Result:='mmCB_COLOR1_BASE'; + mmCB_COLOR1_PITCH :Result:='mmCB_COLOR1_PITCH'; + mmCB_COLOR1_SLICE :Result:='mmCB_COLOR1_SLICE'; + mmCB_COLOR1_VIEW :Result:='mmCB_COLOR1_VIEW'; + mmCB_COLOR1_INFO :Result:='mmCB_COLOR1_INFO'; + mmCB_COLOR1_ATTRIB :Result:='mmCB_COLOR1_ATTRIB'; + mmCB_COLOR1_DCC_CONTROL :Result:='mmCB_COLOR1_DCC_CONTROL'; + mmCB_COLOR1_CMASK :Result:='mmCB_COLOR1_CMASK'; + mmCB_COLOR1_CMASK_SLICE :Result:='mmCB_COLOR1_CMASK_SLICE'; + mmCB_COLOR1_FMASK :Result:='mmCB_COLOR1_FMASK'; + mmCB_COLOR1_FMASK_SLICE :Result:='mmCB_COLOR1_FMASK_SLICE'; + mmCB_COLOR1_CLEAR_WORD0 :Result:='mmCB_COLOR1_CLEAR_WORD0'; + mmCB_COLOR1_CLEAR_WORD1 :Result:='mmCB_COLOR1_CLEAR_WORD1'; + mmCB_COLOR1_DCC_BASE :Result:='mmCB_COLOR1_DCC_BASE'; + mmCB_COLOR2_BASE :Result:='mmCB_COLOR2_BASE'; + mmCB_COLOR2_PITCH :Result:='mmCB_COLOR2_PITCH'; + mmCB_COLOR2_SLICE :Result:='mmCB_COLOR2_SLICE'; + mmCB_COLOR2_VIEW :Result:='mmCB_COLOR2_VIEW'; + mmCB_COLOR2_INFO :Result:='mmCB_COLOR2_INFO'; + mmCB_COLOR2_ATTRIB :Result:='mmCB_COLOR2_ATTRIB'; + mmCB_COLOR2_DCC_CONTROL :Result:='mmCB_COLOR2_DCC_CONTROL'; + mmCB_COLOR2_CMASK :Result:='mmCB_COLOR2_CMASK'; + mmCB_COLOR2_CMASK_SLICE :Result:='mmCB_COLOR2_CMASK_SLICE'; + mmCB_COLOR2_FMASK :Result:='mmCB_COLOR2_FMASK'; + mmCB_COLOR2_FMASK_SLICE :Result:='mmCB_COLOR2_FMASK_SLICE'; + mmCB_COLOR2_CLEAR_WORD0 :Result:='mmCB_COLOR2_CLEAR_WORD0'; + mmCB_COLOR2_CLEAR_WORD1 :Result:='mmCB_COLOR2_CLEAR_WORD1'; + mmCB_COLOR2_DCC_BASE :Result:='mmCB_COLOR2_DCC_BASE'; + mmCB_COLOR3_BASE :Result:='mmCB_COLOR3_BASE'; + mmCB_COLOR3_PITCH :Result:='mmCB_COLOR3_PITCH'; + mmCB_COLOR3_SLICE :Result:='mmCB_COLOR3_SLICE'; + mmCB_COLOR3_VIEW :Result:='mmCB_COLOR3_VIEW'; + mmCB_COLOR3_INFO :Result:='mmCB_COLOR3_INFO'; + mmCB_COLOR3_ATTRIB :Result:='mmCB_COLOR3_ATTRIB'; + mmCB_COLOR3_DCC_CONTROL :Result:='mmCB_COLOR3_DCC_CONTROL'; + mmCB_COLOR3_CMASK :Result:='mmCB_COLOR3_CMASK'; + mmCB_COLOR3_CMASK_SLICE :Result:='mmCB_COLOR3_CMASK_SLICE'; + mmCB_COLOR3_FMASK :Result:='mmCB_COLOR3_FMASK'; + mmCB_COLOR3_FMASK_SLICE :Result:='mmCB_COLOR3_FMASK_SLICE'; + mmCB_COLOR3_CLEAR_WORD0 :Result:='mmCB_COLOR3_CLEAR_WORD0'; + mmCB_COLOR3_CLEAR_WORD1 :Result:='mmCB_COLOR3_CLEAR_WORD1'; + mmCB_COLOR3_DCC_BASE :Result:='mmCB_COLOR3_DCC_BASE'; + mmCB_COLOR4_BASE :Result:='mmCB_COLOR4_BASE'; + mmCB_COLOR4_PITCH :Result:='mmCB_COLOR4_PITCH'; + mmCB_COLOR4_SLICE :Result:='mmCB_COLOR4_SLICE'; + mmCB_COLOR4_VIEW :Result:='mmCB_COLOR4_VIEW'; + mmCB_COLOR4_INFO :Result:='mmCB_COLOR4_INFO'; + mmCB_COLOR4_ATTRIB :Result:='mmCB_COLOR4_ATTRIB'; + mmCB_COLOR4_DCC_CONTROL :Result:='mmCB_COLOR4_DCC_CONTROL'; + mmCB_COLOR4_CMASK :Result:='mmCB_COLOR4_CMASK'; + mmCB_COLOR4_CMASK_SLICE :Result:='mmCB_COLOR4_CMASK_SLICE'; + mmCB_COLOR4_FMASK :Result:='mmCB_COLOR4_FMASK'; + mmCB_COLOR4_FMASK_SLICE :Result:='mmCB_COLOR4_FMASK_SLICE'; + mmCB_COLOR4_CLEAR_WORD0 :Result:='mmCB_COLOR4_CLEAR_WORD0'; + mmCB_COLOR4_CLEAR_WORD1 :Result:='mmCB_COLOR4_CLEAR_WORD1'; + mmCB_COLOR4_DCC_BASE :Result:='mmCB_COLOR4_DCC_BASE'; + mmCB_COLOR5_BASE :Result:='mmCB_COLOR5_BASE'; + mmCB_COLOR5_PITCH :Result:='mmCB_COLOR5_PITCH'; + mmCB_COLOR5_SLICE :Result:='mmCB_COLOR5_SLICE'; + mmCB_COLOR5_VIEW :Result:='mmCB_COLOR5_VIEW'; + mmCB_COLOR5_INFO :Result:='mmCB_COLOR5_INFO'; + mmCB_COLOR5_ATTRIB :Result:='mmCB_COLOR5_ATTRIB'; + mmCB_COLOR5_DCC_CONTROL :Result:='mmCB_COLOR5_DCC_CONTROL'; + mmCB_COLOR5_CMASK :Result:='mmCB_COLOR5_CMASK'; + mmCB_COLOR5_CMASK_SLICE :Result:='mmCB_COLOR5_CMASK_SLICE'; + mmCB_COLOR5_FMASK :Result:='mmCB_COLOR5_FMASK'; + mmCB_COLOR5_FMASK_SLICE :Result:='mmCB_COLOR5_FMASK_SLICE'; + mmCB_COLOR5_CLEAR_WORD0 :Result:='mmCB_COLOR5_CLEAR_WORD0'; + mmCB_COLOR5_CLEAR_WORD1 :Result:='mmCB_COLOR5_CLEAR_WORD1'; + mmCB_COLOR5_DCC_BASE :Result:='mmCB_COLOR5_DCC_BASE'; + mmCB_COLOR6_BASE :Result:='mmCB_COLOR6_BASE'; + mmCB_COLOR6_PITCH :Result:='mmCB_COLOR6_PITCH'; + mmCB_COLOR6_SLICE :Result:='mmCB_COLOR6_SLICE'; + mmCB_COLOR6_VIEW :Result:='mmCB_COLOR6_VIEW'; + mmCB_COLOR6_INFO :Result:='mmCB_COLOR6_INFO'; + mmCB_COLOR6_ATTRIB :Result:='mmCB_COLOR6_ATTRIB'; + mmCB_COLOR6_DCC_CONTROL :Result:='mmCB_COLOR6_DCC_CONTROL'; + mmCB_COLOR6_CMASK :Result:='mmCB_COLOR6_CMASK'; + mmCB_COLOR6_CMASK_SLICE :Result:='mmCB_COLOR6_CMASK_SLICE'; + mmCB_COLOR6_FMASK :Result:='mmCB_COLOR6_FMASK'; + mmCB_COLOR6_FMASK_SLICE :Result:='mmCB_COLOR6_FMASK_SLICE'; + mmCB_COLOR6_CLEAR_WORD0 :Result:='mmCB_COLOR6_CLEAR_WORD0'; + mmCB_COLOR6_CLEAR_WORD1 :Result:='mmCB_COLOR6_CLEAR_WORD1'; + mmCB_COLOR6_DCC_BASE :Result:='mmCB_COLOR6_DCC_BASE'; + mmCB_COLOR7_BASE :Result:='mmCB_COLOR7_BASE'; + mmCB_COLOR7_PITCH :Result:='mmCB_COLOR7_PITCH'; + mmCB_COLOR7_SLICE :Result:='mmCB_COLOR7_SLICE'; + mmCB_COLOR7_VIEW :Result:='mmCB_COLOR7_VIEW'; + mmCB_COLOR7_INFO :Result:='mmCB_COLOR7_INFO'; + mmCB_COLOR7_ATTRIB :Result:='mmCB_COLOR7_ATTRIB'; + mmCB_COLOR7_DCC_CONTROL :Result:='mmCB_COLOR7_DCC_CONTROL'; + mmCB_COLOR7_CMASK :Result:='mmCB_COLOR7_CMASK'; + mmCB_COLOR7_CMASK_SLICE :Result:='mmCB_COLOR7_CMASK_SLICE'; + mmCB_COLOR7_FMASK :Result:='mmCB_COLOR7_FMASK'; + mmCB_COLOR7_FMASK_SLICE :Result:='mmCB_COLOR7_FMASK_SLICE'; + mmCB_COLOR7_CLEAR_WORD0 :Result:='mmCB_COLOR7_CLEAR_WORD0'; + mmCB_COLOR7_CLEAR_WORD1 :Result:='mmCB_COLOR7_CLEAR_WORD1'; + mmCB_COLOR7_DCC_BASE :Result:='mmCB_COLOR7_DCC_BASE'; + mmCP_EOP_DONE_ADDR_LO :Result:='mmCP_EOP_DONE_ADDR_LO'; + mmCP_EOP_DONE_ADDR_HI :Result:='mmCP_EOP_DONE_ADDR_HI'; + mmCP_EOP_DONE_DATA_LO :Result:='mmCP_EOP_DONE_DATA_LO'; + mmCP_EOP_DONE_DATA_HI :Result:='mmCP_EOP_DONE_DATA_HI'; + mmCP_EOP_LAST_FENCE_LO :Result:='mmCP_EOP_LAST_FENCE_LO'; + mmCP_EOP_LAST_FENCE_HI :Result:='mmCP_EOP_LAST_FENCE_HI'; + mmCP_STREAM_OUT_ADDR_LO :Result:='mmCP_STREAM_OUT_ADDR_LO'; + mmCP_STREAM_OUT_ADDR_HI :Result:='mmCP_STREAM_OUT_ADDR_HI'; + mmCP_NUM_PRIM_WRITTEN_COUNT0_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_LO'; + mmCP_NUM_PRIM_WRITTEN_COUNT0_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT0_HI'; + mmCP_NUM_PRIM_NEEDED_COUNT0_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_LO'; + mmCP_NUM_PRIM_NEEDED_COUNT0_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT0_HI'; + mmCP_NUM_PRIM_WRITTEN_COUNT1_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_LO'; + mmCP_NUM_PRIM_WRITTEN_COUNT1_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT1_HI'; + mmCP_NUM_PRIM_NEEDED_COUNT1_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_LO'; + mmCP_NUM_PRIM_NEEDED_COUNT1_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT1_HI'; + mmCP_NUM_PRIM_WRITTEN_COUNT2_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_LO'; + mmCP_NUM_PRIM_WRITTEN_COUNT2_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT2_HI'; + mmCP_NUM_PRIM_NEEDED_COUNT2_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_LO'; + mmCP_NUM_PRIM_NEEDED_COUNT2_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT2_HI'; + mmCP_NUM_PRIM_WRITTEN_COUNT3_LO :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_LO'; + mmCP_NUM_PRIM_WRITTEN_COUNT3_HI :Result:='mmCP_NUM_PRIM_WRITTEN_COUNT3_HI'; + mmCP_NUM_PRIM_NEEDED_COUNT3_LO :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_LO'; + mmCP_NUM_PRIM_NEEDED_COUNT3_HI :Result:='mmCP_NUM_PRIM_NEEDED_COUNT3_HI'; + mmCP_PIPE_STATS_ADDR_LO :Result:='mmCP_PIPE_STATS_ADDR_LO'; + mmCP_PIPE_STATS_ADDR_HI :Result:='mmCP_PIPE_STATS_ADDR_HI'; + mmCP_VGT_IAVERT_COUNT_LO :Result:='mmCP_VGT_IAVERT_COUNT_LO'; + mmCP_VGT_IAVERT_COUNT_HI :Result:='mmCP_VGT_IAVERT_COUNT_HI'; + mmCP_VGT_IAPRIM_COUNT_LO :Result:='mmCP_VGT_IAPRIM_COUNT_LO'; + mmCP_VGT_IAPRIM_COUNT_HI :Result:='mmCP_VGT_IAPRIM_COUNT_HI'; + mmCP_VGT_GSPRIM_COUNT_LO :Result:='mmCP_VGT_GSPRIM_COUNT_LO'; + mmCP_VGT_GSPRIM_COUNT_HI :Result:='mmCP_VGT_GSPRIM_COUNT_HI'; + mmCP_VGT_VSINVOC_COUNT_LO :Result:='mmCP_VGT_VSINVOC_COUNT_LO'; + mmCP_VGT_VSINVOC_COUNT_HI :Result:='mmCP_VGT_VSINVOC_COUNT_HI'; + mmCP_VGT_GSINVOC_COUNT_LO :Result:='mmCP_VGT_GSINVOC_COUNT_LO'; + mmCP_VGT_GSINVOC_COUNT_HI :Result:='mmCP_VGT_GSINVOC_COUNT_HI'; + mmCP_VGT_HSINVOC_COUNT_LO :Result:='mmCP_VGT_HSINVOC_COUNT_LO'; + mmCP_VGT_HSINVOC_COUNT_HI :Result:='mmCP_VGT_HSINVOC_COUNT_HI'; + mmCP_VGT_DSINVOC_COUNT_LO :Result:='mmCP_VGT_DSINVOC_COUNT_LO'; + mmCP_VGT_DSINVOC_COUNT_HI :Result:='mmCP_VGT_DSINVOC_COUNT_HI'; + mmCP_PA_CINVOC_COUNT_LO :Result:='mmCP_PA_CINVOC_COUNT_LO'; + mmCP_PA_CINVOC_COUNT_HI :Result:='mmCP_PA_CINVOC_COUNT_HI'; + mmCP_PA_CPRIM_COUNT_LO :Result:='mmCP_PA_CPRIM_COUNT_LO'; + mmCP_PA_CPRIM_COUNT_HI :Result:='mmCP_PA_CPRIM_COUNT_HI'; + mmCP_SC_PSINVOC_COUNT0_LO :Result:='mmCP_SC_PSINVOC_COUNT0_LO'; + mmCP_SC_PSINVOC_COUNT0_HI :Result:='mmCP_SC_PSINVOC_COUNT0_HI'; + mmCP_SC_PSINVOC_COUNT1_LO :Result:='mmCP_SC_PSINVOC_COUNT1_LO'; + mmCP_SC_PSINVOC_COUNT1_HI :Result:='mmCP_SC_PSINVOC_COUNT1_HI'; + mmCP_VGT_CSINVOC_COUNT_LO :Result:='mmCP_VGT_CSINVOC_COUNT_LO'; + mmCP_VGT_CSINVOC_COUNT_HI :Result:='mmCP_VGT_CSINVOC_COUNT_HI'; + mmCP_PIPE_STATS_CONTROL :Result:='mmCP_PIPE_STATS_CONTROL'; + mmCP_STREAM_OUT_CONTROL :Result:='mmCP_STREAM_OUT_CONTROL'; + mmCP_STRMOUT_CNTL :Result:='mmCP_STRMOUT_CNTL'; + mmSCRATCH_REG0 :Result:='mmSCRATCH_REG0'; + mmSCRATCH_REG1 :Result:='mmSCRATCH_REG1'; + mmSCRATCH_REG2 :Result:='mmSCRATCH_REG2'; + mmSCRATCH_REG3 :Result:='mmSCRATCH_REG3'; + mmSCRATCH_REG4 :Result:='mmSCRATCH_REG4'; + mmSCRATCH_REG5 :Result:='mmSCRATCH_REG5'; + mmSCRATCH_REG6 :Result:='mmSCRATCH_REG6'; + mmSCRATCH_REG7 :Result:='mmSCRATCH_REG7'; + mmSCRATCH_UMSK :Result:='mmSCRATCH_UMSK'; + mmSCRATCH_ADDR :Result:='mmSCRATCH_ADDR'; + mmCP_PFP_ATOMIC_PREOP_LO :Result:='mmCP_PFP_ATOMIC_PREOP_LO'; + mmCP_PFP_ATOMIC_PREOP_HI :Result:='mmCP_PFP_ATOMIC_PREOP_HI'; + mmCP_PFP_GDS_ATOMIC0_PREOP_LO :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_LO'; + mmCP_PFP_GDS_ATOMIC0_PREOP_HI :Result:='mmCP_PFP_GDS_ATOMIC0_PREOP_HI'; + mmCP_PFP_GDS_ATOMIC1_PREOP_LO :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_LO'; + mmCP_PFP_GDS_ATOMIC1_PREOP_HI :Result:='mmCP_PFP_GDS_ATOMIC1_PREOP_HI'; + mmCP_APPEND_ADDR_LO :Result:='mmCP_APPEND_ADDR_LO'; + mmCP_APPEND_ADDR_HI :Result:='mmCP_APPEND_ADDR_HI'; + mmCP_APPEND_DATA :Result:='mmCP_APPEND_DATA'; + mmCP_APPEND_LAST_CS_FENCE :Result:='mmCP_APPEND_LAST_CS_FENCE'; + mmCP_APPEND_LAST_PS_FENCE :Result:='mmCP_APPEND_LAST_PS_FENCE'; + mmCP_ATOMIC_PREOP_LO :Result:='mmCP_ATOMIC_PREOP_LO'; + mmCP_ATOMIC_PREOP_HI :Result:='mmCP_ATOMIC_PREOP_HI'; + mmCP_GDS_ATOMIC0_PREOP_LO :Result:='mmCP_GDS_ATOMIC0_PREOP_LO'; + mmCP_GDS_ATOMIC0_PREOP_HI :Result:='mmCP_GDS_ATOMIC0_PREOP_HI'; + mmCP_GDS_ATOMIC1_PREOP_LO :Result:='mmCP_GDS_ATOMIC1_PREOP_LO'; + mmCP_GDS_ATOMIC1_PREOP_HI :Result:='mmCP_GDS_ATOMIC1_PREOP_HI'; + mmCP_ME_MC_WADDR_LO :Result:='mmCP_ME_MC_WADDR_LO'; + mmCP_ME_MC_WADDR_HI :Result:='mmCP_ME_MC_WADDR_HI'; + mmCP_ME_MC_WDATA_LO :Result:='mmCP_ME_MC_WDATA_LO'; + mmCP_ME_MC_WDATA_HI :Result:='mmCP_ME_MC_WDATA_HI'; + mmCP_ME_MC_RADDR_LO :Result:='mmCP_ME_MC_RADDR_LO'; + mmCP_ME_MC_RADDR_HI :Result:='mmCP_ME_MC_RADDR_HI'; + mmCP_SEM_WAIT_TIMER :Result:='mmCP_SEM_WAIT_TIMER'; + mmCP_SIG_SEM_ADDR_LO :Result:='mmCP_SIG_SEM_ADDR_LO'; + mmCP_SIG_SEM_ADDR_HI :Result:='mmCP_SIG_SEM_ADDR_HI'; + mmCP_WAIT_REG_MEM_TIMEOUT :Result:='mmCP_WAIT_REG_MEM_TIMEOUT'; + mmCP_WAIT_SEM_ADDR_LO :Result:='mmCP_WAIT_SEM_ADDR_LO'; + mmCP_WAIT_SEM_ADDR_HI :Result:='mmCP_WAIT_SEM_ADDR_HI'; + mmCP_DMA_PFP_CONTROL :Result:='mmCP_DMA_PFP_CONTROL'; + mmCP_DMA_ME_CONTROL :Result:='mmCP_DMA_ME_CONTROL'; + mmCP_COHER_BASE_HI :Result:='mmCP_COHER_BASE_HI'; + mmCP_COHER_START_DELAY :Result:='mmCP_COHER_START_DELAY'; + mmCP_COHER_CNTL :Result:='mmCP_COHER_CNTL'; + mmCP_COHER_SIZE :Result:='mmCP_COHER_SIZE'; + mmCP_COHER_BASE :Result:='mmCP_COHER_BASE'; + mmCP_COHER_STATUS :Result:='mmCP_COHER_STATUS'; + mmCP_DMA_ME_SRC_ADDR :Result:='mmCP_DMA_ME_SRC_ADDR'; + mmCP_DMA_ME_SRC_ADDR_HI :Result:='mmCP_DMA_ME_SRC_ADDR_HI'; + mmCP_DMA_ME_DST_ADDR :Result:='mmCP_DMA_ME_DST_ADDR'; + mmCP_DMA_ME_DST_ADDR_HI :Result:='mmCP_DMA_ME_DST_ADDR_HI'; + mmCP_DMA_ME_COMMAND :Result:='mmCP_DMA_ME_COMMAND'; + mmCP_DMA_PFP_SRC_ADDR :Result:='mmCP_DMA_PFP_SRC_ADDR'; + mmCP_DMA_PFP_SRC_ADDR_HI :Result:='mmCP_DMA_PFP_SRC_ADDR_HI'; + mmCP_DMA_PFP_DST_ADDR :Result:='mmCP_DMA_PFP_DST_ADDR'; + mmCP_DMA_PFP_DST_ADDR_HI :Result:='mmCP_DMA_PFP_DST_ADDR_HI'; + mmCP_DMA_PFP_COMMAND :Result:='mmCP_DMA_PFP_COMMAND'; + mmCP_DMA_CNTL :Result:='mmCP_DMA_CNTL'; + mmCP_DMA_READ_TAGS :Result:='mmCP_DMA_READ_TAGS'; + mmCP_COHER_SIZE_HI :Result:='mmCP_COHER_SIZE_HI'; + mmCP_PFP_IB_CONTROL :Result:='mmCP_PFP_IB_CONTROL'; + mmCP_PFP_LOAD_CONTROL :Result:='mmCP_PFP_LOAD_CONTROL'; + mmCP_SCRATCH_INDEX :Result:='mmCP_SCRATCH_INDEX'; + mmCP_SCRATCH_DATA :Result:='mmCP_SCRATCH_DATA'; + mmCP_RB_OFFSET :Result:='mmCP_RB_OFFSET'; + mmCP_IB1_OFFSET :Result:='mmCP_IB1_OFFSET'; + mmCP_IB2_OFFSET :Result:='mmCP_IB2_OFFSET'; + mmCP_IB1_PREAMBLE_BEGIN :Result:='mmCP_IB1_PREAMBLE_BEGIN'; + mmCP_IB1_PREAMBLE_END :Result:='mmCP_IB1_PREAMBLE_END'; + mmCP_IB2_PREAMBLE_BEGIN :Result:='mmCP_IB2_PREAMBLE_BEGIN'; + mmCP_IB2_PREAMBLE_END :Result:='mmCP_IB2_PREAMBLE_END'; + mmCP_CE_IB1_OFFSET :Result:='mmCP_CE_IB1_OFFSET'; + mmCP_CE_IB2_OFFSET :Result:='mmCP_CE_IB2_OFFSET'; + mmCP_CE_COUNTER :Result:='mmCP_CE_COUNTER'; + mmCP_CE_RB_OFFSET :Result:='mmCP_CE_RB_OFFSET'; + mmCP_CE_INIT_BASE_LO :Result:='mmCP_CE_INIT_BASE_LO'; + mmCP_CE_INIT_BASE_HI :Result:='mmCP_CE_INIT_BASE_HI'; + mmCP_CE_INIT_BUFSZ :Result:='mmCP_CE_INIT_BUFSZ'; + mmCP_CE_IB1_BASE_LO :Result:='mmCP_CE_IB1_BASE_LO'; + mmCP_CE_IB1_BASE_HI :Result:='mmCP_CE_IB1_BASE_HI'; + mmCP_CE_IB1_BUFSZ :Result:='mmCP_CE_IB1_BUFSZ'; + mmCP_CE_IB2_BASE_LO :Result:='mmCP_CE_IB2_BASE_LO'; + mmCP_CE_IB2_BASE_HI :Result:='mmCP_CE_IB2_BASE_HI'; + mmCP_CE_IB2_BUFSZ :Result:='mmCP_CE_IB2_BUFSZ'; + mmCP_IB1_BASE_LO :Result:='mmCP_IB1_BASE_LO'; + mmCP_IB1_BASE_HI :Result:='mmCP_IB1_BASE_HI'; + mmCP_IB1_BUFSZ :Result:='mmCP_IB1_BUFSZ'; + mmCP_IB2_BASE_LO :Result:='mmCP_IB2_BASE_LO'; + mmCP_IB2_BASE_HI :Result:='mmCP_IB2_BASE_HI'; + mmCP_IB2_BUFSZ :Result:='mmCP_IB2_BUFSZ'; + mmCP_ST_BASE_LO :Result:='mmCP_ST_BASE_LO'; + mmCP_ST_BASE_HI :Result:='mmCP_ST_BASE_HI'; + mmCP_ST_BUFSZ :Result:='mmCP_ST_BUFSZ'; + mmCP_EOP_DONE_EVENT_CNTL :Result:='mmCP_EOP_DONE_EVENT_CNTL'; + mmCP_EOP_DONE_DATA_CNTL :Result:='mmCP_EOP_DONE_DATA_CNTL'; + mmCP_EOP_DONE_CNTX_ID :Result:='mmCP_EOP_DONE_CNTX_ID'; + mmCP_PFP_COMPLETION_STATUS :Result:='mmCP_PFP_COMPLETION_STATUS'; + mmCP_CE_COMPLETION_STATUS :Result:='mmCP_CE_COMPLETION_STATUS'; + mmCP_PRED_NOT_VISIBLE :Result:='mmCP_PRED_NOT_VISIBLE'; + mmCP_PFP_METADATA_BASE_ADDR :Result:='mmCP_PFP_METADATA_BASE_ADDR'; + mmCP_PFP_METADATA_BASE_ADDR_HI :Result:='mmCP_PFP_METADATA_BASE_ADDR_HI'; + mmCP_CE_METADATA_BASE_ADDR :Result:='mmCP_CE_METADATA_BASE_ADDR'; + mmCP_CE_METADATA_BASE_ADDR_HI :Result:='mmCP_CE_METADATA_BASE_ADDR_HI'; + mmCP_DRAW_INDX_INDR_ADDR :Result:='mmCP_DRAW_INDX_INDR_ADDR'; + mmCP_DRAW_INDX_INDR_ADDR_HI :Result:='mmCP_DRAW_INDX_INDR_ADDR_HI'; + mmCP_DISPATCH_INDR_ADDR :Result:='mmCP_DISPATCH_INDR_ADDR'; + mmCP_DISPATCH_INDR_ADDR_HI :Result:='mmCP_DISPATCH_INDR_ADDR_HI'; + mmCP_INDEX_BASE_ADDR :Result:='mmCP_INDEX_BASE_ADDR'; + mmCP_INDEX_BASE_ADDR_HI :Result:='mmCP_INDEX_BASE_ADDR_HI'; + mmCP_INDEX_TYPE :Result:='mmCP_INDEX_TYPE'; + mmCP_GDS_BKUP_ADDR :Result:='mmCP_GDS_BKUP_ADDR'; + mmCP_GDS_BKUP_ADDR_HI :Result:='mmCP_GDS_BKUP_ADDR_HI'; + mmCP_SAMPLE_STATUS :Result:='mmCP_SAMPLE_STATUS'; + mmGRBM_GFX_INDEX :Result:='mmGRBM_GFX_INDEX'; + mmVGT_ESGS_RING_SIZE :Result:='mmVGT_ESGS_RING_SIZE'; + mmVGT_GSVS_RING_SIZE :Result:='mmVGT_GSVS_RING_SIZE'; + mmVGT_PRIMITIVE_TYPE :Result:='mmVGT_PRIMITIVE_TYPE'; + mmVGT_INDEX_TYPE :Result:='mmVGT_INDEX_TYPE'; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0'; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1'; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2'; + mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 :Result:='mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3'; + mmVGT_NUM_INDICES :Result:='mmVGT_NUM_INDICES'; + mmVGT_NUM_INSTANCES :Result:='mmVGT_NUM_INSTANCES'; + mmVGT_TF_RING_SIZE :Result:='mmVGT_TF_RING_SIZE'; + mmVGT_HS_OFFCHIP_PARAM :Result:='mmVGT_HS_OFFCHIP_PARAM'; + mmVGT_TF_MEMORY_BASE :Result:='mmVGT_TF_MEMORY_BASE'; + mmPA_SU_LINE_STIPPLE_VALUE :Result:='mmPA_SU_LINE_STIPPLE_VALUE'; + mmPA_SC_LINE_STIPPLE_STATE :Result:='mmPA_SC_LINE_STIPPLE_STATE'; + mmPA_SC_P3D_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_P3D_TRAP_SCREEN_HV_EN'; + mmPA_SC_P3D_TRAP_SCREEN_H :Result:='mmPA_SC_P3D_TRAP_SCREEN_H'; + mmPA_SC_P3D_TRAP_SCREEN_V :Result:='mmPA_SC_P3D_TRAP_SCREEN_V'; + mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE'; + mmPA_SC_P3D_TRAP_SCREEN_COUNT :Result:='mmPA_SC_P3D_TRAP_SCREEN_COUNT'; + mmPA_SC_HP3D_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_HP3D_TRAP_SCREEN_HV_EN'; + mmPA_SC_HP3D_TRAP_SCREEN_H :Result:='mmPA_SC_HP3D_TRAP_SCREEN_H'; + mmPA_SC_HP3D_TRAP_SCREEN_V :Result:='mmPA_SC_HP3D_TRAP_SCREEN_V'; + mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE'; + mmPA_SC_HP3D_TRAP_SCREEN_COUNT :Result:='mmPA_SC_HP3D_TRAP_SCREEN_COUNT'; + mmPA_SC_TRAP_SCREEN_HV_EN :Result:='mmPA_SC_TRAP_SCREEN_HV_EN'; + mmPA_SC_TRAP_SCREEN_H :Result:='mmPA_SC_TRAP_SCREEN_H'; + mmPA_SC_TRAP_SCREEN_V :Result:='mmPA_SC_TRAP_SCREEN_V'; + mmPA_SC_TRAP_SCREEN_OCCURRENCE :Result:='mmPA_SC_TRAP_SCREEN_OCCURRENCE'; + mmPA_SC_TRAP_SCREEN_COUNT :Result:='mmPA_SC_TRAP_SCREEN_COUNT'; + mmSQ_THREAD_TRACE_BASE :Result:='mmSQ_THREAD_TRACE_BASE'; + mmSQ_THREAD_TRACE_SIZE :Result:='mmSQ_THREAD_TRACE_SIZE'; + mmSQ_THREAD_TRACE_MASK :Result:='mmSQ_THREAD_TRACE_MASK'; + mmSQ_THREAD_TRACE_TOKEN_MASK :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK'; + mmSQ_THREAD_TRACE_PERF_MASK :Result:='mmSQ_THREAD_TRACE_PERF_MASK'; + mmSQ_THREAD_TRACE_CTRL :Result:='mmSQ_THREAD_TRACE_CTRL'; + mmSQ_THREAD_TRACE_MODE :Result:='mmSQ_THREAD_TRACE_MODE'; + mmSQ_THREAD_TRACE_BASE2 :Result:='mmSQ_THREAD_TRACE_BASE2'; + mmSQ_THREAD_TRACE_TOKEN_MASK2 :Result:='mmSQ_THREAD_TRACE_TOKEN_MASK2'; + mmSQ_THREAD_TRACE_WPTR :Result:='mmSQ_THREAD_TRACE_WPTR'; + mmSQ_THREAD_TRACE_STATUS :Result:='mmSQ_THREAD_TRACE_STATUS'; + mmSQ_THREAD_TRACE_HIWATER :Result:='mmSQ_THREAD_TRACE_HIWATER'; + mmSQ_THREAD_TRACE_USERDATA_0 :Result:='mmSQ_THREAD_TRACE_USERDATA_0'; + mmSQ_THREAD_TRACE_USERDATA_1 :Result:='mmSQ_THREAD_TRACE_USERDATA_1'; + mmSQ_THREAD_TRACE_USERDATA_2 :Result:='mmSQ_THREAD_TRACE_USERDATA_2'; + mmSQ_THREAD_TRACE_USERDATA_3 :Result:='mmSQ_THREAD_TRACE_USERDATA_3'; + mmSQC_CACHES :Result:='mmSQC_CACHES'; + mmSQC_WRITEBACK :Result:='mmSQC_WRITEBACK'; + mmTA_CS_BC_BASE_ADDR :Result:='mmTA_CS_BC_BASE_ADDR'; + mmTA_CS_BC_BASE_ADDR_HI :Result:='mmTA_CS_BC_BASE_ADDR_HI'; + mmDB_OCCLUSION_COUNT0_LOW :Result:='mmDB_OCCLUSION_COUNT0_LOW'; + mmDB_OCCLUSION_COUNT0_HI :Result:='mmDB_OCCLUSION_COUNT0_HI'; + mmDB_OCCLUSION_COUNT1_LOW :Result:='mmDB_OCCLUSION_COUNT1_LOW'; + mmDB_OCCLUSION_COUNT1_HI :Result:='mmDB_OCCLUSION_COUNT1_HI'; + mmDB_OCCLUSION_COUNT2_LOW :Result:='mmDB_OCCLUSION_COUNT2_LOW'; + mmDB_OCCLUSION_COUNT2_HI :Result:='mmDB_OCCLUSION_COUNT2_HI'; + mmDB_OCCLUSION_COUNT3_LOW :Result:='mmDB_OCCLUSION_COUNT3_LOW'; + mmDB_OCCLUSION_COUNT3_HI :Result:='mmDB_OCCLUSION_COUNT3_HI'; + mmDB_ZPASS_COUNT_LOW :Result:='mmDB_ZPASS_COUNT_LOW'; + mmDB_ZPASS_COUNT_HI :Result:='mmDB_ZPASS_COUNT_HI'; + mmGDS_RD_ADDR :Result:='mmGDS_RD_ADDR'; + mmGDS_RD_DATA :Result:='mmGDS_RD_DATA'; + mmGDS_RD_BURST_ADDR :Result:='mmGDS_RD_BURST_ADDR'; + mmGDS_RD_BURST_COUNT :Result:='mmGDS_RD_BURST_COUNT'; + mmGDS_RD_BURST_DATA :Result:='mmGDS_RD_BURST_DATA'; + mmGDS_WR_ADDR :Result:='mmGDS_WR_ADDR'; + mmGDS_WR_DATA :Result:='mmGDS_WR_DATA'; + mmGDS_WR_BURST_ADDR :Result:='mmGDS_WR_BURST_ADDR'; + mmGDS_WR_BURST_DATA :Result:='mmGDS_WR_BURST_DATA'; + mmGDS_WRITE_COMPLETE :Result:='mmGDS_WRITE_COMPLETE'; + mmGDS_ATOM_CNTL :Result:='mmGDS_ATOM_CNTL'; + mmGDS_ATOM_COMPLETE :Result:='mmGDS_ATOM_COMPLETE'; + mmGDS_ATOM_BASE :Result:='mmGDS_ATOM_BASE'; + mmGDS_ATOM_SIZE :Result:='mmGDS_ATOM_SIZE'; + mmGDS_ATOM_OFFSET0 :Result:='mmGDS_ATOM_OFFSET0'; + mmGDS_ATOM_OFFSET1 :Result:='mmGDS_ATOM_OFFSET1'; + mmGDS_ATOM_DST :Result:='mmGDS_ATOM_DST'; + mmGDS_ATOM_OP :Result:='mmGDS_ATOM_OP'; + mmGDS_ATOM_SRC0 :Result:='mmGDS_ATOM_SRC0'; + mmGDS_ATOM_SRC0_U :Result:='mmGDS_ATOM_SRC0_U'; + mmGDS_ATOM_SRC1 :Result:='mmGDS_ATOM_SRC1'; + mmGDS_ATOM_SRC1_U :Result:='mmGDS_ATOM_SRC1_U'; + mmGDS_ATOM_READ0 :Result:='mmGDS_ATOM_READ0'; + mmGDS_ATOM_READ0_U :Result:='mmGDS_ATOM_READ0_U'; + mmGDS_ATOM_READ1 :Result:='mmGDS_ATOM_READ1'; + mmGDS_ATOM_READ1_U :Result:='mmGDS_ATOM_READ1_U'; + mmGDS_GWS_RESOURCE_CNTL :Result:='mmGDS_GWS_RESOURCE_CNTL'; + mmGDS_GWS_RESOURCE :Result:='mmGDS_GWS_RESOURCE'; + mmGDS_GWS_RESOURCE_CNT :Result:='mmGDS_GWS_RESOURCE_CNT'; + mmGDS_OA_CNTL :Result:='mmGDS_OA_CNTL'; + mmGDS_OA_COUNTER :Result:='mmGDS_OA_COUNTER'; + mmGDS_OA_ADDRESS :Result:='mmGDS_OA_ADDRESS'; + mmGDS_OA_INCDEC :Result:='mmGDS_OA_INCDEC'; + mmGDS_OA_RING_SIZE :Result:='mmGDS_OA_RING_SIZE'; + mmCPG_PERFCOUNTER1_LO :Result:='mmCPG_PERFCOUNTER1_LO'; + mmCPG_PERFCOUNTER1_HI :Result:='mmCPG_PERFCOUNTER1_HI'; + mmCPG_PERFCOUNTER0_LO :Result:='mmCPG_PERFCOUNTER0_LO'; + mmCPG_PERFCOUNTER0_HI :Result:='mmCPG_PERFCOUNTER0_HI'; + mmCPC_PERFCOUNTER1_LO :Result:='mmCPC_PERFCOUNTER1_LO'; + mmCPC_PERFCOUNTER1_HI :Result:='mmCPC_PERFCOUNTER1_HI'; + mmCPC_PERFCOUNTER0_LO :Result:='mmCPC_PERFCOUNTER0_LO'; + mmCPC_PERFCOUNTER0_HI :Result:='mmCPC_PERFCOUNTER0_HI'; + mmCPF_PERFCOUNTER1_LO :Result:='mmCPF_PERFCOUNTER1_LO'; + mmCPF_PERFCOUNTER1_HI :Result:='mmCPF_PERFCOUNTER1_HI'; + mmCPF_PERFCOUNTER0_LO :Result:='mmCPF_PERFCOUNTER0_LO'; + mmCPF_PERFCOUNTER0_HI :Result:='mmCPF_PERFCOUNTER0_HI'; + mmGRBM_PERFCOUNTER0_LO :Result:='mmGRBM_PERFCOUNTER0_LO'; + mmGRBM_PERFCOUNTER0_HI :Result:='mmGRBM_PERFCOUNTER0_HI'; + mmGRBM_PERFCOUNTER1_LO :Result:='mmGRBM_PERFCOUNTER1_LO'; + mmGRBM_PERFCOUNTER1_HI :Result:='mmGRBM_PERFCOUNTER1_HI'; + mmGRBM_SE0_PERFCOUNTER_LO :Result:='mmGRBM_SE0_PERFCOUNTER_LO'; + mmGRBM_SE0_PERFCOUNTER_HI :Result:='mmGRBM_SE0_PERFCOUNTER_HI'; + mmGRBM_SE1_PERFCOUNTER_LO :Result:='mmGRBM_SE1_PERFCOUNTER_LO'; + mmGRBM_SE1_PERFCOUNTER_HI :Result:='mmGRBM_SE1_PERFCOUNTER_HI'; + mmGRBM_SE2_PERFCOUNTER_LO :Result:='mmGRBM_SE2_PERFCOUNTER_LO'; + mmGRBM_SE2_PERFCOUNTER_HI :Result:='mmGRBM_SE2_PERFCOUNTER_HI'; + mmGRBM_SE3_PERFCOUNTER_LO :Result:='mmGRBM_SE3_PERFCOUNTER_LO'; + mmGRBM_SE3_PERFCOUNTER_HI :Result:='mmGRBM_SE3_PERFCOUNTER_HI'; + mmWD_PERFCOUNTER0_LO :Result:='mmWD_PERFCOUNTER0_LO'; + mmWD_PERFCOUNTER0_HI :Result:='mmWD_PERFCOUNTER0_HI'; + mmWD_PERFCOUNTER1_LO :Result:='mmWD_PERFCOUNTER1_LO'; + mmWD_PERFCOUNTER1_HI :Result:='mmWD_PERFCOUNTER1_HI'; + mmWD_PERFCOUNTER2_LO :Result:='mmWD_PERFCOUNTER2_LO'; + mmWD_PERFCOUNTER2_HI :Result:='mmWD_PERFCOUNTER2_HI'; + mmWD_PERFCOUNTER3_LO :Result:='mmWD_PERFCOUNTER3_LO'; + mmWD_PERFCOUNTER3_HI :Result:='mmWD_PERFCOUNTER3_HI'; + mmIA_PERFCOUNTER0_LO :Result:='mmIA_PERFCOUNTER0_LO'; + mmIA_PERFCOUNTER0_HI :Result:='mmIA_PERFCOUNTER0_HI'; + mmIA_PERFCOUNTER1_LO :Result:='mmIA_PERFCOUNTER1_LO'; + mmIA_PERFCOUNTER1_HI :Result:='mmIA_PERFCOUNTER1_HI'; + mmIA_PERFCOUNTER2_LO :Result:='mmIA_PERFCOUNTER2_LO'; + mmIA_PERFCOUNTER2_HI :Result:='mmIA_PERFCOUNTER2_HI'; + mmIA_PERFCOUNTER3_LO :Result:='mmIA_PERFCOUNTER3_LO'; + mmIA_PERFCOUNTER3_HI :Result:='mmIA_PERFCOUNTER3_HI'; + mmVGT_PERFCOUNTER0_LO :Result:='mmVGT_PERFCOUNTER0_LO'; + mmVGT_PERFCOUNTER0_HI :Result:='mmVGT_PERFCOUNTER0_HI'; + mmVGT_PERFCOUNTER1_LO :Result:='mmVGT_PERFCOUNTER1_LO'; + mmVGT_PERFCOUNTER1_HI :Result:='mmVGT_PERFCOUNTER1_HI'; + mmVGT_PERFCOUNTER2_LO :Result:='mmVGT_PERFCOUNTER2_LO'; + mmVGT_PERFCOUNTER2_HI :Result:='mmVGT_PERFCOUNTER2_HI'; + mmVGT_PERFCOUNTER3_LO :Result:='mmVGT_PERFCOUNTER3_LO'; + mmVGT_PERFCOUNTER3_HI :Result:='mmVGT_PERFCOUNTER3_HI'; + mmPA_SU_PERFCOUNTER0_LO :Result:='mmPA_SU_PERFCOUNTER0_LO'; + mmPA_SU_PERFCOUNTER0_HI :Result:='mmPA_SU_PERFCOUNTER0_HI'; + mmPA_SU_PERFCOUNTER1_LO :Result:='mmPA_SU_PERFCOUNTER1_LO'; + mmPA_SU_PERFCOUNTER1_HI :Result:='mmPA_SU_PERFCOUNTER1_HI'; + mmPA_SU_PERFCOUNTER2_LO :Result:='mmPA_SU_PERFCOUNTER2_LO'; + mmPA_SU_PERFCOUNTER2_HI :Result:='mmPA_SU_PERFCOUNTER2_HI'; + mmPA_SU_PERFCOUNTER3_LO :Result:='mmPA_SU_PERFCOUNTER3_LO'; + mmPA_SU_PERFCOUNTER3_HI :Result:='mmPA_SU_PERFCOUNTER3_HI'; + mmPA_SC_PERFCOUNTER0_LO :Result:='mmPA_SC_PERFCOUNTER0_LO'; + mmPA_SC_PERFCOUNTER0_HI :Result:='mmPA_SC_PERFCOUNTER0_HI'; + mmPA_SC_PERFCOUNTER1_LO :Result:='mmPA_SC_PERFCOUNTER1_LO'; + mmPA_SC_PERFCOUNTER1_HI :Result:='mmPA_SC_PERFCOUNTER1_HI'; + mmPA_SC_PERFCOUNTER2_LO :Result:='mmPA_SC_PERFCOUNTER2_LO'; + mmPA_SC_PERFCOUNTER2_HI :Result:='mmPA_SC_PERFCOUNTER2_HI'; + mmPA_SC_PERFCOUNTER3_LO :Result:='mmPA_SC_PERFCOUNTER3_LO'; + mmPA_SC_PERFCOUNTER3_HI :Result:='mmPA_SC_PERFCOUNTER3_HI'; + mmPA_SC_PERFCOUNTER4_LO :Result:='mmPA_SC_PERFCOUNTER4_LO'; + mmPA_SC_PERFCOUNTER4_HI :Result:='mmPA_SC_PERFCOUNTER4_HI'; + mmPA_SC_PERFCOUNTER5_LO :Result:='mmPA_SC_PERFCOUNTER5_LO'; + mmPA_SC_PERFCOUNTER5_HI :Result:='mmPA_SC_PERFCOUNTER5_HI'; + mmPA_SC_PERFCOUNTER6_LO :Result:='mmPA_SC_PERFCOUNTER6_LO'; + mmPA_SC_PERFCOUNTER6_HI :Result:='mmPA_SC_PERFCOUNTER6_HI'; + mmPA_SC_PERFCOUNTER7_LO :Result:='mmPA_SC_PERFCOUNTER7_LO'; + mmPA_SC_PERFCOUNTER7_HI :Result:='mmPA_SC_PERFCOUNTER7_HI'; + mmSPI_PERFCOUNTER0_HI :Result:='mmSPI_PERFCOUNTER0_HI'; + mmSPI_PERFCOUNTER0_LO :Result:='mmSPI_PERFCOUNTER0_LO'; + mmSPI_PERFCOUNTER1_HI :Result:='mmSPI_PERFCOUNTER1_HI'; + mmSPI_PERFCOUNTER1_LO :Result:='mmSPI_PERFCOUNTER1_LO'; + mmSPI_PERFCOUNTER2_HI :Result:='mmSPI_PERFCOUNTER2_HI'; + mmSPI_PERFCOUNTER2_LO :Result:='mmSPI_PERFCOUNTER2_LO'; + mmSPI_PERFCOUNTER3_HI :Result:='mmSPI_PERFCOUNTER3_HI'; + mmSPI_PERFCOUNTER3_LO :Result:='mmSPI_PERFCOUNTER3_LO'; + mmSPI_PERFCOUNTER4_HI :Result:='mmSPI_PERFCOUNTER4_HI'; + mmSPI_PERFCOUNTER4_LO :Result:='mmSPI_PERFCOUNTER4_LO'; + mmSPI_PERFCOUNTER5_HI :Result:='mmSPI_PERFCOUNTER5_HI'; + mmSPI_PERFCOUNTER5_LO :Result:='mmSPI_PERFCOUNTER5_LO'; + mmSQ_PERFCOUNTER0_LO :Result:='mmSQ_PERFCOUNTER0_LO'; + mmSQ_PERFCOUNTER0_HI :Result:='mmSQ_PERFCOUNTER0_HI'; + mmSQ_PERFCOUNTER1_LO :Result:='mmSQ_PERFCOUNTER1_LO'; + mmSQ_PERFCOUNTER1_HI :Result:='mmSQ_PERFCOUNTER1_HI'; + mmSQ_PERFCOUNTER2_LO :Result:='mmSQ_PERFCOUNTER2_LO'; + mmSQ_PERFCOUNTER2_HI :Result:='mmSQ_PERFCOUNTER2_HI'; + mmSQ_PERFCOUNTER3_LO :Result:='mmSQ_PERFCOUNTER3_LO'; + mmSQ_PERFCOUNTER3_HI :Result:='mmSQ_PERFCOUNTER3_HI'; + mmSQ_PERFCOUNTER4_LO :Result:='mmSQ_PERFCOUNTER4_LO'; + mmSQ_PERFCOUNTER4_HI :Result:='mmSQ_PERFCOUNTER4_HI'; + mmSQ_PERFCOUNTER5_LO :Result:='mmSQ_PERFCOUNTER5_LO'; + mmSQ_PERFCOUNTER5_HI :Result:='mmSQ_PERFCOUNTER5_HI'; + mmSQ_PERFCOUNTER6_LO :Result:='mmSQ_PERFCOUNTER6_LO'; + mmSQ_PERFCOUNTER6_HI :Result:='mmSQ_PERFCOUNTER6_HI'; + mmSQ_PERFCOUNTER7_LO :Result:='mmSQ_PERFCOUNTER7_LO'; + mmSQ_PERFCOUNTER7_HI :Result:='mmSQ_PERFCOUNTER7_HI'; + mmSQ_PERFCOUNTER8_LO :Result:='mmSQ_PERFCOUNTER8_LO'; + mmSQ_PERFCOUNTER8_HI :Result:='mmSQ_PERFCOUNTER8_HI'; + mmSQ_PERFCOUNTER9_LO :Result:='mmSQ_PERFCOUNTER9_LO'; + mmSQ_PERFCOUNTER9_HI :Result:='mmSQ_PERFCOUNTER9_HI'; + mmSQ_PERFCOUNTER10_LO :Result:='mmSQ_PERFCOUNTER10_LO'; + mmSQ_PERFCOUNTER10_HI :Result:='mmSQ_PERFCOUNTER10_HI'; + mmSQ_PERFCOUNTER11_LO :Result:='mmSQ_PERFCOUNTER11_LO'; + mmSQ_PERFCOUNTER11_HI :Result:='mmSQ_PERFCOUNTER11_HI'; + mmSQ_PERFCOUNTER12_LO :Result:='mmSQ_PERFCOUNTER12_LO'; + mmSQ_PERFCOUNTER12_HI :Result:='mmSQ_PERFCOUNTER12_HI'; + mmSQ_PERFCOUNTER13_LO :Result:='mmSQ_PERFCOUNTER13_LO'; + mmSQ_PERFCOUNTER13_HI :Result:='mmSQ_PERFCOUNTER13_HI'; + mmSQ_PERFCOUNTER14_LO :Result:='mmSQ_PERFCOUNTER14_LO'; + mmSQ_PERFCOUNTER14_HI :Result:='mmSQ_PERFCOUNTER14_HI'; + mmSQ_PERFCOUNTER15_LO :Result:='mmSQ_PERFCOUNTER15_LO'; + mmSQ_PERFCOUNTER15_HI :Result:='mmSQ_PERFCOUNTER15_HI'; + mmSX_PERFCOUNTER0_LO :Result:='mmSX_PERFCOUNTER0_LO'; + mmSX_PERFCOUNTER0_HI :Result:='mmSX_PERFCOUNTER0_HI'; + mmSX_PERFCOUNTER1_LO :Result:='mmSX_PERFCOUNTER1_LO'; + mmSX_PERFCOUNTER1_HI :Result:='mmSX_PERFCOUNTER1_HI'; + mmSX_PERFCOUNTER2_LO :Result:='mmSX_PERFCOUNTER2_LO'; + mmSX_PERFCOUNTER2_HI :Result:='mmSX_PERFCOUNTER2_HI'; + mmSX_PERFCOUNTER3_LO :Result:='mmSX_PERFCOUNTER3_LO'; + mmSX_PERFCOUNTER3_HI :Result:='mmSX_PERFCOUNTER3_HI'; + mmGDS_PERFCOUNTER0_LO :Result:='mmGDS_PERFCOUNTER0_LO'; + mmGDS_PERFCOUNTER0_HI :Result:='mmGDS_PERFCOUNTER0_HI'; + mmGDS_PERFCOUNTER1_LO :Result:='mmGDS_PERFCOUNTER1_LO'; + mmGDS_PERFCOUNTER1_HI :Result:='mmGDS_PERFCOUNTER1_HI'; + mmGDS_PERFCOUNTER2_LO :Result:='mmGDS_PERFCOUNTER2_LO'; + mmGDS_PERFCOUNTER2_HI :Result:='mmGDS_PERFCOUNTER2_HI'; + mmGDS_PERFCOUNTER3_LO :Result:='mmGDS_PERFCOUNTER3_LO'; + mmGDS_PERFCOUNTER3_HI :Result:='mmGDS_PERFCOUNTER3_HI'; + mmTA_PERFCOUNTER0_LO :Result:='mmTA_PERFCOUNTER0_LO'; + mmTA_PERFCOUNTER0_HI :Result:='mmTA_PERFCOUNTER0_HI'; + mmTA_PERFCOUNTER1_LO :Result:='mmTA_PERFCOUNTER1_LO'; + mmTA_PERFCOUNTER1_HI :Result:='mmTA_PERFCOUNTER1_HI'; + mmTD_PERFCOUNTER0_LO :Result:='mmTD_PERFCOUNTER0_LO'; + mmTD_PERFCOUNTER0_HI :Result:='mmTD_PERFCOUNTER0_HI'; + mmTD_PERFCOUNTER1_LO :Result:='mmTD_PERFCOUNTER1_LO'; + mmTD_PERFCOUNTER1_HI :Result:='mmTD_PERFCOUNTER1_HI'; + mmTCP_PERFCOUNTER0_LO :Result:='mmTCP_PERFCOUNTER0_LO'; + mmTCP_PERFCOUNTER0_HI :Result:='mmTCP_PERFCOUNTER0_HI'; + mmTCP_PERFCOUNTER1_LO :Result:='mmTCP_PERFCOUNTER1_LO'; + mmTCP_PERFCOUNTER1_HI :Result:='mmTCP_PERFCOUNTER1_HI'; + mmTCP_PERFCOUNTER2_LO :Result:='mmTCP_PERFCOUNTER2_LO'; + mmTCP_PERFCOUNTER2_HI :Result:='mmTCP_PERFCOUNTER2_HI'; + mmTCP_PERFCOUNTER3_LO :Result:='mmTCP_PERFCOUNTER3_LO'; + mmTCP_PERFCOUNTER3_HI :Result:='mmTCP_PERFCOUNTER3_HI'; + mmTCC_PERFCOUNTER0_LO :Result:='mmTCC_PERFCOUNTER0_LO'; + mmTCC_PERFCOUNTER0_HI :Result:='mmTCC_PERFCOUNTER0_HI'; + mmTCC_PERFCOUNTER1_LO :Result:='mmTCC_PERFCOUNTER1_LO'; + mmTCC_PERFCOUNTER1_HI :Result:='mmTCC_PERFCOUNTER1_HI'; + mmTCC_PERFCOUNTER2_LO :Result:='mmTCC_PERFCOUNTER2_LO'; + mmTCC_PERFCOUNTER2_HI :Result:='mmTCC_PERFCOUNTER2_HI'; + mmTCC_PERFCOUNTER3_LO :Result:='mmTCC_PERFCOUNTER3_LO'; + mmTCC_PERFCOUNTER3_HI :Result:='mmTCC_PERFCOUNTER3_HI'; + mmTCA_PERFCOUNTER0_LO :Result:='mmTCA_PERFCOUNTER0_LO'; + mmTCA_PERFCOUNTER0_HI :Result:='mmTCA_PERFCOUNTER0_HI'; + mmTCA_PERFCOUNTER1_LO :Result:='mmTCA_PERFCOUNTER1_LO'; + mmTCA_PERFCOUNTER1_HI :Result:='mmTCA_PERFCOUNTER1_HI'; + mmTCA_PERFCOUNTER2_LO :Result:='mmTCA_PERFCOUNTER2_LO'; + mmTCA_PERFCOUNTER2_HI :Result:='mmTCA_PERFCOUNTER2_HI'; + mmTCA_PERFCOUNTER3_LO :Result:='mmTCA_PERFCOUNTER3_LO'; + mmTCA_PERFCOUNTER3_HI :Result:='mmTCA_PERFCOUNTER3_HI'; + mmCB_PERFCOUNTER0_LO :Result:='mmCB_PERFCOUNTER0_LO'; + mmCB_PERFCOUNTER0_HI :Result:='mmCB_PERFCOUNTER0_HI'; + mmCB_PERFCOUNTER1_LO :Result:='mmCB_PERFCOUNTER1_LO'; + mmCB_PERFCOUNTER1_HI :Result:='mmCB_PERFCOUNTER1_HI'; + mmCB_PERFCOUNTER2_LO :Result:='mmCB_PERFCOUNTER2_LO'; + mmCB_PERFCOUNTER2_HI :Result:='mmCB_PERFCOUNTER2_HI'; + mmCB_PERFCOUNTER3_LO :Result:='mmCB_PERFCOUNTER3_LO'; + mmCB_PERFCOUNTER3_HI :Result:='mmCB_PERFCOUNTER3_HI'; + mmDB_PERFCOUNTER0_LO :Result:='mmDB_PERFCOUNTER0_LO'; + mmDB_PERFCOUNTER0_HI :Result:='mmDB_PERFCOUNTER0_HI'; + mmDB_PERFCOUNTER1_LO :Result:='mmDB_PERFCOUNTER1_LO'; + mmDB_PERFCOUNTER1_HI :Result:='mmDB_PERFCOUNTER1_HI'; + mmDB_PERFCOUNTER2_LO :Result:='mmDB_PERFCOUNTER2_LO'; + mmDB_PERFCOUNTER2_HI :Result:='mmDB_PERFCOUNTER2_HI'; + mmDB_PERFCOUNTER3_LO :Result:='mmDB_PERFCOUNTER3_LO'; + mmDB_PERFCOUNTER3_HI :Result:='mmDB_PERFCOUNTER3_HI'; + mmRLC_PERFCOUNTER0_LO :Result:='mmRLC_PERFCOUNTER0_LO'; + mmRLC_PERFCOUNTER0_HI :Result:='mmRLC_PERFCOUNTER0_HI'; + mmRLC_PERFCOUNTER1_LO :Result:='mmRLC_PERFCOUNTER1_LO'; + mmRLC_PERFCOUNTER1_HI :Result:='mmRLC_PERFCOUNTER1_HI'; + mmCPG_PERFCOUNTER1_SELECT :Result:='mmCPG_PERFCOUNTER1_SELECT'; + mmCPG_PERFCOUNTER0_SELECT1 :Result:='mmCPG_PERFCOUNTER0_SELECT1'; + mmCPG_PERFCOUNTER0_SELECT :Result:='mmCPG_PERFCOUNTER0_SELECT'; + mmCPC_PERFCOUNTER1_SELECT :Result:='mmCPC_PERFCOUNTER1_SELECT'; + mmCPC_PERFCOUNTER0_SELECT1 :Result:='mmCPC_PERFCOUNTER0_SELECT1'; + mmCPF_PERFCOUNTER1_SELECT :Result:='mmCPF_PERFCOUNTER1_SELECT'; + mmCPF_PERFCOUNTER0_SELECT1 :Result:='mmCPF_PERFCOUNTER0_SELECT1'; + mmCPF_PERFCOUNTER0_SELECT :Result:='mmCPF_PERFCOUNTER0_SELECT'; + mmCP_PERFMON_CNTL :Result:='mmCP_PERFMON_CNTL'; + mmCPC_PERFCOUNTER0_SELECT :Result:='mmCPC_PERFCOUNTER0_SELECT'; + mmCP_DRAW_OBJECT :Result:='mmCP_DRAW_OBJECT'; + mmCP_DRAW_OBJECT_COUNTER :Result:='mmCP_DRAW_OBJECT_COUNTER'; + mmCP_DRAW_WINDOW_MASK_HI :Result:='mmCP_DRAW_WINDOW_MASK_HI'; + mmCP_DRAW_WINDOW_HI :Result:='mmCP_DRAW_WINDOW_HI'; + mmCP_DRAW_WINDOW_LO :Result:='mmCP_DRAW_WINDOW_LO'; + mmCP_DRAW_WINDOW_CNTL :Result:='mmCP_DRAW_WINDOW_CNTL'; + mmGRBM_PERFCOUNTER0_SELECT :Result:='mmGRBM_PERFCOUNTER0_SELECT'; + mmGRBM_PERFCOUNTER1_SELECT :Result:='mmGRBM_PERFCOUNTER1_SELECT'; + mmGRBM_SE0_PERFCOUNTER_SELECT :Result:='mmGRBM_SE0_PERFCOUNTER_SELECT'; + mmGRBM_SE1_PERFCOUNTER_SELECT :Result:='mmGRBM_SE1_PERFCOUNTER_SELECT'; + mmGRBM_SE2_PERFCOUNTER_SELECT :Result:='mmGRBM_SE2_PERFCOUNTER_SELECT'; + mmGRBM_SE3_PERFCOUNTER_SELECT :Result:='mmGRBM_SE3_PERFCOUNTER_SELECT'; + mmWD_PERFCOUNTER0_SELECT :Result:='mmWD_PERFCOUNTER0_SELECT'; + mmWD_PERFCOUNTER1_SELECT :Result:='mmWD_PERFCOUNTER1_SELECT'; + mmWD_PERFCOUNTER2_SELECT :Result:='mmWD_PERFCOUNTER2_SELECT'; + mmWD_PERFCOUNTER3_SELECT :Result:='mmWD_PERFCOUNTER3_SELECT'; + mmIA_PERFCOUNTER0_SELECT :Result:='mmIA_PERFCOUNTER0_SELECT'; + mmIA_PERFCOUNTER1_SELECT :Result:='mmIA_PERFCOUNTER1_SELECT'; + mmIA_PERFCOUNTER2_SELECT :Result:='mmIA_PERFCOUNTER2_SELECT'; + mmIA_PERFCOUNTER3_SELECT :Result:='mmIA_PERFCOUNTER3_SELECT'; + mmIA_PERFCOUNTER0_SELECT1 :Result:='mmIA_PERFCOUNTER0_SELECT1'; + mmVGT_PERFCOUNTER0_SELECT :Result:='mmVGT_PERFCOUNTER0_SELECT'; + mmVGT_PERFCOUNTER1_SELECT :Result:='mmVGT_PERFCOUNTER1_SELECT'; + mmVGT_PERFCOUNTER2_SELECT :Result:='mmVGT_PERFCOUNTER2_SELECT'; + mmVGT_PERFCOUNTER3_SELECT :Result:='mmVGT_PERFCOUNTER3_SELECT'; + mmVGT_PERFCOUNTER0_SELECT1 :Result:='mmVGT_PERFCOUNTER0_SELECT1'; + mmVGT_PERFCOUNTER1_SELECT1 :Result:='mmVGT_PERFCOUNTER1_SELECT1'; + mmVGT_PERFCOUNTER_SEID_MASK :Result:='mmVGT_PERFCOUNTER_SEID_MASK'; + mmPA_SU_PERFCOUNTER0_SELECT :Result:='mmPA_SU_PERFCOUNTER0_SELECT'; + mmPA_SU_PERFCOUNTER0_SELECT1 :Result:='mmPA_SU_PERFCOUNTER0_SELECT1'; + mmPA_SU_PERFCOUNTER1_SELECT :Result:='mmPA_SU_PERFCOUNTER1_SELECT'; + mmPA_SU_PERFCOUNTER1_SELECT1 :Result:='mmPA_SU_PERFCOUNTER1_SELECT1'; + mmPA_SU_PERFCOUNTER2_SELECT :Result:='mmPA_SU_PERFCOUNTER2_SELECT'; + mmPA_SU_PERFCOUNTER3_SELECT :Result:='mmPA_SU_PERFCOUNTER3_SELECT'; + mmPA_SC_PERFCOUNTER0_SELECT :Result:='mmPA_SC_PERFCOUNTER0_SELECT'; + mmPA_SC_PERFCOUNTER0_SELECT1 :Result:='mmPA_SC_PERFCOUNTER0_SELECT1'; + mmPA_SC_PERFCOUNTER1_SELECT :Result:='mmPA_SC_PERFCOUNTER1_SELECT'; + mmPA_SC_PERFCOUNTER2_SELECT :Result:='mmPA_SC_PERFCOUNTER2_SELECT'; + mmPA_SC_PERFCOUNTER3_SELECT :Result:='mmPA_SC_PERFCOUNTER3_SELECT'; + mmPA_SC_PERFCOUNTER4_SELECT :Result:='mmPA_SC_PERFCOUNTER4_SELECT'; + mmPA_SC_PERFCOUNTER5_SELECT :Result:='mmPA_SC_PERFCOUNTER5_SELECT'; + mmPA_SC_PERFCOUNTER6_SELECT :Result:='mmPA_SC_PERFCOUNTER6_SELECT'; + mmPA_SC_PERFCOUNTER7_SELECT :Result:='mmPA_SC_PERFCOUNTER7_SELECT'; + mmSPI_PERFCOUNTER0_SELECT :Result:='mmSPI_PERFCOUNTER0_SELECT'; + mmSPI_PERFCOUNTER1_SELECT :Result:='mmSPI_PERFCOUNTER1_SELECT'; + mmSPI_PERFCOUNTER2_SELECT :Result:='mmSPI_PERFCOUNTER2_SELECT'; + mmSPI_PERFCOUNTER3_SELECT :Result:='mmSPI_PERFCOUNTER3_SELECT'; + mmSPI_PERFCOUNTER0_SELECT1 :Result:='mmSPI_PERFCOUNTER0_SELECT1'; + mmSPI_PERFCOUNTER1_SELECT1 :Result:='mmSPI_PERFCOUNTER1_SELECT1'; + mmSPI_PERFCOUNTER2_SELECT1 :Result:='mmSPI_PERFCOUNTER2_SELECT1'; + mmSPI_PERFCOUNTER3_SELECT1 :Result:='mmSPI_PERFCOUNTER3_SELECT1'; + mmSPI_PERFCOUNTER4_SELECT :Result:='mmSPI_PERFCOUNTER4_SELECT'; + mmSPI_PERFCOUNTER5_SELECT :Result:='mmSPI_PERFCOUNTER5_SELECT'; + mmSPI_PERFCOUNTER_BINS :Result:='mmSPI_PERFCOUNTER_BINS'; + mmSQ_PERFCOUNTER0_SELECT :Result:='mmSQ_PERFCOUNTER0_SELECT'; + mmSQ_PERFCOUNTER1_SELECT :Result:='mmSQ_PERFCOUNTER1_SELECT'; + mmSQ_PERFCOUNTER2_SELECT :Result:='mmSQ_PERFCOUNTER2_SELECT'; + mmSQ_PERFCOUNTER3_SELECT :Result:='mmSQ_PERFCOUNTER3_SELECT'; + mmSQ_PERFCOUNTER4_SELECT :Result:='mmSQ_PERFCOUNTER4_SELECT'; + mmSQ_PERFCOUNTER5_SELECT :Result:='mmSQ_PERFCOUNTER5_SELECT'; + mmSQ_PERFCOUNTER6_SELECT :Result:='mmSQ_PERFCOUNTER6_SELECT'; + mmSQ_PERFCOUNTER7_SELECT :Result:='mmSQ_PERFCOUNTER7_SELECT'; + mmSQ_PERFCOUNTER8_SELECT :Result:='mmSQ_PERFCOUNTER8_SELECT'; + mmSQ_PERFCOUNTER9_SELECT :Result:='mmSQ_PERFCOUNTER9_SELECT'; + mmSQ_PERFCOUNTER10_SELECT :Result:='mmSQ_PERFCOUNTER10_SELECT'; + mmSQ_PERFCOUNTER11_SELECT :Result:='mmSQ_PERFCOUNTER11_SELECT'; + mmSQ_PERFCOUNTER12_SELECT :Result:='mmSQ_PERFCOUNTER12_SELECT'; + mmSQ_PERFCOUNTER13_SELECT :Result:='mmSQ_PERFCOUNTER13_SELECT'; + mmSQ_PERFCOUNTER14_SELECT :Result:='mmSQ_PERFCOUNTER14_SELECT'; + mmSQ_PERFCOUNTER15_SELECT :Result:='mmSQ_PERFCOUNTER15_SELECT'; + mmSQ_PERFCOUNTER_CTRL :Result:='mmSQ_PERFCOUNTER_CTRL'; + mmSQ_PERFCOUNTER_MASK :Result:='mmSQ_PERFCOUNTER_MASK'; + mmSQ_PERFCOUNTER_CTRL2 :Result:='mmSQ_PERFCOUNTER_CTRL2'; + mmSX_PERFCOUNTER0_SELECT :Result:='mmSX_PERFCOUNTER0_SELECT'; + mmSX_PERFCOUNTER1_SELECT :Result:='mmSX_PERFCOUNTER1_SELECT'; + mmSX_PERFCOUNTER2_SELECT :Result:='mmSX_PERFCOUNTER2_SELECT'; + mmSX_PERFCOUNTER3_SELECT :Result:='mmSX_PERFCOUNTER3_SELECT'; + mmSX_PERFCOUNTER0_SELECT1 :Result:='mmSX_PERFCOUNTER0_SELECT1'; + mmSX_PERFCOUNTER1_SELECT1 :Result:='mmSX_PERFCOUNTER1_SELECT1'; + mmGDS_PERFCOUNTER0_SELECT :Result:='mmGDS_PERFCOUNTER0_SELECT'; + mmGDS_PERFCOUNTER1_SELECT :Result:='mmGDS_PERFCOUNTER1_SELECT'; + mmGDS_PERFCOUNTER2_SELECT :Result:='mmGDS_PERFCOUNTER2_SELECT'; + mmGDS_PERFCOUNTER3_SELECT :Result:='mmGDS_PERFCOUNTER3_SELECT'; + mmGDS_PERFCOUNTER0_SELECT1 :Result:='mmGDS_PERFCOUNTER0_SELECT1'; + mmTA_PERFCOUNTER0_SELECT :Result:='mmTA_PERFCOUNTER0_SELECT'; + mmTA_PERFCOUNTER0_SELECT1 :Result:='mmTA_PERFCOUNTER0_SELECT1'; + mmTA_PERFCOUNTER1_SELECT :Result:='mmTA_PERFCOUNTER1_SELECT'; + mmTD_PERFCOUNTER0_SELECT :Result:='mmTD_PERFCOUNTER0_SELECT'; + mmTD_PERFCOUNTER0_SELECT1 :Result:='mmTD_PERFCOUNTER0_SELECT1'; + mmTD_PERFCOUNTER1_SELECT :Result:='mmTD_PERFCOUNTER1_SELECT'; + mmTCP_PERFCOUNTER0_SELECT :Result:='mmTCP_PERFCOUNTER0_SELECT'; + mmTCP_PERFCOUNTER0_SELECT1 :Result:='mmTCP_PERFCOUNTER0_SELECT1'; + mmTCP_PERFCOUNTER1_SELECT :Result:='mmTCP_PERFCOUNTER1_SELECT'; + mmTCP_PERFCOUNTER1_SELECT1 :Result:='mmTCP_PERFCOUNTER1_SELECT1'; + mmTCP_PERFCOUNTER2_SELECT :Result:='mmTCP_PERFCOUNTER2_SELECT'; + mmTCP_PERFCOUNTER3_SELECT :Result:='mmTCP_PERFCOUNTER3_SELECT'; + mmTCC_PERFCOUNTER0_SELECT :Result:='mmTCC_PERFCOUNTER0_SELECT'; + mmTCC_PERFCOUNTER0_SELECT1 :Result:='mmTCC_PERFCOUNTER0_SELECT1'; + mmTCC_PERFCOUNTER1_SELECT :Result:='mmTCC_PERFCOUNTER1_SELECT'; + mmTCC_PERFCOUNTER1_SELECT1 :Result:='mmTCC_PERFCOUNTER1_SELECT1'; + mmTCC_PERFCOUNTER2_SELECT :Result:='mmTCC_PERFCOUNTER2_SELECT'; + mmTCC_PERFCOUNTER3_SELECT :Result:='mmTCC_PERFCOUNTER3_SELECT'; + mmTCA_PERFCOUNTER0_SELECT :Result:='mmTCA_PERFCOUNTER0_SELECT'; + mmTCA_PERFCOUNTER0_SELECT1 :Result:='mmTCA_PERFCOUNTER0_SELECT1'; + mmTCA_PERFCOUNTER1_SELECT :Result:='mmTCA_PERFCOUNTER1_SELECT'; + mmTCA_PERFCOUNTER1_SELECT1 :Result:='mmTCA_PERFCOUNTER1_SELECT1'; + mmTCA_PERFCOUNTER2_SELECT :Result:='mmTCA_PERFCOUNTER2_SELECT'; + mmTCA_PERFCOUNTER3_SELECT :Result:='mmTCA_PERFCOUNTER3_SELECT'; + mmCB_PERFCOUNTER_FILTER :Result:='mmCB_PERFCOUNTER_FILTER'; + mmCB_PERFCOUNTER0_SELECT :Result:='mmCB_PERFCOUNTER0_SELECT'; + mmCB_PERFCOUNTER0_SELECT1 :Result:='mmCB_PERFCOUNTER0_SELECT1'; + mmCB_PERFCOUNTER1_SELECT :Result:='mmCB_PERFCOUNTER1_SELECT'; + mmCB_PERFCOUNTER2_SELECT :Result:='mmCB_PERFCOUNTER2_SELECT'; + mmCB_PERFCOUNTER3_SELECT :Result:='mmCB_PERFCOUNTER3_SELECT'; + mmDB_PERFCOUNTER0_SELECT :Result:='mmDB_PERFCOUNTER0_SELECT'; + mmDB_PERFCOUNTER0_SELECT1 :Result:='mmDB_PERFCOUNTER0_SELECT1'; + mmDB_PERFCOUNTER1_SELECT :Result:='mmDB_PERFCOUNTER1_SELECT'; + mmDB_PERFCOUNTER1_SELECT1 :Result:='mmDB_PERFCOUNTER1_SELECT1'; + mmDB_PERFCOUNTER2_SELECT :Result:='mmDB_PERFCOUNTER2_SELECT'; + mmDB_PERFCOUNTER3_SELECT :Result:='mmDB_PERFCOUNTER3_SELECT'; else Result:=HexStr(i,4); end; diff --git a/chip/si_ci_vi_merged_registers.pas b/chip/si_ci_vi_merged_registers.pas index b4f8f0ea..ff569d1a 100644 --- a/chip/si_ci_vi_merged_registers.pas +++ b/chip/si_ci_vi_merged_registers.pas @@ -8,11 +8,559 @@ uses bittype; type + TLX0=bit32; + + TLX1=bit32; + + TLX2=bit32; + + TLX3=bit32; + + TBIST=bitpacked record + BIST_COMP:bit4; + RESERVED0:bit2; + BIST_STRT:bit1; + BIST_CAP :bit1; + RESERVED1:bit24; + end; + + TEXP0=bit32; + + TEXP1=bit32; + + TEXP2=bit32; + + TEXP3=bit32; + + TEXP4=bit32; + + TEXP5=bit32; + + TEXP6=bit32; + + TEXP7=bit32; + + TATTRX=bitpacked record + ATTR_IDX :bit5; + ATTR_PAL_RW_ENB:bit1; + RESERVED0 :bit26; + end; + + TCRT00=bitpacked record + H_TOTAL :bit8; + RESERVED0:bit24; + end; + + TCRT01=bitpacked record + H_DISP_END:bit8; + RESERVED0 :bit24; + end; + + TCRT02=bitpacked record + H_BLANK_START:bit8; + RESERVED0 :bit24; + end; + + TCRT03=bitpacked record + H_BLANK_END :bit5; + H_DE_SKEW :bit2; + CR10CR11_R_DIS_B:bit1; + RESERVED0 :bit24; + end; + + TCRT04=bitpacked record + H_SYNC_START:bit8; + RESERVED0 :bit24; + end; + + TCRT05=bitpacked record + H_SYNC_END :bit5; + H_SYNC_SKEW :bit2; + H_BLANK_END_B5:bit1; + RESERVED0 :bit24; + end; + + TCRT06=bitpacked record + V_TOTAL :bit8; + RESERVED0:bit24; + end; + + TCRT07=bitpacked record + V_TOTAL_B8 :bit1; + V_DISP_END_B8 :bit1; + V_SYNC_START_B8 :bit1; + V_BLANK_START_B8:bit1; + LINE_CMP_B8 :bit1; + V_TOTAL_B9 :bit1; + V_DISP_END_B9 :bit1; + V_SYNC_START_B9 :bit1; + RESERVED0 :bit24; + end; + + TCRT08=bitpacked record + ROW_SCAN_START:bit5; + BYTE_PAN :bit2; + RESERVED0 :bit25; + end; + + TCRT09=bitpacked record + MAX_ROW_SCAN :bit5; + V_BLANK_START_B9 :bit1; + LINE_CMP_B9 :bit1; + DOUBLE_CHAR_HEIGHT:bit1; + RESERVED0 :bit24; + end; + + TCRT0A=bitpacked record + CURSOR_START :bit5; + CURSOR_DISABLE:bit1; + RESERVED0 :bit26; + end; + + TCRT0B=bitpacked record + CURSOR_END :bit5; + CURSOR_SKEW:bit2; + RESERVED0 :bit25; + end; + + TCRT0C=bitpacked record + DISP_START:bit8; + RESERVED0 :bit24; + end; + + TCRT0D=bitpacked record + DISP_START:bit8; + RESERVED0 :bit24; + end; + + TCRT0E=bitpacked record + CURSOR_LOC_HI:bit8; + RESERVED0 :bit24; + end; + + TCRT0F=bitpacked record + CURSOR_LOC_LO:bit8; + RESERVED0 :bit24; + end; + + TCRT10=bitpacked record + V_SYNC_START:bit8; + RESERVED0 :bit24; + end; + + TCRT11=bitpacked record + V_SYNC_END :bit4; + V_INTR_CLR :bit1; + V_INTR_EN :bit1; + SEL5_REFRESH_CYC:bit1; + C0T7_WR_ONLY :bit1; + RESERVED0 :bit24; + end; + + TCRT12=bitpacked record + V_DISP_END:bit8; + RESERVED0 :bit24; + end; + + TCRT13=bitpacked record + DISP_PITCH:bit8; + RESERVED0 :bit24; + end; + + TCRT14=bitpacked record + UNDRLN_LOC :bit5; + ADDR_CNT_BY4:bit1; + DOUBLE_WORD :bit1; + RESERVED0 :bit25; + end; + + TCRT15=bitpacked record + V_BLANK_START:bit8; + RESERVED0 :bit24; + end; + + TCRT16=bitpacked record + V_BLANK_END:bit8; + RESERVED0 :bit24; + end; + + TCRT17=bitpacked record + RA0_AS_A13B :bit1; + RA1_AS_A14B :bit1; + VCOUNT_BY2 :bit1; + ADDR_CNT_BY2:bit1; + RESERVED0 :bit1; + WRAP_A15TOA0:bit1; + BYTE_MODE :bit1; + CRTC_SYNC_EN:bit1; + RESERVED1 :bit24; + end; + + TCRT18=bitpacked record + LINE_CMP :bit8; + RESERVED0:bit24; + end; + + TCRT1E=bitpacked record + RESERVED0 :bit1; + GRPH_DEC_RD1:bit1; + RESERVED1 :bit30; + end; + + TCRT1F=bitpacked record + GRPH_DEC_RD0:bit8; + RESERVED0 :bit24; + end; + + TCRT22=bitpacked record + GRPH_LATCH_DATA:bit8; + RESERVED0 :bit24; + end; + + TGENS0=bitpacked record + RESERVED0 :bit4; + SENSE_SWITCH:bit1; + RESERVED1 :bit2; + CRT_INTR :bit1; + RESERVED2 :bit24; + end; + + TGENS1=bitpacked record + NO_DISPLAY :bit1; + RESERVED0 :bit2; + VGA_VSTATUS :bit1; + PIXEL_READ_BACK:bit2; + RESERVED1 :bit26; + end; + + TGRA00=bitpacked record + GRPH_SET_RESET0:bit1; + GRPH_SET_RESET1:bit1; + GRPH_SET_RESET2:bit1; + GRPH_SET_RESET3:bit1; + RESERVED0 :bit28; + end; + + TGRA01=bitpacked record + GRPH_SET_RESET_ENA0:bit1; + GRPH_SET_RESET_ENA1:bit1; + GRPH_SET_RESET_ENA2:bit1; + GRPH_SET_RESET_ENA3:bit1; + RESERVED0 :bit28; + end; + + TGRA02=bitpacked record + GRPH_CCOMP:bit4; + RESERVED0 :bit28; + end; + + TGRA03=bitpacked record + GRPH_ROTATE:bit3; + GRPH_FN_SEL:bit2; + RESERVED0 :bit27; + end; + + TGRA04=bitpacked record + GRPH_RMAP:bit2; + RESERVED0:bit30; + end; + + TGRA05=bitpacked record + GRPH_WRITE_MODE:bit2; + RESERVED0 :bit1; + GRPH_READ1 :bit1; + CGA_ODDEVEN :bit1; + GRPH_OES :bit1; + GRPH_PACK :bit1; + RESERVED1 :bit25; + end; + + TGRA06=bitpacked record + GRPH_GRAPHICS:bit1; + GRPH_ODDEVEN :bit1; + GRPH_ADRSEL :bit2; + RESERVED0 :bit28; + end; + + TGRA07=bitpacked record + GRPH_XCARE0:bit1; + GRPH_XCARE1:bit1; + GRPH_XCARE2:bit1; + GRPH_XCARE3:bit1; + RESERVED0 :bit28; + end; + + TGRA08=bitpacked record + GRPH_BMSK:bit8; + RESERVED0:bit24; + end; + + TKHFS0=bit32; + + TKHFS1=bit32; + + TKHFS2=bit32; + + TKHFS3=bit32; + + TKSIG0=bit32; + + TKSIG1=bit32; + + TKSIG2=bit32; + + TKSIG3=bit32; + + TSEQ00=bitpacked record + SEQ_RST0B:bit1; + SEQ_RST1B:bit1; + RESERVED0:bit30; + end; + + TSEQ01=bitpacked record + SEQ_DOT8 :bit1; + RESERVED0 :bit1; + SEQ_SHIFT2 :bit1; + SEQ_PCLKBY2:bit1; + SEQ_SHIFT4 :bit1; + SEQ_MAXBW :bit1; + RESERVED1 :bit26; + end; + + TSEQ02=bitpacked record + SEQ_MAP0_EN:bit1; + SEQ_MAP1_EN:bit1; + SEQ_MAP2_EN:bit1; + SEQ_MAP3_EN:bit1; + RESERVED0 :bit28; + end; + + TSEQ03=bitpacked record + SEQ_FONT_B1:bit1; + SEQ_FONT_B2:bit1; + SEQ_FONT_A1:bit1; + SEQ_FONT_A2:bit1; + SEQ_FONT_B0:bit1; + SEQ_FONT_A0:bit1; + RESERVED0 :bit26; + end; + + TSEQ04=bitpacked record + RESERVED0 :bit1; + SEQ_256K :bit1; + SEQ_ODDEVEN:bit1; + SEQ_CHAIN :bit1; + RESERVED1 :bit28; + end; + + TATTR00=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR01=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR02=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR03=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR04=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR05=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR06=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR07=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR08=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR09=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0A=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0B=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0C=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0D=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0E=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR0F=bitpacked record + ATTR_PAL :bit6; + RESERVED0:bit26; + end; + + TATTR10=bitpacked record + ATTR_GRPH_MODE :bit1; + ATTR_MONO_EN :bit1; + ATTR_LGRPH_EN :bit1; + ATTR_BLINK_EN :bit1; + RESERVED0 :bit1; + ATTR_PANTOPONLY:bit1; + ATTR_PCLKBY2 :bit1; + ATTR_CSEL_EN :bit1; + RESERVED1 :bit24; + end; + + TATTR11=bitpacked record + ATTR_OVSC:bit8; + RESERVED0:bit24; + end; + + TATTR12=bitpacked record + ATTR_MAP_EN:bit4; + ATTR_VSMUX :bit2; + RESERVED0 :bit26; + end; + + TATTR13=bitpacked record + ATTR_PPAN:bit4; + RESERVED0:bit28; + end; + + TATTR14=bitpacked record + ATTR_CSEL1:bit2; + ATTR_CSEL2:bit2; + RESERVED0 :bit28; + end; + + TATTRDR=bitpacked record + ATTR_DATA:bit8; + RESERVED0:bit24; + end; + + TATTRDW=bitpacked record + ATTR_DATA:bit8; + RESERVED0:bit24; + end; + + TGENENB=bitpacked record + BLK_IO_BASE:bit8; + RESERVED0 :bit24; + end; + + THEADER=bitpacked record + HEADER_TYPE:bit7; + DEVICE_TYPE:bit1; + RESERVED0 :bit24; + end; + + TSMC_PC=bitpacked record + RESERVED0:bit30; + RESERVED1:bit2; + end; + + TSQ_CMD=bitpacked record + CMD :bit3; + RESERVED0 :bit1; + MODE :bit3; + CHECK_VMID:bit1; + DATA :bit3; + RESERVED1 :bit5; + WAVE_ID :bit4; + SIMD_ID :bit2; + RESERVED2 :bit2; + QUEUE_ID :bit3; + RESERVED3 :bit1; + VM_ID :bit4; + end; + + TSTATUS=bitpacked record + RESERVED0 :bit3; + INT_STATUS :bit1; + CAP_LIST :bit1; + PCI_66_EN :bit1; + RESERVED1 :bit1; + FAST_BACK_CAPABLE :bit1; + MASTER_DATA_PARITY_ERROR:bit1; + DEVSEL_TIMING :bit2; + SIGNAL_TARGET_ABORT :bit1; + RECEIVED_TARGET_ABORT :bit1; + RECEIVED_MASTER_ABORT :bit1; + SIGNALED_SYSTEM_ERROR :bit1; + PARITY_ERROR_DETECTED :bit1; + RESERVED2 :bit16; + end; + TWD_QOS=bitpacked record DRAW_STALL:bit1; RESERVED0 :bit31; end; + TCAP_PTR=bitpacked record + CAP_PTR :bit8; + RESERVED0:bit24; + end; + + TCM_STAT=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit30; + end; + + TCOMMAND=bitpacked record + IO_ACCESS_EN :bit1; + MEM_ACCESS_EN :bit1; + BUS_MASTER_EN :bit1; + SPECIAL_CYCLE_EN :bit1; + MEM_WRITE_INVALIDATE_EN:bit1; + PAL_SNOOP_EN :bit1; + PARITY_ERROR_RESPONSE :bit1; + AD_STEPPING :bit1; + SERR_EN :bit1; + FAST_B2B_EN :bit1; + INT_DIS :bit1; + RESERVED0 :bit21; + end; + + TCP_CNTL=bitpacked record + RESERVED0:bit1; + RESERVED1:bit31; + end; + TCP_STAT=bitpacked record RESERVED0 :bit9; ROQ_RING_BUSY :bit1; @@ -66,6 +614,194 @@ type RESERVED5 :bit4; end; + TDH_TEST=bitpacked record + DH_TEST :bit1; + RESERVED0:bit31; + end; + + THDMI_GC=bitpacked record + HDMI_GC_AVMUTE :bit1; + RESERVED0 :bit1; + HDMI_GC_AVMUTE_CONT :bit1; + RESERVED1 :bit1; + HDMI_DEFAULT_PHASE :bit1; + RESERVED2 :bit3; + HDMI_PACKING_PHASE :bit4; + HDMI_PACKING_PHASE_OVERRIDE:bit1; + RESERVED3 :bit19; + end; + + TIH_CNTL=bitpacked record + ENABLE_INTR :bit1; + MC_SWAP :bit2; + MC_TRAN :bit1; + RPTR_REARM :bit1; + RESERVED0 :bit3; + CLIENT_FIFO_HIGHWATER:bit2; + MC_FIFO_HIGHWATER :bit5; + MC_WRREQ_CREDIT :bit5; + MC_WR_CLEAN_CNT :bit5; + MC_VMID :bit4; + RESERVED1 :bit3; + end; + + TIT_STAT=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit16; + end; + + TKEFUSE0=bit32; + + TKEFUSE1=bit32; + + TKEFUSE2=bit32; + + TKEFUSE3=bit32; + + TLATENCY=bitpacked record + LATENCY_TIMER:bit8; + RESERVED0 :bit24; + end; + + TMM_DATA=bit32; + + TMP_STAT=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit4; + RESERVED5:bit8; + RESERVED6:bit8; + RESERVED7:bit8; + end; + + TOVL_END=bitpacked record + OVL_Y_END:bit15; + RESERVED0:bit1; + OVL_X_END:bit15; + RESERVED1:bit1; + end; + + TPMI_CAP=bitpacked record + VERSION :bit3; + PME_CLOCK :bit1; + RESERVED0 :bit1; + DEV_SPECIFIC_INIT:bit1; + AUX_CURRENT :bit3; + D1_SUPPORT :bit1; + D2_SUPPORT :bit1; + PME_SUPPORT :bit5; + RESERVED1 :bit16; + end; + + TRE_STAT=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit19; + end; + + TSQ_DS_0=bitpacked record + OFFSET0 :bit8; + OFFSET1 :bit8; + GDS :bit1; + OP :bit8; + RESERVED0:bit1; + ENCODING :bit6; + end; + + TSQ_DS_1=bitpacked record + ADDR :bit8; + DATA0:bit8; + DATA1:bit8; + VDST :bit8; + end; + + TSQ_INST=bit32; + + TSQ_SOP1=bitpacked record + SSRC0 :bit8; + OP :bit8; + SDST :bit7; + ENCODING:bit9; + end; + + TSQ_SOP2=bitpacked record + SSRC0 :bit8; + SSRC1 :bit8; + SDST :bit7; + OP :bit7; + ENCODING:bit2; + end; + + TSQ_SOPC=bitpacked record + SSRC0 :bit8; + SSRC1 :bit8; + OP :bit7; + ENCODING:bit9; + end; + + TSQ_SOPK=bitpacked record + SIMM16 :bit16; + SDST :bit7; + OP :bit5; + ENCODING:bit4; + end; + + TSQ_SOPP=bitpacked record + SIMM16 :bit16; + OP :bit7; + ENCODING:bit9; + end; + + TSQ_VOP1=bitpacked record + SRC0 :bit9; + OP :bit8; + VDST :bit8; + ENCODING:bit7; + end; + + TSQ_VOP2=bitpacked record + SRC0 :bit9; + VSRC1 :bit8; + VDST :bit8; + OP :bit6; + ENCODING:bit1; + end; + + TSQ_VOPC=bitpacked record + SRC0 :bit9; + VSRC1 :bit8; + OP :bit8; + ENCODING:bit7; + end; + TTA_CNTL=bitpacked record FX_XNACK_CREDIT:bit7; RESERVED0 :bit2; @@ -97,6 +833,67 @@ type RESERVED4 :bit8; end; + TVGA_HDP=bitpacked record + RESERVED0:bit1; + RESERVED1:bit5; + RESERVED2:bit1; + RESERVED3:bit6; + RESERVED4:bit1; + RESERVED5:bit15; + RESERVED6:bit1; + RESERVED7:bit1; + RESERVED8:bit1; + end; + + TVGA_REG=bitpacked record + RESERVED0:bit4; + RESERVED1:bit4; + RESERVED2:bit4; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit8; + RESERVED6:bit4; + RESERVED7:bit1; + RESERVED8:bit1; + RESERVED9:bit4; + end; + + TBUS_CNTL=bitpacked record + BIOS_ROM_WRT_EN :bit1; + BIOS_ROM_DIS :bit1; + PMI_IO_DIS :bit1; + PMI_MEM_DIS :bit1; + PMI_BM_DIS :bit1; + PMI_INT_DIS :bit1; + VGA_REG_COHERENCY_DIS :bit1; + VGA_MEM_COHERENCY_DIS :bit1; + BIF_ERR_RTR_BKPRESSURE_EN:bit1; + RESERVED0 :bit1; + SET_AZ_TC :bit3; + SET_MC_TC :bit3; + ZERO_BE_WR_EN :bit1; + ZERO_BE_RD_EN :bit1; + RD_STALL_IO_WR :bit1; + RESERVED1 :bit13; + end; + + TCNV_MODE=bitpacked record + RESERVED0 :bit8; + CNV_FRAME_CAPTURE_RATE :bit2; + RESERVED1 :bit2; + CNV_WINDOW_CROP_EN :bit1; + CNV_STEREO_TYPE :bit2; + CNV_INTERLACED_MODE :bit1; + CNV_EYE_SELECTION :bit2; + CNV_STEREO_POLARITY :bit1; + CNV_INTERLACED_FIELD_ORDER:bit1; + CNV_STEREO_SPLIT :bit1; + RESERVED2 :bit3; + CNV_NEW_CONTENT :bit1; + RESERVED3 :bit6; + CNV_FRAME_CAPTURE_EN :bit1; + end; + TCP_DEBUG=bitpacked record RESERVED0 :bit6; RESERVED1 :bit1; @@ -116,6 +913,23 @@ type RESERVED15:bit1; end; + TCUR_SIZE=bitpacked record + CURSOR_HEIGHT:bit7; + RESERVED0 :bit9; + CURSOR_WIDTH :bit7; + RESERVED1 :bit9; + end; + + TDAC_DATA=bitpacked record + DAC_DATA :bit6; + RESERVED0:bit26; + end; + + TDAC_MASK=bitpacked record + DAC_MASK :bit8; + RESERVED0:bit24; + end; + TDB_DEBUG=bitpacked record DEBUG_STENCIL_COMPRESS_DISABLE :bit1; DEBUG_DEPTH_COMPRESS_DISABLE :bit1; @@ -143,6 +957,322 @@ type DISABLE_HTILE_SURFACE_SYNC :bit1; end; + TDP_VID_M=bitpacked record + DP_VID_M :bit24; + RESERVED0:bit8; + end; + + TDP_VID_N=bitpacked record + DP_VID_N :bit24; + RESERVED0:bit8; + end; + + TFBC_CNTL=bitpacked record + FBC_GRPH_COMP_EN :bit1; + FBC_SRC_SEL :bit3; + RESERVED0 :bit12; + FBC_COHERENCY_MODE :bit2; + RESERVED1 :bit7; + FBC_SOFT_COMPRESS_EN:bit1; + RESERVED2 :bit5; + FBC_EN :bit1; + end; + + TFBC_MISC=bitpacked record + FBC_DECOMPRESS_ERROR :bit2; + FBC_STOP_ON_ERROR :bit1; + FBC_INVALIDATE_ON_ERROR :bit1; + FBC_ERROR_PIXEL :bit4; + FBC_DIVIDE_X :bit2; + FBC_DIVIDE_Y :bit1; + FBC_RSM_WRITE_VALUE :bit1; + FBC_RSM_UNCOMP_DATA_IMMEDIATELY:bit1; + RESERVED0 :bit3; + FBC_DECOMPRESS_ERROR_CLEAR :bit1; + RESERVED1 :bit3; + FBC_RESET_AT_ENABLE :bit1; + FBC_RESET_AT_DISABLE :bit1; + RESERVED2 :bit2; + FBC_SLOW_REQ_INTERVAL :bit5; + RESERVED3 :bit3; + end; + + TGENFC_RD=bitpacked record + RESERVED0 :bit3; + VSYNC_SEL_R:bit1; + RESERVED1 :bit28; + end; + + TGENFC_WT=bitpacked record + RESERVED0 :bit3; + VSYNC_SEL_W:bit1; + RESERVED1 :bit28; + end; + + TGENMO_RD=bitpacked record + GENMO_MONO_ADDRESS_B:bit1; + VGA_RAM_EN :bit1; + VGA_CKSEL :bit2; + RESERVED0 :bit1; + ODD_EVEN_MD_PGSEL :bit1; + VGA_HSYNC_POL :bit1; + VGA_VSYNC_POL :bit1; + RESERVED1 :bit24; + end; + + TGENMO_WT=bitpacked record + GENMO_MONO_ADDRESS_B:bit1; + VGA_RAM_EN :bit1; + VGA_CKSEL :bit2; + RESERVED0 :bit1; + ODD_EVEN_MD_PGSEL :bit1; + VGA_HSYNC_POL :bit1; + VGA_VSYNC_POL :bit1; + RESERVED1 :bit24; + end; + + THW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + HW_16_DEBUG:bit1; + HW_17_DEBUG:bit1; + HW_18_DEBUG:bit1; + HW_19_DEBUG:bit1; + HW_20_DEBUG:bit1; + HW_21_DEBUG:bit1; + HW_22_DEBUG:bit1; + HW_23_DEBUG:bit1; + HW_24_DEBUG:bit1; + HW_25_DEBUG:bit1; + HW_26_DEBUG:bit1; + HW_27_DEBUG:bit1; + HW_28_DEBUG:bit1; + HW_29_DEBUG:bit1; + HW_30_DEBUG:bit1; + HW_31_DEBUG:bit1; + end; + + TI2C_DATA=bitpacked record + RESERVED0:bit8; + RESERVED1:bit24; + end; + + TIH_DEBUG=bitpacked record + RB_FULL_DRAIN_ENABLE :bit1; + WPTR_OVERFLOW_ENABLE :bit1; + MC_WR_FIFO_BLOCK_ENABLE:bit1; + RESERVED0 :bit29; + end; + + TINT_MASK=bitpacked record + RESERVED0:bit1; + RESERVED1:bit3; + RESERVED2:bit1; + RESERVED3:bit25; + RESERVED4:bit1; + RESERVED5:bit1; + end; + + TLB_DEBUG=bit32; + + TLINK_CAP=bitpacked record + LINK_SPEED :bit4; + LINK_WIDTH :bit6; + PM_SUPPORT :bit2; + L0S_EXIT_LATENCY :bit3; + L1_EXIT_LATENCY :bit3; + CLOCK_POWER_MANAGEMENT :bit1; + SURPRISE_DOWN_ERR_REPORTING:bit1; + DL_ACTIVE_REPORTING_CAPABLE:bit1; + LINK_BW_NOTIFICATION_CAP :bit1; + ASPM_OPTIONALITY_COMPLIANCE:bit1; + RESERVED0 :bit1; + PORT_NUMBER :bit8; + end; + + TMC_RD_CB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_RD_DB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_WR_CB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_WR_DB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMM_INDEX=bitpacked record + MM_OFFSET:bit31; + MM_APER :bit1; + end; + + TMSI_MASK=bit32; + + TPCIE_CAP=bitpacked record + VERSION :bit4; + DEVICE_TYPE :bit4; + SLOT_IMPLEMENTED:bit1; + INT_MESSAGE_NUM :bit5; + RESERVED0 :bit1; + RESERVED1 :bit17; + end; + + TPLL_CNTL=bitpacked record + PLL_RESET :bit1; + PLL_POWER_DOWN :bit1; + PLL_BYPASS_CAL :bit1; + PLL_POST_DIV_SRC :bit1; + PLL_VCOREF :bit2; + PLL_PCIE_REFCLK_SEL :bit1; + PLL_ANTIGLITCH_RESETB :bit1; + PLL_CALREF :bit2; + PLL_CAL_BYPASS_REFDIV :bit1; + PLL_REFCLK_SEL :bit2; + PLL_ANTI_GLITCH_RESET :bit1; + PLL_XOCLK_DRV_R_EN :bit1; + RESERVED0 :bit1; + PLL_REF_DIV_SRC :bit3; + PLL_LOCK_FREQ_SEL :bit1; + PLL_CALIB_DONE :bit1; + PLL_LOCKED :bit1; + PLL_REFCLK_RECV_EN :bit1; + PLL_REFCLK_RECV_SEL :bit1; + PLL_TIMING_MODE_STATUS:bit2; + PLL_DIG_SPARE :bit6; + end; + + TRLC_CNTL=bitpacked record + RLC_ENABLE_F32 :bit1; + FORCE_RETRY :bit1; + READ_CACHE_DISABLE :bit1; + RLC_STEP_F32 :bit1; + SOFT_RESET_DEBUG_MODE:bit1; + RESERVED0 :bit3; + RESERVED :bit24; + end; + + TRLC_STAT=bitpacked record + RLC_BUSY :bit1; + RLC_GPM_BUSY:bit1; + RLC_SPM_BUSY:bit1; + RLC_SRM_BUSY:bit1; + RESERVED :bit28; + end; + + TRLC_VMID=bitpacked record + RESERVED0:bit4; + RESERVED1:bit28; + end; + + TROM_CNTL=bitpacked record + RESERVED0 :bit1; + SCK_OVERWRITE :bit1; + CLOCK_GATING_EN :bit1; + RESERVED1 :bit5; + CSB_ACTIVE_TO_SCK_SETUP_TIME:bit8; + CSB_ACTIVE_TO_SCK_HOLD_TIME :bit8; + SCK_PRESCALE_REFCLK :bit4; + SCK_PRESCALE_CRYSTAL_CLK :bit4; + end; + + TROM_DATA=bit32; + + TSCL_MODE=bitpacked record + SCL_MODE :bit2; + RESERVED0 :bit2; + SCL_PSCL_EN:bit1; + RESERVED1 :bit27; + end; + + TSDMA0_ID=bitpacked record + DEVICE_ID:bit8; + RESERVED0:bit24; + end; + + TSDMA1_ID=bitpacked record + DEVICE_ID:bit8; + RESERVED0:bit24; + end; + + TSEQ8_IDX=bitpacked record + SEQ_IDX :bit3; + RESERVED0:bit29; + end; + + TSMC_PC_C=bit32; + + TSQ_EXP_0=bitpacked record + EN :bit4; + TGT :bit6; + COMPR :bit1; + DONE :bit1; + VM :bit1; + RESERVED0:bit13; + ENCODING :bit6; + end; + + TSQ_EXP_1=bitpacked record + VSRC0:bit8; + VSRC1:bit8; + VSRC2:bit8; + VSRC3:bit8; + end; + TTCA_CTRL=bitpacked record HOLE_TIMEOUT:bit4; RESERVED0 :bit28; @@ -177,11 +1307,147 @@ type RESERVED2 :bit2; end; + TVGA_CRTC=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit5; + RESERVED3:bit4; + RESERVED4:bit11; + RESERVED5:bit8; + RESERVED6:bit2; + end; + + TVGA_MAIN=bitpacked record + RESERVED0 :bit4; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit2; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit2; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit1; + RESERVED25:bit1; + RESERVED26:bit1; + end; + + TVGA_TEXT=bitpacked record + RESERVED0 :bit4; + RESERVED1 :bit4; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit2; + RESERVED8 :bit3; + RESERVED9 :bit3; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + end; + + TVM_DEBUG=bit32; + + TVM_L2_CG=bitpacked record + RESERVED0 :bit6; + OFFDLY :bit6; + RESERVED1 :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + _OVERRIDE :bit1; + RESERVED2 :bit11; + end; + + TBACO_CNTL=bitpacked record + BACO_EN :bit1; + BACO_BCLK_OFF :bit1; + BACO_ISO_DIS :bit1; + BACO_POWER_OFF :bit1; + BACO_RESET_EN :bit1; + BACO_HANG_PROTECTION_EN :bit1; + BACO_MODE :bit1; + BACO_ANA_ISO_DIS :bit1; + RCU_BIF_CONFIG_DONE :bit1; + PWRGOOD_BF :bit1; + PWRGOOD_GPIO :bit1; + PWRGOOD_MEM :bit1; + PWRGOOD_DVO :bit1; + PWRGOOD_IDSC :bit1; + RESERVED0 :bit2; + BACO_POWER_OFF_DRAM :bit1; + BACO_BF_MEM_PHY_ISO_CNTRL:bit1; + BACO_BIF_SCLK_SWITCH :bit1; + RESERVED1 :bit13; + end; + + TBIF_FB_EN=bitpacked record + FB_READ_EN :bit1; + FB_WRITE_EN:bit1; + RESERVED0 :bit30; + end; + + TCORB_SIZE=bitpacked record + CORB_SIZE :bit2; + RESERVED0 :bit2; + CORB_SIZE_CAPABILITY:bit4; + RESERVED1 :bit24; + end; + + TCP_CONFIG=bitpacked record + RESERVED0 :bit8; + CP_RDREQ_URG:bit4; + RESERVED1 :bit4; + CP_REQ_TRAN :bit1; + RESERVED2 :bit15; + end; + TCP_PIPEID=bitpacked record PIPE_ID :bit2; RESERVED0:bit30; end; + TCP_RINGID=bitpacked record + RINGID :bit2; + RESERVED0:bit30; + end; + + TCRTC8_IDX=bitpacked record + VCRTC_IDX:bit6; + RESERVED0:bit26; + end; + + TCUR2_SIZE=bitpacked record + CURSOR2_HEIGHT:bit7; + RESERVED0 :bit9; + CURSOR2_WIDTH :bit7; + RESERVED1 :bit9; + end; + TDB_DEBUG2=bitpacked record ALLOW_COMPZ_BYTE_MASKING :bit1; DISABLE_TC_ZRANGE_L0_CACHE :bit1; @@ -265,12 +1531,495 @@ type ZRANGE_PRECISION :bit1; end; + TDCP_DEBUG=bit32; + + TDEVICE_ID=bitpacked record + DEVICE_ID:bit16; + RESERVED0:bit16; + end; + + TDMCU_CTRL=bitpacked record + RESET_UC :bit1; + IGNORE_PWRMGT :bit1; + DISABLE_IRQ_TO_UC :bit1; + DISABLE_XIRQ_TO_UC:bit1; + DMCU_ENABLE :bit1; + RESERVED0 :bit11; + UC_REG_RD_TIMEOUT :bit16; + end; + + TDP_CONFIG=bitpacked record + DP_UDI_LANES:bit2; + RESERVED0 :bit30; + end; + + TGB_GPU_ID=bitpacked record + GPU_ID :bit4; + RESERVED0:bit28; + end; + + TGPIOPAD_A=bitpacked record + GPIO_A :bit31; + RESERVED0:bit1; + end; + + TGPIOPAD_Y=bitpacked record + GPIO_Y :bit31; + RESERVED0:bit1; + end; + TGRBM_CNTL=bitpacked record READ_TIMEOUT :bit8; RESERVED0 :bit23; REPORT_LAST_RDERR:bit1; end; + TGRPH8_IDX=bitpacked record + GRPH_IDX :bit4; + RESERVED0:bit28; + end; + + THFS_SEED0=bit32; + + THFS_SEED1=bit32; + + THFS_SEED2=bit32; + + THFS_SEED3=bit32; + + TIH_STATUS=bitpacked record + IDLE :bit1; + INPUT_IDLE :bit1; + RB_IDLE :bit1; + RB_FULL :bit1; + RB_FULL_DRAIN :bit1; + RB_OVERFLOW :bit1; + MC_WR_IDLE :bit1; + MC_WR_STALL :bit1; + MC_WR_CLEAN_PENDING:bit1; + MC_WR_CLEAN_STALL :bit1; + BIF_INTERRUPT_LINE :bit1; + SWITCH_READY :bit1; + RESERVED0 :bit20; + end; + + TIT_INT_EN=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit9; + end; + + TKSESSION0=bit32; + + TKSESSION1=bit32; + + TKSESSION2=bit32; + + TKSESSION3=bit32; + + TLBV_DEBUG=bit32; + + TLB_DEBUG2=bit32; + + TLB_DEBUG3=bit32; + + TLINK_CAP2=bitpacked record + RESERVED0 :bit1; + SUPPORTED_LINK_SPEED:bit7; + CROSSLINK_SUPPORTED :bit1; + RESERVED1 :bit23; + end; + + TLINK_CNTL=bitpacked record + PM_CONTROL :bit2; + RESERVED0 :bit1; + READ_CPL_BOUNDARY :bit1; + LINK_DIS :bit1; + RETRAIN_LINK :bit1; + COMMON_CLOCK_CFG :bit1; + EXTENDED_SYNC :bit1; + CLOCK_POWER_MANAGEMENT_EN :bit1; + HW_AUTONOMOUS_WIDTH_DISABLE:bit1; + LINK_BW_MANAGEMENT_INT_EN :bit1; + LINK_AUTONOMOUS_BW_INT_EN :bit1; + RESERVED1 :bit20; + end; + + TMCIF_VMID=bitpacked record + MCIF_WR_VMID:bit4; + VIP_WR_VMID :bit4; + RESERVED0 :bit24; + end; + + TMC_ARB_CG=bitpacked record + CG_ARB_REQ :bit8; + CG_ARB_RESP:bit8; + RSV_0 :bit8; + RSV_1 :bit8; + end; + + TMC_CONFIG=bitpacked record + MCDW_WR_ENABLE :bit1; + MCDX_WR_ENABLE :bit1; + MCDY_WR_ENABLE :bit1; + MCDZ_WR_ENABLE :bit1; + MCDS_WR_ENABLE :bit1; + MCDT_WR_ENABLE :bit1; + MCDU_WR_ENABLE :bit1; + MCDV_WR_ENABLE :bit1; + MC_RD_ENABLE :bit3; + RESERVED0 :bit20; + MCC_INDEX_MODE_ENABLE:bit1; + end; + + TMC_RD_HUB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_RD_TC0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_RD_TC1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_SEQ_CG=bitpacked record + CG_SEQ_REQ :bit8; + CG_SEQ_RESP:bit8; + SEQ_CG_REQ :bit8; + SEQ_CG_RESP:bit8; + end; + + TMC_WR_HUB=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_WR_TC0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_WR_TC1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAX_BURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM:bit1; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMIN_GRANT=bitpacked record + MIN_GNT :bit8; + RESERVED0:bit24; + end; + + TMP_INT_EN=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit8; + end; + + TMVP_DEBUG=bitpacked record + MVP_SWAP_LOCK_IN_EN :bit1; + MVP_FLOW_CONTROL_IN_EN :bit1; + MVP_SWAP_LOCK_IN_SEL :bit1; + MVP_FLOW_CONTROL_IN_SEL :bit1; + MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP :bit1; + MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP :bit1; + MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR:bit1; + MVP_DIS_READ_POINTER_RESET_DELAY :bit1; + MVP_DEBUG_BITS :bit24; + end; + + TOVL_ALPHA=bitpacked record + RESERVED0:bit8; + RESERVED1:bit24; + end; + + TOVL_PITCH=bitpacked record + OVL_PITCH:bit15; + RESERVED0:bit17; + end; + + TOVL_START=bitpacked record + OVL_Y_START:bit14; + RESERVED0 :bit2; + OVL_X_START:bit14; + RESERVED1 :bit2; + end; + + TPCIE_CNTL=bitpacked record + HWINIT_WR_LOCK :bit1; + LC_HOT_PLUG_DELAY_SEL :bit3; + RESERVED0 :bit3; + UR_ERR_REPORT_DIS :bit1; + PCIE_MALFORM_ATOMIC_OPS :bit1; + PCIE_HT_NP_MEM_WRITE :bit1; + RX_SB_ADJ_PAYLOAD_SIZE :bit3; + RESERVED1 :bit2; + RX_RCB_ATS_UC_DIS :bit1; + RX_RCB_REORDER_EN :bit1; + RX_RCB_INVALID_SIZE_DIS :bit1; + RX_RCB_UNEXP_CPL_DIS :bit1; + RX_RCB_CPL_TIMEOUT_TEST_MODE:bit1; + RX_RCB_WRONG_PREFIX_DIS :bit1; + RX_RCB_WRONG_ATTR_DIS :bit1; + RX_RCB_WRONG_FUNCNUM_DIS :bit1; + RX_ATS_TRAN_CPL_SPLIT_DIS :bit1; + TX_CPL_DEBUG :bit6; + RX_IGNORE_LTR_MSG_UR :bit1; + RX_CPL_POSTED_REQ_ORD_EN :bit1; + end; + + TPCIE_DATA=bit32; + + TPCIE_FC_P=bitpacked record + PD_CREDITS:bit8; + PH_CREDITS:bit8; + RESERVED0 :bit16; + end; + + TRIRB_SIZE=bitpacked record + RIRB_SIZE :bit2; + RESERVED0 :bit2; + RIRB_SIZE_CAPABILITY:bit4; + RESERVED1 :bit24; + end; + + TRLC_DEBUG=bit32; + + TROM_INDEX=bitpacked record + ROM_INDEX:bit24; + RESERVED0:bit8; + end; + + TROM_START=bitpacked record + ROM_START:bit24; + RESERVED0:bit8; + end; + + TSCLV_MODE=bitpacked record + SCL_MODE :bit1; + RESERVED0 :bit3; + SCL_PSCL_EN :bit1; + RESERVED1 :bit3; + SCL_INTERLACE_SOURCE:bit2; + RESERVED2 :bit22; + end; + + TSCL_DEBUG=bit32; + + TSEQ8_DATA=bitpacked record + SEQ_DATA :bit8; + RESERVED0:bit24; + end; + + TSQ_CONFIG=bitpacked record + UNUSED :bit8; + DEBUG_EN :bit1; + DEBUG_SINGLE_MEMOP :bit1; + DEBUG_ONE_INST_CLAUSE :bit1; + RESERVED0 :bit1; + EARLY_TA_DONE_DISABLE :bit1; + DUA_FLAT_LOCK_ENABLE :bit1; + DUA_LDS_BYPASS_DISABLE :bit1; + DUA_FLAT_LDS_PINGPONG_DISABLE:bit1; + DISABLE_VMEM_SOFT_CLAUSE :bit1; + DISABLE_SMEM_SOFT_CLAUSE :bit1; + ENABLE_HIPRIO_ON_EXP_RDY_VS :bit1; + PRIO_VAL_ON_EXP_RDY_VS :bit2; + REPLAY_SLEEP_CNT :bit4; + RESERVED1 :bit7; + end; + + TSQ_FLAT_0=bitpacked record + RESERVED0:bit16; + GLC :bit1; + SLC :bit1; + OP :bit7; + RESERVED1:bit1; + ENCODING :bit6; + end; + + TSQ_FLAT_1=bitpacked record + ADDR :bit8; + DATA :bit8; + RESERVED0:bit7; + TFE :bit1; + VDST :bit8; + end; + + TSQ_MIMG_0=bitpacked record + RESERVED0:bit8; + DMASK :bit4; + UNORM :bit1; + GLC :bit1; + DA :bit1; + R128 :bit1; + TFE :bit1; + LWE :bit1; + OP :bit7; + SLC :bit1; + ENCODING :bit6; + end; + + TSQ_MIMG_1=bitpacked record + VADDR :bit8; + VDATA :bit8; + SRSRC :bit5; + SSAMP :bit5; + RESERVED0:bit5; + D16 :bit1; + end; + + TSQ_SMEM_0=bitpacked record + SBASE :bit6; + SDATA :bit7; + RESERVED0:bit3; + GLC :bit1; + IMM :bit1; + OP :bit8; + ENCODING :bit6; + end; + + TSQ_SMEM_1=bitpacked record + OFFSET :bit20; + RESERVED0:bit12; + end; + + TSQ_VINTRP=bitpacked record + VSRC :bit8; + ATTRCHAN:bit2; + ATTR :bit6; + OP :bit2; + VDST :bit8; + ENCODING:bit6; + end; + + TSQ_VOP3_0=bitpacked record + VDST :bit8; + ABS :bit3; + RESERVED0:bit4; + CLAMP :bit1; + OP :bit10; + ENCODING :bit6; + end; + + TSQ_VOP3_1=bitpacked record + SRC0:bit9; + SRC1:bit9; + SRC2:bit9; + OMOD:bit2; + NEG :bit3; + end; + + TSRBM_CNTL=bitpacked record + READ_TIMEOUT :bit10; + RESERVED0 :bit6; + PWR_REQUEST_HALT :bit1; + COMBINE_SYSTEM_MC :bit1; + REPORT_LAST_RDERR :bit1; + PWR_GFX3D_REQUEST_HALT:bit1; + RESERVED1 :bit12; + end; + + TSUB_CLASS=bitpacked record + SUB_CLASS:bit8; + RESERVED0:bit24; + end; + TTA_STATUS=bitpacked record RESERVED0 :bit12; FG_PFIFO_EMPTYB:bit1; @@ -305,12 +2054,303 @@ type BUSY :bit1; end; + TTMDS_CNTL=bitpacked record + TMDS_SYNC_PHASE :bit1; + RESERVED0 :bit3; + TMDS_PIXEL_ENCODING:bit1; + RESERVED1 :bit3; + TMDS_COLOR_FORMAT :bit2; + RESERVED2 :bit22; + end; + + TUNP_DEBUG=bit32; + + TVENDOR_ID=bitpacked record + VENDOR_ID:bit16; + RESERVED0:bit16; + end; + + TV_COUNTER=bitpacked record + RESERVED0:bit14; + RESERVED1:bit18; + end; + + TWB_ENABLE=bitpacked record + WB_ENABLE:bit1; + RESERVED0:bit31; + end; + + TADAPTER_ID=bitpacked record + SUBSYSTEM_VENDOR_ID:bit16; + SUBSYSTEM_ID :bit16; + end; + + TBASE_CLASS=bitpacked record + BASE_CLASS:bit8; + RESERVED0 :bit24; + end; + + TBLND_DEBUG=bitpacked record + BLND_CNV_MUX_SELECT:bit1; + BLND_DEBUG :bit31; + end; + + TCACHE_LINE=bitpacked record + CACHE_LINE_SIZE:bit8; + RESERVED0 :bit24; + end; + + TCG_FPS_CNT=bit32; + + TCLIENT0_BM=bit32; + + TCLIENT0_K0=bit32; + + TCLIENT0_K1=bit32; + + TCLIENT0_K2=bit32; + + TCLIENT0_K3=bit32; + + TCLIENT1_BM=bit32; + + TCLIENT1_K0=bit32; + + TCLIENT1_K1=bit32; + + TCLIENT1_K2=bit32; + + TCLIENT1_K3=bit32; + + TCLIENT2_BM=bit32; + + TCLIENT2_K0=bit32; + + TCLIENT2_K1=bit32; + + TCLIENT2_K2=bit32; + + TCLIENT2_K3=bit32; + + TCLIENT3_BM=bit32; + + TCLIENT3_K0=bit32; + + TCLIENT3_K1=bit32; + + TCLIENT3_K2=bit32; + + TCLIENT3_K3=bit32; + + TCLIENT4_BM=bit32; + + TCLIENT4_K0=bit32; + + TCLIENT4_K1=bit32; + + TCLIENT4_K2=bit32; + + TCLIENT4_K3=bit32; + + TCNV_UPDATE=bitpacked record + CNV_UPDATE_PENDING:bit1; + RESERVED0 :bit7; + CNV_UPDATE_TAKEN :bit1; + RESERVED1 :bit7; + CNV_UPDATE_LOCK :bit1; + RESERVED2 :bit15; + end; + TCP_DFY_CMD=bitpacked record OFFSET :bit9; RESERVED0:bit7; SIZE :bit16; end; + TCP_ME_CNTL=bitpacked record + RESERVED0 :bit4; + CE_INVALIDATE_ICACHE :bit1; + RESERVED1 :bit1; + PFP_INVALIDATE_ICACHE:bit1; + RESERVED2 :bit1; + ME_INVALIDATE_ICACHE :bit1; + RESERVED3 :bit7; + CE_PIPE0_RESET :bit1; + RESERVED4 :bit1; + PFP_PIPE0_RESET :bit1; + RESERVED5 :bit1; + ME_PIPE0_RESET :bit1; + RESERVED6 :bit3; + CE_HALT :bit1; + CE_STEP :bit1; + PFP_HALT :bit1; + PFP_STEP :bit1; + ME_HALT :bit1; + ME_STEP :bit1; + RESERVED7 :bit2; + end; + + TCP_RB_BASE=bit32; + + TCP_RB_CNTL=bitpacked record + RB_BUFSZ :bit6; + RESERVED0 :bit2; + RB_BLKSZ :bit6; + RESERVED1 :bit1; + MTYPE :bit2; + BUF_SWAP :bit2; + RESERVED2 :bit1; + MIN_AVAILSZ :bit2; + MIN_IB_AVAILSZ:bit2; + CACHE_POLICY :bit1; + RESERVED3 :bit2; + RB_NO_UPDATE :bit1; + RESERVED4 :bit3; + RB_RPTR_WR_ENA:bit1; + end; + + TCP_RB_RPTR=bitpacked record + RB_RPTR :bit20; + RESERVED0:bit12; + end; + + TCP_RB_VMID=bitpacked record + RB0_VMID :bit4; + RESERVED0:bit4; + RB1_VMID :bit4; + RESERVED1:bit4; + RB2_VMID :bit4; + RESERVED2:bit12; + end; + + TCP_RB_WPTR=bitpacked record + RB_WPTR :bit20; + RESERVED0:bit12; + end; + + TCRTC8_DATA=bitpacked record + VCRTC_DATA:bit8; + RESERVED0 :bit24; + end; + + TCUR_COLOR1=bitpacked record + CUR_COLOR1_BLUE :bit8; + CUR_COLOR1_GREEN:bit8; + CUR_COLOR1_RED :bit8; + RESERVED0 :bit8; + end; + + TCUR_COLOR2=bitpacked record + CUR_COLOR2_BLUE :bit8; + CUR_COLOR2_GREEN:bit8; + CUR_COLOR2_RED :bit8; + RESERVED0 :bit8; + end; + + TCUR_UPDATE=bitpacked record + CURSOR_UPDATE_PENDING :bit1; + CURSOR_UPDATE_TAKEN :bit1; + RESERVED0 :bit14; + CURSOR_UPDATE_LOCK :bit1; + RESERVED1 :bit7; + CURSOR_DISABLE_MULTIPLE_UPDATE:bit1; + CURSOR_UPDATE_STEREO_MODE :bit2; + RESERVED2 :bit5; + end; + + TDAC_CRC_EN=bitpacked record + DAC_CRC_EN :bit1; + RESERVED0 :bit15; + DAC_CRC_CONT_EN:bit1; + RESERVED1 :bit15; + end; + + TDAC_ENABLE=bitpacked record + DAC_ENABLE :bit1; + DAC_RESYNC_FIFO_ENABLE :bit1; + DAC_RESYNC_FIFO_POINTER_SKEW:bit2; + DAC_RESYNC_FIFO_ERROR :bit1; + DAC_RESYNC_FIFO_ERROR_ACK :bit1; + RESERVED0 :bit2; + DAC_RESYNC_FIFO_TVOUT_SIM :bit1; + RESERVED1 :bit23; + end; + + TDCIO_DEBUG=bit32; + + TDCP_DEBUG2=bit32; + + TDEBUG_DATA=bit32; + + TDEVICE_CAP=bitpacked record + MAX_PAYLOAD_SUPPORT :bit3; + PHANTOM_FUNC :bit2; + EXTENDED_TAG :bit1; + L0S_ACCEPTABLE_LATENCY :bit3; + L1_ACCEPTABLE_LATENCY :bit3; + RESERVED0 :bit3; + ROLE_BASED_ERR_REPORTING :bit1; + RESERVED1 :bit2; + CAPTURED_SLOT_POWER_LIMIT:bit8; + CAPTURED_SLOT_POWER_SCALE:bit2; + FLR_CAPABLE :bit1; + RESERVED2 :bit3; + end; + + TDPDBG_CNTL=bitpacked record + DPDBG_ENABLE :bit1; + DPDBG_INPUT_ENABLE :bit1; + RESERVED0 :bit2; + DPDBG_SYMCLK_ON :bit1; + RESERVED1 :bit3; + DPDBG_ERROR_DETECTION_MODE:bit1; + RESERVED2 :bit7; + DPDBG_LINE_LENGTH :bit16; + end; + + TDVO_CRC_EN=bitpacked record + RESERVED0 :bit16; + DVO_CRC2_EN:bit1; + RESERVED1 :bit15; + end; + + TDVO_ENABLE=bitpacked record + DVO_ENABLE :bit1; + RESERVED0 :bit3; + DVO_PIXEL_WIDTH:bit2; + RESERVED1 :bit26; + end; + + TDVO_OUTPUT=bitpacked record + DVO_OUTPUT_ENABLE_MODE:bit2; + RESERVED0 :bit6; + DVO_CLOCK_MODE :bit1; + RESERVED1 :bit23; + end; + + TFBC_DEBUG0=bitpacked record + FBC_PERF_MUX0 :bit8; + FBC_PERF_MUX1 :bit8; + FBC_COMP_WAKE_DIS:bit1; + FBC_DEBUG0 :bit7; + FBC_DEBUG_MUX :bit8; + end; + + TFBC_DEBUG1=bit32; + + TFBC_DEBUG2=bit32; + + TFBC_STATUS=bitpacked record + FBC_ENABLE_STATUS:bit1; + RESERVED0 :bit31; + end; + + TFMT_DEBUG0=bit32; + + TFMT_DEBUG1=bit32; + + TFMT_DEBUG2=bit32; + TGDS_CONFIG=bitpacked record RESERVED0 :bit1; SH0_GPR_PHASE_SEL:bit2; @@ -320,6 +2360,47 @@ type RESERVED1 :bit23; end; + TGDS_OA_DED=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + UNUSED :bit28; + end; + + TGMCON_MASK=bitpacked record + STCTRL_BUSY_MASK_ACP_RD :bit1; + STCTRL_BUSY_MASK_ACP_WR :bit1; + STCTRL_BUSY_MASK_VCE_RD :bit1; + STCTRL_BUSY_MASK_VCE_WR :bit1; + STCTRL_SR_HANDSHAKE_MASK:bit8; + RESERVED0 :bit20; + end; + + TGMCON_MISC=bitpacked record + RESERVED0 :bit10; + RENG_EXECUTE_NOW_MODE :bit1; + RENG_EXECUTE_ON_REG_UPDATE :bit1; + RENG_SRBM_CREDITS_MCD :bit4; + STCTRL_STUTTER_EN :bit1; + STCTRL_GMC_IDLE_THRESHOLD :bit2; + STCTRL_SRBM_IDLE_THRESHOLD :bit2; + STCTRL_IGNORE_PRE_SR :bit1; + STCTRL_IGNORE_ALLOW_STOP :bit1; + STCTRL_IGNORE_SR_COMMIT :bit1; + STCTRL_IGNORE_PROTECTION_FAULT:bit1; + STCTRL_DISABLE_ALLOW_SR :bit1; + STCTRL_DISABLE_GMC_OFFLINE :bit1; + CRITICAL_REGS_LOCK :bit1; + ALLOW_DEEP_SLEEP_MODE :bit3; + STCTRL_FORCE_ALLOW_SR :bit1; + end; + + TGPIOPAD_EN=bitpacked record + GPIO_EN :bit31; + RESERVED0:bit1; + end; + TGRBM_DEBUG=bitpacked record RESERVED0 :bit1; IGNORE_RDY :bit1; @@ -334,8 +2415,560 @@ type DEBUG_BUS_FGCG_EN :bit1; end; + TGRPH8_DATA=bitpacked record + GRPH_DATA:bit8; + RESERVED0:bit24; + end; + + TGRPH_ALPHA=bitpacked record + RESERVED0:bit8; + RESERVED1:bit24; + end; + + TGRPH_PITCH=bitpacked record + GRPH_PITCH:bit15; + RESERVED0 :bit17; + end; + + TGRPH_X_END=bitpacked record + GRPH_X_END:bit15; + RESERVED0 :bit17; + end; + + TGRPH_Y_END=bitpacked record + GRPH_Y_END:bit15; + RESERVED0 :bit17; + end; + + THDP_DEBUG0=bit32; + + THDP_DEBUG1=bit32; + TIA_ENHANCE=bit32; + TIH_RB_BASE=bit32; + + TIH_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RB_FULL_DRAIN_ENABLE :bit1; + RB_GPU_TS_ENABLE :bit1; + WPTR_WRITEBACK_ENABLE:bit1; + WPTR_WRITEBACK_TIMER :bit5; + RESERVED0 :bit2; + WPTR_OVERFLOW_ENABLE :bit1; + ENABLE_INTR :bit1; + MC_SWAP :bit2; + RESERVED1 :bit1; + RPTR_REARM :bit1; + RESERVED2 :bit2; + MC_VMID :bit4; + RESERVED3 :bit3; + WPTR_OVERFLOW_CLEAR :bit1; + end; + + TIH_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit16; + RESERVED1:bit14; + end; + + TIH_RB_WPTR=bitpacked record + RB_OVERFLOW :bit1; + RESERVED0 :bit1; + OFFSET :bit16; + RB_LEFT_NONE :bit1; + RB_MAY_OVERFLOW:bit1; + RESERVED1 :bit12; + end; + + TIH_VERSION=bitpacked record + VALUE :bit12; + RESERVED0:bit20; + end; + + TLBV_DEBUG2=bit32; + + TLBV_DEBUG3=bit32; + + TLINK_CNTL2=bitpacked record + TARGET_LINK_SPEED :bit4; + ENTER_COMPLIANCE :bit1; + HW_AUTONOMOUS_SPEED_DISABLE:bit1; + SELECTABLE_DEEMPHASIS :bit1; + XMIT_MARGIN :bit3; + ENTER_MOD_COMPLIANCE :bit1; + COMPLIANCE_SOS :bit1; + COMPLIANCE_DEEMPHASIS :bit4; + RESERVED0 :bit16; + end; + + TLM_CONTROL=bitpacked record + RESERVED0 :bit1; + LoopbackSelect :bit4; + PRBSPCIeLbSelect:bit1; + LoopbackHalfRate:bit2; + LoopbackFifoPtr :bit3; + RESERVED1 :bit21; + end; + + TMC_ARB_POP=bitpacked record + ENABLE_ARB :bit1; + SPEC_OPEN :bit1; + POP_DEPTH :bit4; + WRDATAINDEX_DEPTH :bit6; + SKID_DEPTH :bit3; + WAIT_AFTER_RFSH :bit2; + QUICK_STOP :bit1; + ENABLE_TWO_PAGE :bit1; + ALLOW_EOB_BY_WRRET_STALL:bit1; + RESERVED0 :bit12; + end; + + TMC_PMG_CFG=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit4; + RESERVED13 :bit1; + RESERVED14 :bit1; + WRITE_DURING_DLOCK:bit1; + RESERVED15 :bit1; + RESERVED16 :bit4; + EARLY_ACK_ACPI :bit1; + RESERVED17 :bit1; + RESERVED18 :bit6; + end; + + TMC_SEQ_CMD=bitpacked record + ADR :bit16; + RESERVED0:bit4; + MOP :bit4; + _END :bit1; + RESERVED1:bit3; + CHAN0 :bit1; + CHAN1 :bit1; + RESERVED2:bit1; + RESERVED3:bit1; + end; + + TMP_FPS_CNT=bitpacked record + FPS_CNT :bit8; + RESERVED0:bit24; + end; + + TOVL_ENABLE=bitpacked record + OVL_ENABLE:bit1; + RESERVED0 :bit7; + OVLSCL_EN :bit1; + RESERVED1 :bit23; + end; + + TOVL_UPDATE=bitpacked record + OVL_UPDATE_PENDING :bit1; + OVL_UPDATE_TAKEN :bit1; + RESERVED0 :bit14; + OVL_UPDATE_LOCK :bit1; + RESERVED1 :bit7; + OVL_DISABLE_MULTIPLE_UPDATE:bit1; + RESERVED2 :bit7; + end; + + TPCIE_CNTL2=bitpacked record + TX_ARB_ROUND_ROBIN_EN :bit1; + TX_ARB_SLV_LIMIT :bit5; + TX_ARB_MST_LIMIT :bit5; + TX_BLOCK_TLP_ON_PM_DIS :bit1; + TX_NP_MEM_WRITE_SWP_ENCODING:bit1; + TX_ATOMIC_OPS_DISABLE :bit1; + TX_ATOMIC_ORDERING_DIS :bit1; + RESERVED0 :bit1; + SLV_MEM_LS_EN :bit1; + SLV_MEM_AGGRESSIVE_LS_EN :bit1; + MST_MEM_LS_EN :bit1; + REPLAY_MEM_LS_EN :bit1; + SLV_MEM_SD_EN :bit1; + SLV_MEM_AGGRESSIVE_SD_EN :bit1; + MST_MEM_SD_EN :bit1; + REPLAY_MEM_SD_EN :bit1; + RX_NP_MEM_WRITE_ENCODING :bit5; + SLV_MEM_DS_EN :bit1; + MST_MEM_DS_EN :bit1; + REPLAY_MEM_DS_EN :bit1; + end; + + TPCIE_EFUSE=bit32; + + TPCIE_FC_NP=bitpacked record + NPD_CREDITS:bit8; + NPH_CREDITS:bit8; + RESERVED0 :bit16; + end; + + TPCIE_INDEX=bit32; + + TPERFMON_HI=bitpacked record + PERFMON_HI :bit16; + RESERVED0 :bit13; + PERFMON_READ_SEL:bit3; + end; + + TPLL_ANALOG=bitpacked record + PLL_CAL_MODE :bit5; + PLL_PFD_PULSE_SEL:bit2; + RESERVED0 :bit1; + PLL_CP :bit4; + PLL_LF_MODE :bit9; + PLL_VREG_FB_TRIM :bit3; + PLL_IBIAS :bit8; + end; + + TPLL_FB_DIV=bitpacked record + PLL_FB_DIV_FRACTION :bit4; + PLL_FB_DIV_FRACTION_CNTL:bit2; + RESERVED0 :bit10; + PLL_FB_DIV :bit12; + RESERVED1 :bit4; + end; + + TPM_FUSES_1=bitpacked record + SviLoadLineOffsetVddC:bit8; + SviLoadLineTrimVddC :bit8; + SviLoadLineVddC :bit8; + SviLoadLineEn :bit8; + end; + + TPM_FUSES_2=bitpacked record + TDC_MAWt :bit8; + TDC_VDDC_ThrottleReleaseLimitPerc:bit8; + TDC_VDDC_PkgLimit :bit16; + end; + + TPM_FUSES_3=bitpacked record + Reserved :bit8; + LPMLTemperatureMax:bit8; + LPMLTemperatureMin:bit8; + TdcWaterfallCtl :bit8; + end; + + TPM_FUSES_4=bitpacked record + LPMLTemperatureScaler_3:bit8; + LPMLTemperatureScaler_2:bit8; + LPMLTemperatureScaler_1:bit8; + LPMLTemperatureScaler_0:bit8; + end; + + TPM_FUSES_5=bitpacked record + LPMLTemperatureScaler_7:bit8; + LPMLTemperatureScaler_6:bit8; + LPMLTemperatureScaler_5:bit8; + LPMLTemperatureScaler_4:bit8; + end; + + TPM_FUSES_6=bitpacked record + LPMLTemperatureScaler_11:bit8; + LPMLTemperatureScaler_10:bit8; + LPMLTemperatureScaler_9 :bit8; + LPMLTemperatureScaler_8 :bit8; + end; + + TPM_FUSES_7=bitpacked record + LPMLTemperatureScaler_15:bit8; + LPMLTemperatureScaler_14:bit8; + LPMLTemperatureScaler_13:bit8; + LPMLTemperatureScaler_12:bit8; + end; + + TPM_FUSES_8=bitpacked record + FuzzyFan_ErrorRateSetDelta:bit16; + FuzzyFan_ErrorSetDelta :bit16; + end; + + TPM_FUSES_9=bitpacked record + Reserved6 :bit16; + FuzzyFan_PwmSetDelta:bit16; + end; + + TROM_STATUS=bitpacked record + ROM_BUSY :bit1; + RESERVED0:bit31; + end; + + TSCLV_DEBUG=bit32; + + TSCL_DEBUG2=bitpacked record + SCL_DEBUG_REQ_MODE:bit1; + SCL_DEBUG_EOF_MODE:bit2; + SCL_DEBUG2 :bit29; + end; + + TSCL_UPDATE=bitpacked record + SCL_UPDATE_PENDING :bit1; + RESERVED0 :bit7; + SCL_UPDATE_TAKEN :bit1; + RESERVED1 :bit7; + SCL_UPDATE_LOCK :bit1; + RESERVED2 :bit7; + SCL_COEF_UPDATE_COMPLETE:bit1; + RESERVED3 :bit7; + end; + + TSDMA0_CNTL=bitpacked record + TRAP_ENABLE :bit1; + ATC_L1_ENABLE :bit1; + SEM_WAIT_INT_ENABLE :bit1; + DATA_SWAP_ENABLE :bit1; + FENCE_SWAP_ENABLE :bit1; + MIDCMD_PREEMPT_ENABLE :bit1; + RESERVED0 :bit5; + MC_WRREQ_CREDIT :bit6; + MIDCMD_WORLDSWITCH_ENABLE:bit1; + AUTO_CTXSW_ENABLE :bit1; + RESERVED1 :bit1; + RESERVED2 :bit2; + MC_RDREQ_CREDIT :bit6; + CTXEMPTY_INT_ENABLE :bit1; + FROZEN_INT_ENABLE :bit1; + IB_PREEMPT_INT_ENABLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA0_HASH=bitpacked record + CHANNEL_BITS :bit3; + RESERVED0 :bit1; + BANK_BITS :bit3; + RESERVED1 :bit1; + CHANNEL_XOR_COUNT:bit3; + RESERVED2 :bit1; + BANK_XOR_COUNT :bit3; + RESERVED3 :bit17; + end; + + TSDMA1_CNTL=bitpacked record + TRAP_ENABLE :bit1; + ATC_L1_ENABLE :bit1; + SEM_WAIT_INT_ENABLE :bit1; + DATA_SWAP_ENABLE :bit1; + FENCE_SWAP_ENABLE :bit1; + MIDCMD_PREEMPT_ENABLE :bit1; + RESERVED0 :bit5; + MC_WRREQ_CREDIT :bit6; + MIDCMD_WORLDSWITCH_ENABLE:bit1; + AUTO_CTXSW_ENABLE :bit1; + RESERVED1 :bit1; + RESERVED2 :bit2; + MC_RDREQ_CREDIT :bit6; + CTXEMPTY_INT_ENABLE :bit1; + FROZEN_INT_ENABLE :bit1; + IB_PREEMPT_INT_ENABLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA1_HASH=bitpacked record + CHANNEL_BITS :bit3; + RESERVED0 :bit1; + BANK_BITS :bit3; + RESERVED1 :bit1; + CHANNEL_XOR_COUNT:bit3; + RESERVED2 :bit1; + BANK_XOR_COUNT :bit3; + RESERVED3 :bit17; + end; + + TSEM_STATUS=bitpacked record + SEM_IDLE :bit1; + SEM_INTERNAL_IDLE :bit1; + MC_RDREQ_FIFO_FULL :bit1; + MC_WRREQ_FIFO_FULL :bit1; + WRITE1_FIFO_FULL :bit1; + CHECK0_FIFO_FULL :bit1; + MC_RDREQ_PENDING :bit1; + MC_WRREQ_PENDING :bit1; + SDMA0_MAILBOX_PENDING:bit1; + SDMA1_MAILBOX_PENDING:bit1; + UVD_MAILBOX_PENDING :bit1; + VCE_MAILBOX_PENDING :bit1; + CPG1_MAILBOX_PENDING :bit1; + CPG2_MAILBOX_PENDING :bit1; + VCE1_MAILBOX_PENDING :bit1; + ATC_REQ_PENDING :bit1; + RESERVED0 :bit15; + SWITCH_READY :bit1; + end; + + TSMC_RESP_0=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_1=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_2=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_3=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_4=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_5=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_6=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_7=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_8=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_9=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSPMI_RESET=bitpacked record + RESERVED0:bit1; + RESERVED1:bit30; + RESERVED2:bit1; + end; + + TSPMI_SPARE=bit32; + + TSQC_CACHES=bitpacked record + TARGET_INST:bit1; + TARGET_DATA:bit1; + INVALIDATE :bit1; + WRITEBACK :bit1; + VOL :bit1; + RESERVED0 :bit11; + COMPLETE :bit1; + RESERVED1 :bit15; + end; + + TSQC_CONFIG=bitpacked record + INST_CACHE_SIZE :bit2; + DATA_CACHE_SIZE :bit2; + MISS_FIFO_DEPTH :bit2; + HIT_FIFO_DEPTH :bit1; + FORCE_ALWAYS_MISS :bit1; + FORCE_IN_ORDER :bit1; + IDENTITY_HASH_BANK :bit1; + IDENTITY_HASH_SET :bit1; + PER_VMID_INV_DISABLE:bit1; + EVICT_LRU :bit2; + FORCE_2_BANK :bit1; + FORCE_1_BANK :bit1; + LS_DISABLE_CLOCKS :bit8; + RESERVED0 :bit8; + end; + + TSQ_MTBUF_0=bitpacked record + OFFSET :bit12; + OFFEN :bit1; + IDXEN :bit1; + GLC :bit1; + OP :bit4; + DFMT :bit4; + NFMT :bit3; + ENCODING:bit6; + end; + + TSQ_MTBUF_1=bitpacked record + VADDR :bit8; + VDATA :bit8; + SRSRC :bit5; + RESERVED0:bit1; + SLC :bit1; + TFE :bit1; + SOFFSET :bit8; + end; + + TSQ_MUBUF_0=bitpacked record + OFFSET :bit12; + OFFEN :bit1; + IDXEN :bit1; + GLC :bit1; + ADDR64 :bit1; + LDS :bit1; + SLC :bit1; + OP :bit7; + RESERVED0:bit1; + ENCODING :bit6; + end; + + TSQ_MUBUF_1=bitpacked record + VADDR :bit8; + VDATA :bit8; + SRSRC :bit5; + RESERVED0:bit2; + TFE :bit1; + SOFFSET :bit8; + end; + + TSQ_TIME_HI=bit32; + + TSQ_TIME_LO=bit32; + + TSQ_VOP_DPP=bitpacked record + SRC0 :bit8; + DPP_CTRL :bit9; + RESERVED0 :bit2; + BOUND_CTRL:bit1; + SRC0_NEG :bit1; + SRC0_ABS :bit1; + SRC1_NEG :bit1; + SRC1_ABS :bit1; + BANK_MASK :bit4; + ROW_MASK :bit4; + end; + + TSQ_WAVE_M0=bit32; + + TSRBM_DEBUG=bitpacked record + IGNORE_RDY :bit1; + DISABLE_READ_TIMEOUT :bit1; + SNAPSHOT_FREE_CNTRS :bit1; + RESERVED0 :bit1; + SYS_CLOCK_DOMAIN_OVERRIDE :bit1; + VCE_CLOCK_DOMAIN_OVERRIDE :bit1; + UVD_CLOCK_DOMAIN_OVERRIDE :bit1; + SDMA_CLOCK_DOMAIN_OVERRIDE:bit1; + MC_CLOCK_DOMAIN_OVERRIDE :bit1; + SAM_CLOCK_DOMAIN_OVERRIDE :bit1; + ISP_CLOCK_DOMAIN_OVERRIDE :bit1; + VP8_CLOCK_DOMAIN_OVERRIDE :bit1; + RESERVED1 :bit20; + end; + TSX_DEBUG_1=bitpacked record SX_DB_QUAD_CREDIT :bit7; RESERVED0 :bit1; @@ -349,6 +2982,23 @@ type TTA_SCRATCH=bit32; + TTCI_CNTL_1=bitpacked record + WBINVL1_NUM_CYCLES:bit16; + REQ_FIFO_DEPTH :bit8; + WDATA_RAM_DEPTH :bit8; + end; + + TTCI_CNTL_2=bitpacked record + L1_INVAL_ON_WBINVL2:bit1; + TCA_MAX_CREDIT :bit8; + RESERVED0 :bit23; + end; + + TTCI_STATUS=bitpacked record + TCI_BUSY :bit1; + RESERVED0:bit31; + end; + TTCP_CREDIT=bitpacked record LFIFO_CREDIT :bit10; RESERVED0 :bit6; @@ -369,10 +3019,414 @@ type RESERVED0 :bit24; end; + TTDC_STATUS=bitpacked record + VDD_Boost :bit8; + VDD_Throttle :bit8; + VDDC_Boost :bit8; + VDDC_Throttle:bit8; + end; + TTD_SCRATCH=bit32; + TTMDS_DEBUG=bitpacked record + TMDS_DEBUG_EN :bit1; + RESERVED0 :bit7; + TMDS_DEBUG_HSYNC :bit1; + TMDS_DEBUG_HSYNC_EN:bit1; + RESERVED1 :bit6; + TMDS_DEBUG_VSYNC :bit1; + TMDS_DEBUG_VSYNC_EN:bit1; + RESERVED2 :bit6; + TMDS_DEBUG_DE :bit1; + TMDS_DEBUG_DE_EN :bit1; + RESERVED3 :bit6; + end; + + TUNP_DEBUG2=bit32; + + TUVD_CONFIG=bitpacked record + RESERVED0 :bit8; + UVD_RDREQ_URG:bit4; + RESERVED1 :bit4; + UVD_REQ_TRAN :bit1; + RESERVED2 :bit15; + end; + + TUVD_STATUS=bitpacked record + RBC_BUSY :bit1; + VCPU_REPORT:bit7; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit13; + RESERVED11 :bit1; + end; + + TVCE_CONFIG=bitpacked record + RESERVED0 :bit8; + VCE_RDREQ_URG:bit4; + RESERVED1 :bit4; + VCE_REQ_TRAN :bit1; + RESERVED2 :bit15; + end; + + TVCE_STATUS=bitpacked record + JOB_BUSY :bit1; + VCPU_REPORT :bit7; + UENC_BUSY :bit1; + RESERVED0 :bit13; + VCE_CONFIGURATION:bit2; + VCE_INSTANCE_ID :bit2; + RESERVED1 :bit4; + RESERVED2 :bit1; + RESERVED3 :bit1; + end; + + TVGA_STATUS=bitpacked record + VGA_MEM_ACCESS_STATUS :bit1; + VGA_REG_ACCESS_STATUS :bit1; + VGA_DISPLAY_SWITCH_STATUS :bit1; + VGA_MODE_AUTO_TRIGGER_STATUS:bit1; + RESERVED0 :bit28; + end; + + TVM_L2_CNTL=bitpacked record + ENABLE_L2_CACHE :bit1; + ENABLE_L2_FRAGMENT_PROCESSING :bit1; + L2_CACHE_PTE_ENDIAN_SWAP_MODE :bit2; + L2_CACHE_PDE_ENDIAN_SWAP_MODE :bit2; + RESERVED0 :bit2; + L2_PDE0_CACHE_TAG_GENERATION_MODE :bit1; + ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE :bit1; + ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE:bit1; + ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY:bit1; + L2_PDE0_CACHE_SPLIT_MODE :bit3; + EFFECTIVE_L2_QUEUE_SIZE :bit3; + PDE_FAULT_CLASSIFICATION :bit1; + CONTEXT1_IDENTITY_ACCESS_MODE :bit2; + IDENTITY_MODE_FRAGMENT_SIZE :bit5; + L2_CACHE_4K_SWAP_TAG_INDEX_LSBS :bit2; + L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS :bit3; + RESERVED1 :bit1; + end; + TWD_ENHANCE=bit32; + TAFMT_STATUS=bitpacked record + RESERVED0 :bit4; + AFMT_AUDIO_ENABLE :bit1; + RESERVED1 :bit3; + AFMT_AZ_HBR_ENABLE :bit1; + RESERVED2 :bit15; + AFMT_AUDIO_FIFO_OVERFLOW:bit1; + RESERVED3 :bit5; + AFMT_AZ_AUDIO_ENABLE_CHG:bit1; + RESERVED4 :bit1; + end; + + TATC_L1_CNTL=bitpacked record + DONT_NEED_ATS_BEHAVIOR:bit2; + NEED_ATS_BEHAVIOR :bit1; + RESERVED0 :bit1; + NEED_ATS_SNOOP_DEFAULT:bit1; + RESERVED1 :bit27; + end; + + TATC_L2_CNTL=bitpacked record + NUMBER_OF_TRANSLATION_READ_REQUESTS :bit2; + RESERVED0 :bit2; + NUMBER_OF_TRANSLATION_WRITE_REQUESTS :bit2; + RESERVED1 :bit2; + NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD :bit1; + NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD:bit1; + RESERVED2 :bit22; + end; + + TATC_MISC_CG=bitpacked record + RESERVED0 :bit6; + OFFDLY :bit6; + RESERVED1 :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED2 :bit12; + end; + + TAUXN_IMPCAL=bitpacked record + AUXN_IMPCAL_ENABLE :bit1; + RESERVED0 :bit7; + AUXN_IMPCAL_CALOUT :bit1; + AUXN_CALOUT_ERROR :bit1; + AUXN_CALOUT_ERROR_AK :bit1; + RESERVED1 :bit5; + AUXN_IMPCAL_VALUE :bit4; + AUXN_IMPCAL_STEP_DELAY :bit4; + AUXN_IMPCAL_OVERRIDE :bit4; + AUXN_IMPCAL_OVERRIDE_ENABLE:bit1; + RESERVED2 :bit3; + end; + + TAUXP_IMPCAL=bitpacked record + AUXP_IMPCAL_ENABLE :bit1; + RESERVED0 :bit7; + AUXP_IMPCAL_CALOUT :bit1; + AUXP_CALOUT_ERROR :bit1; + AUXP_CALOUT_ERROR_AK :bit1; + RESERVED1 :bit5; + AUXP_IMPCAL_VALUE :bit4; + AUXP_IMPCAL_STEP_DELAY :bit4; + AUXP_IMPCAL_OVERRIDE :bit4; + AUXP_IMPCAL_OVERRIDE_ENABLE:bit1; + RESERVED2 :bit3; + end; + + TAUX_CONTROL=bitpacked record + AUX_EN :bit1; + RESERVED0 :bit7; + AUX_LS_READ_EN :bit1; + RESERVED1 :bit3; + AUX_LS_UPDATE_DISABLE:bit1; + RESERVED2 :bit3; + AUX_IGNORE_HPD_DISCON:bit1; + RESERVED3 :bit1; + AUX_MODE_DET_EN :bit1; + RESERVED4 :bit1; + AUX_HPD_SEL :bit3; + RESERVED5 :bit1; + AUX_IMPCAL_REQ_EN :bit1; + RESERVED6 :bit3; + AUX_TEST_MODE :bit1; + AUX_DEGLITCH_EN :bit1; + SPARE_0 :bit1; + SPARE_1 :bit1; + end; + + TAUX_LS_DATA=bitpacked record + RESERVED0 :bit8; + AUX_LS_DATA :bit8; + AUX_LS_INDEX:bit5; + RESERVED1 :bit11; + end; + + TAUX_SW_DATA=bitpacked record + AUX_SW_DATA_RW :bit1; + RESERVED0 :bit7; + AUX_SW_DATA :bit8; + AUX_SW_INDEX :bit5; + RESERVED1 :bit10; + AUX_SW_AUTOINCREMENT_DISABLE:bit1; + end; + + TBASE_ADDR_1=bit32; + + TBASE_ADDR_2=bit32; + + TBASE_ADDR_3=bit32; + + TBASE_ADDR_4=bit32; + + TBASE_ADDR_5=bit32; + + TBASE_ADDR_6=bit32; + + TBIF_RB_BASE=bit32; + + TBIF_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit2; + WPTR_WRITEBACK_ENABLE:bit1; + WPTR_WRITEBACK_TIMER :bit5; + RESERVED1 :bit3; + BIF_RB_TRAN :bit1; + RESERVED2 :bit13; + WPTR_OVERFLOW_CLEAR :bit1; + end; + + TBIF_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit16; + RESERVED1:bit14; + end; + + TBIF_RB_WPTR=bitpacked record + BIF_RB_OVERFLOW:bit1; + RESERVED0 :bit1; + OFFSET :bit16; + RESERVED1 :bit14; + end; + + TBIF_XDMA_HI=bitpacked record + BIF_XDMA_UPPER_BOUND:bit29; + RESERVED0 :bit3; + end; + + TBIF_XDMA_LO=bitpacked record + BIF_XDMA_LOWER_BOUND:bit29; + RESERVED0 :bit2; + BIF_XDMA_APER_EN :bit1; + end; + + TBLND_UPDATE=bitpacked record + BLND_UPDATE_PENDING:bit1; + RESERVED0 :bit7; + BLND_UPDATE_TAKEN :bit1; + RESERVED1 :bit7; + BLND_UPDATE_LOCK :bit1; + RESERVED2 :bit15; + end; + + TBL_PWM_CNTL=bitpacked record + BL_ACTIVE_INT_FRAC_CNT:bit16; + RESERVED0 :bit14; + BL_PWM_FRACTIONAL_EN :bit1; + BL_PWM_EN :bit1; + end; + + TBX_RESET_EN=bitpacked record + COR_RESET_EN :bit1; + REG_RESET_EN :bit1; + STY_RESET_EN :bit1; + RESERVED0 :bit5; + FLR_TWICE_EN :bit1; + FLR_TIMER_SEL :bit2; + RESERVED1 :bit4; + DB_APER_RESET_EN :bit1; + RESET_ON_VFENABLE_LOW_EN:bit1; + PF_FLR_NEWHDL_EN :bit1; + RESERVED2 :bit14; + end; + + TCGTS_RD_REG=bitpacked record + READ_DATA:bit14; + RESERVED0:bit18; + end; + + TCLIENT0_CD0=bit32; + + TCLIENT0_CD1=bit32; + + TCLIENT0_CD2=bit32; + + TCLIENT0_CD3=bit32; + + TCLIENT0_CK0=bit32; + + TCLIENT0_CK1=bit32; + + TCLIENT0_CK2=bit32; + + TCLIENT0_CK3=bit32; + + TCLIENT1_CD0=bit32; + + TCLIENT1_CD1=bit32; + + TCLIENT1_CD2=bit32; + + TCLIENT1_CD3=bit32; + + TCLIENT1_CK0=bit32; + + TCLIENT1_CK1=bit32; + + TCLIENT1_CK2=bit32; + + TCLIENT1_CK3=bit32; + + TCLIENT2_CD0=bit32; + + TCLIENT2_CD1=bit32; + + TCLIENT2_CD2=bit32; + + TCLIENT2_CD3=bit32; + + TCLIENT2_CK0=bit32; + + TCLIENT2_CK1=bit32; + + TCLIENT2_CK2=bit32; + + TCLIENT2_CK3=bit32; + + TCLIENT3_CD0=bit32; + + TCLIENT3_CD1=bit32; + + TCLIENT3_CD2=bit32; + + TCLIENT3_CD3=bit32; + + TCLIENT3_CK0=bit32; + + TCLIENT3_CK1=bit32; + + TCLIENT3_CK2=bit32; + + TCLIENT3_CK3=bit32; + + TCLIENT4_CD0=bit32; + + TCLIENT4_CD1=bit32; + + TCLIENT4_CD2=bit32; + + TCLIENT4_CD3=bit32; + + TCLIENT4_CK0=bit32; + + TCLIENT4_CK1=bit32; + + TCLIENT4_CK2=bit32; + + TCLIENT4_CK3=bit32; + + TCONFIG_CNTL=bitpacked record + CFG_VGA_RAM_EN :bit1; + VGA_DIS :bit1; + GENMO_MONO_ADDRESS_B:bit1; + GRPH_ADRSEL :bit2; + RESERVED0 :bit27; + end; + + TCORB_STATUS=bitpacked record + CORB_MEMORY_ERROR_INDICATION:bit1; + RESERVED0 :bit31; + end; + + TCPM_CONTROL=bitpacked record + LCLK_DYN_GATE_ENABLE :bit1; + TXCLK_DYN_GATE_ENABLE :bit1; + TXCLK_PERM_GATE_ENABLE :bit1; + TXCLK_PIF_GATE_ENABLE :bit1; + TXCLK_GSKT_GATE_ENABLE :bit1; + TXCLK_LCNT_GATE_ENABLE :bit1; + TXCLK_REGS_GATE_ENABLE :bit1; + TXCLK_PRBS_GATE_ENABLE :bit1; + REFCLK_REGS_GATE_ENABLE :bit1; + LCLK_DYN_GATE_LATENCY :bit1; + TXCLK_DYN_GATE_LATENCY :bit1; + TXCLK_PERM_GATE_LATENCY :bit1; + TXCLK_REGS_GATE_LATENCY :bit1; + REFCLK_REGS_GATE_LATENCY:bit1; + LCLK_GATE_TXCLK_FREE :bit1; + RCVR_DET_CLK_ENABLE :bit1; + TXCLK_PERM_GATE_PLL_PDN :bit1; + FAST_TXCLK_LATENCY :bit3; + MASTER_PCIE_PLL_SELECT :bit1; + MASTER_PCIE_PLL_AUTO :bit1; + REFCLK_XSTCLK_ENABLE :bit1; + REFCLK_XSTCLK_LATENCY :bit1; + SPARE_REGS :bit8; + end; + TCP_CMD_DATA=bit32; TCP_CSF_CNTL=bitpacked record @@ -585,6 +3639,436 @@ type RESERVED0:bit12; end; + TCRTC_STATUS=bitpacked record + CRTC_V_BLANK :bit1; + CRTC_V_ACTIVE_DISP :bit1; + CRTC_V_SYNC_A :bit1; + CRTC_V_UPDATE :bit1; + CRTC_V_START_LINE :bit1; + CRTC_V_BLANK_3D_STRUCTURE:bit1; + RESERVED0 :bit10; + CRTC_H_BLANK :bit1; + CRTC_H_ACTIVE_DISP :bit1; + CRTC_H_SYNC_A :bit1; + RESERVED1 :bit13; + end; + + TCUR2_COLOR1=bitpacked record + CUR2_COLOR1_BLUE :bit8; + CUR2_COLOR1_GREEN:bit8; + CUR2_COLOR1_RED :bit8; + RESERVED0 :bit8; + end; + + TCUR2_COLOR2=bitpacked record + CUR2_COLOR2_BLUE :bit8; + CUR2_COLOR2_GREEN:bit8; + CUR2_COLOR2_RED :bit8; + RESERVED0 :bit8; + end; + + TCUR2_UPDATE=bitpacked record + CURSOR2_UPDATE_PENDING :bit1; + CURSOR2_UPDATE_TAKEN :bit1; + RESERVED0 :bit14; + CURSOR2_UPDATE_LOCK :bit1; + RESERVED1 :bit7; + CURSOR2_DISABLE_MULTIPLE_UPDATE:bit1; + CURSOR2_UPDATE_STEREO_MODE :bit2; + RESERVED2 :bit5; + end; + + TCUR_CONTROL=bitpacked record + CURSOR_EN :bit1; + RESERVED0 :bit3; + CUR_INV_TRANS_CLAMP :bit1; + RESERVED1 :bit3; + CURSOR_MODE :bit2; + RESERVED2 :bit6; + CURSOR_2X_MAGNIFY :bit1; + RESERVED3 :bit3; + CURSOR_FORCE_MC_ON :bit1; + RESERVED4 :bit3; + CURSOR_URGENT_CONTROL:bit3; + RESERVED5 :bit5; + end; + + TDAC_CONTROL=bitpacked record + DAC_DFORCE_EN :bit1; + RESERVED0 :bit7; + DAC_TV_ENABLE :bit1; + RESERVED1 :bit7; + DAC_ZSCALE_SHIFT:bit1; + RESERVED2 :bit15; + end; + + TDAC_R_INDEX=bitpacked record + DAC_R_INDEX:bit8; + RESERVED0 :bit24; + end; + + TDAC_W_INDEX=bitpacked record + DAC_W_INDEX:bit8; + RESERVED0 :bit24; + end; + + TDATA_FORMAT=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + RESERVED2 :bit1; + RESERVED3 :bit3; + RESERVED4 :bit1; + RESERVED5 :bit3; + RESERVED6 :bit1; + RESERVED7 :bit3; + RESERVED8 :bit5; + RESERVED9 :bit3; + RESERVED10:bit2; + RESERVED11:bit2; + RESERVED12:bit1; + RESERVED13:bit3; + end; + + TDCIO_DEBUG1=bitpacked record + DCO_DCIO_MVP_DVOCNTL_A0_REG :bit2; + DCO_DCIO_MVP_DVOCNTL_MASK_REG:bit2; + DCO_DCIO_MVP_DVOCNTL_EN_REG :bit2; + DCO_DCIO_MVP_DVOCNTL_A0 :bit2; + DCO_DCIO_MVP_DVOCNTL_SEL0 :bit2; + DCO_DCIO_MVP_DVOCNTL_EN :bit2; + DCO_DCIO_MVP_DVOCLK_C :bit1; + DCO_DCIO_DVOCNTL1_A0_REG :bit1; + DCO_DCIO_DVOCNTL1_A0_PREMUX :bit1; + DCO_DCIO_DVOCNTL1_A0 :bit1; + DCO_DCIO_DVOCNTL1_EN_REG :bit1; + DCO_DCIO_DVO_HSYNC_TRISTATE :bit1; + DCO_DCIO_DVO_CLK_TRISTATE :bit1; + DCO_DCIO_DVOCNTL1_EN_PREMUX :bit1; + DCO_DCIO_DVOCNTL1_EN :bit1; + DCO_DCIO_DVOCNTL1_MUX :bit1; + DCO_DCIO_DVOCNTL1_MASK_REG :bit1; + DCO_DCIO_DVO_ENABLE :bit1; + DCO_DCIO_DVO_VSYNC_TRISTATE :bit1; + DCO_DCIO_DVO_RATE_SEL :bit1; + DCO_DCIO_DVOCNTL1_SEL0_PREMUX:bit1; + DCO_DCIO_DVOCNTL1_SEL0 :bit1; + RESERVED0 :bit4; + end; + + TDCIO_DEBUG2=bit32; + + TDCIO_DEBUG3=bit32; + + TDCIO_DEBUG4=bit32; + + TDCIO_DEBUG5=bit32; + + TDCIO_DEBUG6=bit32; + + TDCIO_DEBUG7=bit32; + + TDCIO_DEBUG8=bit32; + + TDCIO_DEBUG9=bit32; + + TDCIO_DEBUGA=bit32; + + TDCIO_DEBUGB=bit32; + + TDCIO_DEBUGC=bit32; + + TDCIO_DEBUGD=bit32; + + TDCIO_DEBUGE=bit32; + + TDCIO_DEBUGF=bit32; + + TDC_GENERICA=bitpacked record + GENERICA_EN :bit1; + RESERVED0 :bit6; + GENERICA_SEL :bit5; + GENERICA_UNIPHY_REFDIV_CLK_SEL :bit3; + RESERVED1 :bit1; + GENERICA_UNIPHY_FBDIV_CLK_SEL :bit3; + RESERVED2 :bit1; + GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL :bit3; + RESERVED3 :bit1; + GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL:bit3; + RESERVED4 :bit5; + end; + + TDC_GENERICB=bitpacked record + GENERICB_EN :bit1; + RESERVED0 :bit7; + GENERICB_SEL :bit4; + GENERICB_UNIPHY_REFDIV_CLK_SEL :bit3; + RESERVED1 :bit1; + GENERICB_UNIPHY_FBDIV_CLK_SEL :bit3; + RESERVED2 :bit1; + GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL :bit3; + RESERVED3 :bit1; + GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL:bit3; + RESERVED4 :bit5; + end; + + TDC_I2C_DATA=bitpacked record + DC_I2C_DATA_RW :bit1; + RESERVED0 :bit7; + DC_I2C_DATA :bit8; + DC_I2C_INDEX :bit8; + RESERVED1 :bit7; + DC_I2C_INDEX_WRITE:bit1; + end; + + TDEBUG_INDEX=bitpacked record + DEBUG_INDEX:bit18; + RESERVED0 :bit14; + end; + + TDEVICE_CAP2=bitpacked record + CPL_TIMEOUT_RANGE_SUPPORTED :bit4; + CPL_TIMEOUT_DIS_SUPPORTED :bit1; + ARI_FORWARDING_SUPPORTED :bit1; + ATOMICOP_ROUTING_SUPPORTED :bit1; + ATOMICOP_32CMPLT_SUPPORTED :bit1; + ATOMICOP_64CMPLT_SUPPORTED :bit1; + CAS128_CMPLT_SUPPORTED :bit1; + NO_RO_ENABLED_P2P_PASSING :bit1; + LTR_SUPPORTED :bit1; + TPH_CPLR_SUPPORTED :bit2; + RESERVED0 :bit4; + OBFF_SUPPORTED :bit2; + EXTENDED_FMT_FIELD_SUPPORTED:bit1; + END_END_TLP_PREFIX_SUPPORTED:bit1; + MAX_END_END_TLP_PREFIXES :bit2; + RESERVED1 :bit8; + end; + + TDEVICE_CNTL=bitpacked record + CORR_ERR_EN :bit1; + NON_FATAL_ERR_EN :bit1; + FATAL_ERR_EN :bit1; + USR_REPORT_EN :bit1; + RELAXED_ORD_EN :bit1; + MAX_PAYLOAD_SIZE :bit3; + EXTENDED_TAG_EN :bit1; + PHANTOM_FUNC_EN :bit1; + AUX_POWER_PM_EN :bit1; + NO_SNOOP_EN :bit1; + MAX_READ_REQUEST_SIZE:bit3; + INITIATE_FLR :bit1; + RESERVED0 :bit16; + end; + + TDIG_BE_CNTL=bitpacked record + RESERVED0 :bit8; + DIG_FE_SOURCE_SELECT:bit7; + RESERVED1 :bit1; + DIG_MODE :bit3; + RESERVED2 :bit9; + DIG_HPD_SELECT :bit3; + RESERVED3 :bit1; + end; + + TDIG_FE_CNTL=bitpacked record + DIG_SOURCE_SELECT :bit3; + RESERVED0 :bit1; + DIG_STEREOSYNC_SELECT :bit3; + RESERVED1 :bit1; + DIG_STEREOSYNC_GATE_EN:bit1; + RESERVED2 :bit1; + DIG_START :bit1; + RESERVED3 :bit5; + DIG_DUAL_LINK_ENABLE :bit1; + RESERVED4 :bit1; + DIG_SWAP :bit1; + RESERVED5 :bit1; + DIG_RB_SWITCH_EN :bit1; + RESERVED6 :bit3; + DIG_SYMCLK_FE_ON :bit1; + RESERVED7 :bit7; + end; + + TDMCU_STATUS=bitpacked record + UC_IN_RESET :bit1; + UC_IN_WAIT_MODE:bit1; + UC_IN_STOP_MODE:bit1; + RESERVED0 :bit28; + RESERVED1 :bit1; + end; + + TDMIF_P_VMID=bitpacked record + P_VMID_PIPE0:bit4; + P_VMID_PIPE1:bit4; + P_VMID_PIPE2:bit4; + P_VMID_PIPE3:bit4; + P_VMID_PIPE4:bit4; + P_VMID_PIPE5:bit4; + P_VMID_PIPE6:bit4; + P_VMID_PIPE7:bit4; + end; + + TDMIF_STATUS=bitpacked record + DMIF_MC_SEND_ON_IDLE :bit8; + DMIF_CLEAR_MC_SEND_ON_IDLE :bit8; + DMIF_MC_LATENCY_COUNTER_ENABLE :bit1; + DMIF_MC_LATENCY_COUNTER_URGENT_ONLY :bit1; + RESERVED0 :bit2; + DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT :bit3; + RESERVED1 :bit1; + DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT:bit3; + RESERVED2 :bit1; + DMIF_UNDERFLOW :bit1; + RESERVED3 :bit3; + end; + + TDPM_TABLE_1=bit32; + + TDPM_TABLE_2=bit32; + + TDPM_TABLE_3=bit32; + + TDPM_TABLE_4=bit32; + + TDPM_TABLE_5=bit32; + + TDPM_TABLE_6=bit32; + + TDPM_TABLE_7=bit32; + + TDPM_TABLE_8=bit32; + + TDPM_TABLE_9=bit32; + + TDP_DPHY_SYM=bitpacked record + RESERVED0:bit10; + RESERVED1:bit10; + RESERVED2:bit12; + end; + + TDP_MSA_MISC=bitpacked record + RESERVED0 :bit3; + DP_MSA_MISC1:bit4; + RESERVED1 :bit1; + DP_MSA_MISC2:bit8; + DP_MSA_MISC3:bit8; + DP_MSA_MISC4:bit8; + end; + + TDP_MSE_SAT0=bitpacked record + DP_MSE_SAT_SRC0 :bit3; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit3; + DP_MSE_SAT_SLOT_COUNT0:bit6; + RESERVED3 :bit2; + DP_MSE_SAT_SRC1 :bit3; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit3; + DP_MSE_SAT_SLOT_COUNT1:bit6; + RESERVED7 :bit2; + end; + + TDP_MSE_SAT1=bitpacked record + DP_MSE_SAT_SRC2 :bit3; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit3; + DP_MSE_SAT_SLOT_COUNT2:bit6; + RESERVED3 :bit2; + DP_MSE_SAT_SRC3 :bit3; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit3; + DP_MSE_SAT_SLOT_COUNT3:bit6; + RESERVED7 :bit2; + end; + + TDP_MSE_SAT2=bitpacked record + DP_MSE_SAT_SRC4 :bit3; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit3; + DP_MSE_SAT_SLOT_COUNT4:bit6; + RESERVED3 :bit2; + DP_MSE_SAT_SRC5 :bit3; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit3; + DP_MSE_SAT_SLOT_COUNT5:bit6; + RESERVED7 :bit2; + end; + + TDP_SEC_CNTL=bitpacked record + DP_SEC_STREAM_ENABLE:bit1; + RESERVED0 :bit3; + DP_SEC_ASP_ENABLE :bit1; + RESERVED1 :bit3; + DP_SEC_ATP_ENABLE :bit1; + RESERVED2 :bit3; + DP_SEC_AIP_ENABLE :bit1; + RESERVED3 :bit3; + DP_SEC_ACM_ENABLE :bit1; + RESERVED4 :bit3; + DP_SEC_GSP0_ENABLE :bit1; + DP_SEC_GSP1_ENABLE :bit1; + DP_SEC_GSP2_ENABLE :bit1; + DP_SEC_GSP3_ENABLE :bit1; + DP_SEC_AVI_ENABLE :bit1; + RESERVED5 :bit3; + DP_SEC_MPG_ENABLE :bit1; + RESERVED6 :bit3; + end; + + TDVO_CONTROL=bitpacked record + DVO_RATE_SELECT :bit1; + DVO_SDRCLK_SEL :bit1; + RESERVED0 :bit2; + DVO_DVPDATA_WIDTH :bit2; + RESERVED1 :bit2; + DVO_DUAL_CHANNEL_EN:bit1; + RESERVED2 :bit7; + DVO_RESET_FIFO :bit1; + DVO_SYNC_PHASE :bit1; + DVO_INVERT_DVOCLK :bit1; + RESERVED3 :bit1; + DVO_HSYNC_POLARITY :bit1; + DVO_VSYNC_POLARITY :bit1; + DVO_DE_POLARITY :bit1; + RESERVED4 :bit1; + DVO_COLOR_FORMAT :bit2; + RESERVED5 :bit5; + DVO_CTL3 :bit1; + end; + + TFMT_CONTROL=bitpacked record + FMT_STEREOSYNC_OVERRIDE :bit1; + RESERVED0 :bit3; + FMT_STEREOSYNC_OVR_POL :bit1; + RESERVED1 :bit3; + FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX :bit4; + FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP:bit2; + RESERVED2 :bit2; + FMT_PIXEL_ENCODING :bit1; + FMT_SUBSAMPLING_MODE :bit1; + FMT_SUBSAMPLING_ORDER :bit1; + RESERVED3 :bit5; + FMT_SRC_SELECT :bit3; + RESERVED4 :bit5; + end; + + TGB_EDC_MODE=bitpacked record + RESERVED0 :bit16; + FORCE_SEC_ON_DED:bit1; + RESERVED1 :bit3; + DED_MODE :bit2; + RESERVED2 :bit7; + PROP_FED :bit1; + RESERVED3 :bit1; + BYPASS :bit1; + end; + TGDS_ATOM_OP=bitpacked record OP :bit8; UNUSED:bit24; @@ -617,6 +4101,35 @@ type TGDS_WR_DATA=bit32; + TGMCON_DEBUG=bitpacked record + GFX_STALL :bit1; + GFX_CLEAR :bit1; + GMCON_DEBUG_RESERVED0:bit1; + SR_COMMIT_STATE :bit1; + STCTRL_ST :bit4; + MISC_FLAGS :bit24; + end; + + TGMCON_MISC2=bitpacked record + GMCON_MISC2_RESERVED0 :bit6; + STCTRL_NONDISP_IDLE_THRESHOLD:bit5; + RENG_SR_HOLD_THRESHOLD :bit6; + GMCON_MISC2_RESERVED1 :bit12; + STCTRL_IGNORE_ARB_BUSY :bit1; + STCTRL_EXTEND_GMC_OFFLINE :bit1; + STCTRL_TIMER_PULSE_OVERRIDE :bit1; + end; + + TGMCON_MISC3=bitpacked record + RENG_DISABLE_MCC :bit8; + RENG_DISABLE_MCD :bit8; + STCTRL_FORCE_PGFSM_CMD_DONE :bit12; + STCTRL_IGNORE_ALLOW_STUTTER :bit1; + RENG_MEM_LS_ENABLE :bit1; + STCTRL_EXCLUDE_NONMEM_CLIENTS:bit1; + RESERVED0 :bit1; + end; + TGRBM_STATUS=bitpacked record ME0PIPE0_CMDFIFO_AVAIL:bit4; RESERVED0 :bit1; @@ -648,11 +4161,606 @@ type GUI_ACTIVE :bit1; end; + TGRPH_ENABLE=bitpacked record + GRPH_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TGRPH_UPDATE=bitpacked record + GRPH_MODE_UPDATE_PENDING :bit1; + GRPH_MODE_UPDATE_TAKEN :bit1; + GRPH_SURFACE_UPDATE_PENDING :bit1; + GRPH_SURFACE_UPDATE_TAKEN :bit1; + RESERVED0 :bit4; + GRPH_SURFACE_XDMA_PENDING_ENABLE :bit1; + RESERVED1 :bit7; + GRPH_UPDATE_LOCK :bit1; + RESERVED2 :bit3; + GRPH_SURFACE_IGNORE_UPDATE_LOCK :bit1; + RESERVED3 :bit3; + GRPH_MODE_DISABLE_MULTIPLE_UPDATE :bit1; + RESERVED4 :bit3; + GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE:bit1; + RESERVED5 :bit3; + end; + + THDMI_STATUS=bitpacked record + HDMI_ACTIVE_AVMUTE :bit1; + RESERVED0 :bit15; + HDMI_AUDIO_PACKET_ERROR:bit1; + RESERVED1 :bit3; + HDMI_VBI_PACKET_ERROR :bit1; + RESERVED2 :bit6; + HDMI_ERROR_INT :bit1; + RESERVED3 :bit4; + end; + + THOST_BUSNUM=bitpacked record + HOST_ID :bit16; + RESERVED0:bit16; + end; + + THW_ROTATION=bitpacked record + GRPH_ROTATION_ANGLE:bit3; + RESERVED0 :bit29; + end; + + TKEY_CONTROL=bitpacked record + KEY_SELECT :bit1; + KEY_MODE :bit2; + RESERVED0 :bit25; + GRPH_OVL_HALF_BLEND:bit1; + RESERVED1 :bit3; + end; + + TLINK_STATUS=bitpacked record + CURRENT_LINK_SPEED :bit4; + NEGOTIATED_LINK_WIDTH :bit6; + RESERVED0 :bit1; + LINK_TRAINING :bit1; + SLOT_CLOCK_CFG :bit1; + DL_ACTIVE :bit1; + LINK_BW_MANAGEMENT_STATUS:bit1; + LINK_AUTONOMOUS_BW_STATUS:bit1; + RESERVED1 :bit16; + end; + + TLNC_BW_WACC=bit32; + + TMAX_LATENCY=bitpacked record + MAX_LAT :bit8; + RESERVED0:bit24; + end; + + TMC_ARB_GRUB=bitpacked record + GRUB_WATERMARK :bit8; + GRUB_WATERMARK_PRI:bit8; + GRUB_WATERMARK_MED:bit8; + REG_WR_EN :bit2; + REG_RD_SEL :bit1; + RESERVED0 :bit5; + end; + + TMC_ARB_MISC=bitpacked record + STICKY_RFSH :bit1; + IDLE_RFSH :bit1; + STUTTER_RFSH :bit1; + CHAN_COUPLE :bit8; + HARSHNESS :bit8; + SMART_RDWR_SW :bit1; + CALI_ENABLE :bit1; + CALI_RATES :bit2; + DISPURGVLD_NOWRT:bit1; + DISPURG_NOSW2WR :bit1; + DISPURG_STALL :bit1; + DISPURG_THROTTLE:bit4; + EXTEND_WEIGHT :bit1; + ACPURG_STALL :bit1; + end; + + TMC_BIST_CMD=bitpacked record + RESERVED0 :bit3; + RESERVED1 :bit1; + RESERVED2 :bit4; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit2; + RESERVED8 :bit2; + RESERVED9 :bit2; + RESERVED10:bit14; + end; + + TMC_BIST_DAT=bitpacked record + RESERVED0:bit4; + RESERVED1:bit4; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit3; + RESERVED5:bit12; + RESERVED6:bit7; + end; + + TMC_RPB_CONF=bitpacked record + RESERVED0 :bit15; + XPB_PCIE_ORDER :bit1; + RPB_RD_PCIE_ORDER:bit1; + RPB_WR_PCIE_ORDER:bit1; + RESERVED1 :bit14; + end; + + TMC_RPB_DBG1=bitpacked record + RPB_BIF_OUTSTANDING_RD :bit8; + RPB_BIF_OUTSTANDING_RD_32B:bit12; + DEBUG_BITS :bit12; + end; + + TMC_SEQ_CNTL=bitpacked record + CHANNEL_DISABLE:bit4; + SAFE_MODE :bit2; + DAT_INV :bit1; + RET_HOLD_EOP :bit1; + BANKGROUP_SIZE :bit1; + BANKGROUP_ENB :bit1; + MSKOFF_DAT_TL :bit1; + MSKOFF_DAT_TH :bit1; + ARB_REQCMD_WMK :bit4; + ARB_REQDAT_WMK :bit4; + ARB_RTDAT_WMK :bit6; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RTR_OVERRIDE :bit1; + end; + + TMC_SEQ_DRAM=bitpacked record + STB_CNT :bit4; + CKE_DYN :bit1; + CKE_ACT :bit1; + DAT_INV :bit1; + INV_ACM :bit1; + RST_CTL :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + DQM_ACT :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit3; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit8; + end; + + TMC_XBAR_ARB=bitpacked record + HUBRD_HIGHEST :bit1; + DISABLE_HUB_STALL_HIGHEST:bit1; + BREAK_BURST_CID_CHANGE :bit1; + ACP_RDRET_URG :bit1; + HDP_RDRET_URG :bit1; + BREAK_BURST_BY_URG :bit1; + RESERVED0 :bit26; + end; + + TMM_INDEX_HI=bit32; + + TMP_INT_STAT=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit8; + end; + + TMSI_MASK_64=bit32; + + TMSI_PENDING=bit32; + + TPCIE_DATA_2=bit32; + + TPCIE_EFUSE2=bit32; + + TPCIE_EFUSE3=bit32; + + TPCIE_EFUSE4=bit32; + + TPCIE_EFUSE5=bit32; + + TPCIE_EFUSE6=bitpacked record + RESERVED0 :bit1; + STRAP_BIF_F0_SUPPORTED_PAGE_SIZES:bit16; + SPARE_15_PCIEFUSE6 :bit15; + end; + + TPCIE_EFUSE7=bitpacked record + RESERVED0 :bit1; + STRAP_BIF_F0_SRIOV_VF_DEVICE_ID:bit16; + SPARE_15_PCIEFUSE7 :bit15; + end; + + TPCIE_FC_CPL=bitpacked record + CPLD_CREDITS:bit8; + CPLH_CREDITS:bit8; + RESERVED0 :bit16; + end; + + TPCIE_MC_CAP=bitpacked record + MC_MAX_GROUP :bit6; + RESERVED0 :bit2; + MC_WIN_SIZE_REQ :bit6; + RESERVED1 :bit1; + MC_ECRC_REGEN_SUPP:bit1; + RESERVED2 :bit16; + end; + + TPCIE_P_CNTL=bitpacked record + P_PWRDN_EN :bit1; + P_SYMALIGN_MODE :bit1; + P_SYMALIGN_HW_DEBUG :bit1; + P_ELASTDESKEW_HW_DEBUG :bit1; + P_IGNORE_CRC_ERR :bit1; + P_IGNORE_LEN_ERR :bit1; + P_IGNORE_EDB_ERR :bit1; + P_IGNORE_IDL_ERR :bit1; + P_IGNORE_TOK_ERR :bit1; + RESERVED0 :bit3; + P_BLK_LOCK_MODE :bit1; + P_ALWAYS_USE_FAST_TXCLK:bit1; + P_ELEC_IDLE_MODE :bit2; + DLP_IGNORE_IN_L1_EN :bit1; + RESERVED1 :bit15; + end; + + TPCIE_TX_SEQ=bitpacked record + TX_NEXT_TRANSMIT_SEQ:bit12; + RESERVED0 :bit4; + TX_ACKD_SEQ :bit12; + RESERVED1 :bit4; + end; + + TPERFMON_LOW=bit32; + + TPLL_DS_CNTL=bitpacked record + PLL_DS_FRAC :bit16; + PLL_DS_ORDER :bit2; + PLL_DS_MODE :bit1; + PLL_DS_PRBS_EN:bit1; + RESERVED0 :bit12; + end; + + TPLL_REF_DIV=bitpacked record + PLL_REF_DIV :bit10; + RESERVED0 :bit2; + PLL_CALIBRATION_REF_DIV:bit4; + RESERVED1 :bit16; + end; + + TPLL_SS_CNTL=bitpacked record + PLL_SS_AMOUNT_FBDIV :bit8; + PLL_SS_AMOUNT_NFRAC_SLIP:bit4; + PLL_SS_EN :bit1; + PLL_SS_MODE :bit1; + RESERVED0 :bit2; + PLL_SS_STEP_SIZE_DSFRAC :bit16; + end; + + TPM_FUSES_10=bitpacked record + GnbLPML_3:bit8; + GnbLPML_2:bit8; + GnbLPML_1:bit8; + GnbLPML_0:bit8; + end; + + TPM_FUSES_11=bitpacked record + GnbLPML_7:bit8; + GnbLPML_6:bit8; + GnbLPML_5:bit8; + GnbLPML_4:bit8; + end; + + TPM_FUSES_12=bitpacked record + GnbLPML_11:bit8; + GnbLPML_10:bit8; + GnbLPML_9 :bit8; + GnbLPML_8 :bit8; + end; + + TPM_FUSES_13=bitpacked record + GnbLPML_15:bit8; + GnbLPML_14:bit8; + GnbLPML_13:bit8; + GnbLPML_12:bit8; + end; + + TPM_FUSES_14=bitpacked record + Reserved1_1 :bit8; + Reserved1_0 :bit8; + GnbLPMLMinVid:bit8; + GnbLPMLMaxVid:bit8; + end; + + TPM_FUSES_15=bitpacked record + BapmVddCBaseLeakageLoSidd:bit16; + BapmVddCBaseLeakageHiSidd:bit16; + end; + + TPPLL_SPARE0=bit32; + + TPPLL_SPARE1=bit32; + + TREFCLK_CNTL=bitpacked record + REFCLK_CLOCK_EN:bit1; + REFCLK_SRC_SEL :bit1; + RESERVED0 :bit30; + end; + + TREVISION_ID=bitpacked record + MINOR_REV_ID:bit4; + MAJOR_REV_ID:bit4; + RESERVED0 :bit24; + end; + + TRIRB_STATUS=bitpacked record + RESPONSE_INTERRUPT :bit1; + RESERVED0 :bit1; + RESPONSE_OVERRUN_INTERRUPT_STATUS:bit1; + RESERVED1 :bit29; + end; + + TRLC_LB_CNTL=bitpacked record + LOAD_BALANCE_ENABLE :bit1; + LB_CNT_CP_BUSY :bit1; + LB_CNT_SPIM_ACTIVE :bit1; + LB_CNT_REG_INC :bit1; + CU_MASK_USED_OFF_HYST:bit8; + RESERVED0 :bit20; + end; + + TRLC_MC_CNTL=bitpacked record + WRREQ_SWAP :bit2; + WRREQ_TRAN :bit1; + WRREQ_PRIV :bit1; + WRNFO_STALL :bit1; + WRNFO_URG :bit4; + WRREQ_DW_IMASK:bit4; + RESERVED_B :bit7; + RDNFO_URG :bit4; + RDREQ_SWAP :bit2; + RDREQ_TRAN :bit1; + RDREQ_PRIV :bit1; + RDNFO_STALL :bit1; + RESERVED :bit3; + end; + + TRLC_PG_CNTL=bitpacked record + GFX_POWER_GATING_ENABLE :bit1; + GFX_POWER_GATING_SRC :bit1; + DYN_PER_CU_PG_ENABLE :bit1; + STATIC_PER_CU_PG_ENABLE :bit1; + GFX_PIPELINE_PG_ENABLE :bit1; + RESERVED :bit9; + PG_OVERRIDE :bit1; + CP_PG_DISABLE :bit1; + CHUB_HANDSHAKE_ENABLE :bit1; + SMU_CLK_SLOWDOWN_ON_PU_ENABLE:bit1; + SMU_CLK_SLOWDOWN_ON_PD_ENABLE:bit1; + SMU_HANDSHAKE_ENABLE :bit1; + RESERVED1 :bit4; + PG_ERROR_STATUS :bit8; + end; + + TROM_SW_CNTL=bitpacked record + DATA_SIZE :bit16; + COMMAND_SIZE :bit2; + ROM_SW_RETURN_DATA_ENABLE:bit1; + RESERVED0 :bit13; + end; + + TSCLV_DEBUG2=bitpacked record + SCL_DEBUG_REQ_MODE:bit1; + SCL_DEBUG_EOF_MODE:bit2; + SCL_DEBUG2 :bit29; + end; + + TSCLV_UPDATE=bitpacked record + SCL_UPDATE_PENDING :bit1; + RESERVED0 :bit7; + SCL_UPDATE_TAKEN :bit1; + RESERVED1 :bit7; + SCL_UPDATE_LOCK :bit1; + RESERVED2 :bit7; + SCL_COEF_UPDATE_COMPLETE:bit1; + RESERVED3 :bit7; + end; + + TSCL_CONTROL=bitpacked record + SCL_BOUNDARY_MODE :bit1; + RESERVED0 :bit3; + SCL_EARLY_EOL_MODE:bit1; + RESERVED1 :bit27; + end; + + TSDMA_CONFIG=bitpacked record + RESERVED0 :bit8; + SDMA_RDREQ_URG:bit4; + RESERVED1 :bit4; + SDMA_REQ_TRAN :bit1; + RESERVED2 :bit15; + end; + + TSEM_MAILBOX=bitpacked record + SIDEPORT :bit8; + HOSTPORT :bit8; + SIDEPORT_EXTRA:bit8; + HOSTPORT_EXTRA:bit8; + end; + + TSMC_RESP_10=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMC_RESP_11=bitpacked record + SMC_RESP :bit16; + RESERVED0:bit16; + end; + + TSMU_CONTROL=bitpacked record + DISPLAY0_FORCE_VBI :bit1; + DISPLAY1_FORCE_VBI :bit1; + DISPLAY2_FORCE_VBI :bit1; + DISPLAY3_FORCE_VBI :bit1; + DISPLAY4_FORCE_VBI :bit1; + DISPLAY5_FORCE_VBI :bit1; + DISPLAY_V0_FORCE_VBI:bit1; + RESERVED0 :bit9; + SMU_DC_INT_CLEAR :bit1; + RESERVED1 :bit15; + end; + + TSMU_EFUSE_0=bit32; + + TSM_CONTROL2=bitpacked record + SM_MODE :bit3; + RESERVED0 :bit1; + SM_FRAME_ALTERNATE :bit1; + SM_FIELD_ALTERNATE :bit1; + RESERVED1 :bit2; + SM_FORCE_NEXT_FRAME_POL:bit2; + RESERVED2 :bit6; + SM_FORCE_NEXT_TOP_POL :bit2; + RESERVED3 :bit6; + SM_CURRENT_FRAME_POL :bit1; + RESERVED4 :bit7; + end; + TSPI_EDC_CNT=bitpacked record SED :bit8; RESERVED0:bit24; end; + TSPMI_PATH_0=bitpacked record + PATH_ENABLE_REQ :bit1; + PATH_ENABLE_ACK :bit1; + RESERVED0 :bit2; + PATH_ENABLE_REQ_auto_clear:bit1; + RESERVED1 :bit27; + end; + + TSQC_EDC_CNT=bitpacked record + INST_SEC:bit8; + INST_DED:bit8; + DATA_SEC:bit8; + DATA_DED:bit8; + end; + + TSQ_DSM_CNTL=bitpacked record + WAVEFRONT_STALL_0 :bit1; + WAVEFRONT_STALL_1 :bit1; + SPI_BACKPRESSURE_0 :bit1; + SPI_BACKPRESSURE_1 :bit1; + RESERVED0 :bit4; + SEL_DSM_SGPR_IRRITATOR_DATA0:bit1; + SEL_DSM_SGPR_IRRITATOR_DATA1:bit1; + SGPR_ENABLE_SINGLE_WRITE :bit1; + RESERVED1 :bit5; + SEL_DSM_LDS_IRRITATOR_DATA0 :bit1; + SEL_DSM_LDS_IRRITATOR_DATA1 :bit1; + LDS_ENABLE_SINGLE_WRITE01 :bit1; + SEL_DSM_LDS_IRRITATOR_DATA2 :bit1; + SEL_DSM_LDS_IRRITATOR_DATA3 :bit1; + LDS_ENABLE_SINGLE_WRITE23 :bit1; + RESERVED2 :bit2; + SEL_DSM_SP_IRRITATOR_DATA0 :bit1; + SEL_DSM_SP_IRRITATOR_DATA1 :bit1; + SP_ENABLE_SINGLE_WRITE :bit1; + RESERVED3 :bit5; + end; + + TSQ_EDC_INFO=bitpacked record + WAVE_ID :bit4; + SIMD_ID :bit2; + SOURCE :bit3; + VM_ID :bit4; + RESERVED0:bit19; + end; + + TSQ_IND_DATA=bit32; + + TSQ_VOP_SDWA=bitpacked record + SRC0 :bit8; + DST_SEL :bit3; + DST_UNUSED:bit2; + CLAMP :bit1; + RESERVED0 :bit2; + SRC0_SEL :bit3; + SRC0_SEXT :bit1; + SRC0_NEG :bit1; + SRC0_ABS :bit1; + RESERVED1 :bit2; + SRC1_SEL :bit3; + SRC1_SEXT :bit1; + SRC1_NEG :bit1; + SRC1_ABS :bit1; + RESERVED2 :bit2; + end; + + TSRBM_STATUS=bitpacked record + RESERVED0 :bit1; + UVD_RQ_PENDING :bit1; + SAMMSP_RQ_PENDING :bit1; + ACP_RQ_PENDING :bit1; + SMU_RQ_PENDING :bit1; + GRBM_RQ_PENDING :bit1; + HI_RQ_PENDING :bit1; + RESERVED1 :bit1; + VMC_BUSY :bit1; + MCB_BUSY :bit1; + MCB_NON_DISPLAY_BUSY:bit1; + MCC_BUSY :bit1; + MCD_BUSY :bit1; + VMC1_BUSY :bit1; + SEM_BUSY :bit1; + RESERVED2 :bit1; + ACP_BUSY :bit1; + IH_BUSY :bit1; + RESERVED3 :bit1; + UVD_BUSY :bit1; + SAMMSP_BUSY :bit1; + GCATCL2_BUSY :bit1; + OSATCL2_BUSY :bit1; + RESERVED4 :bit6; + BIF_BUSY :bit1; + RESERVED5 :bit2; + end; + TTA_CNTL_AUX=bitpacked record SCOAL_DSWIZZLE_N :bit1; RESERVED :bit3; @@ -686,6 +4794,24 @@ type RESERVED0 :bit29; end; + TVCE_RB_RPTR=bitpacked record + RESERVED0:bit4; + RB_RPTR :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_SIZE=bitpacked record + RESERVED0:bit4; + RB_SIZE :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_WPTR=bitpacked record + RESERVED0:bit4; + RB_WPTR :bit19; + RESERVED1:bit9; + end; + TVGT_ENHANCE=bit32; TVGT_GS_MODE=bitpacked record @@ -707,13 +4833,391 @@ type RESERVED0 :bit9; end; + TVM_L2_CNTL2=bitpacked record + INVALIDATE_ALL_L1_TLBS :bit1; + INVALIDATE_L2_CACHE :bit1; + RESERVED0 :bit19; + DISABLE_INVALIDATE_PER_DOMAIN :bit1; + DISABLE_BIGK_CACHE_OPTIMIZATION:bit1; + L2_CACHE_BIGK_VMID_MODE :bit3; + INVALIDATE_CACHE_MODE :bit2; + PDE_CACHE_EFFECTIVE_SIZE :bit3; + RESERVED1 :bit1; + end; + + TVM_L2_CNTL3=bitpacked record + BANK_SELECT :bit6; + L2_CACHE_UPDATE_MODE :bit2; + L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE:bit5; + RESERVED0 :bit2; + L2_CACHE_BIGK_FRAGMENT_SIZE :bit5; + L2_CACHE_BIGK_ASSOCIATIVITY :bit1; + L2_CACHE_4K_EFFECTIVE_SIZE :bit3; + L2_CACHE_BIGK_EFFECTIVE_SIZE :bit4; + L2_CACHE_4K_FORCE_MISS :bit1; + L2_CACHE_BIGK_FORCE_MISS :bit1; + PDE_CACHE_FORCE_MISS :bit1; + L2_CACHE_4K_ASSOCIATIVITY :bit1; + end; + + TVM_L2_CNTL4=bitpacked record + L2_CACHE_4K_PARTITION_COUNT:bit6; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit20; + end; + + TVM_PRT_CNTL=bitpacked record + CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS :bit1; + TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS :bit1; + L2_CACHE_STORE_INVALID_ENTRIES :bit1; + L1_TLB_STORE_INVALID_ENTRIES :bit1; + CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS:bit1; + TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS:bit1; + MASK_PDE0_FAULT :bit1; + RESERVED0 :bit25; + end; + + TWAKE_ENABLE=bitpacked record + SDIN_WAKE_ENABLE_FLAG:bit1; + RESERVED0 :bit31; + end; + + TWB_DBG_MODE=bitpacked record + WB_DBG_MODE_EN :bit1; + WB_DBG_DIN_FMT :bit1; + WB_DBG_36MODE :bit1; + WB_DBG_CMAP :bit1; + RESERVED0 :bit4; + WB_DBG_PXLRATE_ERROR:bit1; + RESERVED1 :bit7; + WB_DBG_SOURCE_WIDTH :bit15; + RESERVED2 :bit1; + end; + + TWB_HW_DEBUG=bit32; + + TADAPTER_ID_W=bitpacked record + SUBSYSTEM_VENDOR_ID:bit16; + SUBSYSTEM_ID :bit16; + end; + + TAFMT_60958_0=bitpacked record + AFMT_60958_CS_A :bit1; + AFMT_60958_CS_B :bit1; + AFMT_60958_CS_C :bit1; + AFMT_60958_CS_D :bit3; + AFMT_60958_CS_MODE :bit2; + AFMT_60958_CS_CATEGORY_CODE :bit8; + AFMT_60958_CS_SOURCE_NUMBER :bit4; + AFMT_60958_CS_CHANNEL_NUMBER_L :bit4; + AFMT_60958_CS_SAMPLING_FREQUENCY:bit4; + AFMT_60958_CS_CLOCK_ACCURACY :bit2; + RESERVED0 :bit2; + end; + + TAFMT_60958_1=bitpacked record + AFMT_60958_CS_WORD_LENGTH :bit4; + AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY:bit4; + RESERVED0 :bit8; + AFMT_60958_VALID_L :bit1; + RESERVED1 :bit1; + AFMT_60958_VALID_R :bit1; + RESERVED2 :bit1; + AFMT_60958_CS_CHANNEL_NUMBER_R :bit4; + RESERVED3 :bit8; + end; + + TAFMT_60958_2=bitpacked record + AFMT_60958_CS_CHANNEL_NUMBER_2:bit4; + AFMT_60958_CS_CHANNEL_NUMBER_3:bit4; + AFMT_60958_CS_CHANNEL_NUMBER_4:bit4; + AFMT_60958_CS_CHANNEL_NUMBER_5:bit4; + AFMT_60958_CS_CHANNEL_NUMBER_6:bit4; + AFMT_60958_CS_CHANNEL_NUMBER_7:bit4; + RESERVED0 :bit8; + end; + + TAFMT_ISRC1_0=bitpacked record + AFMT_ISRC_STATUS :bit3; + RESERVED0 :bit3; + AFMT_ISRC_CONTINUE:bit1; + AFMT_ISRC_VALID :bit1; + RESERVED1 :bit24; + end; + + TAFMT_ISRC1_1=bitpacked record + AFMT_UPC_EAN_ISRC0:bit8; + AFMT_UPC_EAN_ISRC1:bit8; + AFMT_UPC_EAN_ISRC2:bit8; + AFMT_UPC_EAN_ISRC3:bit8; + end; + + TAFMT_ISRC1_2=bitpacked record + AFMT_UPC_EAN_ISRC4:bit8; + AFMT_UPC_EAN_ISRC5:bit8; + AFMT_UPC_EAN_ISRC6:bit8; + AFMT_UPC_EAN_ISRC7:bit8; + end; + + TAFMT_ISRC1_3=bitpacked record + AFMT_UPC_EAN_ISRC8 :bit8; + AFMT_UPC_EAN_ISRC9 :bit8; + AFMT_UPC_EAN_ISRC10:bit8; + AFMT_UPC_EAN_ISRC11:bit8; + end; + + TAFMT_ISRC1_4=bitpacked record + AFMT_UPC_EAN_ISRC12:bit8; + AFMT_UPC_EAN_ISRC13:bit8; + AFMT_UPC_EAN_ISRC14:bit8; + AFMT_UPC_EAN_ISRC15:bit8; + end; + + TAFMT_ISRC2_0=bitpacked record + AFMT_UPC_EAN_ISRC16:bit8; + AFMT_UPC_EAN_ISRC17:bit8; + AFMT_UPC_EAN_ISRC18:bit8; + AFMT_UPC_EAN_ISRC19:bit8; + end; + + TAFMT_ISRC2_1=bitpacked record + AFMT_UPC_EAN_ISRC20:bit8; + AFMT_UPC_EAN_ISRC21:bit8; + AFMT_UPC_EAN_ISRC22:bit8; + AFMT_UPC_EAN_ISRC23:bit8; + end; + + TAFMT_ISRC2_2=bitpacked record + AFMT_UPC_EAN_ISRC24:bit8; + AFMT_UPC_EAN_ISRC25:bit8; + AFMT_UPC_EAN_ISRC26:bit8; + AFMT_UPC_EAN_ISRC27:bit8; + end; + + TAFMT_ISRC2_3=bitpacked record + AFMT_UPC_EAN_ISRC28:bit8; + AFMT_UPC_EAN_ISRC29:bit8; + AFMT_UPC_EAN_ISRC30:bit8; + AFMT_UPC_EAN_ISRC31:bit8; + end; + + TATC_ATS_CNTL=bitpacked record + DISABLE_ATC :bit1; + DISABLE_PRI :bit1; + DISABLE_PASID :bit1; + RESERVED0 :bit5; + CREDITS_ATS_RPB:bit6; + RESERVED1 :bit2; + DEBUG_ECO :bit4; + RESERVED2 :bit12; + end; + + TATC_L2_CNTL2=bitpacked record + BANK_SELECT :bit6; + L2_CACHE_UPDATE_MODE :bit2; + ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE :bit1; + L2_CACHE_SWAP_TAG_INDEX_LSBS :bit3; + L2_CACHE_VMID_MODE :bit3; + L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE:bit6; + RESERVED0 :bit11; + end; + + TATC_L2_CNTL3=bitpacked record + ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING :bit7; + ENABLE_FREE_COUNTER :bit1; + L2_CACHE_EVICTION_THRESHOLD :bit5; + DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION:bit1; + L2_DELAY_SEND_INVALIDATION_REQUEST :bit3; + RESERVED0 :bit15; + end; + + TATC_L2_DEBUG=bitpacked record + CREDITS_L2_ATS :bit6; + RESERVED0 :bit1; + L2_MEM_SELECT :bit1; + CACHE_INDEX :bit12; + RESERVED1 :bit4; + CACHE_SELECT :bit1; + CACHE_BANK_SELECT :bit1; + RESERVED2 :bit1; + CACHE_WAY_SELECT :bit1; + RESERVED3 :bit1; + CACHE_READ :bit1; + CACHE_INJECT_SOFT_PARITY_ERROR:bit1; + CACHE_INJECT_HARD_PARITY_ERROR:bit1; + end; + + TAZALIA_DEBUG=bit32; + + TBIF_CLK_CTRL=bitpacked record + BIF_XSTCLK_READY :bit1; + BACO_XSTCLK_SWITCH_BYPASS:bit1; + RESERVED0 :bit30; + end; + + TBIF_SCRATCH0=bit32; + + TBIF_SCRATCH1=bit32; + + TBIF_SMU_DATA=bitpacked record + RESERVED0 :bit2; + BIF_SMU_DATA:bit17; + RESERVED1 :bit13; + end; + + TBLND_CONTROL=bitpacked record + BLND_GLOBAL_GAIN :bit8; + BLND_MODE :bit2; + BLND_STEREO_TYPE :bit2; + BLND_STEREO_POLARITY:bit1; + BLND_FEEDTHROUGH_EN :bit1; + RESERVED0 :bit2; + BLND_ALPHA_MODE :bit2; + RESERVED1 :bit2; + BLND_MULTIPLIED_MODE:bit1; + RESERVED2 :bit3; + BLND_GLOBAL_ALPHA :bit8; + end; + + TBL_PWM_CNTL2=bitpacked record + BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE:bit16; + RESERVED0 :bit12; + DBG_BL_PWM_INPUT_REFCLK_SELECT :bit2; + BL_PWM_OVERRIDE_BL_OUT_ENABLE :bit1; + BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN :bit1; + end; + TCB_BLEND_RED=bit32; + TCC_RCU_FUSES=bitpacked record + RESERVED0 :bit1; + GPU_DIS :bit1; + DEBUG_DISABLE :bit1; + RESERVED1 :bit1; + EFUSE_RD_DISABLE :bit1; + CG_RST_GLB_REQ_DIS :bit1; + DRV_RST_MODE :bit1; + ROM_DIS :bit1; + JPC_REP_DISABLE :bit1; + RCU_BREAK_POINT1 :bit1; + RCU_BREAK_POINT2 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + SMU_IOC_MST_DISABLE :bit1; + FCH_LOCKOUT_ENABLE :bit1; + FCH_XFIRE_FILTER_ENABLE:bit1; + XFIRE_DISABLE :bit1; + SAMU_FUSE_DISABLE :bit1; + BIF_RST_POLLING_DISABLE:bit1; + RESERVED5 :bit1; + MEM_HARDREP_EN :bit1; + PCIE_INIT_DISABLE :bit1; + DSMU_DISABLE :bit1; + WRP_FUSE_VALID :bit1; + PHY_FUSE_VALID :bit1; + RCU_SPARE :bit6; + end; + + TCG_ACLK_CNTL=bitpacked record + ACLK_DIVIDER :bit7; + RESERVED0 :bit1; + ACLK_DIR_CNTL_EN :bit1; + ACLK_DIR_CNTL_TOG :bit1; + ACLK_DIR_CNTL_DIVIDER:bit7; + RESERVED1 :bit15; + end; + + TCG_ACPI_CNTL=bitpacked record + SCLK_ACPI_DIV :bit7; + SCLK_CHANGE_SKIP:bit1; + RESERVED0 :bit24; + end; + + TCG_DCLK_CNTL=bitpacked record + DCLK_DIVIDER :bit7; + RESERVED0 :bit1; + DCLK_DIR_CNTL_EN :bit1; + DCLK_DIR_CNTL_TOG :bit1; + DCLK_DIR_CNTL_DIVIDER:bit7; + RESERVED1 :bit15; + end; + + TCG_ECLK_CNTL=bitpacked record + ECLK_DIVIDER :bit7; + RESERVED0 :bit1; + ECLK_DIR_CNTL_EN :bit1; + ECLK_DIR_CNTL_TOG :bit1; + ECLK_DIR_CNTL_DIVIDER:bit7; + RESERVED1 :bit15; + end; + + TCG_FDO_CTRL0=bitpacked record + FDO_STATIC_DUTY:bit8; + FAN_SPINUP_DUTY:bit8; + FDO_PWM_MANUAL :bit1; + FDO_PWM_HYSTER :bit6; + FDO_PWM_RAMP_EN:bit1; + FDO_PWM_RAMP :bit8; + end; + + TCG_FDO_CTRL1=bitpacked record + FMAX_DUTY100:bit8; + FMIN_DUTY :bit8; + M :bit8; + RESERVED :bit6; + FDO_PWRDNB :bit1; + RESERVED0 :bit1; + end; + + TCG_FDO_CTRL2=bitpacked record + TMIN :bit8; + FAN_SPINUP_TIME :bit3; + FDO_PWM_MODE :bit3; + TMIN_HYSTER :bit3; + TMAX :bit8; + TACH_PWM_RESP_RATE:bit7; + end; + + TCG_MCLK_CNTL=bitpacked record + MCLK_DIVIDER :bit7; + RESERVED0 :bit1; + MCLK_DIR_CNTL_EN :bit1; + MCLK_DIR_CNTL_TOG :bit1; + MCLK_DIR_CNTL_DIVIDER:bit7; + RESERVED1 :bit15; + end; + + TCG_TACH_CTRL=bitpacked record + EDGE_PER_REV :bit3; + TARGET_PERIOD:bit29; + end; + + TCG_VCLK_CNTL=bitpacked record + VCLK_DIVIDER :bit7; + RESERVED0 :bit1; + VCLK_DIR_CNTL_EN :bit1; + VCLK_DIR_CNTL_TOG :bit1; + VCLK_DIR_CNTL_DIVIDER:bit7; + RESERVED1 :bit15; + end; + TCOMPUTE_VMID=bitpacked record DATA :bit4; RESERVED0:bit28; end; + TCORB_CONTROL=bitpacked record + CORB_MEMORY_ERROR_INTERRUPT_ENABLE:bit1; + ENABLE_CORB_DMA_ENGINE :bit1; + RESERVED0 :bit30; + end; + TCPC_INT_CNTL=bitpacked record RESERVED0 :bit12; CMP_QUERY_STATUS_INT_ENABLE :bit1; @@ -811,6 +5315,11 @@ type RESERVED0 :bit30; end; + TCP_RB_OFFSET=bitpacked record + RB_OFFSET:bit20; + RESERVED0:bit12; + end; + TCP_ROQ_AVAIL=bitpacked record ROQ_CNT_RING:bit11; RESERVED0 :bit5; @@ -823,6 +5332,833 @@ type RESERVED0:bit23; end; + TCRTC_CONTROL=bitpacked record + CRTC_MASTER_EN :bit1; + RESERVED0 :bit3; + CRTC_SYNC_RESET_SEL :bit1; + RESERVED1 :bit3; + CRTC_DISABLE_POINT_CNTL :bit2; + RESERVED2 :bit2; + CRTC_START_POINT_CNTL :bit1; + CRTC_FIELD_NUMBER_CNTL :bit1; + CRTC_FIELD_NUMBER_POLARITY :bit1; + RESERVED3 :bit1; + CRTC_CURRENT_MASTER_EN_STATE :bit1; + RESERVED4 :bit3; + CRTC_HBLANK_EARLY_CONTROL :bit3; + RESERVED5 :bit1; + CRTC_DISP_READ_REQUEST_DISABLE:bit1; + RESERVED6 :bit4; + CRTC_SOF_PULL_EN :bit1; + CRTC_AVSYNC_LOCK_SNAPSHOT :bit1; + CRTC_AVSYNC_VSYNC_N_HSYNC_MODE:bit1; + end; + + TCRTC_H_TOTAL=bitpacked record + CRTC_H_TOTAL:bit14; + RESERVED0 :bit18; + end; + + TCRTC_VBI_END=bitpacked record + CRTC_VBI_V_END:bit14; + RESERVED0 :bit2; + CRTC_VBI_H_END:bit14; + RESERVED1 :bit2; + end; + + TCRTC_V_TOTAL=bitpacked record + CRTC_V_TOTAL:bit14; + RESERVED0 :bit18; + end; + + TCUR2_CONTROL=bitpacked record + CURSOR2_EN :bit1; + RESERVED0 :bit3; + CUR2_INV_TRANS_CLAMP :bit1; + RESERVED1 :bit3; + CURSOR2_MODE :bit2; + RESERVED2 :bit6; + CURSOR2_2X_MAGNIFY :bit1; + RESERVED3 :bit3; + CURSOR2_FORCE_MC_ON :bit1; + RESERVED4 :bit3; + CURSOR2_URGENT_CONTROL:bit3; + RESERVED5 :bit5; + end; + + TCUR_HOT_SPOT=bitpacked record + CURSOR_HOT_SPOT_Y:bit7; + RESERVED0 :bit9; + CURSOR_HOT_SPOT_X:bit7; + RESERVED1 :bit9; + end; + + TCUR_POSITION=bitpacked record + CURSOR_Y_POSITION:bit14; + RESERVED0 :bit2; + CURSOR_X_POSITION:bit14; + RESERVED1 :bit2; + end; + + TDAC_PWR_CNTL=bitpacked record + DAC_BG_MODE:bit2; + RESERVED0 :bit14; + DAC_PWRCNTL:bit2; + RESERVED1 :bit14; + end; + + TDBG_OUT_CNTL=bitpacked record + DBG_OUT_PIN_EN :bit1; + RESERVED0 :bit3; + DBG_OUT_PIN_SEL :bit1; + RESERVED1 :bit3; + DBG_OUT_12BIT_SEL:bit2; + RESERVED2 :bit2; + DBG_OUT_TEST_DATA:bit12; + RESERVED3 :bit8; + end; + + TDCCG_DS_CNTL=bitpacked record + DCCG_DS_ENABLE :bit1; + RESERVED0 :bit7; + DCCG_DS_HW_CAL_ENABLE :bit1; + DCCG_DS_ENABLED_STATUS :bit1; + RESERVED1 :bit6; + DCCG_DS_XTALIN_RATE_DIV :bit2; + RESERVED2 :bit6; + DCCG_DS_JITTER_REMOVE_DIS:bit1; + DCCG_DS_DELAY_XTAL_SEL :bit1; + RESERVED3 :bit6; + end; + + TDCFE_DBG_SEL=bitpacked record + DCFE_DBG_SEL:bit4; + RESERVED0 :bit28; + end; + + TDCIO_DEBUG10=bit32; + + TDCIO_DEBUG11=bit32; + + TDCIO_DEBUG12=bit32; + + TDCIO_DEBUG13=bit32; + + TDCIO_DEBUG14=bit32; + + TDCIO_DEBUG15=bit32; + + TDCIO_DEBUG16=bit32; + + TDCI_CLK_CNTL=bitpacked record + DCI_TEST_CLK_SEL :bit5; + DISPCLK_R_DCI_GATE_DIS :bit1; + DISPCLK_M_GATE_DIS :bit1; + SCLK_G_STREAM_AZ_GATE_DIS :bit1; + SCLK_R_AZ_GATE_DIS :bit1; + DISPCLK_G_FBC_GATE_DIS :bit1; + RESERVED0 :bit1; + DISPCLK_G_VGA_GATE_DIS :bit1; + RESERVED1 :bit1; + DISPCLK_G_VIP_GATE_DIS :bit1; + VPCLK_POL :bit1; + DISPCLK_G_DMCU_GATE_DIS :bit1; + DISPCLK_G_DMIF0_GATE_DIS :bit1; + DISPCLK_G_DMIF1_GATE_DIS :bit1; + DISPCLK_G_DMIF2_GATE_DIS :bit1; + DISPCLK_G_DMIF3_GATE_DIS :bit1; + DISPCLK_G_DMIF4_GATE_DIS :bit1; + DISPCLK_G_DMIF5_GATE_DIS :bit1; + SCLK_G_DMIF_GATE_DIS :bit1; + SCLK_G_DMIFTRK_GATE_DIS :bit1; + SCLK_G_CNTL_AZ_GATE_DIS :bit1; + DISPCLK_G_DMIFV_L_GATE_DIS:bit1; + DISPCLK_G_DMIFV_C_GATE_DIS:bit1; + DCI_PG_TEST_CLK_SEL :bit5; + end; + + TDCO_CLK_CNTL=bitpacked record + DCO_TEST_CLK_SEL :bit5; + DISPCLK_R_DCO_GATE_DIS :bit1; + DISPCLK_G_ABM_GATE_DIS :bit1; + DISPCLK_G_DVO_GATE_DIS :bit1; + DISPCLK_G_DACA_GATE_DIS:bit1; + DISPCLK_G_DACB_GATE_DIS:bit1; + REFCLK_R_DCO_GATE_DIS :bit1; + RESERVED0 :bit5; + DISPCLK_G_FMT0_GATE_DIS:bit1; + DISPCLK_G_FMT1_GATE_DIS:bit1; + DISPCLK_G_FMT2_GATE_DIS:bit1; + DISPCLK_G_FMT3_GATE_DIS:bit1; + DISPCLK_G_FMT4_GATE_DIS:bit1; + DISPCLK_G_FMT5_GATE_DIS:bit1; + RESERVED1 :bit2; + DISPCLK_G_DIGA_GATE_DIS:bit1; + DISPCLK_G_DIGB_GATE_DIS:bit1; + DISPCLK_G_DIGC_GATE_DIS:bit1; + DISPCLK_G_DIGD_GATE_DIS:bit1; + DISPCLK_G_DIGE_GATE_DIS:bit1; + DISPCLK_G_DIGF_GATE_DIS:bit1; + DISPCLK_G_DIGG_GATE_DIS:bit1; + RESERVED2 :bit1; + end; + + TDCO_SCRATCH0=bit32; + + TDCO_SCRATCH1=bit32; + + TDCO_SCRATCH2=bit32; + + TDCO_SCRATCH3=bit32; + + TDCO_SCRATCH4=bit32; + + TDCO_SCRATCH5=bit32; + + TDCO_SCRATCH6=bit32; + + TDCO_SCRATCH7=bit32; + + TDCP_CRC_LAST=bit32; + + TDCP_CRC_MASK=bit32; + + TDC_ABM1_CNTL=bitpacked record + ABM1_EN :bit1; + RESERVED0 :bit7; + ABM1_SOURCE_SELECT :bit3; + RESERVED1 :bit20; + ABM1_BLANK_MODE_SUPPORT_ENABLE:bit1; + end; + + TDC_PINSTRAPS=bitpacked record + RESERVED0 :bit10; + DC_PINSTRAPS_BIF_CEC_DIS :bit1; + RESERVED1 :bit2; + DC_PINSTRAPS_SMS_EN_HARD :bit1; + DC_PINSTRAPS_AUDIO :bit2; + DC_PINSTRAPS_CCBYPASS :bit1; + DC_PINSTRAPS_CONNECTIVITY:bit3; + RESERVED2 :bit12; + end; + + TDEVICE_CNTL2=bitpacked record + CPL_TIMEOUT_VALUE :bit4; + CPL_TIMEOUT_DIS :bit1; + ARI_FORWARDING_EN :bit1; + ATOMICOP_REQUEST_EN :bit1; + ATOMICOP_EGRESS_BLOCKING :bit1; + IDO_REQUEST_ENABLE :bit1; + IDO_COMPLETION_ENABLE :bit1; + LTR_EN :bit1; + RESERVED0 :bit2; + OBFF_EN :bit2; + END_END_TLP_PREFIX_BLOCKING:bit1; + RESERVED1 :bit16; + end; + + TDMCU_INT_CNT=bitpacked record + DMCU_ABM1_HG_READY_INT_CNT :bit8; + DMCU_ABM1_LS_READY_INT_CNT :bit8; + DMCU_ABM1_BL_UPDATE_INT_CNT:bit8; + RESERVED0 :bit8; + end; + + TDMIF_CONTROL=bitpacked record + DMIF_BUFF_SIZE :bit2; + DMIF_GROUP_REQUESTS_IN_CHUNK :bit1; + RESERVED0 :bit1; + DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT :bit1; + RESERVED1 :bit3; + DMIF_REQ_BURST_SIZE :bit3; + DMIF_UNDERFLOW_RECOVERY_EN :bit1; + DMIF_FORCE_TOTAL_REQ_BURST_SIZE :bit4; + DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS:bit6; + RESERVED2 :bit2; + DMIF_DELAY_ARBITRATION :bit5; + DMIF_CHUNK_BUFF_MARGIN :bit2; + RESERVED3 :bit1; + end; + + TDMIF_DEBUG02=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit1; + RESERVED6:bit1; + RESERVED7:bit25; + end; + + TDMIF_STATUS2=bitpacked record + DMIF_PIPE0_DISPCLK_STATUS :bit1; + DMIF_PIPE1_DISPCLK_STATUS :bit1; + DMIF_PIPE2_DISPCLK_STATUS :bit1; + DMIF_PIPE3_DISPCLK_STATUS :bit1; + DMIF_PIPE4_DISPCLK_STATUS :bit1; + DMIF_PIPE5_DISPCLK_STATUS :bit1; + RESERVED0 :bit2; + DMIF_CHUNK_TRACKER_SCLK_STATUS:bit1; + DMIF_FBC_TRACKER_SCLK_STATUS :bit1; + RESERVED1 :bit22; + end; + + TDPM_TABLE_10=bit32; + + TDPM_TABLE_11=bit32; + + TDPM_TABLE_12=bit32; + + TDPM_TABLE_13=bit32; + + TDPM_TABLE_14=bit32; + + TDPM_TABLE_15=bit32; + + TDPM_TABLE_16=bit32; + + TDPM_TABLE_17=bit32; + + TDPM_TABLE_18=bit32; + + TDPM_TABLE_19=bit32; + + TDPM_TABLE_20=bit32; + + TDPM_TABLE_21=bit32; + + TDPM_TABLE_22=bit32; + + TDPM_TABLE_23=bit32; + + TDPM_TABLE_24=bit32; + + TDPM_TABLE_25=bit32; + + TDPM_TABLE_26=bit32; + + TDPM_TABLE_27=bit32; + + TDPM_TABLE_28=bit32; + + TDPM_TABLE_29=bit32; + + TDPM_TABLE_30=bit32; + + TDPM_TABLE_31=bit32; + + TDPM_TABLE_32=bitpacked record + SmioTable1_Pattern_0_padding:bit8; + SmioTable1_Pattern_0_Smio :bit8; + SmioTable1_Pattern_0_Voltage:bit16; + end; + + TDPM_TABLE_33=bitpacked record + SmioTable1_Pattern_1_padding:bit8; + SmioTable1_Pattern_1_Smio :bit8; + SmioTable1_Pattern_1_Voltage:bit16; + end; + + TDPM_TABLE_34=bitpacked record + SmioTable1_Pattern_2_padding:bit8; + SmioTable1_Pattern_2_Smio :bit8; + SmioTable1_Pattern_2_Voltage:bit16; + end; + + TDPM_TABLE_35=bitpacked record + SmioTable1_Pattern_3_padding:bit8; + SmioTable1_Pattern_3_Smio :bit8; + SmioTable1_Pattern_3_Voltage:bit16; + end; + + TDPM_TABLE_36=bitpacked record + SmioTable2_Pattern_0_padding:bit8; + SmioTable2_Pattern_0_Smio :bit8; + SmioTable2_Pattern_0_Voltage:bit16; + end; + + TDPM_TABLE_37=bitpacked record + SmioTable2_Pattern_1_padding:bit8; + SmioTable2_Pattern_1_Smio :bit8; + SmioTable2_Pattern_1_Voltage:bit16; + end; + + TDPM_TABLE_38=bitpacked record + SmioTable2_Pattern_2_padding:bit8; + SmioTable2_Pattern_2_Smio :bit8; + SmioTable2_Pattern_2_Voltage:bit16; + end; + + TDPM_TABLE_39=bitpacked record + SmioTable2_Pattern_3_padding:bit8; + SmioTable2_Pattern_3_Smio :bit8; + SmioTable2_Pattern_3_Voltage:bit16; + end; + + TDPM_TABLE_40=bit32; + + TDPM_TABLE_41=bit32; + + TDPM_TABLE_42=bit32; + + TDPM_TABLE_43=bit32; + + TDPM_TABLE_44=bitpacked record + VddcTable_1:bit16; + VddcTable_0:bit16; + end; + + TDPM_TABLE_45=bitpacked record + VddcTable_3:bit16; + VddcTable_2:bit16; + end; + + TDPM_TABLE_46=bitpacked record + VddcTable_5:bit16; + VddcTable_4:bit16; + end; + + TDPM_TABLE_47=bitpacked record + VddcTable_7:bit16; + VddcTable_6:bit16; + end; + + TDPM_TABLE_48=bitpacked record + VddcTable_9:bit16; + VddcTable_8:bit16; + end; + + TDPM_TABLE_49=bitpacked record + VddcTable_11:bit16; + VddcTable_10:bit16; + end; + + TDPM_TABLE_50=bitpacked record + VddcTable_13:bit16; + VddcTable_12:bit16; + end; + + TDPM_TABLE_51=bitpacked record + VddcTable_15:bit16; + VddcTable_14:bit16; + end; + + TDPM_TABLE_52=bitpacked record + VddGfxTable_1:bit16; + VddGfxTable_0:bit16; + end; + + TDPM_TABLE_53=bitpacked record + VddGfxTable_3:bit16; + VddGfxTable_2:bit16; + end; + + TDPM_TABLE_54=bitpacked record + VddGfxTable_5:bit16; + VddGfxTable_4:bit16; + end; + + TDPM_TABLE_55=bitpacked record + VddGfxTable_7:bit16; + VddGfxTable_6:bit16; + end; + + TDPM_TABLE_56=bitpacked record + VddGfxTable_9:bit16; + VddGfxTable_8:bit16; + end; + + TDPM_TABLE_57=bitpacked record + VddGfxTable_11:bit16; + VddGfxTable_10:bit16; + end; + + TDPM_TABLE_58=bitpacked record + VddGfxTable_13:bit16; + VddGfxTable_12:bit16; + end; + + TDPM_TABLE_59=bitpacked record + VddGfxTable_15:bit16; + VddGfxTable_14:bit16; + end; + + TDPM_TABLE_60=bitpacked record + VddciTable_1:bit16; + VddciTable_0:bit16; + end; + + TDPM_TABLE_61=bitpacked record + VddciTable_3:bit16; + VddciTable_2:bit16; + end; + + TDPM_TABLE_62=bitpacked record + VddciTable_5:bit16; + VddciTable_4:bit16; + end; + + TDPM_TABLE_63=bitpacked record + VddciTable_7:bit16; + VddciTable_6:bit16; + end; + + TDPM_TABLE_64=bitpacked record + BapmVddGfxVidHiSidd_3:bit8; + BapmVddGfxVidHiSidd_2:bit8; + BapmVddGfxVidHiSidd_1:bit8; + BapmVddGfxVidHiSidd_0:bit8; + end; + + TDPM_TABLE_65=bitpacked record + BapmVddGfxVidHiSidd_7:bit8; + BapmVddGfxVidHiSidd_6:bit8; + BapmVddGfxVidHiSidd_5:bit8; + BapmVddGfxVidHiSidd_4:bit8; + end; + + TDPM_TABLE_66=bitpacked record + BapmVddGfxVidHiSidd_11:bit8; + BapmVddGfxVidHiSidd_10:bit8; + BapmVddGfxVidHiSidd_9 :bit8; + BapmVddGfxVidHiSidd_8 :bit8; + end; + + TDPM_TABLE_67=bitpacked record + BapmVddGfxVidHiSidd_15:bit8; + BapmVddGfxVidHiSidd_14:bit8; + BapmVddGfxVidHiSidd_13:bit8; + BapmVddGfxVidHiSidd_12:bit8; + end; + + TDPM_TABLE_68=bitpacked record + BapmVddGfxVidLoSidd_3:bit8; + BapmVddGfxVidLoSidd_2:bit8; + BapmVddGfxVidLoSidd_1:bit8; + BapmVddGfxVidLoSidd_0:bit8; + end; + + TDPM_TABLE_69=bitpacked record + BapmVddGfxVidLoSidd_7:bit8; + BapmVddGfxVidLoSidd_6:bit8; + BapmVddGfxVidLoSidd_5:bit8; + BapmVddGfxVidLoSidd_4:bit8; + end; + + TDPM_TABLE_70=bitpacked record + BapmVddGfxVidLoSidd_11:bit8; + BapmVddGfxVidLoSidd_10:bit8; + BapmVddGfxVidLoSidd_9 :bit8; + BapmVddGfxVidLoSidd_8 :bit8; + end; + + TDPM_TABLE_71=bitpacked record + BapmVddGfxVidLoSidd_15:bit8; + BapmVddGfxVidLoSidd_14:bit8; + BapmVddGfxVidLoSidd_13:bit8; + BapmVddGfxVidLoSidd_12:bit8; + end; + + TDPM_TABLE_72=bitpacked record + BapmVddGfxVidHiSidd2_3:bit8; + BapmVddGfxVidHiSidd2_2:bit8; + BapmVddGfxVidHiSidd2_1:bit8; + BapmVddGfxVidHiSidd2_0:bit8; + end; + + TDPM_TABLE_73=bitpacked record + BapmVddGfxVidHiSidd2_7:bit8; + BapmVddGfxVidHiSidd2_6:bit8; + BapmVddGfxVidHiSidd2_5:bit8; + BapmVddGfxVidHiSidd2_4:bit8; + end; + + TDPM_TABLE_74=bitpacked record + BapmVddGfxVidHiSidd2_11:bit8; + BapmVddGfxVidHiSidd2_10:bit8; + BapmVddGfxVidHiSidd2_9 :bit8; + BapmVddGfxVidHiSidd2_8 :bit8; + end; + + TDPM_TABLE_75=bitpacked record + BapmVddGfxVidHiSidd2_15:bit8; + BapmVddGfxVidHiSidd2_14:bit8; + BapmVddGfxVidHiSidd2_13:bit8; + BapmVddGfxVidHiSidd2_12:bit8; + end; + + TDPM_TABLE_76=bitpacked record + BapmVddcVidHiSidd_3:bit8; + BapmVddcVidHiSidd_2:bit8; + BapmVddcVidHiSidd_1:bit8; + BapmVddcVidHiSidd_0:bit8; + end; + + TDPM_TABLE_77=bitpacked record + BapmVddcVidHiSidd_7:bit8; + BapmVddcVidHiSidd_6:bit8; + BapmVddcVidHiSidd_5:bit8; + BapmVddcVidHiSidd_4:bit8; + end; + + TDPM_TABLE_78=bitpacked record + BapmVddcVidHiSidd_11:bit8; + BapmVddcVidHiSidd_10:bit8; + BapmVddcVidHiSidd_9 :bit8; + BapmVddcVidHiSidd_8 :bit8; + end; + + TDPM_TABLE_79=bitpacked record + BapmVddcVidHiSidd_15:bit8; + BapmVddcVidHiSidd_14:bit8; + BapmVddcVidHiSidd_13:bit8; + BapmVddcVidHiSidd_12:bit8; + end; + + TDPM_TABLE_80=bitpacked record + BapmVddcVidLoSidd_3:bit8; + BapmVddcVidLoSidd_2:bit8; + BapmVddcVidLoSidd_1:bit8; + BapmVddcVidLoSidd_0:bit8; + end; + + TDPM_TABLE_81=bitpacked record + BapmVddcVidLoSidd_7:bit8; + BapmVddcVidLoSidd_6:bit8; + BapmVddcVidLoSidd_5:bit8; + BapmVddcVidLoSidd_4:bit8; + end; + + TDPM_TABLE_82=bitpacked record + BapmVddcVidLoSidd_11:bit8; + BapmVddcVidLoSidd_10:bit8; + BapmVddcVidLoSidd_9 :bit8; + BapmVddcVidLoSidd_8 :bit8; + end; + + TDPM_TABLE_83=bitpacked record + BapmVddcVidLoSidd_15:bit8; + BapmVddcVidLoSidd_14:bit8; + BapmVddcVidLoSidd_13:bit8; + BapmVddcVidLoSidd_12:bit8; + end; + + TDPM_TABLE_84=bitpacked record + BapmVddcVidHiSidd2_3:bit8; + BapmVddcVidHiSidd2_2:bit8; + BapmVddcVidHiSidd2_1:bit8; + BapmVddcVidHiSidd2_0:bit8; + end; + + TDPM_TABLE_85=bitpacked record + BapmVddcVidHiSidd2_7:bit8; + BapmVddcVidHiSidd2_6:bit8; + BapmVddcVidHiSidd2_5:bit8; + BapmVddcVidHiSidd2_4:bit8; + end; + + TDPM_TABLE_86=bitpacked record + BapmVddcVidHiSidd2_11:bit8; + BapmVddcVidHiSidd2_10:bit8; + BapmVddcVidHiSidd2_9 :bit8; + BapmVddcVidHiSidd2_8 :bit8; + end; + + TDPM_TABLE_87=bitpacked record + BapmVddcVidHiSidd2_15:bit8; + BapmVddcVidHiSidd2_14:bit8; + BapmVddcVidHiSidd2_13:bit8; + BapmVddcVidHiSidd2_12:bit8; + end; + + TDPM_TABLE_88=bitpacked record + MasterDeepSleepControl:bit8; + LinkLevelCount :bit8; + MemoryDpmLevelCount :bit8; + GraphicsDpmLevelCount :bit8; + end; + + TDPM_TABLE_89=bitpacked record + SamuLevelCount:bit8; + AcpLevelCount :bit8; + VceLevelCount :bit8; + UvdLevelCount :bit8; + end; + + TDPM_TABLE_90=bitpacked record + Reserved_0 :bit8; + ThermOutMode :bit8; + ThermOutPolarity:bit8; + ThermOutGpio :bit8; + end; + + TDPM_TABLE_91=bit32; + + TDPM_TABLE_92=bit32; + + TDPM_TABLE_93=bit32; + + TDPM_TABLE_94=bit32; + + TDPM_TABLE_95=bitpacked record + GraphicsLevel_0_MinVoltage_Phases:bit8; + GraphicsLevel_0_MinVoltage_VddGfx:bit8; + GraphicsLevel_0_MinVoltage_Vddci :bit8; + GraphicsLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_96=bit32; + + TDPM_TABLE_97=bitpacked record + GraphicsLevel_0_ActivityLevel :bit16; + GraphicsLevel_0_DeepSleepDivId:bit8; + GraphicsLevel_0_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_98=bit32; + + TDPM_TABLE_99=bit32; + + TDP_DPHY_CNTL=bitpacked record + DPHY_ATEST_SEL_LANE0:bit1; + DPHY_ATEST_SEL_LANE1:bit1; + DPHY_ATEST_SEL_LANE2:bit1; + DPHY_ATEST_SEL_LANE3:bit1; + RESERVED0 :bit4; + RESERVED1 :bit1; + RESERVED2 :bit7; + DPHY_BYPASS :bit1; + RESERVED3 :bit7; + DPHY_SKEW_BYPASS :bit1; + RESERVED4 :bit7; + end; + + TDP_DPHY_SYM0=bitpacked record + DPHY_SYM1:bit10; + DPHY_SYM2:bit10; + DPHY_SYM3:bit10; + RESERVED0:bit2; + end; + + TDP_DPHY_SYM1=bitpacked record + DPHY_SYM4:bit10; + DPHY_SYM5:bit10; + DPHY_SYM6:bit10; + RESERVED0:bit2; + end; + + TDP_DPHY_SYM2=bitpacked record + DPHY_SYM7:bit10; + DPHY_SYM8:bit10; + RESERVED0:bit12; + end; + + TDP_LINK_CNTL=bitpacked record + RESERVED0 :bit4; + DP_LINK_TRAINING_COMPLETE:bit1; + RESERVED1 :bit3; + DP_LINK_STATUS :bit1; + RESERVED2 :bit8; + DP_EMBEDDED_PANEL_MODE :bit1; + RESERVED3 :bit14; + end; + + TDP_SEC_AUD_M=bitpacked record + DP_SEC_AUD_M:bit24; + RESERVED0 :bit8; + end; + + TDP_SEC_AUD_N=bitpacked record + DP_SEC_AUD_N:bit24; + RESERVED0 :bit4; + RESERVED1 :bit1; + RESERVED2 :bit3; + end; + + TDP_SEC_CNTL1=bitpacked record + DP_SEC_ISRC_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TEFUSE_STATUS=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit14; + RESERVED3:bit8; + RESERVED4:bit8; + end; + + TFBC_IND_LUT0=bitpacked record + FBC_IND_LUT0:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT1=bitpacked record + FBC_IND_LUT1:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT2=bitpacked record + FBC_IND_LUT2:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT3=bitpacked record + FBC_IND_LUT3:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT4=bitpacked record + FBC_IND_LUT4:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT5=bitpacked record + FBC_IND_LUT5:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT6=bitpacked record + FBC_IND_LUT6:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT7=bitpacked record + FBC_IND_LUT7:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT8=bitpacked record + FBC_IND_LUT8:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT9=bitpacked record + FBC_IND_LUT9:bit24; + RESERVED0 :bit8; + end; + + TFMT_CRC_CNTL=bitpacked record + FMT_CRC_EN :bit1; + FMT_DTMTEST_CRC_EN :bit1; + RESERVED0 :bit2; + FMT_CRC_CONT_EN :bit1; + RESERVED1 :bit3; + FMT_CRC_ONLY_BLANKB :bit1; + RESERVED2 :bit3; + FMT_CRC_INTERLACE_MODE :bit2; + RESERVED3 :bit2; + FMT_CRC_USE_NEW_AND_REPEATED_PIXELS:bit1; + RESERVED4 :bit3; + FMT_CRC_EVEN_ODD_PIX_ENABLE :bit1; + RESERVED5 :bit3; + FMT_CRC_EVEN_ODD_PIX_SELECT :bit1; + RESERVED6 :bit7; + end; + + TFMT_DEBUG_ID=bit32; + TGDS_ATOM_DST=bit32; TGDS_DSM_CNTL=bitpacked record @@ -897,6 +6233,11 @@ type RESERVED0:bit16; end; + TGPIOPAD_MASK=bitpacked record + GPIO_MASK:bit31; + RESERVED0:bit1; + end; + TGRBM_NOWHERE=bit32; TGRBM_STATUS2=bitpacked record @@ -930,6 +6271,970 @@ type TGRBM_TRAP_WD=bit32; + TGRPH_CONTROL=bitpacked record + GRPH_DEPTH :bit2; + GRPH_NUM_BANKS :bit2; + GRPH_Z :bit2; + GRPH_BANK_WIDTH :bit2; + GRPH_FORMAT :bit3; + GRPH_BANK_HEIGHT :bit2; + GRPH_TILE_SPLIT :bit3; + GRPH_ADDRESS_TRANSLATION_ENABLE:bit1; + GRPH_PRIVILEGED_ACCESS_ENABLE :bit1; + GRPH_MACRO_TILE_ASPECT :bit2; + GRPH_ARRAY_MODE :bit4; + GRPH_PIPE_CONFIG :bit5; + GRPH_MICRO_TILE_MODE :bit2; + GRPH_COLOR_EXPANSION_MODE :bit1; + end; + + TGRPH_X_START=bitpacked record + GRPH_X_START:bit14; + RESERVED0 :bit18; + end; + + TGRPH_Y_START=bitpacked record + GRPH_Y_START:bit14; + RESERVED0 :bit18; + end; + + TGSKT_CONTROL=bitpacked record + GSKT_TxFifoBypass:bit1; + GSKT_TxFifoDelay :bit1; + GSKT_TxFifoDelay2:bit1; + GSKT_SpareRegs :bit5; + RESERVED0 :bit24; + end; + + THDMI_CONTROL=bitpacked record + HDMI_KEEPOUT_MODE :bit1; + RESERVED0 :bit3; + HDMI_PACKET_GEN_VERSION:bit1; + RESERVED1 :bit3; + HDMI_ERROR_ACK :bit1; + HDMI_ERROR_MASK :bit1; + RESERVED2 :bit14; + HDMI_DEEP_COLOR_ENABLE :bit1; + RESERVED3 :bit3; + HDMI_DEEP_COLOR_DEPTH :bit2; + RESERVED4 :bit2; + end; + + THDP_XDP_CHKN=bitpacked record + CHKN_0_RSVD:bit8; + CHKN_1_RSVD:bit8; + CHKN_2_RSVD:bit8; + CHKN_3_RSVD:bit8; + end; + + TIH_VF_ENABLE=bitpacked record + VALUE :bit1; + RESERVED0:bit31; + end; + + TIMPCTL_RESET=bitpacked record + IMP_SW_RESET:bit1; + RESERVED0 :bit31; + end; + + TLB_V_COUNTER=bitpacked record + V_COUNTER:bit15; + RESERVED0:bit17; + end; + + TLINK_STATUS2=bitpacked record + CUR_DEEMPHASIS_LEVEL :bit1; + EQUALIZATION_COMPLETE :bit1; + EQUALIZATION_PHASE1_SUCCESS:bit1; + EQUALIZATION_PHASE2_SUCCESS:bit1; + EQUALIZATION_PHASE3_SUCCESS:bit1; + LINK_EQUALIZATION_REQUEST :bit1; + RESERVED0 :bit26; + end; + + TLNCNT_WEIGHT=bitpacked record + CFG_LNC_BW_WEIGHT0 :bit16; + CFG_LNC_CMN_WEIGHT16:bit16; + end; + + TLNC_CMN_WACC=bit32; + + TMCIF_CONTROL=bitpacked record + MCIF_BUFF_SIZE :bit2; + RESERVED0 :bit2; + ADDRESS_TRANSLATION_ENABLE :bit1; + RESERVED1 :bit3; + PRIVILEGED_ACCESS_ENABLE :bit1; + RESERVED2 :bit3; + MCIF_SLOW_REQ_INTERVAL :bit4; + LOW_READ_URG_LEVEL :bit8; + MC_CLEAN_DEASSERT_LATENCY :bit6; + MCIF_MC_LATENCY_COUNTER_ENABLE :bit1; + MCIF_MC_LATENCY_COUNTER_URGENT_ONLY:bit1; + end; + + TMC_ARB_GECC2=bitpacked record + ENABLE :bit1; + ECC_MODE :bit2; + PAGE_BIT0 :bit2; + EXOR_BANK_SEL :bit2; + NO_GECC_CLI :bit4; + READ_ERR :bit3; + CLOSE_BANK_RMW :bit1; + COLFIFO_WATER :bit6; + WRADDR_CONV :bit1; + RMWRD_UNCOR_POISON:bit1; + RESERVED0 :bit9; + end; + + TMC_ARB_GRUB2=bitpacked record + REALTIME_GRP_RD :bit8; + REALTIME_GRP_WR :bit8; + DISP_RD_STALL_EN :bit1; + ACP_RD_STALL_EN :bit1; + UVD_RD_STALL_EN :bit1; + VCE0_RD_STALL_EN :bit1; + VCE1_RD_STALL_EN :bit1; + REALTIME_RD_WTS :bit1; + REALTIME_WR_WTS :bit1; + URGENT_BY_DISP_STALL :bit1; + PROMOTE_BY_DMIF_URG :bit1; + PRIORITY_URGENT_OUTSTANDING_ONLY_RD :bit1; + PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD:bit1; + PRIORITY_URGENT_OUTSTANDING_ONLY_WR :bit1; + PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR:bit1; + RESERVED0 :bit3; + end; + + TMC_ARB_LM_RD=bitpacked record + STREAK_LIMIT :bit8; + STREAK_LIMIT_UBER :bit8; + STREAK_BREAK :bit1; + STREAK_UBER :bit1; + ENABLE_TWO_LIST :bit1; + POPIDLE_RST_TWOLIST:bit1; + SKID1_RST_TWOLIST :bit1; + BANKGROUP_CONFIG :bit3; + RESERVED0 :bit8; + end; + + TMC_ARB_LM_WR=bitpacked record + STREAK_LIMIT :bit8; + STREAK_LIMIT_UBER :bit8; + STREAK_BREAK :bit1; + STREAK_UBER :bit1; + ENABLE_TWO_LIST :bit1; + POPIDLE_RST_TWOLIST:bit1; + SKID1_RST_TWOLIST :bit1; + BANKGROUP_CONFIG :bit3; + MASKWR_LM_EOB :bit1; + ATOMIC_LM_EOB :bit1; + ATOMIC_RTN_LM_EOB :bit1; + RESERVED0 :bit5; + end; + + TMC_ARB_MISC2=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit2; + TCCDL4_BANKBIT3_XOR_ENABLE :bit1; + TCCDL4_BANKBIT3_XOR_COLBIT4:bit1; + TCCDL4_BANKBIT3_XOR_COLBIT5:bit1; + TCCDL4_BANKBIT3_XOR_COLBIT6:bit1; + TCCDL4_BANKBIT3_XOR_COLBIT7:bit1; + TCCDL4_BANKBIT3_XOR_COLBIT8:bit1; + POP_IDLE_REPLAY :bit1; + RDRET_NO_REORDERING :bit1; + RDRET_NO_BP :bit1; + RDRET_SEQ_SKID :bit4; + GECC :bit1; + GECC_RST :bit1; + GECC_STATUS :bit1; + TAGFIFO_THRESHOLD :bit4; + WCDR_REPLAY_MASKCNT :bit3; + REPLAY_DEBUG :bit1; + ARB_DEBUG29 :bit1; + SEQ_RDY_POP_IDLE :bit1; + TCCDL4_REPLAY_EOB :bit1; + end; + + TMC_ARB_MISC3=bitpacked record + NO_GECC_EXT_EOB :bit1; + CHAN4_EN :bit1; + CHAN4_ARB_SEL :bit1; + UVD_URG_MODE :bit1; + UVD_DMIF_HARSH_WT_EN:bit1; + TBD_FIELD :bit27; + end; + + TMC_ARB_SNOOP=bitpacked record + TC_GRP_RD :bit3; + TC_GRP_RD_EN :bit1; + TC_GRP_WR :bit3; + TC_GRP_WR_EN :bit1; + SDMA_GRP_RD :bit3; + SDMA_GRP_RD_EN:bit1; + SDMA_GRP_WR :bit3; + SDMA_GRP_WR_EN:bit1; + OUTSTANDING_RD:bit8; + OUTSTANDING_WR:bit8; + end; + + TMC_BIST_CNTL=bitpacked record + RESET :bit1; + RUN :bit1; + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit4; + RESERVED3:bit2; + RESERVED4:bit1; + RESERVED5:bit1; + LOOP_CNT :bit12; + RESERVED6:bit1; + RESERVED7:bit1; + RESERVED8:bit1; + RESERVED9:bit5; + end; + + TMC_CG_CONFIG=bitpacked record + MCDW_WR_ENABLE:bit1; + MCDX_WR_ENABLE:bit1; + MCDY_WR_ENABLE:bit1; + MCDZ_WR_ENABLE:bit1; + MC_RD_ENABLE :bit2; + INDEX :bit16; + RESERVED0 :bit10; + end; + + TMC_CITF_CNTL=bitpacked record + RESERVED0 :bit2; + IGNOREPM :bit1; + EXEMPTPM :bit1; + GFX_IDLE_OVERRIDE :bit2; + MCD_SRBM_MASK_ENABLE :bit1; + CNTR_CHMAP_MODE :bit2; + REMOTE_RB_CONNECT_ENABLE:bit1; + RESERVED1 :bit22; + end; + + TMC_SEQ_MISC0=bit32; + + TMC_SEQ_MISC1=bit32; + + TMC_SEQ_MISC3=bit32; + + TMC_SEQ_MISC4=bit32; + + TMC_SEQ_MISC5=bit32; + + TMC_SEQ_MISC6=bit32; + + TMC_SEQ_MISC7=bit32; + + TMC_SEQ_MISC8=bit32; + + TMC_SEQ_MISC9=bit32; + + TMSI_CAP_LIST=bitpacked record + CAP_ID :bit8; + NEXT_PTR :bit8; + RESERVED0:bit16; + end; + + TMSI_MSG_CNTL=bitpacked record + MSI_EN :bit1; + MSI_MULTI_CAP :bit3; + MSI_MULTI_EN :bit3; + MSI_64BIT :bit1; + MSI_PERVECTOR_MASKING_CAP:bit1; + RESERVED0 :bit23; + end; + + TMSI_MSG_DATA=bitpacked record + MSI_DATA :bit16; + RESERVED0:bit16; + end; + + TMVP_CONTROL1=bitpacked record + MVP_EN :bit1; + RESERVED0 :bit3; + MVP_MIXER_MODE :bit3; + RESERVED1 :bit1; + MVP_MIXER_SLAVE_SEL :bit1; + MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK :bit1; + MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE:bit1; + RESERVED2 :bit1; + MVP_RATE_CONTROL :bit1; + RESERVED3 :bit3; + MVP_CHANNEL_CONTROL :bit1; + RESERVED4 :bit3; + MVP_GPU_CHAIN_LOCATION :bit2; + RESERVED5 :bit2; + MVP_DISABLE_MSB_EXPAND :bit1; + RESERVED6 :bit3; + MVP_30BPP_EN :bit1; + RESERVED7 :bit1; + MVP_TERMINATION_CNTL_A :bit1; + MVP_TERMINATION_CNTL_B :bit1; + end; + + TMVP_CONTROL2=bitpacked record + MVP_MUX_DE_DVOCNTL0_SEL:bit1; + RESERVED0 :bit3; + MVP_MUX_DE_DVOCNTL2_SEL:bit1; + RESERVED1 :bit3; + MVP_MUXA_CLK_SEL :bit1; + RESERVED2 :bit3; + MVP_MUXB_CLK_SEL :bit1; + RESERVED3 :bit3; + MVP_DVOCNTL_MUX :bit1; + RESERVED4 :bit3; + MVP_FLOW_CONTROL_OUT_EN:bit1; + RESERVED5 :bit3; + MVP_SWAP_LOCK_OUT_EN :bit1; + RESERVED6 :bit3; + MVP_SWAP_AB_IN_DC_DDR :bit1; + RESERVED7 :bit3; + end; + + TMVP_CONTROL3=bitpacked record + MVP_RESET_IN_BETWEEN_FRAMES :bit1; + RESERVED0 :bit3; + MVP_DDR_SC_AB_SEL :bit1; + RESERVED1 :bit3; + MVP_DDR_SC_B_START_MODE :bit1; + RESERVED2 :bit3; + MVP_FLOW_CONTROL_OUT_FORCE_ONE :bit1; + RESERVED3 :bit3; + MVP_FLOW_CONTROL_OUT_FORCE_ZERO:bit1; + RESERVED4 :bit3; + MVP_FLOW_CONTROL_CASCADE_EN :bit1; + RESERVED5 :bit3; + MVP_SWAP_48BIT_EN :bit1; + RESERVED6 :bit3; + MVP_FLOW_CONTROL_IN_CAP :bit1; + RESERVED7 :bit3; + end; + + TMVP_CRC_CNTL=bitpacked record + MVP_CRC_BLUE_MASK :bit8; + MVP_CRC_GREEN_MASK :bit8; + MVP_CRC_RED_MASK :bit8; + RESERVED0 :bit4; + MVP_CRC_EN :bit1; + MVP_CRC_CONT_EN :bit1; + MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL:bit1; + RESERVED1 :bit1; + end; + + TMVP_DEBUG_05=bitpacked record + RESERVED0 :bit1; + IDE0_MVP_GPU_CHAIN_LOCATION:bit2; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit3; + RESERVED20 :bit2; + RESERVED21 :bit1; + RESERVED22 :bit1; + RESERVED23 :bit1; + RESERVED24 :bit1; + RESERVED25 :bit1; + RESERVED26 :bit1; + end; + + TMVP_DEBUG_09=bitpacked record + RESERVED0 :bit1; + IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION:bit2; + RESERVED1 :bit2; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit11; + end; + + TMVP_DEBUG_12=bitpacked record + IDEC_MVP_DATA_A_H:bit1; + IDEC_MVP_DATA_A :bit24; + RESERVED0 :bit7; + end; + + TMVP_DEBUG_13=bitpacked record + IDED_MVP_DATA_B_H :bit1; + IDED_MVP_DATA_B :bit24; + IDED_START_READ_B :bit1; + IDED_READ_FIFO_ENTRY_DE_B:bit1; + IDED_WRITE_ADD_B :bit3; + RESERVED0 :bit2; + end; + + TMVP_DEBUG_14=bitpacked record + IDEE_READ_ADD :bit3; + IDEE_WRITE_ADD_A :bit3; + IDEE_WRITE_ADD_B :bit3; + IDEE_START_READ :bit1; + IDEE_START_READ_B :bit1; + IDEE_START_INCR_WR_A :bit1; + IDEE_START_INCR_WR_B :bit1; + IDEE_WRITE2FIFO :bit1; + IDEE_READ_FIFO_ENTRY_DE :bit1; + IDEE_READ_FIFO_ENTRY_DE_B :bit1; + IDEE_READ_FIFO_DE :bit1; + IDEE_READ_FIFO_DE_B :bit1; + IDEE_READ_FIFO_ENABLE :bit1; + IDEE_CRTC1_CNTL_CAPTURE_START_A:bit1; + IDEE_CRC_PHASE :bit1; + RESERVED0 :bit11; + end; + + TMVP_DEBUG_15=bitpacked record + IDEF_MVP_ASYNC_FIFO_WEN :bit1; + RESERVED0 :bit3; + IDEF_MVP_ASYNC_FIFO_WDATA:bit28; + end; + + TMVP_DEBUG_16=bitpacked record + IDCC_MVP_ASYNC_FIFO_READ :bit1; + IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL :bit1; + IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL:bit1; + IDCC_FLOW_CONTROL_OUT :bit1; + IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES :bit8; + IDCC_MVP_ASYNC_FIFO_OVERFLOW :bit1; + IDCC_MVP_ASYNC_FIFO_UNDERFLOW :bit1; + RESERVED0 :bit2; + IDCC_MVP_ASYNC_READ_ADDR :bit8; + IDCC_MVP_ASYNC_WRITE_ADDR :bit8; + end; + + TMVP_DEBUG_17=bitpacked record + IDCD_MVP_ASYNC_FIFO_READ :bit1; + IDCD_MVP_ASYNC_FIFO_PHASE :bit1; + IDCD_MVP_ASYNC_FIFO_READ_DATA:bit30; + end; + + TOVL_CONTROL1=bitpacked record + OVL_DEPTH :bit2; + OVL_NUM_BANKS :bit2; + OVL_Z :bit2; + OVL_BANK_WIDTH :bit2; + OVL_FORMAT :bit3; + OVL_BANK_HEIGHT :bit2; + OVL_TILE_SPLIT :bit3; + OVL_ADDRESS_TRANSLATION_ENABLE:bit1; + OVL_PRIVILEGED_ACCESS_ENABLE :bit1; + OVL_MACRO_TILE_ASPECT :bit2; + OVL_ARRAY_MODE :bit4; + OVL_COLOR_EXPANSION_MODE :bit1; + OVL_PIPE_CONFIG :bit5; + OVL_MICRO_TILE_MODE :bit2; + end; + + TOVL_CONTROL2=bitpacked record + OVL_HALF_RESOLUTION_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TPB0_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + HW_16_DEBUG:bit1; + HW_17_DEBUG:bit1; + HW_18_DEBUG:bit1; + HW_19_DEBUG:bit1; + HW_20_DEBUG:bit1; + HW_21_DEBUG:bit1; + HW_22_DEBUG:bit1; + HW_23_DEBUG:bit1; + HW_24_DEBUG:bit1; + HW_25_DEBUG:bit1; + HW_26_DEBUG:bit1; + HW_27_DEBUG:bit1; + HW_28_DEBUG:bit1; + HW_29_DEBUG:bit1; + HW_30_DEBUG:bit1; + HW_31_DEBUG:bit1; + end; + + TPB0_PIF_CTRL=bitpacked record + PIF_PLL_PWRDN_EN :bit1; + DTM_FORCE_FREQDIV_X1 :bit1; + PIF_PLL_HNDSHK_EARLY_ABORT:bit1; + PIF_PLL_PWRDN_EARLY_EXIT :bit1; + PHY_RST_PWROK_VDD :bit1; + RESERVED0 :bit1; + PIF_PLL_STATUS :bit2; + PIF_PLL_DEGRADE_OFF_VOTE :bit1; + PIF_PLL_UNUSED_OFF_VOTE :bit1; + PIF_PLL_DEGRADE_S2_VOTE :bit1; + RESERVED1 :bit21; + end; + + TPB1_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + HW_16_DEBUG:bit1; + HW_17_DEBUG:bit1; + HW_18_DEBUG:bit1; + HW_19_DEBUG:bit1; + HW_20_DEBUG:bit1; + HW_21_DEBUG:bit1; + HW_22_DEBUG:bit1; + HW_23_DEBUG:bit1; + HW_24_DEBUG:bit1; + HW_25_DEBUG:bit1; + HW_26_DEBUG:bit1; + HW_27_DEBUG:bit1; + HW_28_DEBUG:bit1; + HW_29_DEBUG:bit1; + HW_30_DEBUG:bit1; + HW_31_DEBUG:bit1; + end; + + TPB1_PIF_CTRL=bitpacked record + PIF_PLL_PWRDN_EN :bit1; + DTM_FORCE_FREQDIV_X1 :bit1; + PIF_PLL_HNDSHK_EARLY_ABORT:bit1; + PIF_PLL_PWRDN_EARLY_EXIT :bit1; + PHY_RST_PWROK_VDD :bit1; + RESERVED0 :bit1; + PIF_PLL_STATUS :bit2; + PIF_PLL_DEGRADE_OFF_VOTE :bit1; + PIF_PLL_UNUSED_OFF_VOTE :bit1; + PIF_PLL_DEGRADE_S2_VOTE :bit1; + RESERVED1 :bit21; + end; + + TPCIE_ACS_CAP=bitpacked record + SOURCE_VALIDATION :bit1; + TRANSLATION_BLOCKING :bit1; + P2P_REQUEST_REDIRECT :bit1; + P2P_COMPLETION_REDIRECT :bit1; + UPSTREAM_FORWARDING :bit1; + P2P_EGRESS_CONTROL :bit1; + DIRECT_TRANSLATED_P2P :bit1; + RESERVED0 :bit1; + EGRESS_CONTROL_VECTOR_SIZE:bit8; + RESERVED1 :bit16; + end; + + TPCIE_ARI_CAP=bitpacked record + ARI_MFVC_FUNC_GROUPS_CAP:bit1; + ARI_ACS_FUNC_GROUPS_CAP :bit1; + RESERVED0 :bit6; + ARI_NEXT_FUNC_NUM :bit8; + RESERVED1 :bit16; + end; + + TPCIE_ATS_CAP=bitpacked record + INVALIDATE_Q_DEPTH :bit5; + PAGE_ALIGNED_REQUEST :bit1; + GLOBAL_INVALIDATE_SUPPORTED:bit1; + RESERVED0 :bit25; + end; + + TPCIE_CI_CNTL=bitpacked record + RESERVED0 :bit2; + CI_SLAVE_SPLIT_MODE :bit1; + CI_SLAVE_GEN_USR_DIS :bit1; + CI_MST_CMPL_DUMMY_DATA :bit1; + RESERVED1 :bit1; + CI_SLV_RC_RD_REQ_SIZE :bit2; + CI_SLV_ORDERING_DIS :bit1; + CI_RC_ORDERING_DIS :bit1; + CI_SLV_CPL_ALLOC_DIS :bit1; + CI_SLV_CPL_ALLOC_MODE :bit1; + CI_SLV_CPL_ALLOC_SOR :bit1; + CI_MST_IGNORE_PAGE_ALIGNED_REQUEST:bit1; + RESERVED2 :bit18; + end; + + TPCIE_DPA_CAP=bitpacked record + SUBSTATE_MAX :bit5; + RESERVED0 :bit3; + TRANS_LAT_UNIT :bit2; + RESERVED1 :bit2; + PWR_ALLOC_SCALE:bit2; + RESERVED2 :bit2; + TRANS_LAT_VAL_0:bit8; + TRANS_LAT_VAL_1:bit8; + end; + + TPCIE_INDEX_2=bit32; + + TPCIE_LC_CNTL=bitpacked record + RESERVED0 :bit1; + LC_DONT_ENTER_L23_IN_D0 :bit1; + LC_RESET_L_IDLE_COUNT_EN :bit1; + LC_RESET_LINK :bit1; + LC_16X_CLEAR_TX_PIPE :bit4; + LC_L0S_INACTIVITY :bit4; + LC_L1_INACTIVITY :bit4; + LC_PMI_TO_L1_DIS :bit1; + LC_INC_N_FTS_EN :bit1; + LC_LOOK_FOR_IDLE_IN_L1L23 :bit2; + LC_FACTOR_IN_EXT_SYNC :bit1; + LC_WAIT_FOR_PM_ACK_DIS :bit1; + LC_WAKE_FROM_L23 :bit1; + LC_L1_IMMEDIATE_ACK :bit1; + LC_ASPM_TO_L1_DIS :bit1; + LC_DELAY_COUNT :bit2; + LC_DELAY_L0S_EXIT :bit1; + LC_DELAY_L1_EXIT :bit1; + LC_EXTEND_WAIT_FOR_EL_IDLE:bit1; + LC_ESCAPE_L1L23_EN :bit1; + LC_GATE_RCVR_IDLE :bit1; + end; + + TPCIE_LTR_CAP=bitpacked record + LTR_MAX_S_LATENCY_VALUE :bit10; + LTR_MAX_S_LATENCY_SCALE :bit3; + RESERVED0 :bit3; + LTR_MAX_NS_LATENCY_VALUE:bit10; + LTR_MAX_NS_LATENCY_SCALE:bit3; + RESERVED1 :bit3; + end; + + TPCIE_MC_CNTL=bitpacked record + MC_NUM_GROUP:bit6; + RESERVED0 :bit9; + MC_ENABLE :bit1; + RESERVED1 :bit16; + end; + + TPCIE_MC_RCV0=bit32; + + TPCIE_MC_RCV1=bit32; + + TPCIE_RX_CNTL=bitpacked record + RX_IGNORE_IO_ERR :bit1; + RX_IGNORE_BE_ERR :bit1; + RX_IGNORE_MSG_ERR :bit1; + RX_IGNORE_CRC_ERR :bit1; + RX_IGNORE_CFG_ERR :bit1; + RX_IGNORE_CPL_ERR :bit1; + RX_IGNORE_EP_ERR :bit1; + RX_IGNORE_LEN_MISMATCH_ERR:bit1; + RX_IGNORE_MAX_PAYLOAD_ERR :bit1; + RX_IGNORE_TC_ERR :bit1; + RX_IGNORE_CFG_UR :bit1; + RX_IGNORE_IO_UR :bit1; + RX_IGNORE_AT_ERR :bit1; + RX_NAK_IF_FIFO_FULL :bit1; + RX_GEN_ONE_NAK :bit1; + RX_FC_INIT_FROM_REG :bit1; + RX_RCB_CPL_TIMEOUT :bit3; + RX_RCB_CPL_TIMEOUT_MODE :bit1; + RX_PCIE_CPL_TIMEOUT_DIS :bit1; + RX_IGNORE_SHORTPREFIX_ERR :bit1; + RX_IGNORE_MAXPREFIX_ERR :bit1; + RX_IGNORE_CPLPREFIX_ERR :bit1; + RX_IGNORE_INVALIDPASID_ERR:bit1; + RX_IGNORE_NOT_PASID_UR :bit1; + RX_TPH_DIS :bit1; + RX_RCB_FLR_TIMEOUT_DIS :bit1; + RESERVED0 :bit4; + end; + + TPCIE_SCRATCH=bit32; + + TPCIE_TX_CNTL=bitpacked record + RESERVED0 :bit10; + TX_SNR_OVERRIDE :bit2; + TX_RO_OVERRIDE :bit2; + TX_PACK_PACKET_DIS :bit1; + TX_FLUSH_TLP_DIS :bit1; + RESERVED1 :bit4; + TX_CPL_PASS_P :bit1; + TX_NP_PASS_P :bit1; + TX_CLEAR_EXTRA_PM_REQS :bit1; + TX_FC_UPDATE_TIMEOUT_DIS:bit1; + TX_F0_TPH_DIS :bit1; + TX_F1_TPH_DIS :bit1; + TX_F2_TPH_DIS :bit1; + RESERVED2 :bit5; + end; + + TPERFMON_CNTL=bitpacked record + PERFMON_STATE :bit2; + PERFMON_RUN_ENABLE_SEL :bit6; + PERFMON_RPT_COUNT :bit20; + PERFMON_CNTOFF_AND_OR :bit1; + PERFMON_CNTOFF_INT_EN :bit1; + PERFMON_CNTOFF_INT_STATUS:bit1; + PERFMON_CNTOFF_INT_ACK :bit1; + end; + + TPHY_AUX_CNTL=bitpacked record + AUXSLAVE_PAD_SLEWN :bit1; + AUXSLAVE_PAD_WAKE :bit1; + AUXSLAVE_PAD_RXSEL :bit1; + AUXSLAVE_PAD_MODE :bit1; + DDCSLAVE_DATA_PD_EN:bit1; + DDCSLAVE_DATA_EN :bit1; + DDCSLAVE_CLK_PD_EN :bit1; + DDCSLAVE_CLK_EN :bit1; + RESERVED0 :bit4; + AUX_PAD_SLEWN :bit1; + AUXSLAVE_CLK_PD_EN :bit1; + AUX_PAD_WAKE :bit1; + RESERVED1 :bit1; + AUX_PAD_RXSEL :bit1; + RESERVED2 :bit15; + end; + + TPLL_POST_DIV=bitpacked record + PLL_POST_DIV_PIXCLK :bit7; + PLL_POST_DIV1P5_DISPCLK :bit1; + PLL_POST_DIV_DVOCLK :bit7; + PLL_POST_DIV1P5_DPREFCLK:bit1; + PLL_POST_DIV_IDCLK :bit7; + RESERVED0 :bit9; + end; + + TPLL_XOR_LOCK=bitpacked record + PLL_XOR_LOCK :bit1; + PLL_XOR_LOCK_READBACK :bit1; + RESERVED0 :bit6; + PLL_SPARE :bit6; + RESERVED1 :bit2; + PLL_LOCK_COUNT_SEL :bit4; + PLL_LOCK_DETECTOR_RESOLUTION_FREF:bit3; + PLL_LOCK_DETECTOR_RESOLUTION_FFB :bit3; + PLL_LOCK_DETECTOR_OPAMP_BIAS :bit2; + PLL_FAST_LOCK_MODE_EN :bit1; + RESERVED2 :bit3; + end; + + TPMI_CAP_LIST=bitpacked record + CAP_ID :bit8; + NEXT_PTR :bit8; + RESERVED0:bit16; + end; + + TPWR_AVFS_SEL=bitpacked record + AvfsSel :bit28; + RESERVED0:bit4; + end; + + TPWR_CKS_CNTL=bitpacked record + CKS_BYPASS :bit1; + CKS_PCCEnable :bit1; + CKS_TEMP_COMP :bit1; + CKS_STRETCH_AMOUNT :bit4; + CKS_SKIP_PHASE_BYPASS :bit1; + CKS_SAMPLE_SIZE :bit4; + CKS_FSM_WAIT_CYCLES :bit4; + CKS_USE_FOR_LOW_FREQ :bit1; + CKS_NO_EXTRA_COARSE_STEP:bit1; + CKS_LDO_REFSEL :bit4; + DDT_DEBUS_SEL :bit1; + CKS_LDO_READY_COUNT_VAL :bit8; + RESERVED0 :bit1; + end; + + TRINGOSC_MASK=bitpacked record + MASK :bit16; + RESERVED0:bit16; + end; + + TRIRB_CONTROL=bitpacked record + RESPONSE_INTERRUPT_CONTROL :bit1; + RIRB_DMA_ENABLE :bit1; + RESPONSE_OVERRUN_INTERRUPT_CONTROL:bit1; + RESERVED0 :bit29; + end; + + TRLC_GPM_STAT=bitpacked record + RLC_BUSY :bit1; + GFX_POWER_STATUS :bit1; + GFX_CLOCK_STATUS :bit1; + GFX_LS_STATUS :bit1; + GFX_PIPELINE_POWER_STATUS :bit1; + CNTX_IDLE_BEING_PROCESSED :bit1; + CNTX_BUSY_BEING_PROCESSED :bit1; + GFX_IDLE_BEING_PROCESSED :bit1; + CMP_BUSY_BEING_PROCESSED :bit1; + SAVING_REGISTERS :bit1; + RESTORING_REGISTERS :bit1; + GFX3D_BLOCKS_CHANGING_POWER_STATE:bit1; + CMP_BLOCKS_CHANGING_POWER_STATE :bit1; + STATIC_CU_POWERING_UP :bit1; + STATIC_CU_POWERING_DOWN :bit1; + DYN_CU_POWERING_UP :bit1; + DYN_CU_POWERING_DOWN :bit1; + ABORTED_PD_SEQUENCE :bit1; + RESERVED :bit6; + PG_ERROR_STATUS :bit8; + end; + + TRLC_GPR_REG1=bit32; + + TRLC_GPR_REG2=bit32; + + TRLC_PG_DELAY=bitpacked record + POWER_UP_DELAY :bit8; + POWER_DOWN_DELAY :bit8; + CMD_PROPAGATE_DELAY:bit8; + MEM_SLEEP_DELAY :bit8; + end; + + TRLC_ROM_CNTL=bitpacked record + USE_ROM :bit1; + SLP_MODE_EN :bit1; + EFUSE_DISTRIB_EN:bit1; + HELLOWORLD_EN :bit1; + CU_HARVEST_EN :bit1; + RESERVED :bit27; + end; + + TRLC_SPM_VMID=bitpacked record + RLC_SPM_VMID:bit4; + RESERVED0 :bit28; + end; + + TRLC_SRM_CNTL=bitpacked record + SRM_ENABLE :bit1; + AUTO_INCR_ADDR:bit1; + RESERVED :bit30; + end; + + TRLC_SRM_STAT=bitpacked record + SRM_STATUS:bit1; + RESERVED :bit31; + end; + + TSCLK_MIN_DIV=bitpacked record + FRACV :bit12; + INTV :bit7; + RESERVED0:bit13; + end; + + TSCLV_CONTROL=bitpacked record + SCL_BOUNDARY_MODE :bit1; + RESERVED0 :bit3; + SCL_EARLY_EOL_MODE:bit1; + RESERVED1 :bit3; + SCL_TOTAL_PHASE :bit1; + RESERVED2 :bit23; + end; + + TSCRATCH_ADDR=bit32; + + TSCRATCH_REG0=bit32; + + TSCRATCH_REG1=bit32; + + TSCRATCH_REG2=bit32; + + TSCRATCH_REG3=bit32; + + TSCRATCH_REG4=bit32; + + TSCRATCH_REG5=bit32; + + TSCRATCH_REG6=bit32; + + TSCRATCH_REG7=bit32; + + TSCRATCH_UMSK=bitpacked record + OBSOLETE_UMSK:bit8; + RESERVED0 :bit8; + OBSOLETE_SWAP:bit2; + RESERVED1 :bit14; + end; + + TSDMA0_FREEZE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + FREEZE :bit1; + FROZEN :bit1; + F32_FREEZE:bit1; + RESERVED2 :bit25; + end; + + TSDMA1_CONFIG=bitpacked record + RESERVED0 :bit8; + SDMA_RDREQ_URG:bit4; + RESERVED1 :bit4; + SDMA_REQ_TRAN :bit1; + RESERVED2 :bit15; + end; + + TSDMA1_FREEZE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + FREEZE :bit1; + FROZEN :bit1; + F32_FREEZE:bit1; + RESERVED2 :bit25; + end; + + TSH_MEM_BASES=bitpacked record + PRIVATE_BASE:bit16; + SHARED_BASE :bit16; + end; + + TSMC_IND_DATA=bit32; + + TSMC_SCRATCH9=bit32; + TSPI_DSM_CNTL=bitpacked record Sel_DSM_SPI_Irritator_data0:bit1; Sel_DSM_SPI_Irritator_data1:bit1; @@ -942,6 +7247,107 @@ type RESERVED0 :bit31; end; + TSQC_DSM_CNTL=bitpacked record + SEL_DATA_ICACHE_BANKA :bit2; + EN_SINGLE_WR_ICACHE_BANKA :bit1; + SEL_DATA_ICACHE_BANKB :bit2; + EN_SINGLE_WR_ICACHE_BANKB :bit1; + SEL_DATA_ICACHE_BANKC :bit2; + EN_SINGLE_WR_ICACHE_BANKC :bit1; + SEL_DATA_ICACHE_BANKD :bit2; + EN_SINGLE_WR_ICACHE_BANKD :bit1; + SEL_DATA_ICACHE_GATCL1 :bit2; + EN_SINGLE_WR_ICACHE_GATCL1:bit1; + SEL_DATA_DCACHE_BANKA :bit2; + EN_SINGLE_WR_DCACHE_BANKA :bit1; + SEL_DATA_DCACHE_BANKB :bit2; + EN_SINGLE_WR_DCACHE_BANKB :bit1; + SEL_DATA_DCACHE_BANKC :bit2; + EN_SINGLE_WR_DCACHE_BANKC :bit1; + SEL_DATA_DCACHE_BANKD :bit2; + EN_SINGLE_WR_DCACHE_BANKD :bit1; + SEL_DATA_DCACHE_GATCL1 :bit2; + EN_SINGLE_WR_DCACHE_GATCL1:bit1; + RESERVED0 :bit2; + end; + + TSQ_IND_INDEX=bitpacked record + WAVE_ID :bit4; + SIMD_ID :bit2; + THREAD_ID :bit6; + AUTO_INCR :bit1; + FORCE_READ :bit1; + READ_TIMEOUT:bit1; + UNINDEXED :bit1; + INDEX :bit16; + end; + + TSQ_WAVE_MODE=bitpacked record + FP_ROUND :bit4; + FP_DENORM :bit4; + DX10_CLAMP :bit1; + IEEE :bit1; + LOD_CLAMPED:bit1; + DEBUG_EN :bit1; + EXCP_EN :bit9; + RESERVED0 :bit6; + GPR_IDX_EN :bit1; + VSKIP :bit1; + CSP :bit3; + end; + + TSRBM_INT_ACK=bitpacked record + RDERR_INT_ACK:bit1; + RAERR_INT_ACK:bit1; + RESERVED0 :bit30; + end; + + TSRBM_STATUS2=bitpacked record + SDMA_RQ_PENDING :bit1; + TST_RQ_PENDING :bit1; + SDMA1_RQ_PENDING :bit1; + VCE0_RQ_PENDING :bit1; + VP8_BUSY :bit1; + SDMA_BUSY :bit1; + SDMA1_BUSY :bit1; + VCE0_BUSY :bit1; + XDMA_BUSY :bit1; + CHUB_BUSY :bit1; + SDMA2_BUSY :bit1; + SDMA3_BUSY :bit1; + SAMSCP_BUSY :bit1; + ISP_BUSY :bit1; + VCE1_BUSY :bit1; + ODE_BUSY :bit1; + SDMA2_RQ_PENDING :bit1; + SDMA3_RQ_PENDING :bit1; + SAMSCP_RQ_PENDING:bit1; + ISP_RQ_PENDING :bit1; + VCE1_RQ_PENDING :bit1; + RESERVED0 :bit11; + end; + + TSRBM_STATUS3=bitpacked record + MCC0_BUSY:bit1; + MCC1_BUSY:bit1; + MCC2_BUSY:bit1; + MCC3_BUSY:bit1; + MCC4_BUSY:bit1; + MCC5_BUSY:bit1; + MCC6_BUSY:bit1; + MCC7_BUSY:bit1; + MCD0_BUSY:bit1; + MCD1_BUSY:bit1; + MCD2_BUSY:bit1; + MCD3_BUSY:bit1; + MCD4_BUSY:bit1; + MCD5_BUSY:bit1; + MCD6_BUSY:bit1; + MCD7_BUSY:bit1; + RESERVED0:bit1; + RESERVED1:bit15; + end; + TTA_CGTT_CTRL=bitpacked record ON_DELAY :bit4; OFF_HYSTERESIS:bit8; @@ -984,6 +7390,182 @@ type SOFT_OVERRIDE0:bit1; end; + TTHM_CLK_CNTL=bitpacked record + CMON_CLK_SEL :bit8; + TMON_CLK_SEL :bit8; + CTF_CLK_SHUTOFF_EN:bit1; + RESERVED0 :bit15; + end; + + TUNIPHY_DEBUG=bitpacked record + RESERVED0:bit12; + DEBUG0 :bit10; + DEBUG1 :bit3; + DBG_SEL :bit2; + RESERVED1:bit5; + end; + + TUNP_CRC_LAST=bit32; + + TUNP_CRC_MASK=bit32; + + TURGENCY_STAT=bitpacked record + RESERVED0:bit1; + RESERVED1:bit7; + RESERVED2:bit12; + RESERVED3:bit12; + end; + + TUVD_CGC_CTRL=bitpacked record + DYN_CLOCK_MODE :bit1; + JPEG2_MODE :bit1; + CLK_GATE_DLY_TIMER:bit4; + CLK_OFF_DELAY :bit5; + UDEC_RE_MODE :bit1; + UDEC_CM_MODE :bit1; + UDEC_IT_MODE :bit1; + UDEC_DB_MODE :bit1; + UDEC_MP_MODE :bit1; + SYS_MODE :bit1; + UDEC_MODE :bit1; + MPEG2_MODE :bit1; + REGS_MODE :bit1; + RBC_MODE :bit1; + LMI_MC_MODE :bit1; + LMI_UMC_MODE :bit1; + IDCT_MODE :bit1; + MPRD_MODE :bit1; + MPC_MODE :bit1; + LBSI_MODE :bit1; + LRBBM_MODE :bit1; + WCB_MODE :bit1; + VCPU_MODE :bit1; + SCPU_MODE :bit1; + JPEG_MODE :bit1; + end; + + TUVD_CGC_GATE=bitpacked record + SYS :bit1; + UDEC :bit1; + MPEG2 :bit1; + REGS :bit1; + RBC :bit1; + LMI_MC :bit1; + LMI_UMC :bit1; + IDCT :bit1; + MPRD :bit1; + MPC :bit1; + LBSI :bit1; + LRBBM :bit1; + UDEC_RE :bit1; + UDEC_CM :bit1; + UDEC_IT :bit1; + UDEC_DB :bit1; + UDEC_MP :bit1; + WCB :bit1; + VCPU :bit1; + SCPU :bit1; + JPEG :bit1; + JPEG2 :bit1; + RESERVED0:bit10; + end; + + TUVD_CTX_DATA=bit32; + + TUVD_LMI_CTRL=bitpacked record + WRITE_CLEAN_TIMER :bit8; + WRITE_CLEAN_TIMER_EN :bit1; + REQ_MODE :bit1; + RESERVED0 :bit1; + ASSERT_MC_URGENT :bit1; + MASK_MC_URGENT :bit1; + DATA_COHERENCY_EN :bit1; + CRC_RESET :bit1; + CRC_SEL :bit5; + DISABLE_ON_FWV_FAIL :bit1; + VCPU_DATA_COHERENCY_EN :bit1; + CM_DATA_COHERENCY_EN :bit1; + DB_DB_DATA_COHERENCY_EN :bit1; + DB_IT_DATA_COHERENCY_EN :bit1; + IT_IT_DATA_COHERENCY_EN :bit1; + MIF_MIF_DATA_COHERENCY_EN:bit1; + RFU :bit5; + end; + + TUVD_MPC_CNTL=bitpacked record + RESERVED0 :bit3; + REPLACEMENT_MODE:bit3; + PERF_RST :bit1; + RESERVED1 :bit1; + DBG_MUX :bit4; + RESERVED2 :bit4; + AVE_WEIGHT :bit2; + URGENT_EN :bit1; + RESERVED3 :bit13; + end; + + TUVD_SEMA_CMD=bitpacked record + REQ_CMD :bit4; + WR_PHASE :bit2; + MODE :bit1; + VMID_EN :bit1; + VMID :bit4; + RESERVED0:bit20; + end; + + TVCE_LMI_CTRL=bitpacked record + RESERVED0 :bit11; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit5; + RESERVED6 :bit1; + VCPU_DATA_COHERENCY_EN:bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit7; + end; + + TVCE_RB_RPTR2=bitpacked record + RESERVED0:bit4; + RB_RPTR :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_RPTR3=bitpacked record + RESERVED0:bit4; + RB_RPTR :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_SIZE2=bitpacked record + RESERVED0:bit4; + RB_SIZE :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_SIZE3=bitpacked record + RESERVED0:bit4; + RB_SIZE :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_WPTR2=bitpacked record + RESERVED0:bit4; + RB_WPTR :bit19; + RESERVED1:bit9; + end; + + TVCE_RB_WPTR3=bitpacked record + RESERVED0:bit4; + RB_WPTR :bit19; + RESERVED1:bit9; + end; + + TVGA_HW_DEBUG=bit32; + TVGT_DMA_BASE=bit32; TVGT_DMA_SIZE=bit32; @@ -1007,6 +7589,183 @@ type RESERVED1 :bit11; end; + TVLINE_STATUS=bitpacked record + RESERVED0:bit1; + RESERVED1:bit3; + RESERVED2:bit1; + RESERVED3:bit7; + RESERVED4:bit1; + RESERVED5:bit3; + RESERVED6:bit1; + RESERVED7:bit1; + RESERVED8:bit14; + end; + + TVM_L2_STATUS=bitpacked record + L2_BUSY :bit1; + CONTEXT_DOMAIN_BUSY:bit16; + RESERVED0 :bit15; + end; + + TWB_EC_CONFIG=bitpacked record + DISPCLK_R_WB_GATE_DIS :bit1; + DISPCLK_G_WB_GATE_DIS :bit1; + DISPCLK_G_WBSCL_GATE_DIS :bit1; + DISPCLK_R_WB_RAMP_DIS :bit1; + DISPCLK_G_WB_RAMP_DIS :bit1; + DISPCLK_G_WBSCL_RAMP_DIS :bit1; + WB_LB_LS_DIS :bit1; + WB_LB_SD_DIS :bit1; + WB_LUT_LS_DIS :bit1; + WBSCL_LB_MEM_PWR_MODE_SEL:bit2; + RESERVED0 :bit1; + WB_TEST_CLK_SEL :bit4; + WBSCL_LB_MEM_PWR_DIS :bit1; + WBSCL_LB_MEM_PWR_FORCE :bit2; + WBSCL_LB_MEM_PWR_STATE :bit2; + RESERVED1 :bit2; + WB_RAM_PW_SAVE_MODE :bit1; + RESERVED2 :bit4; + LB_MEM_PWR_STATE :bit2; + LUT_MEM_PWR_STATE :bit2; + end; + + TALPHA_CONTROL=bitpacked record + ALPHA_ROUND_TRUNC_MODE:bit1; + CURSOR_ALPHA_BLND_ENA :bit1; + RESERVED0 :bit30; + end; + + TATC_ATS_DEBUG=bitpacked record + INVALIDATE_ALL :bit1; + IDENT_RETURN :bit1; + ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS :bit1; + RESERVED0 :bit2; + PAGE_REQUESTS_USE_RELAXED_ORDERING :bit1; + PRIV_BIT :bit1; + EXE_BIT :bit1; + PAGE_REQUEST_PERMS :bit1; + UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE :bit1; + NUM_REQUESTS_AT_ERR :bit4; + DISALLOW_ERR_TO_DONE :bit1; + IGNORE_FED :bit1; + INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED:bit1; + DEBUG_BUS_SELECT :bit1; + DISABLE_INVALIDATE_PER_DOMAIN :bit1; + DISABLE_VMID0_PASID_MAPPING :bit1; + DISABLE_INVALIDATION_ON_WORLD_SWITCH :bit1; + ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT :bit1; + RESERVED1 :bit10; + end; + + TATC_L2_DEBUG2=bitpacked record + EFFECTIVE_CACHE_SIZE :bit5; + EFFECTIVE_WORK_QUEUE_SIZE :bit3; + FORCE_CACHE_MISS :bit1; + INVALIDATE_ALL :bit1; + DISABLE_2M_CACHE :bit1; + DISABLE_CACHING_SPECULATIVE_RETURNS :bit1; + RESERVED0 :bit2; + DISABLE_CACHING_FAULT_RETURNS :bit1; + DEBUG_BUS_SELECT :bit2; + DEBUG_ECO :bit2; + EFFECTIVE_2M_CACHE_SIZE :bit4; + CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD:bit8; + CLEAR_PARITY_ERROR_INFO :bit1; + end; + + TATC_L2_STATUS=bitpacked record + BUSY :bit1; + PARITY_ERROR_INFO:bit29; + RESERVED0 :bit2; + end; + + TAUX_LS_STATUS=bitpacked record + AUX_LS_DONE :bit1; + AUX_LS_REQ :bit1; + RESERVED0 :bit2; + AUX_LS_RX_TIMEOUT_STATE :bit3; + AUX_LS_RX_TIMEOUT :bit1; + AUX_LS_RX_OVERFLOW :bit1; + AUX_LS_HPD_DISCON :bit1; + AUX_LS_RX_PARTIAL_BYTE :bit1; + AUX_LS_NON_AUX_MODE :bit1; + AUX_LS_RX_MIN_COUNT_VIOL:bit1; + RESERVED1 :bit1; + AUX_LS_RX_INVALID_STOP :bit1; + RESERVED2 :bit2; + AUX_LS_RX_SYNC_INVALID_L:bit1; + AUX_LS_RX_SYNC_INVALID_H:bit1; + AUX_LS_RX_INVALID_START :bit1; + AUX_LS_RX_RECV_NO_DET :bit1; + RESERVED3 :bit1; + AUX_LS_RX_RECV_INVALID_H:bit1; + AUX_LS_RX_RECV_INVALID_L:bit1; + AUX_LS_REPLY_BYTE_COUNT :bit5; + AUX_LS_CP_IRQ :bit1; + AUX_LS_UPDATED :bit1; + AUX_LS_UPDATED_ACK :bit1; + end; + + TAUX_SW_STATUS=bitpacked record + AUX_SW_DONE :bit1; + AUX_SW_REQ :bit1; + RESERVED0 :bit2; + AUX_SW_RX_TIMEOUT_STATE :bit3; + AUX_SW_RX_TIMEOUT :bit1; + AUX_SW_RX_OVERFLOW :bit1; + AUX_SW_HPD_DISCON :bit1; + AUX_SW_RX_PARTIAL_BYTE :bit1; + AUX_SW_NON_AUX_MODE :bit1; + AUX_SW_RX_MIN_COUNT_VIOL:bit1; + RESERVED1 :bit1; + AUX_SW_RX_INVALID_STOP :bit1; + RESERVED2 :bit2; + AUX_SW_RX_SYNC_INVALID_L:bit1; + AUX_SW_RX_SYNC_INVALID_H:bit1; + AUX_SW_RX_INVALID_START :bit1; + AUX_SW_RX_RECV_NO_DET :bit1; + RESERVED3 :bit1; + AUX_SW_RX_RECV_INVALID_H:bit1; + AUX_SW_RX_RECV_INVALID_L:bit1; + AUX_SW_REPLY_BYTE_COUNT :bit5; + RESERVED4 :bit1; + AUX_ARB_STATUS :bit2; + end; + + TBIF_DEBUG_MUX=bitpacked record + DEBUG_MUX_BLK1:bit6; + RESERVED0 :bit2; + DEBUG_MUX_BLK2:bit6; + RESERVED1 :bit18; + end; + + TBIF_DEBUG_OUT=bitpacked record + DEBUG_OUTPUT:bit17; + RESERVED0 :bit15; + end; + + TBIF_SMU_INDEX=bitpacked record + RESERVED0 :bit2; + BIF_SMU_INDEX:bit17; + RESERVED1 :bit13; + end; + + TBLND_CONTROL2=bitpacked record + PTI_ENABLE :bit1; + RESERVED0 :bit3; + PTI_NEW_PIXEL_GAP :bit2; + BLND_NEW_PIXEL_MODE :bit1; + BLND_SUPERAA_DEGAMMA_EN:bit1; + BLND_SUPERAA_REGAMMA_EN:bit1; + RESERVED1 :bit23; + end; + + TBX_RESET_CNTL=bitpacked record + LINK_TRAIN_EN:bit1; + RESERVED0 :bit31; + end; + TCB_BLEND_BLUE=bit32; TCB_DCC_CONFIG=bitpacked record @@ -1045,6 +7804,16 @@ type DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE :bit1; end; + TCNV_TEST_CNTL=bitpacked record + RESERVED0 :bit4; + CNV_TEST_CRC_EN :bit1; + RESERVED1 :bit3; + CNV_TEST_CRC_CONT_EN:bit1; + RESERVED2 :bit7; + CNV_TEST_CRC_DE_ONLY:bit1; + RESERVED3 :bit15; + end; + TCOMPUTE_DIM_X=bit32; TCOMPUTE_DIM_Y=bit32; @@ -1083,7 +7852,7 @@ type CB7_DEST_BASE_ENA :bit1; DB_DEST_BASE_ENA :bit1; TCL1_VOL_ACTION_ENA :bit1; - TC_VOL_ACTION_ENA__CI :bit1; + TC_VOL_ACTION_ENA :bit1; RESERVED1 :bit1; TC_WB_ACTION_ENA :bit1; DEST_BASE_2_ENA :bit1; @@ -1103,60 +7872,52 @@ type TCP_COHER_SIZE=bit32; - TCP_CONFIG__SI=bitpacked record - RESERVED0 :bit8; - CP_RDREQ_URG:bit4; - RESERVED1 :bit4; - CP_REQ_TRAN :bit1; - RESERVED2 :bit15; - end; - TCP_CPC_STATUS=bitpacked record - MEC1_BUSY :bit1; - MEC2_BUSY :bit1; - DC0_BUSY :bit1; - DC1_BUSY :bit1; - RCIU1_BUSY :bit1; - RCIU2_BUSY :bit1; - ROQ1_BUSY :bit1; - ROQ2_BUSY :bit1; - MIU_RDREQ_BUSY__SI__CI:bit1; - MIU_WRREQ_BUSY__SI__CI:bit1; - TCIU_BUSY :bit1; - SCRATCH_RAM_BUSY :bit1; - QU_BUSY :bit1; - ATCL2IU_BUSY :bit1; - RESERVED0 :bit15; - CPG_CPC_BUSY :bit1; - CPF_CPC_BUSY :bit1; - CPC_BUSY :bit1; + MEC1_BUSY :bit1; + MEC2_BUSY :bit1; + DC0_BUSY :bit1; + DC1_BUSY :bit1; + RCIU1_BUSY :bit1; + RCIU2_BUSY :bit1; + ROQ1_BUSY :bit1; + ROQ2_BUSY :bit1; + MIU_RDREQ_BUSY :bit1; + MIU_WRREQ_BUSY :bit1; + TCIU_BUSY :bit1; + SCRATCH_RAM_BUSY:bit1; + QU_BUSY :bit1; + ATCL2IU_BUSY :bit1; + RESERVED0 :bit15; + CPG_CPC_BUSY :bit1; + CPF_CPC_BUSY :bit1; + CPC_BUSY :bit1; end; TCP_CPF_STATUS=bitpacked record - POST_WPTR_GFX_BUSY :bit1; - CSF_BUSY :bit1; - MIU_RDREQ_BUSY__SI__CI:bit1; - MIU_WRREQ_BUSY__SI__CI:bit1; - ROQ_ALIGN_BUSY :bit1; - ROQ_RING_BUSY :bit1; - ROQ_INDIRECT1_BUSY :bit1; - ROQ_INDIRECT2_BUSY :bit1; - ROQ_STATE_BUSY :bit1; - ROQ_CE_RING_BUSY :bit1; - ROQ_CE_INDIRECT1_BUSY :bit1; - ROQ_CE_INDIRECT2_BUSY :bit1; - SEMAPHORE_BUSY :bit1; - INTERRUPT_BUSY :bit1; - TCIU_BUSY :bit1; - HQD_BUSY :bit1; - PRT_BUSY :bit1; - ATCL2IU_BUSY :bit1; - RESERVED0 :bit8; - CPF_GFX_BUSY :bit1; - CPF_CMP_BUSY :bit1; - GRBM_CPF_STAT_BUSY :bit2; - CPC_CPF_BUSY :bit1; - CPF_BUSY :bit1; + POST_WPTR_GFX_BUSY :bit1; + CSF_BUSY :bit1; + MIU_RDREQ_BUSY :bit1; + MIU_WRREQ_BUSY :bit1; + ROQ_ALIGN_BUSY :bit1; + ROQ_RING_BUSY :bit1; + ROQ_INDIRECT1_BUSY :bit1; + ROQ_INDIRECT2_BUSY :bit1; + ROQ_STATE_BUSY :bit1; + ROQ_CE_RING_BUSY :bit1; + ROQ_CE_INDIRECT1_BUSY:bit1; + ROQ_CE_INDIRECT2_BUSY:bit1; + SEMAPHORE_BUSY :bit1; + INTERRUPT_BUSY :bit1; + TCIU_BUSY :bit1; + HQD_BUSY :bit1; + PRT_BUSY :bit1; + ATCL2IU_BUSY :bit1; + RESERVED0 :bit8; + CPF_GFX_BUSY :bit1; + CPF_CMP_BUSY :bit1; + GRBM_CPF_STAT_BUSY :bit2; + CPC_CPF_BUSY :bit1; + CPF_BUSY :bit1; end; TCP_DFY_DATA_0=bit32; @@ -1223,6 +7984,11 @@ type GENERIC0_INT_STAT :bit1; end; + TCP_RB_RPTR_WR=bitpacked record + RB_RPTR_WR:bit20; + RESERVED0 :bit12; + end; + TCP_ROQ2_AVAIL=bitpacked record ROQ_CNT_IB2:bit11; RESERVED0 :bit21; @@ -1243,6 +8009,153 @@ type RESET_STATUS :bit16; end; + TCRTC_CRC_CNTL=bitpacked record + CRTC_CRC_EN :bit1; + RESERVED0 :bit3; + CRTC_CRC_CONT_EN :bit1; + RESERVED1 :bit3; + CRTC_CRC_STEREO_MODE :bit2; + RESERVED2 :bit2; + CRTC_CRC_INTERLACE_MODE :bit2; + RESERVED3 :bit2; + CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS:bit1; + RESERVED4 :bit3; + CRTC_CRC0_SELECT :bit3; + RESERVED5 :bit1; + CRTC_CRC1_SELECT :bit3; + RESERVED6 :bit5; + end; + + TCRTC_H_SYNC_A=bitpacked record + CRTC_H_SYNC_A_START:bit14; + RESERVED0 :bit2; + CRTC_H_SYNC_A_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_H_SYNC_B=bitpacked record + CRTC_H_SYNC_B_START:bit14; + RESERVED0 :bit2; + CRTC_H_SYNC_B_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_V_SYNC_A=bitpacked record + CRTC_V_SYNC_A_START:bit14; + RESERVED0 :bit2; + CRTC_V_SYNC_A_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_V_SYNC_B=bitpacked record + CRTC_V_SYNC_B_START:bit14; + RESERVED0 :bit2; + CRTC_V_SYNC_B_END :bit14; + RESERVED1 :bit2; + end; + + TCS_COPY_STATE=bitpacked record + SRC_STATE_ID:bit3; + RESERVED0 :bit29; + end; + + TCUR2_HOT_SPOT=bitpacked record + CURSOR2_HOT_SPOT_Y:bit7; + RESERVED0 :bit9; + CURSOR2_HOT_SPOT_X:bit7; + RESERVED1 :bit9; + end; + + TCUR2_POSITION=bitpacked record + CURSOR2_Y_POSITION:bit14; + RESERVED0 :bit2; + CURSOR2_X_POSITION:bit14; + RESERVED1 :bit2; + end; + + TD1VGA_CONTROL=bitpacked record + D1VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D1VGA_TIMING_SELECT :bit1; + D1VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D1VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D1VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TD2VGA_CONTROL=bitpacked record + D2VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D2VGA_TIMING_SELECT :bit1; + D2VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D2VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D2VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TD3VGA_CONTROL=bitpacked record + D3VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D3VGA_TIMING_SELECT :bit1; + D3VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D3VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D3VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TD4VGA_CONTROL=bitpacked record + D4VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D4VGA_TIMING_SELECT :bit1; + D4VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D4VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D4VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TD5VGA_CONTROL=bitpacked record + D5VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D5VGA_TIMING_SELECT :bit1; + D5VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D5VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D5VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TD6VGA_CONTROL=bitpacked record + D6VGA_MODE_ENABLE :bit1; + RESERVED0 :bit7; + D6VGA_TIMING_SELECT :bit1; + D6VGA_SYNC_POLARITY_SELECT:bit1; + RESERVED1 :bit6; + D6VGA_OVERSCAN_COLOR_EN :bit1; + RESERVED2 :bit7; + D6VGA_ROTATE :bit2; + RESERVED3 :bit6; + end; + + TDAC_POWERDOWN=bitpacked record + DAC_POWERDOWN :bit1; + RESERVED0 :bit7; + DAC_POWERDOWN_BLUE :bit1; + RESERVED1 :bit7; + DAC_POWERDOWN_GREEN:bit1; + RESERVED2 :bit7; + DAC_POWERDOWN_RED :bit1; + RESERVED3 :bit7; + end; + TDB_DEPTH_INFO=bitpacked record ADDR5_SWIZZLE_MASK:bit4; ARRAY_MODE :bit4; @@ -1282,6 +8195,1890 @@ type AUTO_FLUSH_QUAD :bit1; end; + TDCCG_GTC_CNTL=bitpacked record + DCCG_GTC_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TDCIO_DEBUG_ID=bit32; + + TDCIO_DPHY_SEL=bitpacked record + DPHY_LANE0_SEL:bit2; + DPHY_LANE1_SEL:bit2; + DPHY_LANE2_SEL:bit2; + DPHY_LANE3_SEL:bit2; + RESERVED0 :bit24; + end; + + TDC_GPIO_DEBUG=bitpacked record + DC_GPIO_VIP_DEBUG :bit1; + RESERVED0 :bit7; + DC_GPIO_MACRO_DEBUG :bit2; + RESERVED1 :bit6; + DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL:bit1; + DC_GPIO_DEBUG_BUS_FLOP_EN :bit1; + RESERVED2 :bit13; + DPRX_LOOPBACK_ENABLE :bit1; + end; + + TDC_GPIO_HPD_A=bitpacked record + DC_GPIO_HPD1_A:bit1; + RESERVED0 :bit7; + DC_GPIO_HPD2_A:bit1; + RESERVED1 :bit7; + DC_GPIO_HPD3_A:bit1; + RESERVED2 :bit7; + DC_GPIO_HPD4_A:bit1; + RESERVED3 :bit1; + DC_GPIO_HPD5_A:bit1; + RESERVED4 :bit1; + DC_GPIO_HPD6_A:bit1; + RESERVED5 :bit3; + end; + + TDC_GPIO_HPD_Y=bitpacked record + DC_GPIO_HPD1_Y:bit1; + RESERVED0 :bit7; + DC_GPIO_HPD2_Y:bit1; + RESERVED1 :bit7; + DC_GPIO_HPD3_Y:bit1; + RESERVED2 :bit7; + DC_GPIO_HPD4_Y:bit1; + RESERVED3 :bit1; + DC_GPIO_HPD5_Y:bit1; + RESERVED4 :bit1; + DC_GPIO_HPD6_Y:bit1; + RESERVED5 :bit3; + end; + + TDEVICE_STATUS=bitpacked record + CORR_ERR :bit1; + NON_FATAL_ERR :bit1; + FATAL_ERR :bit1; + USR_DETECTED :bit1; + AUX_PWR :bit1; + TRANSACTIONS_PEND:bit1; + RESERVED0 :bit26; + end; + + TDIDT_DB_CTRL0=bitpacked record + DIDT_CTRL_EN :bit1; + USE_REF_CLOCK :bit1; + PHASE_OFFSET :bit2; + DIDT_CTRL_RST :bit1; + DIDT_CLK_EN_OVERRIDE:bit1; + RESERVED0 :bit6; + RESERVED1 :bit6; + UNUSED_0 :bit14; + end; + + TDIDT_DB_CTRL1=bitpacked record + MIN_POWER:bit16; + MAX_POWER:bit16; + end; + + TDIDT_DB_CTRL2=bitpacked record + MAX_POWER_DELTA :bit14; + RESERVED0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + RESERVED1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + RESERVED2 :bit1; + end; + + TDIDT_IND_DATA=bit32; + + TDIDT_SQ_CTRL0=bitpacked record + DIDT_CTRL_EN :bit1; + USE_REF_CLOCK :bit1; + PHASE_OFFSET :bit2; + DIDT_CTRL_RST :bit1; + DIDT_CLK_EN_OVERRIDE :bit1; + DIDT_MAX_STALLS_ALLOWED_HI:bit6; + DIDT_MAX_STALLS_ALLOWED_LO:bit6; + UNUSED_0 :bit14; + end; + + TDIDT_SQ_CTRL1=bitpacked record + MIN_POWER:bit16; + MAX_POWER:bit16; + end; + + TDIDT_SQ_CTRL2=bitpacked record + MAX_POWER_DELTA :bit14; + RESERVED0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + RESERVED1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + RESERVED2 :bit1; + end; + + TDIDT_TD_CTRL0=bitpacked record + DIDT_CTRL_EN :bit1; + USE_REF_CLOCK :bit1; + PHASE_OFFSET :bit2; + DIDT_CTRL_RST :bit1; + DIDT_CLK_EN_OVERRIDE :bit1; + DIDT_MAX_STALLS_ALLOWED_HI:bit6; + DIDT_MAX_STALLS_ALLOWED_LO:bit6; + UNUSED_0 :bit14; + end; + + TDIDT_TD_CTRL1=bitpacked record + MIN_POWER:bit16; + MAX_POWER:bit16; + end; + + TDIDT_TD_CTRL2=bitpacked record + MAX_POWER_DELTA :bit14; + RESERVED0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + RESERVED1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + RESERVED2 :bit1; + end; + + TDMCU_FW_CS_HI=bit32; + + TDMCU_FW_CS_LO=bit32; + + TDMIF_HW_DEBUG=bit32; + + TDOUT_SCRATCH0=bit32; + + TDOUT_SCRATCH1=bit32; + + TDOUT_SCRATCH2=bit32; + + TDOUT_SCRATCH3=bit32; + + TDOUT_SCRATCH4=bit32; + + TDOUT_SCRATCH5=bit32; + + TDOUT_SCRATCH6=bit32; + + TDOUT_SCRATCH7=bit32; + + TDPM_TABLE_100=bit32; + + TDPM_TABLE_101=bit32; + + TDPM_TABLE_102=bit32; + + TDPM_TABLE_103=bit32; + + TDPM_TABLE_104=bitpacked record + GraphicsLevel_0_EnabledForThrottle:bit8; + GraphicsLevel_0_EnabledForActivity:bit8; + GraphicsLevel_0_DisplayWatermark :bit8; + GraphicsLevel_0_SclkDid :bit8; + end; + + TDPM_TABLE_105=bitpacked record + GraphicsLevel_0_PowerThrottle :bit8; + GraphicsLevel_0_VoltageDownHyst:bit8; + GraphicsLevel_0_DownHyst :bit8; + GraphicsLevel_0_UpHyst :bit8; + end; + + TDPM_TABLE_106=bitpacked record + GraphicsLevel_1_MinVoltage_Phases:bit8; + GraphicsLevel_1_MinVoltage_VddGfx:bit8; + GraphicsLevel_1_MinVoltage_Vddci :bit8; + GraphicsLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_107=bit32; + + TDPM_TABLE_108=bitpacked record + GraphicsLevel_1_ActivityLevel :bit16; + GraphicsLevel_1_DeepSleepDivId:bit8; + GraphicsLevel_1_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_109=bit32; + + TDPM_TABLE_110=bit32; + + TDPM_TABLE_111=bit32; + + TDPM_TABLE_112=bit32; + + TDPM_TABLE_113=bit32; + + TDPM_TABLE_114=bit32; + + TDPM_TABLE_115=bitpacked record + GraphicsLevel_1_EnabledForThrottle:bit8; + GraphicsLevel_1_EnabledForActivity:bit8; + GraphicsLevel_1_DisplayWatermark :bit8; + GraphicsLevel_1_SclkDid :bit8; + end; + + TDPM_TABLE_116=bitpacked record + GraphicsLevel_1_PowerThrottle :bit8; + GraphicsLevel_1_VoltageDownHyst:bit8; + GraphicsLevel_1_DownHyst :bit8; + GraphicsLevel_1_UpHyst :bit8; + end; + + TDPM_TABLE_117=bitpacked record + GraphicsLevel_2_MinVoltage_Phases:bit8; + GraphicsLevel_2_MinVoltage_VddGfx:bit8; + GraphicsLevel_2_MinVoltage_Vddci :bit8; + GraphicsLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_118=bit32; + + TDPM_TABLE_119=bitpacked record + GraphicsLevel_2_ActivityLevel :bit16; + GraphicsLevel_2_DeepSleepDivId:bit8; + GraphicsLevel_2_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_120=bit32; + + TDPM_TABLE_121=bit32; + + TDPM_TABLE_122=bit32; + + TDPM_TABLE_123=bit32; + + TDPM_TABLE_124=bit32; + + TDPM_TABLE_125=bit32; + + TDPM_TABLE_126=bitpacked record + GraphicsLevel_2_EnabledForThrottle:bit8; + GraphicsLevel_2_EnabledForActivity:bit8; + GraphicsLevel_2_DisplayWatermark :bit8; + GraphicsLevel_2_SclkDid :bit8; + end; + + TDPM_TABLE_127=bitpacked record + GraphicsLevel_2_PowerThrottle :bit8; + GraphicsLevel_2_VoltageDownHyst:bit8; + GraphicsLevel_2_DownHyst :bit8; + GraphicsLevel_2_UpHyst :bit8; + end; + + TDPM_TABLE_128=bitpacked record + GraphicsLevel_3_MinVoltage_Phases:bit8; + GraphicsLevel_3_MinVoltage_VddGfx:bit8; + GraphicsLevel_3_MinVoltage_Vddci :bit8; + GraphicsLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_129=bit32; + + TDPM_TABLE_130=bitpacked record + GraphicsLevel_3_ActivityLevel :bit16; + GraphicsLevel_3_DeepSleepDivId:bit8; + GraphicsLevel_3_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_131=bit32; + + TDPM_TABLE_132=bit32; + + TDPM_TABLE_133=bit32; + + TDPM_TABLE_134=bit32; + + TDPM_TABLE_135=bit32; + + TDPM_TABLE_136=bit32; + + TDPM_TABLE_137=bitpacked record + GraphicsLevel_3_EnabledForThrottle:bit8; + GraphicsLevel_3_EnabledForActivity:bit8; + GraphicsLevel_3_DisplayWatermark :bit8; + GraphicsLevel_3_SclkDid :bit8; + end; + + TDPM_TABLE_138=bitpacked record + GraphicsLevel_3_PowerThrottle :bit8; + GraphicsLevel_3_VoltageDownHyst:bit8; + GraphicsLevel_3_DownHyst :bit8; + GraphicsLevel_3_UpHyst :bit8; + end; + + TDPM_TABLE_139=bitpacked record + GraphicsLevel_4_MinVoltage_Phases:bit8; + GraphicsLevel_4_MinVoltage_VddGfx:bit8; + GraphicsLevel_4_MinVoltage_Vddci :bit8; + GraphicsLevel_4_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_140=bit32; + + TDPM_TABLE_141=bitpacked record + GraphicsLevel_4_ActivityLevel :bit16; + GraphicsLevel_4_DeepSleepDivId:bit8; + GraphicsLevel_4_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_142=bit32; + + TDPM_TABLE_143=bit32; + + TDPM_TABLE_144=bit32; + + TDPM_TABLE_145=bit32; + + TDPM_TABLE_146=bit32; + + TDPM_TABLE_147=bit32; + + TDPM_TABLE_148=bitpacked record + GraphicsLevel_4_EnabledForThrottle:bit8; + GraphicsLevel_4_EnabledForActivity:bit8; + GraphicsLevel_4_DisplayWatermark :bit8; + GraphicsLevel_4_SclkDid :bit8; + end; + + TDPM_TABLE_149=bitpacked record + GraphicsLevel_4_PowerThrottle :bit8; + GraphicsLevel_4_VoltageDownHyst:bit8; + GraphicsLevel_4_DownHyst :bit8; + GraphicsLevel_4_UpHyst :bit8; + end; + + TDPM_TABLE_150=bitpacked record + GraphicsLevel_5_MinVoltage_Phases:bit8; + GraphicsLevel_5_MinVoltage_VddGfx:bit8; + GraphicsLevel_5_MinVoltage_Vddci :bit8; + GraphicsLevel_5_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_151=bit32; + + TDPM_TABLE_152=bitpacked record + GraphicsLevel_5_ActivityLevel :bit16; + GraphicsLevel_5_DeepSleepDivId:bit8; + GraphicsLevel_5_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_153=bit32; + + TDPM_TABLE_154=bit32; + + TDPM_TABLE_155=bit32; + + TDPM_TABLE_156=bit32; + + TDPM_TABLE_157=bit32; + + TDPM_TABLE_158=bit32; + + TDPM_TABLE_159=bitpacked record + GraphicsLevel_5_EnabledForThrottle:bit8; + GraphicsLevel_5_EnabledForActivity:bit8; + GraphicsLevel_5_DisplayWatermark :bit8; + GraphicsLevel_5_SclkDid :bit8; + end; + + TDPM_TABLE_160=bitpacked record + GraphicsLevel_5_PowerThrottle :bit8; + GraphicsLevel_5_VoltageDownHyst:bit8; + GraphicsLevel_5_DownHyst :bit8; + GraphicsLevel_5_UpHyst :bit8; + end; + + TDPM_TABLE_161=bitpacked record + GraphicsLevel_6_MinVoltage_Phases:bit8; + GraphicsLevel_6_MinVoltage_VddGfx:bit8; + GraphicsLevel_6_MinVoltage_Vddci :bit8; + GraphicsLevel_6_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_162=bit32; + + TDPM_TABLE_163=bitpacked record + GraphicsLevel_6_ActivityLevel :bit16; + GraphicsLevel_6_DeepSleepDivId:bit8; + GraphicsLevel_6_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_164=bit32; + + TDPM_TABLE_165=bit32; + + TDPM_TABLE_166=bit32; + + TDPM_TABLE_167=bit32; + + TDPM_TABLE_168=bit32; + + TDPM_TABLE_169=bit32; + + TDPM_TABLE_170=bitpacked record + GraphicsLevel_6_EnabledForThrottle:bit8; + GraphicsLevel_6_EnabledForActivity:bit8; + GraphicsLevel_6_DisplayWatermark :bit8; + GraphicsLevel_6_SclkDid :bit8; + end; + + TDPM_TABLE_171=bitpacked record + GraphicsLevel_6_PowerThrottle :bit8; + GraphicsLevel_6_VoltageDownHyst:bit8; + GraphicsLevel_6_DownHyst :bit8; + GraphicsLevel_6_UpHyst :bit8; + end; + + TDPM_TABLE_172=bitpacked record + GraphicsLevel_7_MinVoltage_Phases:bit8; + GraphicsLevel_7_MinVoltage_VddGfx:bit8; + GraphicsLevel_7_MinVoltage_Vddci :bit8; + GraphicsLevel_7_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_173=bit32; + + TDPM_TABLE_174=bitpacked record + GraphicsLevel_7_ActivityLevel :bit16; + GraphicsLevel_7_DeepSleepDivId:bit8; + GraphicsLevel_7_pcieDpmLevel :bit8; + end; + + TDPM_TABLE_175=bit32; + + TDPM_TABLE_176=bit32; + + TDPM_TABLE_177=bit32; + + TDPM_TABLE_178=bit32; + + TDPM_TABLE_179=bit32; + + TDPM_TABLE_180=bit32; + + TDPM_TABLE_181=bitpacked record + GraphicsLevel_7_EnabledForThrottle:bit8; + GraphicsLevel_7_EnabledForActivity:bit8; + GraphicsLevel_7_DisplayWatermark :bit8; + GraphicsLevel_7_SclkDid :bit8; + end; + + TDPM_TABLE_182=bitpacked record + GraphicsLevel_7_PowerThrottle :bit8; + GraphicsLevel_7_VoltageDownHyst:bit8; + GraphicsLevel_7_DownHyst :bit8; + GraphicsLevel_7_UpHyst :bit8; + end; + + TDPM_TABLE_183=bitpacked record + MemoryACPILevel_MinVoltage_Phases:bit8; + MemoryACPILevel_MinVoltage_VddGfx:bit8; + MemoryACPILevel_MinVoltage_Vddci :bit8; + MemoryACPILevel_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_184=bit32; + + TDPM_TABLE_185=bit32; + + TDPM_TABLE_186=bitpacked record + MemoryACPILevel_EnabledForActivity:bit8; + MemoryACPILevel_EnabledForThrottle:bit8; + MemoryACPILevel_FreqRange :bit8; + MemoryACPILevel_StutterEnable :bit8; + end; + + TDPM_TABLE_187=bitpacked record + MemoryACPILevel_padding :bit8; + MemoryACPILevel_VoltageDownHyst:bit8; + MemoryACPILevel_DownHyst :bit8; + MemoryACPILevel_UpHyst :bit8; + end; + + TDPM_TABLE_188=bitpacked record + MemoryACPILevel_MclkDivider :bit8; + MemoryACPILevel_DisplayWatermark:bit8; + MemoryACPILevel_ActivityLevel :bit16; + end; + + TDPM_TABLE_189=bitpacked record + MemoryLevel_0_MinVoltage_Phases:bit8; + MemoryLevel_0_MinVoltage_VddGfx:bit8; + MemoryLevel_0_MinVoltage_Vddci :bit8; + MemoryLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_190=bit32; + + TDPM_TABLE_191=bit32; + + TDPM_TABLE_192=bitpacked record + MemoryLevel_0_EnabledForActivity:bit8; + MemoryLevel_0_EnabledForThrottle:bit8; + MemoryLevel_0_FreqRange :bit8; + MemoryLevel_0_StutterEnable :bit8; + end; + + TDPM_TABLE_193=bitpacked record + MemoryLevel_0_padding :bit8; + MemoryLevel_0_VoltageDownHyst:bit8; + MemoryLevel_0_DownHyst :bit8; + MemoryLevel_0_UpHyst :bit8; + end; + + TDPM_TABLE_194=bitpacked record + MemoryLevel_0_MclkDivider :bit8; + MemoryLevel_0_DisplayWatermark:bit8; + MemoryLevel_0_ActivityLevel :bit16; + end; + + TDPM_TABLE_195=bitpacked record + MemoryLevel_1_MinVoltage_Phases:bit8; + MemoryLevel_1_MinVoltage_VddGfx:bit8; + MemoryLevel_1_MinVoltage_Vddci :bit8; + MemoryLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_196=bit32; + + TDPM_TABLE_197=bit32; + + TDPM_TABLE_198=bitpacked record + MemoryLevel_1_EnabledForActivity:bit8; + MemoryLevel_1_EnabledForThrottle:bit8; + MemoryLevel_1_FreqRange :bit8; + MemoryLevel_1_StutterEnable :bit8; + end; + + TDPM_TABLE_199=bitpacked record + MemoryLevel_1_padding :bit8; + MemoryLevel_1_VoltageDownHyst:bit8; + MemoryLevel_1_DownHyst :bit8; + MemoryLevel_1_UpHyst :bit8; + end; + + TDPM_TABLE_200=bitpacked record + MemoryLevel_1_MclkDivider :bit8; + MemoryLevel_1_DisplayWatermark:bit8; + MemoryLevel_1_ActivityLevel :bit16; + end; + + TDPM_TABLE_201=bitpacked record + MemoryLevel_2_MinVoltage_Phases:bit8; + MemoryLevel_2_MinVoltage_VddGfx:bit8; + MemoryLevel_2_MinVoltage_Vddci :bit8; + MemoryLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_202=bit32; + + TDPM_TABLE_203=bit32; + + TDPM_TABLE_204=bitpacked record + MemoryLevel_2_EnabledForActivity:bit8; + MemoryLevel_2_EnabledForThrottle:bit8; + MemoryLevel_2_FreqRange :bit8; + MemoryLevel_2_StutterEnable :bit8; + end; + + TDPM_TABLE_205=bitpacked record + MemoryLevel_2_padding :bit8; + MemoryLevel_2_VoltageDownHyst:bit8; + MemoryLevel_2_DownHyst :bit8; + MemoryLevel_2_UpHyst :bit8; + end; + + TDPM_TABLE_206=bitpacked record + MemoryLevel_2_MclkDivider :bit8; + MemoryLevel_2_DisplayWatermark:bit8; + MemoryLevel_2_ActivityLevel :bit16; + end; + + TDPM_TABLE_207=bitpacked record + MemoryLevel_3_MinVoltage_Phases:bit8; + MemoryLevel_3_MinVoltage_VddGfx:bit8; + MemoryLevel_3_MinVoltage_Vddci :bit8; + MemoryLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_208=bit32; + + TDPM_TABLE_209=bit32; + + TDPM_TABLE_210=bitpacked record + MemoryLevel_3_EnabledForActivity:bit8; + MemoryLevel_3_EnabledForThrottle:bit8; + MemoryLevel_3_FreqRange :bit8; + MemoryLevel_3_StutterEnable :bit8; + end; + + TDPM_TABLE_211=bitpacked record + MemoryLevel_3_padding :bit8; + MemoryLevel_3_VoltageDownHyst:bit8; + MemoryLevel_3_DownHyst :bit8; + MemoryLevel_3_UpHyst :bit8; + end; + + TDPM_TABLE_212=bitpacked record + MemoryLevel_3_MclkDivider :bit8; + MemoryLevel_3_DisplayWatermark:bit8; + MemoryLevel_3_ActivityLevel :bit16; + end; + + TDPM_TABLE_213=bitpacked record + LinkLevel_0_SPC :bit8; + LinkLevel_0_EnabledForActivity:bit8; + LinkLevel_0_PcieLaneCount :bit8; + LinkLevel_0_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_214=bit32; + + TDPM_TABLE_215=bit32; + + TDPM_TABLE_216=bit32; + + TDPM_TABLE_217=bitpacked record + LinkLevel_1_SPC :bit8; + LinkLevel_1_EnabledForActivity:bit8; + LinkLevel_1_PcieLaneCount :bit8; + LinkLevel_1_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_218=bit32; + + TDPM_TABLE_219=bit32; + + TDPM_TABLE_220=bit32; + + TDPM_TABLE_221=bitpacked record + LinkLevel_2_SPC :bit8; + LinkLevel_2_EnabledForActivity:bit8; + LinkLevel_2_PcieLaneCount :bit8; + LinkLevel_2_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_222=bit32; + + TDPM_TABLE_223=bit32; + + TDPM_TABLE_224=bit32; + + TDPM_TABLE_225=bitpacked record + LinkLevel_3_SPC :bit8; + LinkLevel_3_EnabledForActivity:bit8; + LinkLevel_3_PcieLaneCount :bit8; + LinkLevel_3_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_226=bit32; + + TDPM_TABLE_227=bit32; + + TDPM_TABLE_228=bit32; + + TDPM_TABLE_229=bitpacked record + LinkLevel_4_SPC :bit8; + LinkLevel_4_EnabledForActivity:bit8; + LinkLevel_4_PcieLaneCount :bit8; + LinkLevel_4_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_230=bit32; + + TDPM_TABLE_231=bit32; + + TDPM_TABLE_232=bit32; + + TDPM_TABLE_233=bitpacked record + LinkLevel_5_SPC :bit8; + LinkLevel_5_EnabledForActivity:bit8; + LinkLevel_5_PcieLaneCount :bit8; + LinkLevel_5_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_234=bit32; + + TDPM_TABLE_235=bit32; + + TDPM_TABLE_236=bit32; + + TDPM_TABLE_237=bitpacked record + LinkLevel_6_SPC :bit8; + LinkLevel_6_EnabledForActivity:bit8; + LinkLevel_6_PcieLaneCount :bit8; + LinkLevel_6_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_238=bit32; + + TDPM_TABLE_239=bit32; + + TDPM_TABLE_240=bit32; + + TDPM_TABLE_241=bitpacked record + LinkLevel_7_SPC :bit8; + LinkLevel_7_EnabledForActivity:bit8; + LinkLevel_7_PcieLaneCount :bit8; + LinkLevel_7_PcieGenSpeed :bit8; + end; + + TDPM_TABLE_242=bit32; + + TDPM_TABLE_243=bit32; + + TDPM_TABLE_244=bit32; + + TDPM_TABLE_245=bit32; + + TDPM_TABLE_246=bitpacked record + ACPILevel_MinVoltage_Phases:bit8; + ACPILevel_MinVoltage_VddGfx:bit8; + ACPILevel_MinVoltage_Vddci :bit8; + ACPILevel_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_247=bit32; + + TDPM_TABLE_248=bitpacked record + ACPILevel_padding :bit8; + ACPILevel_DeepSleepDivId :bit8; + ACPILevel_DisplayWatermark:bit8; + ACPILevel_SclkDid :bit8; + end; + + TDPM_TABLE_249=bit32; + + TDPM_TABLE_250=bit32; + + TDPM_TABLE_251=bit32; + + TDPM_TABLE_252=bit32; + + TDPM_TABLE_253=bit32; + + TDPM_TABLE_254=bit32; + + TDPM_TABLE_255=bit32; + + TDPM_TABLE_256=bit32; + + TDPM_TABLE_257=bit32; + + TDPM_TABLE_258=bit32; + + TDPM_TABLE_259=bitpacked record + UvdLevel_0_MinVoltage_Phases:bit8; + UvdLevel_0_MinVoltage_VddGfx:bit8; + UvdLevel_0_MinVoltage_Vddci :bit8; + UvdLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_260=bitpacked record + UvdLevel_0_padding_1 :bit8; + UvdLevel_0_padding_0 :bit8; + UvdLevel_0_DclkDivider:bit8; + UvdLevel_0_VclkDivider:bit8; + end; + + TDPM_TABLE_261=bit32; + + TDPM_TABLE_262=bit32; + + TDPM_TABLE_263=bitpacked record + UvdLevel_1_MinVoltage_Phases:bit8; + UvdLevel_1_MinVoltage_VddGfx:bit8; + UvdLevel_1_MinVoltage_Vddci :bit8; + UvdLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_264=bitpacked record + UvdLevel_1_padding_1 :bit8; + UvdLevel_1_padding_0 :bit8; + UvdLevel_1_DclkDivider:bit8; + UvdLevel_1_VclkDivider:bit8; + end; + + TDPM_TABLE_265=bit32; + + TDPM_TABLE_266=bit32; + + TDPM_TABLE_267=bitpacked record + UvdLevel_2_MinVoltage_Phases:bit8; + UvdLevel_2_MinVoltage_VddGfx:bit8; + UvdLevel_2_MinVoltage_Vddci :bit8; + UvdLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_268=bitpacked record + UvdLevel_2_padding_1 :bit8; + UvdLevel_2_padding_0 :bit8; + UvdLevel_2_DclkDivider:bit8; + UvdLevel_2_VclkDivider:bit8; + end; + + TDPM_TABLE_269=bit32; + + TDPM_TABLE_270=bit32; + + TDPM_TABLE_271=bitpacked record + UvdLevel_3_MinVoltage_Phases:bit8; + UvdLevel_3_MinVoltage_VddGfx:bit8; + UvdLevel_3_MinVoltage_Vddci :bit8; + UvdLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_272=bitpacked record + UvdLevel_3_padding_1 :bit8; + UvdLevel_3_padding_0 :bit8; + UvdLevel_3_DclkDivider:bit8; + UvdLevel_3_VclkDivider:bit8; + end; + + TDPM_TABLE_273=bit32; + + TDPM_TABLE_274=bit32; + + TDPM_TABLE_275=bitpacked record + UvdLevel_4_MinVoltage_Phases:bit8; + UvdLevel_4_MinVoltage_VddGfx:bit8; + UvdLevel_4_MinVoltage_Vddci :bit8; + UvdLevel_4_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_276=bitpacked record + UvdLevel_4_padding_1 :bit8; + UvdLevel_4_padding_0 :bit8; + UvdLevel_4_DclkDivider:bit8; + UvdLevel_4_VclkDivider:bit8; + end; + + TDPM_TABLE_277=bit32; + + TDPM_TABLE_278=bit32; + + TDPM_TABLE_279=bitpacked record + UvdLevel_5_MinVoltage_Phases:bit8; + UvdLevel_5_MinVoltage_VddGfx:bit8; + UvdLevel_5_MinVoltage_Vddci :bit8; + UvdLevel_5_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_280=bitpacked record + UvdLevel_5_padding_1 :bit8; + UvdLevel_5_padding_0 :bit8; + UvdLevel_5_DclkDivider:bit8; + UvdLevel_5_VclkDivider:bit8; + end; + + TDPM_TABLE_281=bit32; + + TDPM_TABLE_282=bit32; + + TDPM_TABLE_283=bitpacked record + UvdLevel_6_MinVoltage_Phases:bit8; + UvdLevel_6_MinVoltage_VddGfx:bit8; + UvdLevel_6_MinVoltage_Vddci :bit8; + UvdLevel_6_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_284=bitpacked record + UvdLevel_6_padding_1 :bit8; + UvdLevel_6_padding_0 :bit8; + UvdLevel_6_DclkDivider:bit8; + UvdLevel_6_VclkDivider:bit8; + end; + + TDPM_TABLE_285=bit32; + + TDPM_TABLE_286=bit32; + + TDPM_TABLE_287=bitpacked record + UvdLevel_7_MinVoltage_Phases:bit8; + UvdLevel_7_MinVoltage_VddGfx:bit8; + UvdLevel_7_MinVoltage_Vddci :bit8; + UvdLevel_7_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_288=bitpacked record + UvdLevel_7_padding_1 :bit8; + UvdLevel_7_padding_0 :bit8; + UvdLevel_7_DclkDivider:bit8; + UvdLevel_7_VclkDivider:bit8; + end; + + TDPM_TABLE_289=bit32; + + TDPM_TABLE_290=bitpacked record + VceLevel_0_MinVoltage_Phases:bit8; + VceLevel_0_MinVoltage_VddGfx:bit8; + VceLevel_0_MinVoltage_Vddci :bit8; + VceLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_291=bitpacked record + VceLevel_0_padding_2:bit8; + VceLevel_0_padding_1:bit8; + VceLevel_0_padding_0:bit8; + VceLevel_0_Divider :bit8; + end; + + TDPM_TABLE_292=bit32; + + TDPM_TABLE_293=bitpacked record + VceLevel_1_MinVoltage_Phases:bit8; + VceLevel_1_MinVoltage_VddGfx:bit8; + VceLevel_1_MinVoltage_Vddci :bit8; + VceLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_294=bitpacked record + VceLevel_1_padding_2:bit8; + VceLevel_1_padding_1:bit8; + VceLevel_1_padding_0:bit8; + VceLevel_1_Divider :bit8; + end; + + TDPM_TABLE_295=bit32; + + TDPM_TABLE_296=bitpacked record + VceLevel_2_MinVoltage_Phases:bit8; + VceLevel_2_MinVoltage_VddGfx:bit8; + VceLevel_2_MinVoltage_Vddci :bit8; + VceLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_297=bitpacked record + VceLevel_2_padding_2:bit8; + VceLevel_2_padding_1:bit8; + VceLevel_2_padding_0:bit8; + VceLevel_2_Divider :bit8; + end; + + TDPM_TABLE_298=bit32; + + TDPM_TABLE_299=bitpacked record + VceLevel_3_MinVoltage_Phases:bit8; + VceLevel_3_MinVoltage_VddGfx:bit8; + VceLevel_3_MinVoltage_Vddci :bit8; + VceLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_300=bitpacked record + VceLevel_3_padding_2:bit8; + VceLevel_3_padding_1:bit8; + VceLevel_3_padding_0:bit8; + VceLevel_3_Divider :bit8; + end; + + TDPM_TABLE_301=bit32; + + TDPM_TABLE_302=bitpacked record + VceLevel_4_MinVoltage_Phases:bit8; + VceLevel_4_MinVoltage_VddGfx:bit8; + VceLevel_4_MinVoltage_Vddci :bit8; + VceLevel_4_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_303=bitpacked record + VceLevel_4_padding_2:bit8; + VceLevel_4_padding_1:bit8; + VceLevel_4_padding_0:bit8; + VceLevel_4_Divider :bit8; + end; + + TDPM_TABLE_304=bit32; + + TDPM_TABLE_305=bitpacked record + VceLevel_5_MinVoltage_Phases:bit8; + VceLevel_5_MinVoltage_VddGfx:bit8; + VceLevel_5_MinVoltage_Vddci :bit8; + VceLevel_5_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_306=bitpacked record + VceLevel_5_padding_2:bit8; + VceLevel_5_padding_1:bit8; + VceLevel_5_padding_0:bit8; + VceLevel_5_Divider :bit8; + end; + + TDPM_TABLE_307=bit32; + + TDPM_TABLE_308=bitpacked record + VceLevel_6_MinVoltage_Phases:bit8; + VceLevel_6_MinVoltage_VddGfx:bit8; + VceLevel_6_MinVoltage_Vddci :bit8; + VceLevel_6_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_309=bitpacked record + VceLevel_6_padding_2:bit8; + VceLevel_6_padding_1:bit8; + VceLevel_6_padding_0:bit8; + VceLevel_6_Divider :bit8; + end; + + TDPM_TABLE_310=bit32; + + TDPM_TABLE_311=bitpacked record + VceLevel_7_MinVoltage_Phases:bit8; + VceLevel_7_MinVoltage_VddGfx:bit8; + VceLevel_7_MinVoltage_Vddci :bit8; + VceLevel_7_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_312=bitpacked record + VceLevel_7_padding_2:bit8; + VceLevel_7_padding_1:bit8; + VceLevel_7_padding_0:bit8; + VceLevel_7_Divider :bit8; + end; + + TDPM_TABLE_313=bit32; + + TDPM_TABLE_314=bitpacked record + AcpLevel_0_MinVoltage_Phases:bit8; + AcpLevel_0_MinVoltage_VddGfx:bit8; + AcpLevel_0_MinVoltage_Vddci :bit8; + AcpLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_315=bitpacked record + AcpLevel_0_padding_2:bit8; + AcpLevel_0_padding_1:bit8; + AcpLevel_0_padding_0:bit8; + AcpLevel_0_Divider :bit8; + end; + + TDPM_TABLE_316=bit32; + + TDPM_TABLE_317=bitpacked record + AcpLevel_1_MinVoltage_Phases:bit8; + AcpLevel_1_MinVoltage_VddGfx:bit8; + AcpLevel_1_MinVoltage_Vddci :bit8; + AcpLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_318=bitpacked record + AcpLevel_1_padding_2:bit8; + AcpLevel_1_padding_1:bit8; + AcpLevel_1_padding_0:bit8; + AcpLevel_1_Divider :bit8; + end; + + TDPM_TABLE_319=bit32; + + TDPM_TABLE_320=bitpacked record + AcpLevel_2_MinVoltage_Phases:bit8; + AcpLevel_2_MinVoltage_VddGfx:bit8; + AcpLevel_2_MinVoltage_Vddci :bit8; + AcpLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_321=bitpacked record + AcpLevel_2_padding_2:bit8; + AcpLevel_2_padding_1:bit8; + AcpLevel_2_padding_0:bit8; + AcpLevel_2_Divider :bit8; + end; + + TDPM_TABLE_322=bit32; + + TDPM_TABLE_323=bitpacked record + AcpLevel_3_MinVoltage_Phases:bit8; + AcpLevel_3_MinVoltage_VddGfx:bit8; + AcpLevel_3_MinVoltage_Vddci :bit8; + AcpLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_324=bitpacked record + AcpLevel_3_padding_2:bit8; + AcpLevel_3_padding_1:bit8; + AcpLevel_3_padding_0:bit8; + AcpLevel_3_Divider :bit8; + end; + + TDPM_TABLE_325=bit32; + + TDPM_TABLE_326=bitpacked record + AcpLevel_4_MinVoltage_Phases:bit8; + AcpLevel_4_MinVoltage_VddGfx:bit8; + AcpLevel_4_MinVoltage_Vddci :bit8; + AcpLevel_4_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_327=bitpacked record + AcpLevel_4_padding_2:bit8; + AcpLevel_4_padding_1:bit8; + AcpLevel_4_padding_0:bit8; + AcpLevel_4_Divider :bit8; + end; + + TDPM_TABLE_328=bit32; + + TDPM_TABLE_329=bitpacked record + AcpLevel_5_MinVoltage_Phases:bit8; + AcpLevel_5_MinVoltage_VddGfx:bit8; + AcpLevel_5_MinVoltage_Vddci :bit8; + AcpLevel_5_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_330=bitpacked record + AcpLevel_5_padding_2:bit8; + AcpLevel_5_padding_1:bit8; + AcpLevel_5_padding_0:bit8; + AcpLevel_5_Divider :bit8; + end; + + TDPM_TABLE_331=bit32; + + TDPM_TABLE_332=bitpacked record + AcpLevel_6_MinVoltage_Phases:bit8; + AcpLevel_6_MinVoltage_VddGfx:bit8; + AcpLevel_6_MinVoltage_Vddci :bit8; + AcpLevel_6_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_333=bitpacked record + AcpLevel_6_padding_2:bit8; + AcpLevel_6_padding_1:bit8; + AcpLevel_6_padding_0:bit8; + AcpLevel_6_Divider :bit8; + end; + + TDPM_TABLE_334=bit32; + + TDPM_TABLE_335=bitpacked record + AcpLevel_7_MinVoltage_Phases:bit8; + AcpLevel_7_MinVoltage_VddGfx:bit8; + AcpLevel_7_MinVoltage_Vddci :bit8; + AcpLevel_7_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_336=bitpacked record + AcpLevel_7_padding_2:bit8; + AcpLevel_7_padding_1:bit8; + AcpLevel_7_padding_0:bit8; + AcpLevel_7_Divider :bit8; + end; + + TDPM_TABLE_337=bit32; + + TDPM_TABLE_338=bitpacked record + SamuLevel_0_MinVoltage_Phases:bit8; + SamuLevel_0_MinVoltage_VddGfx:bit8; + SamuLevel_0_MinVoltage_Vddci :bit8; + SamuLevel_0_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_339=bitpacked record + SamuLevel_0_padding_2:bit8; + SamuLevel_0_padding_1:bit8; + SamuLevel_0_padding_0:bit8; + SamuLevel_0_Divider :bit8; + end; + + TDPM_TABLE_340=bit32; + + TDPM_TABLE_341=bitpacked record + SamuLevel_1_MinVoltage_Phases:bit8; + SamuLevel_1_MinVoltage_VddGfx:bit8; + SamuLevel_1_MinVoltage_Vddci :bit8; + SamuLevel_1_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_342=bitpacked record + SamuLevel_1_padding_2:bit8; + SamuLevel_1_padding_1:bit8; + SamuLevel_1_padding_0:bit8; + SamuLevel_1_Divider :bit8; + end; + + TDPM_TABLE_343=bit32; + + TDPM_TABLE_344=bitpacked record + SamuLevel_2_MinVoltage_Phases:bit8; + SamuLevel_2_MinVoltage_VddGfx:bit8; + SamuLevel_2_MinVoltage_Vddci :bit8; + SamuLevel_2_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_345=bitpacked record + SamuLevel_2_padding_2:bit8; + SamuLevel_2_padding_1:bit8; + SamuLevel_2_padding_0:bit8; + SamuLevel_2_Divider :bit8; + end; + + TDPM_TABLE_346=bit32; + + TDPM_TABLE_347=bitpacked record + SamuLevel_3_MinVoltage_Phases:bit8; + SamuLevel_3_MinVoltage_VddGfx:bit8; + SamuLevel_3_MinVoltage_Vddci :bit8; + SamuLevel_3_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_348=bitpacked record + SamuLevel_3_padding_2:bit8; + SamuLevel_3_padding_1:bit8; + SamuLevel_3_padding_0:bit8; + SamuLevel_3_Divider :bit8; + end; + + TDPM_TABLE_349=bit32; + + TDPM_TABLE_350=bitpacked record + SamuLevel_4_MinVoltage_Phases:bit8; + SamuLevel_4_MinVoltage_VddGfx:bit8; + SamuLevel_4_MinVoltage_Vddci :bit8; + SamuLevel_4_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_351=bitpacked record + SamuLevel_4_padding_2:bit8; + SamuLevel_4_padding_1:bit8; + SamuLevel_4_padding_0:bit8; + SamuLevel_4_Divider :bit8; + end; + + TDPM_TABLE_352=bit32; + + TDPM_TABLE_353=bitpacked record + SamuLevel_5_MinVoltage_Phases:bit8; + SamuLevel_5_MinVoltage_VddGfx:bit8; + SamuLevel_5_MinVoltage_Vddci :bit8; + SamuLevel_5_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_354=bitpacked record + SamuLevel_5_padding_2:bit8; + SamuLevel_5_padding_1:bit8; + SamuLevel_5_padding_0:bit8; + SamuLevel_5_Divider :bit8; + end; + + TDPM_TABLE_355=bit32; + + TDPM_TABLE_356=bitpacked record + SamuLevel_6_MinVoltage_Phases:bit8; + SamuLevel_6_MinVoltage_VddGfx:bit8; + SamuLevel_6_MinVoltage_Vddci :bit8; + SamuLevel_6_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_357=bitpacked record + SamuLevel_6_padding_2:bit8; + SamuLevel_6_padding_1:bit8; + SamuLevel_6_padding_0:bit8; + SamuLevel_6_Divider :bit8; + end; + + TDPM_TABLE_358=bit32; + + TDPM_TABLE_359=bitpacked record + SamuLevel_7_MinVoltage_Phases:bit8; + SamuLevel_7_MinVoltage_VddGfx:bit8; + SamuLevel_7_MinVoltage_Vddci :bit8; + SamuLevel_7_MinVoltage_Vddc :bit8; + end; + + TDPM_TABLE_360=bitpacked record + SamuLevel_7_padding_2:bit8; + SamuLevel_7_padding_1:bit8; + SamuLevel_7_padding_0:bit8; + SamuLevel_7_Divider :bit8; + end; + + TDPM_TABLE_361=bit32; + + TDPM_TABLE_362=bit32; + + TDPM_TABLE_363=bitpacked record + Ulv_VddcPhase :bit8; + Ulv_VddcOffsetVid:bit8; + Ulv_VddcOffset :bit16; + end; + + TDPM_TABLE_364=bit32; + + TDPM_TABLE_365=bit32; + + TDPM_TABLE_366=bit32; + + TDPM_TABLE_367=bit32; + + TDPM_TABLE_368=bit32; + + TDPM_TABLE_369=bit32; + + TDPM_TABLE_370=bit32; + + TDPM_TABLE_371=bit32; + + TDPM_TABLE_372=bit32; + + TDPM_TABLE_373=bit32; + + TDPM_TABLE_374=bit32; + + TDPM_TABLE_375=bit32; + + TDPM_TABLE_376=bit32; + + TDPM_TABLE_377=bit32; + + TDPM_TABLE_378=bit32; + + TDPM_TABLE_379=bit32; + + TDPM_TABLE_380=bit32; + + TDPM_TABLE_381=bit32; + + TDPM_TABLE_382=bit32; + + TDPM_TABLE_383=bit32; + + TDPM_TABLE_384=bit32; + + TDPM_TABLE_385=bit32; + + TDPM_TABLE_386=bit32; + + TDPM_TABLE_387=bit32; + + TDPM_TABLE_388=bit32; + + TDPM_TABLE_389=bit32; + + TDPM_TABLE_390=bit32; + + TDPM_TABLE_391=bit32; + + TDPM_TABLE_392=bit32; + + TDPM_TABLE_393=bit32; + + TDPM_TABLE_394=bit32; + + TDPM_TABLE_395=bit32; + + TDPM_TABLE_396=bit32; + + TDPM_TABLE_397=bit32; + + TDPM_TABLE_398=bitpacked record + SamuBootLevel:bit8; + AcpBootLevel :bit8; + VceBootLevel :bit8; + UvdBootLevel :bit8; + end; + + TDPM_TABLE_399=bitpacked record + GraphicsInterval :bit8; + GraphicsThermThrottleEnable:bit8; + GraphicsVoltageChangeEnable:bit8; + GraphicsBootLevel :bit8; + end; + + TDPM_TABLE_400=bitpacked record + TemperatureLimitHigh:bit16; + ThermalInterval :bit8; + VoltageInterval :bit8; + end; + + TDPM_TABLE_401=bitpacked record + MemoryVoltageChangeEnable:bit8; + MemoryBootLevel :bit8; + TemperatureLimitLow :bit16; + end; + + TDPM_TABLE_402=bitpacked record + MemoryThermThrottleEnable:bit8; + MemoryInterval :bit8; + BootMVdd :bit16; + end; + + TDPM_TABLE_403=bitpacked record + PhaseResponseTime :bit16; + VoltageResponseTime:bit16; + end; + + TDPM_TABLE_404=bitpacked record + DTEMode :bit8; + DTEInterval :bit8; + PCIeGenInterval :bit8; + PCIeBootLinkLevel:bit8; + end; + + TDPM_TABLE_405=bitpacked record + ThermGpio :bit8; + AcDcGpio :bit8; + VRHotGpio :bit8; + SVI2Enable:bit8; + end; + + TDPM_TABLE_406=bitpacked record + PPM_TemperatureLimit:bit16; + PPM_PkgPwrLimit :bit16; + end; + + TDPM_TABLE_407=bitpacked record + TargetTdp :bit16; + DefaultTdp:bit16; + end; + + TDPM_TABLE_408=bitpacked record + FpsLowThreshold :bit16; + FpsHighThreshold:bit16; + end; + + TDPM_TABLE_409=bitpacked record + BAPMTI_R_0_1_0:bit16; + BAPMTI_R_0_0_0:bit16; + end; + + TDPM_TABLE_410=bitpacked record + BAPMTI_R_1_0_0:bit16; + BAPMTI_R_0_2_0:bit16; + end; + + TDPM_TABLE_411=bitpacked record + BAPMTI_R_1_2_0:bit16; + BAPMTI_R_1_1_0:bit16; + end; + + TDPM_TABLE_412=bitpacked record + BAPMTI_R_2_1_0:bit16; + BAPMTI_R_2_0_0:bit16; + end; + + TDPM_TABLE_413=bitpacked record + BAPMTI_R_3_0_0:bit16; + BAPMTI_R_2_2_0:bit16; + end; + + TDPM_TABLE_414=bitpacked record + BAPMTI_R_3_2_0:bit16; + BAPMTI_R_3_1_0:bit16; + end; + + TDPM_TABLE_415=bitpacked record + BAPMTI_R_4_1_0:bit16; + BAPMTI_R_4_0_0:bit16; + end; + + TDPM_TABLE_416=bitpacked record + BAPMTI_RC_0_0_0:bit16; + BAPMTI_R_4_2_0 :bit16; + end; + + TDPM_TABLE_417=bitpacked record + BAPMTI_RC_0_2_0:bit16; + BAPMTI_RC_0_1_0:bit16; + end; + + TDPM_TABLE_418=bitpacked record + BAPMTI_RC_1_1_0:bit16; + BAPMTI_RC_1_0_0:bit16; + end; + + TDPM_TABLE_419=bitpacked record + BAPMTI_RC_2_0_0:bit16; + BAPMTI_RC_1_2_0:bit16; + end; + + TDPM_TABLE_420=bitpacked record + BAPMTI_RC_2_2_0:bit16; + BAPMTI_RC_2_1_0:bit16; + end; + + TDPM_TABLE_421=bitpacked record + BAPMTI_RC_3_1_0:bit16; + BAPMTI_RC_3_0_0:bit16; + end; + + TDPM_TABLE_422=bitpacked record + BAPMTI_RC_4_0_0:bit16; + BAPMTI_RC_3_2_0:bit16; + end; + + TDPM_TABLE_423=bitpacked record + BAPMTI_RC_4_2_0:bit16; + BAPMTI_RC_4_1_0:bit16; + end; + + TDPM_TABLE_424=bitpacked record + GpuTjHyst :bit8; + GpuTjMax :bit8; + DTETjOffset :bit8; + DTEAmbientTempBase:bit8; + end; + + TDPM_TABLE_425=bitpacked record + BootVoltage_Phases:bit8; + BootVoltage_VddGfx:bit8; + BootVoltage_Vddci :bit8; + BootVoltage_Vddc :bit8; + end; + + TDPM_TABLE_426=bit32; + + TDPM_TABLE_427=bit32; + + TDPM_TABLE_428=bit32; + + TDPM_TABLE_429=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID :bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID :bit8; + end; + + TDPM_TABLE_430=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0:bit8; + end; + + TDPM_TABLE_431=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4:bit8; + end; + + TDPM_TABLE_432=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID :bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID :bit8; + end; + + TDPM_TABLE_433=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0:bit8; + end; + + TDPM_TABLE_434=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4:bit8; + end; + + TDPM_TABLE_435=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID :bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID :bit8; + end; + + TDPM_TABLE_436=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0:bit8; + end; + + TDPM_TABLE_437=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4:bit8; + end; + + TDPM_TABLE_438=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID :bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID :bit8; + end; + + TDPM_TABLE_439=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0:bit8; + end; + + TDPM_TABLE_440=bitpacked record + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5:bit8; + ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4:bit8; + end; + + TDPREFCLK_CNTL=bitpacked record + DPREFCLK_SRC_SEL :bit3; + RESERVED0 :bit5; + UNB_DB_CLK_ENABLE:bit1; + RESERVED1 :bit23; + end; + + TDP_DTO0_PHASE=bit32; + + TDP_DTO1_PHASE=bit32; + + TDP_DTO2_PHASE=bit32; + + TDP_DTO3_PHASE=bit32; + + TDP_DTO4_PHASE=bit32; + + TDP_DTO5_PHASE=bit32; + + TDP_STEER_FIFO=bitpacked record + DP_STEER_FIFO_RESET :bit1; + RESERVED0 :bit3; + DP_STEER_OVERFLOW_FLAG:bit1; + DP_STEER_OVERFLOW_INT :bit1; + DP_STEER_OVERFLOW_ACK :bit1; + DP_STEER_OVERFLOW_MASK:bit1; + DP_TU_OVERFLOW_FLAG :bit1; + RESERVED1 :bit3; + DP_TU_OVERFLOW_ACK :bit1; + RESERVED2 :bit19; + end; + + TDP_VID_TIMING=bitpacked record + DP_VID_TIMING_MODE:bit1; + RESERVED0 :bit7; + DP_VID_M_N_GEN_EN :bit1; + RESERVED1 :bit15; + DP_VID_N_DIV :bit8; + end; + + TDVOACLKC_CNTL=bitpacked record + DVOACLKC_FINE_SKEW_CNTL :bit3; + RESERVED0 :bit5; + DVOACLKC_COARSE_SKEW_CNTL:bit5; + RESERVED1 :bit3; + DVOACLKC_FINE_ADJUST_EN :bit1; + DVOACLKC_COARSE_ADJUST_EN:bit1; + DVOACLKC_IN_PHASE :bit1; + RESERVED2 :bit13; + end; + + TDVOACLKD_CNTL=bitpacked record + DVOACLKD_FINE_SKEW_CNTL :bit3; + RESERVED0 :bit5; + DVOACLKD_COARSE_SKEW_CNTL:bit5; + RESERVED1 :bit3; + DVOACLKD_FINE_ADJUST_EN :bit1; + DVOACLKD_COARSE_ADJUST_EN:bit1; + DVOACLKD_IN_PHASE :bit1; + RESERVED2 :bit13; + end; + + TFBC_COMP_CNTL=bitpacked record + FBC_MIN_COMPRESSION:bit4; + RESERVED0 :bit12; + FBC_DEPTH_MONO08_EN:bit1; + FBC_DEPTH_MONO16_EN:bit1; + FBC_DEPTH_RGB04_EN :bit1; + FBC_DEPTH_RGB08_EN :bit1; + FBC_DEPTH_RGB16_EN :bit1; + RESERVED1 :bit11; + end; + + TFBC_COMP_MODE=bitpacked record + FBC_RLE_EN :bit1; + RESERVED0 :bit7; + FBC_DPCM4_RGB_EN:bit1; + FBC_DPCM8_RGB_EN:bit1; + FBC_DPCM4_YUV_EN:bit1; + FBC_DPCM8_YUV_EN:bit1; + RESERVED1 :bit4; + FBC_IND_EN :bit1; + RESERVED2 :bit15; + end; + + TFBC_DEBUG_CSR=bitpacked record + FBC_DEBUG_CSR_ADDR :bit10; + RESERVED0 :bit6; + FBC_DEBUG_CSR_WR_DATA:bit1; + FBC_DEBUG_CSR_RD_DATA:bit1; + RESERVED1 :bit13; + FBC_DEBUG_CSR_EN :bit1; + end; + + TFBC_IDLE_MASK=bit32; + + TFBC_IND_LUT10=bitpacked record + FBC_IND_LUT10:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT11=bitpacked record + FBC_IND_LUT11:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT12=bitpacked record + FBC_IND_LUT12:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT13=bitpacked record + FBC_IND_LUT13:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT14=bitpacked record + FBC_IND_LUT14:bit24; + RESERVED0 :bit8; + end; + + TFBC_IND_LUT15=bitpacked record + FBC_IND_LUT15:bit24; + RESERVED0 :bit8; + end; + + TGB_TILE_MODE0=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE1=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE2=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE3=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE4=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE5=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE6=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE7=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE8=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE9=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + TGDS_ATOM_BASE=bitpacked record BASE :bit16; UNUSED:bit16; @@ -1408,6 +10205,22 @@ type RESERVED0:bit16; end; + TGLOBAL_STATUS=bitpacked record + RESERVED0 :bit1; + FLUSH_STATUS:bit1; + RESERVED1 :bit30; + end; + + TGPIOPAD_PD_EN=bitpacked record + GPIO_PD_EN:bit31; + RESERVED0 :bit1; + end; + + TGPIOPAD_PU_EN=bitpacked record + GPIO_PU_EN:bit31; + RESERVED0 :bit1; + end; + TGRBM_CAM_DATA=bitpacked record CAM_ADDR :bit16; CAM_REMAPADDR:bit16; @@ -1431,6 +10244,59 @@ type RESERVED1 :bit16; end; + THDMI_ACR_32_0=bitpacked record + RESERVED0 :bit12; + HDMI_ACR_CTS_32:bit20; + end; + + THDMI_ACR_32_1=bitpacked record + HDMI_ACR_N_32:bit20; + RESERVED0 :bit12; + end; + + THDMI_ACR_44_0=bitpacked record + RESERVED0 :bit12; + HDMI_ACR_CTS_44:bit20; + end; + + THDMI_ACR_44_1=bitpacked record + HDMI_ACR_N_44:bit20; + RESERVED0 :bit12; + end; + + THDMI_ACR_48_0=bitpacked record + RESERVED0 :bit12; + HDMI_ACR_CTS_48:bit20; + end; + + THDMI_ACR_48_1=bitpacked record + HDMI_ACR_N_48:bit20; + RESERVED0 :bit12; + end; + + THDP_MISC_CNTL=bitpacked record + FLUSH_INVALIDATE_CACHE :bit1; + VM_ID :bit4; + OUTSTANDING_WRITE_COUNT_1024:bit1; + MULTIPLE_READS :bit1; + HDP_BIF_RDRET_CREDIT :bit4; + SIMULTANEOUS_READS_WRITES :bit1; + NO_SPLIT_ARRAY_LINEAR :bit1; + MC_RDREQ_CREDIT :bit6; + READ_CACHE_INVALIDATE :bit1; + ADDRLIB_LINEAR_BYPASS :bit1; + FED_ENABLE :bit1; + LEGACY_TILING_ENABLE :bit1; + LEGACY_SURFACES_ENABLE :bit1; + RESERVED0 :bit8; + end; + + THDP_VF_ENABLE=bitpacked record + VF_EN :bit1; + RESERVED0:bit15; + VF_NUM :bit16; + end; + TIA_DEBUG_CNTL=bitpacked record IA_DEBUG_INDX :bit6; IA_DEBUG_SEL_BUS_B:bit1; @@ -1679,6 +10545,560 @@ type prim_counter_q :bit12; end; + TIH_VMID_0_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_1_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_2_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_3_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_4_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_5_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_6_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_7_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_8_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_9_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TINTERRUPT_PIN=bitpacked record + INTERRUPT_PIN:bit8; + RESERVED0 :bit24; + end; + + TKEY_RANGE_RED=bitpacked record + KEY_RED_LOW :bit16; + KEY_RED_HIGH:bit16; + end; + + TLBV_V_COUNTER=bitpacked record + V_COUNTER:bit15; + RESERVED0:bit17; + end; + + TLCAC_CPL_CNTL=bitpacked record + CPL_ENABLE :bit1; + CPL_THRESHOLD:bit16; + CPL_BLOCK_ID :bit5; + CPL_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC0_CNTL=bitpacked record + MC0_ENABLE :bit1; + MC0_THRESHOLD:bit16; + MC0_BLOCK_ID :bit5; + MC0_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC1_CNTL=bitpacked record + MC1_ENABLE :bit1; + MC1_THRESHOLD:bit16; + MC1_BLOCK_ID :bit5; + MC1_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC2_CNTL=bitpacked record + MC2_ENABLE :bit1; + MC2_THRESHOLD:bit16; + MC2_BLOCK_ID :bit5; + MC2_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC3_CNTL=bitpacked record + MC3_ENABLE :bit1; + MC3_THRESHOLD:bit16; + MC3_BLOCK_ID :bit5; + MC3_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC4_CNTL=bitpacked record + MC4_ENABLE :bit1; + MC4_THRESHOLD:bit16; + MC4_BLOCK_ID :bit5; + MC4_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC5_CNTL=bitpacked record + MC5_ENABLE :bit1; + MC5_THRESHOLD:bit16; + MC5_BLOCK_ID :bit5; + MC5_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC6_CNTL=bitpacked record + MC6_ENABLE :bit1; + MC6_THRESHOLD:bit16; + MC6_BLOCK_ID :bit5; + MC6_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLCAC_MC7_CNTL=bitpacked record + MC7_ENABLE :bit1; + MC7_THRESHOLD:bit16; + MC7_BLOCK_ID :bit5; + MC7_SIGNAL_ID:bit8; + RESERVED0 :bit2; + end; + + TLM_LANEENABLE=bitpacked record + LANE_enable:bit16; + RESERVED0 :bit16; + end; + + TLM_PCIERXMUX0=bitpacked record + RXLANE0:bit8; + RXLANE1:bit8; + RXLANE2:bit8; + RXLANE3:bit8; + end; + + TLM_PCIERXMUX1=bitpacked record + RXLANE4:bit8; + RXLANE5:bit8; + RXLANE6:bit8; + RXLANE7:bit8; + end; + + TLM_PCIERXMUX2=bitpacked record + RXLANE8 :bit8; + RXLANE9 :bit8; + RXLANE10:bit8; + RXLANE11:bit8; + end; + + TLM_PCIERXMUX3=bitpacked record + RXLANE12:bit8; + RXLANE13:bit8; + RXLANE14:bit8; + RXLANE15:bit8; + end; + + TLM_PCIETXMUX0=bitpacked record + TXLANE0:bit8; + TXLANE1:bit8; + TXLANE2:bit8; + TXLANE3:bit8; + end; + + TLM_PCIETXMUX1=bitpacked record + TXLANE4:bit8; + TXLANE5:bit8; + TXLANE6:bit8; + TXLANE7:bit8; + end; + + TLM_PCIETXMUX2=bitpacked record + TXLANE8 :bit8; + TXLANE9 :bit8; + TXLANE10:bit8; + TXLANE11:bit8; + end; + + TLM_PCIETXMUX3=bitpacked record + TXLANE12:bit8; + TXLANE13:bit8; + TXLANE14:bit8; + TXLANE15:bit8; + end; + + TLNCNT_CONTROL=bitpacked record + CFG_LNC_WINDOW_EN0 :bit1; + CFG_LNC_BW_CNT_EN1 :bit1; + CFG_LNC_CMN_CNT_EN2:bit1; + CFG_LNC_OVRD_EN3 :bit1; + CFG_LNC_OVRD_VAL4 :bit1; + RESERVED0 :bit27; + end; + + TMAILBOX_INDEX=bitpacked record + MAILBOX_INDEX:bit4; + RESERVED0 :bit28; + end; + + TMAJOR_VERSION=bitpacked record + MAJOR_VERSION:bit8; + RESERVED0 :bit24; + end; + + TMC_ARB_AGE_RD=bitpacked record + RATE_GROUP0 :bit2; + RATE_GROUP1 :bit2; + RATE_GROUP2 :bit2; + RATE_GROUP3 :bit2; + RATE_GROUP4 :bit2; + RATE_GROUP5 :bit2; + RATE_GROUP6 :bit2; + RATE_GROUP7 :bit2; + ENABLE_GROUP0:bit1; + ENABLE_GROUP1:bit1; + ENABLE_GROUP2:bit1; + ENABLE_GROUP3:bit1; + ENABLE_GROUP4:bit1; + ENABLE_GROUP5:bit1; + ENABLE_GROUP6:bit1; + ENABLE_GROUP7:bit1; + DIVIDE_GROUP0:bit1; + DIVIDE_GROUP1:bit1; + DIVIDE_GROUP2:bit1; + DIVIDE_GROUP3:bit1; + DIVIDE_GROUP4:bit1; + DIVIDE_GROUP5:bit1; + DIVIDE_GROUP6:bit1; + DIVIDE_GROUP7:bit1; + end; + + TMC_ARB_AGE_WR=bitpacked record + RATE_GROUP0 :bit2; + RATE_GROUP1 :bit2; + RATE_GROUP2 :bit2; + RATE_GROUP3 :bit2; + RATE_GROUP4 :bit2; + RATE_GROUP5 :bit2; + RATE_GROUP6 :bit2; + RATE_GROUP7 :bit2; + ENABLE_GROUP0:bit1; + ENABLE_GROUP1:bit1; + ENABLE_GROUP2:bit1; + ENABLE_GROUP3:bit1; + ENABLE_GROUP4:bit1; + ENABLE_GROUP5:bit1; + ENABLE_GROUP6:bit1; + ENABLE_GROUP7:bit1; + DIVIDE_GROUP0:bit1; + DIVIDE_GROUP1:bit1; + DIVIDE_GROUP2:bit1; + DIVIDE_GROUP3:bit1; + DIVIDE_GROUP4:bit1; + DIVIDE_GROUP5:bit1; + DIVIDE_GROUP6:bit1; + DIVIDE_GROUP7:bit1; + end; + + TMC_ARB_ATOMIC=bitpacked record + TC_GRP :bit3; + TC_GRP_EN :bit1; + SDMA_GRP :bit3; + SDMA_GRP_EN :bit1; + OUTSTANDING :bit8; + ATOMIC_RTN_GRP:bit8; + RESERVED0 :bit8; + end; + + TMC_ARB_RAMCFG=bitpacked record + NOOFBANK :bit2; + NOOFRANKS :bit1; + NOOFROWS :bit3; + NOOFCOLS :bit2; + CHANSIZE :bit1; + RSV_1 :bit1; + RSV_2 :bit1; + RSV_3 :bit1; + NOOFGROUPS:bit1; + RSV_4 :bit5; + RESERVED0 :bit14; + end; + + TMC_ARB_REMREQ=bitpacked record + RD_WATER :bit8; + WR_WATER :bit8; + WR_MAXBURST_SIZE :bit4; + WR_LAZY_TIMER :bit4; + ENABLE_REMOTE_NACK_REQ:bit1; + RESERVED0 :bit7; + end; + + TMC_ARB_REPLAY=bitpacked record + ENABLE_RD :bit1; + ENABLE_WR :bit1; + WRACK_MODE :bit1; + WAW_ENABLE :bit1; + RAW_ENABLE :bit1; + IGNORE_WR_CDC :bit1; + BREAK_ON_STALL :bit1; + BOS_ENABLE_WAIT_CYC :bit1; + BOS_WAIT_CYC :bit7; + NO_PCH_AT_REPLAY_START:bit1; + RESERVED0 :bit16; + end; + + TMC_CONFIG_MCD=bitpacked record + MCD0_WR_ENABLE :bit1; + MCD1_WR_ENABLE :bit1; + MCD2_WR_ENABLE :bit1; + MCD3_WR_ENABLE :bit1; + MCD4_WR_ENABLE :bit1; + MCD5_WR_ENABLE :bit1; + MCD6_WR_ENABLE :bit1; + MCD7_WR_ENABLE :bit1; + MC_RD_ENABLE :bit3; + MC_RD_ENABLE_SUB :bit1; + ARB0_WR_ENABLE :bit1; + ARB1_WR_ENABLE :bit1; + RESERVED0 :bit17; + MCD_INDEX_MODE_ENABLE:bit1; + end; + + TMC_HUB_WDP_BP=bitpacked record + ENABLE :bit1; + RDRET :bit17; + WRREQ :bit12; + RESERVED0:bit2; + end; + + TMC_HUB_WDP_CP=bitpacked record + RESERVED0:bit1; + RESERVED1:bit2; + RESERVED2:bit1; + RESERVED3:bit2; + RESERVED4:bit1; + RESERVED5:bit4; + RESERVED6:bit4; + RESERVED7:bit1; + RESERVED8:bit16; + end; + + TMC_HUB_WDP_IH=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_RD_GRP_EXT=bitpacked record + DBSTEN0 :bit4; + TC0 :bit4; + RESERVED0:bit24; + end; + + TMC_RD_GRP_GFX=bitpacked record + CP :bit4; + SH :bit4; + IA :bit4; + ACPG :bit4; + ACPO :bit4; + ISP :bit4; + VP8 :bit4; + XDMAM:bit4; + end; + + TMC_RD_GRP_LCL=bitpacked record + RESERVED0:bit12; + CB0 :bit4; + CBCMASK0 :bit4; + CBFMASK0 :bit4; + DB0 :bit4; + DBHTILE0 :bit4; + end; + + TMC_RD_GRP_OTH=bitpacked record + UVD_EXT0:bit4; + SDMA0 :bit4; + HDP :bit4; + SEM :bit4; + UMC :bit4; + UVD :bit4; + UVD_EXT1:bit4; + SAMMSP :bit4; + end; + + TMC_RD_GRP_SYS=bitpacked record + RLC :bit4; + VMC :bit4; + SDMA1:bit4; + DMIF :bit4; + MCIF :bit4; + SMU :bit4; + VCE :bit4; + VCEU :bit4; + end; + + TMC_SEQ_CNTL_2=bitpacked record + RESERVED0 :bit3; + RESERVED1 :bit3; + RESERVED2 :bit3; + RESERVED3 :bit3; + RESERVED4 :bit3; + RESERVED5 :bit3; + RESERVED6 :bit3; + RESERVED7 :bit3; + RESERVED8 :bit3; + RESERVED9 :bit3; + RESERVED10:bit2; + end; + + TMC_SEQ_CNTL_3=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit4; + RESERVED9 :bit3; + RESERVED10:bit1; + RESERVED11:bit8; + RESERVED12:bit4; + RESERVED13:bit1; + RESERVED14:bit3; + end; + + TMC_SEQ_DRAM_2=bitpacked record + RESERVED0:bit2; + PCH_BNK :bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit1; + WDAT_EDC :bit1; + RDAT_EDC :bit1; + RESERVED6:bit4; + DLL_EST :bit1; + RESERVED7:bit1; + RESERVED8:bit8; + RESERVED9:bit8; + end; + + TMC_VM_AGP_BOT=bitpacked record + AGP_BOT :bit18; + RESERVED0:bit14; + end; + + TMC_VM_AGP_TOP=bitpacked record + AGP_TOP :bit18; + RESERVED0:bit14; + end; + + TMC_WR_GRP_EXT=bitpacked record + DBSTEN0 :bit4; + TC0 :bit4; + RESERVED0:bit24; + end; + + TMC_WR_GRP_GFX=bitpacked record + CP :bit4; + SH :bit4; + ACPG :bit4; + ACPO :bit4; + ISP :bit4; + VP8 :bit4; + XDMA :bit4; + XDMAM:bit4; + end; + + TMC_WR_GRP_LCL=bitpacked record + CB0 :bit4; + CBCMASK0 :bit4; + CBFMASK0 :bit4; + DB0 :bit4; + DBHTILE0 :bit4; + SX0 :bit4; + RESERVED0:bit4; + CBIMMED0 :bit4; + end; + + TMC_WR_GRP_OTH=bitpacked record + UVD_EXT0:bit4; + SDMA0 :bit4; + HDP :bit4; + SEM :bit4; + UMC :bit4; + UVD :bit4; + XDP :bit4; + UVD_EXT1:bit4; + end; + + TMC_WR_GRP_SYS=bitpacked record + IH :bit4; + MCIF :bit4; + RLC :bit4; + SAMMSP:bit4; + SMU :bit4; + SDMA1 :bit4; + VCE :bit4; + VCEU :bit4; + end; + + TMC_XPB_STICKY=bit32; + + TMEM_TYPE_CNTL=bitpacked record + BF_MEM_PHY_G5_G3:bit1; + RESERVED0 :bit31; + end; + + TMINOR_VERSION=bitpacked record + MINOR_VERSION:bit8; + RESERVED0 :bit24; + end; + + TMISC_CLK_CTRL=bitpacked record + DEEP_SLEEP_CLK_SEL:bit8; + ZCLK_SEL :bit8; + DFT_SMS_PG_CLK_SEL:bit8; + RESERVED0 :bit8; + end; + + TOVL_SWAP_CNTL=bitpacked record + OVL_ENDIAN_SWAP :bit2; + RESERVED0 :bit2; + OVL_RED_CROSSBAR :bit2; + OVL_GREEN_CROSSBAR:bit2; + OVL_BLUE_CROSSBAR :bit2; + OVL_ALPHA_CROSSBAR:bit2; + RESERVED1 :bit20; + end; + TPA_CL_ENHANCE=bitpacked record CLIP_VTX_REORDER_ENA :bit1; NUM_CLIP_SEQ :bit2; @@ -1774,6 +11194,775 @@ type ECO_SPARE0 :bit1; end; + TPCIEP_SCRATCH=bit32; + + TPCIE_ACS_CNTL=bitpacked record + SOURCE_VALIDATION_EN :bit1; + TRANSLATION_BLOCKING_EN :bit1; + P2P_REQUEST_REDIRECT_EN :bit1; + P2P_COMPLETION_REDIRECT_EN:bit1; + UPSTREAM_FORWARDING_EN :bit1; + P2P_EGRESS_CONTROL_EN :bit1; + DIRECT_TRANSLATED_P2P_EN :bit1; + RESERVED0 :bit25; + end; + + TPCIE_ARI_CNTL=bitpacked record + ARI_MFVC_FUNC_GROUPS_EN:bit1; + ARI_ACS_FUNC_GROUPS_EN :bit1; + RESERVED0 :bit2; + ARI_FUNCTION_GROUP :bit3; + RESERVED1 :bit25; + end; + + TPCIE_ATS_CNTL=bitpacked record + STU :bit5; + RESERVED0 :bit10; + ATC_ENABLE:bit1; + RESERVED1 :bit16; + end; + + TPCIE_BAR1_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BAR2_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BAR3_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BAR4_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BAR5_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BAR6_CAP=bitpacked record + RESERVED0 :bit4; + BAR_SIZE_SUPPORTED:bit20; + RESERVED1 :bit8; + end; + + TPCIE_BUS_CNTL=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit5; + PMI_INT_DIS :bit1; + IMMEDIATE_PMI_DIS:bit1; + RESERVED2 :bit4; + TRUE_PM_STATUS_EN:bit1; + RESERVED3 :bit19; + end; + + TPCIE_CAP_LIST=bitpacked record + CAP_ID :bit8; + NEXT_PTR :bit8; + RESERVED0:bit16; + end; + + TPCIE_CFG_CNTL=bitpacked record + CFG_EN_DEC_TO_HIDDEN_REG :bit1; + CFG_EN_DEC_TO_GEN2_HIDDEN_REG:bit1; + CFG_EN_DEC_TO_GEN3_HIDDEN_REG:bit1; + RESERVED0 :bit29; + end; + + TPCIE_DPA_CNTL=bitpacked record + SUBSTATE_CNTL:bit5; + RESERVED0 :bit27; + end; + + TPCIE_ERR_CNTL=bitpacked record + ERR_REPORTING_DIS :bit1; + STRAP_FIRST_RCVD_ERR_LOG :bit1; + RX_DROP_ECRC_FAILURES :bit1; + RESERVED0 :bit1; + TX_GENERATE_LCRC_ERR :bit1; + RX_GENERATE_LCRC_ERR :bit1; + TX_GENERATE_ECRC_ERR :bit1; + RX_GENERATE_ECRC_ERR :bit1; + AER_HDR_LOG_TIMEOUT :bit3; + AER_HDR_LOG_F0_TIMER_EXPIRED :bit1; + AER_HDR_LOG_F1_TIMER_EXPIRED :bit1; + AER_HDR_LOG_F2_TIMER_EXPIRED :bit1; + CI_P_SLV_BUF_RD_HALT_STATUS :bit1; + CI_NP_SLV_BUF_RD_HALT_STATUS :bit1; + CI_SLV_BUF_HALT_RESET :bit1; + SEND_ERR_MSG_IMMEDIATELY :bit1; + STRAP_POISONED_ADVISORY_NONFATAL:bit1; + RESERVED1 :bit13; + end; + + TPCIE_HDR_LOG0=bit32; + + TPCIE_HDR_LOG1=bit32; + + TPCIE_HDR_LOG2=bit32; + + TPCIE_HDR_LOG3=bit32; + + TPCIE_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + RESERVED0 :bit16; + end; + + TPCIE_INT_CNTL=bitpacked record + CORR_ERR_INT_EN :bit1; + NON_FATAL_ERR_INT_EN :bit1; + FATAL_ERR_INT_EN :bit1; + USR_DETECTED_INT_EN :bit1; + MISC_ERR_INT_EN :bit1; + RESERVED0 :bit1; + POWER_STATE_CHG_INT_EN:bit1; + LINK_BW_INT_EN :bit1; + QUIESCE_RCVD_INT_EN :bit1; + RESERVED1 :bit23; + end; + + TPCIE_LC_CNTL2=bitpacked record + LC_TIMED_OUT_STATE :bit6; + LC_STATE_TIMED_OUT :bit1; + LC_LOOK_FOR_BW_REDUCTION :bit1; + LC_MORE_TS2_EN :bit1; + LC_X12_NEGOTIATION_DIS :bit1; + LC_LINK_UP_REVERSAL_EN :bit1; + LC_ILLEGAL_STATE :bit1; + LC_ILLEGAL_STATE_RESTART_EN :bit1; + LC_WAIT_FOR_OTHER_LANES_MODE :bit1; + LC_ELEC_IDLE_MODE :bit2; + LC_DISABLE_INFERRED_ELEC_IDLE_DET :bit1; + LC_ALLOW_PDWN_IN_L1 :bit1; + LC_ALLOW_PDWN_IN_L23 :bit1; + LC_DEASSERT_RX_EN_IN_L0S :bit1; + LC_BLOCK_EL_IDLE_IN_L0 :bit1; + LC_RCV_L0_TO_RCV_L0S_DIS :bit1; + LC_ASSERT_INACTIVE_DURING_HOLD :bit1; + LC_WAIT_FOR_LANES_IN_LW_NEG :bit2; + LC_PWR_DOWN_NEG_OFF_LANES :bit1; + LC_DISABLE_LOST_SYM_LOCK_ARCS :bit1; + LC_LINK_BW_NOTIFICATION_DIS :bit1; + LC_PMI_L1_WAIT_FOR_SLV_IDLE :bit1; + LC_TEST_TIMER_SEL :bit2; + LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI:bit1; + end; + + TPCIE_LC_CNTL3=bitpacked record + LC_SELECT_DEEMPHASIS :bit1; + LC_SELECT_DEEMPHASIS_CNTL :bit2; + LC_RCVD_DEEMPHASIS :bit1; + LC_COMP_TO_DETECT :bit1; + LC_RESET_TSX_CNT_IN_RLOCK_EN :bit1; + LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED :bit2; + LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED :bit1; + LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT :bit1; + LC_ENHANCED_HOT_PLUG_EN :bit1; + LC_RCVR_DET_EN_OVERRIDE :bit1; + LC_EHP_RX_PHY_CMD :bit2; + LC_EHP_TX_PHY_CMD :bit2; + LC_CHIP_BIF_USB_IDLE_EN :bit1; + LC_L1_BLOCK_RECONFIG_EN :bit1; + LC_AUTO_DISABLE_SPEED_SUPPORT_EN :bit1; + LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL:bit2; + LC_FAST_L1_ENTRY_EXIT_EN :bit1; + LC_RXPHYCMD_INACTIVE_EN_MODE :bit1; + LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK :bit1; + LC_HW_VOLTAGE_IF_CONTROL :bit2; + LC_VOLTAGE_TIMER_SEL :bit4; + LC_GO_TO_RECOVERY :bit1; + LC_N_EIE_SEL :bit1; + end; + + TPCIE_LC_CNTL4=bitpacked record + LC_TX_ENABLE_BEHAVIOUR :bit2; + LC_DIS_CONTIG_END_SET_CHECK :bit1; + LC_DIS_ASPM_L1_IN_SPEED_CHANGE :bit1; + LC_BYPASS_EQ :bit1; + LC_REDO_EQ :bit1; + LC_EXTEND_EIEOS :bit1; + LC_IGNORE_PARITY :bit1; + LC_EQ_SEARCH_MODE :bit2; + LC_DSC_CHECK_COEFFS_IN_RLOCK :bit1; + LC_USC_EQ_NOT_REQD :bit1; + LC_USC_GO_TO_EQ :bit1; + LC_SET_QUIESCE :bit1; + LC_QUIESCE_RCVD :bit1; + LC_UNEXPECTED_COEFFS_RCVD :bit1; + LC_BYPASS_EQ_REQ_PHASE :bit1; + LC_FORCE_PRESET_IN_EQ_REQ_PHASE:bit1; + LC_FORCE_PRESET_VALUE :bit4; + LC_USC_DELAY_DLLPS :bit1; + LC_PCIE_TX_FULL_SWING :bit1; + LC_EQ_WAIT_FOR_EVAL_DONE :bit1; + LC_8GT_SKIP_ORDER_EN :bit1; + LC_WAIT_FOR_MORE_TS_IN_RLOCK :bit6; + end; + + TPCIE_LC_CNTL5=bitpacked record + LC_EQ_FS_0 :bit6; + LC_EQ_FS_8 :bit6; + LC_EQ_LF_0 :bit6; + LC_EQ_LF_8 :bit6; + LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS:bit1; + RESERVED0 :bit7; + end; + + TPCIE_LC_CNTL6=bitpacked record + LC_SPC_MODE_2P5GT:bit1; + RESERVED0 :bit1; + LC_SPC_MODE_5GT :bit1; + RESERVED1 :bit1; + LC_SPC_MODE_8GT :bit1; + RESERVED2 :bit27; + end; + + TPCIE_MC_ADDR0=bitpacked record + MC_INDEX_POS :bit6; + RESERVED0 :bit6; + MC_BASE_ADDR_0:bit20; + end; + + TPCIE_MC_ADDR1=bit32; + + TPCIE_PRBS_CLR=bitpacked record + PRBS_CLR :bit16; + PRBS_CHECKER_DEBUG_BUS_SELECT:bit4; + RESERVED0 :bit12; + end; + + TPCIE_RESERVED=bit32; + + TPCIE_RX_CNTL2=bitpacked record + RX_IGNORE_EP_INVALIDPASID_UR:bit1; + RX_IGNORE_EP_TRANSMRD_UR :bit1; + RX_IGNORE_EP_TRANSMWR_UR :bit1; + RX_IGNORE_EP_ATSTRANSREQ_UR :bit1; + RX_IGNORE_EP_PAGEREQMSG_UR :bit1; + RX_IGNORE_EP_INVCPL_UR :bit1; + RESERVED0 :bit2; + RX_RCB_LATENCY_EN :bit1; + RX_RCB_LATENCY_SCALE :bit3; + RESERVED1 :bit4; + RX_RCB_LATENCY_MAX_COUNT :bit10; + RESERVED2 :bit2; + FLR_EXTEND_MODE :bit3; + RESERVED3 :bit1; + end; + + TPCIE_RX_CNTL3=bitpacked record + RX_IGNORE_RC_TRANSMRDPASID_UR:bit1; + RX_IGNORE_RC_TRANSMWRPASID_UR:bit1; + RX_IGNORE_RC_PRGRESPMSG_UR :bit1; + RX_IGNORE_RC_INVREQ_UR :bit1; + RX_IGNORE_RC_INVCPLPASID_UR :bit1; + RESERVED0 :bit27; + end; + + TPCIE_STRAP_F0=bitpacked record + STRAP_F0_EN :bit1; + STRAP_F0_LEGACY_DEVICE_TYPE_EN :bit1; + STRAP_F0_MSI_EN :bit1; + STRAP_F0_VC_EN :bit1; + STRAP_F0_DSN_EN :bit1; + STRAP_F0_AER_EN :bit1; + STRAP_F0_ACS_EN :bit1; + STRAP_F0_BAR_EN :bit1; + STRAP_F0_PWR_EN :bit1; + STRAP_F0_DPA_EN :bit1; + STRAP_F0_ATS_EN :bit1; + STRAP_F0_PAGE_REQ_EN :bit1; + STRAP_F0_PASID_EN :bit1; + STRAP_F0_ECRC_CHECK_EN :bit1; + STRAP_F0_ECRC_GEN_EN :bit1; + STRAP_F0_CPL_ABORT_ERR_EN :bit1; + STRAP_F0_POISONED_ADVISORY_NONFATAL:bit1; + STRAP_F0_MC_EN :bit1; + STRAP_F0_ATOMIC_EN :bit1; + STRAP_F0_ATOMIC_64BIT_EN :bit1; + STRAP_F0_ATOMIC_ROUTING_EN :bit1; + STRAP_F0_MSI_MULTI_CAP :bit3; + STRAP_F0_VFn_MSI_MULTI_CAP :bit3; + STRAP_F0_MSI_PERVECTOR_MASK_CAP :bit1; + STRAP_F0_NO_RO_ENABLED_P2P_PASSING :bit1; + STRAP_F0_ARI_EN :bit1; + STRAP_F0_SRIOV_EN :bit1; + RESERVED0 :bit1; + end; + + TPCIE_STRAP_F1=bitpacked record + STRAP_F1_EN :bit1; + STRAP_F1_LEGACY_DEVICE_TYPE_EN :bit1; + STRAP_F1_MSI_EN :bit1; + STRAP_F1_VC_EN :bit1; + STRAP_F1_DSN_EN :bit1; + STRAP_F1_AER_EN :bit1; + STRAP_F1_ACS_EN :bit1; + STRAP_F1_BAR_EN :bit1; + STRAP_F1_PWR_EN :bit1; + STRAP_F1_DPA_EN :bit1; + STRAP_F1_ATS_EN :bit1; + STRAP_F1_PAGE_REQ_EN :bit1; + STRAP_F1_PASID_EN :bit1; + STRAP_F1_ECRC_CHECK_EN :bit1; + STRAP_F1_ECRC_GEN_EN :bit1; + STRAP_F1_CPL_ABORT_ERR_EN :bit1; + STRAP_F1_POISONED_ADVISORY_NONFATAL:bit1; + RESERVED0 :bit1; + STRAP_F1_ATOMIC_EN :bit1; + STRAP_F1_ATOMIC_64BIT_EN :bit1; + STRAP_F1_ATOMIC_ROUTING_EN :bit1; + STRAP_F1_MSI_MULTI_CAP :bit3; + RESERVED1 :bit3; + STRAP_F1_MSI_PERVECTOR_MASK_CAP :bit1; + RESERVED2 :bit4; + end; + + TPCIE_STRAP_F2=bitpacked record + STRAP_F2_EN :bit1; + STRAP_F2_LEGACY_DEVICE_TYPE_EN :bit1; + STRAP_F2_MSI_EN :bit1; + STRAP_F2_VC_EN :bit1; + STRAP_F2_DSN_EN :bit1; + STRAP_F2_AER_EN :bit1; + STRAP_F2_ACS_EN :bit1; + STRAP_F2_BAR_EN :bit1; + STRAP_F2_PWR_EN :bit1; + STRAP_F2_DPA_EN :bit1; + STRAP_F2_ATS_EN :bit1; + STRAP_F2_PAGE_REQ_EN :bit1; + STRAP_F2_PASID_EN :bit1; + STRAP_F2_ECRC_CHECK_EN :bit1; + STRAP_F2_ECRC_GEN_EN :bit1; + STRAP_F2_CPL_ABORT_ERR_EN :bit1; + STRAP_F2_POISONED_ADVISORY_NONFATAL:bit1; + RESERVED0 :bit1; + STRAP_F2_ATOMIC_EN :bit1; + STRAP_F2_ATOMIC_64BIT_EN :bit1; + STRAP_F2_ATOMIC_ROUTING_EN :bit1; + STRAP_F2_MSI_MULTI_CAP :bit3; + RESERVED1 :bit3; + STRAP_F2_MSI_PERVECTOR_MASK_CAP :bit1; + RESERVED2 :bit4; + end; + + TPCIE_STRAP_F3=bit32; + + TPCIE_STRAP_F4=bit32; + + TPCIE_STRAP_F5=bit32; + + TPCIE_STRAP_F6=bit32; + + TPCIE_STRAP_F7=bit32; + + TPCIE_STRAP_PI=bitpacked record + STRAP_QUICKSIM_START :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit4; + RESERVED3 :bit4; + RESERVED4 :bit2; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit2; + RESERVED8 :bit1; + RESERVED9 :bit2; + RESERVED10 :bit1; + RESERVED11 :bit4; + RESERVED12 :bit1; + RESERVED13 :bit2; + STRAP_TEST_TOGGLE_PATTERN:bit1; + STRAP_TEST_TOGGLE_MODE :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + end; + + TPCIE_WPR_CNTL=bitpacked record + WPR_RESET_HOT_RST_EN:bit1; + WPR_RESET_LNK_DWN_EN:bit1; + WPR_RESET_LNK_DIS_EN:bit1; + WPR_RESET_COR_EN :bit1; + WPR_RESET_REG_EN :bit1; + WPR_RESET_STY_EN :bit1; + WPR_RESET_PHY_EN :bit1; + RESERVED0 :bit25; + end; + + TPERFMON_CNTL2=bitpacked record + PERFMON_CNTOFF_INT_TYPE:bit1; + RESERVED0 :bit31; + end; + + TPLL_TEST_CNTL=bitpacked record + TST_SRC_SEL :bit4; + TST_REF_SEL :bit4; + REF_TEST_COUNT:bit7; + TST_RESET :bit1; + RESERVED0 :bit1; + TEST_COUNT :bit15; + end; + + TPLL_VREG_CNTL=bitpacked record + PLL_VREG_CNTL :bit20; + PLL_BG_VREG_BIAS:bit2; + RESERVED0 :bit4; + PLL_VREF_SEL :bit1; + RESERVED1 :bit1; + PLL_VREG_BIAS :bit4; + end; + + TPWR_AVFS_CNTL=bitpacked record + MmBusIn :bit8; + MmLclRdEn :bit1; + MmLclWrEn :bit1; + MmLclSz :bit2; + MmState :bit6; + PsmScanMode :bit1; + PsmGater :bit1; + PsmTrst :bit1; + PsmEn :bit1; + SkipPhaseEn :bit1; + Isolate :bit1; + AvfsRst :bit1; + PccIsolateEn :bit1; + DeepSleepIsolateEn:bit1; + RESERVED0 :bit5; + end; + + TRBBMIF_STATUS=bitpacked record + RBBMIF_TIMEOUT_CLIENTS_DEC:bit15; + RESERVED0 :bit13; + RBBMIF_TIMEOUT_OP :bit1; + RBBMIF_TIMEOUT_RDWR_STATUS:bit1; + RBBMIF_TIMEOUT_ACK :bit1; + RBBMIF_TIMEOUT_MASK :bit1; + end; + + TRCU_MISC_CTRL=bitpacked record + RESERVED0 :bit1; + REG_DRV_RST_MODE :bit1; + RESERVED1 :bit1; + REG_RCU_MEMREP_DIS :bit1; + REG_CC_FUSE_DISABLE :bit1; + REG_SAMU_FUSE_DISABLE :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + REG_CC_SRBM_RD_DISABLE:bit1; + RESERVED4 :bit7; + BREAK_PT1_DONE :bit1; + BREAK_PT2_DONE :bit1; + RESERVED5 :bit3; + RESERVED6 :bit1; + SAMU_START :bit1; + RST_PULSE_WIDTH :bit9; + end; + + TRCU_UC_EVENTS=bitpacked record + RCU_TST_jpc_rep_req :bit1; + TST_RCU_jpc_rep_done :bit1; + drv_rst_mode :bit1; + SMU_DC_efuse_status_invalid:bit1; + RESERVED0 :bit2; + TP_Tester :bit1; + boot_seq_done :bit1; + sclk_deep_sleep_exit :bit1; + BREAK_PT1_ACTIVE :bit1; + BREAK_PT2_ACTIVE :bit1; + FCH_HALT :bit1; + RESERVED1 :bit1; + RCU_GIO_fch_lockdown :bit1; + RESERVED2 :bit2; + INTERRUPTS_ENABLED :bit1; + RCU_DtmCnt0_Done :bit1; + RCU_DtmCnt1_Done :bit1; + RCU_DtmCnt2_Done :bit1; + RESERVED3 :bit4; + RESERVED4 :bit2; + RESERVED5 :bit6; + end; + + TRLC_CU_STATUS=bit32; + + TRLC_GPM_DEBUG=bit32; + + TRLC_LB_PARAMS=bitpacked record + SKIP_L2_CHECK :bit1; + FIFO_SAMPLES :bit7; + PG_IDLE_SAMPLES :bit8; + PG_IDLE_SAMPLE_INTERVAL:bit16; + end; + + TRLC_MAX_PG_CU=bitpacked record + MAX_POWERED_UP_CU:bit8; + SPARE :bit24; + end; + + TRLC_MGCG_CTRL=bitpacked record + MGCG_EN :bit1; + SILICON_EN :bit1; + SIMULATION_EN :bit1; + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + GC_CAC_MGCG_CLK_CNTL:bit1; + SE_CAC_MGCG_CLK_CNTL:bit1; + SPARE :bit15; + end; + + TRLC_SAFE_MODE=bitpacked record + CMD :bit1; + MESSAGE :bit4; + RESERVED1:bit3; + RESPONSE :bit4; + RESERVED :bit20; + end; + + TRLC_SPM_DEBUG=bit32; + + TRLC_SRM_DEBUG=bit32; + + TROM_BASE_ADDR=bit32; + + TROM_SW_DATA_1=bit32; + + TROM_SW_DATA_2=bit32; + + TROM_SW_DATA_3=bit32; + + TROM_SW_DATA_4=bit32; + + TROM_SW_DATA_5=bit32; + + TROM_SW_DATA_6=bit32; + + TROM_SW_DATA_7=bit32; + + TROM_SW_DATA_8=bit32; + + TROM_SW_DATA_9=bit32; + + TROM_SW_STATUS=bitpacked record + ROM_SW_DONE:bit1; + RESERVED0 :bit31; + end; + + TSDMA0_PROGRAM=bit32; + + TSDMA0_VERSION=bitpacked record + VALUE :bit16; + RESERVED0:bit16; + end; + + TSDMA0_VM_CNTL=bitpacked record + CMD :bit4; + RESERVED0:bit28; + end; + + TSDMA1_PROGRAM=bit32; + + TSDMA1_VERSION=bitpacked record + VALUE :bit16; + RESERVED0:bit16; + end; + + TSDMA1_VM_CNTL=bitpacked record + CMD :bit4; + RESERVED0:bit28; + end; + + TSEM_VF_ENABLE=bitpacked record + VALUE :bit1; + RESERVED0:bit31; + end; + + TSH_MEM_CONFIG=bitpacked record + ADDRESS_MODE :bit2; + PRIVATE_ATC :bit1; + ALIGNMENT_MODE:bit2; + DEFAULT_MTYPE :bit3; + APE1_MTYPE :bit3; + APE1_ATC :bit1; + RESERVED0 :bit20; + end; + + TSMC_IND_INDEX=bit32; + + TSMC_MESSAGE_0=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_1=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_2=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_3=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_4=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_5=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_6=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_7=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_8=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_9=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MSG_ARG_0=bit32; + + TSMC_MSG_ARG_1=bit32; + + TSMC_MSG_ARG_2=bit32; + + TSMC_MSG_ARG_3=bit32; + + TSMC_MSG_ARG_4=bit32; + + TSMC_MSG_ARG_5=bit32; + + TSMC_MSG_ARG_6=bit32; + + TSMC_MSG_ARG_7=bit32; + + TSMC_MSG_ARG_8=bit32; + + TSMC_MSG_ARG_9=bit32; + + TSPMI_SPARE_EX=bit32; + + TSQC_WRITEBACK=bitpacked record + DWB :bit1; + DIRTY :bit1; + RESERVED0:bit30; + end; + + TSQ_FIFO_SIZES=bitpacked record + INTERRUPT_FIFO_SIZE:bit4; + RESERVED0 :bit4; + TTRACE_FIFO_SIZE :bit4; + RESERVED1 :bit4; + EXPORT_BUF_SIZE :bit2; + VMEM_DATA_FIFO_SIZE:bit2; + RESERVED2 :bit12; + end; + + TSQ_WAVE_HW_ID=bitpacked record + WAVE_ID :bit4; + SIMD_ID :bit2; + PIPE_ID :bit2; + CU_ID :bit4; + SH_ID :bit1; + SE_ID :bit2; + RESERVED0:bit1; + TG_ID :bit4; + VM_ID :bit4; + QUEUE_ID :bit3; + STATE_ID :bit3; + ME_ID :bit2; + end; + + TSQ_WAVE_PC_HI=bitpacked record + PC_HI :bit16; + RESERVED0:bit16; + end; + + TSQ_WAVE_PC_LO=bit32; + + TSQ_WAVE_TTMP0=bit32; + + TSQ_WAVE_TTMP1=bit32; + + TSQ_WAVE_TTMP2=bit32; + + TSQ_WAVE_TTMP3=bit32; + + TSQ_WAVE_TTMP4=bit32; + + TSQ_WAVE_TTMP5=bit32; + + TSQ_WAVE_TTMP6=bit32; + + TSQ_WAVE_TTMP7=bit32; + + TSQ_WAVE_TTMP8=bit32; + + TSQ_WAVE_TTMP9=bit32; + + TSRBM_CAM_DATA=bitpacked record + CAM_ADDR :bit16; + CAM_REMAPADDR:bit16; + end; + + TSRBM_GFX_CNTL=bitpacked record + PIPEID :bit2; + MEID :bit2; + VMID :bit4; + QUEUEID :bit3; + RESERVED0:bit21; + end; + + TSRBM_INT_CNTL=bitpacked record + RDERR_INT_MASK:bit1; + RAERR_INT_MASK:bit1; + RESERVED0 :bit30; + end; + TSX_DEBUG_BUSY=bitpacked record POS_FREE_OR_VALIDS:bit1; POS_REQUESTER_BUSY:bit1; @@ -1811,8 +12000,118 @@ type TTA_DEBUG_DATA=bit32; + TTDC_VRM_LIMIT=bitpacked record + IDD :bit16; + IDDC:bit16; + end; + TTD_DEBUG_DATA=bit32; + TTMDS_CTL_BITS=bitpacked record + TMDS_CTL0:bit1; + RESERVED0:bit7; + TMDS_CTL1:bit1; + RESERVED1:bit7; + TMDS_CTL2:bit1; + RESERVED2:bit7; + TMDS_CTL3:bit1; + RESERVED3:bit7; + end; + + TUVD_CGC_CTRL2=bitpacked record + DYN_OCLK_RAMP_EN:bit1; + DYN_RCLK_RAMP_EN:bit1; + GATER_DIV_ID :bit3; + RESERVED0 :bit27; + end; + + TUVD_CTX_INDEX=bitpacked record + INDEX :bit9; + RESERVED0:bit23; + end; + + TUVD_LMI_CTRL2=bitpacked record + SPH_DIS :bit1; + STALL_ARB :bit1; + ASSERT_UMC_URGENT :bit1; + MASK_UMC_URGENT :bit1; + MCIF_WR_WATERMARK :bit3; + DRCITF_BUBBLE_FIX_DIS :bit1; + STALL_ARB_UMC :bit1; + MC_READ_ID_SEL :bit2; + MC_WRITE_ID_SEL :bit2; + VCPU_NC0_EXT_EN :bit1; + VCPU_NC1_EXT_EN :bit1; + SPU_EXTRA_CID_EN :bit1; + RE_OFFLOAD_EN :bit1; + RE_OFLD_MIF_WR_REQ_NUM:bit8; + RESERVED0 :bit7; + end; + + TUVD_SEMA_CNTL=bitpacked record + SEMAPHORE_EN :bit1; + ADVANCED_MODE_DIS:bit1; + RESERVED0 :bit30; + end; + + TUVD_VCPU_CNTL=bitpacked record + IRQ_ERR :bit4; + AXI_MAX_BRST_SIZE_IS_4 :bit1; + PMB_ED_ENABLE :bit1; + PMB_SOFT_RESET :bit1; + RBBM_SOFT_RESET :bit1; + ABORT_REQ :bit1; + CLK_EN :bit1; + TRCE_EN :bit1; + TRCE_MUX :bit2; + DBG_MUX :bit3; + JTAG_EN :bit1; + MIF_WR_LOW_THRESHOLD_BP:bit1; + TIMEOUT_DIS :bit1; + SUVD_EN :bit1; + PRB_TIMEOUT_VAL :bit8; + CABAC_MB_ACC :bit1; + RESERVED0 :bit1; + WMV9_EN :bit1; + RE_OFFLOAD_EN :bit1; + end; + + TVBLANK_STATUS=bitpacked record + RESERVED0:bit1; + RESERVED1:bit3; + RESERVED2:bit1; + RESERVED3:bit7; + RESERVED4:bit1; + RESERVED5:bit3; + RESERVED6:bit1; + RESERVED7:bit1; + RESERVED8:bit14; + end; + + TVCE_LMI_CTRL2=bitpacked record + RESERVED0 :bit1; + STALL_ARB :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit3; + RESERVED4 :bit1; + STALL_ARB_UMC:bit1; + RESERVED5 :bit2; + RESERVED6 :bit21; + end; + + TVCE_VCPU_CNTL=bitpacked record + CLK_EN :bit1; + RESERVED0 :bit1; + RESERVED1 :bit14; + RESERVED2 :bit1; + RESERVED3 :bit1; + RBBM_SOFT_RESET:bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit11; + end; + TVGT_ES_PER_GS=bitpacked record ES_PER_GS:bit11; RESERVED0:bit21; @@ -1833,6 +12132,25 @@ type RESERVED0:bit31; end; + TVIEWPORT_SIZE=bitpacked record + VIEWPORT_HEIGHT:bit14; + RESERVED0 :bit2; + VIEWPORT_WIDTH :bit14; + RESERVED1 :bit2; + end; + + TWB_DEBUG_CTRL=bitpacked record + WB_DEBUG_EN :bit1; + RESERVED0 :bit5; + WB_DEBUG_SEL:bit2; + RESERVED1 :bit24; + end; + + TWB_SOFT_RESET=bitpacked record + WB_SOFT_RESET:bit1; + RESERVED0 :bit31; + end; + TWD_DEBUG_CNTL=bitpacked record WD_DEBUG_INDX :bit6; WD_DEBUG_SEL_BUS_B:bit1; @@ -2099,6 +12417,205 @@ type pipe4_rtr :bit1; end; + TXDMA_PG_WDATA=bit32; + + TXDMA_SLV_CNTL=bitpacked record + XDMA_SLV_READ_LINES :bit1; + RESERVED0 :bit8; + XDMA_SLV_MEM_READY :bit1; + XDMA_SLV_ACTIVE :bit1; + RESERVED1 :bit1; + XDMA_SLV_ALPHA_POSITION :bit2; + RESERVED2 :bit2; + XDMA_SLV_ENABLE :bit1; + RESERVED3 :bit2; + XDMA_SLV_READ_LAT_TEST_EN:bit1; + XDMA_SLV_SOFT_RESET :bit1; + RESERVED4 :bit3; + XDMA_SLV_REQ_MAXED_OUT :bit1; + XDMA_SLV_WB_BURST_RESET :bit1; + RESERVED5 :bit6; + end; + + TAFMT_AVI_INFO0=bitpacked record + AFMT_AVI_INFO_CHECKSUM:bit8; + AFMT_AVI_INFO_S :bit2; + AFMT_AVI_INFO_B :bit2; + AFMT_AVI_INFO_A :bit1; + AFMT_AVI_INFO_Y :bit2; + AFMT_AVI_INFO_PB1_RSVD:bit1; + AFMT_AVI_INFO_R :bit4; + AFMT_AVI_INFO_M :bit2; + AFMT_AVI_INFO_C :bit2; + AFMT_AVI_INFO_SC :bit2; + AFMT_AVI_INFO_Q :bit2; + AFMT_AVI_INFO_EC :bit3; + AFMT_AVI_INFO_ITC :bit1; + end; + + TAFMT_AVI_INFO1=bitpacked record + AFMT_AVI_INFO_VIC :bit7; + AFMT_AVI_INFO_PB4_RSVD:bit1; + AFMT_AVI_INFO_PR :bit4; + AFMT_AVI_INFO_CN :bit2; + AFMT_AVI_INFO_YQ :bit2; + AFMT_AVI_INFO_TOP :bit16; + end; + + TAFMT_AVI_INFO2=bitpacked record + AFMT_AVI_INFO_BOTTOM:bit16; + AFMT_AVI_INFO_LEFT :bit16; + end; + + TAFMT_AVI_INFO3=bitpacked record + AFMT_AVI_INFO_RIGHT :bit16; + RESERVED0 :bit8; + AFMT_AVI_INFO_VERSION:bit8; + end; + + TAFMT_GENERIC_0=bitpacked record + AFMT_GENERIC_BYTE0:bit8; + AFMT_GENERIC_BYTE1:bit8; + AFMT_GENERIC_BYTE2:bit8; + AFMT_GENERIC_BYTE3:bit8; + end; + + TAFMT_GENERIC_1=bitpacked record + AFMT_GENERIC_BYTE4:bit8; + AFMT_GENERIC_BYTE5:bit8; + AFMT_GENERIC_BYTE6:bit8; + AFMT_GENERIC_BYTE7:bit8; + end; + + TAFMT_GENERIC_2=bitpacked record + AFMT_GENERIC_BYTE8 :bit8; + AFMT_GENERIC_BYTE9 :bit8; + AFMT_GENERIC_BYTE10:bit8; + AFMT_GENERIC_BYTE11:bit8; + end; + + TAFMT_GENERIC_3=bitpacked record + AFMT_GENERIC_BYTE12:bit8; + AFMT_GENERIC_BYTE13:bit8; + AFMT_GENERIC_BYTE14:bit8; + AFMT_GENERIC_BYTE15:bit8; + end; + + TAFMT_GENERIC_4=bitpacked record + AFMT_GENERIC_BYTE16:bit8; + AFMT_GENERIC_BYTE17:bit8; + AFMT_GENERIC_BYTE18:bit8; + AFMT_GENERIC_BYTE19:bit8; + end; + + TAFMT_GENERIC_5=bitpacked record + AFMT_GENERIC_BYTE20:bit8; + AFMT_GENERIC_BYTE21:bit8; + AFMT_GENERIC_BYTE22:bit8; + AFMT_GENERIC_BYTE23:bit8; + end; + + TAFMT_GENERIC_6=bitpacked record + AFMT_GENERIC_BYTE24:bit8; + AFMT_GENERIC_BYTE25:bit8; + AFMT_GENERIC_BYTE26:bit8; + AFMT_GENERIC_BYTE27:bit8; + end; + + TAFMT_GENERIC_7=bitpacked record + AFMT_GENERIC_BYTE28:bit8; + AFMT_GENERIC_BYTE29:bit8; + AFMT_GENERIC_BYTE30:bit8; + AFMT_GENERIC_BYTE31:bit8; + end; + + TATC_ATS_STATUS=bitpacked record + BUSY :bit1; + CRASHED :bit1; + DEADLOCK_DETECTION:bit1; + RESERVED0 :bit29; + end; + + TATC_L2_STATUS2=bitpacked record + CACHE_ADDRESS_MODE:bit3; + PARITY_ERROR_INFO :bit8; + RESERVED0 :bit21; + end; + + TAUX_SW_CONTROL=bitpacked record + AUX_SW_GO :bit1; + RESERVED0 :bit1; + AUX_LS_READ_TRIG :bit1; + RESERVED1 :bit1; + AUX_SW_START_DELAY:bit4; + RESERVED2 :bit8; + AUX_SW_WR_BYTES :bit5; + RESERVED3 :bit11; + end; + + TBACO_CNTL_MISC=bitpacked record + BIF_ROM_REQ_DIS :bit1; + BIF_AZ_REQ_DIS :bit1; + BACO_LINK_RST_WIDTH_SEL:bit2; + BACO_REFCLK_SEL :bit1; + RESERVED0 :bit27; + end; + + TBCI_DEBUG_READ=bitpacked record + DATA :bit24; + RESERVED0:bit8; + end; + + TBIF_BACO_DEBUG=bitpacked record + BIF_BACO_SCANDUMP_FLG:bit1; + RESERVED0 :bit31; + end; + + TBIF_BME_STATUS=bitpacked record + DMA_ON_BME_LOW :bit1; + RESERVED0 :bit15; + CLEAR_DMA_ON_BME_LOW:bit1; + RESERVED1 :bit15; + end; + + TBIF_DEBUG_CNTL=bitpacked record + DEBUG_EN :bit1; + DEBUG_MULTIBLOCKEN:bit1; + DEBUG_OUT_EN :bit1; + DEBUG_PAD_SEL :bit1; + DEBUG_BYTESEL_BLK1:bit1; + DEBUG_BYTESEL_BLK2:bit1; + DEBUG_SYNC_EN :bit1; + DEBUG_SWAP :bit1; + DEBUG_IDSEL_BLK1 :bit5; + RESERVED0 :bit3; + DEBUG_IDSEL_BLK2 :bit5; + RESERVED1 :bit3; + DEBUG_IDSEL_XSP :bit1; + RESERVED2 :bit5; + DEBUG_SYNC_CLKSEL :bit2; + end; + + TBIOS_SCRATCH_0=bit32; + + TBIOS_SCRATCH_1=bit32; + + TBIOS_SCRATCH_2=bit32; + + TBIOS_SCRATCH_3=bit32; + + TBIOS_SCRATCH_4=bit32; + + TBIOS_SCRATCH_5=bit32; + + TBIOS_SCRATCH_6=bit32; + + TBIOS_SCRATCH_7=bit32; + + TBIOS_SCRATCH_8=bit32; + + TBIOS_SCRATCH_9=bit32; + TCB_BLEND_ALPHA=bit32; TCB_BLEND_GREEN=bit32; @@ -2436,6 +12953,112 @@ type TARGET7_ENABLE:bit4; end; + TCC_DC_PIPE_DIS=bitpacked record + RESERVED0 :bit1; + DC_PIPE_DIS :bit6; + RESERVED1 :bit1; + MCIF_WB_URG_OVRD:bit1; + MCIF_WB_URG_LVL :bit4; + RESERVED2 :bit19; + end; + + TCC_FCTRL_FUSES=bitpacked record + RESERVED0 :bit1; + EXT_EFUSE_MACRO_PRESENT:bit1; + RESERVED1 :bit30; + end; + + TCC_THM_STRAPS0=bitpacked record + RESERVED0 :bit1; + TMON0_BGADJ :bit8; + TMON1_BGADJ :bit8; + TMON_CMON_FUSE_SEL:bit1; + NUM_ACQ :bit3; + TMON_CLK_SEL :bit3; + TMON_CONFIG_SOURCE:bit1; + CTF_DISABLE :bit1; + TMON0_DISABLE :bit1; + TMON1_DISABLE :bit1; + TMON2_DISABLE :bit1; + TMON3_DISABLE :bit1; + RESERVED1 :bit2; + end; + + TCFG_LNC_WINDOW=bitpacked record + CFG_LNC_WINDOW0:bit24; + RESERVED0 :bit8; + end; + + TCG_CLKPIN_CNTL=bitpacked record + RESERVED0 :bit1; + XTALIN_DIVIDE:bit1; + BCLK_AS_XCLK :bit1; + RESERVED1 :bit29; + end; + + TCG_DCLK_STATUS=bitpacked record + DCLK_STATUS :bit1; + DCLK_DIR_CNTL_DONETOG:bit1; + RESERVED0 :bit30; + end; + + TCG_ECLK_STATUS=bitpacked record + ECLK_STATUS :bit1; + ECLK_DIR_CNTL_DONETOG:bit1; + RESERVED0 :bit30; + end; + + TCG_MCLK_STATUS=bitpacked record + MCLK_STATUS :bit1; + MCLK_DIR_CNTL_DONETOG:bit1; + RESERVED0 :bit30; + end; + + TCG_TACH_STATUS=bit32; + + TCG_THERMAL_INT=bitpacked record + DIG_THERM_CTF :bit8; + DIG_THERM_INTH:bit8; + DIG_THERM_INTL:bit8; + THERM_INT_MASK:bit4; + RESERVED0 :bit2; + RESERVED1 :bit2; + end; + + TCG_VCLK_STATUS=bitpacked record + VCLK_STATUS :bit1; + VCLK_DIR_CNTL_DONETOG:bit1; + RESERVED0 :bit30; + end; + + TCLIENT0_OFFSET=bit32; + + TCLIENT0_STATUS=bit32; + + TCLIENT1_OFFSET=bit32; + + TCLIENT2_OFFSET=bit32; + + TCLIENT2_STATUS=bit32; + + TCLIENT3_OFFSET=bit32; + + TCLIENT3_STATUS=bit32; + + TCLIENT4_OFFSET=bit32; + + TCLIENT4_STATUS=bit32; + + TCOL_MAN_UPDATE=bitpacked record + COL_MAN_UPDATE_PENDING :bit1; + COL_MAN_UPDATE_TAKEN :bit1; + RESERVED0 :bit14; + COL_MAN_UPDATE_LOCK :bit1; + RESERVED1 :bit7; + COL_MAN_DISABLE_MULTIPLE_UPDATE:bit1; + RESERVED2 :bit7; + end; + TCOMPUTE_PGM_HI=bitpacked record DATA :bit8; INST_ATC :bit1; @@ -2458,6 +13081,10 @@ type TCOMPUTE_TMA_LO=bit32; + TCONFIG_F0_BASE=bit32; + + TCONFIG_MEMSIZE=bit32; + TCPC_INT_STATUS=bitpacked record RESERVED0 :bit12; CMP_QUERY_STATUS_INT_STATUS :bit1; @@ -2579,6 +13206,8 @@ type RESERVED0 :bit29; end; + TCP_ME_RAM_DATA=bit32; + TCP_MQD_CONTROL=bitpacked record VMID :bit4; RESERVED0 :bit4; @@ -2623,6 +13252,46 @@ type PREEMPT_CE_STATUS:bit16; end; + TCRTC_MASTER_EN=bitpacked record + CRTC_MASTER_EN:bit1; + RESERVED0 :bit31; + end; + + TCSPRIV_CONNECT=bitpacked record + DOORBELL_OFFSET:bit21; + QUEUE_ID :bit3; + RESERVED0 :bit2; + VMID :bit4; + RESERVED1 :bit1; + UNORD_DISP :bit1; + end; + + TDAC_CLK_ENABLE=bitpacked record + DACA_CLK_ENABLE:bit1; + RESERVED0 :bit3; + DACB_CLK_ENABLE:bit1; + RESERVED1 :bit27; + end; + + TDAC_DFT_CONFIG=bit32; + + TDAC_FORCE_DATA=bitpacked record + DAC_FORCE_DATA:bit10; + RESERVED0 :bit22; + end; + + TDAC_MACRO_CNTL=bitpacked record + RESERVED0:bit2; + RESERVED1:bit6; + RESERVED2:bit6; + RESERVED3:bit2; + RESERVED4:bit6; + RESERVED5:bit2; + RESERVED6:bit4; + RESERVED7:bit1; + RESERVED8:bit3; + end; + TDB_DEPTH_CLEAR=bit32; TDB_DEPTH_SLICE=bitpacked record @@ -2648,6 +13317,830 @@ type TDB_Z_READ_BASE=bit32; + TDCIO_GSL0_CNTL=bitpacked record + DCIO_GSL0_VSYNC_SEL :bit3; + RESERVED0 :bit5; + DCIO_GSL0_TIMING_SYNC_SEL :bit3; + RESERVED1 :bit5; + DCIO_GSL0_GLOBAL_UNLOCK_SEL:bit3; + RESERVED2 :bit13; + end; + + TDCIO_GSL1_CNTL=bitpacked record + DCIO_GSL1_VSYNC_SEL :bit3; + RESERVED0 :bit5; + DCIO_GSL1_TIMING_SYNC_SEL :bit3; + RESERVED1 :bit5; + DCIO_GSL1_GLOBAL_UNLOCK_SEL:bit3; + RESERVED2 :bit13; + end; + + TDCIO_GSL2_CNTL=bitpacked record + DCIO_GSL2_VSYNC_SEL :bit3; + RESERVED0 :bit5; + DCIO_GSL2_TIMING_SYNC_SEL :bit3; + RESERVED1 :bit5; + DCIO_GSL2_GLOBAL_UNLOCK_SEL:bit3; + RESERVED2 :bit13; + end; + + TDCI_SOFT_RESET=bitpacked record + VGA_SOFT_RESET :bit1; + VIP_SOFT_RESET :bit1; + MCIF_SOFT_RESET :bit1; + FBC_SOFT_RESET :bit1; + DMIF0_SOFT_RESET :bit1; + DMIF1_SOFT_RESET :bit1; + DMIF2_SOFT_RESET :bit1; + DMIF3_SOFT_RESET :bit1; + DMIF4_SOFT_RESET :bit1; + DMIF5_SOFT_RESET :bit1; + DCFEV0_L_SOFT_RESET :bit1; + DCFEV0_C_SOFT_RESET :bit1; + DMIFARB_SOFT_RESET :bit1; + RESERVED0 :bit3; + MCIF_DWB_SOFT_RESET :bit1; + MCIF_CWB0_SOFT_RESET:bit1; + MCIF_CWB1_SOFT_RESET:bit1; + RESERVED1 :bit13; + end; + + TDCO_SOFT_RESET=bitpacked record + DACA_SOFT_RESET :bit1; + RESERVED0 :bit3; + I2S0_SPDIF0_SOFT_RESET:bit1; + I2S1_SOFT_RESET :bit1; + SPDIF1_SOFT_RESET :bit1; + RESERVED1 :bit5; + DB_CLK_SOFT_RESET :bit1; + RESERVED2 :bit3; + FMT0_SOFT_RESET :bit1; + FMT1_SOFT_RESET :bit1; + FMT2_SOFT_RESET :bit1; + FMT3_SOFT_RESET :bit1; + FMT4_SOFT_RESET :bit1; + FMT5_SOFT_RESET :bit1; + RESERVED3 :bit2; + MVP_SOFT_RESET :bit1; + ABM_SOFT_RESET :bit1; + RESERVED4 :bit1; + DVO_SOFT_RESET :bit1; + RESERVED5 :bit4; + end; + + TDC_GPIO_DDC1_A=bitpacked record + DC_GPIO_DDC1CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC1DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC1_Y=bitpacked record + DC_GPIO_DDC1CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC1DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC2_A=bitpacked record + DC_GPIO_DDC2CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC2DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC2_Y=bitpacked record + DC_GPIO_DDC2CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC2DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC3_A=bitpacked record + DC_GPIO_DDC3CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC3DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC3_Y=bitpacked record + DC_GPIO_DDC3CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC3DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC4_A=bitpacked record + DC_GPIO_DDC4CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC4DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC4_Y=bitpacked record + DC_GPIO_DDC4CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC4DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC5_A=bitpacked record + DC_GPIO_DDC5CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC5DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC5_Y=bitpacked record + DC_GPIO_DDC5CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC5DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC6_A=bitpacked record + DC_GPIO_DDC6CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC6DATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC6_Y=bitpacked record + DC_GPIO_DDC6CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC6DATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_HPD_EN=bitpacked record + DC_GPIO_HPD1_EN :bit1; + HPD1_SCHMEN_PI :bit1; + HPD1_SLEWNCORE :bit1; + RX_HPD_SCHMEN_PI:bit1; + RX_HPD_SLEWNCORE:bit1; + RESERVED0 :bit1; + HPD1_SEL0 :bit1; + RX_HPD_SEL0 :bit1; + DC_GPIO_HPD2_EN :bit1; + RESERVED1 :bit7; + DC_GPIO_HPD3_EN :bit1; + RESERVED2 :bit7; + DC_GPIO_HPD4_EN :bit1; + RESERVED3 :bit1; + DC_GPIO_HPD5_EN :bit1; + RESERVED4 :bit1; + DC_GPIO_HPD6_EN :bit1; + RESERVED5 :bit3; + end; + + TDC_HPD_CONTROL=bitpacked record + DC_HPD_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_I2C_CONTROL=bitpacked record + DC_I2C_GO :bit1; + DC_I2C_SOFT_RESET :bit1; + DC_I2C_SEND_RESET :bit1; + DC_I2C_SW_STATUS_RESET :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DC_I2C_DDC_SELECT :bit3; + RESERVED4 :bit9; + DC_I2C_TRANSACTION_COUNT:bit2; + RESERVED5 :bit9; + DC_I2C_DBG_REF_SEL :bit1; + end; + + TDC_LUT_CONTROL=bitpacked record + DC_LUT_INC_B :bit4; + DC_LUT_DATA_B_SIGNED_EN :bit1; + DC_LUT_DATA_B_FLOAT_POINT_EN:bit1; + DC_LUT_DATA_B_FORMAT :bit2; + DC_LUT_INC_G :bit4; + DC_LUT_DATA_G_SIGNED_EN :bit1; + DC_LUT_DATA_G_FLOAT_POINT_EN:bit1; + DC_LUT_DATA_G_FORMAT :bit2; + DC_LUT_INC_R :bit4; + DC_LUT_DATA_R_SIGNED_EN :bit1; + DC_LUT_DATA_R_FLOAT_POINT_EN:bit1; + DC_LUT_DATA_R_FORMAT :bit2; + RESERVED0 :bit8; + end; + + TDC_LUT_RW_MODE=bitpacked record + DC_LUT_RW_MODE :bit1; + RESERVED0 :bit15; + DC_LUT_ERROR :bit1; + DC_LUT_ERROR_RST:bit1; + RESERVED1 :bit14; + end; + + TDENORM_CONTROL=bitpacked record + DENORM_MODE :bit3; + RESERVED0 :bit1; + DENORM_14BIT_OUT:bit1; + RESERVED1 :bit27; + end; + + TDESKTOP_HEIGHT=bitpacked record + RESERVED0:bit14; + RESERVED1:bit18; + end; + + TDEVICE_STATUS2=bitpacked record + RESERVED :bit16; + RESERVED0:bit16; + end; + + TDIDT_DBR_CTRL0=bitpacked record + DIDT_CTRL_EN :bit1; + USE_REF_CLOCK :bit1; + PHASE_OFFSET :bit2; + DIDT_CTRL_RST :bit1; + DIDT_CLK_EN_OVERRIDE:bit1; + RESERVED0 :bit6; + RESERVED1 :bit6; + UNUSED_0 :bit14; + end; + + TDIDT_DBR_CTRL1=bitpacked record + MIN_POWER:bit16; + MAX_POWER:bit16; + end; + + TDIDT_DBR_CTRL2=bitpacked record + MAX_POWER_DELTA :bit14; + UNUSED_0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + UNUSED_1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + UNUSED_2 :bit1; + end; + + TDIDT_IND_INDEX=bit32; + + TDIDT_TCP_CTRL0=bitpacked record + DIDT_CTRL_EN :bit1; + USE_REF_CLOCK :bit1; + PHASE_OFFSET :bit2; + DIDT_CTRL_RST :bit1; + DIDT_CLK_EN_OVERRIDE :bit1; + DIDT_MAX_STALLS_ALLOWED_HI:bit6; + DIDT_MAX_STALLS_ALLOWED_LO:bit6; + UNUSED_0 :bit14; + end; + + TDIDT_TCP_CTRL1=bitpacked record + MIN_POWER:bit16; + MAX_POWER:bit16; + end; + + TDIDT_TCP_CTRL2=bitpacked record + MAX_POWER_DELTA :bit14; + RESERVED0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + RESERVED1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + RESERVED2 :bit1; + end; + + TDIG_BE_EN_CNTL=bitpacked record + DIG_ENABLE :bit1; + RESERVED0 :bit7; + DIG_SYMCLK_BE_ON:bit1; + RESERVED1 :bit23; + end; + + TDIG_SOFT_RESET=bitpacked record + DIGA_FE_SOFT_RESET:bit1; + DIGA_BE_SOFT_RESET:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + DIGB_FE_SOFT_RESET:bit1; + DIGB_BE_SOFT_RESET:bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGC_FE_SOFT_RESET:bit1; + DIGC_BE_SOFT_RESET:bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + DIGD_FE_SOFT_RESET:bit1; + DIGD_BE_SOFT_RESET:bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + DIGE_FE_SOFT_RESET:bit1; + DIGE_BE_SOFT_RESET:bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + DIGF_FE_SOFT_RESET:bit1; + DIGF_BE_SOFT_RESET:bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + DIGG_FE_SOFT_RESET:bit1; + DIGG_BE_SOFT_RESET:bit1; + RESERVED12 :bit1; + RESERVED13 :bit4; + DPDBG_SOFT_RESET :bit1; + end; + + TDMIF_ADDR_CALC=bitpacked record + RESERVED0 :bit4; + ADDR_CONFIG_PIPE_INTERLEAVE_SIZE:bit3; + RESERVED1 :bit21; + ADDR_CONFIG_ROW_SIZE :bit2; + RESERVED2 :bit2; + end; + + TDPG_HW_DEBUG_A=bit32; + + TDPG_HW_DEBUG_B=bit32; + + TDP_AUX_DEBUG_A=bit32; + + TDP_AUX_DEBUG_B=bit32; + + TDP_AUX_DEBUG_C=bit32; + + TDP_AUX_DEBUG_D=bit32; + + TDP_AUX_DEBUG_E=bit32; + + TDP_AUX_DEBUG_F=bit32; + + TDP_AUX_DEBUG_G=bit32; + + TDP_AUX_DEBUG_H=bit32; + + TDP_AUX_DEBUG_I=bit32; + + TDP_AUX_DEBUG_J=bit32; + + TDP_AUX_DEBUG_K=bit32; + + TDP_AUX_DEBUG_L=bit32; + + TDP_AUX_DEBUG_M=bit32; + + TDP_AUX_DEBUG_N=bit32; + + TDP_AUX_DEBUG_O=bit32; + + TDP_AUX_DEBUG_P=bit32; + + TDP_AUX_DEBUG_Q=bit32; + + TDP_DPHY_CRC_EN=bitpacked record + DPHY_CRC_EN :bit1; + RESERVED0 :bit3; + DPHY_CRC_CONT_EN :bit1; + RESERVED1 :bit3; + DPHY_CRC_RESULT_VALID:bit1; + RESERVED2 :bit23; + end; + + TDP_DTO0_MODULO=bit32; + + TDP_DTO1_MODULO=bit32; + + TDP_DTO2_MODULO=bit32; + + TDP_DTO3_MODULO=bit32; + + TDP_DTO4_MODULO=bit32; + + TDP_DTO5_MODULO=bit32; + + TDVO_CLK_ENABLE=bitpacked record + DVO_CLK_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TFBC_DEBUG_COMP=bitpacked record + FBC_COMP_SWAP :bit2; + RESERVED0 :bit1; + FBC_COMP_RSIZE :bit1; + FBC_COMP_BUSY_HYSTERESIS :bit4; + FBC_COMP_CLK_CNTL :bit2; + FBC_COMP_PRIVILEGED_ACCESS_ENABLE :bit1; + FBC_COMP_ADDRESS_TRANSLATION_ENABLE:bit1; + RESERVED1 :bit20; + end; + + TFEATURE_STATUS=bitpacked record + SCLK_DPM_ON :bit1; + MCLK_DPM_ON :bit1; + LCLK_DPM_ON :bit1; + UVD_DPM_ON :bit1; + VCE_DPM_ON :bit1; + SAMU_DPM_ON :bit1; + ACP_DPM_ON :bit1; + PCIE_DPM_ON :bit1; + BAPM_ON :bit1; + LPMX_ON :bit1; + NBDPM_ON :bit1; + LHTC_ON :bit1; + VPC_ON :bit1; + VOLTAGE_CONTROLLER_ON:bit1; + TDC_LIMIT_ON :bit1; + GPU_CAC_ON :bit1; + AVS_ON :bit1; + SPMI_ON :bit1; + SCLK_DPM_FORCED :bit1; + MCLK_DPM_FORCED :bit1; + LCLK_DPM_FORCED :bit1; + PCIE_DPM_FORCED :bit1; + RESERVED :bit10; + end; + + TFIRMWARE_FLAGS=bitpacked record + INTERRUPTS_ENABLED:bit1; + RESERVED0 :bit23; + TEST_COUNT :bit8; + end; + + TFMT_CLAMP_CNTL=bitpacked record + FMT_CLAMP_DATA_EN :bit1; + RESERVED0 :bit15; + FMT_CLAMP_COLOR_FORMAT:bit3; + RESERVED1 :bit13; + end; + + TFMT_DEBUG_CNTL=bitpacked record + FMT_DEBUG_COLOR_SELECT:bit2; + RESERVED0 :bit30; + end; + + TGB_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TGB_BACKEND_MAP=bit32; + + TGB_TILE_MODE10=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE11=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE12=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE13=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE14=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE15=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE16=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE17=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE18=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE19=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE20=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE21=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE22=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE23=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE24=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE25=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE26=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE27=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE28=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE29=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE30=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGB_TILE_MODE31=bitpacked record + MICRO_TILE_MODE :bit2; + ARRAY_MODE :bit4; + PIPE_CONFIG :bit5; + TILE_SPLIT :bit3; + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT :bit2; + NUM_BANKS :bit2; + MICRO_TILE_MODE_NEW:bit3; + SAMPLE_SPLIT :bit2; + RESERVED0 :bit5; + end; + + TGCK_MCLK_FUSES=bitpacked record + StartupMClkDid:bit7; + MClkADCA :bit4; + MClkDDCA :bit2; + MClkDiDtWait :bit3; + MClkDiDtFloor :bit2; + RESERVED0 :bit14; + end; + + TGC_CAC_ACC_CU0=bit32; + + TGC_CAC_ACC_CU1=bit32; + + TGC_CAC_ACC_CU2=bit32; + + TGC_CAC_ACC_CU3=bit32; + + TGC_CAC_ACC_CU4=bit32; + + TGC_CAC_ACC_CU5=bit32; + + TGC_CAC_ACC_CU6=bit32; + + TGC_CAC_ACC_CU7=bit32; + + TGC_CAC_ACC_CU8=bit32; + + TGC_CAC_ACC_CU9=bit32; + + TGC_CAC_OVRD_CU=bitpacked record + OVRRD_SELECT:bit16; + OVRRD_VALUE :bit16; + end; + TGDS_ATOM_READ0=bit32; TGDS_ATOM_READ1=bit32; @@ -2883,6 +14376,11 @@ type TGDS_OA_COUNTER=bit32; + TGDS_SECDED_CNT=bitpacked record + SEC:bit16; + DED:bit16; + end; + TGDS_VMID0_BASE=bitpacked record BASE :bit16; RESERVED0:bit16; @@ -2983,6 +14481,51 @@ type RESERVED0:bit15; end; + TGENERAL_PWRMGT=bitpacked record + GLOBAL_PWRMGT_EN :bit1; + STATIC_PM_EN :bit1; + THERMAL_PROTECTION_DIS :bit1; + THERMAL_PROTECTION_TYPE:bit1; + RESERVED0 :bit2; + SW_SMIO_INDEX :bit1; + RESERVED1 :bit1; + LOW_VOLT_D2_ACPI :bit1; + LOW_VOLT_D3_ACPI :bit1; + VOLT_PWRMGT_EN :bit1; + SPARE11 :bit1; + RESERVED2 :bit2; + GPU_COUNTER_ACPI :bit1; + GPU_COUNTER_CLK :bit1; + GPU_COUNTER_OFF :bit1; + GPU_COUNTER_INTF_OFF :bit1; + SPARE18 :bit1; + ACPI_D3_VID :bit2; + RESERVED3 :bit2; + DYN_SPREAD_SPECTRUM_EN :bit1; + RESERVED4 :bit3; + SPARE27 :bit1; + SPARE :bit4; + end; + + TGFX_COPY_STATE=bitpacked record + SRC_STATE_ID:bit3; + RESERVED0 :bit29; + end; + + TGLOBAL_CONTROL=bitpacked record + CONTROLLER_RESET :bit1; + FLUSH_CONTROL :bit1; + RESERVED0 :bit6; + ACCEPT_UNSOLICITED_RESPONSE_ENABLE:bit1; + RESERVED1 :bit23; + end; + + TGPIOPAD_INT_EN=bitpacked record + GPIO_INT_EN :bit29; + RESERVED0 :bit2; + SW_INITIATED_INT_EN:bit1; + end; + TGRBM_CAM_INDEX=bitpacked record CAM_INDEX:bit3; RESERVED0:bit29; @@ -3009,6 +14552,37 @@ type RESERVED0:bit16; end; + TGRPH_SWAP_CNTL=bitpacked record + GRPH_ENDIAN_SWAP :bit2; + RESERVED0 :bit2; + GRPH_RED_CROSSBAR :bit2; + GRPH_GREEN_CROSSBAR:bit2; + GRPH_BLUE_CROSSBAR :bit2; + GRPH_ALPHA_CROSSBAR:bit2; + RESERVED1 :bit20; + end; + + THDP_MEMIO_ADDR=bit32; + + THDP_MEMIO_CNTL=bitpacked record + MEMIO_SEND :bit1; + MEMIO_OP :bit1; + MEMIO_BE :bit4; + MEMIO_WR_STROBE :bit1; + MEMIO_RD_STROBE :bit1; + MEMIO_ADDR_UPPER :bit6; + MEMIO_CLR_WR_ERROR:bit1; + MEMIO_CLR_RD_ERROR:bit1; + MEMIO_VF :bit1; + MEMIO_VFID :bit4; + RESERVED0 :bit11; + end; + + THDP_XDP_STICKY=bitpacked record + STICKY_STS:bit16; + STICKY_W1C:bit16; + end; + TIA_CNTL_STATUS=bitpacked record IA_BUSY :bit1; IA_DMA_BUSY :bit1; @@ -3018,6 +14592,422 @@ type RESERVED0 :bit27; end; + TIH_VMID_10_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_11_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_12_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_13_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_14_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TIH_VMID_15_LUT=bitpacked record + PASID :bit16; + RESERVED0:bit16; + end; + + TINTERRUPT_CNTL=bitpacked record + IH_DUMMY_RD_OVERRIDE :bit1; + IH_DUMMY_RD_EN :bit1; + RESERVED0 :bit1; + IH_REQ_NONSNOOP_EN :bit1; + IH_INTR_DLY_CNTR :bit4; + GEN_IH_INT_EN :bit1; + GEN_GPIO_INT_EN :bit4; + SELECT_INT_GPIO_OUTPUT:bit2; + BIF_RB_REQ_NONSNOOP_EN:bit1; + RESERVED1 :bit16; + end; + + TINTERRUPT_LINE=bitpacked record + INTERRUPT_LINE:bit8; + RESERVED0 :bit24; + end; + + TKEY_RANGE_BLUE=bitpacked record + KEY_BLUE_LOW :bit16; + KEY_BLUE_HIGH:bit16; + end; + + TLB_DATA_FORMAT=bitpacked record + PIXEL_DEPTH :bit2; + PIXEL_EXPAN_MODE :bit1; + INTERLEAVE_EN :bit1; + PIXEL_REDUCE_MODE :bit1; + DYNAMIC_PIXEL_DEPTH:bit1; + RESERVED0 :bit6; + PREFETCH :bit1; + RESERVED1 :bit11; + REQUEST_MODE :bit1; + RESERVED2 :bit6; + ALPHA_EN :bit1; + end; + + TLB_MEMORY_CTRL=bitpacked record + LB_MEMORY_SIZE :bit12; + RESERVED0 :bit4; + LB_NUM_PARTITIONS:bit4; + LB_MEMORY_CONFIG :bit2; + RESERVED1 :bit10; + end; + + TLM_PRBSCONTROL=bitpacked record + PRBSPCIeSelect:bit16; + RESERVED0 :bit12; + LMLaneDegrade0:bit1; + LMLaneDegrade1:bit1; + LMLaneDegrade2:bit1; + LMLaneDegrade3:bit1; + end; + + TLNC_TOTAL_WACC=bit32; + + TLVDS_DATA_CNTL=bitpacked record + LVDS_24BIT_ENABLE :bit1; + RESERVED0 :bit3; + LVDS_24BIT_FORMAT :bit1; + RESERVED1 :bit3; + LVDS_2ND_CHAN_DE :bit1; + LVDS_2ND_CHAN_VS :bit1; + LVDS_2ND_CHAN_HS :bit1; + RESERVED2 :bit1; + LVDS_2ND_LINK_CNTL_BITS:bit3; + RESERVED3 :bit1; + LVDS_FP_POL :bit1; + LVDS_LP_POL :bit1; + LVDS_DTMG_POL :bit1; + RESERVED4 :bit13; + end; + + TMC_ARB_BANKMAP=bitpacked record + BANK0 :bit4; + BANK1 :bit4; + BANK2 :bit4; + BANK3 :bit4; + RANK :bit4; + RESERVED0:bit12; + end; + + TMC_ARB_MINCLKS=bitpacked record + READ_CLKS :bit8; + WRITE_CLKS :bit8; + ARB_RW_SWITCH :bit1; + RW_SWITCH_HARSH:bit2; + RESERVED0 :bit13; + end; + + TMC_ARB_PM_CNTL=bitpacked record + OVERRIDE_CGSTATE:bit2; + OVRR_CGRFSH :bit1; + OVRR_CGSQM :bit1; + SRFSH_ON_D1 :bit1; + BLKOUT_ON_D1 :bit1; + IDLE_ON_D1 :bit1; + OVRR_PM :bit1; + OVRR_PM_STATE :bit2; + OVRR_RD :bit1; + OVRR_RD_STATE :bit1; + OVRR_WR :bit1; + OVRR_WR_STATE :bit1; + OVRR_RFSH :bit1; + OVRR_RFSH_STATE :bit1; + OVRR_RD0_BUSY :bit1; + OVRR_RD1_BUSY :bit1; + IDLE_ON_D2 :bit1; + IDLE_ON_D3 :bit1; + IDLE_CNT :bit4; + OVRR_WR0_BUSY :bit1; + OVRR_WR1_BUSY :bit1; + RESERVED0 :bit6; + end; + + TMC_CG_DATAPORT=bit32; + + TMC_CITF_REMREQ=bitpacked record + READ_CREDITS :bit7; + WRITE_CREDITS :bit7; + CREDITS_ENABLE:bit1; + RESERVED0 :bit17; + end; + + TMC_HUB_WDP_BP2=bitpacked record + RDRET :bit16; + RESERVED0:bit16; + end; + + TMC_HUB_WDP_ERR=bitpacked record + MGPU1_TARG_SYS:bit1; + MGPU2_TARG_SYS:bit1; + RESERVED0 :bit30; + end; + + TMC_HUB_WDP_HDP=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_RLC=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SEM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SH0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SH1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SH2=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SH3=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SIP=bitpacked record + STALL_MODE :bit2; + ASK_CREDITS:bit7; + RESERVED0 :bit23; + end; + + TMC_HUB_WDP_SMU=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_UMC=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_UVD=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit13; + end; + + TMC_HUB_WDP_VP8=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_XDP=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_PMG_CMD_MRS=bitpacked record + ADR :bit16; + RESERVED0:bit4; + MOP :bit4; + _END :bit1; + RESERVED1:bit7; + end; + + TMC_RPB_IF_CONF=bitpacked record + RPB_BIF_CREDITS :bit8; + OUTSTANDING_WRRET_ASK:bit8; + RESERVED0 :bit16; + end; + + TMC_SEQ_SUP_PGM=bit32; + + TMC_VM_AGP_BASE=bitpacked record + AGP_BASE :bit18; + RESERVED0:bit14; + end; + + TMC_VM_STEERING=bitpacked record + DEFAULT_STEERING:bit2; + RESERVED0 :bit30; + end; + + TMC_XBAR_REMOTE=bitpacked record + WRREQ_EN_GOQ:bit1; + RDREQ_EN_GOQ:bit1; + RESERVED0 :bit30; + end; + + TMC_XBAR_SPARE0=bit32; + + TMC_XBAR_SPARE1=bit32; + + TMC_XPB_CLK_GAT=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_XPB_LB_ADDR=bitpacked record + CMP0 :bit10; + MASK0:bit10; + CMP1 :bit6; + MASK1:bit6; + end; + + TMC_XPB_WCB_CFG=bitpacked record + TIMEOUT :bit16; + HST_MAX :bit2; + SID_MAX :bit2; + RESERVED0:bit12; + end; + + TMC_XPB_WCB_STS=bitpacked record + PBUF_VLD :bit16; + WCB_HST_DATA_BUF_CNT:bit7; + WCB_SID_DATA_BUF_CNT:bit7; + RESERVED0 :bit2; + end; + + TMSI_PENDING_64=bit32; + + TOVL_DFQ_STATUS=bitpacked record + OVL_DFQ_NUM_ENTRIES :bit4; + OVL_SECONDARY_DFQ_NUM_ENTRIES:bit4; + OVL_DFQ_RESET_FLAG :bit1; + OVL_DFQ_RESET_ACK :bit1; + RESERVED0 :bit22; + end; + TPA_CL_VTE_CNTL=bitpacked record VPORT_X_SCALE_ENA :bit1; VPORT_X_OFFSET_ENA:bit1; @@ -3050,6 +15040,537 @@ type RESERVED0 :bit26; end; + TPCIEP_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + RESERVED0 :bit16; + end; + + TPCIEP_RESERVED=bit32; + + TPCIEP_STRAP_LC=bitpacked record + STRAP_FTS_yTSx_COUNT :bit2; + STRAP_LONG_yTSx_COUNT :bit2; + STRAP_MED_yTSx_COUNT :bit2; + STRAP_SHORT_yTSx_COUNT :bit2; + STRAP_SKIP_INTERVAL :bit3; + STRAP_BYPASS_RCVR_DET :bit1; + STRAP_COMPLIANCE_DIS :bit1; + STRAP_FORCE_COMPLIANCE :bit1; + STRAP_REVERSE_LC_LANES :bit1; + STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS:bit1; + STRAP_LANE_NEGOTIATION :bit3; + RESERVED0 :bit13; + end; + + TPCIE_BAR1_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_BAR2_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_BAR3_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_BAR4_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_BAR5_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_BAR6_CNTL=bitpacked record + BAR_INDEX :bit3; + RESERVED0 :bit2; + BAR_TOTAL_NUM:bit3; + BAR_SIZE :bit5; + RESERVED1 :bit19; + end; + + TPCIE_LC_STATE0=bitpacked record + LC_CURRENT_STATE:bit6; + RESERVED0 :bit2; + LC_PREV_STATE1 :bit6; + RESERVED1 :bit2; + LC_PREV_STATE2 :bit6; + RESERVED2 :bit2; + LC_PREV_STATE3 :bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE1=bitpacked record + LC_PREV_STATE4:bit6; + RESERVED0 :bit2; + LC_PREV_STATE5:bit6; + RESERVED1 :bit2; + LC_PREV_STATE6:bit6; + RESERVED2 :bit2; + LC_PREV_STATE7:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE2=bitpacked record + LC_PREV_STATE8 :bit6; + RESERVED0 :bit2; + LC_PREV_STATE9 :bit6; + RESERVED1 :bit2; + LC_PREV_STATE10:bit6; + RESERVED2 :bit2; + LC_PREV_STATE11:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE3=bitpacked record + LC_PREV_STATE12:bit6; + RESERVED0 :bit2; + LC_PREV_STATE13:bit6; + RESERVED1 :bit2; + LC_PREV_STATE14:bit6; + RESERVED2 :bit2; + LC_PREV_STATE15:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE4=bitpacked record + LC_PREV_STATE16:bit6; + RESERVED0 :bit2; + LC_PREV_STATE17:bit6; + RESERVED1 :bit2; + LC_PREV_STATE18:bit6; + RESERVED2 :bit2; + LC_PREV_STATE19:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE5=bitpacked record + LC_PREV_STATE20:bit6; + RESERVED0 :bit2; + LC_PREV_STATE21:bit6; + RESERVED1 :bit2; + LC_PREV_STATE22:bit6; + RESERVED2 :bit2; + LC_PREV_STATE23:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE6=bitpacked record + LC_PREV_STATE24:bit6; + RESERVED0 :bit2; + LC_PREV_STATE25:bit6; + RESERVED1 :bit2; + LC_PREV_STATE26:bit6; + RESERVED2 :bit2; + LC_PREV_STATE27:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE7=bitpacked record + LC_PREV_STATE28:bit6; + RESERVED0 :bit2; + LC_PREV_STATE29:bit6; + RESERVED1 :bit2; + LC_PREV_STATE30:bit6; + RESERVED2 :bit2; + LC_PREV_STATE31:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE8=bitpacked record + LC_PREV_STATE32:bit6; + RESERVED0 :bit2; + LC_PREV_STATE33:bit6; + RESERVED1 :bit2; + LC_PREV_STATE34:bit6; + RESERVED2 :bit2; + LC_PREV_STATE35:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE9=bitpacked record + LC_PREV_STATE36:bit6; + RESERVED0 :bit2; + LC_PREV_STATE37:bit6; + RESERVED1 :bit2; + LC_PREV_STATE38:bit6; + RESERVED2 :bit2; + LC_PREV_STATE39:bit6; + RESERVED3 :bit2; + end; + + TPCIE_OBFF_CNTL=bitpacked record + TX_OBFF_PRIV_DISABLE :bit1; + TX_OBFF_WAKE_SIMPLE_MODE_EN :bit1; + TX_OBFF_HOSTMEM_TO_ACTIVE :bit1; + TX_OBFF_SLVCPL_TO_ACTIVE :bit1; + TX_OBFF_WAKE_MAX_PULSE_WIDTH :bit4; + TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH:bit4; + TX_OBFF_WAKE_SAMPLING_PERIOD :bit4; + TX_OBFF_INTR_TO_ACTIVE :bit1; + TX_OBFF_ERR_TO_ACTIVE :bit1; + TX_OBFF_ANY_MSG_TO_ACTIVE :bit1; + TX_OBFF_ACCEPT_IN_NOND0 :bit1; + TX_OBFF_PENDING_REQ_TO_ACTIVE :bit4; + RESERVED0 :bit8; + end; + + TPCIE_PASID_CAP=bitpacked record + RESERVED0 :bit1; + PASID_EXE_PERMISSION_SUPPORTED:bit1; + PASID_PRIV_MODE_SUPPORTED :bit1; + RESERVED1 :bit1; + RESERVED2 :bit4; + MAX_PASID_WIDTH :bit5; + RESERVED3 :bit19; + end; + + TPCIE_PORT_DATA=bit32; + + TPCIE_PRBS_MISC=bitpacked record + PRBS_EN :bit1; + PRBS_TEST_MODE :bit3; + PRBS_USER_PATTERN_TOGGLE:bit1; + PRBS_8BIT_SEL :bit1; + PRBS_COMMA_NUM :bit2; + PRBS_LOCK_CNT :bit5; + RESERVED0 :bit1; + PRBS_DATA_RATE :bit2; + PRBS_CHK_ERR_MASK :bit16; + end; + + TPCIE_SRIOV_CAP=bitpacked record + SRIOV_VF_MIGRATION_CAP :bit1; + SRIOV_ARI_CAP_HIERARCHY_PRESERVED:bit1; + RESERVED0 :bit19; + SRIOV_VF_MIGRATION_INTR_MSG_NUM :bit11; + end; + + TPCIE_TX_REPLAY=bitpacked record + TX_REPLAY_NUM :bit10; + RESERVED0 :bit5; + TX_REPLAY_TIMER_OVERWRITE:bit1; + TX_REPLAY_TIMER :bit16; + end; + + TPCIE_WRAP_MISC=bitpacked record + RESERVED0 :bit1; + STRAP_BIF_HOLD_TRAINING_STICKY:bit1; + STRAP_BIF_QUICKSIM_START :bit1; + RESERVED1 :bit29; + end; + + TPLL_DEBUG_CNTL=bitpacked record + PLL_DEBUG_SIGNALS_ENABLE:bit1; + RESERVED0 :bit3; + PLL_DEBUG_MUXOUT_SEL :bit4; + PLL_DEBUG_CLK_SEL :bit5; + RESERVED1 :bit3; + PLL_DEBUG_ADC_CNTL :bit8; + PLL_DEBUG_ADC_READBACK :bit3; + PLL_DEBUG_ADC_EN :bit1; + RESERVED2 :bit4; + end; + + TPLL_IDCLK_CNTL=bitpacked record + PLL_LTDP_IDCLK_EN :bit1; + PLL_LTDP_IDCLK_DIFF_EN :bit1; + PLL_TMDP_IDCLK_EN :bit1; + PLL_TMDP_IDCLK_DIFF_EN :bit1; + PLL_IDCLK_EN :bit1; + RESERVED0 :bit3; + PLL_DIFF_POST_DIV_RESET :bit1; + RESERVED1 :bit3; + PLL_DIFF_POST_DIV_SELECT:bit1; + RESERVED2 :bit3; + PLL_DIFF_POST_DIV :bit4; + PLL_CUR_LTDP :bit2; + PLL_CUR_PREDRV :bit2; + PLL_CUR_TMDP :bit2; + PLL_CML_A_DRVSTR :bit2; + PLL_CML_B_DRVSTR :bit2; + RESERVED3 :bit2; + end; + + TPROG_INTERFACE=bitpacked record + PROG_INTERFACE:bit8; + RESERVED0 :bit24; + end; + + TPWR_CKS_ENABLE=bitpacked record + STRETCH_ENABLE :bit1; + masterReset :bit1; + staticEnable :bit1; + IGNORE_DROOP_DETECT:bit1; + PCC_HAND_SHAKE_EN :bit1; + MET_CTRL_SEL :bit2; + DS_HAND_SHAKE_EN :bit1; + RESERVED0 :bit24; + end; + + TRBBMIF_TIMEOUT=bitpacked record + RBBMIF_TIMEOUT_DELAY:bit20; + RBBMIF_ACK_HOLD :bit12; + end; + + TRLC_PG_DELAY_2=bitpacked record + SERDES_TIMEOUT_VALUE:bit8; + SERDES_CMD_DELAY :bit8; + PERCU_TIMEOUT_VALUE :bit16; + end; + + TRLC_PG_DELAY_3=bitpacked record + CGCG_ACTIVE_BEFORE_CGPG:bit8; + RESERVED :bit24; + end; + + TRLC_UCODE_CNTL=bit32; + + TROM_SW_COMMAND=bitpacked record + ROM_SW_INSTRUCTION:bit8; + ROM_SW_ADDRESS :bit24; + end; + + TROM_SW_DATA_10=bit32; + + TROM_SW_DATA_11=bit32; + + TROM_SW_DATA_12=bit32; + + TROM_SW_DATA_13=bit32; + + TROM_SW_DATA_14=bit32; + + TROM_SW_DATA_15=bit32; + + TROM_SW_DATA_16=bit32; + + TROM_SW_DATA_17=bit32; + + TROM_SW_DATA_18=bit32; + + TROM_SW_DATA_19=bit32; + + TROM_SW_DATA_20=bit32; + + TROM_SW_DATA_21=bit32; + + TROM_SW_DATA_22=bit32; + + TROM_SW_DATA_23=bit32; + + TROM_SW_DATA_24=bit32; + + TROM_SW_DATA_25=bit32; + + TROM_SW_DATA_26=bit32; + + TROM_SW_DATA_27=bit32; + + TROM_SW_DATA_28=bit32; + + TROM_SW_DATA_29=bit32; + + TROM_SW_DATA_30=bit32; + + TROM_SW_DATA_31=bit32; + + TROM_SW_DATA_32=bit32; + + TROM_SW_DATA_33=bit32; + + TROM_SW_DATA_34=bit32; + + TROM_SW_DATA_35=bit32; + + TROM_SW_DATA_36=bit32; + + TROM_SW_DATA_37=bit32; + + TROM_SW_DATA_38=bit32; + + TROM_SW_DATA_39=bit32; + + TROM_SW_DATA_40=bit32; + + TROM_SW_DATA_41=bit32; + + TROM_SW_DATA_42=bit32; + + TROM_SW_DATA_43=bit32; + + TROM_SW_DATA_44=bit32; + + TROM_SW_DATA_45=bit32; + + TROM_SW_DATA_46=bit32; + + TROM_SW_DATA_47=bit32; + + TROM_SW_DATA_48=bit32; + + TROM_SW_DATA_49=bit32; + + TROM_SW_DATA_50=bit32; + + TROM_SW_DATA_51=bit32; + + TROM_SW_DATA_52=bit32; + + TROM_SW_DATA_53=bit32; + + TROM_SW_DATA_54=bit32; + + TROM_SW_DATA_55=bit32; + + TROM_SW_DATA_56=bit32; + + TROM_SW_DATA_57=bit32; + + TROM_SW_DATA_58=bit32; + + TROM_SW_DATA_59=bit32; + + TROM_SW_DATA_60=bit32; + + TROM_SW_DATA_61=bit32; + + TROM_SW_DATA_62=bit32; + + TROM_SW_DATA_63=bit32; + + TROM_SW_DATA_64=bit32; + + TSDMA0_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TSDMA0_F32_CNTL=bitpacked record + HALT :bit1; + STEP :bit1; + DBG_SELECT_BITS:bit6; + RESERVED0 :bit24; + end; + + TSDMA1_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TSDMA1_F32_CNTL=bitpacked record + HALT :bit1; + STEP :bit1; + DBG_SELECT_BITS:bit6; + RESERVED0 :bit24; + end; + + TSEM_EDC_CONFIG=bitpacked record + RESERVED0:bit1; + DIS_EDC :bit1; + RESERVED1:bit30; + end; + + TSMC_IND_DATA_0=bit32; + + TSMC_IND_DATA_1=bit32; + + TSMC_IND_DATA_2=bit32; + + TSMC_IND_DATA_3=bit32; + + TSMC_IND_DATA_4=bit32; + + TSMC_IND_DATA_5=bit32; + + TSMC_IND_DATA_6=bit32; + + TSMC_IND_DATA_7=bit32; + + TSMC_MESSAGE_10=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MESSAGE_11=bitpacked record + SMC_MSG :bit16; + RESERVED0:bit16; + end; + + TSMC_MSG_ARG_10=bit32; + + TSMC_MSG_ARG_11=bit32; + + TSMU_IND_DATA_0=bit32; + + TSMU_IND_DATA_1=bit32; + + TSMU_IND_DATA_2=bit32; + + TSMU_IND_DATA_3=bit32; + + TSMU_IND_DATA_4=bit32; + + TSMU_IND_DATA_5=bit32; + + TSMU_IND_DATA_6=bit32; + + TSMU_IND_DATA_7=bit32; + TSPI_BARYC_CNTL=bitpacked record PERSP_CENTER_CNTL :bit1; RESERVED0 :bit3; @@ -3124,6 +15645,149 @@ type RESERVED0:bit16; end; + TSPLL_CNTL_MODE=bitpacked record + SPLL_SW_DIR_CONTROL :bit1; + SPLL_LEGACY_PDIV :bit1; + SPLL_TEST :bit1; + SPLL_FASTEN :bit1; + SPLL_ENSAT :bit1; + RESERVED0 :bit5; + SPLL_TEST_CLK_EXT_DIV:bit2; + SPLL_CTLREQ_DLY_CNT :bit8; + RESERVED1 :bit8; + SPLL_RESET_EN :bit1; + SPLL_VCO_MODE :bit2; + RESERVED2 :bit1; + end; + + TSPMI_CONFIG0_0=bitpacked record + SPMI_ENABLE :bit1; + RESERVED0 :bit1; + SPMI_PATH_NUM_TIMING_FLOPS :bit5; + SPMI_SIGNALING_DELAY_CYCLES :bit5; + SPMI_SIGNALING_HOLD_CYCLES :bit5; + SPMI_PATH_ENABLE_DELAY_CYCLES :bit5; + SPMI_PATH_DISABLE_DELAY_CYCLES:bit5; + RESERVED1 :bit5; + end; + + TSPMI_CONFIG1_0=bitpacked record + SPMI_SIGNALING_RESET_HOLD_CYCLES:bit5; + SPMI_CHAIN_SIZE :bit11; + RESERVED0 :bit16; + end; + + TSPMI_SRAM_DATA=bit32; + + TSQ_EDC_DED_CNT=bitpacked record + LDS_DED :bit8; + SGPR_DED :bit8; + VGPR_DED :bit8; + RESERVED0:bit8; + end; + + TSQ_EDC_SEC_CNT=bitpacked record + LDS_SEC :bit8; + SGPR_SEC :bit8; + VGPR_SEC :bit8; + RESERVED0:bit8; + end; + + TSQ_LB_CTR_CTRL=bitpacked record + START :bit1; + LOAD :bit1; + CLEAR :bit1; + RESERVED0:bit29; + end; + + TSQ_REG_CREDITS=bitpacked record + SRBM_CREDITS :bit6; + RESERVED0 :bit2; + CMD_CREDITS :bit4; + RESERVED1 :bit16; + REG_BUSY :bit1; + SRBM_OVERFLOW :bit1; + IMMED_OVERFLOW:bit1; + CMD_OVERFLOW :bit1; + end; + + TSQ_WAVE_IB_STS=bitpacked record + VM_CNT :bit4; + EXP_CNT :bit3; + RESERVED0 :bit1; + LGKM_CNT :bit4; + VALU_CNT :bit3; + FIRST_REPLAY:bit1; + RCNT :bit4; + RESERVED1 :bit12; + end; + + TSQ_WAVE_STATUS=bitpacked record + SCC :bit1; + SPI_PRIO :bit2; + USER_PRIO :bit2; + PRIV :bit1; + TRAP_EN :bit1; + TTRACE_EN :bit1; + EXPORT_RDY :bit1; + EXECZ :bit1; + VCCZ :bit1; + IN_TG :bit1; + IN_BARRIER :bit1; + HALT :bit1; + TRAP :bit1; + TTRACE_CU_EN :bit1; + VALID :bit1; + ECC_ERR :bit1; + SKIP_EXPORT :bit1; + PERF_EN :bit1; + COND_DBG_USER:bit1; + COND_DBG_SYS :bit1; + ALLOW_REPLAY :bit1; + INST_ATC :bit1; + RESERVED0 :bit3; + MUST_EXPORT :bit1; + RESERVED1 :bit4; + end; + + TSQ_WAVE_TBA_HI=bitpacked record + ADDR_HI :bit8; + RESERVED0:bit24; + end; + + TSQ_WAVE_TBA_LO=bit32; + + TSQ_WAVE_TMA_HI=bitpacked record + ADDR_HI :bit8; + RESERVED0:bit24; + end; + + TSQ_WAVE_TMA_LO=bit32; + + TSQ_WAVE_TTMP10=bit32; + + TSQ_WAVE_TTMP11=bit32; + + TSRBM_CAM_INDEX=bitpacked record + CAM_INDEX:bit3; + RESERVED0:bit29; + end; + + TSRBM_READ_CNTL=bitpacked record + READ_TIMEOUT:bit24; + RESERVED0 :bit8; + end; + + TSRBM_VF_ENABLE=bitpacked record + VF_ENABLE:bit1; + RESERVED0:bit31; + end; + + TSRBM_VIRT_CNTL=bitpacked record + VF_WRITE_ENABLE:bit1; + RESERVED0 :bit31; + end; + TTA_DEBUG_INDEX=bitpacked record INDEX :bit5; RESERVED0:bit27; @@ -3140,11 +15804,184 @@ type RESERVED0:bit31; end; + TTDC_MV_AVERAGE=bitpacked record + IDD :bit16; + IDDC:bit16; + end; + TTD_DEBUG_INDEX=bitpacked record INDEX :bit5; RESERVED0:bit27; end; + TTHM_TMON2_CTRL=bitpacked record + POWER_DOWN :bit1; + BGADJ :bit8; + BGADJ_MODE :bit1; + TMON_PAUSE :bit1; + INT_MEAS_EN :bit1; + DEBUG_MODE :bit1; + EN_CFG_SERDES:bit1; + RESERVED0 :bit18; + end; + + TUVD_CGC_STATUS=bitpacked record + SYS_SCLK :bit1; + SYS_DCLK :bit1; + SYS_VCLK :bit1; + UDEC_SCLK :bit1; + UDEC_DCLK :bit1; + UDEC_VCLK :bit1; + MPEG2_SCLK :bit1; + MPEG2_DCLK :bit1; + MPEG2_VCLK :bit1; + REGS_SCLK :bit1; + REGS_VCLK :bit1; + RBC_SCLK :bit1; + LMI_MC_SCLK :bit1; + LMI_UMC_SCLK :bit1; + IDCT_SCLK :bit1; + IDCT_VCLK :bit1; + MPRD_SCLK :bit1; + MPRD_DCLK :bit1; + MPRD_VCLK :bit1; + MPC_SCLK :bit1; + MPC_DCLK :bit1; + LBSI_SCLK :bit1; + LBSI_VCLK :bit1; + LRBBM_SCLK :bit1; + WCB_SCLK :bit1; + VCPU_SCLK :bit1; + VCPU_VCLK :bit1; + SCPU_SCLK :bit1; + SCPU_VCLK :bit1; + RESERVED0 :bit1; + JPEG_ACTIVE :bit1; + ALL_DEC_ACTIVE:bit1; + end; + + TUVD_CONTEXT_ID=bit32; + + TUVD_LMI_STATUS=bitpacked record + READ_CLEAN :bit1; + WRITE_CLEAN :bit1; + WRITE_CLEAN_RAW :bit1; + VCPU_LMI_WRITE_CLEAN:bit1; + UMC_READ_CLEAN :bit1; + UMC_WRITE_CLEAN :bit1; + UMC_WRITE_CLEAN_RAW :bit1; + PENDING_UVD_MC_WRITE:bit1; + READ_CLEAN_RAW :bit1; + UMC_READ_CLEAN_RAW :bit1; + UMC_UVD_IDLE :bit1; + UMC_AVP_IDLE :bit1; + ADP_MC_READ_CLEAN :bit1; + ADP_UMC_READ_CLEAN :bit1; + RESERVED0 :bit18; + end; + + TUVD_MASTINT_EN=bitpacked record + OVERRUN_RST:bit1; + VCPU_EN :bit1; + SYS_EN :bit1; + RESERVED0 :bit1; + INT_OVERRUN:bit19; + RESERVED1 :bit9; + end; + + TUVD_SOFT_RESET=bitpacked record + RBC_SOFT_RESET :bit1; + LBSI_SOFT_RESET :bit1; + LMI_SOFT_RESET :bit1; + VCPU_SOFT_RESET :bit1; + UDEC_SOFT_RESET :bit1; + CSM_SOFT_RESET :bit1; + CXW_SOFT_RESET :bit1; + TAP_SOFT_RESET :bit1; + MPC_SOFT_RESET :bit1; + JPEG_SCLK_RESET_STATUS:bit1; + IH_SOFT_RESET :bit1; + MPRD_SOFT_RESET :bit1; + IDCT_SOFT_RESET :bit1; + LMI_UMC_SOFT_RESET :bit1; + SPH_SOFT_RESET :bit1; + MIF_SOFT_RESET :bit1; + LCM_SOFT_RESET :bit1; + SUVD_SOFT_RESET :bit1; + LBSI_VCLK_RESET_STATUS:bit1; + VCPU_VCLK_RESET_STATUS:bit1; + UDEC_VCLK_RESET_STATUS:bit1; + UDEC_DCLK_RESET_STATUS:bit1; + MPC_DCLK_RESET_STATUS :bit1; + MPRD_VCLK_RESET_STATUS:bit1; + MPRD_DCLK_RESET_STATUS:bit1; + IDCT_VCLK_RESET_STATUS:bit1; + MIF_DCLK_RESET_STATUS :bit1; + LCM_DCLK_RESET_STATUS :bit1; + SUVD_VCLK_RESET_STATUS:bit1; + SUVD_DCLK_RESET_STATUS:bit1; + RE_DCLK_RESET_STATUS :bit1; + SRE_DCLK_RESET_STATUS :bit1; + end; + + TVCE_INT_STATUS=bitpacked record + RESERVED0:bit16; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit13; + end; + + TVCE_RB_BASE_HI=bit32; + + TVCE_RB_BASE_LO=bitpacked record + RESERVED0 :bit6; + RB_BASE_LO:bit26; + end; + + TVCE_SOFT_RESET=bitpacked record + ECPU_SOFT_RESET:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit1; + RESERVED22 :bit9; + end; + + TVCE_SYS_INT_EN=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit2; + VCE_SYS_INT_TRAP_INTERRUPT_EN:bit1; + RESERVED2 :bit1; + RESERVED3 :bit6; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit14; + end; + TVGT_DEBUG_CNTL=bitpacked record VGT_DEBUG_INDX :bit6; VGT_DEBUG_SEL_BUS_B:bit1; @@ -3383,6 +16220,18 @@ type RESERVED0 :bit31; end; + TVIEWPORT_START=bitpacked record + VIEWPORT_Y_START:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START:bit14; + RESERVED1 :bit2; + end; + + TVM_INIT_STATUS=bitpacked record + VM_INIT_STATUS:bit1; + RESERVED0 :bit31; + end; + TWD_CNTL_STATUS=bitpacked record WD_BUSY :bit1; WD_SPL_DMA_BUSY:bit1; @@ -3419,6 +16268,133 @@ type wd_te11_out_se3_fifo_empty:bit1; end; + TXDMA_IF_STATUS=bitpacked record + XDMA_MC_PCIEWR_BUSY:bit1; + RESERVED0 :bit31; + end; + + TXDMA_INTERRUPT=bitpacked record + RESERVED0 :bit8; + XDMA_MSTR_MEM_URGENT_STAT:bit1; + XDMA_MSTR_MEM_URGENT_MASK:bit1; + XDMA_MSTR_MEM_URGENT_ACK :bit1; + RESERVED1 :bit5; + XDMA_SLV_READ_URGENT_STAT:bit1; + XDMA_SLV_READ_URGENT_MASK:bit1; + XDMA_SLV_READ_URGENT_ACK :bit1; + RESERVED2 :bit1; + XDMA_PERF_MEAS_STAT :bit1; + XDMA_PERF_MEAS_MASK :bit1; + XDMA_PERF_MEAS_ACK :bit1; + RESERVED3 :bit9; + end; + + TXDMA_MSTR_CNTL=bitpacked record + RESERVED0 :bit12; + XDMA_MSTR_ALPHA_POSITION:bit2; + XDMA_MSTR_MEM_READY :bit1; + RESERVED1 :bit1; + XDMA_MSTR_ENABLE :bit1; + RESERVED2 :bit1; + XDMA_MSTR_DEBUG_MODE :bit1; + RESERVED3 :bit1; + XDMA_MSTR_SOFT_RESET :bit1; + XDMA_MSTR_BIF_STALL_EN :bit1; + RESERVED4 :bit10; + end; + + TXDMA_PG_STATUS=bitpacked record + XDMA_SERDES_RDATA :bit24; + XDMA_PGFSM_READ_READY :bit1; + XDMA_SERDES_BUSY :bit1; + XDMA_SERDES_SMU_POWER_STATUS:bit1; + RESERVED0 :bit5; + end; + + TAFMT_MPEG_INFO0=bitpacked record + AFMT_MPEG_INFO_CHECKSUM:bit8; + AFMT_MPEG_INFO_MB0 :bit8; + AFMT_MPEG_INFO_MB1 :bit8; + AFMT_MPEG_INFO_MB2 :bit8; + end; + + TAFMT_MPEG_INFO1=bitpacked record + AFMT_MPEG_INFO_MB3:bit8; + AFMT_MPEG_INFO_MF :bit2; + RESERVED0 :bit2; + AFMT_MPEG_INFO_FR :bit1; + RESERVED1 :bit19; + end; + + TATC_L1RD_STATUS=bitpacked record + BUSY :bit1; + DEADLOCK_DETECTION:bit1; + RESERVED0 :bit6; + BAD_NEED_ATS :bit1; + RESERVED1 :bit3; + CAM_PARITY_ERRORS :bit5; + CAM_INDEX :bit5; + RESERVED2 :bit10; + end; + + TATC_L1WR_STATUS=bitpacked record + BUSY :bit1; + DEADLOCK_DETECTION:bit1; + RESERVED0 :bit6; + BAD_NEED_ATS :bit1; + RESERVED1 :bit3; + CAM_PARITY_ERRORS :bit5; + CAM_INDEX :bit5; + RESERVED2 :bit10; + end; + + TAUX_ARB_CONTROL=bitpacked record + AUX_ARB_PRIORITY :bit2; + AUX_REG_RW_CNTL_STATUS :bit2; + RESERVED0 :bit4; + AUX_NO_QUEUED_SW_GO :bit1; + RESERVED1 :bit1; + AUX_NO_QUEUED_LS_GO :bit1; + RESERVED2 :bit5; + AUX_SW_USE_AUX_REG_REQ :bit1; + AUX_SW_DONE_USING_AUX_REG :bit1; + RESERVED3 :bit6; + AUX_DMCU_USE_AUX_REG_REQ :bit1; + AUX_DMCU_DONE_USING_AUX_REG:bit1; + RESERVED4 :bit6; + end; + + TBF_ANA_ISO_CNTL=bitpacked record + BF_ANA_ISO_DIS_MASK :bit1; + BF_VDDC_ISO_DIS_MASK:bit1; + RESERVED0 :bit30; + end; + + TBIF_PWDN_STATUS=bitpacked record + BU_REG_pw_status :bit1; + RWREG_RFEWDBIF_REG_pw_status:bit1; + SMBUS_REG_pw_status :bit1; + BX_REG_pw_status :bit1; + RESERVED0 :bit28; + end; + + TBIF_SLVARB_MODE=bitpacked record + SLVARB_MODE:bit2; + RESERVED0 :bit30; + end; + + TBIOS_SCRATCH_10=bit32; + + TBIOS_SCRATCH_11=bit32; + + TBIOS_SCRATCH_12=bit32; + + TBIOS_SCRATCH_13=bit32; + + TBIOS_SCRATCH_14=bit32; + + TBIOS_SCRATCH_15=bit32; + TCB_COLOR0_CMASK=bit32; TCB_COLOR0_FMASK=bit32; @@ -3741,6 +16717,101 @@ type RESERVED0 :bit19; end; + TCG_THERMAL_CTRL=bitpacked record + DPM_EVENT_SRC :bit3; + THERM_INC_CLK :bit1; + SPARE :bit10; + DIG_THERM_DPM :bit8; + RESERVED :bit3; + CTF_PAD_POLARITY:bit1; + CTF_PAD_EN :bit1; + RESERVED0 :bit5; + end; + + TCNB_PWRMGT_CNTL=bitpacked record + GNB_SLOW_MODE:bit2; + GNB_SLOW :bit1; + FORCE_NB_PS1 :bit1; + DPM_ENABLED :bit1; + SPARE :bit27; + end; + + TCNV_CSC_C11_C12=bitpacked record + CNV_CSC_C11:bit13; + RESERVED0 :bit3; + CNV_CSC_C12:bit13; + RESERVED1 :bit3; + end; + + TCNV_CSC_C13_C14=bitpacked record + CNV_CSC_C13:bit13; + RESERVED0 :bit3; + CNV_CSC_C14:bit15; + RESERVED1 :bit1; + end; + + TCNV_CSC_C21_C22=bitpacked record + CNV_CSC_C21:bit13; + RESERVED0 :bit3; + CNV_CSC_C22:bit13; + RESERVED1 :bit3; + end; + + TCNV_CSC_C23_C24=bitpacked record + CNV_CSC_C23:bit13; + RESERVED0 :bit3; + CNV_CSC_C24:bit15; + RESERVED1 :bit1; + end; + + TCNV_CSC_C31_C32=bitpacked record + CNV_CSC_C31:bit13; + RESERVED0 :bit3; + CNV_CSC_C32:bit13; + RESERVED1 :bit3; + end; + + TCNV_CSC_C33_C34=bitpacked record + CNV_CSC_C33:bit13; + RESERVED0 :bit3; + CNV_CSC_C34:bit15; + RESERVED1 :bit1; + end; + + TCNV_CSC_CLAMP_B=bitpacked record + CNV_CSC_CLAMP_UPPER_B:bit16; + CNV_CSC_CLAMP_LOWER_B:bit16; + end; + + TCNV_CSC_CLAMP_G=bitpacked record + CNV_CSC_CLAMP_UPPER_G:bit16; + CNV_CSC_CLAMP_LOWER_G:bit16; + end; + + TCNV_CSC_CLAMP_R=bitpacked record + CNV_CSC_CLAMP_UPPER_R:bit16; + CNV_CSC_CLAMP_LOWER_R:bit16; + end; + + TCNV_CSC_CONTROL=bitpacked record + CNV_CSC_BYPASS:bit1; + RESERVED0 :bit31; + end; + + TCNV_SOURCE_SIZE=bitpacked record + CNV_SOURCE_WIDTH :bit15; + RESERVED0 :bit1; + CNV_SOURCE_HEIGHT:bit15; + RESERVED1 :bit1; + end; + + TCNV_WINDOW_SIZE=bitpacked record + CNV_WINDOW_WIDTH :bit12; + RESERVED0 :bit4; + CNV_WINDOW_HEIGHT:bit12; + RESERVED1 :bit4; + end; + TCOMPUTE_NOWHERE=bit32; TCOMPUTE_START_X=bit32; @@ -3749,6 +16820,8 @@ type TCOMPUTE_START_Z=bit32; + TCONFIG_RESERVED=bit32; + TCPC_INT_CNTX_ID=bitpacked record CNTX_ID :bit28; QUEUE_ID :bit3; @@ -3844,6 +16917,16 @@ type RESERVED1 :bit8; end; + TCP_ME_RAM_RADDR=bitpacked record + ME_RAM_RADDR:bit13; + RESERVED0 :bit19; + end; + + TCP_ME_RAM_WADDR=bitpacked record + ME_RAM_WADDR:bit13; + RESERVED0 :bit19; + end; + TCP_PERFMON_CNTL=bitpacked record PERFMON_STATE :bit4; SPM_PERFMON_STATE :bit4; @@ -3852,6 +16935,11 @@ type RESERVED0 :bit21; end; + TCP_RB_RPTR_ADDR=bitpacked record + RB_RPTR_SWAP:bit2; + RB_RPTR_ADDR:bit30; + end; + TCP_ROQ_IB1_STAT=bitpacked record ROQ_RPTR_INDIRECT1:bit10; RESERVED0 :bit6; @@ -3879,6 +16967,89 @@ type RESERVED0 :bit12; end; + TCRTC_GSL_WINDOW=bitpacked record + CRTC_GSL_WINDOW_START:bit14; + RESERVED0 :bit2; + CRTC_GSL_WINDOW_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_MVP_STATUS=bitpacked record + CRTC_FLIP_NOW_OCCURRED :bit1; + RESERVED0 :bit3; + CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED:bit1; + RESERVED1 :bit11; + CRTC_FLIP_NOW_CLEAR :bit1; + RESERVED2 :bit3; + CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR :bit1; + RESERVED3 :bit11; + end; + + TCRTC_TRIGA_CNTL=bitpacked record + CRTC_TRIGA_SOURCE_SELECT :bit5; + CRTC_TRIGA_POLARITY_SELECT :bit3; + CRTC_TRIGA_RESYNC_BYPASS_EN :bit1; + CRTC_TRIGA_INPUT_STATUS :bit1; + CRTC_TRIGA_POLARITY_STATUS :bit1; + CRTC_TRIGA_OCCURRED :bit1; + CRTC_TRIGA_RISING_EDGE_DETECT_CNTL :bit2; + RESERVED0 :bit2; + CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL:bit2; + RESERVED1 :bit2; + CRTC_TRIGA_FREQUENCY_SELECT :bit2; + RESERVED2 :bit2; + CRTC_TRIGA_DELAY :bit5; + RESERVED3 :bit2; + CRTC_TRIGA_CLEAR :bit1; + end; + + TCRTC_TRIGB_CNTL=bitpacked record + CRTC_TRIGB_SOURCE_SELECT :bit5; + CRTC_TRIGB_POLARITY_SELECT :bit3; + CRTC_TRIGB_RESYNC_BYPASS_EN :bit1; + CRTC_TRIGB_INPUT_STATUS :bit1; + CRTC_TRIGB_POLARITY_STATUS :bit1; + CRTC_TRIGB_OCCURRED :bit1; + CRTC_TRIGB_RISING_EDGE_DETECT_CNTL :bit2; + RESERVED0 :bit2; + CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL:bit2; + RESERVED1 :bit2; + CRTC_TRIGB_FREQUENCY_SELECT :bit2; + RESERVED2 :bit2; + CRTC_TRIGB_DELAY :bit5; + RESERVED3 :bit2; + CRTC_TRIGB_CLEAR :bit1; + end; + + TDAC_CRC_CONTROL=bitpacked record + DAC_CRC_FIELD :bit1; + RESERVED0 :bit7; + DAC_CRC_ONLY_BLANKB:bit1; + RESERVED1 :bit23; + end; + + TDAC_CRC_SIG_RGB=bitpacked record + DAC_CRC_SIG_BLUE :bit10; + DAC_CRC_SIG_GREEN:bit10; + DAC_CRC_SIG_RED :bit10; + RESERVED0 :bit2; + end; + + TDAC_FIFO_STATUS=bitpacked record + RESERVED0 :bit1; + DAC_FIFO_USE_OVERWRITE_LEVEL:bit1; + DAC_FIFO_OVERWRITE_LEVEL :bit6; + RESERVED1 :bit2; + DAC_FIFO_CAL_AVERAGE_LEVEL :bit6; + DAC_FIFO_MAXIMUM_LEVEL :bit4; + RESERVED2 :bit2; + DAC_FIFO_MINIMUM_LEVEL :bit4; + RESERVED3 :bit3; + DAC_FIFO_CALIBRATED :bit1; + DAC_FIFO_FORCE_RECAL_AVERAGE:bit1; + DAC_FIFO_FORCE_RECOMP_MINMAX:bit1; + end; + TDB_CREDIT_LIMIT=bitpacked record DB_SC_TILE_CREDITS :bit5; DB_SC_QUAD_CREDITS :bit5; @@ -3941,6 +17112,514 @@ type TDB_Z_WRITE_BASE=bit32; + TDCCG_CAC_STATUS=bit32; + + TDCCG_SOFT_RESET=bitpacked record + REFCLK_SOFT_RESET :bit1; + PCIE_REFCLK_SOFT_RESET :bit1; + SOFT_RESET_DVO :bit1; + DVO_ENABLE_RST :bit1; + AUDIO_DTO2_CLK_SOFT_RESET:bit1; + RESERVED0 :bit3; + DPREFCLK_SOFT_RESET :bit1; + RESERVED1 :bit3; + AMCLK0_SOFT_RESET :bit1; + AMCLK1_SOFT_RESET :bit1; + P0PLL_CFG_IF_SOFT_RESET :bit1; + P1PLL_CFG_IF_SOFT_RESET :bit1; + P2PLL_CFG_IF_SOFT_RESET :bit1; + A0PLL_CFG_IF_SOFT_RESET :bit1; + A1PLL_CFG_IF_SOFT_RESET :bit1; + C0PLL_CFG_IF_SOFT_RESET :bit1; + C1PLL_CFG_IF_SOFT_RESET :bit1; + C2PLL_CFG_IF_SOFT_RESET :bit1; + RESERVED2 :bit10; + end; + + TDCCG_VPCLK_CNTL=bitpacked record + DCCG_VPCLK_POL:bit1; + RESERVED0 :bit31; + end; + + TDCE_VCE_CONTROL=bitpacked record + DC_VCE_VIDEO_PIPE_SELECT :bit3; + RESERVED0 :bit1; + DC_VCE_AUDIO_STREAM_SELECT:bit3; + RESERVED1 :bit25; + end; + + TDCFE_DBG_CONFIG=bitpacked record + DCFE_DBG_EN :bit1; + RESERVED0 :bit3; + DCFE_DBG_SEL:bit4; + RESERVED1 :bit24; + end; + + TDCFE_SOFT_RESET=bitpacked record + DCP_PIXPIPE_SOFT_RESET:bit1; + DCP_REQ_SOFT_RESET :bit1; + SCL_ALU_SOFT_RESET :bit1; + SCL_SOFT_RESET :bit1; + CRTC_SOFT_RESET :bit1; + RESERVED0 :bit27; + end; + + TDCIO_CLOCK_CNTL=bitpacked record + DCIO_TEST_CLK_SEL :bit5; + DISPCLK_R_DCIO_GATE_DIS:bit1; + RESERVED0 :bit2; + DISPCLK_R_DCIO_RAMP_DIS:bit1; + RESERVED1 :bit23; + end; + + TDCIO_SOFT_RESET=bitpacked record + UNIPHYA_SOFT_RESET:bit1; + DSYNCA_SOFT_RESET :bit1; + UNIPHYB_SOFT_RESET:bit1; + DSYNCB_SOFT_RESET :bit1; + UNIPHYC_SOFT_RESET:bit1; + DSYNCC_SOFT_RESET :bit1; + UNIPHYD_SOFT_RESET:bit1; + DSYNCD_SOFT_RESET :bit1; + UNIPHYE_SOFT_RESET:bit1; + DSYNCE_SOFT_RESET :bit1; + UNIPHYF_SOFT_RESET:bit1; + DSYNCF_SOFT_RESET :bit1; + UNIPHYG_SOFT_RESET:bit1; + DSYNCG_SOFT_RESET :bit1; + RESERVED0 :bit2; + DACA_SOFT_RESET :bit1; + RESERVED1 :bit3; + DCRXPHY_SOFT_RESET:bit1; + RESERVED2 :bit3; + DPHY_SOFT_RESET :bit1; + RESERVED3 :bit7; + end; + + TDCP_CRC_CONTROL=bitpacked record + DCP_CRC_ENABLE :bit1; + RESERVED0 :bit1; + DCP_CRC_SOURCE_SEL:bit3; + RESERVED1 :bit3; + DCP_CRC_LINE_SEL :bit2; + RESERVED2 :bit22; + end; + + TDCP_CRC_CURRENT=bit32; + + TDCP_GSL_CONTROL=bitpacked record + DCP_GSL0_EN :bit1; + DCP_GSL1_EN :bit1; + DCP_GSL2_EN :bit1; + RESERVED0 :bit5; + DCP_GSL_MODE :bit2; + RESERVED1 :bit2; + DCP_GSL_HSYNC_FLIP_FORCE_DELAY :bit4; + DCP_GSL_MASTER_EN :bit1; + DCP_GSL_XDMA_GROUP :bit2; + DCP_GSL_XDMA_GROUP_UNDERFLOW_EN :bit1; + RESERVED2 :bit4; + DCP_GSL_SYNC_SOURCE :bit2; + RESERVED3 :bit1; + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING:bit1; + DCP_GSL_HSYNC_FLIP_CHECK_DELAY :bit4; + end; + + TDC_DMCU_SCRATCH=bit32; + + TDC_GPIO_DDC1_EN=bitpacked record + DC_GPIO_DDC1CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC1DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC2_EN=bitpacked record + DC_GPIO_DDC2CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC2DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC3_EN=bitpacked record + DC_GPIO_DDC3CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC3DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC4_EN=bitpacked record + DC_GPIO_DDC4CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC4DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC5_EN=bitpacked record + DC_GPIO_DDC5CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC5DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDC6_EN=bitpacked record + DC_GPIO_DDC6CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDC6DATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_GENLK_A=bitpacked record + DC_GPIO_GENLK_CLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_GENLK_VSYNC_A:bit1; + RESERVED1 :bit7; + DC_GPIO_SWAPLOCK_A_A :bit1; + RESERVED2 :bit7; + DC_GPIO_SWAPLOCK_B_A :bit1; + RESERVED3 :bit7; + end; + + TDC_GPIO_GENLK_Y=bitpacked record + DC_GPIO_GENLK_CLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_GENLK_VSYNC_Y:bit1; + RESERVED1 :bit7; + DC_GPIO_SWAPLOCK_A_Y :bit1; + RESERVED2 :bit7; + DC_GPIO_SWAPLOCK_B_Y :bit1; + RESERVED3 :bit7; + end; + + TDC_GPIO_SYNCA_A=bitpacked record + DC_GPIO_HSYNCA_A:bit1; + RESERVED0 :bit7; + DC_GPIO_VSYNCA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_SYNCA_Y=bitpacked record + DC_GPIO_HSYNCA_Y:bit1; + RESERVED0 :bit7; + DC_GPIO_VSYNCA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD1_CONTROL=bitpacked record + DC_HPD1_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD1_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD1_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_HPD2_CONTROL=bitpacked record + DC_HPD2_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD2_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD2_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_HPD3_CONTROL=bitpacked record + DC_HPD3_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD3_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD3_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_HPD4_CONTROL=bitpacked record + DC_HPD4_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD4_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD4_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_HPD5_CONTROL=bitpacked record + DC_HPD5_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD5_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD5_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_HPD6_CONTROL=bitpacked record + DC_HPD6_CONNECTION_TIMER:bit13; + RESERVED0 :bit3; + DC_HPD6_RX_INT_TIMER :bit10; + RESERVED1 :bit2; + DC_HPD6_EN :bit1; + RESERVED2 :bit3; + end; + + TDC_LUT_30_COLOR=bitpacked record + DC_LUT_COLOR_10_BLUE :bit10; + DC_LUT_COLOR_10_GREEN:bit10; + DC_LUT_COLOR_10_RED :bit10; + RESERVED0 :bit2; + end; + + TDC_LUT_AUTOFILL=bitpacked record + DC_LUT_AUTOFILL :bit1; + DC_LUT_AUTOFILL_DONE:bit1; + RESERVED0 :bit30; + end; + + TDC_LUT_PWL_DATA=bitpacked record + DC_LUT_BASE :bit16; + DC_LUT_DELTA:bit16; + end; + + TDC_LUT_RW_INDEX=bitpacked record + DC_LUT_RW_INDEX:bit8; + RESERVED0 :bit24; + end; + + TDC_REF_CLK_CNTL=bitpacked record + HSYNCA_OUTPUT_SEL :bit2; + RESERVED0 :bit6; + GENLK_CLK_OUTPUT_SEL:bit2; + RESERVED1 :bit22; + end; + + TDEGAMMA_CONTROL=bitpacked record + GRPH_DEGAMMA_MODE :bit2; + RESERVED0 :bit2; + OVL_DEGAMMA_MODE :bit2; + RESERVED1 :bit2; + CURSOR2_DEGAMMA_MODE:bit2; + RESERVED2 :bit2; + CURSOR_DEGAMMA_MODE :bit2; + RESERVED3 :bit18; + end; + + TDIG_FIFO_STATUS=bitpacked record + DIG_FIFO_LEVEL_ERROR :bit1; + DIG_FIFO_USE_OVERWRITE_LEVEL:bit1; + DIG_FIFO_OVERWRITE_LEVEL :bit6; + DIG_FIFO_ERROR_ACK :bit1; + RESERVED0 :bit1; + DIG_FIFO_CAL_AVERAGE_LEVEL :bit6; + DIG_FIFO_MAXIMUM_LEVEL :bit5; + RESERVED1 :bit1; + DIG_FIFO_MINIMUM_LEVEL :bit4; + RESERVED2 :bit3; + DIG_FIFO_CALIBRATED :bit1; + DIG_FIFO_FORCE_RECAL_AVERAGE:bit1; + DIG_FIFO_FORCE_RECOMP_MINMAX:bit1; + end; + + TDIG_LANE_ENABLE=bitpacked record + DIG_LANE0EN:bit1; + DIG_LANE1EN:bit1; + DIG_LANE2EN:bit1; + DIG_LANE3EN:bit1; + RESERVED0 :bit4; + DIG_CLK_EN :bit1; + RESERVED1 :bit23; + end; + + TDISPPLL_BG_CNTL=bitpacked record + DISPPLL_BG_PDN:bit1; + RESERVED0 :bit3; + DISPPLL_BG_ADJ:bit4; + RESERVED1 :bit24; + end; + + TDPDBG_INTERRUPT=bitpacked record + DPDBG_FIFO_OVERFLOW_INT_MASK :bit1; + DPDBG_FIFO_OVERFLOW_INT_TYPE :bit1; + RESERVED0 :bit6; + DPDBG_FIFO_OVERFLOW_INT_ACK :bit1; + RESERVED1 :bit7; + DPDBG_FIFO_OVERFLOW_OCCURRED :bit1; + RESERVED2 :bit7; + DPDBG_FIFO_OVERFLOW_INT_STATUS:bit1; + RESERVED3 :bit7; + end; + + TDPG_HW_DEBUG_11=bitpacked record + DPG_HW_DEBUG_11:bit1; + RESERVED0 :bit31; + end; + + TDP_AUX1_DEBUG_A=bit32; + + TDP_AUX1_DEBUG_B=bit32; + + TDP_AUX1_DEBUG_C=bit32; + + TDP_AUX1_DEBUG_D=bit32; + + TDP_AUX1_DEBUG_E=bit32; + + TDP_AUX1_DEBUG_F=bit32; + + TDP_AUX1_DEBUG_G=bit32; + + TDP_AUX1_DEBUG_H=bit32; + + TDP_AUX1_DEBUG_I=bit32; + + TDP_AUX2_DEBUG_A=bit32; + + TDP_AUX2_DEBUG_B=bit32; + + TDP_AUX2_DEBUG_C=bit32; + + TDP_AUX2_DEBUG_D=bit32; + + TDP_AUX2_DEBUG_E=bit32; + + TDP_AUX2_DEBUG_F=bit32; + + TDP_AUX2_DEBUG_G=bit32; + + TDP_AUX2_DEBUG_H=bit32; + + TDP_AUX2_DEBUG_I=bit32; + + TDP_AUX3_DEBUG_A=bit32; + + TDP_AUX3_DEBUG_B=bit32; + + TDP_AUX3_DEBUG_C=bit32; + + TDP_AUX3_DEBUG_D=bit32; + + TDP_AUX3_DEBUG_E=bit32; + + TDP_AUX3_DEBUG_F=bit32; + + TDP_AUX3_DEBUG_G=bit32; + + TDP_AUX3_DEBUG_H=bit32; + + TDP_AUX3_DEBUG_I=bit32; + + TDP_AUX4_DEBUG_A=bit32; + + TDP_AUX4_DEBUG_B=bit32; + + TDP_AUX4_DEBUG_C=bit32; + + TDP_AUX4_DEBUG_D=bit32; + + TDP_AUX4_DEBUG_E=bit32; + + TDP_AUX4_DEBUG_F=bit32; + + TDP_AUX4_DEBUG_G=bit32; + + TDP_AUX4_DEBUG_H=bit32; + + TDP_AUX4_DEBUG_I=bit32; + + TDP_AUX5_DEBUG_A=bit32; + + TDP_AUX5_DEBUG_B=bit32; + + TDP_AUX5_DEBUG_C=bit32; + + TDP_AUX5_DEBUG_D=bit32; + + TDP_AUX5_DEBUG_E=bit32; + + TDP_AUX5_DEBUG_F=bit32; + + TDP_AUX5_DEBUG_G=bit32; + + TDP_AUX5_DEBUG_H=bit32; + + TDP_AUX5_DEBUG_I=bit32; + + TDP_AUX6_DEBUG_A=bit32; + + TDP_AUX6_DEBUG_B=bit32; + + TDP_AUX6_DEBUG_C=bit32; + + TDP_AUX6_DEBUG_D=bit32; + + TDP_AUX6_DEBUG_E=bit32; + + TDP_AUX6_DEBUG_F=bit32; + + TDP_AUX6_DEBUG_G=bit32; + + TDP_AUX6_DEBUG_H=bit32; + + TDP_AUX6_DEBUG_I=bit32; + + TDP_PIXEL_FORMAT=bitpacked record + DP_PIXEL_ENCODING :bit3; + RESERVED0 :bit5; + DP_DYN_RANGE :bit1; + RESERVED1 :bit7; + DP_YCBCR_RANGE :bit1; + RESERVED2 :bit7; + DP_COMPONENT_DEPTH:bit3; + RESERVED3 :bit5; + end; + + TDP_SEC_FRAMING1=bitpacked record + DP_SEC_FRAME_START_LOCATION :bit12; + RESERVED0 :bit4; + DP_SEC_VBLANK_TRANSMIT_WIDTH:bit16; + end; + + TDP_SEC_FRAMING2=bitpacked record + DP_SEC_START_POSITION :bit16; + DP_SEC_HBLANK_TRANSMIT_WIDTH:bit16; + end; + + TDP_SEC_FRAMING3=bitpacked record + DP_SEC_IDLE_FRAME_SIZE :bit14; + RESERVED0 :bit2; + DP_SEC_IDLE_TRANSMIT_WIDTH:bit16; + end; + + TDP_SEC_FRAMING4=bitpacked record + RESERVED0 :bit20; + DP_SEC_COLLISION_STATUS :bit1; + RESERVED1 :bit3; + DP_SEC_COLLISION_ACK :bit1; + RESERVED2 :bit3; + DP_SEC_AUDIO_MUTE :bit1; + DP_SEC_AUDIO_MUTE_STATUS:bit1; + RESERVED3 :bit2; + end; + + TDP_VID_MSA_VBID=bitpacked record + DP_VID_MSA_LOCATION :bit12; + RESERVED0 :bit4; + DP_VID_MSA_TOP_FIELD_MODE:bit1; + RESERVED1 :bit7; + DP_VID_VBID_FIELD_POL :bit1; + RESERVED2 :bit7; + end; + + TDVO_SKEW_ADJUST=bit32; + + TGC_CAC_ACC_CU10=bit32; + + TGC_CAC_ACC_CU11=bit32; + + TGC_CAC_ACC_CU12=bit32; + + TGC_CAC_ACC_CU13=bit32; + + TGC_CAC_ACC_CU14=bit32; + + TGC_CAC_ACC_CU15=bit32; + TGDS_ATOM_SRC0_U=bit32; TGDS_ATOM_SRC1_U=bit32; @@ -4140,6 +17819,987 @@ type CB_BUSY :bit1; end; + TGRPH_DFQ_STATUS=bitpacked record + GRPH_PRIMARY_DFQ_NUM_ENTRIES :bit4; + GRPH_SECONDARY_DFQ_NUM_ENTRIES:bit4; + GRPH_DFQ_RESET_FLAG :bit1; + GRPH_DFQ_RESET_ACK :bit1; + RESERVED0 :bit22; + end; + + THDP_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + THDP_XDP_HST_CFG=bitpacked record + HST_CFG_WR_COMBINE_EN :bit1; + HST_CFG_WR_COMBINE_TIMER:bit2; + RESERVED0 :bit29; + end; + + THDP_XDP_SID_CFG=bitpacked record + SID_CFG_WR_COMBINE_EN :bit1; + SID_CFG_WR_COMBINE_TIMER:bit2; + SID_CFG_FLNUM_MSB_SEL :bit2; + RESERVED0 :bit27; + end; + + TIH_LEVEL_STATUS=bitpacked record + DC_STATUS :bit1; + RESERVED0 :bit1; + ROM_STATUS :bit1; + SRBM_STATUS:bit1; + BIF_STATUS :bit1; + XDMA_STATUS:bit1; + RESERVED1 :bit26; + end; + + TIH_PERFMON_CNTL=bitpacked record + ENABLE0 :bit1; + CLEAR0 :bit1; + PERF_SEL0:bit6; + ENABLE1 :bit1; + CLEAR1 :bit1; + PERF_SEL1:bit6; + RESERVED0:bit16; + end; + + TIH_VF_RB_STATUS=bitpacked record + RB_FULL_DRAIN_VF:bit16; + RB_OVERFLOW_VF :bit16; + end; + + TINTERRUPT_CNTL2=bit32; + + TKEY_RANGE_ALPHA=bitpacked record + KEY_ALPHA_LOW :bit16; + KEY_ALPHA_HIGH:bit16; + end; + + TKEY_RANGE_GREEN=bitpacked record + KEY_GREEN_LOW :bit16; + KEY_GREEN_HIGH:bit16; + end; + + TLBV_DATA_FORMAT=bitpacked record + PIXEL_DEPTH :bit2; + PIXEL_EXPAN_MODE :bit1; + INTERLEAVE_EN :bit1; + PIXEL_REDUCE_MODE :bit1; + DYNAMIC_PIXEL_DEPTH :bit1; + DITHER_EN :bit1; + DOWNSCALE_PREFETCH_EN:bit1; + RESERVED0 :bit4; + PREFETCH :bit1; + RESERVED1 :bit11; + REQUEST_MODE :bit1; + RESERVED2 :bit6; + ALPHA_EN :bit1; + end; + + TLBV_MEMORY_CTRL=bitpacked record + LB_MEMORY_SIZE :bit12; + RESERVED0 :bit4; + LB_NUM_PARTITIONS:bit4; + LB_MEMORY_CONFIG :bit2; + RESERVED1 :bit10; + end; + + TLB_VLINE_STATUS=bitpacked record + VLINE_OCCURRED :bit1; + RESERVED0 :bit3; + VLINE_ACK :bit1; + RESERVED1 :bit7; + VLINE_STAT :bit1; + RESERVED2 :bit3; + VLINE_INTERRUPT :bit1; + VLINE_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLM_POWERCONTROL=bitpacked record + LMTxPhyCmd0 :bit3; + LMRxPhyCmd0 :bit3; + LMLinkSpeed0:bit2; + LMTxPhyCmd1 :bit3; + LMRxPhyCmd1 :bit3; + LMLinkSpeed1:bit2; + LMTxPhyCmd2 :bit3; + LMRxPhyCmd2 :bit3; + LMLinkSpeed2:bit2; + LMTxPhyCmd3 :bit3; + LMRxPhyCmd3 :bit3; + LMLinkSpeed3:bit2; + end; + + TLNCNT_QUAN_THRD=bitpacked record + CFG_LNC_BW_QUAN_THRD0 :bit3; + RESERVED0 :bit1; + CFG_LNC_CMN_QUAN_THRD4:bit3; + RESERVED1 :bit25; + end; + + TMAILBOX_CONTROL=bitpacked record + TRN_MSG_VALID:bit1; + TRN_MSG_ACK :bit1; + RCV_MSG_VALID:bit1; + RCV_MSG_ACK :bit1; + RESERVED0 :bit28; + end; + + TMC_ARB_AGE_CNTL=bitpacked record + RESET_RD_GROUP0 :bit1; + RESET_RD_GROUP1 :bit1; + RESET_RD_GROUP2 :bit1; + RESET_RD_GROUP3 :bit1; + RESET_RD_GROUP4 :bit1; + RESET_RD_GROUP5 :bit1; + RESET_RD_GROUP6 :bit1; + RESET_RD_GROUP7 :bit1; + RESET_WR_GROUP0 :bit1; + RESET_WR_GROUP1 :bit1; + RESET_WR_GROUP2 :bit1; + RESET_WR_GROUP3 :bit1; + RESET_WR_GROUP4 :bit1; + RESET_WR_GROUP5 :bit1; + RESET_WR_GROUP6 :bit1; + RESET_WR_GROUP7 :bit1; + AGE_LOW_RATE_RD :bit3; + AGE_LOW_RATE_WR :bit3; + TIMER_STALL_RD :bit1; + TIMER_STALL_WR :bit1; + EXTEND_WEIGHT_RD:bit1; + EXTEND_WEIGHT_WR:bit1; + RESERVED0 :bit6; + end; + + TMC_ARB_CAC_CNTL=bitpacked record + ENABLE :bit1; + READ_WEIGHT :bit6; + WRITE_WEIGHT :bit6; + ALLOW_OVERFLOW:bit1; + RESERVED0 :bit18; + end; + + TMC_ARB_FED_CNTL=bitpacked record + MODE :bit2; + WR_ERR :bit2; + KEEP_POISON_IN_PAGE:bit1; + RDRET_PARITY_NACK :bit1; + USE_LEGACY_NACK :bit1; + DEBUG_RSV :bit25; + end; + + TMC_ARB_LAZY0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_LAZY0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_LAZY1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_LAZY1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_PERF_CID=bitpacked record + CH0 :bit8; + CH1 :bit8; + CH0_EN :bit1; + CH1_EN :bit1; + RESERVED0:bit14; + end; + + TMC_ARB_RTT_DATA=bitpacked record + PATTERN :bit8; + RESERVED0:bit24; + end; + + TMC_ARB_SQM_CNTL=bitpacked record + MIN_PENAL :bit8; + DYN_SQM_ENABLE:bit1; + SQM_RDY16 :bit1; + SQM_RESERVE :bit6; + RATIO :bit8; + RATIO_DEBUG :bit8; + end; + + TMC_HUB_RDREQ_CP=bitpacked record + RESERVED0:bit1; + RESERVED1:bit2; + RESERVED2:bit1; + RESERVED3:bit2; + RESERVED4:bit1; + RESERVED5:bit4; + RESERVED6:bit4; + RESERVED7:bit1; + RESERVED8:bit16; + end; + + TMC_HUB_WDP_ACPG=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_WDP_ACPO=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_WDP_CNTL=bitpacked record + RESERVED0 :bit1; + JUMPAHEAD_GBL0 :bit1; + JUMPAHEAD_GBL1 :bit1; + JUMPAHEAD_INTERNAL :bit1; + OVERRIDE_STALL_ENABLE :bit1; + DEBUG_REG :bit8; + DISABLE_SELF_INIT_GBL0 :bit1; + DISABLE_SELF_INIT_GBL1 :bit1; + DISABLE_SELF_INIT_INTERNAL:bit1; + FAIR_CH_SW :bit1; + LCLWRREQ_BYPASS :bit1; + DISP_WAIT_EOP :bit1; + MCD_WAIT_EOP :bit1; + SIP_WAIT_EOP :bit1; + UVD_VCE_WRITE_PRI_EN :bit1; + WRITE_PRI_EN :bit1; + IH_PHYSADDR_ENABLE :bit1; + RESERVED1 :bit8; + end; + + TMC_HUB_WDP_GBL0=bitpacked record + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_THRESHOLD :bit8; + STALL_MODE :bit1; + STALL_THRESHOLD_PRI:bit8; + STALL_THRESHOLD_URG:bit7; + end; + + TMC_HUB_WDP_GBL1=bitpacked record + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_THRESHOLD :bit8; + STALL_MODE :bit1; + STALL_THRESHOLD_PRI:bit8; + STALL_THRESHOLD_URG:bit7; + end; + + TMC_HUB_WDP_MCDS=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDT=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDU=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDV=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDW=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDX=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDY=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCDZ=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + STALL_MODE :bit1; + MAXBURST :bit4; + ASK_CREDITS :bit6; + LAZY_TIMER :bit4; + STALL_THRESHOLD:bit7; + ASK_CREDITS_W :bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_MCIF=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_VCE0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit13; + end; + + TMC_HUB_WDP_VCE1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit13; + end; + + TMC_HUB_WDP_VIN0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_VP8U=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_XDMA=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_MEM_POWER_LS=bitpacked record + LS_SETUP :bit6; + LS_HOLD :bit6; + RESERVED0:bit20; + end; + + TMC_PMG_CMD_EMRS=bitpacked record + ADR :bit16; + RESERVED0:bit4; + MOP :bit4; + _END :bit1; + RESERVED1:bit7; + end; + + TMC_PMG_CMD_MRS1=bitpacked record + ADR :bit16; + RESERVED0:bit4; + MOP :bit4; + _END :bit1; + RESERVED1:bit7; + end; + + TMC_PMG_CMD_MRS2=bitpacked record + ADR :bit16; + RESERVED0:bit4; + MOP :bit4; + _END :bit1; + RESERVED1:bit7; + end; + + TMC_RPB_ARB_CNTL=bitpacked record + WR_SWITCH_NUM :bit8; + RD_SWITCH_NUM :bit8; + ATC_SWITCH_NUM:bit8; + RESERVED0 :bit8; + end; + + TMC_RPB_BIF_CNTL=bitpacked record + ARB_SWITCH_NUM:bit8; + XPB_SWITCH_NUM:bit8; + RESERVED0 :bit1; + RESERVED1 :bit15; + end; + + TMC_RPB_EFF_CNTL=bitpacked record + WR_LAZY_TIMER:bit8; + RD_LAZY_TIMER:bit8; + RESERVED0 :bit16; + end; + + TMC_RPB_TCI_CNTL=bitpacked record + TCI_ENABLE :bit1; + TCI_POLICY :bit2; + TCI_VOL :bit1; + TCI_VMID :bit4; + TCI_REQ_CREDITS:bit8; + TCI_MAX_WRITES :bit8; + TCI_MAX_READS :bit8; + end; + + TMC_SEQ_FIFO_CTL=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit2; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit6; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit1; + RESERVED25:bit1; + end; + + TMC_SEQ_STATUS_M=bitpacked record + PWRUP_COMPL_D0 :bit1; + PWRUP_COMPL_D1 :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + CMD_RDY_D0 :bit1; + CMD_RDY_D1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + SEQ0_ARB_CMD_FIFO_EMPTY:bit1; + SEQ1_ARB_CMD_FIFO_EMPTY:bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + SEQ0_RS_DATA_FIFO_FULL :bit1; + SEQ1_RS_DATA_FIFO_FULL :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + SEQ0_BUSY :bit1; + SEQ1_BUSY :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit11; + RESERVED11 :bit1; + end; + + TMC_SEQ_STATUS_S=bitpacked record + SEQ0_ARB_DATA_FIFO_FULL:bit1; + SEQ1_ARB_DATA_FIFO_FULL:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + SEQ0_ARB_CMD_FIFO_FULL :bit1; + SEQ1_ARB_CMD_FIFO_FULL :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + SEQ0_RS_DATA_FIFO_EMPTY:bit1; + SEQ1_RS_DATA_FIFO_EMPTY:bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit20; + end; + + TMC_SEQ_SUP_CNTL=bitpacked record + RUN :bit1; + SINGLE_STEP:bit1; + SW_WAKE :bit1; + RESET_PC :bit1; + PGM_WRITE :bit1; + PGM_READ :bit1; + FAST_WRITE :bit1; + BKPT_CLEAR :bit1; + RESERVED0 :bit16; + PGM_CHKSUM :bit8; + end; + + TMC_SEQ_TIMER_RD=bit32; + + TMC_SEQ_TIMER_WR=bit32; + + TMC_SHARED_CHMAP=bitpacked record + CHAN0 :bit4; + CHAN1 :bit4; + CHAN2 :bit4; + NOOFCHAN :bit4; + CHAN3 :bit4; + CHAN4 :bit4; + RESERVED0:bit8; + end; + + TMC_VM_FB_OFFSET=bitpacked record + FB_OFFSET:bit18; + RESERVED0:bit14; + end; + + TMC_VM_MARC_CNTL=bitpacked record + ENABLE_ALL_CLIENTS:bit1; + RESERVED0 :bit31; + end; + + TMC_XBAR_TWOCHAN=bitpacked record + DISABLE_ONEPORT:bit1; + CH0 :bit2; + CH1 :bit2; + RESERVED0 :bit2; + RESERVED1 :bit2; + RESERVED2 :bit23; + end; + + TMC_XPB_CLG_CFG0=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG1=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG2=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG3=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG4=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG5=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG6=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG7=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG8=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG9=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_INTF_CFG=bitpacked record + RPB_WRREQ_CRD :bit8; + MC_WRRET_ASK :bit8; + XSP_REQ_CRD :bit7; + BIF_REG_SNOOP_SEL:bit1; + BIF_REG_SNOOP_VAL:bit1; + BIF_MEM_SNOOP_SEL:bit1; + BIF_MEM_SNOOP_VAL:bit1; + XSP_SNOOP_SEL :bit2; + XSP_SNOOP_VAL :bit1; + XSP_ORDERING_SEL :bit1; + XSP_ORDERING_VAL :bit1; + end; + + TMC_XPB_INTF_STS=bitpacked record + RPB_WRREQ_CRD :bit8; + XSP_REQ_CRD :bit7; + HOP_DATA_BUF_FULL:bit1; + HOP_ATTR_BUF_FULL:bit1; + CNS_BUF_FULL :bit1; + CNS_BUF_BUSY :bit1; + RPB_RDREQ_CRD :bit8; + RESERVED0 :bit5; + end; + + TMC_XPB_MISC_CFG=bitpacked record + FIELDNAME0 :bit8; + FIELDNAME1 :bit8; + FIELDNAME2 :bit8; + FIELDNAME3 :bit7; + TRIGGERNAME:bit1; + end; + + TMC_XPB_P2P_BAR0=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR1=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR2=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR3=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR4=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR5=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR6=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_P2P_BAR7=bitpacked record + HOST_FLUSH :bit4; + REG_SYS_BAR :bit4; + MEM_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_PIPE_STS=bitpacked record + WCB_ANY_PBUF :bit1; + WCB_HST_DATA_BUF_CNT :bit7; + WCB_SID_DATA_BUF_CNT :bit7; + WCB_HST_RD_PTR_BUF_FULL:bit1; + WCB_SID_RD_PTR_BUF_FULL:bit1; + WCB_HST_REQ_FIFO_FULL :bit1; + WCB_SID_REQ_FIFO_FULL :bit1; + WCB_HST_REQ_OBUF_FULL :bit1; + WCB_SID_REQ_OBUF_FULL :bit1; + WCB_HST_DATA_OBUF_FULL :bit1; + WCB_SID_DATA_OBUF_FULL :bit1; + RET_BUF_FULL :bit1; + XPB_CLK_BUSY_BITS :bit8; + end; + + TMC_XPB_SUB_CTRL=bitpacked record + WRREQ_BYPASS_XPB :bit1; + STALL_CNS_RTR_REQ :bit1; + STALL_RTR_RPB_WRREQ :bit1; + STALL_RTR_MAP_REQ :bit1; + STALL_MAP_WCB_REQ :bit1; + STALL_WCB_SID_REQ :bit1; + STALL_MC_XSP_REQ_SEND :bit1; + STALL_WCB_HST_REQ :bit1; + STALL_HST_HOP_REQ :bit1; + STALL_XPB_RPB_REQ_ATTR:bit1; + RESET_CNS :bit1; + RESET_RTR :bit1; + RESET_RET :bit1; + RESET_MAP :bit1; + RESET_WCB :bit1; + RESET_HST :bit1; + RESET_HOP :bit1; + RESET_SID :bit1; + RESET_SRB :bit1; + RESET_CGR :bit1; + RESERVED0 :bit12; + end; + + TMM_CFGREGS_CNTL=bitpacked record + MM_CFG_FUNC_SEL:bit3; + MM_WR_TO_CFG_EN:bit1; + RESERVED0 :bit28; + end; + + TMSI_MSG_ADDR_HI=bit32; + + TMSI_MSG_ADDR_LO=bitpacked record + RESERVED0 :bit2; + MSI_MSG_ADDR_LO:bit30; + end; + + TMSI_MSG_DATA_64=bitpacked record + MSI_DATA_64:bit16; + RESERVED0 :bit16; + end; + + TMVP_BLACK_KEYER=bitpacked record + MVP_BLACK_KEYER_R:bit10; + MVP_BLACK_KEYER_G:bit10; + MVP_BLACK_KEYER_B:bit10; + RESERVED0 :bit2; + end; + + TMVP_FIFO_STATUS=bitpacked record + MVP_FIFO_LEVEL :bit8; + MVP_FIFO_OVERFLOW :bit1; + RESERVED0 :bit3; + MVP_FIFO_OVERFLOW_OCCURRED :bit1; + RESERVED1 :bit3; + MVP_FIFO_OVERFLOW_ACK :bit1; + RESERVED2 :bit3; + MVP_FIFO_UNDERFLOW :bit1; + RESERVED3 :bit3; + MVP_FIFO_UNDERFLOW_OCCURRED:bit1; + RESERVED4 :bit3; + MVP_FIFO_UNDERFLOW_ACK :bit1; + RESERVED5 :bit1; + MVP_FIFO_ERROR_MASK :bit1; + MVP_FIFO_ERROR_INT_STATUS :bit1; + end; + + TOVL_DFQ_CONTROL=bitpacked record + OVL_DFQ_RESET :bit1; + RESERVED0 :bit3; + OVL_DFQ_SIZE :bit3; + RESERVED1 :bit1; + OVL_DFQ_MIN_FREE_ENTRIES:bit3; + RESERVED2 :bit21; + end; + TPA_CL_CLIP_CNTL=bitpacked record UCP_ENA_0 :bit1; UCP_ENA_1 :bit1; @@ -4200,6 +18860,562 @@ type RESERVED0:bit16; end; + TPB0_PIF_RX_CTRL=bitpacked record + RXPWR_IN_S2 :bit3; + RXPWR_IN_SPDCHNG :bit3; + RXPWR_IN_OFF :bit3; + RXPWR_IN_DEGRADE :bit3; + RXPWR_IN_UNUSED :bit3; + RXPWR_IN_INIT :bit3; + RXPWR_IN_PLL_OFF :bit3; + RXPWR_IN_DEGRADE_MODE :bit1; + RXPWR_IN_UNUSED_MODE :bit1; + RXPWR_GATING_IN_L1 :bit1; + RXPWR_GATING_IN_UNUSED :bit1; + RX_HLD_EIE_COUNT :bit1; + RX_EI_DET_IN_PS2_DEGRADE:bit1; + RESERVED0 :bit5; + end; + + TPB0_PIF_SCRATCH=bit32; + + TPB0_PIF_STRAP_0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_RDY_XTND_DIS :bit1; + STRAP_RX_RDY_XTND_DIS :bit1; + STRAP_TX_STATUS_XTND_DIS :bit1; + STRAP_RX_STATUS_XTND_DIS :bit1; + STRAP_FORCE_OWN_MSTR :bit1; + STRAP_PIF_CDR_EN_MODE :bit2; + STRAP_RX_EI_FILTER :bit2; + STRAP_RX_DIS_HLD_EIE_IN_PS1:bit1; + STRAP_RX_DIS_HLD_EIE_IN_PS2:bit1; + STRAP_PIF_BIT_12 :bit1; + STRAP_PIF_BIT_13 :bit1; + STRAP_PIF_BIT_14 :bit1; + STRAP_PIF_BIT_15 :bit1; + STRAP_PIF_BIT_16 :bit1; + RESERVED1 :bit15; + end; + + TPB0_PIF_TX_CTRL=bitpacked record + TXPWR_IN_S2 :bit3; + TXPWR_IN_SPDCHNG :bit3; + TXPWR_IN_OFF :bit3; + TXPWR_IN_DEGRADE :bit3; + TXPWR_IN_UNUSED :bit3; + TXPWR_IN_INIT :bit3; + TXPWR_IN_PLL_OFF :bit3; + TXPWR_IN_DEGRADE_MODE:bit1; + TXPWR_IN_UNUSED_MODE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit7; + end; + + TPB1_PIF_RX_CTRL=bitpacked record + RXPWR_IN_S2 :bit3; + RXPWR_IN_SPDCHNG :bit3; + RXPWR_IN_OFF :bit3; + RXPWR_IN_DEGRADE :bit3; + RXPWR_IN_UNUSED :bit3; + RXPWR_IN_INIT :bit3; + RXPWR_IN_PLL_OFF :bit3; + RXPWR_IN_DEGRADE_MODE :bit1; + RXPWR_IN_UNUSED_MODE :bit1; + RXPWR_GATING_IN_L1 :bit1; + RXPWR_GATING_IN_UNUSED :bit1; + RX_HLD_EIE_COUNT :bit1; + RX_EI_DET_IN_PS2_DEGRADE:bit1; + RESERVED0 :bit5; + end; + + TPB1_PIF_SCRATCH=bit32; + + TPB1_PIF_STRAP_0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_RDY_XTND_DIS :bit1; + STRAP_RX_RDY_XTND_DIS :bit1; + STRAP_TX_STATUS_XTND_DIS :bit1; + STRAP_RX_STATUS_XTND_DIS :bit1; + STRAP_FORCE_OWN_MSTR :bit1; + STRAP_PIF_CDR_EN_MODE :bit2; + STRAP_RX_EI_FILTER :bit2; + STRAP_RX_DIS_HLD_EIE_IN_PS1:bit1; + STRAP_RX_DIS_HLD_EIE_IN_PS2:bit1; + STRAP_PIF_BIT_12 :bit1; + STRAP_PIF_BIT_13 :bit1; + STRAP_PIF_BIT_14 :bit1; + STRAP_PIF_BIT_15 :bit1; + STRAP_PIF_BIT_16 :bit1; + RESERVED1 :bit15; + end; + + TPB1_PIF_TX_CTRL=bitpacked record + TXPWR_IN_S2 :bit3; + TXPWR_IN_SPDCHNG :bit3; + TXPWR_IN_OFF :bit3; + TXPWR_IN_DEGRADE :bit3; + TXPWR_IN_UNUSED :bit3; + TXPWR_IN_INIT :bit3; + TXPWR_IN_PLL_OFF :bit3; + TXPWR_IN_DEGRADE_MODE:bit1; + TXPWR_IN_UNUSED_MODE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit7; + end; + + TPCIEP_PORT_CNTL=bitpacked record + SLV_PORT_REQ_EN :bit1; + CI_SNOOP_OVERRIDE :bit1; + HOTPLUG_MSG_EN :bit1; + NATIVE_PME_EN :bit1; + PWR_FAULT_EN :bit1; + PMI_BM_DIS :bit1; + SEQNUM_DEBUG_MODE :bit1; + RESERVED0 :bit1; + CI_SLV_CPL_STATIC_ALLOC_LIMIT_S:bit7; + RESERVED1 :bit1; + CI_MAX_CPL_PAYLOAD_SIZE_MODE :bit2; + CI_PRIV_MAX_CPL_PAYLOAD_SIZE :bit3; + RESERVED2 :bit11; + end; + + TPCIE_DEBUG_CNTL=bitpacked record + DEBUG_PORT_EN:bit8; + DEBUG_SELECT :bit1; + RESERVED0 :bit7; + DEBUG_LANE_EN:bit16; + end; + + TPCIE_DPA_STATUS=bitpacked record + SUBSTATE_STATUS :bit5; + RESERVED0 :bit3; + SUBSTATE_CNTL_ENABLED:bit1; + RESERVED1 :bit23; + end; + + TPCIE_F0_DPA_CAP=bitpacked record + RESERVED0 :bit8; + TRANS_LAT_UNIT :bit2; + RESERVED1 :bit2; + PWR_ALLOC_SCALE:bit2; + RESERVED2 :bit2; + TRANS_LAT_VAL_0:bit8; + TRANS_LAT_VAL_1:bit8; + end; + + TPCIE_INT_STATUS=bitpacked record + CORR_ERR_INT_STATUS :bit1; + NON_FATAL_ERR_INT_STATUS :bit1; + FATAL_ERR_INT_STATUS :bit1; + USR_DETECTED_INT_STATUS :bit1; + MISC_ERR_INT_STATUS :bit1; + RESERVED0 :bit1; + POWER_STATE_CHG_INT_STATUS:bit1; + LINK_BW_INT_STATUS :bit1; + QUIESCE_RCVD_INT_STATUS :bit1; + RESERVED1 :bit23; + end; + + TPCIE_LC_STATE10=bitpacked record + LC_PREV_STATE40:bit6; + RESERVED0 :bit2; + LC_PREV_STATE41:bit6; + RESERVED1 :bit2; + LC_PREV_STATE42:bit6; + RESERVED2 :bit2; + LC_PREV_STATE43:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATE11=bitpacked record + LC_PREV_STATE44:bit6; + RESERVED0 :bit2; + LC_PREV_STATE45:bit6; + RESERVED1 :bit2; + LC_PREV_STATE46:bit6; + RESERVED2 :bit2; + LC_PREV_STATE47:bit6; + RESERVED3 :bit2; + end; + + TPCIE_LC_STATUS1=bitpacked record + LC_REVERSE_RCVR :bit1; + LC_REVERSE_XMIT :bit1; + LC_OPERATING_LINK_WIDTH:bit3; + LC_DETECTED_LINK_WIDTH :bit3; + RESERVED0 :bit24; + end; + + TPCIE_LC_STATUS2=bitpacked record + LC_TOTAL_INACTIVE_LANES:bit16; + LC_TURN_ON_LANE :bit16; + end; + + TPCIE_LINK_CNTL3=bitpacked record + PERFORM_EQUALIZATION :bit1; + LINK_EQUALIZATION_REQ_INT_EN:bit1; + RESERVED0 :bit30; + end; + + TPCIE_PASID_CNTL=bitpacked record + PASID_ENABLE :bit1; + PASID_EXE_PERMISSION_ENABLE :bit1; + PASID_PRIV_MODE_SUPPORTED_ENABLE:bit1; + RESERVED0 :bit29; + end; + + TPCIE_PORT_INDEX=bitpacked record + PCIE_INDEX:bit8; + RESERVED0 :bit24; + end; + + TPCIE_RX_NUM_NAK=bit32; + + TPCIE_STRAP_MISC=bitpacked record + STRAP_LINK_CONFIG :bit4; + STRAP_TL_ALT_BUF_EN :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + STRAP_MAX_PASID_WIDTH :bit5; + STRAP_PASID_EXE_PERMISSION_SUPPORTED :bit1; + STRAP_PASID_PRIV_MODE_SUPPORTED :bit1; + STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED:bit1; + RESERVED3 :bit8; + STRAP_CLK_PM_EN :bit1; + STRAP_ECN1P1_EN :bit1; + STRAP_EXT_VC_COUNT :bit1; + RESERVED4 :bit1; + STRAP_REVERSE_ALL :bit1; + STRAP_MST_ADR64_EN :bit1; + STRAP_FLR_EN :bit1; + STRAP_INTERNAL_ERR_EN :bit1; + end; + + TPEER_REG_RANGE0=bitpacked record + START_ADDR:bit16; + END_ADDR :bit16; + end; + + TPEER_REG_RANGE1=bitpacked record + START_ADDR:bit16; + END_ADDR :bit16; + end; + + TPIPE0_PG_CONFIG=bitpacked record + PIPE0_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE0_PG_ENABLE=bitpacked record + PIPE0_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE0_PG_STATUS=bitpacked record + PIPE0_PGFSM_READ_DATA :bit24; + PIPE0_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE0_DESIRED_PWR_STATE :bit1; + PIPE0_REQUESTED_PWR_STATE:bit1; + PIPE0_PGFSM_PWR_STATUS :bit2; + end; + + TPIPE1_PG_CONFIG=bitpacked record + PIPE1_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE1_PG_ENABLE=bitpacked record + PIPE1_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE1_PG_STATUS=bitpacked record + PIPE1_PGFSM_READ_DATA :bit24; + PIPE1_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE1_DESIRED_PWR_STATE :bit1; + PIPE1_REQUESTED_PWR_STATE:bit1; + PIPE1_PGFSM_PWR_STATUS :bit2; + end; + + TPIPE2_PG_CONFIG=bitpacked record + PIPE2_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE2_PG_ENABLE=bitpacked record + PIPE2_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE2_PG_STATUS=bitpacked record + PIPE2_PGFSM_READ_DATA :bit24; + PIPE2_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE2_DESIRED_PWR_STATE :bit1; + PIPE2_REQUESTED_PWR_STATE:bit1; + PIPE2_PGFSM_PWR_STATUS :bit2; + end; + + TPIPE3_PG_CONFIG=bitpacked record + PIPE3_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE3_PG_ENABLE=bitpacked record + PIPE3_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE3_PG_STATUS=bitpacked record + PIPE3_PGFSM_READ_DATA :bit24; + PIPE3_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE3_DESIRED_PWR_STATE :bit1; + PIPE3_REQUESTED_PWR_STATE:bit1; + PIPE3_PGFSM_PWR_STATUS :bit2; + end; + + TPIPE4_PG_CONFIG=bitpacked record + PIPE4_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE4_PG_ENABLE=bitpacked record + PIPE4_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE4_PG_STATUS=bitpacked record + PIPE4_PGFSM_READ_DATA :bit24; + PIPE4_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE4_DESIRED_PWR_STATE :bit1; + PIPE4_REQUESTED_PWR_STATE:bit1; + PIPE4_PGFSM_PWR_STATUS :bit2; + end; + + TPIPE5_PG_CONFIG=bitpacked record + PIPE5_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TPIPE5_PG_ENABLE=bitpacked record + PIPE5_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TPIPE5_PG_STATUS=bitpacked record + PIPE5_PGFSM_READ_DATA :bit24; + PIPE5_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + PIPE5_DESIRED_PWR_STATE :bit1; + PIPE5_REQUESTED_PWR_STATE:bit1; + PIPE5_PGFSM_PWR_STATUS :bit2; + end; + + TPLL_ANALOG_CNTL=bitpacked record + PLL_ANALOG_TEST_EN :bit1; + PLL_ANALOG_MUX_CNTL :bit4; + PLL_ANALOGOUT_MUX_CNTL:bit4; + PLL_REGREF_TRIM :bit5; + PLL_CALIB_FBDIV :bit3; + PLL_CALIB_FASTCAL :bit1; + PLL_TEST_SSAMP_EN :bit1; + RESERVED0 :bit13; + end; + + TPLL_UPDATE_CNTL=bitpacked record + PLL_UPDATE_PENDING :bit1; + RESERVED0 :bit7; + PLL_UPDATE_POINT :bit1; + RESERVED1 :bit7; + PLL_AUTO_RESET_DISABLE:bit1; + RESERVED2 :bit15; + end; + + TPLL_UPDATE_LOCK=bitpacked record + PLL_UPDATE_LOCK:bit1; + RESERVED0 :bit31; + end; + + TPMI_STATUS_CNTL=bitpacked record + POWER_STATE :bit2; + RESERVED0 :bit1; + NO_SOFT_RESET:bit1; + RESERVED1 :bit4; + PME_EN :bit1; + DATA_SELECT :bit4; + DATA_SCALE :bit2; + PME_STATUS :bit1; + RESERVED2 :bit6; + B2_B3_SUPPORT:bit1; + BUS_PWR_EN :bit1; + PMI_DATA :bit8; + end; + + TPWR_PCC_CONTROL=bitpacked record + PCC_POLARITY:bit1; + RESERVED0 :bit31; + end; + + TREGAMMA_CONTROL=bitpacked record + GRPH_REGAMMA_MODE:bit3; + RESERVED0 :bit1; + OVL_REGAMMA_MODE :bit3; + RESERVED1 :bit25; + end; + + TRLC_CSIB_LENGTH=bit32; + + TRLC_LB_CNTR_MAX=bit32; + + TRLC_SMU_COMMAND=bit32; + + TRLC_SMU_MESSAGE=bit32; + + TRLC_SMU_PG_CTRL=bitpacked record + START_PG:bit1; + SPARE :bit31; + end; + + TSCL_ALU_CONTROL=bitpacked record + SCL_ALU_DISABLE:bit1; + RESERVED0 :bit31; + end; + + TSCL_TAP_CONTROL=bitpacked record + SCL_V_NUM_OF_TAPS:bit3; + RESERVED0 :bit5; + SCL_H_NUM_OF_TAPS:bit4; + RESERVED1 :bit20; + end; + + TSDMA0_VF_ENABLE=bitpacked record + VF_ENABLE:bit1; + RESERVED0:bit31; + end; + + TSDMA0_VM_CTX_HI=bit32; + + TSDMA0_VM_CTX_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_VF_ENABLE=bitpacked record + VF_ENABLE:bit1; + RESERVED0:bit31; + end; + + TSDMA1_VM_CTX_HI=bit32; + + TSDMA1_VM_CTX_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA_PGFSM_READ=bitpacked record + VALUE :bit24; + RESERVED0:bit8; + end; + + TSEM_MCIF_CONFIG=bitpacked record + MC_REQ_SWAP :bit2; + MC_WRREQ_CREDIT:bit6; + MC_RDREQ_CREDIT:bit6; + RESERVED0 :bit18; + end; + + TSMBCLK_PAD_CNTL=bitpacked record + SMBCLK_PAD_A :bit1; + SMBCLK_PAD_SEL :bit1; + SMBCLK_PAD_MODE :bit1; + SMBCLK_PAD_SPARE :bit2; + SMBCLK_PAD_SN0 :bit1; + SMBCLK_PAD_SN1 :bit1; + SMBCLK_PAD_SN2 :bit1; + SMBCLK_PAD_SN3 :bit1; + SMBCLK_PAD_SLEW :bit1; + SMBCLK_PAD_WAKE :bit1; + SMBCLK_PAD_SCHMEN :bit1; + SMBCLK_PAD_CNTL_EN:bit1; + RESERVED0 :bit19; + end; + + TSMBDAT_PAD_CNTL=bitpacked record + SMBDAT_PAD_A :bit1; + SMBDAT_PAD_SEL :bit1; + SMBDAT_PAD_MODE :bit1; + SMBDAT_PAD_SPARE :bit2; + SMBDAT_PAD_SN0 :bit1; + SMBDAT_PAD_SN1 :bit1; + SMBDAT_PAD_SN2 :bit1; + SMBDAT_PAD_SN3 :bit1; + SMBDAT_PAD_SLEW :bit1; + SMBDAT_PAD_WAKE :bit1; + SMBDAT_PAD_SCHMEN :bit1; + SMBDAT_PAD_CNTL_EN:bit1; + RESERVED0 :bit19; + end; + + TSMC_IND_INDEX_0=bit32; + + TSMC_IND_INDEX_1=bit32; + + TSMC_IND_INDEX_2=bit32; + + TSMC_IND_INDEX_3=bit32; + + TSMC_IND_INDEX_4=bit32; + + TSMC_IND_INDEX_5=bit32; + + TSMC_IND_INDEX_6=bit32; + + TSMC_IND_INDEX_7=bit32; + + TSMU_IND_INDEX_0=bit32; + + TSMU_IND_INDEX_1=bit32; + + TSMU_IND_INDEX_2=bit32; + + TSMU_IND_INDEX_3=bit32; + + TSMU_IND_INDEX_4=bit32; + + TSMU_IND_INDEX_5=bit32; + + TSMU_IND_INDEX_6=bit32; + + TSMU_IND_INDEX_7=bit32; + + TSMU_PM_STATUS_0=bit32; + + TSMU_PM_STATUS_1=bit32; + + TSMU_PM_STATUS_2=bit32; + + TSMU_PM_STATUS_3=bit32; + + TSMU_PM_STATUS_4=bit32; + + TSMU_PM_STATUS_5=bit32; + + TSMU_PM_STATUS_6=bit32; + + TSMU_PM_STATUS_7=bit32; + + TSMU_PM_STATUS_8=bit32; + + TSMU_PM_STATUS_9=bit32; + TSPI_CONFIG_CNTL=bitpacked record GPR_WRITE_PRIORITY :bit21; EXP_PRIORITY_ORDER :bit3; @@ -4253,6 +19469,340 @@ type RESERVED0 :bit26; end; + TSPMI_C6_STATE_0=bitpacked record + SPMI_IF_C6_STATE_ENTERED :bit1; + SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY:bit1; + SPMI_IF_COUNTER_ADDRESS_C6 :bit15; + RESERVED0 :bit15; + end; + + TSPMI_FSM_BUSY_0=bitpacked record + FSM_BUSY :bit1; + RESERVED0:bit31; + end; + + TSPU_PORT_STATUS=bit32; + + TSQC_GATCL1_CNTL=bitpacked record + RESERVED :bit18; + DCACHE_INVALIDATE_ALL_VMID :bit1; + DCACHE_FORCE_MISS :bit1; + DCACHE_FORCE_IN_ORDER :bit1; + DCACHE_REDUCE_FIFO_DEPTH_BY_2:bit2; + DCACHE_REDUCE_CACHE_SIZE_BY_2:bit2; + ICACHE_INVALIDATE_ALL_VMID :bit1; + ICACHE_FORCE_MISS :bit1; + ICACHE_FORCE_IN_ORDER :bit1; + ICACHE_REDUCE_FIFO_DEPTH_BY_2:bit2; + ICACHE_REDUCE_CACHE_SIZE_BY_2:bit2; + end; + + TSQ_ALU_CLK_CTRL=bitpacked record + FORCE_CU_ON_SH0:bit16; + FORCE_CU_ON_SH1:bit16; + end; + + TSQ_HV_VMID_CTRL=bitpacked record + DEFAULT_VMID :bit4; + ALLOWED_VMID_MASK:bit16; + RESERVED0 :bit12; + end; + + TSQ_LDS_CLK_CTRL=bitpacked record + FORCE_CU_ON_SH0:bit16; + FORCE_CU_ON_SH1:bit16; + end; + + TSQ_TEX_CLK_CTRL=bitpacked record + FORCE_CU_ON_SH0:bit16; + FORCE_CU_ON_SH1:bit16; + end; + + TSQ_WAVE_EXEC_HI=bit32; + + TSQ_WAVE_EXEC_LO=bit32; + + TSQ_WAVE_IB_DBG0=bitpacked record + IBUF_ST :bit3; + PC_INVALID :bit1; + NEED_NEXT_DW :bit1; + NO_PREFETCH_CNT :bit3; + IBUF_RPTR :bit2; + IBUF_WPTR :bit2; + RESERVED0 :bit4; + INST_STR_ST :bit4; + MISC_CNT :bit4; + ECC_ST :bit2; + IS_HYB :bit1; + HYB_CNT :bit2; + KILL :bit1; + NEED_KILL_IFETCH:bit1; + RESERVED1 :bit1; + end; + + TSQ_WAVE_IB_DBG1=bitpacked record + IXNACK :bit1; + XNACK :bit1; + TA_NEED_RESET:bit1; + RESERVED0 :bit1; + XCNT :bit4; + QCNT :bit4; + RESERVED1 :bit20; + end; + + TSQ_WAVE_TRAPSTS=bitpacked record + EXCP :bit9; + RESERVED0 :bit1; + SAVECTX :bit1; + RESERVED1 :bit5; + EXCP_CYCLE:bit6; + RESERVED2 :bit7; + DP_RATE :bit3; + end; + + TSRBM_DEBUG_CNTL=bitpacked record + SRBM_DEBUG_INDEX:bit6; + RESERVED0 :bit26; + end; + + TSRBM_DEBUG_DATA=bit32; + + TSRBM_INT_STATUS=bitpacked record + RDERR_INT_STAT:bit1; + RAERR_INT_STAT:bit1; + RESERVED0 :bit30; + end; + + TSRBM_READ_ERROR=bitpacked record + RESERVED0 :bit2; + READ_ADDRESS :bit16; + READ_REQUESTER_SDMA3 :bit1; + READ_REQUESTER_SDMA2 :bit1; + READ_REQUESTER_VCE0 :bit1; + READ_REQUESTER_SDMA1 :bit1; + READ_REQUESTER_TST :bit1; + READ_REQUESTER_SAMMSP:bit1; + READ_REQUESTER_HI :bit1; + READ_REQUESTER_GRBM :bit1; + READ_REQUESTER_SMU :bit1; + READ_REQUESTER_SAMSCP:bit1; + READ_REQUESTER_SDMA :bit1; + READ_REQUESTER_UVD :bit1; + RESERVED1 :bit1; + READ_ERROR :bit1; + end; + + TSRBM_SOFT_RESET=bitpacked record + SOFT_RESET_ATCL2 :bit1; + SOFT_RESET_BIF :bit1; + SOFT_RESET_SDMA3 :bit1; + SOFT_RESET_SDMA2 :bit1; + SOFT_RESET_GIONB :bit1; + SOFT_RESET_DC :bit1; + SOFT_RESET_SDMA1 :bit1; + RESERVED0 :bit1; + SOFT_RESET_GRBM :bit1; + SOFT_RESET_HDP :bit1; + SOFT_RESET_IH :bit1; + SOFT_RESET_MC :bit1; + SOFT_RESET_CHUB :bit1; + SOFT_RESET_ESRAM :bit1; + SOFT_RESET_ROM :bit1; + SOFT_RESET_SEM :bit1; + SOFT_RESET_SMU :bit1; + SOFT_RESET_VMC :bit1; + SOFT_RESET_UVD :bit1; + SOFT_RESET_VP8 :bit1; + SOFT_RESET_SDMA :bit1; + SOFT_RESET_TST :bit1; + SOFT_RESET_REGBB :bit1; + SOFT_RESET_ODE :bit1; + SOFT_RESET_VCE0 :bit1; + SOFT_RESET_XDMA :bit1; + SOFT_RESET_ACP :bit1; + SOFT_RESET_SAMMSP:bit1; + SOFT_RESET_SAMSCP:bit1; + SOFT_RESET_GRN :bit1; + SOFT_RESET_ISP :bit1; + SOFT_RESET_VCE1 :bit1; + end; + + TSWRST_COMMAND_0=bitpacked record + RESERVED0 :bit15; + BIF_STRAPREG_RESET :bit1; + BIF0_GLOBAL_RESET :bit1; + BIF0_CALIB_RESET :bit1; + BIF0_CORE_RESET :bit1; + BIF0_REGISTER_RESET:bit1; + BIF0_PHY_RESET :bit1; + BIF0_STICKY_RESET :bit1; + BIF0_CONFIG_RESET :bit1; + RESERVED1 :bit9; + end; + + TSWRST_COMMAND_1=bitpacked record + SWITCHCLK :bit1; + RESERVED0 :bit1; + RESETLANEMUX :bit1; + RESETWRAPREGS:bit1; + RESETSRBM0 :bit1; + RESETSRBM1 :bit1; + RESETLC :bit1; + RESERVED1 :bit1; + SYNCIDLEPIF0 :bit1; + SYNCIDLEPIF1 :bit1; + RESERVED2 :bit3; + RESETMNTR :bit1; + RESETHLTR :bit1; + RESETCPM :bit1; + RESETPIF0 :bit1; + RESETPIF1 :bit1; + RESERVED3 :bit2; + RESETIMPARB0 :bit1; + RESETIMPARB1 :bit1; + RESERVED4 :bit2; + RESETPHY0 :bit1; + RESETPHY1 :bit1; + RESERVED5 :bit2; + TOGGLESTRAP :bit1; + CMDCFGEN :bit1; + RESERVED6 :bit2; + end; + + TSWRST_CONTROL_0=bitpacked record + RESERVED0 :bit15; + BIF_STRAPREG_RESETRCEN :bit1; + BIF0_GLOBAL_RESETRCEN :bit1; + BIF0_CALIB_RESETRCEN :bit1; + BIF0_CORE_RESETRCEN :bit1; + BIF0_REGISTER_RESETRCEN:bit1; + BIF0_PHY_RESETRCEN :bit1; + BIF0_STICKY_RESETRCEN :bit1; + BIF0_CONFIG_RESETRCEN :bit1; + RESERVED1 :bit9; + end; + + TSWRST_CONTROL_1=bitpacked record + SWITCHCLK_RCEN :bit1; + RESERVED0 :bit1; + RESETLANEMUX_RCEN :bit1; + RESETWRAPREGS_RCEN:bit1; + RESETSRBM0_RCEN :bit1; + RESETSRBM1_RCEN :bit1; + RESETLC_RCEN :bit1; + RESERVED1 :bit1; + SYNCIDLEPIF0_RCEN :bit1; + SYNCIDLEPIF1_RCEN :bit1; + RESERVED2 :bit3; + RESETMNTR_RCEN :bit1; + RESETHLTR_RCEN :bit1; + RESETCPM_RCEN :bit1; + RESETPIF0_RCEN :bit1; + RESETPIF1_RCEN :bit1; + RESERVED3 :bit2; + RESETIMPARB0_RCEN :bit1; + RESETIMPARB1_RCEN :bit1; + RESERVED4 :bit2; + RESETPHY0_RCEN :bit1; + RESETPHY1_RCEN :bit1; + RESERVED5 :bit2; + STRAPVLD_RCEN :bit1; + CMDCFG_RCEN :bit1; + RESERVED6 :bit2; + end; + + TSWRST_CONTROL_2=bitpacked record + RESERVED0 :bit15; + BIF_STRAPREG_RESETATEN :bit1; + BIF0_GLOBAL_RESETATEN :bit1; + BIF0_CALIB_RESETATEN :bit1; + BIF0_CORE_RESETATEN :bit1; + BIF0_REGISTER_RESETATEN:bit1; + BIF0_PHY_RESETATEN :bit1; + BIF0_STICKY_RESETATEN :bit1; + BIF0_CONFIG_RESETATEN :bit1; + RESERVED1 :bit9; + end; + + TSWRST_CONTROL_3=bitpacked record + SWITCHCLK_ATEN :bit1; + RESERVED0 :bit1; + RESETLANEMUX_ATEN :bit1; + RESETWRAPREGS_ATEN:bit1; + RESETSRBM0_ATEN :bit1; + RESETSRBM1_ATEN :bit1; + RESETLC_ATEN :bit1; + RESERVED1 :bit1; + SYNCIDLEPIF0_ATEN :bit1; + SYNCIDLEPIF1_ATEN :bit1; + RESERVED2 :bit3; + RESETMNTR_ATEN :bit1; + RESETHLTR_ATEN :bit1; + RESETCPM_ATEN :bit1; + RESETPIF0_ATEN :bit1; + RESETPIF1_ATEN :bit1; + RESERVED3 :bit2; + RESETIMPARB0_ATEN :bit1; + RESETIMPARB1_ATEN :bit1; + RESERVED4 :bit2; + RESETPHY0_ATEN :bit1; + RESETPHY1_ATEN :bit1; + RESERVED5 :bit2; + STRAPVLD_ATEN :bit1; + CMDCFG_ATEN :bit1; + RESERVED6 :bit2; + end; + + TSWRST_CONTROL_4=bitpacked record + RESERVED0 :bit14; + BIF_STRAPREG_WRRESETEN :bit1; + RESERVED1 :bit1; + BIF0_GLOBAL_WRRESETEN :bit1; + BIF0_CALIB_WRRESETEN :bit1; + BIF0_CORE_WRRESETEN :bit1; + BIF0_REGISTER_WRRESETEN:bit1; + BIF0_PHY_WRRESETEN :bit1; + BIF0_STICKY_WRRESETEN :bit1; + BIF0_CONFIG_WRRESETEN :bit1; + RESERVED2 :bit9; + end; + + TSWRST_CONTROL_5=bitpacked record + WRSWITCHCLK_EN :bit1; + RESERVED0 :bit1; + WRRESETLANEMUX_EN :bit1; + WRRESETWRAPREGS_EN:bit1; + WRRESETSRBM0_EN :bit1; + WRRESETSRBM1_EN :bit1; + WRRESETLC_EN :bit1; + RESERVED1 :bit1; + WRSYNCIDLEPIF0_EN :bit1; + WRSYNCIDLEPIF1_EN :bit1; + RESERVED2 :bit3; + WRRESETMNTR_EN :bit1; + WRRESETHLTR_EN :bit1; + WRRESETCPM_EN :bit1; + WRRESETPIF0_EN :bit1; + WRRESETPIF1_EN :bit1; + RESERVED3 :bit2; + WRRESETIMPARB0_EN :bit1; + WRRESETIMPARB1_EN :bit1; + RESERVED4 :bit2; + WRRESETPHY0_EN :bit1; + WRRESETPHY1_EN :bit1; + RESERVED5 :bit2; + WRSTRAPVLD_EN :bit1; + WRCMDCFG_EN :bit1; + RESERVED6 :bit2; + end; + + TSWRST_CONTROL_6=bitpacked record + WARMRESET_EN :bit1; + RESERVED0 :bit7; + CONNECTWITHWRAPREGS_EN:bit1; + RESERVED1 :bit23; + end; + TSX_DEBUG_BUSY_2=bitpacked record COL_SCBD_BUSY :bit1; COL_REQ3_FREECNT_NE0 :bit1; @@ -4409,6 +19959,203 @@ type VALID:bit1; end; + TTHM_TMON0_DEBUG=bitpacked record + DEBUG_RDI:bit5; + DEBUG_Z :bit11; + RESERVED0:bit16; + end; + + TTHM_TMON1_DEBUG=bitpacked record + DEBUG_RDI:bit5; + DEBUG_Z :bit11; + RESERVED0:bit16; + end; + + TTHM_TMON2_CTRL2=bitpacked record + RDIL_PRESENT:bit16; + RDIR_PRESENT:bit16; + end; + + TTHM_TMON2_DEBUG=bitpacked record + DEBUG_RDI:bit5; + DEBUG_Z :bit11; + RESERVED0:bit16; + end; + + TUNIPHY_TPG_SEED=bitpacked record + UNIPHY_TPG_SEED:bit23; + RESERVED0 :bit9; + end; + + TUNP_CRC_CONTROL=bitpacked record + UNP_CRC_ENABLE :bit1; + RESERVED0 :bit1; + UNP_CRC_SOURCE_SEL:bit3; + RESERVED1 :bit3; + UNP_CRC_LINE_SEL :bit2; + RESERVED2 :bit22; + end; + + TUNP_CRC_CURRENT=bit32; + + TUNP_GRPH_ENABLE=bitpacked record + GRPH_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TUNP_GRPH_UPDATE=bitpacked record + GRPH_MODE_UPDATE_PENDING :bit1; + GRPH_MODE_UPDATE_TAKEN :bit1; + GRPH_SURFACE_UPDATE_PENDING :bit1; + GRPH_SURFACE_UPDATE_TAKEN :bit1; + RESERVED0 :bit12; + GRPH_UPDATE_LOCK :bit1; + RESERVED1 :bit3; + GRPH_SURFACE_IGNORE_UPDATE_LOCK :bit1; + RESERVED2 :bit3; + GRPH_MODE_DISABLE_MULTIPLE_UPDATE :bit1; + RESERVED3 :bit3; + GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE:bit1; + RESERVED4 :bit3; + end; + + TUNP_HW_ROTATION=bitpacked record + ROTATION_ANGLE:bit3; + RESERVED0 :bit1; + PIXEL_DROP :bit1; + RESERVED1 :bit3; + BUFFER_MODE :bit1; + RESERVED2 :bit23; + end; + + TUVD_ENGINE_CNTL=bitpacked record + ENGINE_START :bit1; + ENGINE_START_MODE:bit1; + RESERVED0 :bit30; + end; + + TUVD_MPC_SET_ALU=bitpacked record + FUNCT :bit3; + RESERVED0:bit1; + OPERAND :bit8; + RESERVED1:bit20; + end; + + TUVD_MPC_SET_MUX=bitpacked record + SET_0 :bit3; + SET_1 :bit3; + SET_2 :bit3; + RESERVED0:bit23; + end; + + TUVD_PGFSM_WRITE=bit32; + + TUVD_RBC_IB_BASE=bitpacked record + RESERVED0:bit6; + IB_BASE :bit26; + end; + + TUVD_RBC_IB_SIZE=bitpacked record + RESERVED0:bit4; + IB_SIZE :bit19; + RESERVED1:bit9; + end; + + TUVD_RBC_RB_BASE=bitpacked record + RESERVED0:bit6; + RB_BASE :bit26; + end; + + TUVD_RBC_RB_CNTL=bitpacked record + RB_BUFSZ :bit5; + RESERVED0 :bit3; + RB_BLKSZ :bit5; + RESERVED1 :bit3; + RB_NO_FETCH :bit1; + RESERVED2 :bit3; + RB_WPTR_POLL_EN:bit1; + RESERVED3 :bit3; + RB_NO_UPDATE :bit1; + RESERVED4 :bit3; + RB_RPTR_WR_EN :bit1; + RESERVED5 :bit3; + end; + + TUVD_RBC_RB_RPTR=bitpacked record + RESERVED0:bit4; + RB_RPTR :bit19; + RESERVED1:bit9; + end; + + TUVD_RBC_RB_WPTR=bitpacked record + RESERVED0:bit4; + RB_WPTR :bit19; + RESERVED1:bit9; + end; + + TVCE_OUT_RB_WPTR=bitpacked record + RESERVED0:bit4; + RESERVED1:bit19; + RESERVED2:bit9; + end; + + TVCE_RB_ARB_CTRL=bitpacked record + RESERVED0 :bit9; + RESERVED1 :bit7; + VCE_CGTT_OVERRIDE:bit1; + RESERVED2 :bit15; + end; + + TVCE_RB_BASE_HI2=bit32; + + TVCE_RB_BASE_HI3=bit32; + + TVCE_RB_BASE_LO2=bitpacked record + RESERVED0 :bit6; + RB_BASE_LO:bit26; + end; + + TVCE_RB_BASE_LO3=bitpacked record + RESERVED0 :bit6; + RB_BASE_LO:bit26; + end; + + TVCE_SYS_INT_ACK=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit2; + VCE_SYS_INT_TRAP_INTERRUPT_ACK:bit1; + RESERVED2 :bit1; + RESERVED3 :bit6; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit14; + end; + + TVENDOR_CAP_LIST=bitpacked record + CAP_ID :bit8; + NEXT_PTR :bit8; + LENGTH :bit8; + RESERVED0:bit8; + end; + + TVGA_HDP_CONTROL=bitpacked record + VGA_MEM_PAGE_SELECT_EN:bit1; + RESERVED0 :bit3; + VGA_MEMORY_DISABLE :bit1; + RESERVED1 :bit3; + VGA_RBBM_LOCK_DISABLE :bit1; + RESERVED2 :bit7; + VGA_SOFT_RESET :bit1; + RESERVED3 :bit7; + VGA_TEST_RESET_CONTROL:bit1; + RESERVED4 :bit7; + end; + TVGT_CNTL_STATUS=bitpacked record VGT_BUSY :bit1; VGT_OUT_INDX_BUSY:bit1; @@ -4837,6 +20584,39 @@ type use_stored_inner_q_ring3 :bit1; end; + TVGT_DEBUG_REG30=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit1; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit1; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit1; + RESERVED25:bit1; + RESERVED26:bit1; + RESERVED27:bit1; + RESERVED28:bit1; + RESERVED29:bit3; + end; + TVGT_DEBUG_REG31=bitpacked record pipe0_dr :bit1; pipe0_rtr :bit1; @@ -4968,6 +20748,16 @@ type use_stored_inner_q_ring1 :bit1; end; + TVGT_DEBUG_REG35=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit11; + RESERVED6:bit16; + end; + TVGT_DEBUG_REG36=bit32; TVGT_DMA_BASE_HI=bitpacked record @@ -5008,6 +20798,109 @@ type RESERVED0 :bit29; end; + TVLINE_START_END=bitpacked record + RESERVED0:bit14; + RESERVED1:bit2; + RESERVED2:bit14; + RESERVED3:bit1; + RESERVED4:bit1; + end; + + TXDMA_MSTR_CACHE=bitpacked record + XDMA_MSTR_CACHE_PITCH :bit14; + RESERVED0 :bit15; + XDMA_MSTR_CACHE_TLB_PG_STATE:bit2; + XDMA_MSTR_CACHE_TLB_PG_TRANS:bit1; + end; + + TXDMA_PG_CONTROL=bit32; + + TAFMT_AUDIO_INFO0=bitpacked record + AFMT_AUDIO_INFO_CHECKSUM :bit8; + AFMT_AUDIO_INFO_CC :bit3; + AFMT_AUDIO_INFO_CT :bit4; + RESERVED0 :bit1; + AFMT_AUDIO_INFO_CHECKSUM_OFFSET:bit8; + AFMT_AUDIO_INFO_CXT :bit5; + RESERVED1 :bit3; + end; + + TAFMT_AUDIO_INFO1=bitpacked record + AFMT_AUDIO_INFO_CA :bit8; + RESERVED0 :bit3; + AFMT_AUDIO_INFO_LSV :bit4; + AFMT_AUDIO_INFO_DM_INH:bit1; + AFMT_AUDIO_INFO_LFEPBL:bit2; + RESERVED1 :bit14; + end; + + TAFMT_GENERIC_HDR=bitpacked record + AFMT_GENERIC_HB0:bit8; + AFMT_GENERIC_HB1:bit8; + AFMT_GENERIC_HB2:bit8; + AFMT_GENERIC_HB3:bit8; + end; + + TAZALIA_AUDIO_DTO=bitpacked record + AZALIA_AUDIO_DTO_PHASE :bit16; + AZALIA_AUDIO_DTO_MODULE:bit16; + end; + + TBIF_BUSNUM_CNTL1=bitpacked record + ID_MASK :bit8; + RESERVED0:bit24; + end; + + TBIF_BUSNUM_CNTL2=bitpacked record + AUTOUPDATE_SEL :bit8; + AUTOUPDATE_EN :bit1; + RESERVED0 :bit7; + HDPREG_CNTL :bit1; + ERROR_MULTIPLE_ID_MATCH:bit1; + RESERVED1 :bit14; + end; + + TBIF_BUSNUM_LIST0=bitpacked record + ID0:bit8; + ID1:bit8; + ID2:bit8; + ID3:bit8; + end; + + TBIF_BUSNUM_LIST1=bitpacked record + ID4:bit8; + ID5:bit8; + ID6:bit8; + ID7:bit8; + end; + + TBIF_PERFMON_CNTL=bitpacked record + PERFCOUNTER_EN :bit1; + PERFCOUNTER_RESET0:bit1; + PERFCOUNTER_RESET1:bit1; + RESERVED0 :bit5; + PERF_SEL0 :bit5; + PERF_SEL1 :bit5; + RESERVED1 :bit14; + end; + + TBIF_PWDN_COMMAND=bitpacked record + REG_BU_pw_cmd :bit1; + REG_RWREG_RFEWDBIF_pw_cmd:bit1; + REG_SMBUS_pw_cmd :bit1; + REG_BX_pw_cmd :bit1; + RESERVED0 :bit28; + end; + + TBL1_PWM_ABM_CNTL=bitpacked record + BL1_PWM_USE_ABM_EN :bit1; + BL1_PWM_USE_AMBIENT_LEVEL_EN :bit1; + BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN :bit1; + BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN :bit1; + RESERVED0 :bit12; + BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE:bit16; + end; + TCB_COLOR0_ATTRIB=bitpacked record TILE_MODE_INDEX :bit5; FMASK_TILE_MODE_INDEX:bit5; @@ -5098,12 +20991,245 @@ type RESERVED2 :bit8; end; + TCC_DRM_ID_STRAPS=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + DEVICE_ID :bit16; + MAJOR_REV_ID:bit4; + MINOR_REV_ID:bit4; + ATI_REV_ID :bit4; + end; + + TCC_GC_EDC_CONFIG=bitpacked record + RESERVED0:bit1; + DIS_EDC :bit1; + RESERVED1:bit30; + end; + + TCC_GIO_IOC_FUSES=bitpacked record + RESERVED0:bit1; + IOC_FUSES:bit5; + RESERVED1:bit26; + end; + + TCC_HARVEST_FUSES=bitpacked record + RESERVED0 :bit1; + VCE_DISABLE:bit2; + RESERVED1 :bit1; + UVD_DISABLE:bit1; + RESERVED2 :bit1; + ACP_EXISTS :bit1; + RESERVED3 :bit1; + DC_DISABLE :bit6; + RESERVED4 :bit18; + end; + + TCC_RB_REDUNDANCY=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit7; + FAILED_RB0 :bit4; + EN_REDUNDANCY0:bit1; + RESERVED2 :bit3; + FAILED_RB1 :bit4; + EN_REDUNDANCY1:bit1; + RESERVED3 :bit11; + end; + + TCC_TST_ID_STRAPS=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + DEVICE_ID :bit16; + MAJOR_REV_ID:bit4; + MINOR_REV_ID:bit4; + ATI_REV_ID :bit4; + end; + + TCGTS_RD_CTRL_REG=bitpacked record + ROW_MUX_SEL:bit5; + RESERVED0 :bit3; + REG_MUX_SEL:bit5; + RESERVED1 :bit19; + end; + + TCGTS_SM_CTRL_REG=bitpacked record + ON_SEQ_DELAY :bit4; + OFF_SEQ_DELAY :bit8; + MGCG_ENABLED :bit1; + RESERVED0 :bit3; + BASE_MODE :bit1; + SM_MODE :bit3; + SM_MODE_ENABLE :bit1; + _OVERRIDE :bit1; + LS_OVERRIDE :bit1; + ON_MONITOR_ADD_EN:bit1; + ON_MONITOR_ADD :bit8; + end; + + TCGTS_TCC_DISABLE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit15; + TCC_DISABLE:bit16; + end; + + TCGTT_CP_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit17; + SOFT_OVERRIDE_PERFMON:bit1; + SOFT_OVERRIDE_DYN :bit1; + SOFT_OVERRIDE_REG :bit1; + end; + + TCGTT_IA_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + PERF_ENABLE :bit1; + DBG_ENABLE :bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + CORE_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_PA_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7 :bit1; + SOFT_OVERRIDE6 :bit1; + SOFT_OVERRIDE5 :bit1; + SOFT_OVERRIDE4 :bit1; + SOFT_OVERRIDE3 :bit1; + SU_CLK_OVERRIDE :bit1; + CL_CLK_OVERRIDE :bit1; + REG_CLK_OVERRIDE:bit1; + end; + + TCGTT_PC_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit6; + GRP5_CG_OFF_HYST :bit6; + GRP5_CG_OVERRIDE :bit1; + BACK_CLK_ON_OVERRIDE :bit1; + FRONT_CLK_ON_OVERRIDE:bit1; + CORE3_OVERRIDE :bit1; + CORE2_OVERRIDE :bit1; + CORE1_OVERRIDE :bit1; + CORE0_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_SC_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_SQ_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit17; + PERFMON_OVERRIDE:bit1; + CORE_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_WD_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7 :bit1; + PERF_ENABLE :bit1; + DBG_ENABLE :bit1; + SOFT_OVERRIDE4 :bit1; + TESS_OVERRIDE :bit1; + CORE_OVERRIDE :bit1; + RBIU_INPUT_OVERRIDE:bit1; + REG_OVERRIDE :bit1; + end; + + TCG_CLKPIN_CNTL_2=bitpacked record + ENABLE_XCLK :bit1; + RESERVED0 :bit2; + FORCE_BIF_REFCLK_EN:bit1; + RESERVED1 :bit4; + MUX_TCLK_TO_XCLK :bit1; + RESERVED2 :bit5; + XO_IN_OSCIN_EN :bit1; + XO_IN_ICORE_CLK_OE :bit1; + XO_IN_CML_RXEN :bit1; + XO_IN_BIDIR_CML_OE :bit1; + XO_IN2_OSCIN_EN :bit1; + XO_IN2_ICORE_CLK_OE:bit1; + XO_IN2_CML_RXEN :bit1; + XO_IN2_BIDIR_CML_OE:bit1; + CML_CTRL :bit2; + CLK_SPARE :bit8; + end; + + TCG_ULV_PARAMETER=bitpacked record + ULV_THRESHOLD :bit16; + ULV_THRESHOLD_UNIT:bit4; + RESERVED0 :bit12; + end; + + TCLKREQB_PAD_CNTL=bitpacked record + CLKREQB_PAD_A :bit1; + CLKREQB_PAD_SEL :bit1; + CLKREQB_PAD_MODE :bit1; + CLKREQB_PAD_SPARE :bit2; + CLKREQB_PAD_SN0 :bit1; + CLKREQB_PAD_SN1 :bit1; + CLKREQB_PAD_SN2 :bit1; + CLKREQB_PAD_SN3 :bit1; + CLKREQB_PAD_SLEWN :bit1; + CLKREQB_PAD_WAKE :bit1; + CLKREQB_PAD_SCHMEN :bit1; + CLKREQB_PAD_CNTL_EN :bit1; + CLKREQB_PAD_Y :bit1; + RESERVED0 :bit10; + CLKREQB_PERF_COUNTER_UPPER:bit8; + end; + + TCNV_INPUT_SELECT=bitpacked record + CNV_INPUT_SRC_SELECT :bit2; + CNV_INPUT_PIPE_SELECT:bit3; + RESERVED0 :bit27; + end; + + TCNV_TEST_CRC_RED=bitpacked record + RESERVED0 :bit4; + CNV_TEST_CRC_RED_MASK:bit12; + CNV_TEST_CRC_SIG_RED :bit16; + end; + + TCNV_WINDOW_START=bitpacked record + CNV_WINDOW_START_X:bit12; + RESERVED0 :bit4; + CNV_WINDOW_START_Y:bit12; + RESERVED1 :bit4; + end; + TCOMPUTE_RELAUNCH=bitpacked record PAYLOAD :bit30; IS_EVENT:bit1; IS_STATE:bit1; end; + TCONFIG_APER_SIZE=bit32; + TCP_CE_IB1_OFFSET=bitpacked record IB1_OFFSET:bit20; RESERVED0 :bit12; @@ -5229,6 +21355,11 @@ type DEQ_RETRY:bit8; end; + TCP_ME_PREEMPTION=bitpacked record + OBSOLETE :bit1; + RESERVED0:bit31; + end; + TCP_MQD_BASE_ADDR=bitpacked record RESERVED0:bit2; BASE_ADDR:bit30; @@ -5249,6 +21380,11 @@ type RB_RPTR_ADDR:bit30; end; + TCP_RB_WPTR_DELAY=bitpacked record + PRE_WRITE_TIMER:bit28; + PRE_WRITE_LIMIT:bit4; + end; + TCP_SAMPLE_STATUS=bitpacked record Z_PASS_ACITVE :bit1; STREAMOUT_ACTIVE :bit1; @@ -5334,7 +21470,7 @@ type CE_TO_RAM_WRITE_NOT_RDY :bit1; CE_TO_INC_FIFO_NOT_RDY_TO_RCV :bit1; CE_TO_WR_FIFO_NOT_RDY_TO_RCV :bit1; - CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SI__CI :bit1; + CE_TO_MIU_WRITE_NOT_RDY_TO_RCV :bit1; RESERVED0 :bit1; CE_WAITING_ON_BUFFER_DATA :bit1; CE_WAITING_ON_CE_BUFFER_FLAG :bit1; @@ -5350,6 +21486,54 @@ type RESERVED1 :bit11; end; + TCRTC_BLACK_COLOR=bitpacked record + CRTC_BLACK_COLOR_B_CB:bit10; + CRTC_BLACK_COLOR_G_Y :bit10; + CRTC_BLACK_COLOR_R_CR:bit10; + RESERVED0 :bit2; + end; + + TCRTC_COUNT_RESET=bitpacked record + CRTC_RESET_FRAME_COUNT:bit1; + RESERVED0 :bit31; + end; + + TCRTC_CRC0_DATA_B=bitpacked record + CRC0_B_CB:bit16; + RESERVED0:bit16; + end; + + TCRTC_CRC1_DATA_B=bitpacked record + CRC1_B_CB:bit16; + RESERVED0:bit16; + end; + + TCRTC_GSL_CONTROL=bitpacked record + CRTC_GSL_CHECK_LINE_NUM :bit14; + RESERVED0 :bit2; + CRTC_GSL_FORCE_DELAY :bit5; + RESERVED1 :bit7; + CRTC_GSL_CHECK_ALL_FIELDS:bit1; + RESERVED2 :bit3; + end; + + TCRTC_UPDATE_LOCK=bitpacked record + CRTC_UPDATE_LOCK:bit1; + RESERVED0 :bit31; + end; + + TCRTC_V_TOTAL_MAX=bitpacked record + CRTC_V_TOTAL_MAX :bit14; + RESERVED0 :bit2; + CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING:bit1; + RESERVED1 :bit15; + end; + + TCRTC_V_TOTAL_MIN=bitpacked record + CRTC_V_TOTAL_MIN:bit14; + RESERVED0 :bit18; + end; + TDB_ALPHA_TO_MASK=bitpacked record ALPHA_TO_MASK_ENABLE :bit1; RESERVED0 :bit7; @@ -5407,6 +21591,379 @@ type RESERVED0:bit24; end; + TDCCG_DS_DTO_INCR=bit32; + + TDCCG_GTC_CURRENT=bit32; + + TDCDEBUG_OUT_CNTL=bitpacked record + DCDEBUG_BLOCK_SEL :bit5; + RESERVED0 :bit1; + DCDEBUG_OUT_EN :bit1; + DCDEBUG_OUT_PIN_SEL :bit1; + DCDEBUG_OUT_TEST_DATA_EN:bit1; + DCDEBUG_OUT_TEST_DATA :bit12; + DCDEBUG_OUT_SEL :bit2; + DCDEBUG_OUT_24BIT_SEL :bit1; + DCDEBUG_CLK_SEL :bit5; + RESERVED1 :bit3; + end; + + TDCDEBUG_OUT_DATA=bit32; + + TDCFEV0_PG_CONFIG=bitpacked record + DCFEV0_POWER_FORCEON:bit1; + RESERVED0 :bit31; + end; + + TDCFEV0_PG_ENABLE=bitpacked record + DCFEV0_POWER_GATE:bit1; + RESERVED0 :bit31; + end; + + TDCFEV0_PG_STATUS=bitpacked record + DCFEV0_PGFSM_READ_DATA :bit24; + DCFEV0_DEBUG_PWR_STATUS :bit2; + RESERVED0 :bit2; + DCFEV0_DESIRED_PWR_STATE :bit1; + DCFEV0_REQUESTED_PWR_STATE:bit1; + DCFEV0_PGFSM_PWR_STATUS :bit2; + end; + + TDCFEV_DBG_CONFIG=bitpacked record + DCFEV_DBG_EN :bit1; + RESERVED0 :bit3; + DCFEV_DBG_SEL:bit4; + RESERVED1 :bit24; + end; + + TDCFEV_SOFT_RESET=bitpacked record + UNP_PIXPIPE_SOFT_RESET:bit1; + UNP_REQ_SOFT_RESET :bit1; + SCLV_ALU_SOFT_RESET :bit1; + SCLV_SOFT_RESET :bit1; + CRTC_SOFT_RESET :bit1; + PSCLV_SOFT_RESET :bit1; + COL_MAN_SOFT_RESET :bit1; + RESERVED0 :bit25; + end; + + TDCIO_IMPCAL_CNTL=bitpacked record + CALR_CNTL_OVERRIDE :bit4; + RESERVED0 :bit1; + IMPCAL_SOFT_RESET :bit1; + RESERVED1 :bit2; + IMPCAL_STATUS :bit2; + RESERVED2 :bit2; + IMPCAL_ARB_STATE :bit3; + AUX_IMPCAL_INTERVAL:bit4; + RESERVED3 :bit13; + end; + + TDCIO_WRCMD_DELAY=bitpacked record + UNIPHY_DELAY :bit4; + DAC_DELAY :bit4; + DPHY_DELAY :bit4; + DCRXPHY_DELAY:bit4; + RESERVED0 :bit16; + end; + + TDCI_DEBUG_CONFIG=bitpacked record + DCI_DBG_EN :bit1; + RESERVED0 :bit3; + DCI_DBG_BLOCK_SEL:bit4; + DCI_DBG_CLOCK_SEL:bit4; + RESERVED1 :bit20; + end; + + TDCI_MEM_PWR_CNTL=bitpacked record + DMIF_RDREQ_MEM_PWR_FORCE:bit2; + DMIF_RDREQ_MEM_PWR_DIS :bit1; + MCIF_RDREQ_MEM_PWR_FORCE:bit1; + MCIF_RDREQ_MEM_PWR_DIS :bit1; + MCIF_WRREQ_MEM_PWR_FORCE:bit1; + MCIF_WRREQ_MEM_PWR_DIS :bit1; + VGA_MEM_PWR_FORCE :bit1; + VGA_MEM_PWR_DIS :bit1; + DMCU_ERAM_MEM_PWR_FORCE :bit2; + DMCU_ERAM_MEM_PWR_DIS :bit1; + DMCU_IRAM_MEM_PWR_FORCE :bit1; + DMCU_IRAM_MEM_PWR_DIS :bit1; + FBC_MEM_PWR_FORCE :bit2; + FBC_MEM_PWR_DIS :bit1; + MCIF_MEM_PWR_FORCE :bit2; + MCIF_MEM_PWR_DIS :bit1; + MCIF_DWB_MEM_PWR_FORCE :bit2; + MCIF_DWB_MEM_PWR_DIS :bit1; + MCIF_CWB0_MEM_PWR_FORCE :bit2; + MCIF_CWB0_MEM_PWR_DIS :bit1; + MCIF_CWB1_MEM_PWR_FORCE :bit2; + MCIF_CWB1_MEM_PWR_DIS :bit1; + VIP_MEM_PWR_FORCE :bit1; + VIP_MEM_PWR_DIS :bit1; + RESERVED0 :bit1; + end; + + TDCO_MEM_PWR_CTRL=bitpacked record + I2C_LIGHT_SLEEP_FORCE:bit1; + I2C_LIGHT_SLEEP_DIS :bit1; + TVOUT_LIGHT_SLEEP_DIS:bit1; + MVP_LIGHT_SLEEP_DIS :bit1; + DPA_LIGHT_SLEEP_DIS :bit1; + DPB_LIGHT_SLEEP_DIS :bit1; + DPC_LIGHT_SLEEP_DIS :bit1; + DPD_LIGHT_SLEEP_DIS :bit1; + DPE_LIGHT_SLEEP_DIS :bit1; + DPF_LIGHT_SLEEP_DIS :bit1; + DPG_LIGHT_SLEEP_DIS :bit1; + HDMI0_MEM_PWR_FORCE :bit2; + HDMI0_MEM_PWR_DIS :bit1; + HDMI1_MEM_PWR_FORCE :bit2; + HDMI1_MEM_PWR_DIS :bit1; + HDMI2_MEM_PWR_FORCE :bit2; + HDMI2_MEM_PWR_DIS :bit1; + HDMI3_MEM_PWR_FORCE :bit2; + HDMI3_MEM_PWR_DIS :bit1; + HDMI4_MEM_PWR_FORCE :bit2; + HDMI4_MEM_PWR_DIS :bit1; + HDMI5_MEM_PWR_FORCE :bit2; + HDMI5_MEM_PWR_DIS :bit1; + HDMI6_MEM_PWR_FORCE :bit2; + HDMI6_MEM_PWR_DIS :bit1; + end; + + TDCP_RANDOM_SEEDS=bitpacked record + DCP_RAND_R_SEED:bit8; + DCP_RAND_G_SEED:bit8; + DCP_RAND_B_SEED:bit8; + RESERVED0 :bit8; + end; + + TDC_GPIO_DDCVGA_A=bitpacked record + DC_GPIO_DDCVGACLK_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DDCVGADATA_A:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DDCVGA_Y=bitpacked record + DC_GPIO_DDCVGACLK_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DDCVGADATA_Y:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_GENLK_EN=bitpacked record + DC_GPIO_GENLK_CLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_GENLK_VSYNC_EN:bit1; + RESERVED1 :bit7; + DC_GPIO_SWAPLOCK_A_EN :bit1; + RESERVED2 :bit7; + DC_GPIO_SWAPLOCK_B_EN :bit1; + RESERVED3 :bit7; + end; + + TDC_GPIO_HPD_MASK=bitpacked record + DC_GPIO_HPD1_MASK :bit1; + DC_GPIO_RX_HPD_MASK :bit1; + DC_GPIO_RX_HPD_PD_DIS:bit1; + DC_GPIO_RX_HPD_RX_SEL:bit1; + DC_GPIO_HPD1_PD_DIS :bit1; + RESERVED0 :bit1; + DC_GPIO_HPD1_RECV :bit1; + RESERVED1 :bit1; + DC_GPIO_HPD2_MASK :bit1; + DC_GPIO_HPD2_PD_DIS :bit1; + DC_GPIO_HPD2_RECV :bit1; + RESERVED2 :bit5; + DC_GPIO_HPD3_MASK :bit1; + DC_GPIO_HPD3_PD_DIS :bit1; + DC_GPIO_HPD3_RECV :bit1; + RESERVED3 :bit1; + DC_GPIO_HPD4_MASK :bit1; + DC_GPIO_HPD4_PD_DIS :bit1; + DC_GPIO_HPD4_RECV :bit1; + RESERVED4 :bit1; + DC_GPIO_HPD5_MASK :bit1; + DC_GPIO_HPD5_PD_DIS :bit1; + DC_GPIO_HPD5_RECV :bit1; + RESERVED5 :bit1; + DC_GPIO_HPD6_MASK :bit1; + DC_GPIO_HPD6_PD_DIS :bit1; + DC_GPIO_HPD6_RECV :bit1; + RESERVED6 :bit1; + end; + + TDC_GPIO_I2CPAD_A=bitpacked record + DC_GPIO_SCL_A:bit1; + DC_GPIO_SDA_A:bit1; + RESERVED0 :bit30; + end; + + TDC_GPIO_I2CPAD_Y=bitpacked record + DC_GPIO_SCL_Y:bit1; + DC_GPIO_SDA_Y:bit1; + RESERVED0 :bit30; + end; + + TDC_GPIO_PWRSEQ_A=bitpacked record + DC_GPIO_BLON_A :bit1; + RESERVED0 :bit7; + DC_GPIO_DIGON_A :bit1; + RESERVED1 :bit7; + DC_GPIO_ENA_BL_A :bit1; + RESERVED2 :bit7; + DC_GPIO_VSYNC_IN_A:bit1; + RESERVED3 :bit6; + DC_GPIO_HSYNC_IN_A:bit1; + end; + + TDC_GPIO_PWRSEQ_Y=bitpacked record + DC_GPIO_BLON_Y :bit1; + RESERVED0 :bit7; + DC_GPIO_DIGON_Y :bit1; + RESERVED1 :bit7; + DC_GPIO_ENA_BL_Y:bit1; + RESERVED2 :bit7; + DC_GPIO_VSYNC_IN:bit1; + RESERVED3 :bit6; + DC_GPIO_HSYNC_IN:bit1; + end; + + TDC_GPIO_SYNCA_EN=bitpacked record + DC_GPIO_HSYNCA_EN:bit1; + RESERVED0 :bit7; + DC_GPIO_VSYNCA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_I2C_SW_STATUS=bitpacked record + DC_I2C_SW_STATUS :bit2; + DC_I2C_SW_DONE :bit1; + RESERVED0 :bit1; + DC_I2C_SW_ABORTED :bit1; + DC_I2C_SW_TIMEOUT :bit1; + DC_I2C_SW_INTERRUPTED :bit1; + DC_I2C_SW_BUFFER_OVERFLOW:bit1; + DC_I2C_SW_STOPPED_ON_NACK:bit1; + RESERVED1 :bit3; + DC_I2C_SW_NACK0 :bit1; + DC_I2C_SW_NACK1 :bit1; + DC_I2C_SW_NACK2 :bit1; + DC_I2C_SW_NACK3 :bit1; + RESERVED2 :bit2; + DC_I2C_SW_REQ :bit1; + RESERVED3 :bit13; + end; + + TDC_LUT_SEQ_COLOR=bitpacked record + DC_LUT_SEQ_COLOR:bit16; + RESERVED0 :bit16; + end; + + TDIDT_DB_CTRL_OCP=bitpacked record + UNUSED_0 :bit16; + OCP_MAX_POWER:bit16; + end; + + TDIDT_SQ_CTRL_OCP=bitpacked record + UNUSED_0 :bit16; + OCP_MAX_POWER:bit16; + end; + + TDIDT_TD_CTRL_OCP=bitpacked record + UNUSED_0 :bit16; + OCP_MAX_POWER:bit16; + end; + + TDIG_TEST_PATTERN=bitpacked record + DIG_TEST_PATTERN_OUT_EN :bit1; + DIG_HALF_CLOCK_PATTERN_SEL :bit1; + LVDS_TEST_CLOCK_DATA :bit1; + RESERVED0 :bit1; + DIG_RANDOM_PATTERN_OUT_EN :bit1; + DIG_RANDOM_PATTERN_RESET :bit1; + DIG_TEST_PATTERN_EXTERNAL_RESET_EN:bit1; + RESERVED1 :bit1; + LVDS_EYE_PATTERN :bit1; + RESERVED2 :bit7; + DIG_STATIC_TEST_PATTERN :bit10; + RESERVED3 :bit6; + end; + + TDMCU_FW_END_ADDR=bitpacked record + FW_END_ADDR_LSB:bit8; + FW_END_ADDR_MSB:bit8; + RESERVED0 :bit16; + end; + + TDMIF_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit9; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED5 :bit1; + end; + + TDP_DPHY_CRC_CNTL=bitpacked record + DPHY_CRC_FIELD:bit1; + RESERVED0 :bit3; + DPHY_CRC_SEL :bit2; + RESERVED1 :bit10; + DPHY_CRC_MASK :bit8; + RESERVED2 :bit8; + end; + + TDP_MSE_MISC_CNTL=bitpacked record + DP_MSE_BLANK_CODE :bit1; + RESERVED0 :bit3; + DP_MSE_TIMESTAMP_MODE :bit1; + RESERVED1 :bit3; + DP_MSE_ZERO_ENCODER :bit1; + RESERVED2 :bit7; + DP_MSE_OUTPUT_DPDBG_DATA:bit1; + RESERVED3 :bit15; + end; + + TDP_MSE_RATE_CNTL=bitpacked record + DP_MSE_RATE_Y:bit26; + DP_MSE_RATE_X:bit6; + end; + + TDP_SEC_TIMESTAMP=bitpacked record + DP_SEC_TIMESTAMP_MODE:bit2; + RESERVED0 :bit30; + end; + + TDVO_VREF_CONTROL=bitpacked record + DVO_VREFPON:bit1; + DVO_VREFSEL:bit1; + RESERVED0 :bit2; + DVO_VREFCAL:bit4; + RESERVED1 :bit24; + end; + + TEXTERN_TRIG_CNTL=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit30; + end; + + TGARLIC_FLUSH_REQ=bitpacked record + FLUSH_REQ:bit1; + RESERVED0:bit31; + end; + + TGCK_SMC_IND_DATA=bit32; + TGDS_ATOM_OFFSET0=bitpacked record OFFSET0:bit8; UNUSED :bit24; @@ -5442,6 +21999,63 @@ type TGDS_OA_RING_SIZE=bit32; + TGENERIC_I2C_DATA=bitpacked record + GENERIC_I2C_DATA_RW :bit1; + RESERVED0 :bit7; + GENERIC_I2C_DATA :bit8; + GENERIC_I2C_INDEX :bit4; + RESERVED1 :bit11; + GENERIC_I2C_INDEX_WRITE:bit1; + end; + + TGFX_PIPE_CONTROL=bitpacked record + HYSTERESIS_CNT :bit13; + RESERVED0 :bit3; + CONTEXT_SUSPEND_EN:bit1; + RESERVED1 :bit15; + end; + + TGMCON_LPT_TARGET=bit32; + + TGMCON_PGFSM_READ=bitpacked record + READ_VALUE :bit24; + PGFSM_SELECT :bit4; + SERDES_MASTER_BUSY:bit1; + RESERVED0 :bit3; + end; + + TGPIOPAD_INT_STAT=bitpacked record + GPIO_INT_STAT :bit29; + RESERVED0 :bit2; + SW_INITIATED_INT_STAT:bit1; + end; + + TGPIOPAD_INT_TYPE=bitpacked record + GPIO_INT_TYPE :bit29; + RESERVED0 :bit2; + SW_INITIATED_INT_TYPE:bit1; + end; + + TGPIOPAD_RCVR_SEL=bitpacked record + GPIO_RCVR_SEL:bit31; + RESERVED0 :bit1; + end; + + TGPIOPAD_STRENGTH=bitpacked record + GPIO_STRENGTH_SN:bit4; + GPIO_STRENGTH_SP:bit4; + RESERVED0 :bit24; + end; + + TGPU_BIST_CONTROL=bitpacked record + STOP_ON_FAIL_HW :bit1; + STOP_ON_FAIL_CU_HARV:bit1; + CU_HARV_LOOP_COUNT :bit4; + RESERVED0 :bit1; + RESERVED :bit17; + GLOBAL_LOOP_COUNT :bit8; + end; + TGRBM_READ_ERROR2=bitpacked record RESERVED0 :bit17; READ_REQUESTER_SRBM :bit1; @@ -5478,6 +22092,1124 @@ type WRITE_ERROR :bit1; end; + TGRPH_DFQ_CONTROL=bitpacked record + GRPH_DFQ_RESET :bit1; + RESERVED0 :bit3; + GRPH_DFQ_SIZE :bit3; + RESERVED1 :bit1; + GRPH_DFQ_MIN_FREE_ENTRIES:bit3; + RESERVED2 :bit21; + end; + + THDP_MEMIO_STATUS=bitpacked record + MEMIO_WR_STATUS:bit1; + MEMIO_RD_STATUS:bit1; + MEMIO_WR_ERROR :bit1; + MEMIO_RD_ERROR :bit1; + RESERVED0 :bit28; + end; + + THDP_MEM_POWER_LS=bitpacked record + LS_ENABLE:bit1; + LS_SETUP :bit6; + LS_HOLD :bit6; + RESERVED0:bit19; + end; + + THDP_SW_SEMAPHORE=bit32; + + THDP_XDP_BUSY_STS=bitpacked record + BUSY_BITS:bit18; + RESERVED0:bit14; + end; + + THDP_XDP_DBG_ADDR=bitpacked record + STS :bit16; + CTRL:bit16; + end; + + THDP_XDP_DBG_DATA=bitpacked record + STS :bit16; + CTRL:bit16; + end; + + THDP_XDP_DBG_MASK=bitpacked record + STS :bit16; + CTRL:bit16; + end; + + THDP_XDP_P2P_BAR0=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR1=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR2=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR3=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR4=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR5=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR6=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_P2P_BAR7=bitpacked record + ADDR :bit16; + FLUSH :bit4; + VALID :bit1; + RESERVED0:bit11; + end; + + THDP_XDP_SRBM_CFG=bitpacked record + SRBM_CFG_REG_CLK_ENABLE_COUNT:bit6; + SRBM_CFG_REG_CLK_GATING_DIS :bit1; + SRBM_CFG_WAKE_DYN_CLK :bit1; + RESERVED0 :bit24; + end; + + TIH_ACTIVE_FCN_ID=bitpacked record + VF_ID :bit4; + RESERVED:bit27; + PF_VF :bit1; + end; + + TIH_DOORBELL_RPTR=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TINTERRUPT_STATUS=bitpacked record + STREAM_0_INTERRUPT_STATUS :bit1; + STREAM_1_INTERRUPT_STATUS :bit1; + STREAM_2_INTERRUPT_STATUS :bit1; + STREAM_3_INTERRUPT_STATUS :bit1; + STREAM_4_INTERRUPT_STATUS :bit1; + STREAM_5_INTERRUPT_STATUS :bit1; + STREAM_6_INTERRUPT_STATUS :bit1; + STREAM_7_INTERRUPT_STATUS :bit1; + STREAM_8_INTERRUPT_STATUS :bit1; + STREAM_9_INTERRUPT_STATUS :bit1; + STREAM_10_INTERRUPT_STATUS :bit1; + STREAM_11_INTERRUPT_STATUS :bit1; + STREAM_12_INTERRUPT_STATUS :bit1; + STREAM_13_INTERRUPT_STATUS :bit1; + STREAM_14_INTERRUPT_STATUS :bit1; + STREAM_15_INTERRUPT_STATUS :bit1; + RESERVED0 :bit14; + CONTROLLER_INTERRUPT_STATUS:bit1; + GLOBAL_INTERRUPT_STATUS :bit1; + end; + + TLBV_VLINE_STATUS=bitpacked record + VLINE_OCCURRED :bit1; + RESERVED0 :bit3; + VLINE_ACK :bit1; + RESERVED1 :bit7; + VLINE_STAT :bit1; + RESERVED2 :bit3; + VLINE_INTERRUPT :bit1; + VLINE_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLB_BUFFER_STATUS=bitpacked record + LB_BUFFER_EMPTY_MARGIN :bit4; + LB_BUFFER_EMPTY_STAT :bit1; + RESERVED0 :bit3; + LB_BUFFER_EMPTY_OCCURRED:bit1; + RESERVED1 :bit3; + LB_BUFFER_EMPTY_ACK :bit1; + RESERVED2 :bit3; + LB_BUFFER_FULL_STAT :bit1; + RESERVED3 :bit3; + LB_BUFFER_FULL_OCCURRED :bit1; + RESERVED4 :bit3; + LB_BUFFER_FULL_ACK :bit1; + RESERVED5 :bit7; + end; + + TLB_VBLANK_STATUS=bitpacked record + VBLANK_OCCURRED :bit1; + RESERVED0 :bit3; + VBLANK_ACK :bit1; + RESERVED1 :bit7; + VBLANK_STAT :bit1; + RESERVED2 :bit3; + VBLANK_INTERRUPT :bit1; + VBLANK_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLB_VLINE2_STATUS=bitpacked record + VLINE2_OCCURRED :bit1; + RESERVED0 :bit3; + VLINE2_ACK :bit1; + RESERVED1 :bit7; + VLINE2_STAT :bit1; + RESERVED2 :bit3; + VLINE2_INTERRUPT :bit1; + VLINE2_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLCAC_CPL_OVR_SEL=bit32; + + TLCAC_CPL_OVR_VAL=bit32; + + TLCAC_MC0_OVR_SEL=bit32; + + TLCAC_MC0_OVR_VAL=bit32; + + TLCAC_MC1_OVR_SEL=bit32; + + TLCAC_MC1_OVR_VAL=bit32; + + TLCAC_MC2_OVR_SEL=bit32; + + TLCAC_MC2_OVR_VAL=bit32; + + TLCAC_MC3_OVR_SEL=bit32; + + TLCAC_MC3_OVR_VAL=bit32; + + TLCAC_MC4_OVR_SEL=bit32; + + TLCAC_MC4_OVR_VAL=bit32; + + TLCAC_MC5_OVR_SEL=bit32; + + TLCAC_MC5_OVR_VAL=bit32; + + TLCAC_MC6_OVR_SEL=bit32; + + TLCAC_MC6_OVR_VAL=bit32; + + TLCAC_MC7_OVR_SEL=bit32; + + TLCAC_MC7_OVR_VAL=bit32; + + TLM_POWERCONTROL1=bitpacked record + LMTxEn0 :bit1; + LMTxClkEn0 :bit1; + LMTxMargin0 :bit3; + LMSkipBit0 :bit1; + LMLaneUnused0:bit1; + LMTxMarginEn0:bit1; + LMDeemph0 :bit1; + LMTxEn1 :bit1; + LMTxClkEn1 :bit1; + LMTxMargin1 :bit3; + LMSkipBit1 :bit1; + LMLaneUnused1:bit1; + LMTxMarginEn1:bit1; + LMDeemph1 :bit1; + LMTxEn2 :bit1; + LMTxClkEn2 :bit1; + LMTxMargin2 :bit3; + LMSkipBit2 :bit1; + LMLaneUnused2:bit1; + LMTxMarginEn2:bit1; + LMDeemph2 :bit1; + TxCoeffID0 :bit2; + TxCoeffID1 :bit2; + RESERVED0 :bit1; + end; + + TLM_POWERCONTROL2=bitpacked record + LMTxEn3 :bit1; + LMTxClkEn3 :bit1; + LMTxMargin3 :bit3; + LMSkipBit3 :bit1; + LMLaneUnused3:bit1; + LMTxMarginEn3:bit1; + LMDeemph3 :bit1; + TxCoeffID2 :bit2; + TxCoeffID3 :bit2; + TxCoeff0 :bit6; + TxCoeff1 :bit6; + TxCoeff2 :bit6; + RESERVED0 :bit1; + end; + + TLM_POWERCONTROL3=bitpacked record + TxCoeff3 :bit6; + RxEqCtl0 :bit6; + RxEqCtl1 :bit6; + RxEqCtl2 :bit6; + RxEqCtl3 :bit6; + RESERVED0:bit2; + end; + + TLM_POWERCONTROL4=bitpacked record + LinkNum0:bit3; + LinkNum1:bit3; + LinkNum2:bit3; + LinkNum3:bit3; + LaneNum0:bit4; + LaneNum1:bit4; + LaneNum2:bit4; + LaneNum3:bit4; + SpcMode0:bit1; + SpcMode1:bit1; + SpcMode2:bit1; + SpcMode3:bit1; + end; + + TMAILBOX_INT_CNTL=bitpacked record + VALID_INT_EN:bit1; + ACK_INT_EN :bit1; + RESERVED0 :bit30; + end; + + TMCIF_MEM_CONTROL=bitpacked record + MCIFMEM_CACHE_MODE_DIS:bit1; + RESERVED0 :bit3; + MCIFMEM_CACHE_MODE :bit2; + RESERVED1 :bit2; + MCIFMEM_CACHE_SIZE :bit8; + MCIFMEM_CACHE_PIPE :bit3; + MCIFMEM_CACHE_TYPE :bit2; + RESERVED2 :bit11; + end; + + TMC_ARB_ADDR_HASH=bitpacked record + BANK_XOR_ENABLE:bit4; + COL_XOR :bit8; + ROW_XOR :bit16; + RESERVED0 :bit4; + end; + + TMC_ARB_GECC2_CLI=bitpacked record + NO_GECC_CLI0:bit8; + NO_GECC_CLI1:bit8; + NO_GECC_CLI2:bit8; + NO_GECC_CLI3:bit8; + end; + + TMC_ARB_RFSH_CNTL=bitpacked record + ENABLE :bit1; + URG0 :bit5; + URG1 :bit5; + ACCUM :bit1; + SINGLE_BANK :bit1; + PUSH_SINGLE_BANK_REFRESH:bit1; + PENDING_RATE_SEL :bit3; + REFSB_PER_PAGE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit13; + end; + + TMC_ARB_RFSH_RATE=bitpacked record + POWERMODE0:bit8; + RESERVED0 :bit8; + RESERVED1 :bit8; + RESERVED2 :bit8; + end; + + TMC_ARB_RTT_CNTL0=bitpacked record + ENABLE :bit1; + START_IDLE :bit1; + START_R2W :bit2; + FLUSH_ON_ENTER :bit1; + HARSH_START :bit1; + TPS_HARSH_PRIORITY :bit1; + TWRT_HARSH_PRIORITY:bit1; + BREAK_ON_HARSH :bit1; + BREAK_ON_URGENTRD :bit1; + BREAK_ON_URGENTWR :bit1; + TRAIN_PERIOD :bit3; + START_R2W_RFSH :bit1; + DEBUG_RSV_0 :bit1; + DEBUG_RSV_1 :bit1; + DEBUG_RSV_2 :bit1; + DEBUG_RSV_3 :bit1; + DEBUG_RSV_4 :bit1; + DEBUG_RSV_5 :bit1; + DEBUG_RSV_6 :bit1; + DEBUG_RSV_7 :bit1; + DEBUG_RSV_8 :bit1; + DATA_CNTL :bit1; + NEIGHBOR_BIT :bit1; + RESERVED0 :bit6; + end; + + TMC_ARB_RTT_CNTL1=bitpacked record + WINDOW_SIZE :bit5; + WINDOW_UPDATE :bit1; + WINDOW_INC_THRESHOLD:bit7; + WINDOW_DEC_THRESHOLD:bit7; + WINDOW_SIZE_MAX :bit5; + WINDOW_SIZE_MIN :bit5; + WINDOW_UPDATE_COUNT :bit2; + end; + + TMC_ARB_RTT_CNTL2=bitpacked record + SAMPLE_CNT :bit6; + PHASE_ADJUST_THRESHOLD:bit6; + PHASE_ADJUST_SIZE :bit1; + FILTER_CNTL :bit1; + RESERVED0 :bit18; + end; + + TMC_ARB_RTT_DEBUG=bitpacked record + DEBUG_BYTE_CH0 :bit2; + DEBUG_BYTE_CH1 :bit2; + SHIFTED_PHASE_CH0:bit8; + WINDOW_SIZE_CH0 :bit5; + SHIFTED_PHASE_CH1:bit8; + WINDOW_SIZE_CH1 :bit5; + RESERVED0 :bit2; + end; + + TMC_CG_CONFIG_MCD=bitpacked record + MCD0_WR_ENABLE :bit1; + MCD1_WR_ENABLE :bit1; + MCD2_WR_ENABLE :bit1; + MCD3_WR_ENABLE :bit1; + MCD4_WR_ENABLE :bit1; + MCD5_WR_ENABLE :bit1; + MCD6_WR_ENABLE :bit1; + MCD7_WR_ENABLE :bit1; + MC_RD_ENABLE :bit3; + MC_RD_ENABLE_SUB:bit1; + RESERVED0 :bit1; + INDEX :bit16; + RESERVED1 :bit3; + end; + + TMC_CITF_DAGB_DLY=bitpacked record + DLY :bit6; + RESERVED0:bit10; + CLI :bit6; + RESERVED1:bit2; + POS :bit6; + RESERVED2:bit2; + end; + + TMC_CITF_RET_MODE=bitpacked record + INORDER_RD :bit1; + INORDER_WR :bit1; + REMPRI_RD :bit1; + REMPRI_WR :bit1; + LCLPRI_RD :bit1; + LCLPRI_WR :bit1; + RDRET_STALL_EN :bit1; + RDRET_STALL_THRESHOLD:bit8; + RESERVED0 :bit17; + end; + + TMC_FUS_DRAM_MODE=bitpacked record + DCTSELINTLVADDR:bit3; + DRAMTYPE :bit3; + DRAMHOLEOFFSET :bit9; + RESERVED0 :bit17; + end; + + TMC_GRUB_FEATURES=bitpacked record + WR_COMBINE_OFF :bit1; + SCLK_CG_DISABLE :bit1; + PRB_FILTER_DISABLE :bit1; + ARB_NRT_STACK_DISABLE :bit1; + ARB_FIXED_PRIORITY :bit1; + PRIORITY_UPDATE_DISABLE:bit1; + RT_BYPASS_OFF :bit1; + SYNC_ON_ERROR_DISABLE :bit1; + SYNC_REFLECT_DISABLE :bit1; + RESERVED0 :bit1; + ARB_STALL_EN :bit1; + CREDIT_STALL_EN :bit1; + ARB_STALL_SET_SEL :bit2; + ARB_STALL_CLR_SEL :bit2; + CREDIT_STALL_SET_SEL :bit2; + CREDIT_STALL_CLR_SEL :bit2; + WR_REORDER_OFF :bit1; + RESERVED1 :bit11; + end; + + TMC_HUB_RDREQ_HDP=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_RLC=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_SEM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_SIP=bitpacked record + ASK_CREDITS :bit7; + MED_CREDIT_SEL :bit1; + DISPLAY_CREDITS:bit7; + RESERVED0 :bit17; + end; + + TMC_HUB_RDREQ_SMU=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_TLS=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_UMC=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_RDREQ_UVD=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_RDREQ_VMC=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_VP8=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_WDP_SDMA0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_SDMA1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_VCEU0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_VCEU1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_XDMAM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_IO_DEBUG_UP_0=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_1=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_2=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_3=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_4=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_5=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_6=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_7=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_8=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_9=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_RPB_TCI_CNTL2=bitpacked record + TCI_POLICY :bit1; + TCI_MTYPE :bit2; + TCI_SNOOP :bit1; + TCI_PHYSICAL :bit1; + TCI_PERF_CNTR_EN:bit1; + TCI_EXE :bit1; + RESERVED0 :bit25; + end; + + TMC_SEQ_RD_CTL_D0=bitpacked record + RCV_DLY :bit3; + RCV_EXT :bit5; + RST_SEL :bit2; + RST_HLD :bit4; + RESERVED0:bit1; + RESERVED1:bit1; + RBS_DLY :bit5; + RESERVED2:bit2; + RESERVED3:bit1; + RESERVED4:bit8; + end; + + TMC_SEQ_RD_CTL_D1=bitpacked record + RCV_DLY :bit3; + RCV_EXT :bit5; + RST_SEL :bit2; + RST_HLD :bit4; + RESERVED0:bit1; + RESERVED1:bit1; + RBS_DLY :bit5; + RESERVED2:bit2; + RESERVED3:bit1; + RESERVED4:bit8; + end; + + TMC_SEQ_RESERVE_M=bit32; + + TMC_SEQ_SREG_READ=bit32; + + TMC_SEQ_SUP_R_PGM=bit32; + + TMC_SEQ_WR_CTL_D0=bitpacked record + DAT_DLY :bit5; + DQS_DLY :bit5; + DQS_XTR :bit1; + OEN_DLY :bit5; + OEN_EXT :bit4; + OEN_SEL :bit2; + CMD_DLY :bit1; + ADR_DLY :bit1; + RESERVED0:bit8; + end; + + TMC_SEQ_WR_CTL_D1=bitpacked record + DAT_DLY :bit5; + DQS_DLY :bit5; + DQS_XTR :bit1; + OEN_DLY :bit5; + OEN_EXT :bit4; + OEN_SEL :bit2; + CMD_DLY :bit1; + ADR_DLY :bit1; + RESERVED0:bit8; + end; + + TMC_VM_NB_PCI_ARB=bitpacked record + RESERVED0:bit3; + VGA_HOLE :bit1; + RESERVED1:bit28; + end; + + TMC_XBAR_ADDR_DEC=bitpacked record + NO_DIV_BY_3 :bit1; + GECC :bit1; + RB_SPLIT :bit1; + RB_SPLIT_COLHI:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit26; + end; + + TMC_XPB_CLG_CFG10=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG11=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG12=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG13=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG14=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG15=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG16=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG17=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG18=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG19=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG20=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG21=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG22=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG23=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG24=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG25=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG26=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG27=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG28=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG29=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG30=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG31=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG32=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG33=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG34=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG35=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_CFG36=bitpacked record + WCB_NUM :bit4; + LB_TYPE :bit3; + P2P_BAR :bit3; + HOST_FLUSH:bit4; + SIDE_FLUSH:bit4; + RESERVED0 :bit14; + end; + + TMC_XPB_CLG_EXTRA=bitpacked record + CMP0 :bit8; + MSK0 :bit8; + VLD0 :bit1; + CMP1 :bit8; + VLD1 :bit1; + RESERVED0:bit6; + end; + + TMC_XPB_INTF_CFG2=bitpacked record + RPB_RDREQ_CRD:bit8; + RESERVED0 :bit24; + end; + + TMPLL_FUNC_CNTL_2=bitpacked record + VCTRLADC_EN :bit1; + TEST_VCTL_EN :bit1; + RESET_EN :bit1; + TEST_BYPCLK_EN :bit1; + TEST_BYPCLK_SRC :bit1; + TEST_FBDIV_FRAC_BYPASS:bit1; + TEST_BYPMCLK :bit1; + MPLL_UNLOCK_CLEAR :bit1; + TEST_VCTL_CNTRL :bit1; + TEST_FBDIV_SSC_BYPASS :bit1; + RESET_TIMER :bit2; + PFD_RESET_CNTRL :bit2; + RESERVED0 :bit3; + BACKUP_2 :bit3; + LF_CNTRL :bit7; + BACKUP :bit5; + end; + + TMVP_FIFO_CONTROL=bitpacked record + MVP_STOP_SLAVE_WM :bit8; + MVP_PAUSE_SLAVE_WM :bit8; + MVP_PAUSE_SLAVE_CNT:bit8; + RESERVED0 :bit8; + end; + + TMVP_SLAVE_STATUS=bitpacked record + MVP_SLAVE_PIXELS_PER_LINE_RCVED:bit13; + RESERVED0 :bit3; + MVP_SLAVE_LINES_PER_FRAME_RCVED:bit13; + RESERVED1 :bit3; + end; + + TPAGE_MIRROR_CNTL=bitpacked record + PAGE_MIRROR_BASE_ADDR :bit24; + PAGE_MIRROR_INVALIDATE:bit1; + PAGE_MIRROR_ENABLE :bit1; + PAGE_MIRROR_USAGE :bit2; + RESERVED0 :bit4; + end; + TPA_CL_POINT_SIZE=bit32; TPA_SC_DEBUG_CNTL=bitpacked record @@ -5511,6 +23243,766 @@ type WIDTH :bit16; end; + TPB0_PIF_GLB_OVRD=bitpacked record + RXDETECT_OVERRIDE_VAL_0:bit1; + RXDETECT_OVERRIDE_VAL_1:bit1; + RXDETECT_OVERRIDE_VAL_2:bit1; + RXDETECT_OVERRIDE_VAL_3:bit1; + RXDETECT_OVERRIDE_VAL_4:bit1; + RXDETECT_OVERRIDE_VAL_5:bit1; + RXDETECT_OVERRIDE_VAL_6:bit1; + RXDETECT_OVERRIDE_VAL_7:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RXDETECT_OVERRIDE_EN :bit1; + RESERVED8 :bit15; + end; + + TPB0_PIF_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + RESERVED0 :bit16; + end; + + TPB0_PIF_RX_CTRL2=bitpacked record + RX_RDY_DASRT_COUNT :bit3; + RX_STATUS_DASRT_COUNT :bit3; + RXPHYSTATUS_DELAY :bit3; + RESERVED0 :bit7; + FORCE_CDREN_IN_L0S :bit1; + EI_DET_CYCLE_MODE :bit2; + EI_DET_ON_TIME :bit2; + EI_DET_OFF_TIME :bit3; + EI_DET_CYCLE_DIS_IN_PS1:bit1; + RX_CDR_XTND_MODE :bit2; + RX_L0S_TO_L0_DETECT_EI :bit1; + RESERVED1 :bit4; + end; + + TPB0_PIF_TX_CTRL2=bitpacked record + TX_RDY_DASRT_COUNT :bit3; + TX_STATUS_DASRT_COUNT :bit3; + TXPHYSTATUS_DELAY :bit3; + RESERVED0 :bit7; + TX_HIGH_IMP_STAG_MP :bit1; + TX_HIGH_IMP_STAG_MODE :bit2; + RESERVED1 :bit2; + TX_FORCE_DATA_VALID :bit1; + TX_L0_TO_HIZ_DLY :bit3; + TX_FIFO_INIT_UPCONFIG :bit1; + TX_HIZ_TO_L0_DLY :bit3; + TX_LINKSPEED_ACK_IN_S2:bit1; + RESERVED2 :bit2; + end; + + TPB1_PIF_GLB_OVRD=bitpacked record + RXDETECT_OVERRIDE_VAL_0:bit1; + RXDETECT_OVERRIDE_VAL_1:bit1; + RXDETECT_OVERRIDE_VAL_2:bit1; + RXDETECT_OVERRIDE_VAL_3:bit1; + RXDETECT_OVERRIDE_VAL_4:bit1; + RXDETECT_OVERRIDE_VAL_5:bit1; + RXDETECT_OVERRIDE_VAL_6:bit1; + RXDETECT_OVERRIDE_VAL_7:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RXDETECT_OVERRIDE_EN :bit1; + RESERVED8 :bit15; + end; + + TPB1_PIF_HW_DEBUG=bitpacked record + HW_00_DEBUG:bit1; + HW_01_DEBUG:bit1; + HW_02_DEBUG:bit1; + HW_03_DEBUG:bit1; + HW_04_DEBUG:bit1; + HW_05_DEBUG:bit1; + HW_06_DEBUG:bit1; + HW_07_DEBUG:bit1; + HW_08_DEBUG:bit1; + HW_09_DEBUG:bit1; + HW_10_DEBUG:bit1; + HW_11_DEBUG:bit1; + HW_12_DEBUG:bit1; + HW_13_DEBUG:bit1; + HW_14_DEBUG:bit1; + HW_15_DEBUG:bit1; + RESERVED0 :bit16; + end; + + TPB1_PIF_RX_CTRL2=bitpacked record + RX_RDY_DASRT_COUNT :bit3; + RX_STATUS_DASRT_COUNT :bit3; + RXPHYSTATUS_DELAY :bit3; + RESERVED0 :bit7; + FORCE_CDREN_IN_L0S :bit1; + EI_DET_CYCLE_MODE :bit2; + EI_DET_ON_TIME :bit2; + EI_DET_OFF_TIME :bit3; + EI_DET_CYCLE_DIS_IN_PS1:bit1; + RX_CDR_XTND_MODE :bit2; + RX_L0S_TO_L0_DETECT_EI :bit1; + RESERVED1 :bit4; + end; + + TPB1_PIF_TX_CTRL2=bitpacked record + TX_RDY_DASRT_COUNT :bit3; + TX_STATUS_DASRT_COUNT :bit3; + TXPHYSTATUS_DELAY :bit3; + RESERVED0 :bit7; + TX_HIGH_IMP_STAG_MP :bit1; + TX_HIGH_IMP_STAG_MODE :bit2; + RESERVED1 :bit2; + TX_FORCE_DATA_VALID :bit1; + TX_L0_TO_HIZ_DLY :bit3; + TX_FIFO_INIT_UPCONFIG :bit1; + TX_HIZ_TO_L0_DLY :bit3; + TX_LINKSPEED_ACK_IN_S2:bit1; + RESERVED2 :bit2; + end; + + TPCIEP_STRAP_MISC=bitpacked record + STRAP_REVERSE_LANES :bit1; + STRAP_E2E_PREFIX_EN :bit1; + STRAP_EXTENDED_FMT_SUPPORTED:bit1; + STRAP_OBFF_SUPPORTED :bit2; + STRAP_LTR_SUPPORTED :bit1; + RESERVED0 :bit26; + end; + + TPCIE_CONFIG_CNTL=bitpacked record + DYN_CLK_LATENCY :bit4; + RESERVED0 :bit12; + CI_MAX_PAYLOAD_SIZE_MODE :bit1; + CI_PRIV_MAX_PAYLOAD_SIZE :bit3; + CI_MAX_READ_REQUEST_SIZE_MODE:bit1; + CI_PRIV_MAX_READ_REQUEST_SIZE:bit3; + CI_MAX_READ_SAFE_MODE :bit1; + CI_EXTENDED_TAG_EN_OVERRIDE :bit2; + RESERVED1 :bit5; + end; + + TPCIE_F0_DPA_CNTL=bitpacked record + SUBSTATE_STATUS :bit5; + RESERVED0 :bit3; + DPA_COMPLIANCE_MODE:bit1; + RESERVED1 :bit23; + end; + + TPCIE_LC_CDR_CNTL=bitpacked record + LC_CDR_TEST_OFF :bit12; + LC_CDR_TEST_SETS:bit12; + LC_CDR_SET_TYPE :bit2; + RESERVED0 :bit6; + end; + + TPCIE_STRAP_MISC2=bitpacked record + RESERVED0 :bit1; + STRAP_GEN2_COMPLIANCE :bit1; + STRAP_MSTCPL_TIMEOUT_EN:bit1; + STRAP_GEN3_COMPLIANCE :bit1; + STRAP_TPH_SUPPORTED :bit1; + RESERVED1 :bit27; + end; + + TPCIE_TX_LTR_CNTL=bitpacked record + LTR_PRIV_S_SHORT_VALUE :bit3; + LTR_PRIV_S_LONG_VALUE :bit3; + LTR_PRIV_S_REQUIREMENT :bit1; + LTR_PRIV_NS_SHORT_VALUE :bit3; + LTR_PRIV_NS_LONG_VALUE :bit3; + LTR_PRIV_NS_REQUIREMENT :bit1; + LTR_PRIV_MSG_DIS_IN_PM_NON_D0:bit1; + LTR_PRIV_RST_LTR_IN_DL_DOWN :bit1; + TX_CHK_FC_FOR_L1 :bit1; + RESERVED0 :bit15; + end; + + TPERFCOUNTER_CNTL=bitpacked record + PERFCOUNTER_EVENT_SEL :bit9; + PERFCOUNTER_CVALUE_SEL :bit3; + PERFCOUNTER_INC_MODE :bit2; + PERFCOUNTER_HW_CNTL_SEL :bit1; + PERFCOUNTER_RUNEN_MODE :bit1; + PERFCOUNTER_CNTOFF_SEL :bit5; + PERFCOUNTER_CNTOFF_START_DIS :bit1; + PERFCOUNTER_RESTART_EN :bit1; + PERFCOUNTER_INT_EN :bit1; + PERFCOUNTER_OFF_MASK :bit1; + PERFCOUNTER_ACTIVE :bit1; + PERFCOUNTER_INT_TYPE :bit1; + PERFCOUNTER_COUNTED_VALUE_TYPE:bit1; + RESERVED0 :bit1; + PERFCOUNTER_CNTL_SEL :bit3; + end; + + TPRESCALE_CONTROL=bitpacked record + PRESCALE_MODE:bit2; + RESERVED0 :bit30; + end; + + TREGAMMA_LUT_DATA=bitpacked record + REGAMMA_LUT_DATA:bit19; + RESERVED0 :bit13; + end; + + TRLC_AUTO_PG_CTRL=bitpacked record + AUTO_PG_EN :bit1; + AUTO_GRBM_REG_SAVE_ON_IDLE_EN :bit1; + AUTO_WAKE_UP_EN :bit1; + GRBM_REG_SAVE_GFX_IDLE_THRESHOLD:bit16; + PG_AFTER_GRBM_REG_SAVE_THRESHOLD:bit13; + end; + + TRLC_CP_RESPONSE0=bit32; + + TRLC_CP_RESPONSE1=bit32; + + TRLC_CP_RESPONSE2=bit32; + + TRLC_CP_RESPONSE3=bit32; + + TRLC_CSIB_ADDR_HI=bitpacked record + ADDRESS :bit16; + RESERVED0:bit16; + end; + + TRLC_CSIB_ADDR_LO=bit32; + + TRLC_DEBUG_SELECT=bitpacked record + SELECT :bit8; + RESERVED0:bit6; + RESERVED1:bit1; + RESERVED :bit17; + end; + + TRLC_GPM_LOG_ADDR=bit32; + + TRLC_GPM_LOG_CONT=bit32; + + TRLC_GPM_LOG_SIZE=bit32; + + TRLC_GPU_CLOCK_32=bit32; + + TRLC_LB_CNTR_INIT=bit32; + + TRLC_MEM_SLP_CNTL=bitpacked record + RLC_MEM_LS_EN :bit1; + RLC_MEM_DS_EN :bit1; + RESERVED :bit5; + RLC_LS_DS_BUSY_OVERRIDE:bit1; + RLC_MEM_LS_ON_DELAY :bit8; + RLC_MEM_LS_OFF_DELAY :bit8; + RESERVED1 :bit8; + end; + + TRLC_PERFMON_CNTL=bitpacked record + PERFMON_STATE :bit3; + RESERVED0 :bit7; + PERFMON_SAMPLE_ENABLE:bit1; + RESERVED1 :bit21; + end; + + TRLC_RLCV_COMMAND=bitpacked record + CMD :bit4; + RESERVED:bit28; + end; + + TRLC_SPM_INT_CNTL=bitpacked record + RLC_SPM_INT_CNTL:bit1; + RESERVED0 :bit31; + end; + + TROM_SMC_IND_DATA=bit32; + + TSAM_SAB_RBI_WPTR=bitpacked record + RESERVED0:bit26; + RESERVED1:bit6; + end; + + TSAM_SAB_RBO_WPTR=bitpacked record + RESERVED0:bit30; + RESERVED1:bit2; + end; + + TSCLK_PWRMGT_CNTL=bitpacked record + SCLK_PWRMGT_OFF :bit1; + SCLK_LOW_D1 :bit1; + DYN_PWR_DOWN_EN :bit1; + RESERVED0 :bit1; + RESET_BUSY_CNT :bit1; + RESET_SCLK_CNT :bit1; + RESERVED1 :bit1; + DYN_GFX_CLK_OFF_EN :bit1; + GFX_CLK_FORCE_ON :bit1; + GFX_CLK_REQUEST_OFF :bit1; + GFX_CLK_FORCE_OFF :bit1; + GFX_CLK_OFF_ACPI_D1 :bit1; + GFX_CLK_OFF_ACPI_D2 :bit1; + GFX_CLK_OFF_ACPI_D3 :bit1; + DYN_LIGHT_SLEEP_EN :bit1; + AUTO_SCLK_PULSE_SKIP :bit1; + LIGHT_SLEEP_COUNTER :bit5; + DYNAMIC_PM_EN :bit1; + DPM_DYN_PWR_DOWN_CNTL :bit1; + DPM_DYN_PWR_DOWN_EN :bit1; + RESERVED2 :bit1; + VOLTAGE_UPDATE_EN :bit1; + RESERVED3 :bit2; + FORCE_PM0_INTERRUPT :bit1; + FORCE_PM1_INTERRUPT :bit1; + GFX_VOLTAGE_CHANGE_EN :bit1; + GFX_VOLTAGE_CHANGE_MODE:bit1; + end; + + TSCLV_ALU_CONTROL=bitpacked record + SCL_ALU_DISABLE:bit1; + RESERVED0 :bit31; + end; + + TSCLV_TAP_CONTROL=bitpacked record + SCL_V_NUM_OF_TAPS :bit3; + RESERVED0 :bit1; + SCL_H_NUM_OF_TAPS :bit3; + RESERVED1 :bit1; + SCL_V_NUM_OF_TAPS_C:bit3; + RESERVED2 :bit1; + SCL_H_NUM_OF_TAPS_C:bit3; + RESERVED3 :bit17; + end; + + TSCL_ROUND_OFFSET=bitpacked record + SCL_ROUND_OFFSET_RGB_Y:bit16; + SCL_ROUND_OFFSET_CBCR :bit16; + end; + + TSDMA0_EDC_CONFIG=bitpacked record + RESERVED0 :bit1; + DIS_EDC :bit1; + ECC_INT_ENABLE:bit1; + RESERVED1 :bit29; + end; + + TSDMA0_POWER_CNTL=bitpacked record + RESERVED0 :bit8; + MEM_POWER_OVERRIDE:bit1; + MEM_POWER_LS_EN :bit1; + MEM_POWER_DS_EN :bit1; + MEM_POWER_SD_EN :bit1; + RESERVED1 :bit6; + RESERVED2 :bit4; + RESERVED3 :bit10; + end; + + TSDMA0_STATUS_REG=bitpacked record + IDLE :bit1; + REG_IDLE :bit1; + RB_EMPTY :bit1; + RB_FULL :bit1; + RB_CMD_IDLE :bit1; + RB_CMD_FULL :bit1; + IB_CMD_IDLE :bit1; + IB_CMD_FULL :bit1; + BLOCK_IDLE :bit1; + INSIDE_IB :bit1; + EX_IDLE :bit1; + EX_IDLE_POLL_TIMER_EXPIRE:bit1; + PACKET_READY :bit1; + MC_WR_IDLE :bit1; + SRBM_IDLE :bit1; + CONTEXT_EMPTY :bit1; + DELTA_RPTR_FULL :bit1; + RB_MC_RREQ_IDLE :bit1; + IB_MC_RREQ_IDLE :bit1; + MC_RD_IDLE :bit1; + DELTA_RPTR_EMPTY :bit1; + MC_RD_RET_STALL :bit1; + MC_RD_NO_POLL_IDLE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + PREV_CMD_IDLE :bit1; + SEM_IDLE :bit1; + SEM_REQ_STALL :bit1; + SEM_RESP_STATE :bit2; + INT_IDLE :bit1; + INT_REQ_STALL :bit1; + end; + + TSDMA0_UCODE_ADDR=bitpacked record + VALUE :bit13; + RESERVED0:bit19; + end; + + TSDMA0_UCODE_DATA=bit32; + + TSDMA1_EDC_CONFIG=bitpacked record + RESERVED0 :bit1; + DIS_EDC :bit1; + ECC_INT_ENABLE:bit1; + RESERVED1 :bit29; + end; + + TSDMA1_POWER_CNTL=bitpacked record + RESERVED0 :bit8; + MEM_POWER_OVERRIDE:bit1; + MEM_POWER_LS_EN :bit1; + MEM_POWER_DS_EN :bit1; + MEM_POWER_SD_EN :bit1; + RESERVED1 :bit6; + RESERVED2 :bit4; + RESERVED3 :bit10; + end; + + TSDMA1_STATUS_REG=bitpacked record + IDLE :bit1; + REG_IDLE :bit1; + RB_EMPTY :bit1; + RB_FULL :bit1; + RB_CMD_IDLE :bit1; + RB_CMD_FULL :bit1; + IB_CMD_IDLE :bit1; + IB_CMD_FULL :bit1; + BLOCK_IDLE :bit1; + INSIDE_IB :bit1; + EX_IDLE :bit1; + EX_IDLE_POLL_TIMER_EXPIRE:bit1; + PACKET_READY :bit1; + MC_WR_IDLE :bit1; + SRBM_IDLE :bit1; + CONTEXT_EMPTY :bit1; + DELTA_RPTR_FULL :bit1; + RB_MC_RREQ_IDLE :bit1; + IB_MC_RREQ_IDLE :bit1; + MC_RD_IDLE :bit1; + DELTA_RPTR_EMPTY :bit1; + MC_RD_RET_STALL :bit1; + MC_RD_NO_POLL_IDLE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + PREV_CMD_IDLE :bit1; + SEM_IDLE :bit1; + SEM_REQ_STALL :bit1; + SEM_RESP_STATE :bit2; + INT_IDLE :bit1; + INT_REQ_STALL :bit1; + end; + + TSDMA1_UCODE_ADDR=bitpacked record + VALUE :bit13; + RESERVED0:bit19; + end; + + TSDMA1_UCODE_DATA=bit32; + + TSDMA_PGFSM_WRITE=bit32; + + TSEM_CHICKEN_BITS=bitpacked record + VMID_PIPELINE_EN :bit1; + ENTRY_PIPELINE_EN :bit1; + CHECK_COUNTER_EN :bit1; + ECC_BEHAVIOR :bit2; + SIGNAL_FAIL :bit1; + PHY_TRAN_EN :bit1; + ADDR_CMP_UNTRAN_EN:bit1; + IDLE_COUNTER_INDEX:bit4; + ATCL2_BUS_ID :bit2; + RESERVED0 :bit18; + end; + + TSEM_PERFMON_CNTL=bitpacked record + PERF_ENABLE0:bit1; + PERF_CLEAR0 :bit1; + PERF_SEL0 :bit8; + PERF_ENABLE1:bit1; + PERF_CLEAR1 :bit1; + PERF_SEL1 :bit8; + RESERVED0 :bit12; + end; + + TSETUP_DEBUG_REG0=bitpacked record + su_baryc_cntl_state:bit2; + su_cntl_state :bit4; + RESERVED0 :bit2; + pmode_state :bit6; + ge_stallb :bit1; + geom_enable :bit1; + su_clip_baryc_free :bit2; + su_clip_rtr :bit1; + pfifo_busy :bit1; + su_cntl_busy :bit1; + geom_busy :bit1; + event_id_gated :bit6; + event_gated :bit1; + pmode_prim_gated :bit1; + su_dyn_sclk_vld :bit1; + cl_dyn_sclk_vld :bit1; + end; + + TSETUP_DEBUG_REG1=bitpacked record + y_sort0_gated_23_8:bit16; + x_sort0_gated_23_8:bit16; + end; + + TSETUP_DEBUG_REG2=bitpacked record + y_sort1_gated_23_8:bit16; + x_sort1_gated_23_8:bit16; + end; + + TSETUP_DEBUG_REG3=bitpacked record + y_sort2_gated_23_8:bit16; + x_sort2_gated_23_8:bit16; + end; + + TSETUP_DEBUG_REG4=bitpacked record + attr_indx_sort0_gated:bit14; + null_prim_gated :bit1; + backfacing_gated :bit1; + st_indx_gated :bit3; + clipped_gated :bit1; + dealloc_slot_gated :bit3; + xmajor_gated :bit1; + diamond_rule_gated :bit2; + type_gated :bit3; + fpov_gated :bit2; + eop_gated :bit1; + end; + + TSETUP_DEBUG_REG5=bitpacked record + attr_indx_sort2_gated:bit14; + attr_indx_sort1_gated:bit14; + provoking_vtx_gated :bit2; + valid_prim_gated :bit1; + pa_reg_sclk_vld :bit1; + end; + + TSH_MEM_APE1_BASE=bit32; + + TSLAVE_HANG_ERROR=bitpacked record + SRBM_HANG_ERROR :bit1; + HDP_HANG_ERROR :bit1; + VGA_HANG_ERROR :bit1; + ROM_HANG_ERROR :bit1; + AUDIO_HANG_ERROR :bit1; + CEC_HANG_ERROR :bit1; + RESERVED0 :bit1; + XDMA_HANG_ERROR :bit1; + DOORBELL_HANG_ERROR:bit1; + GARLIC_HANG_ERROR :bit1; + RESERVED1 :bit22; + end; + + TSMBUS_BACO_DUMMY=bit32; + + TSMU_PM_STATUS_10=bit32; + + TSMU_PM_STATUS_11=bit32; + + TSMU_PM_STATUS_12=bit32; + + TSMU_PM_STATUS_13=bit32; + + TSMU_PM_STATUS_14=bit32; + + TSMU_PM_STATUS_15=bit32; + + TSMU_PM_STATUS_16=bit32; + + TSMU_PM_STATUS_17=bit32; + + TSMU_PM_STATUS_18=bit32; + + TSMU_PM_STATUS_19=bit32; + + TSMU_PM_STATUS_20=bit32; + + TSMU_PM_STATUS_21=bit32; + + TSMU_PM_STATUS_22=bit32; + + TSMU_PM_STATUS_23=bit32; + + TSMU_PM_STATUS_24=bit32; + + TSMU_PM_STATUS_25=bit32; + + TSMU_PM_STATUS_26=bit32; + + TSMU_PM_STATUS_27=bit32; + + TSMU_PM_STATUS_28=bit32; + + TSMU_PM_STATUS_29=bit32; + + TSMU_PM_STATUS_30=bit32; + + TSMU_PM_STATUS_31=bit32; + + TSMU_PM_STATUS_32=bit32; + + TSMU_PM_STATUS_33=bit32; + + TSMU_PM_STATUS_34=bit32; + + TSMU_PM_STATUS_35=bit32; + + TSMU_PM_STATUS_36=bit32; + + TSMU_PM_STATUS_37=bit32; + + TSMU_PM_STATUS_38=bit32; + + TSMU_PM_STATUS_39=bit32; + + TSMU_PM_STATUS_40=bit32; + + TSMU_PM_STATUS_41=bit32; + + TSMU_PM_STATUS_42=bit32; + + TSMU_PM_STATUS_43=bit32; + + TSMU_PM_STATUS_44=bit32; + + TSMU_PM_STATUS_45=bit32; + + TSMU_PM_STATUS_46=bit32; + + TSMU_PM_STATUS_47=bit32; + + TSMU_PM_STATUS_48=bit32; + + TSMU_PM_STATUS_49=bit32; + + TSMU_PM_STATUS_50=bit32; + + TSMU_PM_STATUS_51=bit32; + + TSMU_PM_STATUS_52=bit32; + + TSMU_PM_STATUS_53=bit32; + + TSMU_PM_STATUS_54=bit32; + + TSMU_PM_STATUS_55=bit32; + + TSMU_PM_STATUS_56=bit32; + + TSMU_PM_STATUS_57=bit32; + + TSMU_PM_STATUS_58=bit32; + + TSMU_PM_STATUS_59=bit32; + + TSMU_PM_STATUS_60=bit32; + + TSMU_PM_STATUS_61=bit32; + + TSMU_PM_STATUS_62=bit32; + + TSMU_PM_STATUS_63=bit32; + + TSMU_PM_STATUS_64=bit32; + + TSMU_PM_STATUS_65=bit32; + + TSMU_PM_STATUS_66=bit32; + + TSMU_PM_STATUS_67=bit32; + + TSMU_PM_STATUS_68=bit32; + + TSMU_PM_STATUS_69=bit32; + + TSMU_PM_STATUS_70=bit32; + + TSMU_PM_STATUS_71=bit32; + + TSMU_PM_STATUS_72=bit32; + + TSMU_PM_STATUS_73=bit32; + + TSMU_PM_STATUS_74=bit32; + + TSMU_PM_STATUS_75=bit32; + + TSMU_PM_STATUS_76=bit32; + + TSMU_PM_STATUS_77=bit32; + + TSMU_PM_STATUS_78=bit32; + + TSMU_PM_STATUS_79=bit32; + + TSMU_PM_STATUS_80=bit32; + + TSMU_PM_STATUS_81=bit32; + + TSMU_PM_STATUS_82=bit32; + + TSMU_PM_STATUS_83=bit32; + + TSMU_PM_STATUS_84=bit32; + + TSMU_PM_STATUS_85=bit32; + + TSMU_PM_STATUS_86=bit32; + + TSMU_PM_STATUS_87=bit32; + + TSMU_PM_STATUS_88=bit32; + + TSMU_PM_STATUS_89=bit32; + + TSMU_PM_STATUS_90=bit32; + + TSMU_PM_STATUS_91=bit32; + + TSMU_PM_STATUS_92=bit32; + + TSMU_PM_STATUS_93=bit32; + + TSMU_PM_STATUS_94=bit32; + + TSMU_PM_STATUS_95=bit32; + + TSMU_PM_STATUS_96=bit32; + + TSMU_PM_STATUS_97=bit32; + + TSMU_PM_STATUS_98=bit32; + + TSMU_PM_STATUS_99=bit32; + + TSMU_RLC_RESPONSE=bit32; + + TSMU_SMC_IND_DATA=bit32; + TSPI_ARB_CYCLES_0=bitpacked record TS0_DURATION:bit16; TS1_DURATION:bit16; @@ -5584,8 +24076,257 @@ type RESERVED0:bit7; end; + TSPMI_JTAG_OVER_0=bitpacked record + SPMI_IF_JTAG_OVER_HAPPENED:bit1; + RESERVED0 :bit31; + end; + + TSQ_CMD_TIMESTAMP=bitpacked record + TIMESTAMP:bit8; + RESERVED0:bit24; + end; + + TSQ_REG_TIMESTAMP=bitpacked record + TIMESTAMP:bit8; + RESERVED0:bit24; + end; + + TSQ_WAVE_INST_DW0=bit32; + + TSQ_WAVE_INST_DW1=bit32; + + TSRBM_READ_ERROR2=bitpacked record + READ_REQUESTER_ACP :bit1; + READ_REQUESTER_ISP :bit1; + READ_REQUESTER_VCE1:bit1; + RESERVED0 :bit20; + READ_VF :bit1; + READ_VFID :bit4; + RESERVED1 :bit4; + end; + TTA_RESERVED_010C=bit32; + TTHM_TMON0_STATUS=bitpacked record + CURRENT_RDI:bit5; + MEAS_DONE :bit1; + RESERVED0 :bit26; + end; + + TTHM_TMON1_STATUS=bitpacked record + CURRENT_RDI:bit5; + MEAS_DONE :bit1; + RESERVED0 :bit26; + end; + + TTHM_TMON2_CSR_RD=bitpacked record + READ_DATA:bit12; + RESERVED0:bit20; + end; + + TTHM_TMON2_CSR_WR=bitpacked record + CSR_WRITE :bit1; + CSR_READ :bit1; + CSR_ADDR :bit10; + WRITE_DATA:bit12; + SPARE :bit1; + RESERVED0 :bit7; + end; + + TTHM_TMON2_STATUS=bitpacked record + CURRENT_RDI:bit5; + MEAS_DONE :bit1; + RESERVED0 :bit26; + end; + + TUNIPHY_PLL_FBDIV=bitpacked record + RESERVED0 :bit2; + UNIPHY_PLL_FBDIV_FRACTION:bit14; + UNIPHY_PLL_FBDIV :bit12; + RESERVED1 :bit4; + end; + + TUNP_GRPH_CONTROL=bitpacked record + GRPH_DEPTH :bit2; + GRPH_NUM_BANKS :bit2; + GRPH_Z :bit2; + GRPH_BANK_WIDTH :bit2; + GRPH_FORMAT :bit3; + GRPH_BANK_HEIGHT :bit2; + GRPH_TILE_SPLIT :bit3; + GRPH_ADDRESS_TRANSLATION_ENABLE:bit1; + GRPH_PRIVILEGED_ACCESS_ENABLE :bit1; + GRPH_MACRO_TILE_ASPECT :bit2; + GRPH_ARRAY_MODE :bit4; + GRPH_PIPE_CONFIG :bit5; + GRPH_MICRO_TILE_MODE :bit2; + GRPH_COLOR_EXPANSION_MODE :bit1; + end; + + TUNP_GRPH_PITCH_C=bitpacked record + GRPH_PITCH_C:bit15; + RESERVED0 :bit17; + end; + + TUNP_GRPH_PITCH_L=bitpacked record + GRPH_PITCH_L:bit15; + RESERVED0 :bit17; + end; + + TUNP_GRPH_X_END_C=bitpacked record + GRPH_X_END_C:bit15; + RESERVED0 :bit17; + end; + + TUNP_GRPH_X_END_L=bitpacked record + GRPH_X_END_L:bit15; + RESERVED0 :bit17; + end; + + TUNP_GRPH_Y_END_C=bitpacked record + GRPH_Y_END_C:bit15; + RESERVED0 :bit17; + end; + + TUNP_GRPH_Y_END_L=bitpacked record + GRPH_Y_END_L:bit15; + RESERVED0 :bit17; + end; + + TUVD_CGC_MEM_CTRL=bitpacked record + LMI_MC_LS_EN :bit1; + MPC_LS_EN :bit1; + MPRD_LS_EN :bit1; + WCB_LS_EN :bit1; + UDEC_RE_LS_EN :bit1; + UDEC_CM_LS_EN :bit1; + UDEC_IT_LS_EN :bit1; + UDEC_DB_LS_EN :bit1; + UDEC_MP_LS_EN :bit1; + SYS_LS_EN :bit1; + VCPU_LS_EN :bit1; + SCPU_LS_EN :bit1; + MIF_LS_EN :bit1; + LCM_LS_EN :bit1; + JPEG_LS_EN :bit1; + JPEG2_LS_EN :bit1; + LS_SET_DELAY :bit4; + LS_CLEAR_DELAY:bit4; + RESERVED0 :bit8; + end; + + TUVD_LMI_ADDR_EXT=bitpacked record + VCPU_ADDR_EXT :bit4; + CM_ADDR_EXT :bit4; + IT_ADDR_EXT :bit4; + VCPU_VM_ADDR_EXT :bit4; + RE_ADDR_EXT :bit4; + MP_ADDR_EXT :bit4; + VCPU_NC0_ADDR_EXT:bit4; + VCPU_NC1_ADDR_EXT:bit4; + end; + + TUVD_MP_SWAP_CNTL=bitpacked record + MP_REF0_MC_SWAP :bit2; + MP_REF1_MC_SWAP :bit2; + MP_REF2_MC_SWAP :bit2; + MP_REF3_MC_SWAP :bit2; + MP_REF4_MC_SWAP :bit2; + MP_REF5_MC_SWAP :bit2; + MP_REF6_MC_SWAP :bit2; + MP_REF7_MC_SWAP :bit2; + MP_REF8_MC_SWAP :bit2; + MP_REF9_MC_SWAP :bit2; + MP_REF10_MC_SWAP:bit2; + MP_REF11_MC_SWAP:bit2; + MP_REF12_MC_SWAP:bit2; + MP_REF13_MC_SWAP:bit2; + MP_REF14_MC_SWAP:bit2; + MP_REF15_MC_SWAP:bit2; + end; + + TUVD_PGFSM_CONFIG=bitpacked record + UVD_PGFSM_FSM_ADDR :bit8; + UVD_PGFSM_POWER_DOWN:bit1; + UVD_PGFSM_POWER_UP :bit1; + UVD_PGFSM_P1_SELECT :bit1; + UVD_PGFSM_P2_SELECT :bit1; + UVD_PGFSM_WRITE :bit1; + UVD_PGFSM_READ :bit1; + RESERVED0 :bit14; + UVD_PGFSM_REG_ADDR :bit4; + end; + + TUVD_POWER_STATUS=bitpacked record + UVD_POWER_STATUS :bit2; + UVD_PG_MODE :bit1; + UVD_STATUS_CHECK_TIMEOUT:bit1; + PWR_ON_CHECK_TIMEOUT :bit1; + PWR_OFF_CHECK_TIMEOUT :bit1; + UVD_PGFSM_TIMEOUT_MODE :bit2; + UVD_PG_EN :bit1; + PAUSE_DPG_REQ :bit1; + PAUSE_DPG_ACK :bit1; + RESERVED0 :bit21; + end; + + TVDDGFX_IDLE_EXIT=bitpacked record + BIF_EXIT_REQ:bit1; + RESERVED0 :bit31; + end; + + TVGA_MAIN_CONTROL=bitpacked record + VGA_CRTC_TIMEOUT :bit2; + RESERVED0 :bit1; + VGA_RENDER_TIMEOUT_COUNT :bit2; + VGA_VIRTUAL_VERTICAL_RETRACE_DURATION :bit3; + VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT :bit2; + RESERVED1 :bit2; + VGA_MC_WRITE_CLEAN_WAIT_DELAY :bit4; + VGA_READBACK_NO_DISPLAY_SOURCE_SELECT :bit2; + RESERVED2 :bit6; + VGA_READBACK_CRT_INTR_SOURCE_SELECT :bit2; + VGA_READBACK_SENSE_SWITCH_SELECT :bit1; + VGA_READ_URGENT_ENABLE :bit1; + VGA_WRITES_URGENT_ENABLE :bit1; + VGA_EXTERNAL_DAC_SENSE :bit1; + RESERVED3 :bit1; + VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT:bit1; + end; + + TVGA_MODE_CONTROL=bitpacked record + VGA_ATI_LINEAR :bit1; + RESERVED0 :bit3; + VGA_LUT_PALETTE_UPDATE_MODE:bit2; + RESERVED1 :bit2; + VGA_128K_APERTURE_PAGING :bit1; + RESERVED2 :bit7; + VGA_TEXT_132_COLUMNS_EN :bit1; + RESERVED3 :bit15; + end; + + TVGA_STATUS_CLEAR=bitpacked record + VGA_MEM_ACCESS_INT_CLEAR :bit1; + RESERVED0 :bit7; + VGA_REG_ACCESS_INT_CLEAR :bit1; + RESERVED1 :bit7; + VGA_DISPLAY_SWITCH_INT_CLEAR :bit1; + RESERVED2 :bit7; + VGA_MODE_AUTO_TRIGGER_INT_CLEAR:bit1; + RESERVED3 :bit7; + end; + + TVGA_TEST_CONTROL=bitpacked record + VGA_TEST_ENABLE :bit1; + RESERVED0 :bit7; + VGA_TEST_RENDER_START :bit1; + RESERVED1 :bit7; + VGA_TEST_RENDER_DONE :bit1; + RESERVED2 :bit7; + VGA_TEST_RENDER_DISPBUF_SELECT:bit1; + RESERVED3 :bit7; + end; + TVGT_DMA_MAX_SIZE=bit32; TVGT_LS_HS_CONFIG=bitpacked record @@ -5604,6 +24345,228 @@ type RESERVED0:bit16; end; + TVM_CONTEXT0_CNTL=bitpacked record + ENABLE_CONTEXT :bit1; + PAGE_TABLE_DEPTH :bit2; + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + RESERVED0 :bit1; + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT:bit1; + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + RESERVED1 :bit1; + PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + PDE0_PROTECTION_FAULT_ENABLE_SAVE :bit1; + VALID_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + VALID_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + VALID_PROTECTION_FAULT_ENABLE_SAVE :bit1; + READ_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + READ_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + READ_PROTECTION_FAULT_ENABLE_SAVE :bit1; + WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + WRITE_PROTECTION_FAULT_ENABLE_SAVE :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_SAVE :bit1; + PAGE_TABLE_BLOCK_SIZE :bit4; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit2; + end; + + TVM_CONTEXT1_CNTL=bitpacked record + ENABLE_CONTEXT :bit1; + PAGE_TABLE_DEPTH :bit2; + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + RESERVED0 :bit1; + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT:bit1; + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + RESERVED1 :bit1; + PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + PDE0_PROTECTION_FAULT_ENABLE_SAVE :bit1; + VALID_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + VALID_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + VALID_PROTECTION_FAULT_ENABLE_SAVE :bit1; + READ_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + READ_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + READ_PROTECTION_FAULT_ENABLE_SAVE :bit1; + WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + WRITE_PROTECTION_FAULT_ENABLE_SAVE :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT :bit1; + EXECUTE_PROTECTION_FAULT_ENABLE_SAVE :bit1; + PAGE_TABLE_BLOCK_SIZE :bit4; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit2; + end; + + TXDMA_MSTR_HEIGHT=bitpacked record + XDMA_MSTR_ACTIVE_HEIGHT:bit14; + RESERVED0 :bit2; + XDMA_MSTR_FRAME_HEIGHT :bit14; + RESERVED1 :bit2; + end; + + TXDMA_MSTR_STATUS=bitpacked record + XDMA_MSTR_VCOUNT_CURRENT :bit14; + RESERVED0 :bit2; + XDMA_MSTR_WRITE_LINE_CURRENT:bit12; + XDMA_MSTR_STATUS_SELECT :bit3; + RESERVED1 :bit1; + end; + + TAUDIO_DESCRIPTOR0=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR1=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR2=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR3=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR4=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR5=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR6=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR7=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR8=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR9=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUX_GTC_SYNC_DATA=bitpacked record + AUX_GTC_DATA_RW :bit1; + RESERVED0 :bit7; + AUX_GTC_DATA :bit8; + AUX_GTC_INDEX :bit6; + RESERVED1 :bit9; + AUX_GTC_INDEX_AUTOINCREMENT_DISABLE:bit1; + end; + + TBIF_DOORBELL_CNTL=bitpacked record + SELF_RING_DIS :bit1; + TRANS_CHECK_DIS :bit1; + UNTRANS_LBACK_EN :bit1; + NON_CONSECUTIVE_BE_ZERO_DIS:bit1; + DOORBELL_MONITOR_EN :bit1; + DOORBELL_INTERRUPT_STATUS :bit1; + RESERVED0 :bit10; + DOORBELL_INTERRUPT_CLEAR :bit1; + RESERVED1 :bit7; + DB_MNTR_INTGEN_DIS :bit1; + DB_MNTR_INTGEN_MODE_0 :bit1; + DB_MNTR_INTGEN_MODE_1 :bit1; + DB_MNTR_INTGEN_MODE_2 :bit1; + RESERVED2 :bit4; + end; + + TBIF_IMPCTL_RXCNTL=bitpacked record + RX_ADJUST :bit3; + RX_BIAS_HIGH :bit1; + CONT_AFTER_RX_DECT :bit1; + RESERVED0 :bit1; + SUSPEND :bit1; + FORCE_RST :bit1; + LOWER_RX_ADJ_THRESH:bit4; + LOWER_RX_ADJ :bit1; + UPPER_RX_ADJ_THRESH:bit4; + UPPER_RX_ADJ :bit1; + RX_IMP_LOCKED :bit1; + RX_IMP_READBACK_SEL:bit1; + RX_IMP_READBACK :bit4; + RESERVED1 :bit4; + RX_CMP_AMBIG :bit1; + CAL_DONE :bit1; + RESERVED2 :bit2; + end; + + TBIF_RFE_SNOOP_REG=bitpacked record + REG_SNOOP_ARBITER :bit1; + REG_SNOOP_ALLMASTER:bit1; + RESERVED0 :bit30; + end; + + TBIF_RLC_INTR_CNTL=bitpacked record + RLC_HVCMD_INTERRUPT:bit1; + RESERVED0 :bit31; + end; + + TBIF_VDDGFX_FB_CMP=bitpacked record + VDDGFX_FB_HDP_CMP_EN :bit1; + VDDGFX_FB_HDP_STALL_EN :bit1; + VDDGFX_FB_XDMA_CMP_EN :bit1; + VDDGFX_FB_XDMA_STALL_EN:bit1; + VDDGFX_FB_VGA_CMP_EN :bit1; + VDDGFX_FB_VGA_STALL_EN :bit1; + RESERVED0 :bit26; + end; + TCB_BLEND0_CONTROL=bitpacked record COLOR_SRCBLEND :bit5; COLOR_COMB_FCN :bit3; @@ -5722,6 +24685,307 @@ type SOFT_OVERRIDE0:bit1; end; + TCC_GC_PRIM_CONFIG=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit15; + INACTIVE_IA :bit2; + RESERVED2 :bit6; + INACTIVE_VGT_PA:bit4; + RESERVED3 :bit4; + end; + + TCC_MC_MAX_CHANNEL=bitpacked record + RESERVED0:bit1; + NOOFCHAN :bit4; + RESERVED1:bit27; + end; + + TCC_RB_DAISY_CHAIN=bitpacked record + RB_0:bit4; + RB_1:bit4; + RB_2:bit4; + RB_3:bit4; + RB_4:bit4; + RB_5:bit4; + RB_6:bit4; + RB_7:bit4; + end; + + TCC_SCLK_VID_FUSES=bitpacked record + SClkVid0:bit8; + SClkVid1:bit8; + SClkVid2:bit8; + SClkVid3:bit8; + end; + + TCC_SMU_MISC_FUSES=bitpacked record + RESERVED0 :bit1; + IOMMU_V2_DISABLE :bit1; + MinSClkDid :bit7; + MISC_SPARE :bit2; + PostResetGnbClkDid:bit7; + L2IMU_tn2_dtc_half:bit1; + L2IMU_tn2_ptc_half:bit1; + L2IMU_tn2_itc_half:bit1; + L2IMU_tn2_pdc_half:bit1; + L2IMU_tn2_ptc_dis :bit1; + L2IMU_tn2_itc_dis :bit1; + RESERVED1 :bit3; + VCE_DISABLE :bit1; + IOC_IOMMU_DISABLE :bit1; + GNB_SPARE :bit2; + RESERVED2 :bit1; + end; + + TCGTT_BCI_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + CORE6_OVERRIDE:bit1; + CORE5_OVERRIDE:bit1; + CORE4_OVERRIDE:bit1; + CORE3_OVERRIDE:bit1; + CORE2_OVERRIDE:bit1; + CORE1_OVERRIDE:bit1; + CORE0_OVERRIDE:bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_CPC_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit17; + SOFT_OVERRIDE_PERFMON:bit1; + SOFT_OVERRIDE_DYN :bit1; + SOFT_OVERRIDE_REG :bit1; + end; + + TCGTT_CPF_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit17; + SOFT_OVERRIDE_PERFMON:bit1; + SOFT_OVERRIDE_DYN :bit1; + SOFT_OVERRIDE_REG :bit1; + end; + + TCGTT_GDS_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_RLC_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit18; + SOFT_OVERRIDE_DYN:bit1; + SOFT_OVERRIDE_REG:bit1; + end; + + TCGTT_SPI_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit6; + GRP5_CG_OFF_HYST :bit6; + GRP5_CG_OVERRIDE :bit1; + RESERVED1 :bit1; + ALL_CLK_ON_OVERRIDE:bit1; + GRP3_OVERRIDE :bit1; + GRP2_OVERRIDE :bit1; + GRP1_OVERRIDE :bit1; + GRP0_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_SQG_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit16; + TTRACE_OVERRIDE :bit1; + PERFMON_OVERRIDE:bit1; + CORE_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCGTT_SX_CLK_CTRL0=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_SX_CLK_CTRL1=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + DBG_EN :bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_SX_CLK_CTRL2=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + DBG_EN :bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_SX_CLK_CTRL3=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + DBG_EN :bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_SX_CLK_CTRL4=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED :bit12; + DBG_EN :bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_TCI_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_TCP_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + SOFT_OVERRIDE6:bit1; + SOFT_OVERRIDE5:bit1; + SOFT_OVERRIDE4:bit1; + SOFT_OVERRIDE3:bit1; + SOFT_OVERRIDE2:bit1; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCGTT_VGT_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit12; + SOFT_OVERRIDE7:bit1; + PERF_ENABLE :bit1; + DBG_ENABLE :bit1; + SOFT_OVERRIDE4:bit1; + TESS_OVERRIDE :bit1; + GS_OVERRIDE :bit1; + CORE_OVERRIDE :bit1; + REG_OVERRIDE :bit1; + end; + + TCG_CLKPIN_CNTL_DC=bitpacked record + OSC_EN :bit1; + XTL_LOW_GAIN :bit2; + RESERVED0 :bit6; + XTL_XOCLK_DRV_R_EN:bit1; + XTALIN_SEL :bit3; + RESERVED1 :bit19; + end; + + TCG_SPLL_FUNC_CNTL=bitpacked record + SPLL_RESET :bit1; + SPLL_PWRON :bit1; + SPLL_DIVEN :bit1; + SPLL_BYPASS_EN :bit1; + SPLL_BYPASS_THRU_DFS:bit1; + SPLL_REF_DIV :bit6; + SPLL_PDIV_A_UPDATE :bit1; + SPLL_PDIV_A_EN :bit1; + SPLL_BG_PWRON :bit1; + SPLL_BGADJ :bit4; + SPLL_PDIV_A :bit7; + SPLL_REG_BIAS :bit3; + SPLL_OTEST_LOCK_EN :bit1; + RESERVED0 :bit3; + end; + + TCG_THERMAL_STATUS=bitpacked record + SPARE :bit9; + FDO_PWM_DUTY:bit8; + THERM_ALERT :bit1; + GEN_STATUS :bit4; + RESERVED0 :bit10; + end; + + TCLIENT0_OFFSET_HI=bit32; + + TCLIENT1_OFFSET_HI=bit32; + + TCLIENT2_OFFSET_HI=bit32; + + TCLIENT3_OFFSET_HI=bit32; + + TCLIENT4_OFFSET_HI=bit32; + + TCNV_TEST_CRC_BLUE=bitpacked record + RESERVED0 :bit4; + CNV_TEST_CRC_BLUE_MASK:bit12; + CNV_TEST_CRC_SIG_BLUE :bit16; + end; + + TCOHER_DEST_BASE_0=bit32; + + TCOHER_DEST_BASE_1=bit32; + + TCOHER_DEST_BASE_2=bit32; + + TCOHER_DEST_BASE_3=bit32; + TCOMPUTE_PGM_RSRC1=bitpacked record VGPRS :bit6; SGPRS :bit4; @@ -5757,6 +25021,13 @@ type TCOMPUTE_RESTART_Z=bit32; + TCORB_READ_POINTER=bitpacked record + CORB_READ_POINTER :bit8; + RESERVED0 :bit7; + CORB_READ_POINTER_RESET:bit1; + RESERVED1 :bit16; + end; + TCP_APPEND_ADDR_HI=bitpacked record MEM_ADDR_HI :bit16; CS_PS_SEL :bit1; @@ -6019,6 +25290,45 @@ type RESERVED0 :bit16; end; + TCP_ME_HEADER_DUMP=bit32; + + TCP_ME_MC_RADDR_HI=bitpacked record + ME_MC_RADDR_HI:bit16; + RESERVED0 :bit4; + MTYPE :bit2; + CACHE_POLICY :bit1; + RESERVED1 :bit9; + end; + + TCP_ME_MC_RADDR_LO=bitpacked record + ME_MC_RADDR_SWAP:bit2; + ME_MC_RADDR_LO :bit30; + end; + + TCP_ME_MC_WADDR_HI=bitpacked record + ME_MC_WADDR_HI:bit16; + RESERVED0 :bit4; + MTYPE :bit2; + CACHE_POLICY :bit1; + RESERVED1 :bit9; + end; + + TCP_ME_MC_WADDR_LO=bitpacked record + ME_MC_WADDR_SWAP:bit2; + ME_MC_WADDR_LO :bit30; + end; + + TCP_ME_MC_WDATA_HI=bit32; + + TCP_ME_MC_WDATA_LO=bit32; + + TCP_PERFCOUNTER_HI=bitpacked record + RESERVED0:bit16; + RESERVED1:bit16; + end; + + TCP_PERFCOUNTER_LO=bit32; + TCP_PFP_IB_CONTROL=bitpacked record IB_EN :bit8; RESERVED0:bit24; @@ -6031,6 +25341,21 @@ type TCP_PFP_UCODE_DATA=bit32; + TCP_RING0_PRIORITY=bitpacked record + PRIORITY :bit2; + RESERVED0:bit30; + end; + + TCP_RING1_PRIORITY=bitpacked record + PRIORITY :bit2; + RESERVED0:bit30; + end; + + TCP_RING2_PRIORITY=bitpacked record + PRIORITY :bit2; + RESERVED0:bit30; + end; + TCP_ROQ_THRESHOLDS=bitpacked record IB1_START:bit8; IB2_START:bit8; @@ -6046,6 +25371,39 @@ type RESERVED0 :bit8; end; + TCRTC_CRC0_DATA_RG=bitpacked record + CRC0_R_CR:bit16; + CRC0_G_Y :bit16; + end; + + TCRTC_CRC1_DATA_RG=bitpacked record + CRC1_R_CR:bit16; + CRC1_G_Y :bit16; + end; + + TCRTC_DTMTEST_CNTL=bitpacked record + CRTC_DTMTEST_CRTC_EN:bit1; + CRTC_DTMTEST_CLK_DIV:bit4; + RESERVED0 :bit27; + end; + + TCRTC_FLOW_CONTROL=bitpacked record + CRTC_FLOW_CONTROL_SOURCE_SELECT:bit5; + RESERVED0 :bit3; + CRTC_FLOW_CONTROL_POLARITY :bit1; + RESERVED1 :bit7; + CRTC_FLOW_CONTROL_GRANULARITY :bit1; + RESERVED2 :bit7; + CRTC_FLOW_CONTROL_INPUT_STATUS :bit1; + RESERVED3 :bit7; + end; + + TDAC_SOURCE_SELECT=bitpacked record + DAC_SOURCE_SELECT:bit3; + DAC_TV_SELECT :bit1; + RESERVED0 :bit28; + end; + TDB_RENDER_CONTROL=bitpacked record DEPTH_CLEAR_ENABLE :bit1; STENCIL_CLEAR_ENABLE :bit1; @@ -6090,6 +25448,738 @@ type RESERVED0:bit1; end; + TDCCG_GTC_DTO_INCR=bit32; + + TDCCG_PERFMON_CNTL=bitpacked record + DCCG_PERF_DISPCLK_ENABLE :bit1; + DCCG_PERF_DPREFCLK_ENABLE :bit1; + DCCG_PERF_PIXCLK1_ENABLE :bit1; + DCCG_PERF_PIXCLK2_ENABLE :bit1; + DCCG_PERF_PIXCLK0_ENABLE :bit1; + DCCG_PERF_RUN :bit1; + DCCG_PERF_MODE_VSYNC :bit1; + DCCG_PERF_MODE_HSYNC :bit1; + DCCG_PERF_CRTC_SEL :bit3; + DCCG_PERF_XTALIN_PULSE_DIV:bit21; + end; + + TDCCG_TEST_CLK_SEL=bitpacked record + DCCG_TEST_CLK_GENERICA_SEL:bit9; + RESERVED0 :bit3; + DCCG_TEST_CLK_GENERICA_INV:bit1; + RESERVED1 :bit3; + DCCG_TEST_CLK_GENERICB_SEL:bit9; + RESERVED2 :bit3; + DCCG_TEST_CLK_GENERICB_INV:bit1; + RESERVED3 :bit3; + end; + + TDCFE_MEM_PWR_CTRL=bitpacked record + DCP_LUT_MEM_PWR_FORCE :bit2; + DCP_LUT_MEM_PWR_DIS :bit1; + DCP_REGAMMA_MEM_PWR_FORCE:bit2; + DCP_REGAMMA_MEM_PWR_DIS :bit1; + SCL_COEFF_MEM_PWR_FORCE :bit2; + SCL_COEFF_MEM_PWR_DIS :bit1; + DCP_CURSOR_MEM_PWR_FORCE :bit2; + DCP_CURSOR_MEM_PWR_DIS :bit1; + LB0_ALPHA_MEM_PWR_FORCE :bit2; + LB0_ALPHA_MEM_PWR_DIS :bit1; + LB1_ALPHA_MEM_PWR_FORCE :bit2; + LB1_ALPHA_MEM_PWR_DIS :bit1; + LB2_ALPHA_MEM_PWR_FORCE :bit2; + LB2_ALPHA_MEM_PWR_DIS :bit1; + LB0_MEM_PWR_FORCE :bit2; + LB0_MEM_PWR_DIS :bit1; + LB1_MEM_PWR_FORCE :bit2; + LB1_MEM_PWR_DIS :bit1; + LB2_MEM_PWR_FORCE :bit2; + LB2_MEM_PWR_DIS :bit1; + RESERVED0 :bit2; + end; + + TDCIO_DEBUG_CONFIG=bitpacked record + DCIO_DBG_EN:bit1; + RESERVED0 :bit31; + end; + + TDCI_CLK_RAMP_CNTL=bitpacked record + DISPCLK_G_MCIF_DWB_GATE_DIS :bit1; + SCLK_G_MCIF_DWB_GATE_DIS :bit1; + DISPCLK_G_MCIF_CWB0_GATE_DIS:bit1; + SCLK_G_MCIF_CWB0_GATE_DIS :bit1; + DISPCLK_G_MCIF_CWB1_GATE_DIS:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit1; + RESERVED22 :bit1; + RESERVED23 :bit1; + RESERVED24 :bit1; + RESERVED25 :bit1; + SCLK_G_MCIF_CWB1_GATE_DIS :bit1; + end; + + TDCI_MEM_PWR_CNTL2=bitpacked record + DMIF0_ASYNC_MEM_PWR_FORCE:bit2; + DMIF0_ASYNC_MEM_PWR_DIS :bit1; + DMIF0_DATA_MEM_PWR_FORCE :bit2; + DMIF0_DATA_MEM_PWR_DIS :bit1; + DMIF0_CHUNK_MEM_PWR_FORCE:bit1; + DMIF0_CHUNK_MEM_PWR_DIS :bit1; + DMIF1_ASYNC_MEM_PWR_FORCE:bit2; + DMIF1_ASYNC_MEM_PWR_DIS :bit1; + DMIF1_DATA_MEM_PWR_FORCE :bit2; + DMIF1_DATA_MEM_PWR_DIS :bit1; + DMIF1_CHUNK_MEM_PWR_FORCE:bit1; + DMIF1_CHUNK_MEM_PWR_DIS :bit1; + DMIF2_ASYNC_MEM_PWR_FORCE:bit2; + DMIF2_ASYNC_MEM_PWR_DIS :bit1; + DMIF2_DATA_MEM_PWR_FORCE :bit2; + DMIF2_DATA_MEM_PWR_DIS :bit1; + DMIF2_CHUNK_MEM_PWR_FORCE:bit1; + DMIF2_CHUNK_MEM_PWR_DIS :bit1; + DMIF3_ASYNC_MEM_PWR_FORCE:bit2; + DMIF3_ASYNC_MEM_PWR_DIS :bit1; + DMIF3_DATA_MEM_PWR_FORCE :bit2; + DMIF3_DATA_MEM_PWR_DIS :bit1; + DMIF3_CHUNK_MEM_PWR_FORCE:bit1; + DMIF3_CHUNK_MEM_PWR_DIS :bit1; + end; + + TDCI_MEM_PWR_CNTL3=bitpacked record + DMIF4_ASYNC_MEM_PWR_FORCE :bit2; + DMIF4_ASYNC_MEM_PWR_DIS :bit1; + DMIF4_DATA_MEM_PWR_FORCE :bit2; + DMIF4_DATA_MEM_PWR_DIS :bit1; + DMIF4_CHUNK_MEM_PWR_FORCE :bit1; + DMIF4_CHUNK_MEM_PWR_DIS :bit1; + DMIF5_ASYNC_MEM_PWR_FORCE :bit2; + DMIF5_ASYNC_MEM_PWR_DIS :bit1; + DMIF5_DATA_MEM_PWR_FORCE :bit2; + DMIF5_DATA_MEM_PWR_DIS :bit1; + DMIF5_CHUNK_MEM_PWR_FORCE :bit1; + DMIF5_CHUNK_MEM_PWR_DIS :bit1; + DMIF_RDREQ_MEM_PWR_MODE_SEL:bit2; + DMIF_ASYNC_MEM_PWR_MODE_SEL:bit2; + DMIF_DATA_MEM_PWR_MODE_SEL :bit2; + DMCU_ERAM_MEM_PWR_MODE_SEL :bit1; + FBC_MEM_PWR_MODE_SEL :bit2; + MCIF_CWB0_MEM_PWR_MODE_SEL :bit2; + MCIF_CWB1_MEM_PWR_MODE_SEL :bit2; + MCIF_DWB_MEM_PWR_MODE_SEL :bit2; + RESERVED0 :bit1; + end; + + TDCO_CLK_RAMP_CNTL=bitpacked record + RESERVED0 :bit4; + REFCLK_R_DCO_RAMP_DIS :bit1; + DISPCLK_R_DCO_RAMP_DIS :bit1; + DISPCLK_G_ABM_RAMP_DIS :bit1; + DISPCLK_G_DVO_RAMP_DIS :bit1; + DISPCLK_G_DACA_RAMP_DIS:bit1; + DISPCLK_G_DACB_RAMP_DIS:bit1; + RESERVED1 :bit6; + DISPCLK_G_FMT0_RAMP_DIS:bit1; + DISPCLK_G_FMT1_RAMP_DIS:bit1; + DISPCLK_G_FMT2_RAMP_DIS:bit1; + DISPCLK_G_FMT3_RAMP_DIS:bit1; + DISPCLK_G_FMT4_RAMP_DIS:bit1; + DISPCLK_G_FMT5_RAMP_DIS:bit1; + RESERVED2 :bit2; + DISPCLK_G_DIGA_RAMP_DIS:bit1; + DISPCLK_G_DIGB_RAMP_DIS:bit1; + DISPCLK_G_DIGC_RAMP_DIS:bit1; + DISPCLK_G_DIGD_RAMP_DIS:bit1; + DISPCLK_G_DIGE_RAMP_DIS:bit1; + DISPCLK_G_DIGF_RAMP_DIS:bit1; + DISPCLK_G_DIGG_RAMP_DIS:bit1; + RESERVED3 :bit1; + end; + + TDCO_MEM_PWR_CTRL2=bitpacked record + HDMI_MEM_PWR_MODE_SEL:bit2; + RESERVED0 :bit30; + end; + + TDC_DVODATA_CONFIG=bitpacked record + RESERVED0 :bit19; + VIP_MUX_EN :bit1; + VIP_ALTER_MAPPING_EN:bit1; + DVO_ALTER_MAPPING_EN:bit1; + RESERVED1 :bit10; + end; + + TDC_GPIO_DDC1_MASK=bitpacked record + DC_GPIO_DDC1CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC1CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC1CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC1DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC1DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC1DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD1_MODE :bit1; + RESERVED6 :bit3; + AUX1_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC1_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC1CLK_STR :bit4; + DC_GPIO_DDC1DATA_STR :bit4; + end; + + TDC_GPIO_DDC2_MASK=bitpacked record + DC_GPIO_DDC2CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC2CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC2CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC2DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC2DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC2DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD2_MODE :bit1; + RESERVED6 :bit3; + AUX2_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC2_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC2CLK_STR :bit4; + DC_GPIO_DDC2DATA_STR :bit4; + end; + + TDC_GPIO_DDC3_MASK=bitpacked record + DC_GPIO_DDC3CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC3CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC3CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC3DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC3DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC3DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD3_MODE :bit1; + RESERVED6 :bit3; + AUX3_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC3_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC3CLK_STR :bit4; + DC_GPIO_DDC3DATA_STR :bit4; + end; + + TDC_GPIO_DDC4_MASK=bitpacked record + DC_GPIO_DDC4CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC4CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC4CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC4DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC4DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC4DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD4_MODE :bit1; + RESERVED6 :bit3; + AUX4_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC4_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC4CLK_STR :bit4; + DC_GPIO_DDC4DATA_STR :bit4; + end; + + TDC_GPIO_DDC5_MASK=bitpacked record + DC_GPIO_DDC5CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC5CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC5CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC5DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC5DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC5DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD5_MODE :bit1; + RESERVED6 :bit3; + AUX5_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC5_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC5CLK_STR :bit4; + DC_GPIO_DDC5DATA_STR :bit4; + end; + + TDC_GPIO_DDC6_MASK=bitpacked record + DC_GPIO_DDC6CLK_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_DDC6CLK_PD_EN :bit1; + RESERVED1 :bit1; + DC_GPIO_DDC6CLK_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DDC6DATA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DDC6DATA_PD_EN:bit1; + RESERVED4 :bit1; + DC_GPIO_DDC6DATA_RECV :bit1; + RESERVED5 :bit1; + AUX_PAD6_MODE :bit1; + RESERVED6 :bit3; + AUX6_POL :bit1; + RESERVED7 :bit1; + ALLOW_HW_DDC6_PD_EN :bit1; + RESERVED8 :bit1; + DC_GPIO_DDC6CLK_STR :bit4; + DC_GPIO_DDC6DATA_STR :bit4; + end; + + TDC_GPIO_DDCVGA_EN=bitpacked record + DC_GPIO_DDCVGACLK_EN :bit1; + RESERVED0 :bit7; + DC_GPIO_DDCVGADATA_EN:bit1; + RESERVED1 :bit23; + end; + + TDC_GPIO_DVODATA_A=bitpacked record + DC_GPIO_DVODATA_A :bit24; + DC_GPIO_DVOCNTL_A :bit5; + DC_GPIO_DVOCLK_A :bit1; + DC_GPIO_MVP_DVOCNTL_A:bit2; + end; + + TDC_GPIO_DVODATA_Y=bitpacked record + DC_GPIO_DVODATA_Y :bit24; + DC_GPIO_DVOCNTL_Y :bit5; + DC_GPIO_DVOCLK_Y :bit1; + DC_GPIO_MVP_DVOCNTL_Y:bit2; + end; + + TDC_GPIO_GENERIC_A=bitpacked record + DC_GPIO_GENERICA_A:bit1; + RESERVED0 :bit7; + DC_GPIO_GENERICB_A:bit1; + RESERVED1 :bit7; + DC_GPIO_GENERICC_A:bit1; + RESERVED2 :bit3; + DC_GPIO_GENERICD_A:bit1; + DC_GPIO_GENERICE_A:bit1; + DC_GPIO_GENERICF_A:bit1; + DC_GPIO_GENERICG_A:bit1; + RESERVED3 :bit8; + end; + + TDC_GPIO_GENERIC_Y=bitpacked record + DC_GPIO_GENERICA_Y:bit1; + RESERVED0 :bit7; + DC_GPIO_GENERICB_Y:bit1; + RESERVED1 :bit7; + DC_GPIO_GENERICC_Y:bit1; + RESERVED2 :bit3; + DC_GPIO_GENERICD_Y:bit1; + DC_GPIO_GENERICE_Y:bit1; + DC_GPIO_GENERICF_Y:bit1; + DC_GPIO_GENERICG_Y:bit1; + RESERVED3 :bit8; + end; + + TDC_GPIO_I2CPAD_EN=bitpacked record + DC_GPIO_SCL_EN:bit1; + DC_GPIO_SDA_EN:bit1; + RESERVED0 :bit30; + end; + + TDC_GPIO_PWRSEQ_EN=bitpacked record + DC_GPIO_BLON_EN :bit1; + DC_GPIO_VARY_BL_GENERICA_EN:bit1; + RESERVED0 :bit6; + DC_GPIO_DIGON_EN :bit1; + RESERVED1 :bit7; + DC_GPIO_ENA_BL_EN :bit1; + RESERVED2 :bit7; + DC_GPIO_VSYNC_IN_EN :bit1; + RESERVED3 :bit6; + DC_GPIO_HSYNC_IN_EN :bit1; + end; + + TDC_GPU_TIMER_READ=bit32; + + TDC_HPD_INT_STATUS=bitpacked record + DC_HPD_INT_STATUS :bit1; + DC_HPD_SENSE :bit1; + RESERVED0 :bit2; + DC_HPD_SENSE_DELAYED :bit1; + RESERVED1 :bit3; + DC_HPD_RX_INT_STATUS :bit1; + RESERVED2 :bit3; + DC_HPD_TOGGLE_FILT_CON_TIMER_VAL :bit8; + RESERVED3 :bit4; + DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL:bit8; + end; + + TDC_I2C_DDC1_SETUP=bitpacked record + DC_I2C_DDC1_DATA_DRIVE_EN :bit1; + DC_I2C_DDC1_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC1_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC1_EDID_DETECT_MODE :bit1; + DC_I2C_DDC1_ENABLE :bit1; + DC_I2C_DDC1_CLK_DRIVE_EN :bit1; + DC_I2C_DDC1_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC1_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC1_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC1_SPEED=bitpacked record + DC_I2C_DDC1_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC1_PRESCALE :bit16; + end; + + TDC_I2C_DDC2_SETUP=bitpacked record + DC_I2C_DDC2_DATA_DRIVE_EN :bit1; + DC_I2C_DDC2_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC2_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC2_EDID_DETECT_MODE :bit1; + DC_I2C_DDC2_ENABLE :bit1; + DC_I2C_DDC2_CLK_DRIVE_EN :bit1; + DC_I2C_DDC2_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC2_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC2_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC2_SPEED=bitpacked record + DC_I2C_DDC2_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC2_PRESCALE :bit16; + end; + + TDC_I2C_DDC3_SETUP=bitpacked record + DC_I2C_DDC3_DATA_DRIVE_EN :bit1; + DC_I2C_DDC3_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC3_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC3_EDID_DETECT_MODE :bit1; + DC_I2C_DDC3_ENABLE :bit1; + DC_I2C_DDC3_CLK_DRIVE_EN :bit1; + DC_I2C_DDC3_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC3_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC3_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC3_SPEED=bitpacked record + DC_I2C_DDC3_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC3_PRESCALE :bit16; + end; + + TDC_I2C_DDC4_SETUP=bitpacked record + DC_I2C_DDC4_DATA_DRIVE_EN :bit1; + DC_I2C_DDC4_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC4_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC4_EDID_DETECT_MODE :bit1; + DC_I2C_DDC4_ENABLE :bit1; + DC_I2C_DDC4_CLK_DRIVE_EN :bit1; + DC_I2C_DDC4_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC4_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC4_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC4_SPEED=bitpacked record + DC_I2C_DDC4_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC4_PRESCALE :bit16; + end; + + TDC_I2C_DDC5_SETUP=bitpacked record + DC_I2C_DDC5_DATA_DRIVE_EN :bit1; + DC_I2C_DDC5_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC5_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC5_EDID_DETECT_MODE :bit1; + DC_I2C_DDC5_ENABLE :bit1; + DC_I2C_DDC5_CLK_DRIVE_EN :bit1; + DC_I2C_DDC5_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC5_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC5_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC5_SPEED=bitpacked record + DC_I2C_DDC5_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC5_PRESCALE :bit16; + end; + + TDC_I2C_DDC6_SETUP=bitpacked record + DC_I2C_DDC6_DATA_DRIVE_EN :bit1; + DC_I2C_DDC6_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDC6_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDC6_EDID_DETECT_MODE :bit1; + DC_I2C_DDC6_ENABLE :bit1; + DC_I2C_DDC6_CLK_DRIVE_EN :bit1; + DC_I2C_DDC6_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDC6_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDC6_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDC6_SPEED=bitpacked record + DC_I2C_DDC6_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDC6_PRESCALE :bit16; + end; + + TDC_MVP_LB_CONTROL=bitpacked record + MVP_SWAP_LOCK_IN_MODE :bit2; + RESERVED0 :bit6; + DC_MVP_SWAP_LOCK_OUT_SEL :bit1; + RESERVED1 :bit3; + DC_MVP_SWAP_LOCK_OUT_FORCE_ONE :bit1; + RESERVED2 :bit3; + DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO:bit1; + RESERVED3 :bit3; + DC_MVP_SWAP_LOCK_STATUS :bit1; + RESERVED4 :bit7; + DC_MVP_SWAP_LOCK_IN_CAP :bit1; + RESERVED5 :bit2; + DC_MVP_SPARE_FLOPS :bit1; + end; + + TDC_PAD_EXTERN_SIG=bitpacked record + DC_PAD_EXTERN_SIG_SEL:bit4; + MVP_PIXEL_SRC_STATUS :bit2; + RESERVED0 :bit26; + end; + + TDIDT_DBR_CTRL_OCP=bitpacked record + UNUSED_0 :bit16; + OCP_MAX_POWER:bit16; + end; + + TDIDT_DB_WEIGHT0_3=bitpacked record + WEIGHT0:bit8; + WEIGHT1:bit8; + WEIGHT2:bit8; + WEIGHT3:bit8; + end; + + TDIDT_DB_WEIGHT4_7=bitpacked record + WEIGHT4:bit8; + WEIGHT5:bit8; + WEIGHT6:bit8; + WEIGHT7:bit8; + end; + + TDIDT_SQ_WEIGHT0_3=bitpacked record + WEIGHT0:bit8; + WEIGHT1:bit8; + WEIGHT2:bit8; + WEIGHT3:bit8; + end; + + TDIDT_SQ_WEIGHT4_7=bitpacked record + WEIGHT4:bit8; + WEIGHT5:bit8; + WEIGHT6:bit8; + WEIGHT7:bit8; + end; + + TDIDT_TCP_CTRL_OCP=bitpacked record + UNUSED_0 :bit16; + OCP_MAX_POWER:bit16; + end; + + TDIDT_TD_WEIGHT0_3=bitpacked record + WEIGHT0:bit8; + WEIGHT1:bit8; + WEIGHT2:bit8; + WEIGHT3:bit8; + end; + + TDIDT_TD_WEIGHT4_7=bitpacked record + WEIGHT4:bit8; + WEIGHT5:bit8; + WEIGHT6:bit8; + WEIGHT7:bit8; + end; + + TDIG_CLOCK_PATTERN=bitpacked record + DIG_CLOCK_PATTERN:bit10; + RESERVED0 :bit22; + end; + + TDMCU_ERAM_RD_CTRL=bitpacked record + ERAM_RD_ADDR :bit16; + ERAM_RD_BE :bit4; + ERAM_RD_BYTE_MODE:bit1; + RESERVED0 :bit11; + end; + + TDMCU_ERAM_RD_DATA=bit32; + + TDMCU_ERAM_WR_CTRL=bitpacked record + ERAM_WR_ADDR :bit16; + ERAM_WR_BE :bit4; + ERAM_WR_BYTE_MODE:bit1; + RESERVED0 :bit11; + end; + + TDMCU_ERAM_WR_DATA=bit32; + + TDMCU_IRAM_RD_CTRL=bitpacked record + IRAM_RD_ADDR:bit10; + RESERVED0 :bit22; + end; + + TDMCU_IRAM_RD_DATA=bitpacked record + IRAM_RD_DATA:bit8; + RESERVED0 :bit24; + end; + + TDMCU_IRAM_WR_CTRL=bitpacked record + IRAM_WR_ADDR:bit10; + RESERVED0 :bit22; + end; + + TDMCU_IRAM_WR_DATA=bitpacked record + IRAM_WR_DATA:bit8; + RESERVED0 :bit24; + end; + + TDMIF_URG_OVERRIDE=bitpacked record + DMIF_URG_OVERRIDE_EN :bit1; + RESERVED0 :bit3; + DMIF_URG_OVERRIDE_LEVEL:bit4; + RESERVED1 :bit24; + end; + + TDP_DPHY_PRBS_CNTL=bitpacked record + DPHY_PRBS_EN :bit1; + RESERVED0 :bit3; + DPHY_PRBS_SEL :bit2; + RESERVED1 :bit2; + DPHY_PRBS_SEED:bit23; + RESERVED2 :bit1; + end; + + TDP_MSE_SAT_UPDATE=bitpacked record + DP_MSE_SAT_UPDATE :bit2; + RESERVED0 :bit6; + DP_MSE_16_MTP_KEEPOUT:bit1; + RESERVED1 :bit23; + end; + + TDVOACLKC_MVP_CNTL=bitpacked record + DVOACLKC_MVP_FINE_SKEW_CNTL :bit3; + RESERVED0 :bit5; + DVOACLKC_MVP_COARSE_SKEW_CNTL :bit5; + RESERVED1 :bit3; + DVOACLKC_MVP_FINE_ADJUST_EN :bit1; + DVOACLKC_MVP_COARSE_ADJUST_EN :bit1; + DVOACLKC_MVP_IN_PHASE :bit1; + RESERVED2 :bit1; + DVOACLKC_MVP_SKEW_PHASE_OVERRIDE:bit1; + RESERVED3 :bit3; + MVP_CLK_A_SRC_SEL :bit2; + RESERVED4 :bit2; + MVP_CLK_B_SRC_SEL :bit2; + RESERVED5 :bit2; + end; + + TDVO_CRC2_SIG_MASK=bitpacked record + DVO_CRC2_SIG_MASK:bit27; + RESERVED0 :bit5; + end; + + TDVO_SOURCE_SELECT=bitpacked record + DVO_SOURCE_SELECT :bit3; + RESERVED0 :bit13; + DVO_STEREOSYNC_SELECT:bit3; + RESERVED1 :bit13; + end; + + TGARLIC_FLUSH_CNTL=bitpacked record + CP_RB0_WPTR :bit1; + CP_RB1_WPTR :bit1; + CP_RB2_WPTR :bit1; + UVD_RBC_RB_WPTR :bit1; + SDMA0_GFX_RB_WPTR :bit1; + SDMA1_GFX_RB_WPTR :bit1; + CP_DMA_ME_COMMAND :bit1; + CP_DMA_PFP_COMMAND:bit1; + SAM_SAB_RBI_WPTR :bit1; + SAM_SAB_RBO_WPTR :bit1; + VCE_OUT_RB_WPTR :bit1; + VCE_RB_WPTR2 :bit1; + VCE_RB_WPTR :bit1; + HOST_DOORBELL :bit1; + SELFRING_DOORBELL :bit1; + CP_DMA_PIO_COMMAND:bit1; + DISPLAY :bit1; + SDMA2_GFX_RB_WPTR :bit1; + SDMA3_GFX_RB_WPTR :bit1; + RESERVED0 :bit11; + IGNORE_MC_DISABLE :bit1; + DISABLE_ALL :bit1; + end; + + TGCK_PLL_TEST_CNTL=bitpacked record + TST_SRC_SEL :bit5; + TST_REF_SEL :bit5; + REF_TEST_COUNT :bit7; + TST_RESET :bit1; + TST_CLK_SEL_MODE:bit1; + RESERVED0 :bit13; + end; + + TGCK_SMC_IND_INDEX=bit32; + TGDS_ATOM_COMPLETE=bitpacked record COMPLETE:bit1; UNUSED :bit31; @@ -6159,6 +26249,82 @@ type TGDS_WR_BURST_DATA=bit32; + TGENERIC_I2C_SETUP=bitpacked record + GENERIC_I2C_DATA_DRIVE_EN :bit1; + GENERIC_I2C_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit5; + GENERIC_I2C_CLK_DRIVE_EN :bit1; + GENERIC_I2C_INTRA_BYTE_DELAY:bit8; + RESERVED1 :bit8; + GENERIC_I2C_TIME_LIMIT :bit8; + end; + + TGENERIC_I2C_SPEED=bitpacked record + GENERIC_I2C_THRESHOLD :bit2; + RESERVED0 :bit2; + GENERIC_I2C_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + GENERIC_I2C_PRESCALE :bit16; + end; + + TGFX_PIPE_PRIORITY=bitpacked record + HP_PIPE_SELECT:bit1; + RESERVED0 :bit31; + end; + + TGMCON_PGFSM_WRITE=bit32; + + TGPIOPAD_PINSTRAPS=bitpacked record + GPIO_PINSTRAP_0 :bit1; + GPIO_PINSTRAP_1 :bit1; + GPIO_PINSTRAP_2 :bit1; + GPIO_PINSTRAP_3 :bit1; + GPIO_PINSTRAP_4 :bit1; + GPIO_PINSTRAP_5 :bit1; + GPIO_PINSTRAP_6 :bit1; + GPIO_PINSTRAP_7 :bit1; + GPIO_PINSTRAP_8 :bit1; + GPIO_PINSTRAP_9 :bit1; + GPIO_PINSTRAP_10:bit1; + GPIO_PINSTRAP_11:bit1; + GPIO_PINSTRAP_12:bit1; + GPIO_PINSTRAP_13:bit1; + GPIO_PINSTRAP_14:bit1; + GPIO_PINSTRAP_15:bit1; + GPIO_PINSTRAP_16:bit1; + GPIO_PINSTRAP_17:bit1; + GPIO_PINSTRAP_18:bit1; + GPIO_PINSTRAP_19:bit1; + GPIO_PINSTRAP_20:bit1; + GPIO_PINSTRAP_21:bit1; + GPIO_PINSTRAP_22:bit1; + GPIO_PINSTRAP_23:bit1; + GPIO_PINSTRAP_24:bit1; + GPIO_PINSTRAP_25:bit1; + GPIO_PINSTRAP_26:bit1; + GPIO_PINSTRAP_27:bit1; + GPIO_PINSTRAP_28:bit1; + GPIO_PINSTRAP_29:bit1; + GPIO_PINSTRAP_30:bit1; + RESERVED0 :bit1; + end; + + TGPU_HDP_FLUSH_REQ=bitpacked record + CP0 :bit1; + CP1 :bit1; + CP2 :bit1; + CP3 :bit1; + CP4 :bit1; + CP5 :bit1; + CP6 :bit1; + CP7 :bit1; + CP8 :bit1; + CP9 :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + RESERVED0:bit20; + end; + TGRBM_HYP_CAM_DATA=bitpacked record CAM_ADDR :bit16; CAM_REMAPADDR:bit16; @@ -6180,6 +26346,1349 @@ type TGRBM_SCRATCH_REG7=bit32; + TGRPH_FLIP_CONTROL=bitpacked record + GRPH_SURFACE_UPDATE_H_RETRACE_EN:bit1; + GRPH_XDMA_SUPER_AA_EN :bit1; + RESERVED0 :bit30; + end; + + THDMI_ACR_STATUS_0=bitpacked record + RESERVED0 :bit12; + HDMI_ACR_CTS:bit20; + end; + + THDMI_ACR_STATUS_1=bitpacked record + HDMI_ACR_N:bit20; + RESERVED0 :bit12; + end; + + THDP_MEMIO_RD_DATA=bit32; + + THDP_MEMIO_WR_DATA=bit32; + + THDP_NONSURF_FLAGS=bitpacked record + NONSURF_WRITE_FLAG:bit1; + NONSURF_READ_FLAG :bit1; + RESERVED0 :bit30; + end; + + THDP_TILING_CONFIG=bitpacked record + RESERVED0 :bit1; + PIPE_TILING :bit3; + BANK_TILING :bit2; + GROUP_SIZE :bit2; + ROW_TILING :bit3; + BANK_SWAPS :bit3; + SAMPLE_SPLIT:bit2; + RESERVED1 :bit16; + end; + + THDP_XDP_D2H_FLUSH=bitpacked record + D2H_FLUSH_FLUSH_NUM :bit4; + D2H_FLUSH_MBX_ENC_DATA :bit4; + D2H_FLUSH_MBX_ADDR_SEL :bit3; + D2H_FLUSH_XPB_CLG :bit5; + D2H_FLUSH_SEND_HOST :bit1; + D2H_FLUSH_SEND_SIDE :bit1; + D2H_FLUSH_ALTER_FLUSH_NUM:bit1; + D2H_FLUSH_RSVD_0 :bit1; + D2H_FLUSH_RSVD_1 :bit1; + RESERVED0 :bit11; + end; + + TIH_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TINPUT_CSC_C11_C12=bitpacked record + INPUT_CSC_C11:bit16; + INPUT_CSC_C12:bit16; + end; + + TINPUT_CSC_C13_C14=bitpacked record + INPUT_CSC_C13:bit16; + INPUT_CSC_C14:bit16; + end; + + TINPUT_CSC_C21_C22=bitpacked record + INPUT_CSC_C21:bit16; + INPUT_CSC_C22:bit16; + end; + + TINPUT_CSC_C23_C24=bitpacked record + INPUT_CSC_C23:bit16; + INPUT_CSC_C24:bit16; + end; + + TINPUT_CSC_C31_C32=bitpacked record + INPUT_CSC_C31:bit16; + INPUT_CSC_C32:bit16; + end; + + TINPUT_CSC_C33_C34=bitpacked record + INPUT_CSC_C33:bit16; + INPUT_CSC_C34:bit16; + end; + + TINPUT_CSC_CONTROL=bitpacked record + INPUT_CSC_GRPH_MODE:bit2; + RESERVED0 :bit2; + INPUT_CSC_OVL_MODE :bit2; + RESERVED1 :bit26; + end; + + TINTERRUPT_CONTROL=bitpacked record + STREAM_0_INTERRUPT_ENABLE :bit1; + STREAM_1_INTERRUPT_ENABLE :bit1; + STREAM_2_INTERRUPT_ENABLE :bit1; + STREAM_3_INTERRUPT_ENABLE :bit1; + STREAM_4_INTERRUPT_ENABLE :bit1; + STREAM_5_INTERRUPT_ENABLE :bit1; + STREAM_6_INTERRUPT_ENABLE :bit1; + STREAM_7_INTERRUPT_ENABLE :bit1; + STREAM_8_INTERRUPT_ENABLE :bit1; + STREAM_9_INTERRUPT_ENABLE :bit1; + STREAM_10_INTERRUPT_ENABLE :bit1; + STREAM_11_INTERRUPT_ENABLE :bit1; + STREAM_12_INTERRUPT_ENABLE :bit1; + STREAM_13_INTERRUPT_ENABLE :bit1; + STREAM_14_INTERRUPT_ENABLE :bit1; + STREAM_15_INTERRUPT_ENABLE :bit1; + RESERVED0 :bit14; + CONTROLLER_INTERRUPT_ENABLE:bit1; + GLOBAL_INTERRUPT_ENABLE :bit1; + end; + + TLBV_BUFFER_STATUS=bitpacked record + LB_BUFFER_EMPTY_MARGIN :bit4; + LB_BUFFER_EMPTY_STAT :bit1; + RESERVED0 :bit3; + LB_BUFFER_EMPTY_OCCURRED:bit1; + RESERVED1 :bit3; + LB_BUFFER_EMPTY_ACK :bit1; + RESERVED2 :bit3; + LB_BUFFER_FULL_STAT :bit1; + RESERVED3 :bit3; + LB_BUFFER_FULL_OCCURRED :bit1; + RESERVED4 :bit3; + LB_BUFFER_FULL_ACK :bit1; + RESERVED5 :bit7; + end; + + TLBV_VBLANK_STATUS=bitpacked record + VBLANK_OCCURRED :bit1; + RESERVED0 :bit3; + VBLANK_ACK :bit1; + RESERVED1 :bit7; + VBLANK_STAT :bit1; + RESERVED2 :bit3; + VBLANK_INTERRUPT :bit1; + VBLANK_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLBV_VLINE2_STATUS=bitpacked record + VLINE2_OCCURRED :bit1; + RESERVED0 :bit3; + VLINE2_ACK :bit1; + RESERVED1 :bit7; + VLINE2_STAT :bit1; + RESERVED2 :bit3; + VLINE2_INTERRUPT :bit1; + VLINE2_INTERRUPT_TYPE:bit1; + RESERVED3 :bit14; + end; + + TLB_DESKTOP_HEIGHT=bitpacked record + DESKTOP_HEIGHT:bit15; + RESERVED0 :bit17; + end; + + TLB_INTERRUPT_MASK=bitpacked record + VBLANK_INTERRUPT_MASK:bit1; + RESERVED0 :bit3; + VLINE_INTERRUPT_MASK :bit1; + RESERVED1 :bit3; + VLINE2_INTERRUPT_MASK:bit1; + RESERVED2 :bit23; + end; + + TLB_SYNC_RESET_SEL=bitpacked record + LB_SYNC_RESET_SEL :bit2; + RESERVED0 :bit2; + LB_SYNC_RESET_SEL2 :bit1; + RESERVED1 :bit3; + LB_SYNC_RESET_DELAY:bit8; + RESERVED2 :bit6; + LB_SYNC_DURATION :bit2; + RESERVED3 :bit8; + end; + + TLVTMA_PWRSEQ_CNTL=bitpacked record + LVTMA_PWRSEQ_EN :bit1; + LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + LVTMA_PWRSEQ_TARGET_STATE :bit1; + RESERVED2 :bit1; + RESERVED3 :bit2; + LVTMA_SYNCEN :bit1; + LVTMA_SYNCEN_OVRD :bit1; + LVTMA_SYNCEN_POL :bit1; + RESERVED4 :bit5; + LVTMA_DIGON :bit1; + LVTMA_DIGON_OVRD :bit1; + LVTMA_DIGON_POL :bit1; + RESERVED5 :bit5; + LVTMA_BLON :bit1; + LVTMA_BLON_OVRD :bit1; + LVTMA_BLON_POL :bit1; + RESERVED6 :bit5; + end; + + TMCIF_WB_BUF_PITCH=bitpacked record + RESERVED0 :bit8; + MCIF_WB_BUF_LUMA_PITCH :bit8; + RESERVED1 :bit8; + MCIF_WB_BUF_CHROMA_PITCH:bit8; + end; + + TMC_ARB_ADDR_SWIZ0=bitpacked record + A8 :bit4; + A9 :bit4; + A10:bit4; + A11:bit4; + A12:bit4; + A13:bit4; + A14:bit4; + A15:bit4; + end; + + TMC_ARB_ADDR_SWIZ1=bitpacked record + A16 :bit4; + A17 :bit4; + A18 :bit4; + A19 :bit4; + RESERVED0:bit16; + end; + + TMC_ARB_BURST_TIME=bitpacked record + STATE0 :bit5; + STATE1 :bit5; + STATE2 :bit5; + STATE3 :bit5; + RESERVED0:bit12; + end; + + TMC_ARB_GECC2_MISC=bitpacked record + STREAK_BREAK :bit4; + COL10_HACK :bit1; + CWRD_IN_REPLAY :bit1; + NO_EOB_ALL_WR_IN_REPLAY :bit1; + RMW_LM_WR_STALL :bit1; + RMW_STALL_RELEASE :bit1; + WR_EDC_MASK_REPLAY :bit1; + CWRD_REPLAY_AGAIN :bit1; + WRRDWR_REPLAY_AGAIN :bit1; + ALLOW_RMW_ERR_AFTER_REPLAY:bit1; + DEBUG_RSV :bit19; + end; + + TMC_ARB_TM_CNTL_RD=bitpacked record + GROUPBY_RANK:bit1; + BANK_SELECT :bit2; + MATCH_RANK :bit1; + MATCH_BANK :bit1; + RESERVED0 :bit27; + end; + + TMC_ARB_TM_CNTL_WR=bitpacked record + GROUPBY_RANK:bit1; + BANK_SELECT :bit2; + MATCH_RANK :bit1; + MATCH_BANK :bit1; + RESERVED0 :bit27; + end; + + TMC_CITF_DAGB_CNTL=bitpacked record + JUMP_AHEAD :bit1; + CENTER_RD_MAX_BURST:bit4; + DISABLE_SELF_INIT :bit1; + CENTER_WR_MAX_BURST:bit4; + RESERVED0 :bit22; + end; + + TMC_GRUB_PROBE_MAP=bitpacked record + ADDR0_TO_TC_MAP :bit2; + ADDR1_TO_TC_MAP :bit2; + ADDR2_TO_TC_MAP :bit2; + ADDR3_TO_TC_MAP :bit2; + ADDR0_TO_GRUB_MAP:bit1; + ADDR1_TO_GRUB_MAP:bit1; + ADDR2_TO_GRUB_MAP:bit1; + ADDR3_TO_GRUB_MAP:bit1; + RESERVED0 :bit20; + end; + + TMC_GRUB_TCB_INDEX=bitpacked record + INDEX :bit7; + RESERVED0 :bit1; + TCB0_WR_EN:bit1; + TCB1_WR_EN:bit1; + RD_EN :bit1; + TCB_SEL :bit1; + RESERVED1 :bit20; + end; + + TMC_HUB_MISC_POWER=bitpacked record + RESERVED0 :bit2; + SRBM_GATE_OVERRIDE:bit1; + PM_BLACKOUT_CNTL :bit2; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit25; + end; + + TMC_HUB_MISC_VM_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_HUB_RDREQ_ACPG=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_RDREQ_ACPO=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_RDREQ_CNTL=bitpacked record + REMOTE_BLACKOUT :bit1; + RESERVED0 :bit1; + JUMPAHEAD_GBL0 :bit1; + JUMPAHEAD_GBL1 :bit1; + OVERRIDE_STALL_ENABLE :bit1; + MCDW_STALL_MODE :bit1; + MCDX_STALL_MODE :bit1; + MCDY_STALL_MODE :bit1; + MCDZ_STALL_MODE :bit1; + MCDS_STALL_MODE :bit1; + MCDT_STALL_MODE :bit1; + MCDU_STALL_MODE :bit1; + MCDV_STALL_MODE :bit1; + BREAK_HDP_DEADLOCK :bit1; + DEBUG_REG :bit7; + DISABLE_SELF_INIT_GBL0 :bit1; + DISABLE_SELF_INIT_GBL1 :bit1; + PWRXPRESS_MODE :bit1; + ACPG_HP_TO_MCD_OVERRIDE:bit1; + GBL0_PRI_ENABLE :bit1; + UVD_TRANSCODE_ENABLE :bit1; + DMIF_URG_THRESHOLD :bit4; + RESERVED1 :bit1; + end; + + TMC_HUB_RDREQ_DMIF=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_GBL0=bitpacked record + STALL_THRESHOLD :bit8; + STALL_THRESHOLD_PRI:bit8; + RESERVED0 :bit16; + end; + + TMC_HUB_RDREQ_GBL1=bitpacked record + STALL_THRESHOLD :bit8; + STALL_THRESHOLD_PRI:bit8; + RESERVED0 :bit16; + end; + + TMC_HUB_RDREQ_MCDS=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + STALL_THRESHOLD:bit7; + end; + + TMC_HUB_RDREQ_MCDT=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + STALL_THRESHOLD:bit7; + end; + + TMC_HUB_RDREQ_MCDU=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + STALL_THRESHOLD:bit7; + end; + + TMC_HUB_RDREQ_MCDV=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + STALL_THRESHOLD:bit7; + end; + + TMC_HUB_RDREQ_MCDW=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + MED_CREDITS :bit7; + end; + + TMC_HUB_RDREQ_MCDX=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + MED_CREDITS :bit7; + end; + + TMC_HUB_RDREQ_MCDY=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + MED_CREDITS :bit7; + end; + + TMC_HUB_RDREQ_MCDZ=bitpacked record + ENABLE :bit1; + BLACKOUT_EXEMPT:bit1; + BUS :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + ASK_CREDITS :bit7; + DISPLAY_CREDITS:bit7; + MED_CREDITS :bit7; + end; + + TMC_HUB_RDREQ_MCIF=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_VCE0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_RDREQ_VCE1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + VM_BYPASS :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_RDREQ_VP8U=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_WDP_SAMMSP=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE :bit1; + URG_BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit14; + end; + + TMC_HUB_WDP_STATUS=bitpacked record + SIP_AVAIL :bit1; + MCDW_RD_AVAIL :bit1; + MCDX_RD_AVAIL :bit1; + MCDY_RD_AVAIL :bit1; + MCDZ_RD_AVAIL :bit1; + MCDS_RD_AVAIL :bit1; + MCDT_RD_AVAIL :bit1; + MCDU_RD_AVAIL :bit1; + MCDV_RD_AVAIL :bit1; + MCDW_WR_AVAIL :bit1; + MCDX_WR_AVAIL :bit1; + MCDY_WR_AVAIL :bit1; + MCDZ_WR_AVAIL :bit1; + MCDS_WR_AVAIL :bit1; + MCDT_WR_AVAIL :bit1; + MCDU_WR_AVAIL :bit1; + MCDV_WR_AVAIL :bit1; + GBL0_VM_FULL :bit1; + GBL0_STOR_FULL :bit1; + GBL0_BYPASS_STOR_FULL:bit1; + GBL1_VM_FULL :bit1; + GBL1_STOR_FULL :bit1; + GBL1_BYPASS_STOR_FULL:bit1; + RESERVED0 :bit9; + end; + + TMC_HUB_WRRET_CNTL=bitpacked record + JUMPAHEAD :bit1; + BP :bit20; + BP_ENABLE :bit1; + DEBUG_REG :bit8; + DISABLE_SELF_INIT:bit1; + FAIR_CH_SW :bit1; + end; + + TMC_HUB_WRRET_MCDS=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDT=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDU=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDV=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDW=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDX=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDY=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_HUB_WRRET_MCDZ=bitpacked record + STALL_MODE :bit1; + CREDIT_COUNT:bit7; + RESERVED0 :bit24; + end; + + TMC_IO_DEBUG_UP_10=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_11=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_12=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_13=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_14=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_15=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_16=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_17=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_18=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_19=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_20=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_21=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_22=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_23=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_24=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_25=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_26=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_27=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_28=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_29=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_30=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_31=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_32=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_33=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_34=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_35=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_36=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_37=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_38=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_39=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_40=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_41=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_42=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_43=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_44=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_45=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_46=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_47=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_48=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_49=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_50=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_51=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_52=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_53=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_54=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_55=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_56=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_57=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_58=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_59=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_60=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_61=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_62=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_63=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_64=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_65=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_66=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_67=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_68=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_69=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_70=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_71=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_72=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_73=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_74=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_75=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_76=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_77=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_78=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_79=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_80=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_81=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_82=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_83=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_84=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_85=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_86=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_87=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_88=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_89=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_90=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_91=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_92=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_93=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_94=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_95=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_96=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_97=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_98=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_99=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_SEQ_CAS_TIMING=bitpacked record + TNOPW :bit2; + TNOPR :bit2; + TR2W :bit5; + TCCDL :bit3; + TR2R :bit4; + TW2R :bit5; + TCL :bit5; + RESERVED0:bit6; + end; + + TMC_SEQ_IO_RESERVE=bit32; + + TMC_SEQ_PMG_TIMING=bitpacked record + TCKSRE :bit3; + TCKSRX :bit3; + TCKE_PULSE :bit5; + TCKE :bit8; + SEQ_IDLE :bit3; + SEQ_IDLE_SS:bit8; + RESERVED0 :bit2; + end; + + TMC_SEQ_RAS_TIMING=bitpacked record + TRCDW :bit5; + TRCDWA :bit5; + TRCDR :bit5; + TRCDRA :bit5; + TRRD :bit4; + TRC :bit7; + RESERVED0:bit1; + end; + + TMC_SHARED_CHREMAP=bitpacked record + CHAN0:bit4; + CHAN1:bit4; + CHAN2:bit4; + CHAN3:bit4; + CHAN4:bit4; + CHAN5:bit4; + CHAN6:bit4; + CHAN7:bit4; + end; + + TMC_VM_FB_LOCATION=bitpacked record + FB_BASE:bit16; + FB_TOP :bit16; + end; + + TMC_VM_NB_MMIOBASE=bit32; + + TMC_VM_NB_PCI_CTRL=bitpacked record + RESERVED0 :bit23; + MMIOENABLE:bit1; + RESERVED1 :bit8; + end; + + TMC_XPB_PERF_KNOBS=bitpacked record + CNS_FIFO_DEPTH :bit6; + WCB_HST_FIFO_DEPTH:bit6; + WCB_SID_FIFO_DEPTH:bit6; + RESERVED0 :bit14; + end; + + TMC_XPB_STICKY_W1C=bit32; + + TMVP_AFR_FLIP_MODE=bitpacked record + MVP_AFR_FLIP_MODE:bit2; + RESERVED0 :bit30; + end; + + TOUT_ROUND_CONTROL=bitpacked record + OUT_ROUND_TRUNC_MODE:bit4; + RESERVED0 :bit28; + end; + TPA_CL_CNTL_STATUS=bitpacked record RESERVED0:bit31; CL_BUSY :bit1; @@ -6287,6 +27796,913 @@ type SU_BUSY :bit1; end; + TPB0_GLB_CTRL_REG0=bitpacked record + BACKUP :bit16; + CFG_IDLEDET_TH :bit2; + RESERVED0 :bit2; + DBG_RX2TXBYP_SEL :bit3; + DBG_RXFEBYP_EN :bit1; + DBG_RXPRBS_CLR :bit1; + DBG_RXTOGGLE_EN :bit1; + DBG_TX2RXLBACK_EN :bit1; + RESERVED1 :bit3; + TXCFG_CMGOOD_RANGE:bit2; + end; + + TPB0_GLB_CTRL_REG1=bitpacked record + RXDBG_CDR_FR_BYP_EN :bit1; + RXDBG_CDR_FR_BYP_VAL:bit6; + RXDBG_CDR_PH_BYP_EN :bit1; + RXDBG_CDR_PH_BYP_VAL:bit6; + RXDBG_D0TH_BYP_EN :bit1; + RXDBG_D0TH_BYP_VAL :bit7; + RXDBG_D1TH_BYP_EN :bit1; + RXDBG_D1TH_BYP_VAL :bit7; + TST_LOSPDTST_EN :bit1; + PLL_CFG_DISPCLK_DIV :bit1; + end; + + TPB0_GLB_CTRL_REG2=bitpacked record + RXDBG_D2TH_BYP_EN :bit1; + RXDBG_D2TH_BYP_VAL:bit7; + RXDBG_D3TH_BYP_EN :bit1; + RXDBG_D3TH_BYP_VAL:bit7; + RXDBG_DXTH_BYP_EN :bit1; + RXDBG_DXTH_BYP_VAL:bit7; + RXDBG_ETH_BYP_EN :bit1; + RXDBG_ETH_BYP_VAL :bit7; + end; + + TPB0_GLB_CTRL_REG3=bitpacked record + RXDBG_SEL :bit5; + BG_CFG_LC_REG_VREF0_SEL :bit2; + BG_CFG_LC_REG_VREF1_SEL :bit2; + BG_CFG_RO_REG_VREF_SEL :bit2; + BG_DBG_VREFBYP_EN :bit1; + BG_DBG_IREFBYP_EN :bit1; + RESERVED0 :bit1; + BG_DBG_ANALOG_SEL :bit3; + RESERVED1 :bit1; + DBG_DLL_CLK_SEL :bit3; + PLL_DISPCLK_CMOS_SEL :bit1; + DBG_RXPI_OFFSET_BYP_EN :bit1; + DBG_RXPI_OFFSET_BYP_VAL :bit4; + DBG_RXSWAPDX_BYP_EN :bit1; + DBG_RXSWAPDX_BYP_VAL :bit3; + DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE:bit1; + end; + + TPB0_GLB_CTRL_REG4=bitpacked record + DBG_RXAPU_INST :bit16; + DBG_RXDFEMUX_BYP_VAL :bit2; + DBG_RXDFEMUX_BYP_EN :bit1; + RESERVED0 :bit3; + DBG_RXAPU_EXEC :bit4; + DBG_RXDLL_VREG_REF_SEL :bit1; + PWRGOOD_OVRD :bit1; + DBG_RXRDATA_GATING_DISABLE:bit1; + RESERVED1 :bit3; + end; + + TPB0_GLB_CTRL_REG5=bitpacked record + DBG_RXAPU_MODE:bit8; + RESERVED0 :bit24; + end; + + TPB0_GLB_OVRD_REG0=bitpacked record + TXPDTERM_VAL_OVRD_VAL:bit16; + TXPUTERM_VAL_OVRD_VAL:bit16; + end; + + TPB0_GLB_OVRD_REG1=bitpacked record + TXPDTERM_VAL_OVRD_EN :bit1; + TXPUTERM_VAL_OVRD_EN :bit1; + TST_LOSPDTST_RST_OVRD_EN :bit1; + TST_LOSPDTST_RST_OVRD_VAL:bit1; + RESERVED0 :bit11; + RXTERM_VAL_OVRD_EN :bit1; + RXTERM_VAL_OVRD_VAL :bit16; + end; + + TPB0_GLB_OVRD_REG2=bitpacked record + BG_PWRON_OVRD_EN :bit1; + BG_PWRON_OVRD_VAL :bit1; + PLL_DBG_LC_EXT_RESET_OVRD_EN :bit1; + PLL_DBG_LC_EXT_RESET_OVRD_VAL:bit1; + PLL_DBG_RO_EXT_RESET_OVRD_EN :bit1; + PLL_DBG_RO_EXT_RESET_OVRD_VAL:bit1; + RESERVED0 :bit26; + end; + + TPB0_PIF_GLB_OVRD2=bitpacked record + X2_LANE_1_0_OVRD :bit1; + X2_LANE_3_2_OVRD :bit1; + X2_LANE_5_4_OVRD :bit1; + X2_LANE_7_6_OVRD :bit1; + X2_LANE_9_8_OVRD :bit1; + X2_LANE_11_10_OVRD:bit1; + X2_LANE_13_12_OVRD:bit1; + X2_LANE_15_14_OVRD:bit1; + X4_LANE_3_0_OVRD :bit1; + X4_LANE_7_4_OVRD :bit1; + X4_LANE_11_8_OVRD :bit1; + X4_LANE_15_12_OVRD:bit1; + RESERVED0 :bit4; + X8_LANE_7_0_OVRD :bit1; + X8_LANE_15_8_OVRD :bit1; + RESERVED1 :bit2; + X16_LANE_15_0_OVRD:bit1; + RESERVED2 :bit11; + end; + + TPB0_STRAP_RX_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_RX_CFG_TH_LOOP_GAIN :bit4; + STRAP_RX_CFG_DLL_FLOCK_DISABLE :bit1; + STRAP_DBG_RXPI_OFFSET_BYP_EN :bit1; + STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS:bit1; + STRAP_BG_CFG_LC_REG_VREF0_SEL :bit2; + STRAP_BG_CFG_LC_REG_VREF1_SEL :bit2; + STRAP_RX_CFG_CDR_TIME :bit4; + STRAP_RX_CFG_FOM_TIME :bit4; + STRAP_RX_CFG_LEQ_TIME :bit4; + STRAP_RX_CFG_OC_TIME :bit4; + STRAP_TX_CFG_RPTR_RST_VAL :bit3; + STRAP_RX_CFG_TERM_MODE :bit1; + end; + + TPB0_STRAP_RX_REG1=bitpacked record + RESERVED0 :bit1; + STRAP_RX_CFG_CDR_PI_STPSZ :bit1; + STRAP_TX_DEEMPH_PRSHT_STNG :bit3; + STRAP_BG_CFG_RO_REG_VREF_SEL :bit2; + STRAP_RX_CFG_LEQ_POLE_BYP_DIS:bit1; + STRAP_RX_CFG_LEQ_POLE_BYP_VAL:bit3; + STRAP_RX_CFG_CDR_PH_GAIN :bit4; + STRAP_RX_CFG_ADAPT_MODE :bit10; + STRAP_RX_CFG_DFE_TIME :bit4; + STRAP_RX_CFG_LEQ_LOOP_GAIN :bit2; + STRAP_RX_CFG_LEQ_SHUNT_DIS :bit1; + end; + + TPB0_STRAP_TX_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_CFG_DRV0_EN :bit4; + STRAP_TX_CFG_DRV0_TAP_SEL :bit4; + STRAP_TX_CFG_DRV1_EN :bit5; + STRAP_TX_CFG_DRV1_TAP_SEL :bit5; + STRAP_TX_CFG_DRV2_EN :bit4; + STRAP_TX_CFG_DRV2_TAP_SEL :bit4; + STRAP_TX_CFG_DRVX_EN :bit1; + STRAP_TX_CFG_DRVX_TAP_SEL :bit1; + STRAP_RX_TRK_MODE_1_ :bit1; + STRAP_TX_CFG_SWING_BOOST_EN:bit1; + RESERVED1 :bit1; + end; + + TPB1_GLB_CTRL_REG0=bitpacked record + BACKUP :bit16; + CFG_IDLEDET_TH :bit2; + RESERVED0 :bit2; + DBG_RX2TXBYP_SEL :bit3; + DBG_RXFEBYP_EN :bit1; + DBG_RXPRBS_CLR :bit1; + DBG_RXTOGGLE_EN :bit1; + DBG_TX2RXLBACK_EN :bit1; + RESERVED1 :bit3; + TXCFG_CMGOOD_RANGE:bit2; + end; + + TPB1_GLB_CTRL_REG1=bitpacked record + RXDBG_CDR_FR_BYP_EN :bit1; + RXDBG_CDR_FR_BYP_VAL:bit6; + RXDBG_CDR_PH_BYP_EN :bit1; + RXDBG_CDR_PH_BYP_VAL:bit6; + RXDBG_D0TH_BYP_EN :bit1; + RXDBG_D0TH_BYP_VAL :bit7; + RXDBG_D1TH_BYP_EN :bit1; + RXDBG_D1TH_BYP_VAL :bit7; + TST_LOSPDTST_EN :bit1; + PLL_CFG_DISPCLK_DIV :bit1; + end; + + TPB1_GLB_CTRL_REG2=bitpacked record + RXDBG_D2TH_BYP_EN :bit1; + RXDBG_D2TH_BYP_VAL:bit7; + RXDBG_D3TH_BYP_EN :bit1; + RXDBG_D3TH_BYP_VAL:bit7; + RXDBG_DXTH_BYP_EN :bit1; + RXDBG_DXTH_BYP_VAL:bit7; + RXDBG_ETH_BYP_EN :bit1; + RXDBG_ETH_BYP_VAL :bit7; + end; + + TPB1_GLB_CTRL_REG3=bitpacked record + RXDBG_SEL :bit5; + BG_CFG_LC_REG_VREF0_SEL :bit2; + BG_CFG_LC_REG_VREF1_SEL :bit2; + BG_CFG_RO_REG_VREF_SEL :bit2; + BG_DBG_VREFBYP_EN :bit1; + BG_DBG_IREFBYP_EN :bit1; + RESERVED0 :bit1; + BG_DBG_ANALOG_SEL :bit3; + RESERVED1 :bit1; + DBG_DLL_CLK_SEL :bit3; + PLL_DISPCLK_CMOS_SEL :bit1; + DBG_RXPI_OFFSET_BYP_EN :bit1; + DBG_RXPI_OFFSET_BYP_VAL :bit4; + DBG_RXSWAPDX_BYP_EN :bit1; + DBG_RXSWAPDX_BYP_VAL :bit3; + DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE:bit1; + end; + + TPB1_GLB_CTRL_REG4=bitpacked record + DBG_RXAPU_INST :bit16; + DBG_RXDFEMUX_BYP_VAL :bit2; + DBG_RXDFEMUX_BYP_EN :bit1; + RESERVED0 :bit3; + DBG_RXAPU_EXEC :bit4; + DBG_RXDLL_VREG_REF_SEL :bit1; + PWRGOOD_OVRD :bit1; + DBG_RXRDATA_GATING_DISABLE:bit1; + RESERVED1 :bit3; + end; + + TPB1_GLB_CTRL_REG5=bitpacked record + DBG_RXAPU_MODE:bit8; + RESERVED0 :bit24; + end; + + TPB1_GLB_OVRD_REG0=bitpacked record + TXPDTERM_VAL_OVRD_VAL:bit16; + TXPUTERM_VAL_OVRD_VAL:bit16; + end; + + TPB1_GLB_OVRD_REG1=bitpacked record + TXPDTERM_VAL_OVRD_EN :bit1; + TXPUTERM_VAL_OVRD_EN :bit1; + TST_LOSPDTST_RST_OVRD_EN :bit1; + TST_LOSPDTST_RST_OVRD_VAL:bit1; + RESERVED0 :bit11; + RXTERM_VAL_OVRD_EN :bit1; + RXTERM_VAL_OVRD_VAL :bit16; + end; + + TPB1_GLB_OVRD_REG2=bitpacked record + BG_PWRON_OVRD_EN :bit1; + BG_PWRON_OVRD_VAL :bit1; + PLL_DBG_LC_EXT_RESET_OVRD_EN :bit1; + PLL_DBG_LC_EXT_RESET_OVRD_VAL:bit1; + PLL_DBG_RO_EXT_RESET_OVRD_EN :bit1; + PLL_DBG_RO_EXT_RESET_OVRD_VAL:bit1; + RESERVED0 :bit26; + end; + + TPB1_PIF_GLB_OVRD2=bitpacked record + X2_LANE_1_0_OVRD :bit1; + X2_LANE_3_2_OVRD :bit1; + X2_LANE_5_4_OVRD :bit1; + X2_LANE_7_6_OVRD :bit1; + X2_LANE_9_8_OVRD :bit1; + X2_LANE_11_10_OVRD:bit1; + X2_LANE_13_12_OVRD:bit1; + X2_LANE_15_14_OVRD:bit1; + X4_LANE_3_0_OVRD :bit1; + X4_LANE_7_4_OVRD :bit1; + X4_LANE_11_8_OVRD :bit1; + X4_LANE_15_12_OVRD:bit1; + RESERVED0 :bit4; + X8_LANE_7_0_OVRD :bit1; + X8_LANE_15_8_OVRD :bit1; + RESERVED1 :bit2; + X16_LANE_15_0_OVRD:bit1; + RESERVED2 :bit11; + end; + + TPB1_STRAP_RX_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_RX_CFG_TH_LOOP_GAIN :bit4; + STRAP_RX_CFG_DLL_FLOCK_DISABLE :bit1; + STRAP_DBG_RXPI_OFFSET_BYP_EN :bit1; + STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS:bit1; + STRAP_BG_CFG_LC_REG_VREF0_SEL :bit2; + STRAP_BG_CFG_LC_REG_VREF1_SEL :bit2; + STRAP_RX_CFG_CDR_TIME :bit4; + STRAP_RX_CFG_FOM_TIME :bit4; + STRAP_RX_CFG_LEQ_TIME :bit4; + STRAP_RX_CFG_OC_TIME :bit4; + STRAP_TX_CFG_RPTR_RST_VAL :bit3; + STRAP_RX_CFG_TERM_MODE :bit1; + end; + + TPB1_STRAP_RX_REG1=bitpacked record + RESERVED0 :bit1; + STRAP_RX_CFG_CDR_PI_STPSZ :bit1; + STRAP_TX_DEEMPH_PRSHT_STNG :bit3; + STRAP_BG_CFG_RO_REG_VREF_SEL :bit2; + STRAP_RX_CFG_LEQ_POLE_BYP_DIS:bit1; + STRAP_RX_CFG_LEQ_POLE_BYP_VAL:bit3; + STRAP_RX_CFG_CDR_PH_GAIN :bit4; + STRAP_RX_CFG_ADAPT_MODE :bit10; + STRAP_RX_CFG_DFE_TIME :bit4; + STRAP_RX_CFG_LEQ_LOOP_GAIN :bit2; + STRAP_RX_CFG_LEQ_SHUNT_DIS :bit1; + end; + + TPB1_STRAP_TX_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_CFG_DRV0_EN :bit4; + STRAP_TX_CFG_DRV0_TAP_SEL :bit4; + STRAP_TX_CFG_DRV1_EN :bit5; + STRAP_TX_CFG_DRV1_TAP_SEL :bit5; + STRAP_TX_CFG_DRV2_EN :bit4; + STRAP_TX_CFG_DRV2_TAP_SEL :bit4; + STRAP_TX_CFG_DRVX_EN :bit1; + STRAP_TX_CFG_DRVX_TAP_SEL :bit1; + STRAP_RX_TRK_MODE_1_ :bit1; + STRAP_TX_CFG_SWING_BOOST_EN:bit1; + RESERVED1 :bit1; + end; + + TPCIE_I2C_REG_DATA=bit32; + + TPCIE_LC_LANE_CNTL=bitpacked record + LC_CORRUPTED_LANES:bit16; + LC_LANE_DIS :bit16; + end; + + TPCIE_PORT_VC_CNTL=bitpacked record + LOAD_VC_ARB_TABLE:bit1; + VC_ARB_SELECT :bit3; + RESERVED0 :bit28; + end; + + TPCIE_PRBS_FREERUN=bitpacked record + PRBS_FREERUN:bit16; + RESERVED0 :bit16; + end; + + TPCIE_PRBS_STATUS1=bitpacked record + PRBS_ERRSTAT:bit16; + PRBS_LOCKED :bit16; + end; + + TPCIE_PRBS_STATUS2=bitpacked record + PRBS_BITCNT_DONE:bit16; + RESERVED0 :bit16; + end; + + TPCIE_P_BUF_STATUS=bitpacked record + P_OVERFLOW_ERR :bit16; + P_UNDERFLOW_ERR:bit16; + end; + + TPCIE_RX_LAST_TLP0=bit32; + + TPCIE_RX_LAST_TLP1=bit32; + + TPCIE_RX_LAST_TLP2=bit32; + + TPCIE_RX_LAST_TLP3=bit32; + + TPCIE_SRIOV_STATUS=bitpacked record + SRIOV_VF_MIGRATION_STATUS:bit1; + RESERVED0 :bit31; + end; + + TPCIE_STRAP_I2C_BD=bitpacked record + STRAP_BIF_I2C_SLV_ADR:bit7; + STRAP_BIF_DBG_I2C_EN :bit1; + RESERVED0 :bit24; + end; + + TPCIE_TPH_REQR_CAP=bitpacked record + TPH_REQR_NO_ST_MODE_SUPPORTED :bit1; + TPH_REQR_INT_VEC_MODE_SUPPORTED :bit1; + TPH_REQR_DEV_SPC_MODE_SUPPORTED :bit1; + RESERVED0 :bit5; + TPH_REQR_EXTND_TPH_REQR_SUPPORED:bit1; + TPH_REQR_ST_TABLE_LOCATION :bit2; + RESERVED1 :bit5; + TPH_REQR_ST_TABLE_SIZE :bit11; + RESERVED2 :bit5; + end; + + TPCIE_TX_LAST_TLP0=bit32; + + TPCIE_TX_LAST_TLP1=bit32; + + TPCIE_TX_LAST_TLP2=bit32; + + TPCIE_TX_LAST_TLP3=bit32; + + TPERFCOUNTER_STATE=bitpacked record + PERFCOUNTER_CNT0_STATE:bit2; + PERFCOUNTER_STATE_SEL0:bit1; + RESERVED0 :bit1; + PERFCOUNTER_CNT1_STATE:bit2; + PERFCOUNTER_STATE_SEL1:bit1; + RESERVED1 :bit1; + PERFCOUNTER_CNT2_STATE:bit2; + PERFCOUNTER_STATE_SEL2:bit1; + RESERVED2 :bit1; + PERFCOUNTER_CNT3_STATE:bit2; + PERFCOUNTER_STATE_SEL3:bit1; + RESERVED3 :bit1; + PERFCOUNTER_CNT4_STATE:bit2; + PERFCOUNTER_STATE_SEL4:bit1; + RESERVED4 :bit1; + PERFCOUNTER_CNT5_STATE:bit2; + PERFCOUNTER_STATE_SEL5:bit1; + RESERVED5 :bit1; + PERFCOUNTER_CNT6_STATE:bit2; + PERFCOUNTER_STATE_SEL6:bit1; + RESERVED6 :bit1; + PERFCOUNTER_CNT7_STATE:bit2; + PERFCOUNTER_STATE_SEL7:bit1; + RESERVED7 :bit1; + end; + + TPPLL_STATUS_DEBUG=bitpacked record + PLL_DEBUG_BUS :bit16; + PLL_UNLOCK :bit1; + PLL_CAL_RESULT :bit4; + RESERVED0 :bit3; + PLL_POWERGOOD_ISO_ENB:bit1; + PLL_POWERGOOD_S :bit1; + PLL_POWERGOOD_V :bit1; + RESERVED1 :bit5; + end; + + TPRESCALE_VALUES_B=bitpacked record + PRESCALE_BIAS_B :bit16; + PRESCALE_SCALE_B:bit16; + end; + + TPRESCALE_VALUES_G=bitpacked record + PRESCALE_BIAS_G :bit16; + PRESCALE_SCALE_G:bit16; + end; + + TPRESCALE_VALUES_R=bitpacked record + PRESCALE_BIAS_R :bit16; + PRESCALE_SCALE_R:bit16; + end; + + TRAS_CB_SIGNATURE0=bit32; + + TRAS_DB_SIGNATURE0=bit32; + + TRAS_IA_SIGNATURE0=bit32; + + TRAS_IA_SIGNATURE1=bit32; + + TRAS_PA_SIGNATURE0=bit32; + + TRAS_SC_SIGNATURE0=bit32; + + TRAS_SC_SIGNATURE1=bit32; + + TRAS_SC_SIGNATURE2=bit32; + + TRAS_SC_SIGNATURE3=bit32; + + TRAS_SC_SIGNATURE4=bit32; + + TRAS_SC_SIGNATURE5=bit32; + + TRAS_SC_SIGNATURE6=bit32; + + TRAS_SC_SIGNATURE7=bit32; + + TRAS_SQ_SIGNATURE0=bit32; + + TRAS_SX_SIGNATURE0=bit32; + + TRAS_SX_SIGNATURE1=bit32; + + TRAS_SX_SIGNATURE2=bit32; + + TRAS_SX_SIGNATURE3=bit32; + + TRAS_TA_SIGNATURE0=bit32; + + TRAS_TA_SIGNATURE1=bit32; + + TRAS_TD_SIGNATURE0=bit32; + + TREGAMMA_LUT_INDEX=bitpacked record + REGAMMA_LUT_INDEX:bit9; + RESERVED0 :bit23; + end; + + TRLC_CP_SCHEDULERS=bitpacked record + scheduler0:bit8; + scheduler1:bit8; + scheduler2:bit8; + scheduler3:bit8; + end; + + TRLC_DYN_PG_STATUS=bit32; + + TRLC_GPM_GENERAL_0=bit32; + + TRLC_GPM_GENERAL_1=bit32; + + TRLC_GPM_GENERAL_2=bit32; + + TRLC_GPM_GENERAL_3=bit32; + + TRLC_GPM_GENERAL_4=bit32; + + TRLC_GPM_GENERAL_5=bit32; + + TRLC_GPM_GENERAL_6=bit32; + + TRLC_GPM_GENERAL_7=bit32; + + TRLC_GPU_IOV_SCH_0=bit32; + + TRLC_GPU_IOV_SCH_1=bit32; + + TRLC_GPU_IOV_SCH_2=bit32; + + TRLC_GPU_IOV_SCH_3=bit32; + + TRLC_SMU_SAFE_MODE=bitpacked record + CMD :bit1; + MESSAGE :bit4; + RESERVED1:bit3; + RESPONSE :bit4; + RESERVED :bit20; + end; + + TRLC_SRM_ARAM_ADDR=bitpacked record + ADDR :bit10; + RESERVED:bit22; + end; + + TRLC_SRM_ARAM_DATA=bit32; + + TRLC_SRM_DRAM_ADDR=bitpacked record + ADDR :bit10; + RESERVED:bit22; + end; + + TRLC_SRM_DRAM_DATA=bit32; + + TRLC_SRM_GPM_ABORT=bitpacked record + ABORT :bit1; + RESERVED:bit31; + end; + + TRLC_THREAD1_DELAY=bitpacked record + CU_IDEL_DELAY :bit8; + LBPW_INNER_LOOP_DELAY:bit8; + LBPW_OUTER_LOOP_DELAY:bit8; + SPARE :bit8; + end; + + TROM_SMC_IND_INDEX=bit32; + + TSCLV_ROUND_OFFSET=bitpacked record + SCL_ROUND_OFFSET_RGB_Y:bit16; + SCL_ROUND_OFFSET_CBCR :bit16; + end; + + TSDMA0_ATOMIC_CNTL=bitpacked record + LOOP_TIMER :bit31; + ATOMIC_RTN_INT_ENABLE:bit1; + end; + + TSDMA0_GFX_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA0_GFX_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_GFX_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA0_GFX_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA0_GFX_RB_BASE=bit32; + + TSDMA0_GFX_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA0_GFX_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_STATUS1_REG=bitpacked record + CE_WREQ_IDLE :bit1; + CE_WR_IDLE :bit1; + CE_SPLIT_IDLE:bit1; + CE_RREQ_IDLE :bit1; + CE_OUT_IDLE :bit1; + CE_IN_IDLE :bit1; + CE_DST_IDLE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + CE_CMD_IDLE :bit1; + CE_AFIFO_FULL:bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + CE_INFO_FULL :bit1; + CE_INFO1_FULL:bit1; + RESERVED4 :bit2; + CE_RD_STALL :bit1; + CE_WR_STALL :bit1; + RESERVED5 :bit13; + end; + + TSDMA0_STATUS2_REG=bitpacked record + ID :bit2; + F32_INSTR_PTR:bit14; + CMD_OP :bit16; + end; + + TSDMA0_VM_CTX_CNTL=bitpacked record + PRIV :bit1; + RESERVED0:bit3; + VMID :bit4; + RESERVED1:bit24; + end; + + TSDMA1_ATOMIC_CNTL=bitpacked record + LOOP_TIMER :bit31; + ATOMIC_RTN_INT_ENABLE:bit1; + end; + + TSDMA1_GFX_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA1_GFX_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_GFX_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA1_GFX_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA1_GFX_RB_BASE=bit32; + + TSDMA1_GFX_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA1_GFX_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_STATUS1_REG=bitpacked record + CE_WREQ_IDLE :bit1; + CE_WR_IDLE :bit1; + CE_SPLIT_IDLE:bit1; + CE_RREQ_IDLE :bit1; + CE_OUT_IDLE :bit1; + CE_IN_IDLE :bit1; + CE_DST_IDLE :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + CE_CMD_IDLE :bit1; + CE_AFIFO_FULL:bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + CE_INFO_FULL :bit1; + CE_INFO1_FULL:bit1; + RESERVED4 :bit2; + CE_RD_STALL :bit1; + CE_WR_STALL :bit1; + RESERVED5 :bit13; + end; + + TSDMA1_STATUS2_REG=bitpacked record + ID :bit2; + F32_INSTR_PTR:bit14; + CMD_OP :bit16; + end; + + TSDMA1_VM_CTX_CNTL=bitpacked record + PRIV :bit1; + RESERVED0:bit3; + VMID :bit4; + RESERVED1:bit24; + end; + + TSDMA_PGFSM_CONFIG=bitpacked record + FSM_ADDR :bit8; + POWER_DOWN :bit1; + POWER_UP :bit1; + P1_SELECT :bit1; + P2_SELECT :bit1; + WRITE :bit1; + READ :bit1; + RESERVED0 :bit13; + SRBM_OVERRIDE:bit1; + REG_ADDR :bit4; + end; + + TSDMA_POWER_GATING=bitpacked record + PG_CNTL_ENABLE :bit1; + AUTOMATIC_STATUS_ENABLE:bit1; + PG_STATE_VALID :bit1; + RESERVED0 :bit1; + PG_CNTL_STATUS :bit2; + SDMA0_ON_CONDITION :bit1; + SDMA1_ON_CONDITION :bit1; + POWER_OFF_DELAY :bit12; + POWER_ON_DELAY :bit12; + end; + + TSEM_ACTIVE_FCN_ID=bitpacked record + VFID :bit4; + RESERVED0:bit27; + VF :bit1; + end; + + TSH_MEM_APE1_LIMIT=bit32; + + TSINK_DESCRIPTION0=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION1=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION2=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION3=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION4=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION5=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION6=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION7=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION8=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION9=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSMU_PM_STATUS_100=bit32; + + TSMU_PM_STATUS_101=bit32; + + TSMU_PM_STATUS_102=bit32; + + TSMU_PM_STATUS_103=bit32; + + TSMU_PM_STATUS_104=bit32; + + TSMU_PM_STATUS_105=bit32; + + TSMU_PM_STATUS_106=bit32; + + TSMU_PM_STATUS_107=bit32; + + TSMU_PM_STATUS_108=bit32; + + TSMU_PM_STATUS_109=bit32; + + TSMU_PM_STATUS_110=bit32; + + TSMU_PM_STATUS_111=bit32; + + TSMU_PM_STATUS_112=bit32; + + TSMU_PM_STATUS_113=bit32; + + TSMU_PM_STATUS_114=bit32; + + TSMU_PM_STATUS_115=bit32; + + TSMU_PM_STATUS_116=bit32; + + TSMU_PM_STATUS_117=bit32; + + TSMU_PM_STATUS_118=bit32; + + TSMU_PM_STATUS_119=bit32; + + TSMU_PM_STATUS_120=bit32; + + TSMU_PM_STATUS_121=bit32; + + TSMU_PM_STATUS_122=bit32; + + TSMU_PM_STATUS_123=bit32; + + TSMU_PM_STATUS_124=bit32; + + TSMU_PM_STATUS_125=bit32; + + TSMU_PM_STATUS_126=bit32; + + TSMU_PM_STATUS_127=bit32; + + TSMU_SMC_IND_INDEX=bit32; + TSPI_CDBG_SYS_HP3D=bitpacked record PS_EN :bit1; VS_EN :bit1; @@ -6354,6 +28770,8 @@ type RESERVED3 :bit19; end; + TSPMI_SRAM_ADDRESS=bit32; + TSQ_BUF_RSRC_WORD0=bit32; TSQ_BUF_RSRC_WORD1=bitpacked record @@ -6481,6 +28899,85 @@ type BORDER_COLOR_TYPE:bit2; end; + TSQ_POWER_THROTTLE=bitpacked record + MIN_POWER :bit14; + RESERVED0 :bit2; + MAX_POWER :bit14; + PHASE_OFFSET:bit2; + end; + + TSQ_WAVE_GPR_ALLOC=bitpacked record + VGPR_BASE:bit6; + RESERVED0:bit2; + VGPR_SIZE:bit6; + RESERVED1:bit2; + SGPR_BASE:bit6; + RESERVED2:bit2; + SGPR_SIZE:bit4; + RESERVED3:bit4; + end; + + TSQ_WAVE_LDS_ALLOC=bitpacked record + LDS_BASE :bit8; + RESERVED0:bit4; + LDS_SIZE :bit9; + RESERVED1:bit11; + end; + + TSQ_WREXEC_EXEC_HI=bitpacked record + ADDR_HI :bit16; + RESERVED0 :bit10; + FIRST_WAVE:bit1; + ATC :bit1; + MTYPE :bit3; + MSB :bit1; + end; + + TSQ_WREXEC_EXEC_LO=bit32; + + TSRBM_CREDIT_RESET=bitpacked record + CREDIT_RESET_BIF :bit1; + CREDIT_RESET_SMU :bit1; + CREDIT_RESET_DC :bit1; + CREDIT_RESET_GIONB:bit1; + CREDIT_RESET_ACP :bit1; + CREDIT_RESET_XDMA :bit1; + CREDIT_RESET_ODE :bit1; + CREDIT_RESET_REGBB:bit1; + CREDIT_RESET_VP8 :bit1; + CREDIT_RESET_GRBM :bit1; + CREDIT_RESET_UVD :bit1; + CREDIT_RESET_VCE0 :bit1; + CREDIT_RESET_VCE1 :bit1; + CREDIT_RESET_ISP :bit1; + CREDIT_RESET_SAM :bit1; + CREDIT_RESET_MCB :bit1; + CREDIT_RESET_MCC0 :bit1; + CREDIT_RESET_MCC1 :bit1; + CREDIT_RESET_MCC2 :bit1; + CREDIT_RESET_MCC3 :bit1; + CREDIT_RESET_MCC4 :bit1; + CREDIT_RESET_MCC5 :bit1; + CREDIT_RESET_MCC6 :bit1; + CREDIT_RESET_MCC7 :bit1; + CREDIT_RESET_MCD0 :bit1; + CREDIT_RESET_MCD1 :bit1; + CREDIT_RESET_MCD2 :bit1; + CREDIT_RESET_MCD3 :bit1; + CREDIT_RESET_MCD4 :bit1; + CREDIT_RESET_MCD5 :bit1; + CREDIT_RESET_MCD6 :bit1; + CREDIT_RESET_MCD7 :bit1; + end; + + TSRBM_PERFMON_CNTL=bitpacked record + PERFMON_STATE :bit4; + RESERVED0 :bit4; + PERFMON_ENABLE_MODE :bit2; + PERFMON_SAMPLE_ENABLE:bit1; + RESERVED1 :bit21; + end; + TSX_MRT0_BLEND_OPT=bitpacked record COLOR_SRC_OPT :bit3; RESERVED0 :bit1; @@ -6674,6 +29171,316 @@ type ADDR :bit26; end; + TTMDS_CONTROL_CHAR=bitpacked record + TMDS_CONTROL_CHAR0_OUT_EN:bit1; + TMDS_CONTROL_CHAR1_OUT_EN:bit1; + TMDS_CONTROL_CHAR2_OUT_EN:bit1; + TMDS_CONTROL_CHAR3_OUT_EN:bit1; + RESERVED0 :bit28; + end; + + TUNIPHYA_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYB_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYC_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYD_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYE_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYF_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUNIPHYG_LINK_CNTL=bitpacked record + UNIPHY_PFREQCHG :bit1; + RESERVED0 :bit3; + UNIPHY_PIXVLD_RESET :bit1; + RESERVED1 :bit3; + UNIPHY_MINIMUM_PIXVLD_LOW_DURATION:bit3; + RESERVED2 :bit1; + UNIPHY_CHANNEL0_INVERT :bit1; + UNIPHY_CHANNEL1_INVERT :bit1; + UNIPHY_CHANNEL2_INVERT :bit1; + UNIPHY_CHANNEL3_INVERT :bit1; + RESERVED3 :bit4; + UNIPHY_LANE_STAGGER_DELAY :bit3; + RESERVED4 :bit1; + UNIPHY_LINK_ENABLE_HPD_MASK :bit2; + RESERVED5 :bit6; + end; + + TUVD_LMI_ADDR_EXT2=bitpacked record + SCPU_ADDR_EXT :bit4; + SCPU_VM_ADDR_EXT :bit4; + SCPU_NC0_ADDR_EXT:bit4; + SCPU_NC1_ADDR_EXT:bit4; + RESERVED0 :bit16; + end; + + TUVD_LMI_SWAP_CNTL=bitpacked record + RB_MC_SWAP :bit2; + IB_MC_SWAP :bit2; + RB_RPTR_MC_SWAP :bit2; + VCPU_R_MC_SWAP :bit2; + VCPU_W_MC_SWAP :bit2; + CM_MC_SWAP :bit2; + IT_MC_SWAP :bit2; + DB_R_MC_SWAP :bit2; + DB_W_MC_SWAP :bit2; + CSM_MC_SWAP :bit2; + RESERVED0 :bit2; + MP_REF16_MC_SWAP:bit2; + DBW_MC_SWAP :bit2; + RB_WR_MC_SWAP :bit2; + RE_MC_SWAP :bit2; + MP_MC_SWAP :bit2; + end; + + TUVD_MPC_SET_MUXA0=bitpacked record + VARA_0 :bit6; + VARA_1 :bit6; + VARA_2 :bit6; + VARA_3 :bit6; + VARA_4 :bit6; + RESERVED0:bit2; + end; + + TUVD_MPC_SET_MUXA1=bitpacked record + VARA_5 :bit6; + VARA_6 :bit6; + VARA_7 :bit6; + RESERVED0:bit14; + end; + + TUVD_MPC_SET_MUXB0=bitpacked record + VARB_0 :bit6; + VARB_1 :bit6; + VARB_2 :bit6; + VARB_3 :bit6; + VARB_4 :bit6; + RESERVED0:bit2; + end; + + TUVD_MPC_SET_MUXB1=bitpacked record + VARB_5 :bit6; + VARB_6 :bit6; + VARB_7 :bit6; + RESERVED0:bit14; + end; + + TUVD_SEMA_ADDR_LOW=bitpacked record + ADDR_22_3:bit20; + RESERVED0:bit12; + end; + + TUVD_SUVD_CGC_CTRL=bitpacked record + SRE_MODE :bit1; + SIT_MODE :bit1; + SMP_MODE :bit1; + SCM_MODE :bit1; + SDB_MODE :bit1; + SCLR_MODE :bit1; + UVD_SC_MODE:bit1; + RESERVED0 :bit25; + end; + + TUVD_SUVD_CGC_GATE=bitpacked record + SRE :bit1; + SIT :bit1; + SMP :bit1; + SCM :bit1; + SDB :bit1; + SRE_H264 :bit1; + SRE_HEVC :bit1; + SIT_H264 :bit1; + SIT_HEVC :bit1; + SCM_H264 :bit1; + SCM_HEVC :bit1; + SDB_H264 :bit1; + SDB_HEVC :bit1; + SCLR :bit1; + UVD_SC :bit1; + RESERVED0:bit17; + end; + + TVCE_LMI_SWAP_CNTL=bitpacked record + VCPU_W_MC_SWAP:bit2; + WR_MC_CID_SWAP:bit12; + RESERVED0 :bit6; + RESERVED1 :bit6; + RESERVED2 :bit6; + end; + + TVGA25_PPLL_ANALOG=bitpacked record + VGA25_CAL_MODE :bit5; + VGA25_PPLL_PFD_PULSE_SEL:bit2; + RESERVED0 :bit1; + VGA25_PPLL_CP :bit4; + VGA25_PPLL_LF_MODE :bit9; + RESERVED1 :bit3; + VGA25_PPLL_IBIAS :bit8; + end; + + TVGA25_PPLL_FB_DIV=bitpacked record + VGA25_PPLL_FB_DIV_FRACTION :bit4; + VGA25_PPLL_FB_DIV_FRACTION_CNTL:bit2; + RESERVED0 :bit10; + VGA25_PPLL_FB_DIV :bit11; + RESERVED1 :bit5; + end; + + TVGA28_PPLL_ANALOG=bitpacked record + VGA28_CAL_MODE :bit5; + VGA28_PPLL_PFD_PULSE_SEL:bit2; + RESERVED0 :bit1; + VGA28_PPLL_CP :bit4; + VGA28_PPLL_LF_MODE :bit9; + RESERVED1 :bit3; + VGA28_PPLL_IBIAS :bit8; + end; + + TVGA28_PPLL_FB_DIV=bitpacked record + VGA28_PPLL_FB_DIV_FRACTION :bit4; + VGA28_PPLL_FB_DIV_FRACTION_CNTL:bit2; + RESERVED0 :bit10; + VGA28_PPLL_FB_DIV :bit11; + RESERVED1 :bit5; + end; + + TVGA41_PPLL_ANALOG=bitpacked record + VGA41_CAL_MODE :bit5; + VGA41_PPLL_PFD_PULSE_SEL:bit2; + RESERVED0 :bit1; + VGA41_PPLL_CP :bit4; + VGA41_PPLL_LF_MODE :bit9; + RESERVED1 :bit3; + VGA41_PPLL_IBIAS :bit8; + end; + + TVGA41_PPLL_FB_DIV=bitpacked record + VGA41_PPLL_FB_DIV_FRACTION :bit4; + VGA41_PPLL_FB_DIV_FRACTION_CNTL:bit2; + RESERVED0 :bit10; + VGA41_PPLL_FB_DIV :bit11; + RESERVED1 :bit5; + end; + + TVGA_CACHE_CONTROL=bitpacked record + VGA_WRITE_THROUGH_CACHE_DIS:bit1; + RESERVED0 :bit7; + VGA_READ_CACHE_DISABLE :bit1; + RESERVED1 :bit7; + VGA_READ_BUFFER_INVALIDATE :bit1; + RESERVED2 :bit3; + VGA_DCCIF_W256ONLY :bit1; + RESERVED3 :bit3; + VGA_DCCIF_WC_TIMEOUT :bit6; + RESERVED4 :bit2; + end; + + TVGA_SOURCE_SELECT=bitpacked record + VGA_SOURCE_SEL_A:bit3; + RESERVED0 :bit5; + VGA_SOURCE_SEL_B:bit3; + RESERVED1 :bit21; + end; + TVGT_NUM_INSTANCES=bit32; TVGT_STRMOUT_DELAY=bitpacked record @@ -6685,6 +29492,220 @@ type RESERVED0 :bit12; end; + TVM_CONTEXT0_CNTL2=bitpacked record + CLEAR_PROTECTION_FAULT_STATUS_ADDR :bit1; + ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT:bit1; + ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT :bit1; + ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES :bit1; + WAIT_FOR_IDLE_WHEN_INVALIDATE :bit1; + RESERVED0 :bit27; + end; + + TVM_CONTEXT1_CNTL2=bitpacked record + CLEAR_PROTECTION_FAULT_STATUS_ADDR :bit1; + ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT:bit1; + ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT :bit1; + ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES :bit1; + WAIT_FOR_IDLE_WHEN_INVALIDATE :bit1; + RESERVED0 :bit27; + end; + + TAFMT_RAMP_CONTROL0=bitpacked record + AFMT_RAMP_MAX_COUNT:bit24; + RESERVED0 :bit7; + AFMT_RAMP_DATA_SIGN:bit1; + end; + + TAFMT_RAMP_CONTROL1=bitpacked record + AFMT_RAMP_MIN_COUNT :bit24; + AFMT_AUDIO_TEST_CH_DISABLE:bit8; + end; + + TAFMT_RAMP_CONTROL2=bitpacked record + AFMT_RAMP_INC_COUNT:bit24; + RESERVED0 :bit8; + end; + + TAFMT_RAMP_CONTROL3=bitpacked record + AFMT_RAMP_DEC_COUNT:bit24; + RESERVED0 :bit8; + end; + + TATC_ATS_FAULT_CNTL=bitpacked record + FAULT_REGISTER_LOG :bit9; + RESERVED0 :bit1; + FAULT_INTERRUPT_TABLE:bit9; + RESERVED1 :bit1; + FAULT_CRASH_TABLE :bit9; + RESERVED2 :bit3; + end; + + TATC_ATS_SMU_STATUS=bitpacked record + VDDGFX_POWERED_DOWN:bit1; + RESERVED0 :bit31; + end; + + TATC_L1RD_DEBUG_TLB=bitpacked record + DISABLE_FRAGMENTS :bit1; + DISABLE_INVALIDATE_BY_ADDRESS_RANGE:bit1; + RESERVED0 :bit2; + EFFECTIVE_CAM_SIZE :bit4; + EFFECTIVE_WORK_QUEUE_SIZE :bit3; + RESERVED1 :bit1; + CREDITS_L1_L2 :bit6; + RESERVED2 :bit2; + CREDITS_L1_RPB :bit8; + DEBUG_ECO :bit2; + INVALIDATE_ALL :bit1; + DISABLE_CACHING_FAULT_RETURNS :bit1; + end; + + TATC_L1WR_DEBUG_TLB=bitpacked record + DISABLE_FRAGMENTS :bit1; + DISABLE_INVALIDATE_BY_ADDRESS_RANGE:bit1; + RESERVED0 :bit2; + EFFECTIVE_CAM_SIZE :bit4; + EFFECTIVE_WORK_QUEUE_SIZE :bit3; + RESERVED1 :bit1; + CREDITS_L1_L2 :bit6; + RESERVED2 :bit2; + CREDITS_L1_RPB :bit8; + DEBUG_ECO :bit2; + INVALIDATE_ALL :bit1; + DISABLE_CACHING_FAULT_RETURNS :bit1; + end; + + TATC_L2_CACHE_DATA0=bitpacked record + DATA_REGISTER_VALID :bit1; + CACHE_ENTRY_VALID :bit1; + CACHED_ATTRIBUTES :bit18; + VIRTUAL_PAGE_ADDRESS_HIGH:bit4; + RESERVED0 :bit8; + end; + + TATC_L2_CACHE_DATA1=bit32; + + TATC_L2_CACHE_DATA2=bitpacked record + PHYSICAL_PAGE_ADDRESS_LOW:bit28; + RESERVED0 :bit4; + end; + + TATC_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TATC_PERFCOUNTER_LO=bit32; + + TAUDIO_DESCRIPTOR10=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR11=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR12=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUDIO_DESCRIPTOR13=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAUX_DPHY_RX_STATUS=bitpacked record + AUX_RX_STATE :bit3; + RESERVED0 :bit5; + AUX_RX_SYNC_VALID_COUNT :bit5; + RESERVED1 :bit3; + AUX_RX_HALF_SYM_PERIOD_FRACT:bit5; + AUX_RX_HALF_SYM_PERIOD :bit9; + RESERVED2 :bit2; + end; + + TAUX_DPHY_TX_STATUS=bitpacked record + AUX_TX_ACTIVE :bit1; + RESERVED0 :bit3; + AUX_TX_STATE :bit3; + RESERVED1 :bit9; + AUX_TX_HALF_SYM_PERIOD:bit9; + RESERVED2 :bit7; + end; + + TAZALIA_CRC0_RESULT=bit32; + + TAZALIA_CRC1_RESULT=bit32; + + TAZALIA_STREAM_DATA=bit32; + + TAZ_TEST_DEBUG_DATA=bit32; + + TBIF_ATOMIC_ERR_LOG=bitpacked record + UR_ATOMIC_OPCODE :bit1; + UR_ATOMIC_REQEN_LOW :bit1; + RESERVED0 :bit14; + CLEAR_UR_ATOMIC_OPCODE :bit1; + CLEAR_UR_ATOMIC_REQEN_LOW:bit1; + RESERVED1 :bit14; + end; + + TBIF_RFE_MMCFG_CNTL=bitpacked record + CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN:bit1; + CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL:bit3; + CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN:bit1; + CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL:bit3; + RESERVED0 :bit24; + end; + + TBIF_VIRT_RESET_REQ=bitpacked record + VIRT_RESET_REQ_VF :bit16; + RESERVED0 :bit15; + VIRT_RESET_REQ_SOFTPF:bit1; + end; + + TBL1_PWM_USER_LEVEL=bitpacked record + BL1_PWM_USER_LEVEL:bit17; + RESERVED0 :bit15; + end; + + TBLND_V_UPDATE_LOCK=bitpacked record + BLND_DCP_GRPH_V_UPDATE_LOCK :bit1; + BLND_DCP_GRPH_SURF_V_UPDATE_LOCK:bit1; + RESERVED0 :bit6; + BLND_DCP_OVL_V_UPDATE_LOCK :bit1; + RESERVED1 :bit7; + BLND_DCP_CUR_V_UPDATE_LOCK :bit1; + RESERVED2 :bit7; + BLND_DCP_CUR2_V_UPDATE_LOCK :bit1; + RESERVED3 :bit3; + BLND_SCL_V_UPDATE_LOCK :bit1; + BLND_BLND_V_UPDATE_LOCK :bit1; + RESERVED4 :bit1; + BLND_V_UPDATE_LOCK_MODE :bit1; + end; + + TBL_PWM_PERIOD_CNTL=bitpacked record + BL_PWM_PERIOD :bit16; + BL_PWM_PERIOD_BITCNT:bit4; + RESERVED0 :bit12; + end; + TCB_COLOR0_DCC_BASE=bit32; TCB_COLOR1_DCC_BASE=bit32; @@ -6717,6 +29738,35 @@ type TCB_PERFCOUNTER3_LO=bit32; + TCGTT_ROM_CLK_CTRL0=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS:bit8; + RESERVED0 :bit18; + SOFT_OVERRIDE1:bit1; + SOFT_OVERRIDE0:bit1; + end; + + TCG_THERMAL_INT_ENA=bitpacked record + THERM_INTH_SET :bit1; + THERM_INTL_SET :bit1; + THERM_TRIGGER_SET:bit1; + THERM_INTH_CLR :bit1; + THERM_INTL_CLR :bit1; + THERM_TRIGGER_CLR:bit1; + RESERVED0 :bit26; + end; + + TCNV_TEST_CRC_GREEN=bitpacked record + RESERVED0 :bit4; + CNV_TEST_CRC_GREEN_MASK:bit12; + CNV_TEST_CRC_SIG_GREEN :bit16; + end; + + TCORB_WRITE_POINTER=bitpacked record + CORB_WRITE_POINTER:bit8; + RESERVED0 :bit24; + end; + TCP_ATOMIC_PREOP_HI=bit32; TCP_ATOMIC_PREOP_LO=bit32; @@ -6838,6 +29888,11 @@ type TCP_PFP_HEADER_DUMP=bit32; + TCP_RB_RPTR_ADDR_HI=bitpacked record + RB_RPTR_ADDR_HI:bit16; + RESERVED0 :bit16; + end; + TCP_ROQ1_THRESHOLDS=bitpacked record RB1_START :bit8; RB2_START :bit8; @@ -6869,6 +29924,82 @@ type SEM_ADDR_LO :bit29; end; + TCRTC_BLANK_CONTROL=bitpacked record + CRTC_CURRENT_BLANK_STATE:bit1; + RESERVED0 :bit7; + CRTC_BLANK_DATA_EN :bit1; + RESERVED1 :bit7; + CRTC_BLANK_DE_MODE :bit1; + RESERVED2 :bit15; + end; + + TCRTC_COUNT_CONTROL=bitpacked record + CRTC_HORZ_COUNT_BY2_EN :bit1; + CRTC_HORZ_REPETITION_COUNT:bit4; + RESERVED0 :bit27; + end; + + TCRTC_GSL_VSYNC_GAP=bitpacked record + CRTC_GSL_VSYNC_GAP_LIMIT :bit8; + CRTC_GSL_VSYNC_GAP_DELAY :bit8; + CRTC_GSL_VSYNC_GAP_SOURCE_SEL :bit1; + CRTC_GSL_VSYNC_GAP_MODE :bit2; + CRTC_GSL_VSYNC_GAP_CLEAR :bit1; + CRTC_GSL_VSYNC_GAP_OCCURRED :bit1; + RESERVED0 :bit2; + CRTC_GSL_VSYNC_GAP_MASTER_FASTER:bit1; + CRTC_GSL_VSYNC_GAP :bit8; + end; + + TCRTC_H_SYNC_A_CNTL=bitpacked record + CRTC_H_SYNC_A_POL :bit1; + RESERVED0 :bit15; + CRTC_COMP_SYNC_A_EN :bit1; + CRTC_H_SYNC_A_CUTOFF:bit1; + RESERVED1 :bit14; + end; + + TCRTC_H_SYNC_B_CNTL=bitpacked record + CRTC_H_SYNC_B_POL :bit1; + RESERVED0 :bit15; + CRTC_COMP_SYNC_B_EN :bit1; + CRTC_H_SYNC_B_CUTOFF:bit1; + RESERVED1 :bit14; + end; + + TCRTC_STEREO_STATUS=bitpacked record + CRTC_STEREO_CURRENT_EYE :bit1; + RESERVED0 :bit7; + CRTC_STEREO_SYNC_OUTPUT :bit1; + RESERVED1 :bit7; + CRTC_STEREO_SYNC_SELECT :bit1; + RESERVED2 :bit3; + CRTC_STEREO_EYE_FLAG :bit1; + RESERVED3 :bit3; + CRTC_STEREO_FORCE_NEXT_EYE_PENDING:bit2; + RESERVED4 :bit6; + end; + + TCRTC_V_SYNC_A_CNTL=bitpacked record + CRTC_V_SYNC_A_POL:bit1; + RESERVED0 :bit31; + end; + + TCRTC_V_SYNC_B_CNTL=bitpacked record + CRTC_V_SYNC_B_POL:bit1; + RESERVED0 :bit31; + end; + + TCUR_STEREO_CONTROL=bitpacked record + CURSOR_STEREO_EN :bit1; + CURSOR_STEREO_OFFSET_YNX:bit1; + RESERVED0 :bit2; + CURSOR_PRIMARY_OFFSET :bit10; + RESERVED1 :bit2; + CURSOR_SECONDARY_OFFSET :bit10; + RESERVED2 :bit6; + end; + TDB_CGTT_CLK_CTRL_0=bitpacked record ON_DELAY :bit4; OFF_HYSTERESIS:bit8; @@ -6968,6 +30099,565 @@ type TDB_ZPASS_COUNT_LOW=bit32; + TDCCG_DISP_CNTL_REG=bitpacked record + RESERVED0 :bit8; + ALLOW_SR_ON_TRANS_REQ:bit1; + RESERVED1 :bit23; + end; + + TDCCG_DS_DEBUG_CNTL=bitpacked record + DCCG_DS_DEBUG_COUNT_ENABLE :bit1; + RESERVED0 :bit3; + DCCG_DS_DEBUG_COUNT_TRIG_VALUE :bit9; + RESERVED1 :bit3; + DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED:bit1; + DCCG_DS_DEBUG_COUNT_TRIG_CLEAR :bit1; + RESERVED2 :bit2; + DCCG_DS_JITTER_COUNT_ENABLE :bit1; + DCCG_DS_JITTER_COUNT_SRC_SEL :bit1; + RESERVED3 :bit2; + DCCG_DS_JITTER_COUNT :bit8; + end; + + TDCCG_DS_DTO_MODULO=bit32; + + TDCCG_PERFMON_CNTL2=bitpacked record + DCCG_PERF_DSICLK_ENABLE:bit1; + DCCG_PERF_REFCLK_ENABLE:bit1; + RESERVED0 :bit30; + end; + + TDCFE_CLOCK_CONTROL=bitpacked record + RESERVED0 :bit4; + DISPCLK_R_DCFE_GATE_DISABLE:bit1; + RESERVED1 :bit3; + DISPCLK_G_DCP_GATE_DISABLE :bit1; + RESERVED2 :bit3; + DISPCLK_G_SCL_GATE_DISABLE :bit1; + RESERVED3 :bit11; + DCFE_TEST_CLK_SEL :bit5; + RESERVED4 :bit2; + DCFE_CLOCK_ENABLE :bit1; + end; + + TDCFE_MEM_PWR_CTRL2=bitpacked record + DCP_LUT_MEM_PWR_MODE_SEL :bit2; + DCP_REGAMMA_MEM_PWR_MODE_SEL:bit2; + SCL_COEFF_MEM_PWR_MODE_SEL :bit2; + DCP_CURSOR_MEM_PWR_MODE_SEL :bit2; + LB_ALPHA_MEM_PWR_MODE_SEL :bit2; + LB_MEM_PWR_MODE_SEL :bit2; + DCP_CURSOR2_MEM_PWR_MODE_SEL:bit2; + BLND_MEM_PWR_MODE_SEL :bit2; + BLND_MEM_PWR_FORCE :bit2; + BLND_MEM_PWR_DIS :bit1; + OVLSCL_MEM_PWR_FORCE :bit1; + OVLSCL_MEM_PWR_DIS :bit1; + DCP_CURSOR2_MEM_PWR_FORCE :bit2; + DCP_CURSOR2_MEM_PWR_DIS :bit1; + RESERVED0 :bit8; + end; + + TDCI_MEM_PWR_STATUS=bitpacked record + DMIF_RDREQ_MEM1_PWR_STATE:bit2; + DMIF_RDREQ_MEM2_PWR_STATE:bit2; + MCIF_RDREQ_MEM_PWR_STATE :bit1; + RESERVED0 :bit1; + MCIF_WRREQ_MEM_PWR_STATE :bit1; + RESERVED1 :bit1; + VGA_MEM_PWR_STATE :bit1; + DMCU_ERAM_MEM_PWR_STATE :bit2; + DMCU_IRAM_MEM_PWR_STATE :bit1; + FBC_MEM_PWR_STATE :bit2; + MCIF_MEM_PWR_STATE :bit2; + MCIF_DWB_MEM_PWR_STATE :bit2; + MCIF_CWB0_MEM_PWR_STATE :bit2; + MCIF_CWB1_MEM_PWR_STATE :bit2; + VIP_MEM_PWR_STATE :bit1; + RESERVED2 :bit1; + DMIF0_ASYNC_MEM_PWR_STATE:bit2; + DMIF0_DATA_MEM_PWR_STATE :bit2; + DMIF0_CHUNK_MEM_PWR_STATE:bit1; + RESERVED3 :bit3; + end; + + TDCO_MEM_PWR_STATUS=bitpacked record + I2C_MEM_PWR_STATE :bit1; + TVOUT_MEM_PWR_STATE:bit1; + MVP_MEM_PWR_STATE :bit1; + DPA_MEM_PWR_STATE :bit1; + DPB_MEM_PWR_STATE :bit1; + DPC_MEM_PWR_STATE :bit1; + DPD_MEM_PWR_STATE :bit1; + DPE_MEM_PWR_STATE :bit1; + DPF_MEM_PWR_STATE :bit1; + DPG_MEM_PWR_STATE :bit1; + HDMI0_MEM_PWR_STATE:bit2; + HDMI1_MEM_PWR_STATE:bit2; + HDMI2_MEM_PWR_STATE:bit2; + HDMI3_MEM_PWR_STATE:bit2; + HDMI4_MEM_PWR_STATE:bit2; + HDMI5_MEM_PWR_STATE:bit2; + HDMI6_MEM_PWR_STATE:bit2; + RESERVED0 :bit8; + end; + + TDCO_STEREOSYNC_SEL=bitpacked record + GENERICA_STEREOSYNC_SEL:bit3; + RESERVED0 :bit13; + GENERICB_STEREOSYNC_SEL:bit3; + RESERVED1 :bit13; + end; + + TDC_ABM1_DEBUG_MISC=bitpacked record + ABM1_HG_FORCE_INTERRUPT:bit1; + RESERVED0 :bit7; + ABM1_LS_FORCE_INTERRUPT:bit1; + RESERVED1 :bit7; + ABM1_BL_FORCE_INTERRUPT:bit1; + RESERVED2 :bit15; + end; + + TDC_GPIO_DVODATA_EN=bitpacked record + DC_GPIO_DVODATA_EN :bit24; + DC_GPIO_DVOCNTL_EN :bit5; + DC_GPIO_DVOCLK_EN :bit1; + DC_GPIO_MVP_DVOCNTL_EN:bit2; + end; + + TDC_GPIO_GENERIC_EN=bitpacked record + DC_GPIO_GENERICA_EN:bit1; + RESERVED0 :bit7; + DC_GPIO_GENERICB_EN:bit1; + RESERVED1 :bit7; + DC_GPIO_GENERICC_EN:bit1; + RESERVED2 :bit3; + DC_GPIO_GENERICD_EN:bit1; + DC_GPIO_GENERICE_EN:bit1; + DC_GPIO_GENERICF_EN:bit1; + DC_GPIO_GENERICG_EN:bit1; + RESERVED3 :bit8; + end; + + TDC_GPIO_GENLK_MASK=bitpacked record + DC_GPIO_GENLK_CLK_MASK :bit1; + DC_GPIO_GENLK_CLK_PD_DIS :bit1; + DC_GPIO_GENLK_CLK_RECV :bit1; + DC_GPIO_GENLK_CLK_PU_EN :bit1; + RESERVED0 :bit4; + DC_GPIO_GENLK_VSYNC_MASK :bit1; + DC_GPIO_GENLK_VSYNC_PD_DIS:bit1; + DC_GPIO_GENLK_VSYNC_RECV :bit1; + DC_GPIO_GENLK_VSYNC_PU_EN :bit1; + RESERVED1 :bit4; + DC_GPIO_SWAPLOCK_A_MASK :bit1; + DC_GPIO_SWAPLOCK_A_PD_DIS :bit1; + DC_GPIO_SWAPLOCK_A_RECV :bit1; + DC_GPIO_SWAPLOCK_A_PU_EN :bit1; + RESERVED2 :bit4; + DC_GPIO_SWAPLOCK_B_MASK :bit1; + DC_GPIO_SWAPLOCK_B_PD_DIS :bit1; + DC_GPIO_SWAPLOCK_B_RECV :bit1; + DC_GPIO_SWAPLOCK_B_PU_EN :bit1; + RESERVED3 :bit4; + end; + + TDC_GPIO_SYNCA_MASK=bitpacked record + DC_GPIO_HSYNCA_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_HSYNCA_PD_DIS :bit1; + RESERVED1 :bit1; + DC_GPIO_HSYNCA_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_VSYNCA_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_VSYNCA_PD_DIS :bit1; + RESERVED4 :bit1; + DC_GPIO_VSYNCA_RECV :bit1; + RESERVED5 :bit9; + DC_GPIO_HSYNCA_CRTC_HSYNC_MASK:bit3; + RESERVED6 :bit1; + DC_GPIO_VSYNCA_CRTC_VSYNC_MASK:bit3; + RESERVED7 :bit1; + end; + + TDC_HPD1_INT_STATUS=bitpacked record + DC_HPD1_INT_STATUS :bit1; + DC_HPD1_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD1_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD2_INT_STATUS=bitpacked record + DC_HPD2_INT_STATUS :bit1; + DC_HPD2_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD2_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD3_INT_STATUS=bitpacked record + DC_HPD3_INT_STATUS :bit1; + DC_HPD3_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD3_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD4_INT_STATUS=bitpacked record + DC_HPD4_INT_STATUS :bit1; + DC_HPD4_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD4_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD5_INT_STATUS=bitpacked record + DC_HPD5_INT_STATUS :bit1; + DC_HPD5_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD5_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD6_INT_STATUS=bitpacked record + DC_HPD6_INT_STATUS :bit1; + DC_HPD6_SENSE :bit1; + RESERVED0 :bit6; + DC_HPD6_RX_INT_STATUS:bit1; + RESERVED1 :bit23; + end; + + TDC_HPD_INT_CONTROL=bitpacked record + DC_HPD_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_I2C_ARBITRATION=bitpacked record + DC_I2C_SW_PRIORITY :bit2; + DC_I2C_REG_RW_CNTL_STATUS :bit2; + DC_I2C_NO_QUEUED_SW_GO :bit1; + RESERVED0 :bit1; + RESERVED1 :bit2; + DC_I2C_ABORT_HW_XFER :bit1; + RESERVED2 :bit3; + DC_I2C_ABORT_SW_XFER :bit1; + RESERVED3 :bit7; + DC_I2C_SW_USE_I2C_REG_REQ :bit1; + DC_I2C_SW_DONE_USING_I2C_REG :bit1; + RESERVED4 :bit2; + DC_I2C_DMCU_USE_I2C_REG_REQ :bit1; + DC_I2C_DMCU_DONE_USING_I2C_REG:bit1; + RESERVED5 :bit6; + end; + + TDC_IP_REQUEST_CNTL=bitpacked record + IP_REQUEST_EN:bit1; + RESERVED0 :bit31; + end; + + TDC_PGFSM_WRITE_REG=bit32; + + TDC_TEST_DEBUG_DATA=bit32; + + TDIDT_DBR_WEIGHT0_3=bitpacked record + WEIGHT0:bit8; + WEIGHT1:bit8; + WEIGHT2:bit8; + WEIGHT3:bit8; + end; + + TDIDT_DBR_WEIGHT4_7=bitpacked record + WEIGHT4:bit8; + WEIGHT5:bit8; + WEIGHT6:bit8; + WEIGHT7:bit8; + end; + + TDIDT_DB_WEIGHT8_11=bitpacked record + WEIGHT8 :bit8; + WEIGHT9 :bit8; + WEIGHT10:bit8; + WEIGHT11:bit8; + end; + + TDIDT_SQ_WEIGHT8_11=bitpacked record + WEIGHT8 :bit8; + WEIGHT9 :bit8; + WEIGHT10:bit8; + WEIGHT11:bit8; + end; + + TDIDT_TCP_WEIGHT0_3=bitpacked record + WEIGHT0:bit8; + WEIGHT1:bit8; + WEIGHT2:bit8; + WEIGHT3:bit8; + end; + + TDIDT_TCP_WEIGHT4_7=bitpacked record + WEIGHT4:bit8; + WEIGHT5:bit8; + WEIGHT6:bit8; + WEIGHT7:bit8; + end; + + TDIDT_TD_WEIGHT8_11=bitpacked record + WEIGHT8 :bit8; + WEIGHT9 :bit8; + WEIGHT10:bit8; + WEIGHT11:bit8; + end; + + TDISP_TIMER_CONTROL=bitpacked record + DISP_TIMER_INT_COUNT :bit25; + DISP_TIMER_INT_ENABLE :bit1; + DISP_TIMER_INT_RUNNING:bit1; + DISP_TIMER_INT_MSK :bit1; + DISP_TIMER_INT_STAT :bit1; + DISP_TIMER_INT_STAT_AK:bit1; + DISP_TIMER_INT :bit1; + RESERVED0 :bit1; + end; + + TDMCU_EVENT_TRIGGER=bitpacked record + GEN_SW_INT_TO_UC :bit1; + RESERVED0 :bit15; + UC_INTERNAL_INT_CODE :bit7; + GEN_UC_INTERNAL_INT_TO_HOST:bit1; + RESERVED1 :bit7; + RESERVED2 :bit1; + end; + + TDMCU_FW_START_ADDR=bitpacked record + FW_START_ADDR_LSB:bit8; + FW_START_ADDR_MSB:bit8; + RESERVED0 :bit16; + end; + + TDMCU_PC_START_ADDR=bitpacked record + PC_START_ADDR_LSB:bit8; + PC_START_ADDR_MSB:bit8; + RESERVED0 :bit16; + end; + + TDMIF_DEBUG02_CORE0=bitpacked record + DB_DATA :bit16; + MC_RDRET_COUNT_EN:bit1; + MC_RDRET_COUNTER :bit11; + RESERVED0 :bit4; + end; + + TDMIF_DEBUG02_CORE1=bitpacked record + DB_DATA :bit16; + MC_RDRET_COUNT_EN:bit1; + MC_RDRET_COUNTER :bit11; + RESERVED0 :bit4; + end; + + TDP_DPHY_8B10B_CNTL=bitpacked record + RESERVED0 :bit8; + DPHY_8B10B_RESET :bit1; + RESERVED1 :bit7; + DPHY_8B10B_EXT_DISP:bit1; + RESERVED2 :bit7; + DPHY_8B10B_CUR_DISP:bit1; + RESERVED3 :bit7; + end; + + TDP_DPHY_CRC_RESULT=bitpacked record + DPHY_CRC_RESULT :bit8; + DPHY_CRC_RESULT1:bit8; + DPHY_CRC_RESULT2:bit8; + DPHY_CRC_RESULT3:bit8; + end; + + TDP_MSA_COLORIMETRY=bitpacked record + DP_MSA_MISC0_OVERRIDE :bit8; + DP_MSA_MISC0_OVERRIDE_ENABLE:bit1; + RESERVED0 :bit23; + end; + + TDP_MSE_LINK_TIMING=bitpacked record + DP_MSE_LINK_FRAME:bit10; + RESERVED0 :bit6; + DP_MSE_LINK_LINE :bit2; + RESERVED1 :bit14; + end; + + TDP_MSE_RATE_UPDATE=bitpacked record + DP_MSE_RATE_UPDATE_PENDING:bit1; + RESERVED0 :bit31; + end; + + TDP_SEC_PACKET_CNTL=bitpacked record + RESERVED0 :bit1; + DP_SEC_ASP_CODING_TYPE :bit3; + DP_SEC_ASP_PRIORITY :bit1; + RESERVED1 :bit3; + DP_SEC_VERSION :bit6; + RESERVED2 :bit2; + DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE:bit1; + RESERVED3 :bit15; + end; + + TDP_TEST_DEBUG_DATA=bit32; + + TDP_VID_STREAM_CNTL=bitpacked record + DP_VID_STREAM_ENABLE :bit1; + RESERVED0 :bit7; + DP_VID_STREAM_DIS_DEFER :bit2; + RESERVED1 :bit6; + DP_VID_STREAM_STATUS :bit1; + RESERVED2 :bit3; + DP_VID_STREAM_CHANGE_KEEPOUT:bit1; + RESERVED3 :bit11; + end; + + TFMT_FORCE_DATA_0_1=bitpacked record + FMT_FORCE_DATA0:bit16; + FMT_FORCE_DATA1:bit16; + end; + + TFMT_FORCE_DATA_2_3=bitpacked record + FMT_FORCE_DATA2:bit16; + FMT_FORCE_DATA3:bit16; + end; + + TGAMMA_CORR_CONTROL=bitpacked record + GAMMA_CORR_MODE:bit2; + RESERVED0 :bit30; + end; + + TGB_MACROTILE_MODE0=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE1=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE2=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE3=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE4=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE5=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE6=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE7=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE8=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE9=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGC_CAC_WEIGHT_CU_0=bitpacked record + WEIGHT_CU_SIG0:bit16; + WEIGHT_CU_SIG1:bit16; + end; + + TGC_CAC_WEIGHT_CU_1=bitpacked record + WEIGHT_CU_SIG2:bit16; + WEIGHT_CU_SIG3:bit16; + end; + + TGC_CAC_WEIGHT_CU_2=bitpacked record + WEIGHT_CU_SIG4:bit16; + WEIGHT_CU_SIG5:bit16; + end; + + TGC_CAC_WEIGHT_CU_3=bitpacked record + WEIGHT_CU_SIG6:bit16; + WEIGHT_CU_SIG7:bit16; + end; + + TGC_CAC_WEIGHT_CU_4=bitpacked record + WEIGHT_CU_SIG8:bit16; + WEIGHT_CU_SIG9:bit16; + end; + + TGC_CAC_WEIGHT_CU_5=bitpacked record + WEIGHT_CU_SIG10:bit16; + WEIGHT_CU_SIG11:bit16; + end; + + TGC_CAC_WEIGHT_CU_6=bitpacked record + WEIGHT_CU_SIG12:bit16; + WEIGHT_CU_SIG13:bit16; + end; + + TGC_CAC_WEIGHT_CU_7=bitpacked record + WEIGHT_CU_SIG14:bit16; + WEIGHT_CU_SIG15:bit16; + end; + TGDS_PS0_CTXSW_CNT0=bitpacked record UPDN:bit16; PTR :bit16; @@ -7132,6 +30822,54 @@ type TGDS_WRITE_COMPLETE=bit32; + TGENERIC_I2C_STATUS=bitpacked record + GENERIC_I2C_STATUS :bit4; + GENERIC_I2C_DONE :bit1; + GENERIC_I2C_ABORTED :bit1; + GENERIC_I2C_TIMEOUT :bit1; + RESERVED0 :bit2; + GENERIC_I2C_STOPPED_ON_NACK:bit1; + GENERIC_I2C_NACK :bit1; + RESERVED1 :bit21; + end; + + TGMCON_PGFSM_CONFIG=bitpacked record + FSM_ADDR :bit8; + POWER_DOWN :bit1; + POWER_UP :bit1; + P1_SELECT :bit1; + P2_SELECT :bit1; + WRITE :bit1; + READ :bit1; + RSRVD :bit13; + SRBM_OVERRIDE:bit1; + REG_ADDR :bit4; + end; + + TGMCON_RENG_EXECUTE=bitpacked record + RENG_EXECUTE_ON_PWR_UP :bit1; + RENG_EXECUTE_NOW :bit1; + RENG_EXECUTE_NOW_START_PTR:bit10; + RENG_EXECUTE_DSP_END_PTR :bit10; + RENG_EXECUTE_END_PTR :bit10; + end; + + TGPU_HDP_FLUSH_DONE=bitpacked record + CP0 :bit1; + CP1 :bit1; + CP2 :bit1; + CP3 :bit1; + CP4 :bit1; + CP5 :bit1; + CP6 :bit1; + CP7 :bit1; + CP8 :bit1; + CP9 :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + RESERVED0:bit20; + end; + TGRBM_HYP_CAM_INDEX=bitpacked record CAM_INDEX:bit3; RESERVED0:bit29; @@ -7142,6 +30880,52 @@ type RESERVED0:bit16; end; + THDP_HOST_PATH_CNTL=bitpacked record + BIF_RDRET_CREDIT :bit3; + MC_WRREQ_CREDIT :bit6; + WR_STALL_TIMER :bit2; + RD_STALL_TIMER :bit2; + RESERVED0 :bit6; + WRITE_COMBINE_TIMER :bit2; + WRITE_COMBINE_EN :bit1; + CACHE_INVALIDATE :bit1; + CLOCK_GATING_DIS :bit1; + REG_CLK_ENABLE_COUNT :bit4; + RESERVED1 :bit1; + ALL_SURFACES_DIS :bit1; + WRITE_THROUGH_CACHE_DIS:bit1; + LIN_RD_CACHE_DIS :bit1; + end; + + THDP_XDP_D2H_RSVD_3=bit32; + + THDP_XDP_D2H_RSVD_4=bit32; + + THDP_XDP_D2H_RSVD_5=bit32; + + THDP_XDP_D2H_RSVD_6=bit32; + + THDP_XDP_D2H_RSVD_7=bit32; + + THDP_XDP_D2H_RSVD_8=bit32; + + THDP_XDP_D2H_RSVD_9=bit32; + + THDP_XDP_HDP_MC_CFG=bitpacked record + HDP_MC_CFG_HST_TAP_WRREQ_PRIV :bit1; + HDP_MC_CFG_HST_TAP_WRREQ_SWAP :bit2; + HDP_MC_CFG_HST_TAP_WRREQ_TRAN :bit1; + HDP_MC_CFG_SID_TAP_WRREQ_PRIV :bit1; + HDP_MC_CFG_SID_TAP_WRREQ_SWAP :bit2; + HDP_MC_CFG_SID_TAP_WRREQ_TRAN :bit1; + HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE :bit6; + HDP_MC_CFG_XDP_HIGHER_PRI_THRESH :bit6; + HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK:bit3; + HDP_MC_CFG_HST_TAP_WRREQ_VMID :bit4; + HDP_MC_CFG_SID_TAP_WRREQ_VMID :bit4; + RESERVED0 :bit1; + end; + TIA_MULTI_VGT_PARAM=bitpacked record PRIMGROUP_SIZE :bit16; PARTIAL_VS_WAVE_ON :bit1; @@ -7169,6 +30953,952 @@ type TIA_PERFCOUNTER3_LO=bit32; + TIH_LEVEL_INTR_MASK=bitpacked record + MASK :bit1; + RESERVED0:bit31; + end; + + TIH_RB_WPTR_ADDR_HI=bitpacked record + ADDR :bit8; + RESERVED0:bit24; + end; + + TIH_RB_WPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TLBV_DESKTOP_HEIGHT=bitpacked record + DESKTOP_HEIGHT:bit15; + RESERVED0 :bit17; + end; + + TLBV_INTERRUPT_MASK=bitpacked record + VBLANK_INTERRUPT_MASK:bit1; + RESERVED0 :bit3; + VLINE_INTERRUPT_MASK :bit1; + RESERVED1 :bit3; + VLINE2_INTERRUPT_MASK:bit1; + RESERVED2 :bit23; + end; + + TLBV_SYNC_RESET_SEL=bitpacked record + LB_SYNC_RESET_SEL :bit2; + RESERVED0 :bit2; + LB_SYNC_RESET_SEL2 :bit1; + RESERVED1 :bit3; + LB_SYNC_RESET_DELAY:bit8; + RESERVED2 :bit6; + LB_SYNC_DURATION :bit2; + RESERVED3 :bit8; + end; + + TLB_BLACK_KEYER_G_Y=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_G_Y:bit12; + RESERVED1 :bit16; + end; + + TLB_KEYER_COLOR_G_Y=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_G_Y:bit12; + RESERVED1 :bit16; + end; + + TLB_TEST_DEBUG_DATA=bit32; + + TLB_VLINE_START_END=bitpacked record + VLINE_START:bit14; + RESERVED0 :bit2; + VLINE_END :bit15; + VLINE_INV :bit1; + end; + + TLVTMA_PWRSEQ_STATE=bitpacked record + LVTMA_PWRSEQ_TARGET_STATE_R:bit1; + LVTMA_PWRSEQ_DIGON :bit1; + LVTMA_PWRSEQ_SYNCEN :bit1; + LVTMA_PWRSEQ_BLON :bit1; + LVTMA_PWRSEQ_DONE :bit1; + RESERVED0 :bit3; + LVTMA_PWRSEQ_STATE :bit4; + RESERVED1 :bit20; + end; + + TMASTER_CREDIT_CNTL=bitpacked record + BIF_MC_RDRET_CREDIT:bit7; + RESERVED0 :bit9; + BIF_AZ_RDRET_CREDIT:bit6; + RESERVED1 :bit10; + end; + + TMASTER_UPDATE_LOCK=bitpacked record + MASTER_UPDATE_LOCK :bit1; + RESERVED0 :bit7; + GSL_CONTROL_MASTER_UPDATE_LOCK:bit1; + RESERVED1 :bit23; + end; + + TMASTER_UPDATE_MODE=bitpacked record + MASTER_UPDATE_MODE :bit3; + RESERVED0 :bit13; + MASTER_UPDATE_INTERLACED_MODE:bit2; + RESERVED1 :bit14; + end; + + TMC_ARB_BUSY_STATUS=bitpacked record + LM_RD0 :bit1; + LM_RD1 :bit1; + LM_WR0 :bit1; + LM_WR1 :bit1; + HM_RD0 :bit1; + HM_RD1 :bit1; + HM_WR0 :bit1; + HM_WR1 :bit1; + WDE_RD0 :bit1; + WDE_RD1 :bit1; + WDE_WR0 :bit1; + WDE_WR1 :bit1; + POP0 :bit1; + POP1 :bit1; + TAGFIFO0 :bit1; + TAGFIFO1 :bit1; + REPLAY0 :bit1; + REPLAY1 :bit1; + RDRET0 :bit1; + RDRET1 :bit1; + GECC2_RD0:bit1; + GECC2_RD1:bit1; + GECC2_WR0:bit1; + GECC2_WR1:bit1; + WRRET0 :bit1; + WRRET1 :bit1; + RTT0 :bit1; + RTT1 :bit1; + REM_RD0 :bit1; + REM_RD1 :bit1; + REM_WR0 :bit1; + REM_WR1 :bit1; + end; + + TMC_ARB_DRAM_TIMING=bitpacked record + ACTRD :bit8; + ACTWR :bit8; + RASMACTRD:bit8; + RASMACTWR:bit8; + end; + + TMC_ARB_GECC2_DEBUG=bitpacked record + NUM_ERR_BITS:bit2; + DIRECTION :bit1; + DATA_FIELD :bit2; + SW_INJECTION:bit1; + RESERVED0 :bit26; + end; + + TMC_ARB_HARSH_EN_RD=bitpacked record + TX_PRI :bit8; + BW_PRI :bit8; + FIX_PRI:bit8; + ST_PRI :bit8; + end; + + TMC_ARB_HARSH_EN_WR=bitpacked record + TX_PRI :bit8; + BW_PRI :bit8; + FIX_PRI:bit8; + ST_PRI :bit8; + end; + + TMC_ARB_MAX_LAT_CID=bitpacked record + CID_CH0 :bit8; + CID_CH1 :bit8; + WRITE_CH0 :bit1; + WRITE_CH1 :bit1; + REALTIME_CH0:bit1; + REALTIME_CH1:bit1; + RESERVED0 :bit12; + end; + + TMC_ARB_WTM_CNTL_RD=bitpacked record + WTMODE :bit2; + HARSH_PRI :bit1; + ALLOW_STUTTER_GRP0:bit1; + ALLOW_STUTTER_GRP1:bit1; + ALLOW_STUTTER_GRP2:bit1; + ALLOW_STUTTER_GRP3:bit1; + ALLOW_STUTTER_GRP4:bit1; + ALLOW_STUTTER_GRP5:bit1; + ALLOW_STUTTER_GRP6:bit1; + ALLOW_STUTTER_GRP7:bit1; + ACP_HARSH_PRI :bit1; + ACP_OVER_DISP :bit1; + FORCE_ACP_URG :bit1; + RESERVED0 :bit18; + end; + + TMC_ARB_WTM_CNTL_WR=bitpacked record + WTMODE :bit2; + HARSH_PRI :bit1; + ALLOW_STUTTER_GRP0:bit1; + ALLOW_STUTTER_GRP1:bit1; + ALLOW_STUTTER_GRP2:bit1; + ALLOW_STUTTER_GRP3:bit1; + ALLOW_STUTTER_GRP4:bit1; + ALLOW_STUTTER_GRP5:bit1; + ALLOW_STUTTER_GRP6:bit1; + ALLOW_STUTTER_GRP7:bit1; + ACP_HARSH_PRI :bit1; + ACP_OVER_DISP :bit1; + FORCE_ACP_URG :bit1; + RESERVED0 :bit18; + end; + + TMC_BIST_DATA_WORD0=bit32; + + TMC_BIST_DATA_WORD1=bit32; + + TMC_BIST_DATA_WORD2=bit32; + + TMC_BIST_DATA_WORD3=bit32; + + TMC_BIST_DATA_WORD4=bit32; + + TMC_BIST_DATA_WORD5=bit32; + + TMC_BIST_DATA_WORD6=bit32; + + TMC_BIST_DATA_WORD7=bit32; + + TMC_CITF_CREDITS_VM=bitpacked record + READ_ALL :bit6; + WRITE_ALL:bit6; + RESERVED0:bit20; + end; + + TMC_CITF_MISC_RD_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_CITF_MISC_VM_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_CITF_MISC_WR_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_GRUB_TX_CREDITS=bitpacked record + SRCTAG_LIMIT :bit6; + RESERVED0 :bit2; + SRCTAG_RT_RESERVE:bit4; + NPC_RT_RESERVE :bit4; + NPD_RT_RESERVE :bit4; + TX_FIFO_DEPTH :bit5; + RESERVED1 :bit7; + end; + + TMC_HUB_MISC_HUB_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_HUB_MISC_SIP_CG=bitpacked record + ONDLY :bit6; + OFFDLY :bit6; + RDYDLY :bit6; + ENABLE :bit1; + MEM_LS_ENABLE:bit1; + RESERVED0 :bit12; + end; + + TMC_HUB_MISC_STATUS=bitpacked record + OUTSTANDING_READ :bit1; + OUTSTANDING_WRITE :bit1; + OUTSTANDING_ATOMIC :bit1; + OUTSTANDING_HUB_RDREQ :bit1; + OUTSTANDING_HUB_RDRET :bit1; + OUTSTANDING_HUB_WRREQ :bit1; + OUTSTANDING_HUB_WRRET :bit1; + OUTSTANDING_HUB_ATOMIC_REQ:bit1; + OUTSTANDING_HUB_ATOMIC_RET:bit1; + OUTSTANDING_RPB_READ :bit1; + OUTSTANDING_RPB_WRITE :bit1; + OUTSTANDING_RPB_ATOMIC :bit1; + OUTSTANDING_MCD_READ :bit1; + OUTSTANDING_MCD_WRITE :bit1; + OUTSTANDING_MCD_ATOMIC :bit1; + RPB_BUSY :bit1; + WRITE_DEADLOCK_WARNING :bit1; + READ_DEADLOCK_WARNING :bit1; + ATOMIC_DEADLOCK_WARNING :bit1; + GFX_BUSY :bit1; + RESERVED0 :bit12; + end; + + TMC_HUB_RDREQ_SDMA0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_SDMA1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_VCEU0=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_VCEU1=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_XDMAM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_WDP_CREDITS=bitpacked record + VM0 :bit8; + VM1 :bit8; + STOR0:bit8; + STOR1:bit8; + end; + + TMC_HUB_WDP_ISP_MPM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_WDP_ISP_MPS=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_WDP_ISP_SPM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_IO_DEBUG_UP_100=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_101=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_102=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_103=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_104=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_105=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_106=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_107=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_108=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_109=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_110=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_111=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_112=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_113=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_114=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_115=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_116=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_117=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_118=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_119=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_120=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_121=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_122=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_123=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_124=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_125=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_126=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_127=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_128=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_129=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_130=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_131=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_132=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_133=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_134=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_135=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_136=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_137=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_138=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_139=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_140=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_141=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_142=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_143=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_144=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_145=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_146=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_147=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_148=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_149=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_150=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_151=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_152=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_153=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_154=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_155=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_156=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_157=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_158=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_IO_DEBUG_UP_159=bitpacked record + VALUE0:bit8; + VALUE1:bit8; + VALUE2:bit8; + VALUE3:bit8; + end; + + TMC_SEQ_MISC_TIMING=bitpacked record + TRP_WRA :bit6; + TRP_RDA :bit6; + TRP :bit5; + TRFC :bit7; + RESERVED0:bit4; + RESERVED1:bit4; + end; + + TMC_SEQ_RESERVE_0_S=bit32; + + TMC_SEQ_RESERVE_1_S=bit32; + + TMC_SEQ_SREG_STATUS=bitpacked record + AVAIL_RTN:bit4; + RESERVED0:bit4; + PND_RD :bit4; + PND_WR :bit4; + RESERVED1:bit16; + end; + + TMC_SEQ_SUP_IR_STAT=bit32; + + TMC_SHARED_CHREMAP2=bitpacked record + CHAN8 :bit4; + CHAN9 :bit4; + CHAN10:bit4; + CHAN11:bit4; + CHAN12:bit4; + CHAN13:bit4; + CHAN14:bit4; + CHAN15:bit4; + end; + + TMC_VM_NB_MMIOLIMIT=bit32; + + TMC_XBAR_CHTRIREMAP=bitpacked record + CH0 :bit2; + CH1 :bit2; + CH2 :bit2; + RESERVED0:bit26; + end; + + TMC_XPB_P2P_BAR_CFG=bitpacked record + ADDR_SIZE :bit4; + SEND_BAR :bit2; + SNOOP :bit1; + SEND_DIS :bit1; + COMPRESS_DIS :bit1; + UPDATE_DIS :bit1; + REGBAR_FROM_SYSBAR:bit1; + RD_EN :bit1; + ATC_TRANSLATED :bit1; + RESERVED0 :bit19; + end; + + TMPLL_BYPASSCLK_SEL=bitpacked record + RESERVED0 :bit8; + MPLL_CLKOUT_SEL:bit8; + RESERVED1 :bit16; + end; + + TMVP_CRC_RESULT_RED=bitpacked record + MVP_CRC_RED_RESULT:bit16; + RESERVED0 :bit16; + end; + + TOUTPUT_CSC_C11_C12=bitpacked record + OUTPUT_CSC_C11:bit16; + OUTPUT_CSC_C12:bit16; + end; + + TOUTPUT_CSC_C13_C14=bitpacked record + OUTPUT_CSC_C13:bit16; + OUTPUT_CSC_C14:bit16; + end; + + TOUTPUT_CSC_C21_C22=bitpacked record + OUTPUT_CSC_C21:bit16; + OUTPUT_CSC_C22:bit16; + end; + + TOUTPUT_CSC_C23_C24=bitpacked record + OUTPUT_CSC_C23:bit16; + OUTPUT_CSC_C24:bit16; + end; + + TOUTPUT_CSC_C31_C32=bitpacked record + OUTPUT_CSC_C31:bit16; + OUTPUT_CSC_C32:bit16; + end; + + TOUTPUT_CSC_C33_C34=bitpacked record + OUTPUT_CSC_C33:bit16; + OUTPUT_CSC_C34:bit16; + end; + + TOUTPUT_CSC_CONTROL=bitpacked record + OUTPUT_CSC_GRPH_MODE:bit3; + RESERVED0 :bit1; + OUTPUT_CSC_OVL_MODE :bit3; + RESERVED1 :bit25; + end; + TPA_CL_VPORT_XSCALE=bit32; TPA_CL_VPORT_YSCALE=bit32; @@ -7256,6 +31986,1204 @@ type RESERVED2 :bit10; end; + TPB0_PIF_LANE0_OVRD=bitpacked record + GANGMODE_OVRD_EN_0 :bit1; + FREQDIV_OVRD_EN_0 :bit1; + LINKSPEED_OVRD_EN_0 :bit1; + TWOSYMENABLE_OVRD_EN_0 :bit1; + TXPWR_OVRD_EN_0 :bit1; + TXPGENABLE_OVRD_EN_0 :bit1; + RXPWR_OVRD_EN_0 :bit1; + RXPGENABLE_OVRD_EN_0 :bit1; + ELECIDLEDETEN_OVRD_EN_0:bit1; + ENABLEFOM_OVRD_EN_0 :bit1; + REQUESTFOM_OVRD_EN_0 :bit1; + RESPONSEMODE_OVRD_EN_0 :bit1; + REQUESTTRK_OVRD_EN_0 :bit1; + REQUESTTRN_OVRD_EN_0 :bit1; + COEFFICIENTID_OVRD_EN_0:bit1; + COEFFICIENT_OVRD_EN_0 :bit1; + CDREN_OVRD_EN_0 :bit1; + CDREN_OVRD_VAL_0 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE1_OVRD=bitpacked record + GANGMODE_OVRD_EN_1 :bit1; + FREQDIV_OVRD_EN_1 :bit1; + LINKSPEED_OVRD_EN_1 :bit1; + TWOSYMENABLE_OVRD_EN_1 :bit1; + TXPWR_OVRD_EN_1 :bit1; + TXPGENABLE_OVRD_EN_1 :bit1; + RXPWR_OVRD_EN_1 :bit1; + RXPGENABLE_OVRD_EN_1 :bit1; + ELECIDLEDETEN_OVRD_EN_1:bit1; + ENABLEFOM_OVRD_EN_1 :bit1; + REQUESTFOM_OVRD_EN_1 :bit1; + RESPONSEMODE_OVRD_EN_1 :bit1; + REQUESTTRK_OVRD_EN_1 :bit1; + REQUESTTRN_OVRD_EN_1 :bit1; + COEFFICIENTID_OVRD_EN_1:bit1; + COEFFICIENT_OVRD_EN_1 :bit1; + CDREN_OVRD_EN_1 :bit1; + CDREN_OVRD_VAL_1 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE2_OVRD=bitpacked record + GANGMODE_OVRD_EN_2 :bit1; + FREQDIV_OVRD_EN_2 :bit1; + LINKSPEED_OVRD_EN_2 :bit1; + TWOSYMENABLE_OVRD_EN_2 :bit1; + TXPWR_OVRD_EN_2 :bit1; + TXPGENABLE_OVRD_EN_2 :bit1; + RXPWR_OVRD_EN_2 :bit1; + RXPGENABLE_OVRD_EN_2 :bit1; + ELECIDLEDETEN_OVRD_EN_2:bit1; + ENABLEFOM_OVRD_EN_2 :bit1; + REQUESTFOM_OVRD_EN_2 :bit1; + RESPONSEMODE_OVRD_EN_2 :bit1; + REQUESTTRK_OVRD_EN_2 :bit1; + REQUESTTRN_OVRD_EN_2 :bit1; + COEFFICIENTID_OVRD_EN_2:bit1; + COEFFICIENT_OVRD_EN_2 :bit1; + CDREN_OVRD_EN_2 :bit1; + CDREN_OVRD_VAL_2 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE3_OVRD=bitpacked record + GANGMODE_OVRD_EN_3 :bit1; + FREQDIV_OVRD_EN_3 :bit1; + LINKSPEED_OVRD_EN_3 :bit1; + TWOSYMENABLE_OVRD_EN_3 :bit1; + TXPWR_OVRD_EN_3 :bit1; + TXPGENABLE_OVRD_EN_3 :bit1; + RXPWR_OVRD_EN_3 :bit1; + RXPGENABLE_OVRD_EN_3 :bit1; + ELECIDLEDETEN_OVRD_EN_3:bit1; + ENABLEFOM_OVRD_EN_3 :bit1; + REQUESTFOM_OVRD_EN_3 :bit1; + RESPONSEMODE_OVRD_EN_3 :bit1; + REQUESTTRK_OVRD_EN_3 :bit1; + REQUESTTRN_OVRD_EN_3 :bit1; + COEFFICIENTID_OVRD_EN_3:bit1; + COEFFICIENT_OVRD_EN_3 :bit1; + CDREN_OVRD_EN_3 :bit1; + CDREN_OVRD_VAL_3 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE4_OVRD=bitpacked record + GANGMODE_OVRD_EN_4 :bit1; + FREQDIV_OVRD_EN_4 :bit1; + LINKSPEED_OVRD_EN_4 :bit1; + TWOSYMENABLE_OVRD_EN_4 :bit1; + TXPWR_OVRD_EN_4 :bit1; + TXPGENABLE_OVRD_EN_4 :bit1; + RXPWR_OVRD_EN_4 :bit1; + RXPGENABLE_OVRD_EN_4 :bit1; + ELECIDLEDETEN_OVRD_EN_4:bit1; + ENABLEFOM_OVRD_EN_4 :bit1; + REQUESTFOM_OVRD_EN_4 :bit1; + RESPONSEMODE_OVRD_EN_4 :bit1; + REQUESTTRK_OVRD_EN_4 :bit1; + REQUESTTRN_OVRD_EN_4 :bit1; + COEFFICIENTID_OVRD_EN_4:bit1; + COEFFICIENT_OVRD_EN_4 :bit1; + CDREN_OVRD_EN_4 :bit1; + CDREN_OVRD_VAL_4 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE5_OVRD=bitpacked record + GANGMODE_OVRD_EN_5 :bit1; + FREQDIV_OVRD_EN_5 :bit1; + LINKSPEED_OVRD_EN_5 :bit1; + TWOSYMENABLE_OVRD_EN_5 :bit1; + TXPWR_OVRD_EN_5 :bit1; + TXPGENABLE_OVRD_EN_5 :bit1; + RXPWR_OVRD_EN_5 :bit1; + RXPGENABLE_OVRD_EN_5 :bit1; + ELECIDLEDETEN_OVRD_EN_5:bit1; + ENABLEFOM_OVRD_EN_5 :bit1; + REQUESTFOM_OVRD_EN_5 :bit1; + RESPONSEMODE_OVRD_EN_5 :bit1; + REQUESTTRK_OVRD_EN_5 :bit1; + REQUESTTRN_OVRD_EN_5 :bit1; + COEFFICIENTID_OVRD_EN_5:bit1; + COEFFICIENT_OVRD_EN_5 :bit1; + CDREN_OVRD_EN_5 :bit1; + CDREN_OVRD_VAL_5 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE6_OVRD=bitpacked record + GANGMODE_OVRD_EN_6 :bit1; + FREQDIV_OVRD_EN_6 :bit1; + LINKSPEED_OVRD_EN_6 :bit1; + TWOSYMENABLE_OVRD_EN_6 :bit1; + TXPWR_OVRD_EN_6 :bit1; + TXPGENABLE_OVRD_EN_6 :bit1; + RXPWR_OVRD_EN_6 :bit1; + RXPGENABLE_OVRD_EN_6 :bit1; + ELECIDLEDETEN_OVRD_EN_6:bit1; + ENABLEFOM_OVRD_EN_6 :bit1; + REQUESTFOM_OVRD_EN_6 :bit1; + RESPONSEMODE_OVRD_EN_6 :bit1; + REQUESTTRK_OVRD_EN_6 :bit1; + REQUESTTRN_OVRD_EN_6 :bit1; + COEFFICIENTID_OVRD_EN_6:bit1; + COEFFICIENT_OVRD_EN_6 :bit1; + CDREN_OVRD_EN_6 :bit1; + CDREN_OVRD_VAL_6 :bit1; + RESERVED0 :bit14; + end; + + TPB0_PIF_LANE7_OVRD=bitpacked record + GANGMODE_OVRD_EN_7 :bit1; + FREQDIV_OVRD_EN_7 :bit1; + LINKSPEED_OVRD_EN_7 :bit1; + TWOSYMENABLE_OVRD_EN_7 :bit1; + TXPWR_OVRD_EN_7 :bit1; + TXPGENABLE_OVRD_EN_7 :bit1; + RXPWR_OVRD_EN_7 :bit1; + RXPGENABLE_OVRD_EN_7 :bit1; + ELECIDLEDETEN_OVRD_EN_7:bit1; + ENABLEFOM_OVRD_EN_7 :bit1; + REQUESTFOM_OVRD_EN_7 :bit1; + RESPONSEMODE_OVRD_EN_7 :bit1; + REQUESTTRK_OVRD_EN_7 :bit1; + REQUESTTRN_OVRD_EN_7 :bit1; + COEFFICIENTID_OVRD_EN_7:bit1; + COEFFICIENT_OVRD_EN_7 :bit1; + CDREN_OVRD_EN_7 :bit1; + CDREN_OVRD_VAL_7 :bit1; + RESERVED0 :bit14; + end; + + TPB0_STRAP_GLB_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_QUICK_SIM_START :bit1; + STRAP_DFT_RXBSCAN_EN_VAL :bit1; + STRAP_DFT_CALIB_BYPASS :bit1; + STRAP_FORCE_LC_PLL_ON :bit1; + STRAP_CFG_IDLEDET_TH :bit2; + STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL :bit5; + STRAP_RX_CFG_OVR_PWRSF :bit1; + STRAP_RX_TRK_MODE_0_ :bit1; + STRAP_PWRGOOD_OVRD :bit1; + STRAP_DBG_RXDLL_VREG_REF_SEL :bit1; + STRAP_PLL_CFG_LC_VCO_TUNE :bit4; + STRAP_DBG_RXRDATA_GATING_DISABLE:bit1; + STRAP_DBG_RXPI_OFFSET_BYP_VAL :bit4; + RESERVED1 :bit7; + end; + + TPB0_STRAP_GLB_REG1=bitpacked record + RESERVED0 :bit1; + STRAP_RX_ADAPT_RST_MODE :bit2; + STRAP_RX_L0_ENTRY_MODE :bit2; + STRAP_RX_EI_FILTER :bit2; + STRAP_RX_ADAPT_RST_SUB_ENTRY:bit1; + STRAP_RX_PS0_RDY_GEN_MODE :bit2; + STRAP_RX_DLL_RESET_IN_SPDCHG:bit1; + STRAP_RX_ADAPT_TIME_OUT :bit2; + RESERVED1 :bit1; + RESERVED2 :bit18; + end; + + TPB0_STRAP_GLB_REG2=bitpacked record + RESERVED0 :bit2; + STRAP_BPHYC_PLL_RAMP_UP_TIME:bit3; + STRAP_IMPCAL_SETTLE_TIME :bit2; + STRAP_BG_SETTLE_TIME :bit2; + STRAP_TX_CMDET_TIME :bit2; + STRAP_TX_STARTUP_TIME :bit2; + RESERVED1 :bit15; + STRAP_B_PCB_DIS0 :bit1; + STRAP_B_PCB_DIS1 :bit1; + STRAP_B_PCB_DRV_STR :bit2; + end; + + TPB0_STRAP_PIN_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_DEEMPH_EN :bit1; + STRAP_TX_FULL_SWING:bit1; + RESERVED1 :bit29; + end; + + TPB0_STRAP_PLL_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_PLL_CFG_LC_BW_CNTRL :bit3; + STRAP_PLL_CFG_LC_LF_CNTRL :bit9; + STRAP_TX_RXDET_X1_SSF :bit1; + RESERVED1 :bit1; + STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS:bit1; + STRAP_PLL_CFG_RO_BW_CNTRL :bit8; + STRAP_PLL_STRAP_SEL :bit1; + RESERVED2 :bit7; + end; + + TPB1_PIF_LANE0_OVRD=bitpacked record + GANGMODE_OVRD_EN_0 :bit1; + FREQDIV_OVRD_EN_0 :bit1; + LINKSPEED_OVRD_EN_0 :bit1; + TWOSYMENABLE_OVRD_EN_0 :bit1; + TXPWR_OVRD_EN_0 :bit1; + TXPGENABLE_OVRD_EN_0 :bit1; + RXPWR_OVRD_EN_0 :bit1; + RXPGENABLE_OVRD_EN_0 :bit1; + ELECIDLEDETEN_OVRD_EN_0:bit1; + ENABLEFOM_OVRD_EN_0 :bit1; + REQUESTFOM_OVRD_EN_0 :bit1; + RESPONSEMODE_OVRD_EN_0 :bit1; + REQUESTTRK_OVRD_EN_0 :bit1; + REQUESTTRN_OVRD_EN_0 :bit1; + COEFFICIENTID_OVRD_EN_0:bit1; + COEFFICIENT_OVRD_EN_0 :bit1; + CDREN_OVRD_EN_0 :bit1; + CDREN_OVRD_VAL_0 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE1_OVRD=bitpacked record + GANGMODE_OVRD_EN_1 :bit1; + FREQDIV_OVRD_EN_1 :bit1; + LINKSPEED_OVRD_EN_1 :bit1; + TWOSYMENABLE_OVRD_EN_1 :bit1; + TXPWR_OVRD_EN_1 :bit1; + TXPGENABLE_OVRD_EN_1 :bit1; + RXPWR_OVRD_EN_1 :bit1; + RXPGENABLE_OVRD_EN_1 :bit1; + ELECIDLEDETEN_OVRD_EN_1:bit1; + ENABLEFOM_OVRD_EN_1 :bit1; + REQUESTFOM_OVRD_EN_1 :bit1; + RESPONSEMODE_OVRD_EN_1 :bit1; + REQUESTTRK_OVRD_EN_1 :bit1; + REQUESTTRN_OVRD_EN_1 :bit1; + COEFFICIENTID_OVRD_EN_1:bit1; + COEFFICIENT_OVRD_EN_1 :bit1; + CDREN_OVRD_EN_1 :bit1; + CDREN_OVRD_VAL_1 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE2_OVRD=bitpacked record + GANGMODE_OVRD_EN_2 :bit1; + FREQDIV_OVRD_EN_2 :bit1; + LINKSPEED_OVRD_EN_2 :bit1; + TWOSYMENABLE_OVRD_EN_2 :bit1; + TXPWR_OVRD_EN_2 :bit1; + TXPGENABLE_OVRD_EN_2 :bit1; + RXPWR_OVRD_EN_2 :bit1; + RXPGENABLE_OVRD_EN_2 :bit1; + ELECIDLEDETEN_OVRD_EN_2:bit1; + ENABLEFOM_OVRD_EN_2 :bit1; + REQUESTFOM_OVRD_EN_2 :bit1; + RESPONSEMODE_OVRD_EN_2 :bit1; + REQUESTTRK_OVRD_EN_2 :bit1; + REQUESTTRN_OVRD_EN_2 :bit1; + COEFFICIENTID_OVRD_EN_2:bit1; + COEFFICIENT_OVRD_EN_2 :bit1; + CDREN_OVRD_EN_2 :bit1; + CDREN_OVRD_VAL_2 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE3_OVRD=bitpacked record + GANGMODE_OVRD_EN_3 :bit1; + FREQDIV_OVRD_EN_3 :bit1; + LINKSPEED_OVRD_EN_3 :bit1; + TWOSYMENABLE_OVRD_EN_3 :bit1; + TXPWR_OVRD_EN_3 :bit1; + TXPGENABLE_OVRD_EN_3 :bit1; + RXPWR_OVRD_EN_3 :bit1; + RXPGENABLE_OVRD_EN_3 :bit1; + ELECIDLEDETEN_OVRD_EN_3:bit1; + ENABLEFOM_OVRD_EN_3 :bit1; + REQUESTFOM_OVRD_EN_3 :bit1; + RESPONSEMODE_OVRD_EN_3 :bit1; + REQUESTTRK_OVRD_EN_3 :bit1; + REQUESTTRN_OVRD_EN_3 :bit1; + COEFFICIENTID_OVRD_EN_3:bit1; + COEFFICIENT_OVRD_EN_3 :bit1; + CDREN_OVRD_EN_3 :bit1; + CDREN_OVRD_VAL_3 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE4_OVRD=bitpacked record + GANGMODE_OVRD_EN_4 :bit1; + FREQDIV_OVRD_EN_4 :bit1; + LINKSPEED_OVRD_EN_4 :bit1; + TWOSYMENABLE_OVRD_EN_4 :bit1; + TXPWR_OVRD_EN_4 :bit1; + TXPGENABLE_OVRD_EN_4 :bit1; + RXPWR_OVRD_EN_4 :bit1; + RXPGENABLE_OVRD_EN_4 :bit1; + ELECIDLEDETEN_OVRD_EN_4:bit1; + ENABLEFOM_OVRD_EN_4 :bit1; + REQUESTFOM_OVRD_EN_4 :bit1; + RESPONSEMODE_OVRD_EN_4 :bit1; + REQUESTTRK_OVRD_EN_4 :bit1; + REQUESTTRN_OVRD_EN_4 :bit1; + COEFFICIENTID_OVRD_EN_4:bit1; + COEFFICIENT_OVRD_EN_4 :bit1; + CDREN_OVRD_EN_4 :bit1; + CDREN_OVRD_VAL_4 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE5_OVRD=bitpacked record + GANGMODE_OVRD_EN_5 :bit1; + FREQDIV_OVRD_EN_5 :bit1; + LINKSPEED_OVRD_EN_5 :bit1; + TWOSYMENABLE_OVRD_EN_5 :bit1; + TXPWR_OVRD_EN_5 :bit1; + TXPGENABLE_OVRD_EN_5 :bit1; + RXPWR_OVRD_EN_5 :bit1; + RXPGENABLE_OVRD_EN_5 :bit1; + ELECIDLEDETEN_OVRD_EN_5:bit1; + ENABLEFOM_OVRD_EN_5 :bit1; + REQUESTFOM_OVRD_EN_5 :bit1; + RESPONSEMODE_OVRD_EN_5 :bit1; + REQUESTTRK_OVRD_EN_5 :bit1; + REQUESTTRN_OVRD_EN_5 :bit1; + COEFFICIENTID_OVRD_EN_5:bit1; + COEFFICIENT_OVRD_EN_5 :bit1; + CDREN_OVRD_EN_5 :bit1; + CDREN_OVRD_VAL_5 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE6_OVRD=bitpacked record + GANGMODE_OVRD_EN_6 :bit1; + FREQDIV_OVRD_EN_6 :bit1; + LINKSPEED_OVRD_EN_6 :bit1; + TWOSYMENABLE_OVRD_EN_6 :bit1; + TXPWR_OVRD_EN_6 :bit1; + TXPGENABLE_OVRD_EN_6 :bit1; + RXPWR_OVRD_EN_6 :bit1; + RXPGENABLE_OVRD_EN_6 :bit1; + ELECIDLEDETEN_OVRD_EN_6:bit1; + ENABLEFOM_OVRD_EN_6 :bit1; + REQUESTFOM_OVRD_EN_6 :bit1; + RESPONSEMODE_OVRD_EN_6 :bit1; + REQUESTTRK_OVRD_EN_6 :bit1; + REQUESTTRN_OVRD_EN_6 :bit1; + COEFFICIENTID_OVRD_EN_6:bit1; + COEFFICIENT_OVRD_EN_6 :bit1; + CDREN_OVRD_EN_6 :bit1; + CDREN_OVRD_VAL_6 :bit1; + RESERVED0 :bit14; + end; + + TPB1_PIF_LANE7_OVRD=bitpacked record + GANGMODE_OVRD_EN_7 :bit1; + FREQDIV_OVRD_EN_7 :bit1; + LINKSPEED_OVRD_EN_7 :bit1; + TWOSYMENABLE_OVRD_EN_7 :bit1; + TXPWR_OVRD_EN_7 :bit1; + TXPGENABLE_OVRD_EN_7 :bit1; + RXPWR_OVRD_EN_7 :bit1; + RXPGENABLE_OVRD_EN_7 :bit1; + ELECIDLEDETEN_OVRD_EN_7:bit1; + ENABLEFOM_OVRD_EN_7 :bit1; + REQUESTFOM_OVRD_EN_7 :bit1; + RESPONSEMODE_OVRD_EN_7 :bit1; + REQUESTTRK_OVRD_EN_7 :bit1; + REQUESTTRN_OVRD_EN_7 :bit1; + COEFFICIENTID_OVRD_EN_7:bit1; + COEFFICIENT_OVRD_EN_7 :bit1; + CDREN_OVRD_EN_7 :bit1; + CDREN_OVRD_VAL_7 :bit1; + RESERVED0 :bit14; + end; + + TPB1_STRAP_GLB_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_QUICK_SIM_START :bit1; + STRAP_DFT_RXBSCAN_EN_VAL :bit1; + STRAP_DFT_CALIB_BYPASS :bit1; + STRAP_FORCE_LC_PLL_ON :bit1; + STRAP_CFG_IDLEDET_TH :bit2; + STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL :bit5; + STRAP_RX_CFG_OVR_PWRSF :bit1; + STRAP_RX_TRK_MODE_0_ :bit1; + STRAP_PWRGOOD_OVRD :bit1; + STRAP_DBG_RXDLL_VREG_REF_SEL :bit1; + STRAP_PLL_CFG_LC_VCO_TUNE :bit4; + STRAP_DBG_RXRDATA_GATING_DISABLE:bit1; + STRAP_DBG_RXPI_OFFSET_BYP_VAL :bit4; + RESERVED1 :bit7; + end; + + TPB1_STRAP_GLB_REG1=bitpacked record + RESERVED0 :bit1; + STRAP_RX_ADAPT_RST_MODE :bit2; + STRAP_RX_L0_ENTRY_MODE :bit2; + STRAP_RX_EI_FILTER :bit2; + STRAP_RX_ADAPT_RST_SUB_ENTRY:bit1; + STRAP_RX_PS0_RDY_GEN_MODE :bit2; + STRAP_RX_DLL_RESET_IN_SPDCHG:bit1; + STRAP_RX_ADAPT_TIME_OUT :bit2; + RESERVED1 :bit1; + RESERVED2 :bit18; + end; + + TPB1_STRAP_GLB_REG2=bitpacked record + RESERVED0 :bit2; + STRAP_BPHYC_PLL_RAMP_UP_TIME:bit3; + STRAP_IMPCAL_SETTLE_TIME :bit2; + STRAP_BG_SETTLE_TIME :bit2; + STRAP_TX_CMDET_TIME :bit2; + STRAP_TX_STARTUP_TIME :bit2; + RESERVED1 :bit15; + STRAP_B_PCB_DIS0 :bit1; + STRAP_B_PCB_DIS1 :bit1; + STRAP_B_PCB_DRV_STR :bit2; + end; + + TPB1_STRAP_PIN_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_TX_DEEMPH_EN :bit1; + STRAP_TX_FULL_SWING:bit1; + RESERVED1 :bit29; + end; + + TPB1_STRAP_PLL_REG0=bitpacked record + RESERVED0 :bit1; + STRAP_PLL_CFG_LC_BW_CNTRL :bit3; + STRAP_PLL_CFG_LC_LF_CNTRL :bit9; + STRAP_TX_RXDET_X1_SSF :bit1; + RESERVED1 :bit1; + STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS:bit1; + STRAP_PLL_CFG_RO_BW_CNTRL :bit8; + STRAP_PLL_STRAP_SEL :bit1; + RESERVED2 :bit7; + end; + + TPCIEP_BCH_ECC_CNTL=bitpacked record + STRAP_BCH_ECC_EN :bit1; + RESERVED0 :bit7; + BCH_ECC_ERROR_THRESHOLD:bit8; + BCH_ECC_ERROR_STATUS :bit16; + end; + + TPCIE_CORR_ERR_MASK=bitpacked record + RCV_ERR_MASK :bit1; + RESERVED0 :bit5; + BAD_TLP_MASK :bit1; + BAD_DLLP_MASK :bit1; + REPLAY_NUM_ROLLOVER_MASK :bit1; + RESERVED1 :bit3; + REPLAY_TIMER_TIMEOUT_MASK :bit1; + ADVISORY_NONFATAL_ERR_MASK:bit1; + CORR_INT_ERR_MASK :bit1; + HDR_LOG_OVFL_MASK :bit1; + RESERVED2 :bit16; + end; + + TPCIE_LC_N_FTS_CNTL=bitpacked record + LC_XMIT_N_FTS :bit8; + LC_XMIT_N_FTS_OVERRIDE_EN :bit1; + LC_XMIT_FTS_BEFORE_RECOVERY:bit1; + RESERVED0 :bit6; + LC_XMIT_N_FTS_LIMIT :bit8; + LC_N_FTS :bit8; + end; + + TPCIE_LC_SPEED_CNTL=bitpacked record + LC_GEN2_EN_STRAP :bit1; + LC_GEN3_EN_STRAP :bit1; + LC_TARGET_LINK_SPEED_OVERRIDE_EN :bit1; + LC_TARGET_LINK_SPEED_OVERRIDE :bit2; + LC_FORCE_EN_SW_SPEED_CHANGE :bit1; + LC_FORCE_DIS_SW_SPEED_CHANGE :bit1; + LC_FORCE_EN_HW_SPEED_CHANGE :bit1; + LC_FORCE_DIS_HW_SPEED_CHANGE :bit1; + LC_INITIATE_LINK_SPEED_CHANGE :bit1; + LC_SPEED_CHANGE_ATTEMPTS_ALLOWED :bit2; + LC_SPEED_CHANGE_ATTEMPT_FAILED :bit1; + LC_CURRENT_DATA_RATE :bit2; + LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS:bit1; + LC_CLR_FAILED_SPD_CHANGE_CNT :bit1; + LC_1_OR_MORE_TS2_SPEED_ARC_EN :bit1; + LC_OTHER_SIDE_EVER_SENT_GEN2 :bit1; + LC_OTHER_SIDE_SUPPORTS_GEN2 :bit1; + LC_OTHER_SIDE_EVER_SENT_GEN3 :bit1; + LC_OTHER_SIDE_SUPPORTS_GEN3 :bit1; + LC_AUTO_RECOVERY_DIS :bit1; + LC_SPEED_CHANGE_STATUS :bit1; + LC_DATA_RATE_ADVERTISED :bit2; + LC_CHECK_DATA_RATE :bit1; + LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN :bit1; + LC_INIT_SPEED_NEG_IN_L0s_EN :bit1; + LC_INIT_SPEED_NEG_IN_L1_EN :bit1; + LC_DONT_CHECK_EQTS_IN_RCFG :bit1; + LC_DELAY_COEFF_UPDATE_DIS :bit1; + end; + + TPCIE_MC_BLOCK_ALL0=bit32; + + TPCIE_MC_BLOCK_ALL1=bit32; + + TPCIE_PAGE_REQ_CNTL=bitpacked record + PRI_ENABLE:bit1; + PRI_RESET :bit1; + RESERVED0 :bit30; + end; + + TPCIE_PRBS_ERRCNT_0=bit32; + + TPCIE_PRBS_ERRCNT_1=bit32; + + TPCIE_PRBS_ERRCNT_2=bit32; + + TPCIE_PRBS_ERRCNT_3=bit32; + + TPCIE_PRBS_ERRCNT_4=bit32; + + TPCIE_PRBS_ERRCNT_5=bit32; + + TPCIE_PRBS_ERRCNT_6=bit32; + + TPCIE_PRBS_ERRCNT_7=bit32; + + TPCIE_PRBS_ERRCNT_8=bit32; + + TPCIE_PRBS_ERRCNT_9=bit32; + + TPCIE_P_MISC_STATUS=bitpacked record + P_DESKEW_ERR :bit8; + RESERVED0 :bit8; + P_SYMUNLOCK_ERR:bit16; + end; + + TPCIE_SRIOV_CONTROL=bitpacked record + SRIOV_VF_ENABLE :bit1; + SRIOV_VF_MIGRATION_ENABLE :bit1; + SRIOV_VF_MIGRATION_INTR_ENABLE:bit1; + SRIOV_VF_MSE :bit1; + SRIOV_ARI_CAP_HIERARCHY :bit1; + RESERVED0 :bit27; + end; + + TPCIE_SRIOV_NUM_VFS=bitpacked record + SRIOV_NUM_VFS:bit16; + RESERVED0 :bit16; + end; + + TPCIE_TPH_REQR_CNTL=bitpacked record + TPH_REQR_ST_MODE_SEL:bit3; + RESERVED0 :bit5; + TPH_REQR_EN :bit2; + RESERVED1 :bit22; + end; + + TPCIE_WRAP_DTM_MISC=bitpacked record + DTM_BULKPHY_FREQDIV_OVERRIDE:bit1; + RESERVED0 :bit31; + end; + + TPCIE_WRAP_PIF_MISC=bitpacked record + DTM_PIF_DELAY_FI:bit3; + RESERVED0 :bit1; + DTM_PIF_DELAY_DI:bit3; + DTM_PIF_ATSEL_FI:bit1; + DTM_PIF_ATSEL_DI:bit1; + RESERVED1 :bit23; + end; + + TPCIE_WRAP_SCRATCH1=bit32; + + TPCIE_WRAP_SCRATCH2=bit32; + + TPEER0_FB_OFFSET_HI=bitpacked record + PEER0_FB_OFFSET_HI:bit20; + RESERVED0 :bit12; + end; + + TPEER0_FB_OFFSET_LO=bitpacked record + PEER0_FB_OFFSET_LO:bit20; + RESERVED0 :bit11; + PEER0_FB_EN :bit1; + end; + + TPEER1_FB_OFFSET_HI=bitpacked record + PEER1_FB_OFFSET_HI:bit20; + RESERVED0 :bit12; + end; + + TPEER1_FB_OFFSET_LO=bitpacked record + PEER1_FB_OFFSET_LO:bit20; + RESERVED0 :bit11; + PEER1_FB_EN :bit1; + end; + + TPEER2_FB_OFFSET_HI=bitpacked record + PEER2_FB_OFFSET_HI:bit20; + RESERVED0 :bit12; + end; + + TPEER2_FB_OFFSET_LO=bitpacked record + PEER2_FB_OFFSET_LO:bit20; + RESERVED0 :bit11; + PEER2_FB_EN :bit1; + end; + + TPEER3_FB_OFFSET_HI=bitpacked record + PEER3_FB_OFFSET_HI:bit20; + RESERVED0 :bit12; + end; + + TPEER3_FB_OFFSET_LO=bitpacked record + PEER3_FB_OFFSET_LO:bit20; + RESERVED0 :bit11; + PEER3_FB_EN :bit1; + end; + + TPERFMON_CVALUE_LOW=bit32; + + TPIPE0_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE1_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE2_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE3_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE4_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE5_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE6_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TPIPE7_MAX_REQUESTS=bitpacked record + MAX_REQUESTS:bit10; + RESERVED0 :bit22; + end; + + TRAS_BCI_SIGNATURE0=bit32; + + TRAS_BCI_SIGNATURE1=bit32; + + TRAS_SIGNATURE_MASK=bit32; + + TRAS_SPI_SIGNATURE0=bit32; + + TRAS_SPI_SIGNATURE1=bit32; + + TRAS_VGT_SIGNATURE0=bit32; + + TRBBMIF_STATUS_FLAG=bitpacked record + RBBMIF_STATE :bit3; + RBBMIF_ACK_TIMEOUT :bit1; + RBBMIF_READ_TIMEOUT:bit1; + RBBMIF_FIFO_EMPTY :bit1; + RBBMIF_FIFO_FULL :bit1; + RESERVED0 :bit25; + end; + + TRBBMIF_TIMEOUT_DIS=bitpacked record + CLIENT0_TIMEOUT_DIS :bit1; + CLIENT1_TIMEOUT_DIS :bit1; + CLIENT2_TIMEOUT_DIS :bit1; + CLIENT3_TIMEOUT_DIS :bit1; + CLIENT4_TIMEOUT_DIS :bit1; + CLIENT5_TIMEOUT_DIS :bit1; + CLIENT6_TIMEOUT_DIS :bit1; + CLIENT7_TIMEOUT_DIS :bit1; + CLIENT8_TIMEOUT_DIS :bit1; + CLIENT9_TIMEOUT_DIS :bit1; + CLIENT10_TIMEOUT_DIS:bit1; + CLIENT11_TIMEOUT_DIS:bit1; + CLIENT12_TIMEOUT_DIS:bit1; + CLIENT13_TIMEOUT_DIS:bit1; + CLIENT14_TIMEOUT_DIS:bit1; + RESERVED0 :bit17; + end; + + TRCU_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TRIRB_WRITE_POINTER=bitpacked record + RIRB_WRITE_POINTER :bit8; + RESERVED0 :bit7; + RIRB_WRITE_POINTER_RESET:bit1; + RESERVED1 :bit16; + end; + + TRLC_CGCG_CGLS_CTRL=bitpacked record + CGCG_EN :bit1; + CGLS_EN :bit1; + CGLS_REP_COMPANSAT_DELAY:bit6; + CGCG_GFX_IDLE_THRESHOLD :bit19; + CGCG_CONTROLLER :bit1; + CGCG_REG_CTRL :bit1; + SLEEP_MODE :bit2; + SIM_SILICON_EN :bit1; + end; + + TRLC_CGCG_RAMP_CTRL=bitpacked record + DOWN_DIV_START_UNIT:bit4; + DOWN_DIV_STEP_UNIT :bit4; + UP_DIV_START_UNIT :bit4; + UP_DIV_STEP_UNIT :bit4; + STEP_DELAY_CNT :bit12; + STEP_DELAY_UNIT :bit4; + end; + + TRLC_DYN_PG_REQUEST=bit32; + + TRLC_GPM_UCODE_ADDR=bitpacked record + UCODE_ADDR:bit12; + RESERVED0 :bit20; + end; + + TRLC_GPM_UCODE_DATA=bit32; + + TRLC_RLCV_SAFE_MODE=bitpacked record + CMD :bit1; + MESSAGE :bit4; + RESERVED1:bit3; + RESPONSE :bit4; + RESERVED :bit20; + end; + + TRLC_SERDES_WR_CTRL=bitpacked record + BPM_ADDR :bit8; + POWER_DOWN :bit1; + POWER_UP :bit1; + P1_SELECT :bit1; + P2_SELECT :bit1; + WRITE_COMMAND:bit1; + READ_COMMAND :bit1; + RDDATA_RESET :bit1; + SHORT_FORMAT :bit1; + BPM_DATA :bit10; + SRBM_OVERRIDE:bit1; + RSVD_BPM_ADDR:bit1; + REG_ADDR :bit4; + end; + + TRLC_SERDES_WR_DATA=bit32; + + TRLC_SOFT_RESET_GPU=bitpacked record + SOFT_RESET_GPU:bit1; + RESERVED :bit31; + end; + + TRLC_SPM_INT_STATUS=bitpacked record + RLC_SPM_INT_STATUS:bit1; + RESERVED0 :bit31; + end; + + TRLC_SPM_RING_RDPTR=bit32; + + TSCLV_VIEWPORT_SIZE=bitpacked record + VIEWPORT_HEIGHT:bit13; + RESERVED0 :bit3; + VIEWPORT_WIDTH :bit13; + RESERVED1 :bit3; + end; + + TSCL_BYPASS_CONTROL=bitpacked record + SCL_BYPASS_MODE:bit2; + RESERVED0 :bit30; + end; + + TSDMA0_BA_THRESHOLD=bitpacked record + READ_THRES :bit10; + RESERVED0 :bit6; + WRITE_THRES:bit10; + RESERVED1 :bit6; + end; + + TSDMA0_CHICKEN_BITS=bitpacked record + COPY_EFFICIENCY_ENABLE :bit1; + STALL_ON_TRANS_FULL_ENABLE :bit1; + STALL_ON_NO_FREE_DATA_BUFFER_ENABLE:bit1; + RESERVED0 :bit13; + COPY_OVERLAP_ENABLE :bit1; + RESERVED1 :bit3; + SRBM_POLL_RETRYING :bit1; + RESERVED2 :bit2; + CG_STATUS_OUTPUT :bit1; + RESERVED3 :bit2; + CE_AFIFO_WATERMARK :bit2; + CE_DFIFO_WATERMARK :bit2; + CE_LFIFO_WATERMARK :bit2; + end; + + TSDMA0_GFX_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA0_PERFMON_CNTL=bitpacked record + PERF_ENABLE0:bit1; + PERF_CLEAR0 :bit1; + PERF_SEL0 :bit6; + PERF_ENABLE1:bit1; + PERF_CLEAR1 :bit1; + PERF_SEL1 :bit6; + RESERVED0 :bit16; + end; + + TSDMA0_RLC0_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA0_RLC0_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_RLC0_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA0_RLC0_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA0_RLC0_RB_BASE=bit32; + + TSDMA0_RLC0_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA0_RLC0_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_RLC0_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_RLC1_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA0_RLC1_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_RLC1_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA0_RLC1_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA0_RLC1_RB_BASE=bit32; + + TSDMA0_RLC1_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA0_RLC1_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_RLC1_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_BA_THRESHOLD=bitpacked record + READ_THRES :bit10; + RESERVED0 :bit6; + WRITE_THRES:bit10; + RESERVED1 :bit6; + end; + + TSDMA1_CHICKEN_BITS=bitpacked record + COPY_EFFICIENCY_ENABLE :bit1; + STALL_ON_TRANS_FULL_ENABLE :bit1; + STALL_ON_NO_FREE_DATA_BUFFER_ENABLE:bit1; + RESERVED0 :bit13; + COPY_OVERLAP_ENABLE :bit1; + RESERVED1 :bit3; + SRBM_POLL_RETRYING :bit1; + RESERVED2 :bit2; + CG_STATUS_OUTPUT :bit1; + RESERVED3 :bit2; + CE_AFIFO_WATERMARK :bit2; + CE_DFIFO_WATERMARK :bit2; + CE_LFIFO_WATERMARK :bit2; + end; + + TSDMA1_GFX_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA1_PERFMON_CNTL=bitpacked record + PERF_ENABLE0:bit1; + PERF_CLEAR0 :bit1; + PERF_SEL0 :bit6; + PERF_ENABLE1:bit1; + PERF_CLEAR1 :bit1; + PERF_SEL1 :bit6; + RESERVED0 :bit16; + end; + + TSDMA1_RLC0_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA1_RLC0_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_RLC0_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA1_RLC0_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA1_RLC0_RB_BASE=bit32; + + TSDMA1_RLC0_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA1_RLC0_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_RLC0_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_RLC1_IB_CNTL=bitpacked record + IB_ENABLE :bit1; + RESERVED0 :bit3; + IB_SWAP_ENABLE :bit1; + RESERVED1 :bit3; + SWITCH_INSIDE_IB:bit1; + RESERVED2 :bit7; + CMD_VMID :bit4; + RESERVED3 :bit11; + RESERVED4 :bit1; + end; + + TSDMA1_RLC1_IB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_RLC1_IB_SIZE=bitpacked record + SIZE :bit20; + RESERVED0:bit12; + end; + + TSDMA1_RLC1_PREEMPT=bitpacked record + IB_PREEMPT:bit1; + RESERVED0 :bit31; + end; + + TSDMA1_RLC1_RB_BASE=bit32; + + TSDMA1_RLC1_RB_CNTL=bitpacked record + RB_ENABLE :bit1; + RB_SIZE :bit5; + RESERVED0 :bit3; + RB_SWAP_ENABLE :bit1; + RESERVED1 :bit2; + RPTR_WRITEBACK_ENABLE :bit1; + RPTR_WRITEBACK_SWAP_ENABLE:bit1; + RESERVED2 :bit2; + RPTR_WRITEBACK_TIMER :bit5; + RESERVED3 :bit2; + RB_PRIV :bit1; + RB_VMID :bit4; + RESERVED4 :bit4; + end; + + TSDMA1_RLC1_RB_RPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_RLC1_RB_WPTR=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSEM_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TSINK_DESCRIPTION10=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION11=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION12=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION13=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION14=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION15=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION16=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSINK_DESCRIPTION17=bitpacked record + DESCRIPTION:bit8; + RESERVED0 :bit24; + end; + + TSLAVE_COMM_CMD_REG=bitpacked record + SLAVE_COMM_CMD_REG_BYTE0:bit8; + SLAVE_COMM_CMD_REG_BYTE1:bit8; + SLAVE_COMM_CMD_REG_BYTE2:bit8; + SLAVE_COMM_CMD_REG_BYTE3:bit8; + end; + + TSNAPSHOT_V_COUNTER=bitpacked record + RESERVED0:bit14; + RESERVED1:bit18; + end; + TSPI_GDBG_TRAP_MASK=bitpacked record EXCP_EN :bit9; REPLACE :bit1; @@ -7273,6 +33201,23 @@ type RESERVED0 :bit20; end; + TSQ_DEBUG_STS_LOCAL=bitpacked record + BUSY :bit1; + RESERVED0 :bit3; + WAVE_LEVEL:bit6; + RESERVED1 :bit22; + end; + + TSQ_M0_GPR_IDX_WORD=bitpacked record + INDEX :bit8; + RESERVED0:bit4; + VSRC0_REL:bit1; + VSRC1_REL:bit1; + VSRC2_REL:bit1; + VDST_REL :bit1; + RESERVED1:bit16; + end; + TSQ_PERFCOUNTER0_HI=bit32; TSQ_PERFCOUNTER0_LO=bit32; @@ -7313,6 +33258,135 @@ type TSQ_PERFCOUNTER9_LO=bit32; + TSQ_POWER_THROTTLE2=bitpacked record + MAX_POWER_DELTA :bit14; + RESERVED0 :bit2; + SHORT_TERM_INTERVAL_SIZE:bit10; + RESERVED1 :bit1; + LONG_TERM_INTERVAL_RATIO:bit4; + USE_REF_CLOCK :bit1; + end; + + TSQ_RANDOM_WAVE_PRI=bitpacked record + RET :bit7; + RUI :bit3; + RNG :bit11; + RESERVED0:bit11; + end; + + TSQ_VOP3_0_SDST_ENC=bitpacked record + VDST :bit8; + SDST :bit7; + CLAMP :bit1; + OP :bit10; + ENCODING:bit6; + end; + + TSRBM_CHIP_REVISION=bitpacked record + CHIP_REVISION:bit8; + RESERVED0 :bit24; + end; + + TSRBM_GFX_CNTL_DATA=bitpacked record + PIPEID :bit2; + MEID :bit2; + VMID :bit4; + QUEUEID :bit3; + RESERVED0:bit21; + end; + + TSRBM_MC_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSWRST_EP_COMMAND_0=bitpacked record + EP_CFG_RESET_ONLY:bit1; + EP_SOFT_RESET :bit1; + EP_DRV_RESET :bit1; + RESERVED0 :bit5; + EP_HOT_RESET :bit1; + EP_LNKDWN_RESET :bit1; + EP_LNKDIS_RESET :bit1; + RESERVED1 :bit5; + EP_FLR0_RESET :bit1; + EP_FLR1_RESET :bit1; + EP_FLR2_RESET :bit1; + RESERVED2 :bit13; + end; + + TSWRST_EP_CONTROL_0=bitpacked record + EP_CFG_RESET_ONLY_EN :bit1; + EP_SOFT_RESET_EN :bit1; + EP_DRV_RESET_EN :bit1; + RESERVED0 :bit5; + EP_HOT_RESET_EN :bit1; + EP_LNKDWN_RESET_EN :bit1; + EP_LNKDIS_RESET_EN :bit1; + RESERVED1 :bit5; + EP_FLR0_RESET_EN :bit1; + EP_FLR1_RESET_EN :bit1; + EP_FLR2_RESET_EN :bit1; + EP_CFG_WR_RESET_EN :bit1; + EP_FLR_DISABLE_CFG_RST:bit4; + RESERVED2 :bit8; + end; + + TSXIFCCG_DEBUG_REG0=bitpacked record + position_address :bit6; + point_address :bit3; + sx_pending_rd_state_var_indx:bit3; + sx_pending_rd_req_mask :bit4; + sx_pending_rd_pci :bit10; + sx_pending_rd_aux_sel :bit2; + sx_pending_rd_sp_id :bit2; + sx_pending_rd_aux_inc :bit1; + sx_pending_rd_advance :bit1; + end; + + TSXIFCCG_DEBUG_REG1=bitpacked record + available_positions :bit7; + sx_receive_indx :bit3; + sx_pending_fifo_contents :bit5; + statevar_bits_vs_out_misc_vec_ena:bit1; + statevar_bits_disable_sp :bit4; + aux_sel :bit2; + sx_to_pa_empty_1 :bit1; + sx_to_pa_empty_0 :bit1; + pasx_req_cnt_1 :bit4; + pasx_req_cnt_0 :bit4; + end; + + TSXIFCCG_DEBUG_REG2=bitpacked record + param_cache_base :bit7; + sx_aux :bit2; + sx_request_indx :bit6; + req_active_verts_loaded :bit1; + req_active_verts :bit7; + vgt_to_ccgen_state_var_indx:bit3; + vgt_to_ccgen_active_verts :bit6; + end; + + TSXIFCCG_DEBUG_REG3=bitpacked record + ALWAYS_ZERO :bit8; + vertex_fifo_entriesavailable :bit4; + statevar_bits_vs_out_ccdist1_vec_ena:bit1; + statevar_bits_vs_out_ccdist0_vec_ena:bit1; + available_positions :bit7; + current_state :bit2; + vertex_fifo_empty :bit1; + vertex_fifo_full :bit1; + sx0_receive_fifo_empty :bit1; + sx0_receive_fifo_full :bit1; + vgt_to_ccgen_fifo_empty :bit1; + vgt_to_ccgen_fifo_full :bit1; + ccgen_to_clipcc_fifo_full :bit1; + sx0_receive_fifo_write :bit1; + ccgen_to_clipcc_write :bit1; + end; + TSX_PERFCOUNTER0_HI=bit32; TSX_PERFCOUNTER0_LO=bit32; @@ -7372,6 +33446,16 @@ type SOFT_OVERRIDE0:bit1; end; + TTC_CFG_L1_VOLATILE=bitpacked record + VOL :bit4; + RESERVED0:bit28; + end; + + TTC_CFG_L2_VOLATILE=bitpacked record + VOL :bit4; + RESERVED0:bit28; + end; + TTD_PERFCOUNTER0_HI=bit32; TTD_PERFCOUNTER0_LO=bit32; @@ -7380,6 +33464,258 @@ type TTD_PERFCOUNTER1_LO=bit32; + TTHM_TMON0_INT_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_INT_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_INT_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TUNIPHY_PLL_SS_CNTL=bitpacked record + UNIPHY_PLL_SS_STEP_NUM:bit12; + UNIPHY_PLL_DSMOD_EN :bit1; + UNIPHY_PLL_SS_EN :bit1; + RESERVED0 :bit18; + end; + + TUNIPHY_TPG_CONTROL=bitpacked record + UNIPHY_STATIC_TEST_PATTERN:bit10; + RESERVED0 :bit6; + UNIPHY_TPG_EN :bit1; + UNIPHY_TPG_SEL :bit3; + RESERVED1 :bit12; + end; + + TUNIPHY_TX_CONTROL1=bitpacked record + UNIPHY_PREMPH_STR0:bit3; + RESERVED0 :bit1; + UNIPHY_PREMPH_STR1:bit3; + RESERVED1 :bit1; + UNIPHY_PREMPH_STR2:bit3; + RESERVED2 :bit1; + UNIPHY_PREMPH_STR3:bit3; + RESERVED3 :bit1; + UNIPHY_PREMPH_STR4:bit3; + RESERVED4 :bit1; + UNIPHY_TX_VS0 :bit2; + UNIPHY_TX_VS1 :bit2; + UNIPHY_TX_VS2 :bit2; + UNIPHY_TX_VS3 :bit2; + UNIPHY_TX_VS4 :bit2; + RESERVED5 :bit2; + end; + + TUNIPHY_TX_CONTROL2=bitpacked record + UNIPHY_PREMPH0_PC:bit2; + RESERVED0 :bit2; + UNIPHY_PREMPH1_PC:bit2; + RESERVED1 :bit2; + UNIPHY_PREMPH2_PC:bit2; + RESERVED2 :bit2; + UNIPHY_PREMPH3_PC:bit2; + RESERVED3 :bit2; + UNIPHY_PREMPH4_PC:bit2; + RESERVED4 :bit2; + UNIPHY_PREMPH_SEL:bit1; + UNIPHY_RT0_CPSEL :bit2; + UNIPHY_RT1_CPSEL :bit2; + UNIPHY_RT2_CPSEL :bit2; + UNIPHY_RT3_CPSEL :bit2; + UNIPHY_RT4_CPSEL :bit2; + RESERVED5 :bit1; + end; + + TUNIPHY_TX_CONTROL3=bitpacked record + UNIPHY_PREMPH_PW_CLK :bit2; + UNIPHY_PREMPH_PW_DAT :bit2; + UNIPHY_PREMPH_CS_CLK :bit4; + UNIPHY_PREMPH_CS_DAT :bit4; + UNIPHY_PREMPH_STR_CLK:bit3; + RESERVED0 :bit1; + UNIPHY_PREMPH_STR_DAT:bit3; + RESERVED1 :bit1; + UNIPHY_PESEL0 :bit1; + UNIPHY_PESEL1 :bit1; + UNIPHY_PESEL2 :bit1; + UNIPHY_PESEL3 :bit1; + UNIPHY_TX_VS_ADJ :bit5; + RESERVED2 :bit2; + UNIPHY_LVDS_PULLDWN :bit1; + end; + + TUNIPHY_TX_CONTROL4=bitpacked record + UNIPHY_TX_NVS_CLK:bit5; + UNIPHY_TX_NVS_DAT:bit5; + RESERVED0 :bit2; + UNIPHY_TX_PVS_CLK:bit5; + UNIPHY_TX_PVS_DAT:bit5; + RESERVED1 :bit2; + UNIPHY_TX_OP_CLK :bit3; + RESERVED2 :bit1; + UNIPHY_TX_OP_DAT :bit3; + RESERVED3 :bit1; + end; + + TUNP_GRPH_SWAP_CNTL=bitpacked record + GRPH_ENDIAN_SWAP :bit2; + RESERVED0 :bit2; + GRPH_RED_CROSSBAR :bit2; + GRPH_GREEN_CROSSBAR:bit2; + GRPH_BLUE_CROSSBAR :bit2; + RESERVED1 :bit22; + end; + + TUNP_GRPH_X_START_C=bitpacked record + GRPH_X_START_C:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_X_START_L=bitpacked record + GRPH_X_START_L:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_Y_START_C=bitpacked record + GRPH_Y_START_C:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_Y_START_L=bitpacked record + GRPH_Y_START_L:bit14; + RESERVED0 :bit18; + end; + + TUVD_GPCOM_VCPU_CMD=bitpacked record + CMD_SEND :bit1; + CMD :bit30; + CMD_SOURCE:bit1; + end; + + TUVD_LMI_CACHE_CTRL=bitpacked record + IT_EN :bit1; + IT_FLUSH :bit1; + CM_EN :bit1; + CM_FLUSH :bit1; + VCPU_EN :bit1; + VCPU_FLUSH:bit1; + RESERVED0 :bit26; + end; + + TUVD_LMI_EXT40_ADDR=bitpacked record + ADDR :bit8; + RESERVED0 :bit8; + INDEX :bit5; + RESERVED1 :bit10; + WRITE_ADDR:bit1; + end; + + TUVD_LMI_SWAP_CNTL2=bitpacked record + SCPU_R_MC_SWAP:bit2; + SCPU_W_MC_SWAP:bit2; + RESERVED0 :bit28; + end; + + TUVD_SEMA_ADDR_HIGH=bitpacked record + ADDR_42_23:bit20; + RESERVED0 :bit12; + end; + + TVCE_LMI_CACHE_CTRL=bitpacked record + VCPU_EN :bit1; + RESERVED0:bit1; + RESERVED1:bit30; + end; + + TVCE_LMI_SWAP_CNTL1=bitpacked record + VCPU_R_MC_SWAP:bit2; + RD_MC_CID_SWAP:bit12; + RESERVED0 :bit6; + RESERVED1 :bit6; + RESERVED2 :bit6; + end; + + TVCE_LMI_SWAP_CNTL2=bitpacked record + WR_MC_CID_SWAP:bit8; + RESERVED0 :bit6; + RESERVED1 :bit4; + RESERVED2 :bit2; + RESERVED3 :bit4; + RESERVED4 :bit2; + RESERVED5 :bit4; + RESERVED6 :bit2; + end; + + TVCE_LMI_SWAP_CNTL3=bitpacked record + RD_MC_CID_SWAP:bit2; + RESERVED0 :bit12; + RESERVED1 :bit1; + RESERVED2 :bit5; + RESERVED3 :bit1; + RESERVED4 :bit5; + RESERVED5 :bit1; + RESERVED6 :bit5; + end; + + TVCE_SYS_INT_STATUS=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit2; + VCE_SYS_INT_TRAP_INTERRUPT_INT:bit1; + RESERVED2 :bit1; + RESERVED3 :bit6; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit14; + end; + + TVGA25_PPLL_REF_DIV=bitpacked record + VGA25_PPLL_REF_DIV:bit10; + RESERVED0 :bit22; + end; + + TVGA28_PPLL_REF_DIV=bitpacked record + VGA28_PPLL_REF_DIV:bit10; + RESERVED0 :bit22; + end; + + TVGA41_PPLL_REF_DIV=bitpacked record + VGA41_PPLL_REF_DIV:bit10; + RESERVED0 :bit22; + end; + + TVGADCC_DBG_DCCIF_C=bit32; + + TVGA_RENDER_CONTROL=bitpacked record + VGA_BLINK_RATE :bit5; + VGA_BLINK_MODE :bit2; + VGA_CURSOR_BLINK_INVERT :bit1; + VGA_EXTD_ADDR_COUNT_ENABLE :bit1; + RESERVED0 :bit7; + VGA_VSTATUS_CNTL :bit2; + RESERVED1 :bit6; + VGA_LOCK_8DOT :bit1; + VGAREG_LINECMP_COMPATIBILITY_SEL:bit1; + RESERVED2 :bit6; + end; + TVGT_DMA_INDEX_TYPE=bitpacked record INDEX_TYPE :bit2; SWAP_MODE :bit2; @@ -7441,6 +33777,16 @@ type RESERVED0 :bit20; end; + TVM_FAULT_CLIENT_ID=bitpacked record + MEMORY_CLIENT :bit9; + MEMORY_CLIENT_MASK :bit9; + MEMORY_CLIENT_ID_MSB :bit1; + MEMORY_CLIENT_ID_MASK_MSB:bit1; + RESERVED0 :bit12; + end; + + TWALL_CLOCK_COUNTER=bit32; + TWD_PERFCOUNTER0_HI=bit32; TWD_PERFCOUNTER0_LO=bit32; @@ -7457,8 +33803,645 @@ type TWD_PERFCOUNTER3_LO=bit32; + TXDMA_IF_BIF_STATUS=bitpacked record + XDMA_IF_BIF_ERROR_STATUS:bit4; + RESERVED0 :bit4; + XDMA_IF_BIF_ERROR_CLEAR :bit1; + RESERVED1 :bit23; + end; + + TXDMA_SLV_SLS_PITCH=bitpacked record + XDMA_SLV_SLS_PITCH:bit14; + RESERVED0 :bit2; + XDMA_SLV_SLS_WIDTH:bit14; + RESERVED1 :bit2; + end; + + TABM_TEST_DEBUG_DATA=bit32; + + TATC_ATS_FAULT_DEBUG=bitpacked record + CREDITS_ATS_IH :bit5; + RESERVED0 :bit3; + ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES:bit1; + RESERVED1 :bit7; + CLEAR_FAULT_STATUS_ADDR :bit1; + RESERVED2 :bit15; + end; + + TATC_ATS_VMID_STATUS=bitpacked record + VMID0_OUTSTANDING :bit1; + VMID1_OUTSTANDING :bit1; + VMID2_OUTSTANDING :bit1; + VMID3_OUTSTANDING :bit1; + VMID4_OUTSTANDING :bit1; + VMID5_OUTSTANDING :bit1; + VMID6_OUTSTANDING :bit1; + VMID7_OUTSTANDING :bit1; + VMID8_OUTSTANDING :bit1; + VMID9_OUTSTANDING :bit1; + VMID10_OUTSTANDING:bit1; + VMID11_OUTSTANDING:bit1; + VMID12_OUTSTANDING:bit1; + VMID13_OUTSTANDING:bit1; + VMID14_OUTSTANDING:bit1; + VMID15_OUTSTANDING:bit1; + RESERVED0 :bit16; + end; + + TATC_L1RD_DEBUG2_TLB=bitpacked record + RESERVED0 :bit10; + RESERVED1 :bit2; + INJECT_SOFT_PARITY_ERROR:bit1; + INJECT_HARD_PARITY_ERROR:bit1; + CLEAR_CAM_PARITY_ERROR :bit1; + CAM_INDEX :bit5; + RESERVED2 :bit12; + end; + + TATC_L1WR_DEBUG2_TLB=bitpacked record + RESERVED0 :bit10; + RESERVED1 :bit2; + INJECT_SOFT_PARITY_ERROR:bit1; + INJECT_HARD_PARITY_ERROR:bit1; + CLEAR_CAM_PARITY_ERROR :bit1; + CAM_INDEX :bit5; + RESERVED2 :bit12; + end; + + TAUX_DPHY_TX_CONTROL=bitpacked record + AUX_TX_PRECHARGE_LEN :bit3; + RESERVED0 :bit5; + AUX_TX_PRECHARGE_SYMBOLS:bit6; + RESERVED1 :bit2; + AUX_MODE_DET_CHECK_DELAY:bit3; + RESERVED2 :bit13; + end; + + TAUX_GTC_SYNC_STATUS=bitpacked record + AUX_GTC_SYNC_DONE :bit1; + AUX_GTC_SYNC_REQ :bit1; + RESERVED0 :bit2; + AUX_GTC_SYNC_RX_TIMEOUT_STATE :bit3; + AUX_GTC_SYNC_TIMEOUT :bit1; + AUX_GTC_SYNC_RX_OVERFLOW :bit1; + AUX_GTC_SYNC_HPD_DISCON :bit1; + AUX_GTC_SYNC_RX_PARTIAL_BYTE :bit1; + AUX_GTC_SYNC_NON_AUX_MODE :bit1; + AUX_GTC_SYNC_RX_MIN_COUNT_VIOL:bit1; + RESERVED1 :bit1; + AUX_GTC_SYNC_RX_INVALID_STOP :bit1; + RESERVED2 :bit2; + AUX_GTC_SYNC_RX_SYNC_INVALID_L:bit1; + AUX_GTC_SYNC_RX_SYNC_INVALID_H:bit1; + AUX_GTC_SYNC_RX_INVALID_START :bit1; + AUX_GTC_SYNC_RX_RECV_NO_DET :bit1; + RESERVED3 :bit1; + AUX_GTC_SYNC_RX_RECV_INVALID_H:bit1; + AUX_GTC_SYNC_RX_RECV_INVALID_L:bit1; + AUX_GTC_SYNC_REPLY_BYTE_COUNT :bit5; + AUX_GTC_SYNC_NACKED :bit1; + AUX_GTC_MASTER_REQ_BY_RX :bit1; + RESERVED4 :bit1; + end; + + TAUX_TEST_DEBUG_DATA=bit32; + + TAVSYNC_COUNTER_READ=bit32; + + TAZALIA_MEM_PWR_CTRL=bitpacked record + AZ_MEM_PWR_FORCE :bit2; + AZ_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM0_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM0_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM1_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM1_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM2_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM2_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM3_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM3_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM4_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM4_MEM_PWR_DIS :bit1; + AZ_INPUT_STREAM5_MEM_PWR_FORCE:bit2; + AZ_INPUT_STREAM5_MEM_PWR_DIS :bit1; + RESERVED0 :bit7; + AZ_MEM_PWR_MODE_SEL :bit2; + RESERVED1 :bit2; + end; + + TAZALIA_SCLK_CONTROL=bitpacked record + RESERVED0 :bit2; + RESERVED1 :bit2; + AUDIO_SCLK_CONTROL:bit2; + RESERVED2 :bit26; + end; + + TAZALIA_STREAM_DEBUG=bit32; + + TAZALIA_STREAM_INDEX=bitpacked record + AZALIA_STREAM_REG_INDEX :bit8; + AZALIA_STREAM_REG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TAZ_TEST_DEBUG_INDEX=bitpacked record + AZ_TEST_DEBUG_INDEX :bit8; + AZ_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TBIF_BUSY_DELAY_CNTR=bitpacked record + DELAY_CNT:bit6; + RESERVED0:bit26; + end; + + TBIF_IMPCTL_SMPLCNTL=bitpacked record + FORCE_DONE :bit1; + RxPDNB :bit1; + TxPDNB_pd :bit1; + TxPDNB_pu :bit1; + RESERVED0 :bit4; + SAMPLE_PERIOD :bit5; + EXTEND_SAMPLES :bit1; + FORCE_ENABLE :bit1; + SETUP_TIME :bit5; + LOWER_SAMPLE_THRESH:bit6; + UPPER_SAMPLE_THRESH:bit6; + end; + + TBIF_RB_WPTR_ADDR_HI=bitpacked record + ADDR :bit8; + RESERVED0:bit24; + end; + + TBIF_RB_WPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TBIF_RFE_IMPRST_CNTL=bitpacked record + REG_RST_impEn:bit1; + RESERVED0 :bit1; + RESERVED1 :bit30; + end; + + TCAPTURE_HOST_BUSNUM=bitpacked record + CHECK_EN :bit1; + RESERVED0:bit31; + end; + + TCC_GIO_IOCCFG_FUSES=bitpacked record + RESERVED0:bit1; + NB_REV_ID:bit10; + RESERVED1:bit21; + end; + + TCC_SQC_BANK_DISABLE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit15; + SQC0_BANK_DISABLE:bit4; + SQC1_BANK_DISABLE:bit4; + SQC2_BANK_DISABLE:bit4; + SQC3_BANK_DISABLE:bit4; + end; + + TCG_DISPLAY_GAP_CNTL=bitpacked record + DISP_GAP :bit2; + RESERVED0 :bit2; + VBI_TIMER_COUNT :bit14; + RESERVED1 :bit2; + VBI_TIMER_UNIT :bit3; + RESERVED2 :bit1; + DISP_GAP_MCHG :bit2; + RESERVED3 :bit2; + VBI_TIMER_DISABLE:bit1; + RESERVED4 :bit3; + end; + + TCG_FREQ_TRAN_VOTING=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10:bit1; + RESERVED11:bit1; + RESERVED12:bit1; + RESERVED13:bit1; + RESERVED14:bit2; + RESERVED15:bit1; + RESERVED16:bit1; + RESERVED17:bit4; + RESERVED18:bit1; + RESERVED19:bit1; + RESERVED20:bit1; + RESERVED21:bit1; + RESERVED22:bit1; + RESERVED23:bit1; + RESERVED24:bit4; + end; + + TCG_SPLL_FUNC_CNTL_2=bitpacked record + SCLK_MUX_SEL :bit9; + RESERVED0 :bit2; + SPLL_CTLREQ :bit1; + RESERVED1 :bit10; + SPLL_BYPASS_CHG :bit1; + SPLL_CTLREQ_CHG :bit1; + SPLL_RESET_CHG :bit1; + SPLL_BABY_STEP_CHG :bit1; + SCLK_MUX_UPDATE :bit1; + SPLL_UNLOCK_CLEAR :bit1; + SPLL_CLKF_UPDATE :bit1; + RESERVED2 :bit1; + SPLL_TEST_UNLOCK_CLR:bit1; + RESERVED3 :bit1; + end; + + TCG_SPLL_FUNC_CNTL_3=bitpacked record + SPLL_FB_DIV:bit26; + RESERVED0 :bit2; + SPLL_DITHEN:bit1; + RESERVED1 :bit3; + end; + + TCG_SPLL_FUNC_CNTL_4=bitpacked record + SPLL_SCLK_TEST_SEL :bit4; + RESERVED0 :bit1; + SPLL_SCLK_EXT_SEL :bit2; + SPLL_SCLK_EN :bit2; + SPLL_SSAMP_EN :bit1; + SPLL_SPARE :bit9; + RESERVED1 :bit2; + TEST_FRAC_BYPASS :bit1; + RESERVED2 :bit1; + SPLL_ILOCK :bit1; + SPLL_FBCLK_SEL :bit1; + SPLL_VCTRLADC_EN :bit1; + SPLL_SCLK_EXT :bit2; + SPLL_SPARE_EXT :bit3; + SPLL_VTOI_BIAS_CNTL:bit1; + end; + + TCG_SPLL_FUNC_CNTL_5=bitpacked record + FBDIV_SSC_BYPASS:bit1; + RISEFBVCO_EN :bit1; + PFD_RESET_CNTRL :bit2; + RESET_TIMER :bit2; + FAST_LOCK_CNTRL :bit2; + FAST_LOCK_EN :bit1; + RESET_ANTI_MUX :bit1; + REFCLK_BYPASS_EN:bit1; + PLLBYPASS :bit1; + RESERVED0 :bit20; + end; + + TCG_SPLL_FUNC_CNTL_6=bitpacked record + SCLKMUX0_CLKOFF_CNT:bit8; + SCLKMUX1_CLKOFF_CNT:bit8; + SPLL_VCTL_EN :bit1; + SPLL_VCTL_CNTRL_IN :bit4; + SPLL_VCTL_CNTRL_OUT:bit4; + SPLL_LF_CNTR :bit7; + end; + + TCG_SPLL_FUNC_CNTL_7=bitpacked record + SPLL_BW_CNTRL:bit12; + RESERVED0 :bit20; + end; + + TCG_THERMAL_INT_CTRL=bitpacked record + DIG_THERM_INTH :bit8; + DIG_THERM_INTL :bit8; + GNB_TEMP_THRESHOLD :bit8; + THERM_INTH_MASK :bit1; + THERM_INTL_MASK :bit1; + THERM_TRIGGER_MASK :bit1; + THERM_TRIGGER_CNB_MASK:bit1; + THERM_GNB_HW_ENA :bit1; + RESERVED0 :bit3; + end; + + TCLIENT1_PORT_STATUS=bit32; + + TCLIPPER_DEBUG_REG00=bitpacked record + ALWAYS_ZERO :bit8; + clip_ga_bc_fifo_write :bit1; + su_clip_baryc_free :bit2; + clip_to_ga_fifo_write :bit1; + clip_to_ga_fifo_full :bit1; + primic_to_clprim_fifo_empty :bit1; + primic_to_clprim_fifo_full :bit1; + clip_to_outsm_fifo_empty :bit1; + clip_to_outsm_fifo_full :bit1; + vgt_to_clipp_fifo_empty :bit1; + vgt_to_clipp_fifo_full :bit1; + vgt_to_clips_fifo_empty :bit1; + vgt_to_clips_fifo_full :bit1; + clipcode_fifo_fifo_empty :bit1; + clipcode_fifo_full :bit1; + vte_out_clip_fifo_fifo_empty:bit1; + vte_out_clip_fifo_fifo_full :bit1; + vte_out_orig_fifo_fifo_empty:bit1; + vte_out_orig_fifo_fifo_full :bit1; + ccgen_to_clipcc_fifo_empty :bit1; + ccgen_to_clipcc_fifo_full :bit1; + clip_to_outsm_fifo_write :bit1; + vte_out_orig_fifo_fifo_write:bit1; + vgt_to_clipp_fifo_write :bit1; + end; + + TCLIPPER_DEBUG_REG01=bitpacked record + ALWAYS_ZERO :bit8; + clip_extra_bc_valid :bit3; + clip_vert_vte_valid :bit3; + clip_to_outsm_vertex_deallocate :bit3; + clip_to_outsm_deallocate_slot :bit3; + clip_to_outsm_null_primitive :bit1; + vte_positions_vte_clip_vte_naninf_kill_2:bit1; + vte_positions_vte_clip_vte_naninf_kill_1:bit1; + vte_positions_vte_clip_vte_naninf_kill_0:bit1; + vte_out_clip_rd_extra_bc_valid :bit1; + vte_out_clip_rd_vte_naninf_kill :bit1; + vte_out_clip_rd_vertex_store_indx :bit2; + clip_ga_bc_fifo_write :bit1; + clip_to_ga_fifo_write :bit1; + vte_out_clip_fifo_fifo_advanceread :bit1; + vte_out_clip_fifo_fifo_empty :bit1; + end; + + TCLIPPER_DEBUG_REG02=bitpacked record + clip_extra_bc_valid :bit3; + clip_vert_vte_valid :bit3; + clip_to_outsm_clip_seq_indx :bit2; + clip_to_outsm_vertex_store_indx_2:bit4; + clip_to_outsm_vertex_store_indx_1:bit4; + clip_to_outsm_vertex_store_indx_0:bit4; + clip_to_clipga_extra_bc_coords :bit1; + clip_to_clipga_vte_naninf_kill :bit1; + clip_to_outsm_end_of_packet :bit1; + clip_to_outsm_first_prim_of_slot :bit1; + clip_to_outsm_clipped_prim :bit1; + clip_to_outsm_null_primitive :bit1; + clip_ga_bc_fifo_full :bit1; + clip_to_ga_fifo_full :bit1; + clip_ga_bc_fifo_write :bit1; + clip_to_ga_fifo_write :bit1; + clip_to_outsm_fifo_advanceread :bit1; + clip_to_outsm_fifo_empty :bit1; + end; + + TCLIPPER_DEBUG_REG03=bitpacked record + clipsm0_clprim_to_clip_clip_code_or :bit14; + clipsm0_clprim_to_clip_event_id :bit6; + clipsm0_clprim_to_clip_state_var_indx :bit3; + clipsm0_clprim_to_clip_clip_primitive :bit1; + clipsm0_clprim_to_clip_deallocate_slot :bit3; + clipsm0_clprim_to_clip_first_prim_of_slot:bit1; + clipsm0_clprim_to_clip_end_of_packet :bit1; + clipsm0_clprim_to_clip_event :bit1; + clipsm0_clprim_to_clip_null_primitive :bit1; + clipsm0_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG04=bitpacked record + RESERVED0 :bit1; + clipsm0_clprim_to_clip_param_cache_indx_0 :bit10; + clipsm0_clprim_to_clip_vertex_store_indx_2:bit6; + clipsm0_clprim_to_clip_vertex_store_indx_1:bit6; + clipsm0_clprim_to_clip_vertex_store_indx_0:bit6; + clipsm0_clprim_to_clip_event :bit1; + clipsm0_clprim_to_clip_null_primitive :bit1; + clipsm0_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG05=bitpacked record + clipsm1_clprim_to_clip_clip_code_or :bit14; + clipsm1_clprim_to_clip_event_id :bit6; + clipsm1_clprim_to_clip_state_var_indx :bit3; + clipsm1_clprim_to_clip_clip_primitive :bit1; + clipsm1_clprim_to_clip_deallocate_slot :bit3; + clipsm1_clprim_to_clip_first_prim_of_slot:bit1; + clipsm1_clprim_to_clip_end_of_packet :bit1; + clipsm1_clprim_to_clip_event :bit1; + clipsm1_clprim_to_clip_null_primitive :bit1; + clipsm1_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG06=bitpacked record + RESERVED0 :bit1; + clipsm1_clprim_to_clip_param_cache_indx_0 :bit10; + clipsm1_clprim_to_clip_vertex_store_indx_2:bit6; + clipsm1_clprim_to_clip_vertex_store_indx_1:bit6; + clipsm1_clprim_to_clip_vertex_store_indx_0:bit6; + clipsm1_clprim_to_clip_event :bit1; + clipsm1_clprim_to_clip_null_primitive :bit1; + clipsm1_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG07=bitpacked record + clipsm2_clprim_to_clip_clip_code_or :bit14; + clipsm2_clprim_to_clip_event_id :bit6; + clipsm2_clprim_to_clip_state_var_indx :bit3; + clipsm2_clprim_to_clip_clip_primitive :bit1; + clipsm2_clprim_to_clip_deallocate_slot :bit3; + clipsm2_clprim_to_clip_first_prim_of_slot:bit1; + clipsm2_clprim_to_clip_end_of_packet :bit1; + clipsm2_clprim_to_clip_event :bit1; + clipsm2_clprim_to_clip_null_primitive :bit1; + clipsm2_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG08=bitpacked record + RESERVED0 :bit1; + clipsm2_clprim_to_clip_param_cache_indx_0 :bit10; + clipsm2_clprim_to_clip_vertex_store_indx_2:bit6; + clipsm2_clprim_to_clip_vertex_store_indx_1:bit6; + clipsm2_clprim_to_clip_vertex_store_indx_0:bit6; + clipsm2_clprim_to_clip_event :bit1; + clipsm2_clprim_to_clip_null_primitive :bit1; + clipsm2_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG09=bitpacked record + clipsm3_clprim_to_clip_clip_code_or :bit14; + clipsm3_clprim_to_clip_event_id :bit6; + clipsm3_clprim_to_clip_state_var_indx :bit3; + clipsm3_clprim_to_clip_clip_primitive :bit1; + clipsm3_clprim_to_clip_deallocate_slot :bit3; + clipsm3_clprim_to_clip_first_prim_of_slot:bit1; + clipsm3_clprim_to_clip_end_of_packet :bit1; + clipsm3_clprim_to_clip_event :bit1; + clipsm3_clprim_to_clip_null_primitive :bit1; + clipsm3_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG10=bitpacked record + RESERVED0 :bit1; + clipsm3_clprim_to_clip_param_cache_indx_0 :bit10; + clipsm3_clprim_to_clip_vertex_store_indx_2:bit6; + clipsm3_clprim_to_clip_vertex_store_indx_1:bit6; + clipsm3_clprim_to_clip_vertex_store_indx_0:bit6; + clipsm3_clprim_to_clip_event :bit1; + clipsm3_clprim_to_clip_null_primitive :bit1; + clipsm3_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG11=bitpacked record + clipsm3_clip_to_clipga_event :bit1; + clipsm2_clip_to_clipga_event :bit1; + clipsm1_clip_to_clipga_event :bit1; + clipsm0_clip_to_clipga_event :bit1; + clipsm3_clip_to_clipga_clip_primitive :bit1; + clipsm2_clip_to_clipga_clip_primitive :bit1; + clipsm1_clip_to_clipga_clip_primitive :bit1; + clipsm0_clip_to_clipga_clip_primitive :bit1; + clipsm3_clip_to_clipga_clip_to_outsm_cnt :bit4; + clipsm2_clip_to_clipga_clip_to_outsm_cnt :bit4; + clipsm1_clip_to_clipga_clip_to_outsm_cnt :bit4; + clipsm0_clip_to_clipga_clip_to_outsm_cnt :bit4; + clipsm3_clip_to_clipga_prim_valid :bit1; + clipsm2_clip_to_clipga_prim_valid :bit1; + clipsm1_clip_to_clipga_prim_valid :bit1; + clipsm0_clip_to_clipga_prim_valid :bit1; + clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt:bit1; + clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt:bit1; + clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt:bit1; + clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt:bit1; + end; + + TCLIPPER_DEBUG_REG12=bitpacked record + ALWAYS_ZERO :bit8; + clip_priority_available_vte_out_clip :bit5; + clip_priority_available_clip_verts :bit5; + clip_priority_seq_indx_out :bit2; + clip_priority_seq_indx_vert :bit2; + clip_priority_seq_indx_load :bit2; + clipsm3_clprim_to_clip_clip_primitive:bit1; + clipsm3_clprim_to_clip_prim_valid :bit1; + clipsm2_clprim_to_clip_clip_primitive:bit1; + clipsm2_clprim_to_clip_prim_valid :bit1; + clipsm1_clprim_to_clip_clip_primitive:bit1; + clipsm1_clprim_to_clip_prim_valid :bit1; + clipsm0_clprim_to_clip_clip_primitive:bit1; + clipsm0_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG13=bitpacked record + clprim_in_back_state_var_indx :bit3; + point_clip_candidate :bit1; + prim_nan_kill :bit1; + clprim_clip_primitive :bit1; + clprim_cull_primitive :bit1; + prim_back_valid :bit1; + vertval_bits_vertex_cc_next_valid:bit4; + clipcc_vertex_store_indx :bit2; + vte_out_orig_fifo_fifo_empty :bit1; + clipcode_fifo_fifo_empty :bit1; + ccgen_to_clipcc_fifo_empty :bit1; + clip_priority_seq_indx_out_cnt :bit4; + outsm_clr_rd_orig_vertices :bit2; + outsm_clr_rd_clipsm_wait :bit1; + outsm_clr_fifo_contents :bit5; + outsm_clr_fifo_full :bit1; + outsm_clr_fifo_advanceread :bit1; + outsm_clr_fifo_write :bit1; + end; + + TCLIPPER_DEBUG_REG14=bitpacked record + clprim_in_back_vertex_store_indx_2:bit6; + clprim_in_back_vertex_store_indx_1:bit6; + clprim_in_back_vertex_store_indx_0:bit6; + outputclprimtoclip_null_primitive :bit1; + clprim_in_back_end_of_packet :bit1; + clprim_in_back_first_prim_of_slot :bit1; + clprim_in_back_deallocate_slot :bit3; + clprim_in_back_event_id :bit6; + clprim_in_back_event :bit1; + prim_back_valid :bit1; + end; + + TCLIPPER_DEBUG_REG15=bitpacked record + vertval_bits_vertex_vertex_store_msb :bit16; + primic_to_clprim_fifo_vertex_store_indx_2:bit5; + primic_to_clprim_fifo_vertex_store_indx_1:bit5; + primic_to_clprim_fifo_vertex_store_indx_0:bit5; + primic_to_clprim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG16=bitpacked record + sm0_prim_end_state :bit7; + sm0_ps_expand :bit1; + sm0_clip_vert_cnt :bit5; + sm0_vertex_clip_cnt :bit5; + sm0_inv_to_clip_data_valid_1 :bit1; + sm0_inv_to_clip_data_valid_0 :bit1; + sm0_current_state :bit7; + sm0_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1; + sm0_clip_to_outsm_fifo_full :bit1; + sm0_highest_priority_seq :bit1; + sm0_outputcliptoclipga_0 :bit1; + sm0_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG17=bitpacked record + sm1_prim_end_state :bit7; + sm1_ps_expand :bit1; + sm1_clip_vert_cnt :bit5; + sm1_vertex_clip_cnt :bit5; + sm1_inv_to_clip_data_valid_1 :bit1; + sm1_inv_to_clip_data_valid_0 :bit1; + sm1_current_state :bit7; + sm1_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1; + sm1_clip_to_outsm_fifo_full :bit1; + sm1_highest_priority_seq :bit1; + sm1_outputcliptoclipga_0 :bit1; + sm1_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG18=bitpacked record + sm2_prim_end_state :bit7; + sm2_ps_expand :bit1; + sm2_clip_vert_cnt :bit5; + sm2_vertex_clip_cnt :bit5; + sm2_inv_to_clip_data_valid_1 :bit1; + sm2_inv_to_clip_data_valid_0 :bit1; + sm2_current_state :bit7; + sm2_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1; + sm2_clip_to_outsm_fifo_full :bit1; + sm2_highest_priority_seq :bit1; + sm2_outputcliptoclipga_0 :bit1; + sm2_clprim_to_clip_prim_valid :bit1; + end; + + TCLIPPER_DEBUG_REG19=bitpacked record + sm3_prim_end_state :bit7; + sm3_ps_expand :bit1; + sm3_clip_vert_cnt :bit5; + sm3_vertex_clip_cnt :bit5; + sm3_inv_to_clip_data_valid_1 :bit1; + sm3_inv_to_clip_data_valid_0 :bit1; + sm3_current_state :bit7; + sm3_clip_to_clipga_clip_to_outsm_cnt_eq0:bit1; + sm3_clip_to_outsm_fifo_full :bit1; + sm3_highest_priority_seq :bit1; + sm3_outputcliptoclipga_0 :bit1; + sm3_clprim_to_clip_prim_valid :bit1; + end; + + TCNV_TEST_DEBUG_DATA=bit32; + TCOMPUTE_DISPATCH_ID=bit32; + TCOMPUTE_MAX_WAVE_ID=bitpacked record + RESERVED0:bit12; + RESERVED1:bit20; + end; + TCOMPUTE_USER_DATA_0=bit32; TCOMPUTE_USER_DATA_1=bit32; @@ -7536,8 +34519,8 @@ type end; TCP_EOP_DONE_ADDR_LO=bitpacked record - ADDR_SWAP__SI__CI:bit2; - ADDR_LO :bit30; + ADDR_SWAP:bit2; + ADDR_LO :bit30; end; TCP_EOP_DONE_CNTX_ID=bitpacked record @@ -7730,6 +34713,53 @@ type SEM_ADDR_LO :bit29; end; + TCRTC_AVSYNC_COUNTER=bit32; + + TCRTC_OVERSCAN_COLOR=bitpacked record + CRTC_OVERSCAN_COLOR_BLUE :bit10; + CRTC_OVERSCAN_COLOR_GREEN:bit10; + CRTC_OVERSCAN_COLOR_RED :bit10; + RESERVED0 :bit2; + end; + + TCRTC_SNAPSHOT_FRAME=bitpacked record + CRTC_SNAPSHOT_FRAME_COUNT:bit24; + RESERVED0 :bit8; + end; + + TCRTC_STEREO_CONTROL=bitpacked record + CRTC_STEREO_SYNC_OUTPUT_LINE_NUM :bit14; + RESERVED0 :bit1; + CRTC_STEREO_SYNC_OUTPUT_POLARITY :bit1; + CRTC_STEREO_SYNC_SELECT_POLARITY :bit1; + CRTC_STEREO_EYE_FLAG_POLARITY :bit1; + CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP:bit1; + CRTC_DISABLE_FIELD_NUM :bit1; + CRTC_DISABLE_V_BLANK_FOR_DP_FIX :bit1; + RESERVED1 :bit3; + CRTC_STEREO_EN :bit1; + RESERVED2 :bit7; + end; + + TCUR2_STEREO_CONTROL=bitpacked record + CURSOR2_STEREO_EN :bit1; + CURSOR2_STEREO_OFFSET_YNX:bit1; + RESERVED0 :bit2; + CURSOR2_PRIMARY_OFFSET :bit10; + RESERVED1 :bit2; + CURSOR2_SECONDARY_OFFSET :bit10; + RESERVED2 :bit6; + end; + + TCUR_SURFACE_ADDRESS=bit32; + + TDAC_CRC_SIG_CONTROL=bitpacked record + DAC_CRC_SIG_CONTROL:bit6; + RESERVED0 :bit26; + end; + + TDAC_TEST_DEBUG_DATA=bit32; + TDB_DEPTH_BOUNDS_MAX=bit32; TDB_DEPTH_BOUNDS_MIN=bit32; @@ -7753,12 +34783,526 @@ type RESERVED0 :bit8; end; + TDCCG_GTC_DTO_MODULO=bit32; + + TDCFEV_CLOCK_CONTROL=bitpacked record + RESERVED0 :bit3; + DISPCLK_R_DCFEV_GATE_DISABLE :bit1; + RESERVED1 :bit3; + DISPCLK_G_UNP_GATE_DISABLE :bit1; + RESERVED2 :bit1; + DISPCLK_G_SCLV_GATE_DISABLE :bit1; + RESERVED3 :bit1; + DISPCLK_G_COL_MAN_GATE_DISABLE:bit1; + RESERVED4 :bit1; + DISPCLK_G_PSCLV_GATE_DISABLE :bit1; + RESERVED5 :bit1; + DISPCLK_G_CRTC_GATE_DISABLE :bit1; + RESERVED6 :bit8; + DCFEV_TEST_CLK_SEL :bit5; + RESERVED7 :bit2; + DCFEV_CLOCK_ENABLE :bit1; + end; + + TDCFE_MEM_PWR_STATUS=bitpacked record + DCP_LUT_MEM_PWR_STATE :bit2; + DCP_REGAMMA_MEM_PWR_STATE:bit2; + SCL_COEFF_MEM_PWR_STATE :bit2; + DCP_CURSOR_MEM_PWR_STATE :bit2; + DCP_CURSOR2_MEM_PWR_STATE:bit2; + LB0_ALPHA_MEM_PWR_STATE :bit2; + LB1_ALPHA_MEM_PWR_STATE :bit2; + LB2_ALPHA_MEM_PWR_STATE :bit2; + LB0_MEM_PWR_STATE :bit2; + LB1_MEM_PWR_STATE :bit2; + LB2_MEM_PWR_STATE :bit2; + BLND_MEM_PWR_STATE :bit2; + OVLSCL_MEM_PWR_STATE :bit1; + RESERVED0 :bit7; + end; + + TDCIO_IMPCAL_CNTL_AB=bitpacked record + CALR_CNTL_OVERRIDE:bit4; + RESERVED0 :bit1; + IMPCAL_SOFT_RESET :bit1; + RESERVED1 :bit2; + IMPCAL_STATUS :bit2; + RESERVED2 :bit2; + IMPCAL_ARB_STATE :bit3; + RESERVED3 :bit17; + end; + + TDCIO_IMPCAL_CNTL_CD=bitpacked record + CALR_CNTL_OVERRIDE:bit4; + RESERVED0 :bit1; + IMPCAL_SOFT_RESET :bit1; + RESERVED1 :bit2; + IMPCAL_STATUS :bit2; + RESERVED2 :bit2; + IMPCAL_ARB_STATE :bit3; + RESERVED3 :bit17; + end; + + TDCIO_IMPCAL_CNTL_EF=bitpacked record + CALR_CNTL_OVERRIDE:bit4; + RESERVED0 :bit1; + IMPCAL_SOFT_RESET :bit1; + RESERVED1 :bit2; + IMPCAL_STATUS :bit2; + RESERVED2 :bit2; + IMPCAL_ARB_STATE :bit3; + RESERVED3 :bit17; + end; + + TDCI_MEM_PWR_STATUS2=bitpacked record + DMIF1_ASYNC_MEM_PWR_STATE:bit2; + DMIF1_DATA_MEM_PWR_STATE :bit2; + DMIF1_CHUNK_MEM_PWR_STATE:bit1; + DMIF2_ASYNC_MEM_PWR_STATE:bit2; + DMIF2_DATA_MEM_PWR_STATE :bit2; + DMIF2_CHUNK_MEM_PWR_STATE:bit1; + DMIF3_ASYNC_MEM_PWR_STATE:bit2; + DMIF3_DATA_MEM_PWR_STATE :bit2; + DMIF3_CHUNK_MEM_PWR_STATE:bit1; + DMIF4_ASYNC_MEM_PWR_STATE:bit2; + DMIF4_DATA_MEM_PWR_STATE :bit2; + DMIF4_CHUNK_MEM_PWR_STATE:bit1; + DMIF5_ASYNC_MEM_PWR_STATE:bit2; + DMIF5_DATA_MEM_PWR_STATE :bit2; + DMIF5_CHUNK_MEM_PWR_STATE:bit1; + RESERVED0 :bit7; + end; + + TDCI_PG_DEBUG_CONFIG=bitpacked record + DCI_PG_DBG_EN:bit1; + RESERVED0 :bit31; + end; + + TDCI_TEST_DEBUG_DATA=bit32; + + TDCO_TEST_DEBUG_DATA=bit32; + + TDCP_TEST_DEBUG_DATA=bit32; + + TDC_ABM1_HG_RESULT_1=bit32; + + TDC_ABM1_HG_RESULT_2=bit32; + + TDC_ABM1_HG_RESULT_3=bit32; + + TDC_ABM1_HG_RESULT_4=bit32; + + TDC_ABM1_HG_RESULT_5=bit32; + + TDC_ABM1_HG_RESULT_6=bit32; + + TDC_ABM1_HG_RESULT_7=bit32; + + TDC_ABM1_HG_RESULT_8=bit32; + + TDC_ABM1_HG_RESULT_9=bit32; + + TDC_GPIO_DDCVGA_MASK=bitpacked record + DC_GPIO_DDCVGACLK_MASK :bit1; + RESERVED0 :bit5; + DC_GPIO_DDCVGACLK_RECV :bit1; + RESERVED1 :bit1; + DC_GPIO_DDCVGADATA_MASK :bit1; + RESERVED2 :bit3; + DC_GPIO_DDCVGADATA_PD_EN:bit1; + RESERVED3 :bit1; + DC_GPIO_DDCVGADATA_RECV :bit1; + RESERVED4 :bit1; + AUX_PADVGA_MODE :bit1; + RESERVED5 :bit3; + AUXVGA_POL :bit1; + RESERVED6 :bit1; + ALLOW_HW_DDCVGA_PD_EN :bit1; + RESERVED7 :bit1; + DC_GPIO_DDCVGACLK_STR :bit4; + DC_GPIO_DDCVGADATA_STR :bit4; + end; + + TDC_GPIO_I2CPAD_MASK=bitpacked record + DC_GPIO_SCL_MASK :bit1; + DC_GPIO_SCL_PD_DIS:bit1; + DC_GPIO_SCL_RECV :bit1; + RESERVED0 :bit1; + DC_GPIO_SDA_MASK :bit1; + DC_GPIO_SDA_PD_DIS:bit1; + DC_GPIO_SDA_RECV :bit1; + RESERVED1 :bit25; + end; + + TDC_GPIO_PWRSEQ_MASK=bitpacked record + DC_GPIO_BLON_MASK :bit1; + RESERVED0 :bit3; + DC_GPIO_BLON_PD_DIS :bit1; + RESERVED1 :bit1; + DC_GPIO_BLON_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_DIGON_MASK :bit1; + RESERVED3 :bit3; + DC_GPIO_DIGON_PD_DIS :bit1; + RESERVED4 :bit1; + DC_GPIO_DIGON_RECV :bit1; + RESERVED5 :bit1; + DC_GPIO_ENA_BL_MASK :bit1; + RESERVED6 :bit3; + DC_GPIO_ENA_BL_PD_DIS :bit1; + RESERVED7 :bit1; + DC_GPIO_ENA_BL_RECV :bit1; + RESERVED8 :bit1; + DC_GPIO_VSYNC_IN_MASK :bit1; + DC_GPIO_VSYNC_IN_PD_DIS:bit1; + DC_GPIO_VSYNC_IN_RECV :bit1; + RESERVED9 :bit1; + DC_GPIO_HSYNC_IN_MASK :bit1; + DC_GPIO_HSYNC_IN_PD_DIS:bit1; + DC_GPIO_HSYNC_IN_RECV :bit1; + RESERVED10 :bit1; + end; + + TDC_HPD1_INT_CONTROL=bitpacked record + DC_HPD1_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD1_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD1_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD1_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD1_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_HPD2_INT_CONTROL=bitpacked record + DC_HPD2_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD2_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD2_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD2_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD2_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_HPD3_INT_CONTROL=bitpacked record + DC_HPD3_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD3_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD3_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD3_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD3_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_HPD4_INT_CONTROL=bitpacked record + DC_HPD4_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD4_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD4_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD4_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD4_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_HPD5_INT_CONTROL=bitpacked record + DC_HPD5_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD5_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD5_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD5_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD5_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_HPD6_INT_CONTROL=bitpacked record + DC_HPD6_INT_ACK :bit1; + RESERVED0 :bit7; + DC_HPD6_INT_POLARITY:bit1; + RESERVED1 :bit7; + DC_HPD6_INT_EN :bit1; + RESERVED2 :bit3; + DC_HPD6_RX_INT_ACK :bit1; + RESERVED3 :bit3; + DC_HPD6_RX_INT_EN :bit1; + RESERVED4 :bit7; + end; + + TDC_I2C_DDCVGA_SETUP=bitpacked record + DC_I2C_DDCVGA_DATA_DRIVE_EN :bit1; + DC_I2C_DDCVGA_DATA_DRIVE_SEL :bit1; + RESERVED0 :bit2; + DC_I2C_DDCVGA_EDID_DETECT_ENABLE :bit1; + DC_I2C_DDCVGA_EDID_DETECT_MODE :bit1; + DC_I2C_DDCVGA_ENABLE :bit1; + DC_I2C_DDCVGA_CLK_DRIVE_EN :bit1; + DC_I2C_DDCVGA_INTRA_BYTE_DELAY :bit8; + DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY:bit8; + DC_I2C_DDCVGA_TIME_LIMIT :bit8; + end; + + TDC_I2C_DDCVGA_SPEED=bitpacked record + DC_I2C_DDCVGA_THRESHOLD :bit2; + RESERVED0 :bit2; + DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL:bit1; + RESERVED1 :bit11; + DC_I2C_DDCVGA_PRESCALE :bit16; + end; + + TDC_I2C_TRANSACTION0=bitpacked record + DC_I2C_RW0 :bit1; + RESERVED0 :bit7; + DC_I2C_STOP_ON_NACK0:bit1; + RESERVED1 :bit3; + DC_I2C_START0 :bit1; + DC_I2C_STOP0 :bit1; + RESERVED2 :bit2; + DC_I2C_COUNT0 :bit8; + RESERVED3 :bit8; + end; + + TDC_I2C_TRANSACTION1=bitpacked record + DC_I2C_RW1 :bit1; + RESERVED0 :bit7; + DC_I2C_STOP_ON_NACK1:bit1; + RESERVED1 :bit3; + DC_I2C_START1 :bit1; + DC_I2C_STOP1 :bit1; + RESERVED2 :bit2; + DC_I2C_COUNT1 :bit8; + RESERVED3 :bit8; + end; + + TDC_I2C_TRANSACTION2=bitpacked record + DC_I2C_RW2 :bit1; + RESERVED0 :bit7; + DC_I2C_STOP_ON_NACK2:bit1; + RESERVED1 :bit3; + DC_I2C_START2 :bit1; + DC_I2C_STOP2 :bit1; + RESERVED2 :bit2; + DC_I2C_COUNT2 :bit8; + RESERVED3 :bit8; + end; + + TDC_I2C_TRANSACTION3=bitpacked record + DC_I2C_RW3 :bit1; + RESERVED0 :bit7; + DC_I2C_STOP_ON_NACK3:bit1; + RESERVED1 :bit3; + DC_I2C_START3 :bit1; + DC_I2C_STOP3 :bit1; + RESERVED2 :bit2; + DC_I2C_COUNT3 :bit8; + RESERVED3 :bit8; + end; + + TDC_PGFSM_CONFIG_REG=bit32; + + TDC_TEST_DEBUG_INDEX=bitpacked record + DC_TEST_DEBUG_INDEX :bit8; + DC_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDIDT_DBR_WEIGHT8_11=bitpacked record + WEIGHT8 :bit8; + WEIGHT9 :bit8; + WEIGHT10:bit8; + WEIGHT11:bit8; + end; + + TDIDT_TCP_WEIGHT8_11=bitpacked record + WEIGHT8 :bit8; + WEIGHT9 :bit8; + WEIGHT10:bit8; + WEIGHT11:bit8; + end; + + TDIG_OUTPUT_CRC_CNTL=bitpacked record + DIG_OUTPUT_CRC_EN :bit1; + RESERVED0 :bit3; + DIG_OUTPUT_CRC_LINK_SEL:bit1; + RESERVED1 :bit3; + DIG_OUTPUT_CRC_DATA_SEL:bit2; + RESERVED2 :bit22; + end; + + TDIG_TEST_DEBUG_DATA=bit32; + + TDPG_TEST_DEBUG_DATA=bit32; + + TDP_HBR2_EYE_PATTERN=bitpacked record + DP_HBR2_EYE_PATTERN_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TDP_TEST_DEBUG_INDEX=bitpacked record + DP_TEST_DEBUG_INDEX :bit8; + DP_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDVO_CRC2_SIG_RESULT=bitpacked record + DVO_CRC2_SIG_RESULT:bit27; + RESERVED0 :bit5; + end; + + TDVO_TEST_DEBUG_DATA=bit32; + + TFBC_DEBUG_CSR_RDATA=bit32; + + TFBC_DEBUG_CSR_WDATA=bit32; + + TFBC_TEST_DEBUG_DATA=bit32; + + TFMT_TEST_DEBUG_DATA=bit32; + + TGAMMA_CORR_LUT_DATA=bitpacked record + GAMMA_CORR_LUT_DATA:bit19; + RESERVED0 :bit13; + end; + + TGAMUT_REMAP_C11_C12=bitpacked record + GAMUT_REMAP_C11:bit16; + GAMUT_REMAP_C12:bit16; + end; + + TGAMUT_REMAP_C13_C14=bitpacked record + GAMUT_REMAP_C13:bit16; + GAMUT_REMAP_C14:bit16; + end; + + TGAMUT_REMAP_C21_C22=bitpacked record + GAMUT_REMAP_C21:bit16; + GAMUT_REMAP_C22:bit16; + end; + + TGAMUT_REMAP_C23_C24=bitpacked record + GAMUT_REMAP_C23:bit16; + GAMUT_REMAP_C24:bit16; + end; + + TGAMUT_REMAP_C31_C32=bitpacked record + GAMUT_REMAP_C31:bit16; + GAMUT_REMAP_C32:bit16; + end; + + TGAMUT_REMAP_C33_C34=bitpacked record + GAMUT_REMAP_C33:bit16; + GAMUT_REMAP_C34:bit16; + end; + + TGAMUT_REMAP_CONTROL=bitpacked record + GRPH_GAMUT_REMAP_MODE:bit2; + RESERVED0 :bit2; + OVL_GAMUT_REMAP_MODE :bit2; + RESERVED1 :bit26; + end; + + TGB_MACROTILE_MODE10=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE11=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE12=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE13=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE14=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGB_MACROTILE_MODE15=bitpacked record + BANK_WIDTH :bit2; + BANK_HEIGHT :bit2; + MACRO_TILE_ASPECT:bit2; + NUM_BANKS :bit2; + RESERVED0 :bit24; + end; + + TGCK_DFS_BYPASS_CNTL=bitpacked record + BYPASSECLK :bit1; + BYPASSLCLK :bit1; + BYPASSEVCLK :bit1; + BYPASSDCLK :bit1; + BYPASSVCLK :bit1; + BYPASSDISPCLK :bit1; + BYPASSDPREFCLK :bit1; + BYPASSACLK :bit1; + BYPASSADIVCLK :bit1; + BYPASSPSPCLK :bit1; + BYPASSSAMCLK :bit1; + BYPASSSCLK :bit1; + USE_SPLL_BYPASS_EN:bit1; + BYPASSMCLK :bit1; + RESERVED0 :bit18; + end; + + TGCK_PLL_TEST_CNTL_2=bitpacked record + RESERVED0 :bit17; + TEST_COUNT:bit15; + end; + + TGC_USER_PRIM_CONFIG=bitpacked record + RESERVED0 :bit16; + INACTIVE_IA :bit2; + RESERVED1 :bit6; + INACTIVE_VGT_PA:bit4; + RESERVED2 :bit4; + end; + TGDS_CS_CTXSW_STATUS=bitpacked record R :bit1; W :bit1; UNUSED:bit30; end; + TGDS_GRBM_SECDED_CNT=bitpacked record + SEC:bit16; + DED:bit16; + end; + TGDS_OA_CGPG_RESTORE=bitpacked record VMID :bit8; MEID :bit4; @@ -7783,6 +35327,71 @@ type TGDS_PERFCOUNTER3_LO=bit32; + TGENERIC_I2C_CONTROL=bitpacked record + GENERIC_I2C_GO :bit1; + GENERIC_I2C_SOFT_RESET :bit1; + GENERIC_I2C_SEND_RESET :bit1; + GENERIC_I2C_ENABLE :bit1; + RESERVED0 :bit27; + GENERIC_I2C_DBG_REF_SEL:bit1; + end; + + TGLOBAL_CAPABILITIES=bitpacked record + SIXTY_FOUR_BIT_ADDRESS_SUPPORTED :bit1; + NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS :bit2; + NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED:bit5; + NUMBER_OF_INPUT_STREAMS_SUPPORTED :bit4; + NUMBER_OF_OUTPUT_STREAMS_SUPPORTED :bit4; + RESERVED0 :bit16; + end; + + TGMCON_RENG_RAM_DATA=bit32; + + TGPIOPAD_INT_STAT_AK=bitpacked record + GPIO_INT_STAT_AK_0 :bit1; + GPIO_INT_STAT_AK_1 :bit1; + GPIO_INT_STAT_AK_2 :bit1; + GPIO_INT_STAT_AK_3 :bit1; + GPIO_INT_STAT_AK_4 :bit1; + GPIO_INT_STAT_AK_5 :bit1; + GPIO_INT_STAT_AK_6 :bit1; + GPIO_INT_STAT_AK_7 :bit1; + GPIO_INT_STAT_AK_8 :bit1; + GPIO_INT_STAT_AK_9 :bit1; + GPIO_INT_STAT_AK_10 :bit1; + GPIO_INT_STAT_AK_11 :bit1; + GPIO_INT_STAT_AK_12 :bit1; + GPIO_INT_STAT_AK_13 :bit1; + GPIO_INT_STAT_AK_14 :bit1; + GPIO_INT_STAT_AK_15 :bit1; + GPIO_INT_STAT_AK_16 :bit1; + GPIO_INT_STAT_AK_17 :bit1; + GPIO_INT_STAT_AK_18 :bit1; + GPIO_INT_STAT_AK_19 :bit1; + GPIO_INT_STAT_AK_20 :bit1; + GPIO_INT_STAT_AK_21 :bit1; + GPIO_INT_STAT_AK_22 :bit1; + GPIO_INT_STAT_AK_23 :bit1; + GPIO_INT_STAT_AK_24 :bit1; + GPIO_INT_STAT_AK_25 :bit1; + GPIO_INT_STAT_AK_26 :bit1; + GPIO_INT_STAT_AK_27 :bit1; + GPIO_INT_STAT_AK_28 :bit1; + RESERVED0 :bit2; + SW_INITIATED_INT_STAT_AK:bit1; + end; + + TGPIOPAD_INT_STAT_EN=bitpacked record + GPIO_INT_STAT_EN :bit29; + RESERVED0 :bit2; + SW_INITIATED_INT_STAT_EN:bit1; + end; + + TGPIOPAD_SW_INT_STAT=bitpacked record + SW_INT_STAT:bit1; + RESERVED0 :bit31; + end; + TGRBM_DEBUG_SNAPSHOT=bitpacked record CPF_RDY :bit1; CPG_RDY :bit1; @@ -7816,6 +35425,768 @@ type RESERVED1 :bit19; end; + TGRPH_COMPRESS_PITCH=bitpacked record + RESERVED0 :bit6; + GRPH_COMPRESS_PITCH:bit11; + RESERVED1 :bit15; + end; + + TGRPH_FLIP_RATE_CNTL=bitpacked record + GRPH_FLIP_RATE :bit3; + GRPH_FLIP_RATE_ENABLE:bit1; + RESERVED0 :bit28; + end; + + THDP_NONSURFACE_BASE=bitpacked record + NONSURF_BASE:bit28; + RESERVED0 :bit4; + end; + + THDP_NONSURFACE_INFO=bitpacked record + NONSURF_ADDR_TYPE :bit1; + NONSURF_ARRAY_MODE :bit4; + NONSURF_ENDIAN :bit2; + NONSURF_PIXEL_SIZE :bit3; + NONSURF_SAMPLE_NUM :bit3; + NONSURF_SAMPLE_SIZE :bit2; + NONSURF_PRIV :bit1; + NONSURF_TILE_COMPACT :bit1; + NONSURF_TILE_SPLIT :bit3; + NONSURF_NUM_BANKS :bit2; + NONSURF_BANK_WIDTH :bit2; + NONSURF_BANK_HEIGHT :bit2; + NONSURF_MACRO_TILE_ASPECT :bit2; + NONSURF_MICRO_TILE_MODE :bit3; + NONSURF_SLICE_TILE_MAX_MSB:bit1; + end; + + THDP_NONSURFACE_SIZE=bitpacked record + NONSURF_PITCH_TILE_MAX:bit10; + NONSURF_SLICE_TILE_MAX:bit20; + RESERVED0 :bit2; + end; + + THDP_OUTSTANDING_REQ=bitpacked record + WRITE_REQ:bit8; + READ_REQ :bit8; + RESERVED0:bit16; + end; + + THDP_XDP_D2H_RSVD_10=bit32; + + THDP_XDP_D2H_RSVD_11=bit32; + + THDP_XDP_D2H_RSVD_12=bit32; + + THDP_XDP_D2H_RSVD_13=bit32; + + THDP_XDP_D2H_RSVD_14=bit32; + + THDP_XDP_D2H_RSVD_15=bit32; + + THDP_XDP_D2H_RSVD_16=bit32; + + THDP_XDP_D2H_RSVD_17=bit32; + + THDP_XDP_D2H_RSVD_18=bit32; + + THDP_XDP_D2H_RSVD_19=bit32; + + THDP_XDP_D2H_RSVD_20=bit32; + + THDP_XDP_D2H_RSVD_21=bit32; + + THDP_XDP_D2H_RSVD_22=bit32; + + THDP_XDP_D2H_RSVD_23=bit32; + + THDP_XDP_D2H_RSVD_24=bit32; + + THDP_XDP_D2H_RSVD_25=bit32; + + THDP_XDP_D2H_RSVD_26=bit32; + + THDP_XDP_D2H_RSVD_27=bit32; + + THDP_XDP_D2H_RSVD_28=bit32; + + THDP_XDP_D2H_RSVD_29=bit32; + + THDP_XDP_D2H_RSVD_30=bit32; + + THDP_XDP_D2H_RSVD_31=bit32; + + THDP_XDP_D2H_RSVD_32=bit32; + + THDP_XDP_D2H_RSVD_33=bit32; + + THDP_XDP_D2H_RSVD_34=bit32; + + THDP_XDP_HDP_IPH_CFG=bitpacked record + HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE :bit6; + HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE :bit6; + HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING:bit1; + HDP_IPH_CFG_P2P_RD_EN :bit1; + RESERVED0 :bit18; + end; + + THDP_XDP_P2P_BAR_CFG=bitpacked record + P2P_BAR_CFG_ADDR_SIZE:bit4; + P2P_BAR_CFG_BAR_FROM :bit2; + RESERVED0 :bit26; + end; + + TIH_VF_RB_BIF_STATUS=bitpacked record + RB_FULL_VF :bit16; + BIF_INTERRUPT_LINE_VF:bit16; + end; + + TINPUT_CSC_C11_C12_A=bitpacked record + INPUT_CSC_C11_A:bit16; + INPUT_CSC_C12_A:bit16; + end; + + TINPUT_CSC_C11_C12_B=bitpacked record + INPUT_CSC_C11_B:bit16; + INPUT_CSC_C12_B:bit16; + end; + + TINPUT_CSC_C13_C14_A=bitpacked record + INPUT_CSC_C13_A:bit16; + INPUT_CSC_C14_A:bit16; + end; + + TINPUT_CSC_C13_C14_B=bitpacked record + INPUT_CSC_C13_B:bit16; + INPUT_CSC_C14_B:bit16; + end; + + TINPUT_CSC_C21_C22_A=bitpacked record + INPUT_CSC_C21_A:bit16; + INPUT_CSC_C22_A:bit16; + end; + + TINPUT_CSC_C21_C22_B=bitpacked record + INPUT_CSC_C21_B:bit16; + INPUT_CSC_C22_B:bit16; + end; + + TINPUT_CSC_C23_C24_A=bitpacked record + INPUT_CSC_C23_A:bit16; + INPUT_CSC_C24_A:bit16; + end; + + TINPUT_CSC_C23_C24_B=bitpacked record + INPUT_CSC_C23_B:bit16; + INPUT_CSC_C24_B:bit16; + end; + + TINPUT_CSC_C31_C32_A=bitpacked record + INPUT_CSC_C31_A:bit16; + INPUT_CSC_C32_A:bit16; + end; + + TINPUT_CSC_C31_C32_B=bitpacked record + INPUT_CSC_C31_B:bit16; + INPUT_CSC_C32_B:bit16; + end; + + TINPUT_CSC_C33_C34_A=bitpacked record + INPUT_CSC_C33_A:bit16; + INPUT_CSC_C34_A:bit16; + end; + + TINPUT_CSC_C33_C34_B=bitpacked record + INPUT_CSC_C33_B:bit16; + INPUT_CSC_C34_B:bit16; + end; + + TINPUT_GAMMA_CONTROL=bitpacked record + GRPH_INPUT_GAMMA_MODE:bit2; + RESERVED0 :bit2; + OVL_INPUT_GAMMA_MODE :bit2; + RESERVED1 :bit26; + end; + + TLBV_BLACK_KEYER_G_Y=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_G_Y:bit12; + RESERVED1 :bit16; + end; + + TLBV_KEYER_COLOR_G_Y=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_G_Y:bit12; + RESERVED1 :bit16; + end; + + TLBV_TEST_DEBUG_DATA=bit32; + + TLBV_VLINE_START_END=bitpacked record + VLINE_START:bit14; + RESERVED0 :bit2; + VLINE_END :bit15; + VLINE_INV :bit1; + end; + + TLB_BLACK_KEYER_B_CB=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLB_BLACK_KEYER_R_CR=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_R_CR:bit12; + RESERVED1 :bit16; + end; + + TLB_KEYER_COLOR_B_CB=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLB_KEYER_COLOR_CTRL=bitpacked record + LB_KEYER_COLOR_EN :bit1; + RESERVED0 :bit7; + LB_KEYER_COLOR_REP_EN:bit1; + RESERVED1 :bit23; + end; + + TLB_KEYER_COLOR_R_CR=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_R_CR:bit12; + RESERVED1 :bit16; + end; + + TLB_TEST_DEBUG_INDEX=bitpacked record + LB_TEST_DEBUG_INDEX :bit8; + LB_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TLB_VLINE2_START_END=bitpacked record + VLINE2_START:bit14; + RESERVED0 :bit2; + VLINE2_END :bit15; + VLINE2_INV :bit1; + end; + + TLVTMA_PWRSEQ_DELAY1=bitpacked record + LVTMA_PWRUP_DELAY1:bit8; + LVTMA_PWRUP_DELAY2:bit8; + LVTMA_PWRDN_DELAY1:bit8; + LVTMA_PWRDN_DELAY2:bit8; + end; + + TLVTMA_PWRSEQ_DELAY2=bitpacked record + LVTMA_PWRDN_MIN_LENGTH :bit8; + LVTMA_PWRUP_DELAY3 :bit8; + LVTMA_PWRDN_DELAY3 :bit8; + LVTMA_VARY_BL_OVERRIDE_EN:bit1; + RESERVED0 :bit7; + end; + + TMASTER_COMM_CMD_REG=bitpacked record + MASTER_COMM_CMD_REG_BYTE0:bit8; + MASTER_COMM_CMD_REG_BYTE1:bit8; + MASTER_COMM_CMD_REG_BYTE2:bit8; + MASTER_COMM_CMD_REG_BYTE3:bit8; + end; + + TMC_ARB_DRAM_TIMING2=bitpacked record + RAS2RAS :bit8; + RP :bit8; + WRPLUSRP :bit8; + BUS_TURN :bit5; + RESERVED0:bit3; + end; + + TMC_ARB_GDEC_RD_CNTL=bitpacked record + PAGEBIT0 :bit4; + PAGEBIT1 :bit4; + USE_RANK :bit1; + USE_RSNO :bit1; + REM_DEFAULT_GRP:bit4; + RESERVED0 :bit18; + end; + + TMC_ARB_GDEC_WR_CNTL=bitpacked record + PAGEBIT0 :bit4; + PAGEBIT1 :bit4; + USE_RANK :bit1; + USE_RSNO :bit1; + REM_DEFAULT_GRP:bit4; + RESERVED0 :bit18; + end; + + TMC_ARB_GECC2_DEBUG2=bitpacked record + PERIOD :bit8; + ERR0_START:bit8; + ERR1_START:bit8; + ERR2_START:bit8; + end; + + TMC_ARB_GECC2_STATUS=bitpacked record + CORR_STS0 :bit1; + UNCORR_STS0 :bit1; + FED_STS0 :bit1; + RSVD0 :bit1; + CORR_STS1 :bit1; + UNCORR_STS1 :bit1; + FED_STS1 :bit1; + RSVD1 :bit1; + CORR_CLEAR0 :bit1; + UNCORR_CLEAR0 :bit1; + FED_CLEAR0 :bit1; + RSVD2 :bit1; + CORR_CLEAR1 :bit1; + UNCORR_CLEAR1 :bit1; + FED_CLEAR1 :bit1; + RSVD3 :bit1; + RMWRD_CORR_STS0 :bit1; + RMWRD_UNCORR_STS0 :bit1; + RSVD4 :bit2; + RMWRD_CORR_STS1 :bit1; + RMWRD_UNCORR_STS1 :bit1; + RSVD5 :bit2; + RMWRD_CORR_CLEAR0 :bit1; + RMWRD_UNCORR_CLEAR0:bit1; + RSVD6 :bit2; + RMWRD_CORR_CLEAR1 :bit1; + RMWRD_UNCORR_CLEAR1:bit1; + RESERVED0 :bit2; + end; + + TMC_ARB_GRUB_PROMOTE=bitpacked record + URGENT_RD :bit8; + URGENT_WR :bit8; + PROMOTE_RD:bit8; + PROMOTE_WR:bit8; + end; + + TMC_ARB_HARSH_CTL_RD=bitpacked record + FORCE_HIGHEST :bit8; + HARSH_RR :bit1; + BANK_AGE_ONLY :bit1; + USE_LEGACY_HARSH:bit1; + BWCNT_CATCHUP :bit1; + ST_MODE :bit2; + FORCE_STALL :bit8; + PERF_MON_SEL :bit3; + RESERVED0 :bit7; + end; + + TMC_ARB_HARSH_CTL_WR=bitpacked record + FORCE_HIGHEST :bit8; + HARSH_RR :bit1; + BANK_AGE_ONLY :bit1; + USE_LEGACY_HARSH:bit1; + BWCNT_CATCHUP :bit1; + ST_MODE :bit2; + FORCE_STALL :bit8; + PERF_MON_SEL :bit3; + RESERVED0 :bit7; + end; + + TMC_ARB_RET_CREDITS2=bitpacked record + ACP_WR :bit8; + NECKDOWN_CNTR_EN_RD :bit1; + NECKDOWN_CNTR_EN_WR :bit1; + ACP_RDRET_URG :bit1; + HDP_RDRET_URG :bit1; + NECKDOWN_CNTR_MONITOR_RD:bit1; + NECKDOWN_CNTR_MONITOR_WR:bit1; + DISABLE_DISP_RDY_RD :bit1; + DISABLE_ACP_RDY_WR :bit1; + RDRET_CREDIT_MED :bit8; + RESERVED0 :bit8; + end; + + TMC_ARB_WTM_GRPWT_RD=bitpacked record + GRP0 :bit2; + GRP1 :bit2; + GRP2 :bit2; + GRP3 :bit2; + GRP4 :bit2; + GRP5 :bit2; + GRP6 :bit2; + GRP7 :bit2; + GRP_EXT :bit8; + RESERVED0:bit8; + end; + + TMC_ARB_WTM_GRPWT_WR=bitpacked record + GRP0 :bit2; + GRP1 :bit2; + GRP2 :bit2; + GRP3 :bit2; + GRP4 :bit2; + GRP5 :bit2; + GRP6 :bit2; + GRP7 :bit2; + GRP_EXT :bit8; + RESERVED0:bit8; + end; + + TMC_BIST_RDATA_WORD0=bit32; + + TMC_BIST_RDATA_WORD1=bit32; + + TMC_BIST_RDATA_WORD2=bit32; + + TMC_BIST_RDATA_WORD3=bit32; + + TMC_BIST_RDATA_WORD4=bit32; + + TMC_BIST_RDATA_WORD5=bit32; + + TMC_BIST_RDATA_WORD6=bit32; + + TMC_BIST_RDATA_WORD7=bit32; + + TMC_CITF_INT_CREDITS=bitpacked record + REMRDRET :bit6; + RESERVED0 :bit6; + CNTR_RD_HUB_LP:bit6; + CNTR_RD_HUB_HP:bit6; + CNTR_RD_LCL :bit6; + RESERVED1 :bit2; + end; + + TMC_CITF_WTM_RD_CNTL=bitpacked record + GROUP0_DECREMENT:bit3; + GROUP1_DECREMENT:bit3; + GROUP2_DECREMENT:bit3; + GROUP3_DECREMENT:bit3; + GROUP4_DECREMENT:bit3; + GROUP5_DECREMENT:bit3; + GROUP6_DECREMENT:bit3; + GROUP7_DECREMENT:bit3; + DISABLE_REMOTE :bit1; + DISABLE_LOCAL :bit1; + RESERVED0 :bit6; + end; + + TMC_CITF_WTM_WR_CNTL=bitpacked record + GROUP0_DECREMENT:bit3; + GROUP1_DECREMENT:bit3; + GROUP2_DECREMENT:bit3; + GROUP3_DECREMENT:bit3; + GROUP4_DECREMENT:bit3; + GROUP5_DECREMENT:bit3; + GROUP6_DECREMENT:bit3; + GROUP7_DECREMENT:bit3; + DISABLE_REMOTE :bit1; + DISABLE_LOCAL :bit1; + RESERVED0 :bit6; + end; + + TMC_CITF_XTRA_ENABLE=bitpacked record + CB1_RD :bit1; + CB1_WR :bit1; + DB1_RD :bit1; + DB1_WR :bit1; + TC2_RD :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + ARB_DBG :bit4; + TC2_WR :bit1; + CB0_CONNECT_CNTL :bit2; + DB0_CONNECT_CNTL :bit2; + CB1_CONNECT_CNTL :bit2; + DB1_CONNECT_CNTL :bit2; + TC0_CONNECT_CNTL :bit2; + TC1_CONNECT_CNTL :bit2; + CB0_CID_CNTL_ENABLE:bit1; + DB0_CID_CNTL_ENABLE:bit1; + CB1_CID_CNTL_ENABLE:bit1; + DB1_CID_CNTL_ENABLE:bit1; + TC2_REPAIR_ENABLE :bit2; + RESERVED3 :bit1; + end; + + TMC_GRUB_TCB_DATA_HI=bit32; + + TMC_GRUB_TCB_DATA_LO=bit32; + + TMC_HUB_MISC_FRAMING=bit32; + + TMC_HUB_RDREQ_SAMMSP=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + RESERVED0 :bit15; + end; + + TMC_HUB_RDREQ_STATUS=bitpacked record + SIP_AVAIL :bit1; + MCDW_RD_AVAIL :bit1; + MCDX_RD_AVAIL :bit1; + MCDY_RD_AVAIL :bit1; + MCDZ_RD_AVAIL :bit1; + MCDS_RD_AVAIL :bit1; + MCDT_RD_AVAIL :bit1; + MCDU_RD_AVAIL :bit1; + MCDV_RD_AVAIL :bit1; + GBL0_VM_FULL :bit1; + GBL0_STOR_FULL :bit1; + GBL0_BYPASS_STOR_FULL:bit1; + GBL1_VM_FULL :bit1; + GBL1_STOR_FULL :bit1; + GBL1_BYPASS_STOR_FULL:bit1; + PWRXPRESS_ERR :bit1; + RESERVED0 :bit16; + end; + + TMC_HUB_WDP_CREDITS2=bitpacked record + STOR0_PRI:bit8; + STOR1_PRI:bit8; + VM2 :bit8; + VM3 :bit8; + end; + + TMC_HUB_WDP_CREDITS3=bitpacked record + STOR0_URG:bit8; + STOR1_URG:bit8; + RESERVED0:bit16; + end; + + TMC_HUB_WDP_ISP_CCPU=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_WDP_WTM_CNTL=bitpacked record + GROUP0_DECREMENT:bit3; + GROUP1_DECREMENT:bit3; + GROUP2_DECREMENT:bit3; + GROUP3_DECREMENT:bit3; + GROUP4_DECREMENT:bit3; + GROUP5_DECREMENT:bit3; + GROUP6_DECREMENT:bit3; + GROUP7_DECREMENT:bit3; + RESERVED0 :bit8; + end; + + TMC_HUB_WRRET_STATUS=bitpacked record + MCDW_AVAIL:bit1; + MCDX_AVAIL:bit1; + MCDY_AVAIL:bit1; + MCDZ_AVAIL:bit1; + MCDS_AVAIL:bit1; + MCDT_AVAIL:bit1; + MCDU_AVAIL:bit1; + MCDV_AVAIL:bit1; + RESERVED0 :bit24; + end; + + TMC_RPB_CID_QUEUE_EX=bitpacked record + START :bit1; + OFFSET :bit5; + RESERVED0:bit26; + end; + + TMC_RPB_CID_QUEUE_RD=bitpacked record + CLIENT_ID :bit8; + WRITE_QUEUE:bit2; + READ_QUEUE :bit2; + RESERVED0 :bit20; + end; + + TMC_RPB_CID_QUEUE_WR=bitpacked record + CLIENT_ID :bit8; + UPDATE_MODE:bit1; + WRITE_QUEUE:bit2; + READ_QUEUE :bit2; + UPDATE :bit1; + RESERVED0 :bit18; + end; + + TMC_SEQ_MISC_TIMING2=bitpacked record + PA2RDATA :bit3; + PA2WDATA :bit3; + FAW :bit5; + RESERVED0:bit3; + RESERVED1:bit3; + T32AW :bit4; + TWDATATR :bit4; + RESERVED2:bit7; + end; + + TMC_SEQ_RD_CTL_D0_LP=bitpacked record + RCV_DLY :bit3; + RCV_EXT :bit5; + RST_SEL :bit2; + RST_HLD :bit4; + RESERVED0:bit1; + RESERVED1:bit1; + RBS_DLY :bit5; + RESERVED2:bit2; + RESERVED3:bit1; + RESERVED4:bit8; + end; + + TMC_SEQ_RD_CTL_D1_LP=bitpacked record + RCV_DLY :bit3; + RCV_EXT :bit5; + RST_SEL :bit2; + RST_HLD :bit4; + RESERVED0:bit1; + RESERVED1:bit1; + RBS_DLY :bit5; + RESERVED2:bit2; + RESERVED3:bit1; + RESERVED4:bit8; + end; + + TMC_SEQ_SUP_DEC_STAT=bit32; + + TMC_SEQ_SUP_GP0_STAT=bit32; + + TMC_SEQ_SUP_GP1_STAT=bit32; + + TMC_SEQ_SUP_GP2_STAT=bit32; + + TMC_SEQ_SUP_GP3_STAT=bit32; + + TMC_SEQ_SUP_PGM_STAT=bit32; + + TMC_SEQ_WR_CTL_D0_LP=bitpacked record + DAT_DLY :bit5; + DQS_DLY :bit5; + DQS_XTR :bit1; + OEN_DLY :bit5; + OEN_EXT :bit4; + OEN_SEL :bit2; + CMD_DLY :bit1; + ADR_DLY :bit1; + RESERVED0:bit8; + end; + + TMC_SEQ_WR_CTL_D1_LP=bitpacked record + DAT_DLY :bit5; + DQS_DLY :bit5; + DQS_XTR :bit1; + OEN_DLY :bit5; + OEN_EXT :bit4; + OEN_SEL :bit2; + CMD_DLY :bit1; + ADR_DLY :bit1; + RESERVED0:bit8; + end; + + TMC_SHARED_VF_ENABLE=bitpacked record + VF_ENABLE:bit1; + RESERVED0:bit31; + end; + + TMC_VM_DC_WRITE_CNTL=bitpacked record + DC_WRITE_HIT_REGION_0_MODE:bit2; + DC_WRITE_HIT_REGION_1_MODE:bit2; + DC_WRITE_HIT_REGION_2_MODE:bit2; + DC_WRITE_HIT_REGION_3_MODE:bit2; + DC_MEMORY_WRITE_LOCAL :bit1; + DC_MEMORY_WRITE_SYSTEM :bit1; + RESERVED0 :bit22; + end; + + TMC_VM_MARC_LEN_HI_0=bitpacked record + MARC_LEN_HI_0:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_LEN_HI_1=bitpacked record + MARC_LEN_HI_1:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_LEN_HI_2=bitpacked record + MARC_LEN_HI_2:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_LEN_HI_3=bitpacked record + MARC_LEN_HI_3:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_LEN_LO_0=bitpacked record + RESERVED0 :bit12; + MARC_LEN_LO_0:bit20; + end; + + TMC_VM_MARC_LEN_LO_1=bitpacked record + RESERVED0 :bit12; + MARC_LEN_LO_1:bit20; + end; + + TMC_VM_MARC_LEN_LO_2=bitpacked record + RESERVED0 :bit12; + MARC_LEN_LO_2:bit20; + end; + + TMC_VM_MARC_LEN_LO_3=bitpacked record + RESERVED0 :bit12; + MARC_LEN_LO_3:bit20; + end; + + TMC_XPB_CLG_EXTRA_RD=bitpacked record + CMP0 :bit8; + MSK0 :bit8; + VLD0 :bit1; + CMP1 :bit8; + VLD1 :bit1; + RESERVED0:bit6; + end; + + TMVP_INBAND_CNTL_CAP=bitpacked record + MVP_IGNOR_INBAND_CNTL :bit1; + RESERVED0 :bit3; + MVP_PASSING_INBAND_CNTL_EN:bit1; + RESERVED1 :bit3; + MVP_INBAND_CNTL_CHAR_CAP :bit24; + end; + + TMVP_TEST_DEBUG_DATA=bit32; + + TOVL_STEREOSYNC_FLIP=bitpacked record + OVL_STEREOSYNC_FLIP_EN :bit1; + RESERVED0 :bit7; + OVL_STEREOSYNC_FLIP_MODE :bit2; + RESERVED1 :bit6; + OVL_PRIMARY_SURFACE_PENDING :bit1; + OVL_SECONDARY_SURFACE_PENDING:bit1; + RESERVED2 :bit10; + OVL_STEREOSYNC_SELECT_DISABLE:bit1; + RESERVED3 :bit3; + end; + + TOVL_SURFACE_ADDRESS=bitpacked record + OVL_DFQ_ENABLE :bit1; + RESERVED0 :bit7; + OVL_SURFACE_ADDRESS:bit24; + end; + TPA_CL_VPORT_XOFFSET=bit32; TPA_CL_VPORT_YOFFSET=bit32; @@ -7942,6 +36313,690 @@ type WINDOW_Y_OFFSET:bit16; end; + TPB0_PIF_LANE0_OVRD2=bitpacked record + GANGMODE_0 :bit3; + FREQDIV_0 :bit2; + LINKSPEED_0 :bit2; + TWOSYMENABLE_0 :bit1; + TXPWR_0 :bit3; + TXPGENABLE_0 :bit2; + RXPWR_0 :bit3; + RXPGENABLE_0 :bit2; + ELECIDLEDETEN_0:bit1; + ENABLEFOM_0 :bit1; + REQUESTFOM_0 :bit1; + RESPONSEMODE_0 :bit1; + REQUESTTRK_0 :bit1; + REQUESTTRN_0 :bit1; + COEFFICIENTID_0:bit2; + COEFFICIENT_0 :bit6; + end; + + TPB0_PIF_LANE1_OVRD2=bitpacked record + GANGMODE_1 :bit3; + FREQDIV_1 :bit2; + LINKSPEED_1 :bit2; + TWOSYMENABLE_1 :bit1; + TXPWR_1 :bit3; + TXPGENABLE_1 :bit2; + RXPWR_1 :bit3; + RXPGENABLE_1 :bit2; + ELECIDLEDETEN_1:bit1; + ENABLEFOM_1 :bit1; + REQUESTFOM_1 :bit1; + RESPONSEMODE_1 :bit1; + REQUESTTRK_1 :bit1; + REQUESTTRN_1 :bit1; + COEFFICIENTID_1:bit2; + COEFFICIENT_1 :bit6; + end; + + TPB0_PIF_LANE2_OVRD2=bitpacked record + GANGMODE_2 :bit3; + FREQDIV_2 :bit2; + LINKSPEED_2 :bit2; + TWOSYMENABLE_2 :bit1; + TXPWR_2 :bit3; + TXPGENABLE_2 :bit2; + RXPWR_2 :bit3; + RXPGENABLE_2 :bit2; + ELECIDLEDETEN_2:bit1; + ENABLEFOM_2 :bit1; + REQUESTFOM_2 :bit1; + RESPONSEMODE_2 :bit1; + REQUESTTRK_2 :bit1; + REQUESTTRN_2 :bit1; + COEFFICIENTID_2:bit2; + COEFFICIENT_2 :bit6; + end; + + TPB0_PIF_LANE3_OVRD2=bitpacked record + GANGMODE_3 :bit3; + FREQDIV_3 :bit2; + LINKSPEED_3 :bit2; + TWOSYMENABLE_3 :bit1; + TXPWR_3 :bit3; + TXPGENABLE_3 :bit2; + RXPWR_3 :bit3; + RXPGENABLE_3 :bit2; + ELECIDLEDETEN_3:bit1; + ENABLEFOM_3 :bit1; + REQUESTFOM_3 :bit1; + RESPONSEMODE_3 :bit1; + REQUESTTRK_3 :bit1; + REQUESTTRN_3 :bit1; + COEFFICIENTID_3:bit2; + COEFFICIENT_3 :bit6; + end; + + TPB0_PIF_LANE4_OVRD2=bitpacked record + GANGMODE_4 :bit3; + FREQDIV_4 :bit2; + LINKSPEED_4 :bit2; + TWOSYMENABLE_4 :bit1; + TXPWR_4 :bit3; + TXPGENABLE_4 :bit2; + RXPWR_4 :bit3; + RXPGENABLE_4 :bit2; + ELECIDLEDETEN_4:bit1; + ENABLEFOM_4 :bit1; + REQUESTFOM_4 :bit1; + RESPONSEMODE_4 :bit1; + REQUESTTRK_4 :bit1; + REQUESTTRN_4 :bit1; + COEFFICIENTID_4:bit2; + COEFFICIENT_4 :bit6; + end; + + TPB0_PIF_LANE5_OVRD2=bitpacked record + GANGMODE_5 :bit3; + FREQDIV_5 :bit2; + LINKSPEED_5 :bit2; + TWOSYMENABLE_5 :bit1; + TXPWR_5 :bit3; + TXPGENABLE_5 :bit2; + RXPWR_5 :bit3; + RXPGENABLE_5 :bit2; + ELECIDLEDETEN_5:bit1; + ENABLEFOM_5 :bit1; + REQUESTFOM_5 :bit1; + RESPONSEMODE_5 :bit1; + REQUESTTRK_5 :bit1; + REQUESTTRN_5 :bit1; + COEFFICIENTID_5:bit2; + COEFFICIENT_5 :bit6; + end; + + TPB0_PIF_LANE6_OVRD2=bitpacked record + GANGMODE_6 :bit3; + FREQDIV_6 :bit2; + LINKSPEED_6 :bit2; + TWOSYMENABLE_6 :bit1; + TXPWR_6 :bit3; + TXPGENABLE_6 :bit2; + RXPWR_6 :bit3; + RXPGENABLE_6 :bit2; + ELECIDLEDETEN_6:bit1; + ENABLEFOM_6 :bit1; + REQUESTFOM_6 :bit1; + RESPONSEMODE_6 :bit1; + REQUESTTRK_6 :bit1; + REQUESTTRN_6 :bit1; + COEFFICIENTID_6:bit2; + COEFFICIENT_6 :bit6; + end; + + TPB0_PIF_LANE7_OVRD2=bitpacked record + GANGMODE_7 :bit3; + FREQDIV_7 :bit2; + LINKSPEED_7 :bit2; + TWOSYMENABLE_7 :bit1; + TXPWR_7 :bit3; + TXPGENABLE_7 :bit2; + RXPWR_7 :bit3; + RXPGENABLE_7 :bit2; + ELECIDLEDETEN_7:bit1; + ENABLEFOM_7 :bit1; + REQUESTFOM_7 :bit1; + RESPONSEMODE_7 :bit1; + REQUESTTRK_7 :bit1; + REQUESTTRN_7 :bit1; + COEFFICIENTID_7:bit2; + COEFFICIENT_7 :bit6; + end; + + TPB1_PIF_LANE0_OVRD2=bitpacked record + GANGMODE_0 :bit3; + FREQDIV_0 :bit2; + LINKSPEED_0 :bit2; + TWOSYMENABLE_0 :bit1; + TXPWR_0 :bit3; + TXPGENABLE_0 :bit2; + RXPWR_0 :bit3; + RXPGENABLE_0 :bit2; + ELECIDLEDETEN_0:bit1; + ENABLEFOM_0 :bit1; + REQUESTFOM_0 :bit1; + RESPONSEMODE_0 :bit1; + REQUESTTRK_0 :bit1; + REQUESTTRN_0 :bit1; + COEFFICIENTID_0:bit2; + COEFFICIENT_0 :bit6; + end; + + TPB1_PIF_LANE1_OVRD2=bitpacked record + GANGMODE_1 :bit3; + FREQDIV_1 :bit2; + LINKSPEED_1 :bit2; + TWOSYMENABLE_1 :bit1; + TXPWR_1 :bit3; + TXPGENABLE_1 :bit2; + RXPWR_1 :bit3; + RXPGENABLE_1 :bit2; + ELECIDLEDETEN_1:bit1; + ENABLEFOM_1 :bit1; + REQUESTFOM_1 :bit1; + RESPONSEMODE_1 :bit1; + REQUESTTRK_1 :bit1; + REQUESTTRN_1 :bit1; + COEFFICIENTID_1:bit2; + COEFFICIENT_1 :bit6; + end; + + TPB1_PIF_LANE2_OVRD2=bitpacked record + GANGMODE_2 :bit3; + FREQDIV_2 :bit2; + LINKSPEED_2 :bit2; + TWOSYMENABLE_2 :bit1; + TXPWR_2 :bit3; + TXPGENABLE_2 :bit2; + RXPWR_2 :bit3; + RXPGENABLE_2 :bit2; + ELECIDLEDETEN_2:bit1; + ENABLEFOM_2 :bit1; + REQUESTFOM_2 :bit1; + RESPONSEMODE_2 :bit1; + REQUESTTRK_2 :bit1; + REQUESTTRN_2 :bit1; + COEFFICIENTID_2:bit2; + COEFFICIENT_2 :bit6; + end; + + TPB1_PIF_LANE3_OVRD2=bitpacked record + GANGMODE_3 :bit3; + FREQDIV_3 :bit2; + LINKSPEED_3 :bit2; + TWOSYMENABLE_3 :bit1; + TXPWR_3 :bit3; + TXPGENABLE_3 :bit2; + RXPWR_3 :bit3; + RXPGENABLE_3 :bit2; + ELECIDLEDETEN_3:bit1; + ENABLEFOM_3 :bit1; + REQUESTFOM_3 :bit1; + RESPONSEMODE_3 :bit1; + REQUESTTRK_3 :bit1; + REQUESTTRN_3 :bit1; + COEFFICIENTID_3:bit2; + COEFFICIENT_3 :bit6; + end; + + TPB1_PIF_LANE4_OVRD2=bitpacked record + GANGMODE_4 :bit3; + FREQDIV_4 :bit2; + LINKSPEED_4 :bit2; + TWOSYMENABLE_4 :bit1; + TXPWR_4 :bit3; + TXPGENABLE_4 :bit2; + RXPWR_4 :bit3; + RXPGENABLE_4 :bit2; + ELECIDLEDETEN_4:bit1; + ENABLEFOM_4 :bit1; + REQUESTFOM_4 :bit1; + RESPONSEMODE_4 :bit1; + REQUESTTRK_4 :bit1; + REQUESTTRN_4 :bit1; + COEFFICIENTID_4:bit2; + COEFFICIENT_4 :bit6; + end; + + TPB1_PIF_LANE5_OVRD2=bitpacked record + GANGMODE_5 :bit3; + FREQDIV_5 :bit2; + LINKSPEED_5 :bit2; + TWOSYMENABLE_5 :bit1; + TXPWR_5 :bit3; + TXPGENABLE_5 :bit2; + RXPWR_5 :bit3; + RXPGENABLE_5 :bit2; + ELECIDLEDETEN_5:bit1; + ENABLEFOM_5 :bit1; + REQUESTFOM_5 :bit1; + RESPONSEMODE_5 :bit1; + REQUESTTRK_5 :bit1; + REQUESTTRN_5 :bit1; + COEFFICIENTID_5:bit2; + COEFFICIENT_5 :bit6; + end; + + TPB1_PIF_LANE6_OVRD2=bitpacked record + GANGMODE_6 :bit3; + FREQDIV_6 :bit2; + LINKSPEED_6 :bit2; + TWOSYMENABLE_6 :bit1; + TXPWR_6 :bit3; + TXPGENABLE_6 :bit2; + RXPWR_6 :bit3; + RXPGENABLE_6 :bit2; + ELECIDLEDETEN_6:bit1; + ENABLEFOM_6 :bit1; + REQUESTFOM_6 :bit1; + RESPONSEMODE_6 :bit1; + REQUESTTRK_6 :bit1; + REQUESTTRN_6 :bit1; + COEFFICIENTID_6:bit2; + COEFFICIENT_6 :bit6; + end; + + TPB1_PIF_LANE7_OVRD2=bitpacked record + GANGMODE_7 :bit3; + FREQDIV_7 :bit2; + LINKSPEED_7 :bit2; + TWOSYMENABLE_7 :bit1; + TXPWR_7 :bit3; + TXPGENABLE_7 :bit2; + RXPWR_7 :bit3; + RXPGENABLE_7 :bit2; + ELECIDLEDETEN_7:bit1; + ENABLEFOM_7 :bit1; + REQUESTFOM_7 :bit1; + RESPONSEMODE_7 :bit1; + REQUESTTRK_7 :bit1; + REQUESTTRN_7 :bit1; + COEFFICIENTID_7:bit2; + COEFFICIENT_7 :bit6; + end; + + TPCIE_LC_FORCE_COEFF=bitpacked record + LC_FORCE_COEFF :bit1; + LC_FORCE_PRE_CURSOR :bit6; + LC_FORCE_CURSOR :bit6; + LC_FORCE_POST_CURSOR :bit6; + LC_3X3_COEFF_SEARCH_EN:bit1; + LC_PRESET_10_EN :bit1; + RESERVED0 :bit11; + end; + + TPCIE_PORT_VC_STATUS=bitpacked record + VC_ARB_TABLE_STATUS:bit1; + RESERVED0 :bit31; + end; + + TPCIE_PRBS_ERRCNT_10=bit32; + + TPCIE_PRBS_ERRCNT_11=bit32; + + TPCIE_PRBS_ERRCNT_12=bit32; + + TPCIE_PRBS_ERRCNT_13=bit32; + + TPCIE_PRBS_ERRCNT_14=bit32; + + TPCIE_PRBS_ERRCNT_15=bit32; + + TPCIE_PRBS_HI_BITCNT=bitpacked record + PRBS_HI_BITCNT:bit8; + RESERVED0 :bit24; + end; + + TPCIE_PRBS_LO_BITCNT=bit32; + + TPCIE_PWR_BUDGET_CAP=bitpacked record + SYSTEM_ALLOCATED:bit1; + RESERVED0 :bit31; + end; + + TPCIE_RXDET_OVERRIDE=bitpacked record + RxDetOvrVal:bit16; + RxDetOvrEn :bit1; + RESERVED0 :bit15; + end; + + TPIXCLK0_RESYNC_CNTL=bitpacked record + PIXCLK0_RESYNC_ENABLE:bit1; + RESERVED0 :bit3; + DCCG_DEEP_COLOR_CNTL0:bit2; + RESERVED1 :bit26; + end; + + TPIXCLK1_RESYNC_CNTL=bitpacked record + PIXCLK1_RESYNC_ENABLE:bit1; + RESERVED0 :bit3; + DCCG_DEEP_COLOR_CNTL1:bit2; + RESERVED1 :bit26; + end; + + TPIXCLK2_RESYNC_CNTL=bitpacked record + PIXCLK2_RESYNC_ENABLE:bit1; + RESERVED0 :bit3; + DCCG_DEEP_COLOR_CNTL2:bit2; + RESERVED1 :bit26; + end; + + TPPLL_DEBUG_MUX_CNTL=bitpacked record + DEBUG_BUS_MUX_SEL:bit5; + RESERVED0 :bit27; + end; + + TPWR_PCC_GPIO_SELECT=bit32; + + TRLC_GPU_IOV_SCH_INT=bit32; + + TRLC_LB_INIT_CU_MASK=bit32; + + TRLC_PERFCOUNTER0_HI=bit32; + + TRLC_PERFCOUNTER0_LO=bit32; + + TRLC_PERFCOUNTER1_HI=bit32; + + TRLC_PERFCOUNTER1_LO=bit32; + + TRLC_SRM_GPM_COMMAND=bitpacked record + OP :bit1; + INDEX_CNTL :bit1; + INDEX_CNTL_NUM:bit3; + SIZE :bit12; + START_OFFSET :bit12; + RESERVED1 :bit2; + DEST_MEMORY :bit1; + end; + + TSAM_IH_EXT_ERR_INTR=bitpacked record + UVD :bit1; + VCE :bit1; + ISP :bit1; + RESERVED0:bit29; + end; + + TSCLV_VIEWPORT_START=bitpacked record + VIEWPORT_Y_START:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START:bit14; + RESERVED1 :bit2; + end; + + TSCL_COEF_RAM_SELECT=bitpacked record + SCL_C_RAM_TAP_PAIR_IDX:bit4; + RESERVED0 :bit4; + SCL_C_RAM_PHASE :bit4; + RESERVED1 :bit4; + SCL_C_RAM_FILTER_TYPE :bit3; + RESERVED2 :bit13; + end; + + TSCL_F_SHARP_CONTROL=bitpacked record + SCL_HF_SHARP_SCALE_FACTOR:bit3; + RESERVED0 :bit1; + SCL_HF_SHARP_EN :bit1; + RESERVED1 :bit3; + SCL_VF_SHARP_SCALE_FACTOR:bit3; + RESERVED2 :bit1; + SCL_VF_SHARP_EN :bit1; + RESERVED3 :bit19; + end; + + TSCL_TEST_DEBUG_DATA=bit32; + + TSDMA0_ACTIVE_FCN_ID=bitpacked record + VFID :bit4; + RESERVED0:bit27; + VF :bit1; + end; + + TSDMA0_GFX_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA0_GFX_DUMMY_REG=bit32; + + TSDMA0_GFX_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_GFX_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA0_GFX_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA0_PUB_REG_TYPE0=bitpacked record + SDMA0_UCODE_ADDR :bit1; + SDMA0_UCODE_DATA :bit1; + SDMA0_POWER_CNTL :bit1; + SDMA0_CLK_CTRL :bit1; + SDMA0_CNTL :bit1; + SDMA0_CHICKEN_BITS :bit1; + SDMA0_TILING_CONFIG :bit1; + SDMA0_HASH :bit1; + RESERVED0 :bit1; + SDMA0_SEM_WAIT_FAIL_TIMER_CNTL:bit1; + SDMA0_RB_RPTR_FETCH :bit1; + SDMA0_IB_OFFSET_FETCH :bit1; + SDMA0_PROGRAM :bit1; + SDMA0_STATUS_REG :bit1; + SDMA0_STATUS1_REG :bit1; + SDMA0_RD_BURST_CNTL :bit1; + RESERVED_16 :bit1; + RESERVED_17 :bit1; + SDMA0_F32_CNTL :bit1; + SDMA0_FREEZE :bit1; + SDMA0_PHASE0_QUANTUM :bit1; + SDMA0_PHASE1_QUANTUM :bit1; + SDMA_POWER_GATING :bit1; + SDMA_PGFSM_CONFIG :bit1; + SDMA_PGFSM_WRITE :bit1; + SDMA_PGFSM_READ :bit1; + SDMA0_EDC_CONFIG :bit1; + SDMA0_BA_THRESHOLD :bit1; + SDMA0_DEVICE_ID :bit1; + RESERVED1 :bit1; + RESERVED :bit2; + end; + + TSDMA0_PUB_REG_TYPE1=bitpacked record + SDMA0_VM_CNTL :bit1; + SDMA0_VM_CTX_LO :bit1; + SDMA0_VM_CTX_HI :bit1; + SDMA0_STATUS2_REG:bit1; + SDMA0_VM_CTX_CNTL:bit1; + RESERVED :bit27; + end; + + TSDMA0_RB_RPTR_FETCH=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA0_RD_BURST_CNTL=bitpacked record + RD_BURST :bit2; + RESERVED0:bit30; + end; + + TSDMA0_RLC0_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA0_RLC1_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA0_TILING_CONFIG=bitpacked record + RESERVED0 :bit4; + PIPE_INTERLEAVE_SIZE:bit3; + RESERVED1 :bit25; + end; + + TSDMA1_ACTIVE_FCN_ID=bitpacked record + VFID :bit4; + RESERVED0:bit27; + VF :bit1; + end; + + TSDMA1_GFX_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA1_GFX_DUMMY_REG=bit32; + + TSDMA1_GFX_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_GFX_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA1_GFX_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA1_PUB_REG_TYPE0=bitpacked record + SDMA1_UCODE_ADDR :bit1; + SDMA1_UCODE_DATA :bit1; + SDMA1_POWER_CNTL :bit1; + SDMA1_CLK_CTRL :bit1; + SDMA1_CNTL :bit1; + SDMA1_CHICKEN_BITS :bit1; + SDMA1_TILING_CONFIG :bit1; + SDMA1_HASH :bit1; + RESERVED0 :bit1; + SDMA1_SEM_WAIT_FAIL_TIMER_CNTL:bit1; + SDMA1_RB_RPTR_FETCH :bit1; + SDMA1_IB_OFFSET_FETCH :bit1; + SDMA1_PROGRAM :bit1; + SDMA1_STATUS_REG :bit1; + SDMA1_STATUS1_REG :bit1; + SDMA1_RD_BURST_CNTL :bit1; + RESERVED_16 :bit1; + RESERVED_17 :bit1; + SDMA1_F32_CNTL :bit1; + SDMA1_FREEZE :bit1; + SDMA1_PHASE0_QUANTUM :bit1; + SDMA1_PHASE1_QUANTUM :bit1; + VOID_REG0 :bit4; + SDMA1_EDC_CONFIG :bit1; + SDMA1_BA_THRESHOLD :bit1; + SDMA1_DEVICE_ID :bit1; + RESERVED1 :bit1; + RESERVED :bit2; + end; + + TSDMA1_PUB_REG_TYPE1=bitpacked record + SDMA1_VM_CNTL :bit1; + SDMA1_VM_CTX_LO :bit1; + SDMA1_VM_CTX_HI :bit1; + SDMA1_STATUS2_REG:bit1; + SDMA1_VM_CTX_CNTL:bit1; + RESERVED :bit27; + end; + + TSDMA1_RB_RPTR_FETCH=bitpacked record + RESERVED0:bit2; + OFFSET :bit30; + end; + + TSDMA1_RD_BURST_CNTL=bitpacked record + RD_BURST :bit2; + RESERVED0:bit30; + end; + + TSDMA1_RLC0_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA1_RLC1_DOORBELL=bitpacked record + OFFSET :bit21; + RESERVED0:bit7; + ENABLE :bit1; + RESERVED1:bit1; + CAPTURED :bit1; + RESERVED2:bit1; + end; + + TSDMA1_TILING_CONFIG=bitpacked record + RESERVED0 :bit4; + PIPE_INTERLEAVE_SIZE:bit3; + RESERVED1 :bit25; + end; + + TSEM_MAILBOX_CONTROL=bitpacked record + SIDEPORT_ENABLE :bit8; + HOSTPORT_ENABLE :bit8; + SIDEPORT_ENABLE_EXTRA:bit8; + HOSTPORT_ENABLE_EXTRA:bit8; + end; + + TSLAVE_COMM_CNTL_REG=bitpacked record + SLAVE_COMM_INTERRUPT :bit1; + RESERVED0 :bit7; + COMM_PORT_MSG_TO_HOST_IN_PROGRESS:bit1; + RESERVED1 :bit23; + end; + + TSMC_IND_ACCESS_CNTL=bitpacked record + AUTO_INCREMENT_IND_0 :bit1; + AUTO_INCREMENT_IND_1 :bit1; + AUTO_INCREMENT_IND_2 :bit1; + AUTO_INCREMENT_IND_3 :bit1; + AUTO_INCREMENT_IND_4 :bit1; + AUTO_INCREMENT_IND_5 :bit1; + AUTO_INCREMENT_IND_6 :bit1; + AUTO_INCREMENT_IND_7 :bit1; + AUTO_INCREMENT_IND_8 :bit1; + AUTO_INCREMENT_IND_9 :bit1; + AUTO_INCREMENT_IND_10:bit1; + AUTO_INCREMENT_IND_11:bit1; + AUTO_INCREMENT_IND_12:bit1; + AUTO_INCREMENT_IND_13:bit1; + AUTO_INCREMENT_IND_14:bit1; + AUTO_INCREMENT_IND_15:bit1; + RESERVED0 :bit16; + end; + + TSMU_MP1_RLC2MP_RESP=bit32; + TSPI_GDBG_TRAP_DATA0=bit32; TSPI_GDBG_TRAP_DATA1=bit32; @@ -8155,6 +37210,26 @@ type RESERVED0 :bit28; end; + TSPMI_SRAM_CLK_GATER=bitpacked record + RESERVED0:bit1; + RESERVED1:bit10; + RESERVED2:bit21; + end; + + TSQ_DEBUG_CTRL_LOCAL=bitpacked record + UNUSED :bit8; + RESERVED0:bit24; + end; + + TSQ_DEBUG_STS_GLOBAL=bitpacked record + BUSY :bit1; + INTERRUPT_MSG_BUSY:bit1; + RESERVED0 :bit2; + WAVE_LEVEL_SH0 :bit12; + WAVE_LEVEL_SH1 :bit12; + RESERVED1 :bit4; + end; + TSQ_PERFCOUNTER10_HI=bit32; TSQ_PERFCOUNTER10_LO=bit32; @@ -8198,6 +37273,145 @@ type SH1_MASK:bit16; end; + TSRBM_CREDIT_RECOVER=bitpacked record + CREDIT_RECOVER_BIF :bit1; + CREDIT_RECOVER_SMU :bit1; + CREDIT_RECOVER_DC :bit1; + CREDIT_RECOVER_GIONB:bit1; + CREDIT_RECOVER_ACP :bit1; + CREDIT_RECOVER_XDMA :bit1; + CREDIT_RECOVER_ODE :bit1; + CREDIT_RECOVER_REGBB:bit1; + CREDIT_RECOVER_VP8 :bit1; + CREDIT_RECOVER_GRBM :bit1; + CREDIT_RECOVER_UVD :bit1; + CREDIT_RECOVER_VCE0 :bit1; + CREDIT_RECOVER_VCE1 :bit1; + CREDIT_RECOVER_ISP :bit1; + CREDIT_RECOVER_SAM :bit1; + CREDIT_RECOVER_MCB :bit1; + CREDIT_RECOVER_MCC0 :bit1; + CREDIT_RECOVER_MCC1 :bit1; + CREDIT_RECOVER_MCC2 :bit1; + CREDIT_RECOVER_MCC3 :bit1; + CREDIT_RECOVER_MCC4 :bit1; + CREDIT_RECOVER_MCC5 :bit1; + CREDIT_RECOVER_MCC6 :bit1; + CREDIT_RECOVER_MCC7 :bit1; + CREDIT_RECOVER_MCD0 :bit1; + CREDIT_RECOVER_MCD1 :bit1; + CREDIT_RECOVER_MCD2 :bit1; + CREDIT_RECOVER_MCD3 :bit1; + CREDIT_RECOVER_MCD4 :bit1; + CREDIT_RECOVER_MCD5 :bit1; + CREDIT_RECOVER_MCD6 :bit1; + CREDIT_RECOVER_MCD7 :bit1; + end; + + TSRBM_DEBUG_SNAPSHOT=bitpacked record + MCB_RDY :bit1; + GIONB_RDY :bit1; + SMU_RDY :bit1; + SAMMSP_RDY:bit1; + ACP_RDY :bit1; + GRBM_RDY :bit1; + DC_RDY :bit1; + BIF_RDY :bit1; + XDMA_RDY :bit1; + UVD_RDY :bit1; + VP8_RDY :bit1; + REGBB_RDY :bit1; + ODE_RDY :bit1; + MCD7_RDY :bit1; + MCD6_RDY :bit1; + MCD5_RDY :bit1; + MCD4_RDY :bit1; + MCD3_RDY :bit1; + MCD2_RDY :bit1; + MCD1_RDY :bit1; + MCD0_RDY :bit1; + MCC7_RDY :bit1; + MCC6_RDY :bit1; + MCC5_RDY :bit1; + MCC4_RDY :bit1; + MCC3_RDY :bit1; + MCC2_RDY :bit1; + MCC1_RDY :bit1; + MCC0_RDY :bit1; + VCE0_RDY :bit1; + SAMSCP_RDY:bit1; + ISP_RDY :bit1; + end; + + TSRBM_DSM_TRIG_CNTL0=bitpacked record + DSM_TRIG_ADDR:bit16; + DSM_TRIG_OP :bit1; + RESERVED0 :bit15; + end; + + TSRBM_DSM_TRIG_CNTL1=bit32; + + TSRBM_DSM_TRIG_MASK0=bitpacked record + DSM_TRIG_ADDR_MASK:bit16; + DSM_TRIG_OP_MASK :bit1; + RESERVED0 :bit15; + end; + + TSRBM_DSM_TRIG_MASK1=bit32; + + TSRBM_ISP_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSRBM_SAM_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSRBM_SYS_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSRBM_UVD_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSRBM_VCE_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSRBM_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TSRBM_VP8_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSTATE_CHANGE_STATUS=bitpacked record + STATE_CHANGE_STATUS:bit1; + RESERVED0 :bit31; + end; + TTCA_PERFCOUNTER0_HI=bit32; TTCA_PERFCOUNTER0_LO=bit32; @@ -8253,6 +37467,240 @@ type TTCP_PERFCOUNTER3_LO=bit32; + TUNIPHY_IMPCAL_LINKA=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKA :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKA :bit1; + UNIPHY_CALOUT_ERROR_LINKA :bit1; + UNIPHY_CALOUT_ERROR_LINKA_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKA :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKA :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKA :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKA :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_IMPCAL_LINKB=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKB :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKB :bit1; + UNIPHY_CALOUT_ERROR_LINKB :bit1; + UNIPHY_CALOUT_ERROR_LINKB_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKB :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKB :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKB :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKB :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_IMPCAL_LINKC=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKC :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKC :bit1; + UNIPHY_CALOUT_ERROR_LINKC :bit1; + UNIPHY_CALOUT_ERROR_LINKC_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKC :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKC :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKC :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKC :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_IMPCAL_LINKD=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKD :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKD :bit1; + UNIPHY_CALOUT_ERROR_LINKD :bit1; + UNIPHY_CALOUT_ERROR_LINKD_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKD :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKD :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKD :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKD :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_IMPCAL_LINKE=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKE :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKE :bit1; + UNIPHY_CALOUT_ERROR_LINKE :bit1; + UNIPHY_CALOUT_ERROR_LINKE_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKE :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKE :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKE :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKE :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_IMPCAL_LINKF=bitpacked record + UNIPHY_IMPCAL_ENABLE_LINKF :bit1; + RESERVED0 :bit7; + UNIPHY_IMPCAL_CALOUT_LINKF :bit1; + UNIPHY_CALOUT_ERROR_LINKF :bit1; + UNIPHY_CALOUT_ERROR_LINKF_AK :bit1; + RESERVED1 :bit5; + UNIPHY_IMPCAL_VALUE_LINKF :bit4; + UNIPHY_IMPCAL_STEP_DELAY_LINKF :bit4; + UNIPHY_IMPCAL_OVERRIDE_LINKF :bit4; + UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF:bit1; + RESERVED2 :bit1; + UNIPHY_IMPCAL_SEL_LINKF :bit1; + RESERVED3 :bit1; + end; + + TUNIPHY_PLL_CONTROL1=bitpacked record + UNIPHY_PLL_ENABLE :bit1; + UNIPHY_PLL_RESET :bit1; + UNIPHY_PLL_EXT_RESET_EN :bit1; + UNIPHY_PLL_CLK_EN :bit1; + UNIPHY_PLL_CLKPH_EN :bit4; + UNIPHY_PLL_LF_CNTL :bit7; + RESERVED0 :bit1; + UNIPHY_PLL_BW_CNTL :bit8; + UNIPHY_PLL_TEST_BYPCLK_SRC :bit1; + UNIPHY_PLL_TEST_BYPCLK_EN :bit1; + UNIPHY_PLL_TEST_VCTL_ADC_EN:bit1; + RESERVED1 :bit1; + UNIPHY_VCO_MODE :bit2; + RESERVED2 :bit2; + end; + + TUNIPHY_PLL_CONTROL2=bitpacked record + UNIPHY_PLL_DISPCLK_MODE :bit2; + UNIPHY_DPLLSEL :bit2; + UNIPHY_IDCLK_SEL :bit1; + UNIPHY_IPCIE_REFCLK_SEL :bit1; + UNIPHY_IXTALIN_SEL :bit1; + RESERVED0 :bit1; + UNIPHY_PLL_REFCLK_SRC :bit3; + UNIPHY_PCIEREF_CLK_EN :bit1; + UNIPHY_IDCLK_EN :bit1; + UNIPHY_CLKINV :bit1; + RESERVED1 :bit2; + UNIPHY_PLL_VTOI_BIAS_CNTL :bit1; + RESERVED2 :bit2; + UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS:bit1; + UNIPHY_PDIVFRAC_SEL :bit1; + RESERVED3 :bit3; + UNIPHY_PLL_REFDIV :bit5; + UNIPHY_PDIV_SEL :bit3; + end; + + TUNP_GRPH_DFQ_STATUS=bitpacked record + GRPH_PRIMARY_DFQ_NUM_ENTRIES :bit4; + GRPH_SECONDARY_DFQ_NUM_ENTRIES:bit4; + GRPH_DFQ_RESET_FLAG :bit1; + GRPH_DFQ_RESET_ACK :bit1; + RESERVED0 :bit22; + end; + + TUNP_TEST_DEBUG_DATA=bit32; + + TUVD_CGC_UDEC_STATUS=bitpacked record + RE_SCLK :bit1; + RE_DCLK :bit1; + RE_VCLK :bit1; + CM_SCLK :bit1; + CM_DCLK :bit1; + CM_VCLK :bit1; + IT_SCLK :bit1; + IT_DCLK :bit1; + IT_VCLK :bit1; + DB_SCLK :bit1; + DB_DCLK :bit1; + DB_VCLK :bit1; + MP_SCLK :bit1; + MP_DCLK :bit1; + MP_VCLK :bit1; + JPEG_VCLK :bit1; + JPEG_SCLK :bit1; + JPEG2_VCLK:bit1; + JPEG2_SCLK:bit1; + RESERVED0 :bit13; + end; + + TUVD_LMI_RBC_IB_VMID=bitpacked record + IB_VMID :bit4; + RESERVED0:bit28; + end; + + TUVD_LMI_RBC_RB_VMID=bitpacked record + RB_VMID :bit4; + RESERVED0:bit28; + end; + + TUVD_SUVD_CGC_STATUS=bitpacked record + SRE_VCLK :bit1; + SRE_DCLK :bit1; + SIT_DCLK :bit1; + SMP_DCLK :bit1; + SCM_DCLK :bit1; + SDB_DCLK :bit1; + SRE_H264_VCLK:bit1; + SRE_HEVC_VCLK:bit1; + SIT_H264_DCLK:bit1; + SIT_HEVC_DCLK:bit1; + SCM_H264_DCLK:bit1; + SCM_HEVC_DCLK:bit1; + SDB_H264_DCLK:bit1; + SDB_HEVC_DCLK:bit1; + SCLR_DCLK :bit1; + UVD_SC :bit1; + RESERVED0 :bit16; + end; + + TVDDGFX_IDLE_CONTROL=bitpacked record + VDDGFX_IDLE_EN :bit1; + VDDGFX_IDLE_DETECT :bit1; + FORCE_VDDGFX_IDLE_EXIT:bit1; + SMC_VDDGFX_IDLE_STATE :bit1; + RESERVED0 :bit28; + end; + + TVGA25_PPLL_POST_DIV=bitpacked record + VGA25_PPLL_POST_DIV_PIXCLK:bit7; + RESERVED0 :bit1; + VGA25_PPLL_POST_DIV_DVOCLK:bit7; + RESERVED1 :bit1; + VGA25_PPLL_POST_DIV_IDCLK :bit7; + RESERVED2 :bit9; + end; + + TVGA28_PPLL_POST_DIV=bitpacked record + VGA28_PPLL_POST_DIV_PIXCLK:bit7; + RESERVED0 :bit1; + VGA28_PPLL_POST_DIV_DVOCLK:bit7; + RESERVED1 :bit1; + VGA28_PPLL_POST_DIV_IDCLK :bit7; + RESERVED2 :bit9; + end; + + TVGA41_PPLL_POST_DIV=bitpacked record + VGA41_PPLL_POST_DIV_PIXCLK:bit7; + RESERVED0 :bit1; + VGA41_PPLL_POST_DIV_DVOCLK:bit7; + RESERVED1 :bit1; + VGA41_PPLL_POST_DIV_IDCLK :bit7; + RESERVED2 :bit9; + end; + + TVGA_TEST_DEBUG_DATA=bit32; + TVGT_EVENT_INITIATOR=bitpacked record EVENT_TYPE :bit6; RESERVED0 :bit12; @@ -8315,6 +37763,439 @@ type TVGT_PERFCOUNTER3_LO=bit32; + TVM_CONTEXTS_DISABLE=bitpacked record + DISABLE_CONTEXT_0 :bit1; + DISABLE_CONTEXT_1 :bit1; + DISABLE_CONTEXT_2 :bit1; + DISABLE_CONTEXT_3 :bit1; + DISABLE_CONTEXT_4 :bit1; + DISABLE_CONTEXT_5 :bit1; + DISABLE_CONTEXT_6 :bit1; + DISABLE_CONTEXT_7 :bit1; + DISABLE_CONTEXT_8 :bit1; + DISABLE_CONTEXT_9 :bit1; + DISABLE_CONTEXT_10:bit1; + DISABLE_CONTEXT_11:bit1; + DISABLE_CONTEXT_12:bit1; + DISABLE_CONTEXT_13:bit1; + DISABLE_CONTEXT_14:bit1; + DISABLE_CONTEXT_15:bit1; + RESERVED0 :bit16; + end; + + TXDMA_MEM_POWER_CNTL=bitpacked record + XDMA_MEM_CORE_IDLE_STATE:bit2; + XDMA_MEM_IF_IDLE_STATE :bit2; + RESERVED0 :bit15; + XDMA_MEM_IF_PCIE_STATE :bit2; + XDMA_MEM_IF_PCIE_TRANS :bit1; + XDMA_MEM_IF_RD_STATE :bit2; + RESERVED1 :bit1; + XDMA_MEM_IF_RD_TRANS :bit1; + XDMA_MEM_IF_WR_STATE :bit2; + XDMA_MEM_IF_WR_TRANS :bit1; + XDMA_MEM_IF_BIF_STATE :bit2; + XDMA_MEM_IF_BIF_TRANS :bit1; + end; + + TXDMA_MSTR_PIPE_CNTL=bitpacked record + XDMA_MSTR_CACHE_LINES :bit8; + XDMA_MSTR_READ_REQUEST :bit1; + XDMA_MSTR_PIPE_FRAME_MODE :bit1; + XDMA_MSTR_PIPE_SOFT_RESET :bit1; + XDMA_MSTR_CACHE_INVALIDATE :bit1; + XDMA_MSTR_REQUEST_CHANNEL_ID:bit3; + XDMA_MSTR_FLIP_MODE :bit1; + XDMA_MSTR_REQUEST_MIN :bit8; + XDMA_MSTR_PIPE_ACTIVE :bit1; + XDMA_MSTR_PIPE_FLUSHING :bit1; + XDMA_MSTR_PIPE_FLIP_PENDING :bit1; + XDMA_MSTR_VSYNC_GSL_ENABLE :bit1; + XDMA_MSTR_SUPERAA_ENABLE :bit1; + XDMA_MSTR_HSYNC_GSL_GROUP :bit2; + XDMA_MSTR_GSL_GROUP_MASTER :bit1; + end; + + TABM_TEST_DEBUG_INDEX=bitpacked record + ABM_TEST_DEBUG_INDEX :bit8; + ABM_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TATC_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TATC_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TATC_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TATC_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TAUX_DPHY_RX_CONTROL0=bitpacked record + RESERVED0 :bit4; + AUX_RX_START_WINDOW :bit3; + RESERVED1 :bit1; + AUX_RX_RECEIVE_WINDOW :bit3; + RESERVED2 :bit1; + AUX_RX_HALF_SYM_DETECT_LEN :bit2; + RESERVED3 :bit2; + AUX_RX_TRANSITION_FILTER_EN :bit1; + AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT:bit1; + AUX_RX_ALLOW_BELOW_THRESHOLD_START :bit1; + AUX_RX_ALLOW_BELOW_THRESHOLD_STOP :bit1; + AUX_RX_PHASE_DETECT_LEN :bit2; + RESERVED4 :bit2; + AUX_RX_TIMEOUT_LEN :bit3; + RESERVED5 :bit1; + AUX_RX_DETECTION_THRESHOLD :bit3; + RESERVED6 :bit1; + end; + + TAUX_DPHY_RX_CONTROL1=bitpacked record + AUX_RX_PRECHARGE_SKIP:bit8; + RESERVED0 :bit24; + end; + + TAUX_GTC_SYNC_CONTROL=bitpacked record + AUX_GTC_SYNC_EN :bit1; + RESERVED0 :bit3; + AUX_GTC_SYNC_IMPCAL_EN :bit1; + RESERVED1 :bit3; + AUX_GTC_SYNC_IMPCAL_INTERVAL :bit4; + AUX_GTC_SYNC_LOCK_ACQ_PERIOD :bit4; + AUX_GTC_SYNC_LOCK_MAINT_PERIOD :bit3; + RESERVED2 :bit1; + AUX_GTC_SYNC_BLOCK_REQ :bit1; + RESERVED3 :bit1; + AUX_GTC_SYNC_INTERVAL_RESET_WINDOW :bit2; + AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT:bit2; + RESERVED4 :bit2; + AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT :bit4; + end; + + TAUX_TEST_DEBUG_INDEX=bitpacked record + AUX_TEST_DEBUG_INDEX :bit8; + AUX_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TAVSYNC_COUNTER_WRITE=bit32; + + TAZALIA_CRC0_CHANNEL0=bit32; + + TAZALIA_CRC0_CHANNEL1=bit32; + + TAZALIA_CRC0_CHANNEL2=bit32; + + TAZALIA_CRC0_CHANNEL3=bit32; + + TAZALIA_CRC0_CHANNEL4=bit32; + + TAZALIA_CRC0_CHANNEL5=bit32; + + TAZALIA_CRC0_CHANNEL6=bit32; + + TAZALIA_CRC0_CHANNEL7=bit32; + + TAZALIA_CRC0_CONTROL0=bitpacked record + CRC_EN :bit1; + RESERVED0 :bit3; + CRC_BLOCK_MODE :bit1; + RESERVED1 :bit3; + CRC_INSTANCE_SEL:bit3; + RESERVED2 :bit1; + CRC_SOURCE_SEL :bit1; + RESERVED3 :bit19; + end; + + TAZALIA_CRC0_CONTROL1=bit32; + + TAZALIA_CRC0_CONTROL2=bitpacked record + CRC_BLOCK_ITERATION:bit16; + RESERVED0 :bit16; + end; + + TAZALIA_CRC0_CONTROL3=bitpacked record + CRC_COMPLETE :bit1; + RESERVED0 :bit3; + CRC_BLOCK_COMPLETE_PHASE:bit1; + RESERVED1 :bit3; + CRC_CHANNEL_RESULT_SEL :bit3; + RESERVED2 :bit21; + end; + + TAZALIA_CRC1_CHANNEL0=bit32; + + TAZALIA_CRC1_CHANNEL1=bit32; + + TAZALIA_CRC1_CHANNEL2=bit32; + + TAZALIA_CRC1_CHANNEL3=bit32; + + TAZALIA_CRC1_CHANNEL4=bit32; + + TAZALIA_CRC1_CHANNEL5=bit32; + + TAZALIA_CRC1_CHANNEL6=bit32; + + TAZALIA_CRC1_CHANNEL7=bit32; + + TAZALIA_CRC1_CONTROL0=bitpacked record + CRC_EN :bit1; + RESERVED0 :bit3; + CRC_BLOCK_MODE :bit1; + RESERVED1 :bit3; + CRC_INSTANCE_SEL:bit3; + RESERVED2 :bit1; + CRC_SOURCE_SEL :bit1; + RESERVED3 :bit19; + end; + + TAZALIA_CRC1_CONTROL1=bit32; + + TAZALIA_CRC1_CONTROL2=bitpacked record + CRC_BLOCK_ITERATION:bit16; + RESERVED0 :bit16; + end; + + TAZALIA_CRC1_CONTROL3=bitpacked record + CRC_COMPLETE :bit1; + RESERVED0 :bit3; + CRC_BLOCK_COMPLETE_PHASE:bit1; + RESERVED1 :bit3; + CRC_CHANNEL_RESULT_SEL :bit3; + RESERVED2 :bit21; + end; + + TBIF_BACO_DEBUG_LATCH=bitpacked record + BIF_BACO_LATCH_FLG:bit1; + RESERVED0 :bit31; + end; + + TBIF_DEVFUNCNUM_LIST0=bitpacked record + DEVFUNC_ID0:bit8; + DEVFUNC_ID1:bit8; + DEVFUNC_ID2:bit8; + DEVFUNC_ID3:bit8; + end; + + TBIF_DEVFUNCNUM_LIST1=bitpacked record + DEVFUNC_ID4:bit8; + DEVFUNC_ID5:bit8; + DEVFUNC_ID6:bit8; + DEVFUNC_ID7:bit8; + end; + + TBIF_DOORBELL_APER_EN=bitpacked record + BIF_DOORBELL_APER_EN:bit1; + RESERVED0 :bit31; + end; + + TBIF_IMPCTL_TXCNTL_pd=bitpacked record + TX_ADJUST_pd :bit3; + TX_BIAS_HIGH_pd :bit1; + RESERVED0 :bit4; + LOWER_TX_ADJ_THRESH_pd:bit4; + LOWER_TX_ADJ_pd :bit1; + UPPER_TX_ADJ_THRESH_pd:bit4; + UPPER_TX_ADJ_pd :bit1; + TX_IMP_LOCKED_pd :bit1; + TX_IMP_READBACK_SEL_pd:bit1; + TX_IMP_READBACK_pd :bit4; + RESERVED1 :bit4; + TX_CMP_AMBIG_pd :bit1; + RESERVED2 :bit3; + end; + + TBIF_IMPCTL_TXCNTL_pu=bitpacked record + TX_ADJUST_pu :bit3; + TX_BIAS_HIGH_pu :bit1; + RESERVED0 :bit4; + LOWER_TX_ADJ_THRESH_pu:bit4; + LOWER_TX_ADJ_pu :bit1; + UPPER_TX_ADJ_THRESH_pu:bit4; + UPPER_TX_ADJ_pu :bit1; + TX_IMP_LOCKED_pu :bit1; + TX_IMP_READBACK_SEL_pu:bit1; + TX_IMP_READBACK_pu :bit4; + RESERVED1 :bit4; + TX_CMP_AMBIG_pu :bit1; + RESERVED2 :bit3; + end; + + TBIF_RFE_SOFTRST_CNTL=bitpacked record + REG_RST_rstTimer :bit16; + RESERVED0 :bit14; + REG_RST_softRstPropEn:bit1; + SoftRstReg :bit1; + end; + + TBIF_RFE_WARMRST_CNTL=bitpacked record + REG_RST_warmRstRfeEn:bit1; + REG_RST_warmRstImpEn:bit1; + RESERVED0 :bit30; + end; + + TBLND_TEST_DEBUG_DATA=bit32; + + TBL_PWM_GRP1_REG_LOCK=bitpacked record + BL_PWM_GRP1_REG_LOCK :bit1; + RESERVED0 :bit7; + BL_PWM_GRP1_REG_UPDATE_PENDING :bit1; + RESERVED1 :bit7; + BL_PWM_GRP1_UPDATE_AT_FRAME_START :bit1; + BL_PWM_GRP1_FRAME_START_DISP_SEL :bit3; + RESERVED2 :bit4; + BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN:bit1; + RESERVED3 :bit6; + BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN :bit1; + end; + + TBPHYC_DAC_MACRO_CNTL=bitpacked record + BPHYC_DAC_WHITE_LEVEL :bit2; + RESERVED0 :bit6; + BPHYC_DAC_WHITE_FINE_CONTROL:bit6; + RESERVED1 :bit2; + BPHYC_DAC_BANDGAP_ADJUSTMENT:bit6; + RESERVED2 :bit2; + BPHYC_DAC_ANALOG_MONITOR :bit4; + BPHYC_DAC_COREMON :bit1; + RESERVED3 :bit3; + end; + + TCC_SYS_RB_REDUNDANCY=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit7; + FAILED_RB0 :bit4; + EN_REDUNDANCY0:bit1; + RESERVED2 :bit3; + FAILED_RB1 :bit4; + EN_REDUNDANCY1:bit1; + RESERVED3 :bit11; + end; + + TCGTS_CU1_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU2_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU3_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU5_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU6_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU7_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU9_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCG_DISPLAY_GAP_CNTL2=bit32; + + TCG_MULT_THERMAL_CTRL=bitpacked record + TS_FILTER :bit4; + UNUSED :bit5; + THERMAL_RANGE_RST:bit1; + RESERVED0 :bit10; + TEMP_SEL :bit8; + THM_READY_CLEAR :bit1; + RESERVED1 :bit3; + end; + + TCLKREQB_PERF_COUNTER=bit32; + + TCNV_TEST_DEBUG_INDEX=bitpacked record + CNV_TEST_DEBUG_INDEX :bit8; + CNV_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TCOHER_DEST_BASE_HI_0=bit32; + + TCOHER_DEST_BASE_HI_1=bit32; + + TCOHER_DEST_BASE_HI_2=bit32; + + TCOHER_DEST_BASE_HI_3=bit32; + TCOMPUTE_NUM_THREAD_X=bitpacked record NUM_THREAD_FULL :bit16; NUM_THREAD_PARTIAL:bit16; @@ -8348,6 +38229,11 @@ type TCOMPUTE_USER_DATA_15=bit32; + TCONFIG_REG_APER_SIZE=bitpacked record + REG_APER_SIZE:bit20; + RESERVED0 :bit12; + end; + TCP_COHER_START_DELAY=bitpacked record START_DELAY_COUNT:bit6; RESERVED0 :bit26; @@ -8359,45 +38245,45 @@ type end; TCP_CPC_STALLED_STAT1=bitpacked record - MIU_RDREQ_FREE_STALL__SI__CI :bit1; - MIU_WRREQ_FREE_STALL__SI__CI :bit1; - RESERVED0 :bit1; - RCIU_TX_FREE_STALL :bit1; - RCIU_PRIV_VIOLATION :bit1; - RESERVED1 :bit1; - TCIU_TX_FREE_STALL :bit1; - RESERVED2 :bit1; - MEC1_DECODING_PACKET :bit1; - MEC1_WAIT_ON_RCIU :bit1; - MEC1_WAIT_ON_RCIU_READ :bit1; - MEC1_WAIT_ON_MC_READ__SI__CI :bit1; - MEC1_WAIT_ON_MC_WR_ACK__SI__CI:bit1; - MEC1_WAIT_ON_ROQ_DATA :bit1; - RESERVED3 :bit2; - MEC2_DECODING_PACKET :bit1; - MEC2_WAIT_ON_RCIU :bit1; - MEC2_WAIT_ON_RCIU_READ :bit1; - MEC2_WAIT_ON_MC_READ__SI__CI :bit1; - MEC2_WAIT_ON_MC_WR_ACK__SI__CI:bit1; - MEC2_WAIT_ON_ROQ_DATA :bit1; - ATCL2IU_WAITING_ON_FREE :bit1; - ATCL2IU_WAITING_ON_TAGS :bit1; - ATCL1_WAITING_ON_TRANS :bit1; - RESERVED4 :bit7; + MIU_RDREQ_FREE_STALL :bit1; + MIU_WRREQ_FREE_STALL :bit1; + RESERVED0 :bit1; + RCIU_TX_FREE_STALL :bit1; + RCIU_PRIV_VIOLATION :bit1; + RESERVED1 :bit1; + TCIU_TX_FREE_STALL :bit1; + RESERVED2 :bit1; + MEC1_DECODING_PACKET :bit1; + MEC1_WAIT_ON_RCIU :bit1; + MEC1_WAIT_ON_RCIU_READ :bit1; + MEC1_WAIT_ON_MC_READ :bit1; + MEC1_WAIT_ON_MC_WR_ACK :bit1; + MEC1_WAIT_ON_ROQ_DATA :bit1; + RESERVED3 :bit2; + MEC2_DECODING_PACKET :bit1; + MEC2_WAIT_ON_RCIU :bit1; + MEC2_WAIT_ON_RCIU_READ :bit1; + MEC2_WAIT_ON_MC_READ :bit1; + MEC2_WAIT_ON_MC_WR_ACK :bit1; + MEC2_WAIT_ON_ROQ_DATA :bit1; + ATCL2IU_WAITING_ON_FREE:bit1; + ATCL2IU_WAITING_ON_TAGS:bit1; + ATCL1_WAITING_ON_TRANS :bit1; + RESERVED4 :bit7; end; TCP_CPF_STALLED_STAT1=bitpacked record - RING_FETCHING_DATA :bit1; - INDR1_FETCHING_DATA :bit1; - INDR2_FETCHING_DATA :bit1; - STATE_FETCHING_DATA :bit1; - MIU_WAITING_ON_RDREQ_FREE__SI__CI:bit1; - TCIU_WAITING_ON_FREE :bit1; - TCIU_WAITING_ON_TAGS :bit1; - ATCL2IU_WAITING_ON_FREE :bit1; - ATCL2IU_WAITING_ON_TAGS :bit1; - ATCL1_WAITING_ON_TRANS :bit1; - RESERVED0 :bit22; + RING_FETCHING_DATA :bit1; + INDR1_FETCHING_DATA :bit1; + INDR2_FETCHING_DATA :bit1; + STATE_FETCHING_DATA :bit1; + MIU_WAITING_ON_RDREQ_FREE:bit1; + TCIU_WAITING_ON_FREE :bit1; + TCIU_WAITING_ON_TAGS :bit1; + ATCL2IU_WAITING_ON_FREE :bit1; + ATCL2IU_WAITING_ON_TAGS :bit1; + ATCL1_WAITING_ON_TRANS :bit1; + RESERVED0 :bit22; end; TCP_EOP_LAST_FENCE_HI=bit32; @@ -8450,6 +38336,74 @@ type EN :bit1; end; + TCP_RB_WPTR_POLL_CNTL=bitpacked record + POLL_FREQUENCY :bit16; + IDLE_POLL_COUNT:bit16; + end; + + TCRTC_BLACK_COLOR_EXT=bitpacked record + CRTC_BLACK_COLOR_B_CB_EXT:bit2; + RESERVED0 :bit6; + CRTC_BLACK_COLOR_G_Y_EXT :bit2; + RESERVED1 :bit6; + CRTC_BLACK_COLOR_R_CR_EXT:bit2; + RESERVED2 :bit14; + end; + + TCRTC_SNAPSHOT_STATUS=bitpacked record + CRTC_SNAPSHOT_OCCURRED :bit1; + CRTC_SNAPSHOT_CLEAR :bit1; + CRTC_SNAPSHOT_MANUAL_TRIGGER:bit1; + RESERVED0 :bit29; + end; + + TCRTC_STATUS_HV_COUNT=bitpacked record + CRTC_HV_COUNT:bit30; + RESERVED0 :bit2; + end; + + TCRTC_STATUS_POSITION=bitpacked record + CRTC_VERT_COUNT:bit14; + RESERVED0 :bit2; + CRTC_HORZ_COUNT:bit14; + RESERVED1 :bit2; + end; + + TCRTC_STATUS_VF_COUNT=bitpacked record + CRTC_VF_COUNT:bit30; + RESERVED0 :bit2; + end; + + TCRTC_TEST_DEBUG_DATA=bit32; + + TCRTC_V_TOTAL_CONTROL=bitpacked record + CRTC_V_TOTAL_MIN_SEL :bit1; + RESERVED0 :bit3; + CRTC_V_TOTAL_MAX_SEL :bit1; + RESERVED1 :bit3; + CRTC_FORCE_LOCK_ON_EVENT :bit1; + RESERVED2 :bit3; + CRTC_FORCE_LOCK_TO_MASTER_VSYNC:bit1; + RESERVED3 :bit2; + CRTC_SET_V_TOTAL_MIN_MASK_EN :bit1; + CRTC_SET_V_TOTAL_MIN_MASK :bit16; + end; + + TCUR2_SURFACE_ADDRESS=bit32; + + TDAC_CRC_SIG_RGB_MASK=bitpacked record + DAC_CRC_SIG_BLUE_MASK :bit10; + DAC_CRC_SIG_GREEN_MASK:bit10; + DAC_CRC_SIG_RED_MASK :bit10; + RESERVED0 :bit2; + end; + + TDAC_TEST_DEBUG_INDEX=bitpacked record + DAC_TEST_DEBUG_INDEX :bit8; + DAC_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + TDB_STENCILREFMASK_BF=bitpacked record STENCILTESTVAL_BF :bit8; STENCILMASK_BF :bit8; @@ -8459,6 +38413,308 @@ type TDB_STENCIL_READ_BASE=bit32; + TDCCG_TEST_DEBUG_DATA=bit32; + + TDCDEBUG_BUS_CLK1_SEL=bit32; + + TDCDEBUG_BUS_CLK2_SEL=bit32; + + TDCDEBUG_BUS_CLK3_SEL=bit32; + + TDCDEBUG_BUS_CLK4_SEL=bit32; + + TDCDEBUG_BUS_CLK5_SEL=bit32; + + TDCIO_TEST_DEBUG_DATA=bit32; + + TDCI_TEST_DEBUG_INDEX=bitpacked record + DCI_TEST_DEBUG_INDEX :bit8; + DCI_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDCO_TEST_DEBUG_INDEX=bitpacked record + DCO_TEST_DEBUG_INDEX :bit8; + DCO_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDCPG_TEST_DEBUG_DATA=bit32; + + TDCP_TEST_DEBUG_INDEX=bitpacked record + DCP_TEST_DEBUG_INDEX :bit8; + DCP_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDC_ABM1_ACE_THRES_12=bitpacked record + ABM1_ACE_THRES_1:bit10; + RESERVED0 :bit6; + ABM1_ACE_THRES_2:bit10; + RESERVED1 :bit5; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_ACE_THRES_34=bitpacked record + ABM1_ACE_THRES_3 :bit10; + RESERVED0 :bit6; + ABM1_ACE_THRES_4 :bit10; + RESERVED1 :bit2; + ABM1_ACE_IGNORE_MASTER_LOCK_EN :bit1; + ABM1_ACE_READBACK_DB_REG_VALUE_EN:bit1; + ABM1_ACE_DBUF_REG_UPDATE_PENDING :bit1; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_HG_MISC_CTRL=bitpacked record + ABM1_HG_NUM_OF_BINS_SEL :bit2; + RESERVED0 :bit6; + ABM1_HG_VMAX_SEL :bit1; + RESERVED1 :bit3; + ABM1_HG_FINE_MODE_BIN_SEL :bit1; + RESERVED2 :bit3; + ABM1_HG_BIN_BITWIDTH_SIZE_SEL :bit2; + RESERVED3 :bit2; + ABM1_OVR_SCAN_PIXEL_PROCESS_EN :bit1; + RESERVED4 :bit2; + ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN :bit1; + ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL :bit3; + RESERVED5 :bit1; + ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START:bit1; + ABM1_HGLS_IGNORE_MASTER_LOCK_EN :bit1; + ABM1_DBUF_HGLS_REG_UPDATE_PENDING :bit1; + ABM1_HGLS_REG_LOCK :bit1; + end; + + TDC_ABM1_HG_RESULT_10=bit32; + + TDC_ABM1_HG_RESULT_11=bit32; + + TDC_ABM1_HG_RESULT_12=bit32; + + TDC_ABM1_HG_RESULT_13=bit32; + + TDC_ABM1_HG_RESULT_14=bit32; + + TDC_ABM1_HG_RESULT_15=bit32; + + TDC_ABM1_HG_RESULT_16=bit32; + + TDC_ABM1_HG_RESULT_17=bit32; + + TDC_ABM1_HG_RESULT_18=bit32; + + TDC_ABM1_HG_RESULT_19=bit32; + + TDC_ABM1_HG_RESULT_20=bit32; + + TDC_ABM1_HG_RESULT_21=bit32; + + TDC_ABM1_HG_RESULT_22=bit32; + + TDC_ABM1_HG_RESULT_23=bit32; + + TDC_ABM1_HG_RESULT_24=bit32; + + TDC_GPIO_DVODATA_MASK=bitpacked record + DC_GPIO_DVODATA_MASK :bit24; + DC_GPIO_DVOCNTL_MASK :bit5; + DC_GPIO_DVOCLK_MASK :bit1; + DC_GPIO_MVP_DVOCNTL_MASK:bit2; + end; + + TDC_GPIO_GENERIC_MASK=bitpacked record + DC_GPIO_GENERICA_MASK :bit1; + DC_GPIO_GENERICA_PD_DIS:bit1; + DC_GPIO_GENERICA_RECV :bit1; + RESERVED0 :bit1; + DC_GPIO_GENERICB_MASK :bit1; + DC_GPIO_GENERICB_PD_DIS:bit1; + DC_GPIO_GENERICB_RECV :bit1; + RESERVED1 :bit1; + DC_GPIO_GENERICC_MASK :bit1; + DC_GPIO_GENERICC_PD_DIS:bit1; + DC_GPIO_GENERICC_RECV :bit1; + RESERVED2 :bit1; + DC_GPIO_GENERICD_MASK :bit1; + DC_GPIO_GENERICD_PD_DIS:bit1; + DC_GPIO_GENERICD_RECV :bit1; + RESERVED3 :bit1; + DC_GPIO_GENERICE_MASK :bit1; + DC_GPIO_GENERICE_PD_DIS:bit1; + DC_GPIO_GENERICE_RECV :bit1; + RESERVED4 :bit1; + DC_GPIO_GENERICF_MASK :bit1; + DC_GPIO_GENERICF_PD_DIS:bit1; + DC_GPIO_GENERICF_RECV :bit1; + RESERVED5 :bit1; + DC_GPIO_GENERICG_MASK :bit1; + DC_GPIO_GENERICG_PD_DIS:bit1; + DC_GPIO_GENERICG_RECV :bit1; + RESERVED6 :bit5; + end; + + TDC_LUT_WRITE_EN_MASK=bitpacked record + DC_LUT_WRITE_EN_MASK:bit3; + RESERVED0 :bit29; + end; + + TDC_PGCNTL_STATUS_REG=bitpacked record + SWREQ_RWOP_BUSY :bit1; + SWREQ_RWOP_FORCE :bit1; + IPREQ_IGNORE_STATUS:bit1; + RESERVED0 :bit13; + DCPG_ECO_DEBUG :bit16; + end; + + TDENORM_CLAMP_CONTROL=bitpacked record + DENORM_FACTOR:bit2; + RESERVED0 :bit30; + end; + + TDENTIST_DISPCLK_CNTL=bitpacked record + DENTIST_DISPCLK_WDIVIDER :bit7; + RESERVED0 :bit1; + DENTIST_DISPCLK_RDIVIDER :bit7; + DENTIST_DISPCLK_CHG_MODE :bit2; + DENTIST_DISPCLK_CHGTOG :bit1; + DENTIST_DISPCLK_DONETOG :bit1; + DENTIST_DISPCLK_CHG_DONE :bit1; + DENTIST_DPREFCLK_CHG_DONE:bit1; + DENTIST_DPREFCLK_CHGTOG :bit1; + DENTIST_DPREFCLK_DONETOG :bit1; + RESERVED1 :bit1; + DENTIST_DPREFCLK_WDIVIDER:bit7; + RESERVED2 :bit1; + end; + + TDIG_TEST_DEBUG_INDEX=bitpacked record + DIG_TEST_DEBUG_INDEX :bit8; + DIG_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDMCU_RAM_ACCESS_CTRL=bitpacked record + ERAM_WR_ADDR_AUTO_INC :bit1; + ERAM_RD_ADDR_AUTO_INC :bit1; + IRAM_WR_ADDR_AUTO_INC :bit1; + IRAM_RD_ADDR_AUTO_INC :bit1; + ERAM_HOST_ACCESS_EN :bit1; + IRAM_HOST_ACCESS_EN :bit1; + RESERVED0 :bit2; + UC_RST_RELEASE_DELAY_CNT:bit8; + RESERVED1 :bit16; + end; + + TDMCU_TEST_DEBUG_DATA=bit32; + + TDMIF_TEST_DEBUG_DATA=bit32; + + TDOUT_TEST_DEBUG_DATA=bit32; + + TDPG_PIPE_DPM_CONTROL=bitpacked record + DPM_ENABLE :bit1; + RESERVED0 :bit3; + MCLK_CHANGE_ENABLE :bit1; + RESERVED1 :bit3; + MCLK_CHANGE_FORCE_ON :bit1; + RESERVED2 :bit3; + MCLK_CHANGE_WATERMARK_MASK:bit2; + RESERVED3 :bit2; + MCLK_CHANGE_WATERMARK :bit16; + end; + + TDPG_REPEATER_PROGRAM=bitpacked record + REG_DPG_DMIFRC_REPEATER:bit3; + RESERVED0 :bit1; + REG_DMIFRC_DPG_REPEATER:bit3; + RESERVED1 :bit25; + end; + + TDPG_TEST_DEBUG_INDEX=bitpacked record + DPG_TEST_DEBUG_INDEX :bit8; + DPG_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDP_DPHY_CRC_MST_CNTL=bitpacked record + DPHY_CRC_MST_FIRST_SLOT:bit6; + RESERVED0 :bit2; + DPHY_CRC_MST_LAST_SLOT :bit6; + RESERVED1 :bit18; + end; + + TDP_LINK_FRAMING_CNTL=bitpacked record + DP_IDLE_BS_INTERVAL :bit18; + RESERVED0 :bit6; + DP_VBID_DISABLE :bit1; + RESERVED1 :bit3; + DP_VID_ENHANCED_FRAME_MODE:bit1; + RESERVED2 :bit3; + end; + + TDVO_STRENGTH_CONTROL=bitpacked record + DVO_SP :bit4; + DVO_SN :bit4; + DVOCLK_SP :bit4; + DVOCLK_SN :bit4; + DVO_DRVSTRENGTH :bit3; + RESERVED0 :bit1; + DVOCLK_DRVSTRENGTH :bit3; + RESERVED1 :bit1; + FLDO_VITNE_DRVSTRENGTH:bit3; + RESERVED2 :bit1; + DVO_LSB_VMODE :bit1; + DVO_MSB_VMODE :bit1; + RESERVED3 :bit2; + end; + + TDVO_TEST_DEBUG_INDEX=bitpacked record + DVO_TEST_DEBUG_INDEX :bit8; + DVO_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TFBC_START_STOP_DELAY=bitpacked record + FBC_DECOMP_START_DELAY:bit5; + RESERVED0 :bit2; + FBC_DECOMP_STOP_DELAY :bit1; + FBC_COMP_START_DELAY :bit5; + RESERVED1 :bit19; + end; + + TFBC_TEST_DEBUG_INDEX=bitpacked record + FBC_TEST_DEBUG_INDEX :bit8; + FBC_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TFMT_DYNAMIC_EXP_CNTL=bitpacked record + FMT_DYNAMIC_EXP_EN :bit1; + RESERVED0 :bit3; + FMT_DYNAMIC_EXP_MODE:bit1; + RESERVED1 :bit27; + end; + + TFMT_TEST_DEBUG_INDEX=bitpacked record + FMT_TEST_DEBUG_INDEX :bit8; + FMT_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TGAMMA_CORR_LUT_INDEX=bitpacked record + GAMMA_CORR_LUT_INDEX:bit9; + RESERVED0 :bit23; + end; + + TGC_CAC_CGTT_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit18; + SOFT_OVERRIDE_DYN:bit1; + SOFT_OVERRIDE_REG:bit1; + end; + TGDS_GFX_CTXSW_STATUS=bitpacked record R :bit1; W :bit1; @@ -8481,6 +38737,58 @@ type ADDRESS :bit16; end; + TGMCON_PERF_MON_CNTL0=bitpacked record + START_THRESH :bit12; + STOP_THRESH :bit12; + START_MODE :bit2; + STOP_MODE :bit2; + ALLOW_WRAP :bit1; + THRESH_CNTR_ID_EXT:bit1; + START_TRIG_ID_EXT :bit1; + STOP_TRIG_ID_EXT :bit1; + end; + + TGMCON_PERF_MON_CNTL1=bitpacked record + THRESH_CNTR_ID:bit6; + START_TRIG_ID :bit6; + STOP_TRIG_ID :bit6; + MON0_ID :bit7; + MON1_ID :bit7; + end; + + TGMCON_PERF_MON_RSLT0=bit32; + + TGMCON_PERF_MON_RSLT1=bit32; + + TGMCON_RENG_RAM_INDEX=bitpacked record + RENG_RAM_INDEX:bit10; + RESERVED0 :bit22; + end; + + TGPIOPAD_INT_POLARITY=bitpacked record + GPIO_INT_POLARITY :bit29; + RESERVED0 :bit2; + SW_INITIATED_INT_POLARITY:bit1; + end; + + TGPU_GARLIC_FLUSH_REQ=bitpacked record + CP0 :bit1; + CP1 :bit1; + CP2 :bit1; + CP3 :bit1; + CP4 :bit1; + CP5 :bit1; + CP6 :bit1; + CP7 :bit1; + CP8 :bit1; + CP9 :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + SDMA2 :bit1; + SDMA3 :bit1; + RESERVED0:bit18; + end; + TGRBM_PERFCOUNTER0_HI=bit32; TGRBM_PERFCOUNTER0_LO=bit32; @@ -8489,6 +38797,665 @@ type TGRBM_PERFCOUNTER1_LO=bit32; + TGRPH_STEREOSYNC_FLIP=bitpacked record + GRPH_STEREOSYNC_FLIP_EN :bit1; + RESERVED0 :bit7; + GRPH_STEREOSYNC_FLIP_MODE :bit2; + RESERVED1 :bit6; + GRPH_PRIMARY_SURFACE_PENDING :bit1; + GRPH_SECONDARY_SURFACE_PENDING:bit1; + RESERVED2 :bit10; + GRPH_STEREOSYNC_SELECT_DISABLE:bit1; + RESERVED3 :bit3; + end; + + THDP_LAST_SURFACE_HIT=bitpacked record + LAST_SURFACE_HIT:bit6; + RESERVED0 :bit26; + end; + + TLBV_BLACK_KEYER_B_CB=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLBV_BLACK_KEYER_R_CR=bitpacked record + RESERVED0 :bit4; + LB_BLACK_KEYER_R_CR:bit12; + RESERVED1 :bit16; + end; + + TLBV_KEYER_COLOR_B_CB=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLBV_KEYER_COLOR_CTRL=bitpacked record + LB_KEYER_COLOR_EN :bit1; + RESERVED0 :bit7; + LB_KEYER_COLOR_REP_EN:bit1; + RESERVED1 :bit23; + end; + + TLBV_KEYER_COLOR_R_CR=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_R_CR:bit12; + RESERVED1 :bit16; + end; + + TLBV_TEST_DEBUG_INDEX=bitpacked record + LB_TEST_DEBUG_INDEX :bit8; + LB_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TLBV_VLINE2_START_END=bitpacked record + VLINE2_START:bit14; + RESERVED0 :bit2; + VLINE2_END :bit15; + VLINE2_INV :bit1; + end; + + TLBV_V_COUNTER_CHROMA=bitpacked record + V_COUNTER_CHROMA:bit15; + RESERVED0 :bit17; + end; + + TLCLK_DEEP_SLEEP_CNTL=bitpacked record + DIV_ID :bit3; + RAMP_DIS :bit1; + HYSTERESIS:bit12; + RESERVED0 :bit15; + ENABLE_DS :bit1; + end; + + TLVTMA_PWRSEQ_REF_DIV=bitpacked record + LVTMA_PWRSEQ_REF_DIV:bit12; + RESERVED0 :bit4; + BL_PWM_REF_DIV :bit16; + end; + + TMASTER_COMM_CNTL_REG=bitpacked record + MASTER_COMM_INTERRUPT:bit1; + RESERVED0 :bit31; + end; + + TMCIF_TEST_DEBUG_DATA=bit32; + + TMCIF_WB_BUF_1_ADDR_C=bit32; + + TMCIF_WB_BUF_1_ADDR_Y=bit32; + + TMCIF_WB_BUF_1_STATUS=bitpacked record + MCIF_WB_BUF_1_ACTIVE :bit1; + MCIF_WB_BUF_1_SW_LOCKED :bit1; + MCIF_WB_BUF_1_VCE_LOCKED :bit1; + MCIF_WB_BUF_1_OVERFLOW :bit1; + MCIF_WB_BUF_1_DISABLE :bit1; + MCIF_WB_BUF_1_MODE :bit3; + MCIF_WB_BUF_1_BUFTAG :bit4; + MCIF_WB_BUF_1_NXT_BUF :bit3; + MCIF_WB_BUF_1_FIELD :bit1; + MCIF_WB_BUF_1_CUR_LINE_L :bit13; + MCIF_WB_BUF_1_LONG_LINE_ERROR :bit1; + MCIF_WB_BUF_1_SHORT_LINE_ERROR :bit1; + MCIF_WB_BUF_1_FRAME_LENGTH_ERROR:bit1; + end; + + TMCIF_WB_BUF_2_ADDR_C=bit32; + + TMCIF_WB_BUF_2_ADDR_Y=bit32; + + TMCIF_WB_BUF_2_STATUS=bitpacked record + MCIF_WB_BUF_2_ACTIVE :bit1; + MCIF_WB_BUF_2_SW_LOCKED :bit1; + MCIF_WB_BUF_2_VCE_LOCKED :bit1; + MCIF_WB_BUF_2_OVERFLOW :bit1; + MCIF_WB_BUF_2_DISABLE :bit1; + MCIF_WB_BUF_2_MODE :bit3; + MCIF_WB_BUF_2_BUFTAG :bit4; + MCIF_WB_BUF_2_NXT_BUF :bit3; + MCIF_WB_BUF_2_FIELD :bit1; + MCIF_WB_BUF_2_CUR_LINE_L :bit13; + MCIF_WB_BUF_2_LONG_LINE_ERROR :bit1; + MCIF_WB_BUF_2_SHORT_LINE_ERROR :bit1; + MCIF_WB_BUF_2_FRAME_LENGTH_ERROR:bit1; + end; + + TMCIF_WB_BUF_3_ADDR_C=bit32; + + TMCIF_WB_BUF_3_ADDR_Y=bit32; + + TMCIF_WB_BUF_3_STATUS=bitpacked record + MCIF_WB_BUF_3_ACTIVE :bit1; + MCIF_WB_BUF_3_SW_LOCKED :bit1; + MCIF_WB_BUF_3_VCE_LOCKED :bit1; + MCIF_WB_BUF_3_OVERFLOW :bit1; + MCIF_WB_BUF_3_DISABLE :bit1; + MCIF_WB_BUF_3_MODE :bit3; + MCIF_WB_BUF_3_BUFTAG :bit4; + MCIF_WB_BUF_3_NXT_BUF :bit3; + MCIF_WB_BUF_3_FIELD :bit1; + MCIF_WB_BUF_3_CUR_LINE_L :bit13; + MCIF_WB_BUF_3_LONG_LINE_ERROR :bit1; + MCIF_WB_BUF_3_SHORT_LINE_ERROR :bit1; + MCIF_WB_BUF_3_FRAME_LENGTH_ERROR:bit1; + end; + + TMCIF_WB_BUF_4_ADDR_C=bit32; + + TMCIF_WB_BUF_4_ADDR_Y=bit32; + + TMCIF_WB_BUF_4_STATUS=bitpacked record + MCIF_WB_BUF_4_ACTIVE :bit1; + MCIF_WB_BUF_4_SW_LOCKED :bit1; + MCIF_WB_BUF_4_VCE_LOCKED :bit1; + MCIF_WB_BUF_4_OVERFLOW :bit1; + MCIF_WB_BUF_4_DISABLE :bit1; + MCIF_WB_BUF_4_MODE :bit3; + MCIF_WB_BUF_4_BUFTAG :bit4; + MCIF_WB_BUF_4_NXT_BUF :bit3; + MCIF_WB_BUF_4_FIELD :bit1; + MCIF_WB_BUF_4_CUR_LINE_L :bit13; + MCIF_WB_BUF_4_LONG_LINE_ERROR :bit1; + MCIF_WB_BUF_4_SHORT_LINE_ERROR :bit1; + MCIF_WB_BUF_4_FRAME_LENGTH_ERROR:bit1; + end; + + TMC_ARB_DRAM_TIMING_1=bitpacked record + ACTRD :bit8; + ACTWR :bit8; + RASMACTRD:bit8; + RASMACTWR:bit8; + end; + + TMC_ARB_HARSH_SAT0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_SAT0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_SAT1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_SAT1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_MAX_LAT_RSLT0=bit32; + + TMC_ARB_MAX_LAT_RSLT1=bit32; + + TMC_CITF_CREDITS_XBAR=bitpacked record + READ_LCL :bit8; + WRITE_LCL:bit8; + RESERVED0:bit16; + end; + + TMC_FUS_DRAM_APER_DEF=bitpacked record + DEF :bit28; + LOCK_MC_FUS_DRAM_REGS:bit1; + RESERVED0 :bit3; + end; + + TMC_FUS_DRAM_APER_TOP=bitpacked record + TOP :bit20; + RESERVED0:bit12; + end; + + TMC_HUB_MISC_OVERRIDE=bitpacked record + IDLE :bit2; + RESERVED0:bit30; + end; + + TMC_HUB_RDREQ_CREDITS=bitpacked record + VM0 :bit8; + VM1 :bit8; + STOR0:bit8; + STOR1:bit8; + end; + + TMC_HUB_RDREQ_ISP_MPM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_RDREQ_ISP_SPM=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_SEQ_CAS_TIMING_LP=bitpacked record + TNOPW :bit2; + TNOPR :bit2; + TR2W :bit5; + TCCDL :bit3; + TR2R :bit4; + TW2R :bit5; + TCL :bit5; + RESERVED0:bit6; + end; + + TMC_SEQ_IO_DEBUG_DATA=bit32; + + TMC_SEQ_PMG_TIMING_LP=bitpacked record + TCKSRE :bit3; + TCKSRX :bit3; + TCKE_PULSE :bit5; + TCKE :bit8; + SEQ_IDLE :bit3; + SEQ_IDLE_SS:bit8; + RESERVED0 :bit2; + end; + + TMC_SEQ_RAS_TIMING_LP=bitpacked record + TRCDW :bit5; + TRCDWA :bit5; + TRCDR :bit5; + TRCDRA :bit5; + TRRD :bit4; + TRC :bit7; + RESERVED0:bit1; + end; + + TMC_SEQ_TRAIN_CAPTURE=bitpacked record + D0_IDLEH_WAKEUP :bit1; + D1_IDLEH_WAKEUP :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + SCLK_SRBM_READY_WAKEUP:bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + SOFTWARE_WAKEUP :bit1; + RESERVED9 :bit2; + TIMER_DONE_WAKEUP :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit1; + RESERVED22 :bit4; + end; + + TMC_VM_MARC_BASE_HI_0=bitpacked record + MARC_BASE_HI_0:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_BASE_HI_1=bitpacked record + MARC_BASE_HI_1:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_BASE_HI_2=bitpacked record + MARC_BASE_HI_2:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_BASE_HI_3=bitpacked record + MARC_BASE_HI_3:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_BASE_LO_0=bitpacked record + RESERVED0 :bit12; + MARC_BASE_LO_0:bit20; + end; + + TMC_VM_MARC_BASE_LO_1=bitpacked record + RESERVED0 :bit12; + MARC_BASE_LO_1:bit20; + end; + + TMC_VM_MARC_BASE_LO_2=bitpacked record + RESERVED0 :bit12; + MARC_BASE_LO_2:bit20; + end; + + TMC_VM_MARC_BASE_LO_3=bitpacked record + RESERVED0 :bit12; + MARC_BASE_LO_3:bit20; + end; + + TMC_VM_MX_L1_TLB_CNTL=bitpacked record + ENABLE_L1_TLB :bit1; + ENABLE_L1_FRAGMENT_PROCESSING :bit1; + RESERVED0 :bit1; + SYSTEM_ACCESS_MODE :bit2; + SYSTEM_APERTURE_UNMAPPED_ACCESS:bit1; + ENABLE_ADVANCED_DRIVER_MODEL :bit1; + ECO_BITS :bit4; + RESERVED1 :bit21; + end; + + TMC_XBAR_RDREQ_CREDIT=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMC_XBAR_WRREQ_CREDIT=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMC_XPB_P2P_BAR_DEBUG=bitpacked record + SEL :bit8; + HOST_FLUSH :bit4; + MEM_SYS_BAR:bit4; + RESERVED0 :bit16; + end; + + TMC_XPB_P2P_BAR_SETUP=bitpacked record + SEL :bit8; + REG_SYS_BAR :bit4; + VALID :bit1; + SEND_DIS :bit1; + COMPRESS_DIS:bit1; + RESERVED :bit1; + ADDRESS :bit16; + end; + + TMC_XPB_PEER_SYS_BAR0=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR1=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR2=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR3=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR4=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR5=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR6=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR7=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR8=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_PEER_SYS_BAR9=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_RTR_DEST_MAP0=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP1=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP2=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP3=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP4=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP5=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP6=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP7=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP8=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_RTR_DEST_MAP9=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMVP_TEST_DEBUG_INDEX=bitpacked record + MVP_TEST_DEBUG_INDEX :bit8; + MVP_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TOUTPUT_CSC_C11_C12_A=bitpacked record + OUTPUT_CSC_C11_A:bit16; + OUTPUT_CSC_C12_A:bit16; + end; + + TOUTPUT_CSC_C11_C12_B=bitpacked record + OUTPUT_CSC_C11_B:bit16; + OUTPUT_CSC_C12_B:bit16; + end; + + TOUTPUT_CSC_C13_C14_A=bitpacked record + OUTPUT_CSC_C13_A:bit16; + OUTPUT_CSC_C14_A:bit16; + end; + + TOUTPUT_CSC_C13_C14_B=bitpacked record + OUTPUT_CSC_C13_B:bit16; + OUTPUT_CSC_C14_B:bit16; + end; + + TOUTPUT_CSC_C21_C22_A=bitpacked record + OUTPUT_CSC_C21_A:bit16; + OUTPUT_CSC_C22_A:bit16; + end; + + TOUTPUT_CSC_C21_C22_B=bitpacked record + OUTPUT_CSC_C21_B:bit16; + OUTPUT_CSC_C22_B:bit16; + end; + + TOUTPUT_CSC_C23_C24_A=bitpacked record + OUTPUT_CSC_C23_A:bit16; + OUTPUT_CSC_C24_A:bit16; + end; + + TOUTPUT_CSC_C23_C24_B=bitpacked record + OUTPUT_CSC_C23_B:bit16; + OUTPUT_CSC_C24_B:bit16; + end; + + TOUTPUT_CSC_C31_C32_A=bitpacked record + OUTPUT_CSC_C31_A:bit16; + OUTPUT_CSC_C32_A:bit16; + end; + + TOUTPUT_CSC_C31_C32_B=bitpacked record + OUTPUT_CSC_C31_B:bit16; + OUTPUT_CSC_C32_B:bit16; + end; + + TOUTPUT_CSC_C33_C34_A=bitpacked record + OUTPUT_CSC_C33_A:bit16; + OUTPUT_CSC_C34_A:bit16; + end; + + TOUTPUT_CSC_C33_C34_B=bitpacked record + OUTPUT_CSC_C33_B:bit16; + OUTPUT_CSC_C34_B:bit16; + end; + + TOVL_SURFACE_OFFSET_X=bitpacked record + OVL_SURFACE_OFFSET_X:bit14; + RESERVED0 :bit18; + end; + + TOVL_SURFACE_OFFSET_Y=bitpacked record + OVL_SURFACE_OFFSET_Y:bit14; + RESERVED0 :bit18; + end; + TPA_CL_POINT_CULL_RAD=bit32; TPA_CL_VPORT_XSCALE_1=bit32; @@ -8545,6 +39512,1199 @@ type TPA_CL_VPORT_ZSCALE_9=bit32; + TPB0_DFT_JIT_INJ_REG0=bitpacked record + DFT_NUM_STEPS :bit6; + RESERVED0 :bit1; + DFT_DISABLE_ERR :bit1; + DFT_CLK_PER_STEP :bit4; + RESERVED1 :bit8; + DFT_MODE_CDR_EN :bit1; + DFT_EN_RECOVERY :bit1; + DFT_INCR_SWP_EN :bit1; + DFT_DECR_SWP_EN :bit1; + DFT_RECOVERY_TIME:bit8; + end; + + TPB0_DFT_JIT_INJ_REG1=bitpacked record + DFT_BYPASS_VALUE:bit8; + DFT_BYPASS_EN :bit1; + RESERVED0 :bit7; + DFT_BLOCK_EN :bit1; + DFT_NUM_OF_TESTS:bit3; + DFT_CHECK_TIME :bit4; + RESERVED1 :bit8; + end; + + TPB0_DFT_JIT_INJ_REG2=bitpacked record + DFT_LANE_EN:bit16; + RESERVED0 :bit16; + end; + + TPB0_PIF_CMD_BUS_CTRL=bitpacked record + CMD_BUS_SCHL_MODE :bit2; + CMD_BUS_STAG_MODE :bit2; + CMD_BUS_STAG_DIS :bit1; + CMD_BUS_SCH_REQ_MODE :bit2; + CMD_BUS_IGNR_PEND_PWR:bit1; + RESERVED0 :bit24; + end; + + TPB0_RX_GLB_CTRL_REG0=bitpacked record + RX_CFG_ADAPT_MODE_GEN1:bit10; + RX_CFG_ADAPT_MODE_GEN2:bit10; + RX_CFG_ADAPT_MODE_GEN3:bit10; + RX_CFG_ADAPT_RST_MODE :bit2; + end; + + TPB0_RX_GLB_CTRL_REG1=bitpacked record + RX_CFG_CDR_FR_GAIN_GEN1 :bit4; + RX_CFG_CDR_FR_GAIN_GEN2 :bit4; + RX_CFG_CDR_FR_GAIN_GEN3 :bit4; + RX_CFG_CDR_PH_GAIN_GEN1 :bit4; + RX_CFG_CDR_PH_GAIN_GEN2 :bit4; + RX_CFG_CDR_PH_GAIN_GEN3 :bit4; + RX_CFG_CDR_PI_STPSZ_GEN1 :bit1; + RX_CFG_CDR_PI_STPSZ_GEN2 :bit1; + RX_CFG_CDR_PI_STPSZ_GEN3 :bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN1:bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN2:bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN3:bit1; + RX_ADAPT_HLD_ASRT_TO_DCLK_EN :bit2; + end; + + TPB0_RX_GLB_CTRL_REG2=bitpacked record + RESERVED0 :bit12; + RX_CFG_CDR_TIME_GEN1 :bit4; + RX_CFG_CDR_TIME_GEN2 :bit4; + RX_CFG_CDR_TIME_GEN3 :bit4; + RX_CFG_LEQ_LOOP_GAIN_GEN1 :bit2; + RX_CFG_LEQ_LOOP_GAIN_GEN2 :bit2; + RX_CFG_LEQ_LOOP_GAIN_GEN3 :bit2; + RX_DCLK_EN_ASRT_TO_ADAPT_HLD:bit2; + end; + + TPB0_RX_GLB_CTRL_REG3=bitpacked record + RX_CFG_CDR_FR_EN_GEN1 :bit1; + RX_CFG_CDR_FR_EN_GEN2 :bit1; + RX_CFG_CDR_FR_EN_GEN3 :bit1; + RX_ADAPT_RST_MODE_GEN1:bit2; + RX_ADAPT_RST_MODE_GEN2:bit2; + RX_ADAPT_RST_MODE_GEN3:bit2; + RX_ADAPT_RST_SUB_MODE :bit3; + RX_L0_ENTRY_MODE_GEN1 :bit2; + RX_L0_ENTRY_MODE_GEN2 :bit2; + RX_L0_ENTRY_MODE_GEN3 :bit2; + RESERVED0 :bit2; + RX_CFG_DFE_TIME_GEN1 :bit4; + RX_CFG_DFE_TIME_GEN2 :bit4; + RX_CFG_DFE_TIME_GEN3 :bit4; + end; + + TPB0_RX_GLB_CTRL_REG4=bitpacked record + RX_CFG_FOM_BER_GEN1 :bit3; + RX_CFG_FOM_BER_GEN2 :bit3; + RX_CFG_FOM_BER_GEN3 :bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN1:bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN2:bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN3:bit3; + RESERVED0 :bit2; + RX_CFG_FOM_TIME_GEN1 :bit4; + RX_CFG_FOM_TIME_GEN2 :bit4; + RX_CFG_FOM_TIME_GEN3 :bit4; + end; + + TPB0_RX_GLB_CTRL_REG5=bitpacked record + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 :bit5; + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 :bit5; + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 :bit5; + RX_CFG_LEQ_POLE_BYP_EN_GEN1 :bit1; + RX_CFG_LEQ_POLE_BYP_EN_GEN2 :bit1; + RX_CFG_LEQ_POLE_BYP_EN_GEN3 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN1 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN2 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN3 :bit1; + RESERVED0 :bit6; + RX_CFG_TERM_MODE_GEN1 :bit1; + RX_CFG_TERM_MODE_GEN2 :bit1; + RX_CFG_TERM_MODE_GEN3 :bit1; + RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0:bit1; + RX_ADAPT_AUX_PWRON_MODE :bit1; + end; + + TPB0_RX_GLB_CTRL_REG6=bitpacked record + RX_CFG_LEQ_TIME_GEN1 :bit4; + RX_CFG_LEQ_TIME_GEN2 :bit4; + RX_CFG_LEQ_TIME_GEN3 :bit4; + RX_CFG_OC_TIME_GEN1 :bit4; + RX_CFG_OC_TIME_GEN2 :bit4; + RX_CFG_OC_TIME_GEN3 :bit4; + RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0:bit1; + RESERVED0 :bit1; + RX_FRONTEND_PWRON_LUT_ENTRY_LS2 :bit1; + RX_AUX_PWRON_LUT_ENTRY_LS2 :bit1; + RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS :bit1; + RX_ADAPT_HLD_L1_DLL_OFF :bit1; + RESERVED1 :bit2; + end; + + TPB0_RX_GLB_CTRL_REG7=bitpacked record + RX_CFG_TH_LOOP_GAIN_GEN1 :bit4; + RX_CFG_TH_LOOP_GAIN_GEN2 :bit4; + RX_CFG_TH_LOOP_GAIN_GEN3 :bit4; + RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0:bit1; + RX_DCLK_EN_LUT_ENTRY_LS2 :bit1; + RX_DCLK_EN_AFTER_DLL_LOCK :bit1; + RESERVED0 :bit1; + RX_DLL_PWRON_LUT_ENTRY_PS3 :bit1; + RX_DLL_PWRON_LUT_ENTRY_PS2 :bit1; + RX_CFG_DLL_CPI_SEL_GEN1 :bit3; + RX_CFG_DLL_CPI_SEL_GEN2 :bit3; + RX_CFG_DLL_CPI_SEL_GEN3 :bit3; + RX_CFG_DLL_FLOCK_DISABLE_GEN1 :bit1; + RX_CFG_DLL_FLOCK_DISABLE_GEN2 :bit1; + RX_CFG_DLL_FLOCK_DISABLE_GEN3 :bit1; + RESERVED1 :bit2; + end; + + TPB0_RX_GLB_CTRL_REG8=bitpacked record + RX_DLL_LOCK_TIME :bit2; + RX_DLL_SPEEDCHANGE_RESET_TIME:bit2; + RX_DLL_PWRON_IN_RAMPDOWN :bit1; + RX_FSM_L0S_IF_RX_RDY :bit1; + RESERVED0 :bit26; + end; + + TPB0_RX_GLB_OVRD_REG0=bitpacked record + RX_ADAPT_HLD_OVRD_VAL :bit1; + RX_ADAPT_HLD_OVRD_EN :bit1; + RX_ADAPT_RST_OVRD_VAL :bit1; + RX_ADAPT_RST_OVRD_EN :bit1; + RESERVED0 :bit2; + RX_CFG_DCLK_DIV_OVRD_VAL :bit2; + RX_CFG_DCLK_DIV_OVRD_EN :bit1; + RX_CFG_DLL_FREQ_MODE_OVRD_VAL:bit1; + RX_CFG_DLL_FREQ_MODE_OVRD_EN :bit1; + RX_CFG_PLLCLK_SEL_OVRD_VAL :bit1; + RX_CFG_PLLCLK_SEL_OVRD_EN :bit1; + RX_CFG_RCLK_DIV_OVRD_VAL :bit1; + RX_CFG_RCLK_DIV_OVRD_EN :bit1; + RX_DCLK_EN_OVRD_VAL :bit1; + RX_DCLK_EN_OVRD_EN :bit1; + RX_DLL_PWRON_OVRD_VAL :bit1; + RX_DLL_PWRON_OVRD_EN :bit1; + RX_FRONTEND_PWRON_OVRD_VAL :bit1; + RX_FRONTEND_PWRON_OVRD_EN :bit1; + RX_IDLEDET_PWRON_OVRD_VAL :bit1; + RX_IDLEDET_PWRON_OVRD_EN :bit1; + RX_TERM_EN_OVRD_VAL :bit1; + RX_TERM_EN_OVRD_EN :bit1; + RESERVED1 :bit3; + RX_AUX_PWRON_OVRD_VAL :bit1; + RX_AUX_PWRON_OVRD_EN :bit1; + RX_ADAPT_FOM_OVRD_VAL :bit1; + RX_ADAPT_FOM_OVRD_EN :bit1; + end; + + TPB0_RX_GLB_OVRD_REG1=bitpacked record + RX_ADAPT_TRK_OVRD_VAL:bit1; + RX_ADAPT_TRK_OVRD_EN :bit1; + RESERVED0 :bit30; + end; + + TPB0_TX_GLB_CTRL_REG0=bitpacked record + TX_DRV_DATA_ASRT_DLY_VAL:bit3; + TX_DRV_DATA_DSRT_DLY_VAL:bit3; + RESERVED0 :bit2; + TX_CFG_RPTR_RST_VAL_GEN1:bit3; + TX_CFG_RPTR_RST_VAL_GEN2:bit3; + TX_CFG_RPTR_RST_VAL_GEN3:bit3; + TX_STAGGER_CTRL :bit2; + TX_DATA_CLK_GATING :bit1; + TX_PRESET_TABLE_BYPASS :bit1; + TX_COEFF_ROUND_EN :bit1; + TX_COEFF_ROUND_DIR_VER :bit1; + TX_DCLK_EN_LSX_ALWAYS_ON:bit1; + TX_FRONTEND_PWRON_IN_PS4:bit1; + RESERVED1 :bit7; + end; + + TPB0_TX_GLB_OVRD_REG0=bitpacked record + TX_CFG_DCLK_DIV_OVRD_VAL :bit3; + TX_CFG_DCLK_DIV_OVRD_EN :bit1; + TX_CFG_DRV0_EN_GEN1_OVRD_VAL :bit4; + TX_CFG_DRV0_EN_OVRD_EN :bit1; + TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL:bit4; + TX_CFG_DRV0_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRV1_EN_GEN1_OVRD_VAL :bit5; + TX_CFG_DRV1_EN_OVRD_EN :bit1; + TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL:bit5; + TX_CFG_DRV1_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRV2_EN_GEN1_OVRD_VAL :bit4; + TX_CFG_DRV2_EN_OVRD_EN :bit1; + RESERVED0 :bit1; + end; + + TPB0_TX_GLB_OVRD_REG1=bitpacked record + TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL:bit4; + TX_CFG_DRV2_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRVX_EN_GEN1_OVRD_VAL :bit1; + TX_CFG_DRVX_EN_OVRD_EN :bit1; + TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL:bit1; + TX_CFG_DRVX_TAP_SEL_OVRD_EN :bit1; + TX_CFG_PLLCLK_SEL_OVRD_VAL :bit1; + TX_CFG_PLLCLK_SEL_OVRD_EN :bit1; + TX_CFG_TCLK_DIV_OVRD_VAL :bit1; + TX_CFG_TCLK_DIV_OVRD_EN :bit1; + TX_CMDET_EN_OVRD_VAL :bit1; + TX_CMDET_EN_OVRD_EN :bit1; + TX_DATA_IN_OVRD_VAL :bit10; + TX_DATA_IN_OVRD_EN :bit1; + TX_RPTR_RSTN_OVRD_VAL :bit1; + TX_RPTR_RSTN_OVRD_EN :bit1; + TX_RXDET_EN_OVRD_VAL :bit1; + TX_RXDET_EN_OVRD_EN :bit1; + TX_WPTR_RSTN_OVRD_VAL :bit1; + TX_WPTR_RSTN_OVRD_EN :bit1; + end; + + TPB0_TX_GLB_OVRD_REG2=bitpacked record + TX_WRITE_EN_OVRD_VAL :bit1; + TX_WRITE_EN_OVRD_EN :bit1; + TX_CFG_GROUPX1_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX1_EN_OVRD_EN :bit1; + TX_CFG_GROUPX2_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX2_EN_OVRD_EN :bit1; + TX_CFG_GROUPX4_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX4_EN_OVRD_EN :bit1; + TX_CFG_GROUPX8_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX8_EN_OVRD_EN :bit1; + TX_CFG_GROUPX16_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX16_EN_OVRD_EN :bit1; + TX_CFG_DRV0_EN_GEN2_OVRD_VAL :bit4; + TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL:bit4; + TX_CFG_DRV1_EN_GEN2_OVRD_VAL :bit5; + TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL:bit5; + RESERVED0 :bit2; + end; + + TPB0_TX_GLB_OVRD_REG3=bitpacked record + TX_CFG_DRV2_EN_GEN2_OVRD_VAL :bit4; + TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL:bit4; + TX_CFG_DRVX_EN_GEN2_OVRD_VAL :bit1; + TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL:bit1; + TX_CFG_DRV0_EN_GEN3_OVRD_VAL :bit4; + TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL:bit4; + TX_CFG_DRV1_EN_GEN3_OVRD_VAL :bit5; + TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL:bit5; + TX_CFG_DRV2_EN_GEN3_OVRD_VAL :bit4; + end; + + TPB0_TX_GLB_OVRD_REG4=bitpacked record + TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL:bit4; + TX_CFG_DRVX_EN_GEN3_OVRD_VAL :bit1; + TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL:bit1; + RESERVED0 :bit26; + end; + + TPB1_DFT_JIT_INJ_REG0=bitpacked record + DFT_NUM_STEPS :bit6; + RESERVED0 :bit1; + DFT_DISABLE_ERR :bit1; + DFT_CLK_PER_STEP :bit4; + RESERVED1 :bit8; + DFT_MODE_CDR_EN :bit1; + DFT_EN_RECOVERY :bit1; + DFT_INCR_SWP_EN :bit1; + DFT_DECR_SWP_EN :bit1; + DFT_RECOVERY_TIME:bit8; + end; + + TPB1_DFT_JIT_INJ_REG1=bitpacked record + DFT_BYPASS_VALUE:bit8; + DFT_BYPASS_EN :bit1; + RESERVED0 :bit7; + DFT_BLOCK_EN :bit1; + DFT_NUM_OF_TESTS:bit3; + DFT_CHECK_TIME :bit4; + RESERVED1 :bit8; + end; + + TPB1_DFT_JIT_INJ_REG2=bitpacked record + DFT_LANE_EN:bit16; + RESERVED0 :bit16; + end; + + TPB1_PIF_CMD_BUS_CTRL=bitpacked record + CMD_BUS_SCHL_MODE :bit2; + CMD_BUS_STAG_MODE :bit2; + CMD_BUS_STAG_DIS :bit1; + CMD_BUS_SCH_REQ_MODE :bit2; + CMD_BUS_IGNR_PEND_PWR:bit1; + RESERVED0 :bit24; + end; + + TPB1_RX_GLB_CTRL_REG0=bitpacked record + RX_CFG_ADAPT_MODE_GEN1:bit10; + RX_CFG_ADAPT_MODE_GEN2:bit10; + RX_CFG_ADAPT_MODE_GEN3:bit10; + RX_CFG_ADAPT_RST_MODE :bit2; + end; + + TPB1_RX_GLB_CTRL_REG1=bitpacked record + RX_CFG_CDR_FR_GAIN_GEN1 :bit4; + RX_CFG_CDR_FR_GAIN_GEN2 :bit4; + RX_CFG_CDR_FR_GAIN_GEN3 :bit4; + RX_CFG_CDR_PH_GAIN_GEN1 :bit4; + RX_CFG_CDR_PH_GAIN_GEN2 :bit4; + RX_CFG_CDR_PH_GAIN_GEN3 :bit4; + RX_CFG_CDR_PI_STPSZ_GEN1 :bit1; + RX_CFG_CDR_PI_STPSZ_GEN2 :bit1; + RX_CFG_CDR_PI_STPSZ_GEN3 :bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN1:bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN2:bit1; + RX_CFG_LEQ_DCATTN_BYP_EN_GEN3:bit1; + RX_ADAPT_HLD_ASRT_TO_DCLK_EN :bit2; + end; + + TPB1_RX_GLB_CTRL_REG2=bitpacked record + RESERVED0 :bit12; + RX_CFG_CDR_TIME_GEN1 :bit4; + RX_CFG_CDR_TIME_GEN2 :bit4; + RX_CFG_CDR_TIME_GEN3 :bit4; + RX_CFG_LEQ_LOOP_GAIN_GEN1 :bit2; + RX_CFG_LEQ_LOOP_GAIN_GEN2 :bit2; + RX_CFG_LEQ_LOOP_GAIN_GEN3 :bit2; + RX_DCLK_EN_ASRT_TO_ADAPT_HLD:bit2; + end; + + TPB1_RX_GLB_CTRL_REG3=bitpacked record + RX_CFG_CDR_FR_EN_GEN1 :bit1; + RX_CFG_CDR_FR_EN_GEN2 :bit1; + RX_CFG_CDR_FR_EN_GEN3 :bit1; + RX_ADAPT_RST_MODE_GEN1:bit2; + RX_ADAPT_RST_MODE_GEN2:bit2; + RX_ADAPT_RST_MODE_GEN3:bit2; + RX_ADAPT_RST_SUB_MODE :bit3; + RX_L0_ENTRY_MODE_GEN1 :bit2; + RX_L0_ENTRY_MODE_GEN2 :bit2; + RX_L0_ENTRY_MODE_GEN3 :bit2; + RESERVED0 :bit2; + RX_CFG_DFE_TIME_GEN1 :bit4; + RX_CFG_DFE_TIME_GEN2 :bit4; + RX_CFG_DFE_TIME_GEN3 :bit4; + end; + + TPB1_RX_GLB_CTRL_REG4=bitpacked record + RX_CFG_FOM_BER_GEN1 :bit3; + RX_CFG_FOM_BER_GEN2 :bit3; + RX_CFG_FOM_BER_GEN3 :bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN1:bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN2:bit3; + RX_CFG_LEQ_POLE_BYP_VAL_GEN3:bit3; + RESERVED0 :bit2; + RX_CFG_FOM_TIME_GEN1 :bit4; + RX_CFG_FOM_TIME_GEN2 :bit4; + RX_CFG_FOM_TIME_GEN3 :bit4; + end; + + TPB1_RX_GLB_CTRL_REG5=bitpacked record + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1 :bit5; + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2 :bit5; + RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3 :bit5; + RX_CFG_LEQ_POLE_BYP_EN_GEN1 :bit1; + RX_CFG_LEQ_POLE_BYP_EN_GEN2 :bit1; + RX_CFG_LEQ_POLE_BYP_EN_GEN3 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN1 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN2 :bit1; + RX_CFG_LEQ_SHUNT_EN_GEN3 :bit1; + RESERVED0 :bit6; + RX_CFG_TERM_MODE_GEN1 :bit1; + RX_CFG_TERM_MODE_GEN2 :bit1; + RX_CFG_TERM_MODE_GEN3 :bit1; + RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0:bit1; + RX_ADAPT_AUX_PWRON_MODE :bit1; + end; + + TPB1_RX_GLB_CTRL_REG6=bitpacked record + RX_CFG_LEQ_TIME_GEN1 :bit4; + RX_CFG_LEQ_TIME_GEN2 :bit4; + RX_CFG_LEQ_TIME_GEN3 :bit4; + RX_CFG_OC_TIME_GEN1 :bit4; + RX_CFG_OC_TIME_GEN2 :bit4; + RX_CFG_OC_TIME_GEN3 :bit4; + RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0:bit1; + RESERVED0 :bit1; + RX_FRONTEND_PWRON_LUT_ENTRY_LS2 :bit1; + RX_AUX_PWRON_LUT_ENTRY_LS2 :bit1; + RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS :bit1; + RX_ADAPT_HLD_L1_DLL_OFF :bit1; + RESERVED1 :bit2; + end; + + TPB1_RX_GLB_CTRL_REG7=bitpacked record + RX_CFG_TH_LOOP_GAIN_GEN1 :bit4; + RX_CFG_TH_LOOP_GAIN_GEN2 :bit4; + RX_CFG_TH_LOOP_GAIN_GEN3 :bit4; + RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0:bit1; + RX_DCLK_EN_LUT_ENTRY_LS2 :bit1; + RX_DCLK_EN_AFTER_DLL_LOCK :bit1; + RESERVED0 :bit1; + RX_DLL_PWRON_LUT_ENTRY_PS3 :bit1; + RX_DLL_PWRON_LUT_ENTRY_PS2 :bit1; + RX_CFG_DLL_CPI_SEL_GEN1 :bit3; + RX_CFG_DLL_CPI_SEL_GEN2 :bit3; + RX_CFG_DLL_CPI_SEL_GEN3 :bit3; + RX_CFG_DLL_FLOCK_DISABLE_GEN1 :bit1; + RX_CFG_DLL_FLOCK_DISABLE_GEN2 :bit1; + RX_CFG_DLL_FLOCK_DISABLE_GEN3 :bit1; + RESERVED1 :bit2; + end; + + TPB1_RX_GLB_CTRL_REG8=bitpacked record + RX_DLL_LOCK_TIME :bit2; + RX_DLL_SPEEDCHANGE_RESET_TIME:bit2; + RX_DLL_PWRON_IN_RAMPDOWN :bit1; + RX_FSM_L0S_IF_RX_RDY :bit1; + RESERVED0 :bit26; + end; + + TPB1_RX_GLB_OVRD_REG0=bitpacked record + RX_ADAPT_HLD_OVRD_VAL :bit1; + RX_ADAPT_HLD_OVRD_EN :bit1; + RX_ADAPT_RST_OVRD_VAL :bit1; + RX_ADAPT_RST_OVRD_EN :bit1; + RESERVED0 :bit2; + RX_CFG_DCLK_DIV_OVRD_VAL :bit2; + RX_CFG_DCLK_DIV_OVRD_EN :bit1; + RX_CFG_DLL_FREQ_MODE_OVRD_VAL:bit1; + RX_CFG_DLL_FREQ_MODE_OVRD_EN :bit1; + RX_CFG_PLLCLK_SEL_OVRD_VAL :bit1; + RX_CFG_PLLCLK_SEL_OVRD_EN :bit1; + RX_CFG_RCLK_DIV_OVRD_VAL :bit1; + RX_CFG_RCLK_DIV_OVRD_EN :bit1; + RX_DCLK_EN_OVRD_VAL :bit1; + RX_DCLK_EN_OVRD_EN :bit1; + RX_DLL_PWRON_OVRD_VAL :bit1; + RX_DLL_PWRON_OVRD_EN :bit1; + RX_FRONTEND_PWRON_OVRD_VAL :bit1; + RX_FRONTEND_PWRON_OVRD_EN :bit1; + RX_IDLEDET_PWRON_OVRD_VAL :bit1; + RX_IDLEDET_PWRON_OVRD_EN :bit1; + RX_TERM_EN_OVRD_VAL :bit1; + RX_TERM_EN_OVRD_EN :bit1; + RESERVED1 :bit3; + RX_AUX_PWRON_OVRD_VAL :bit1; + RX_AUX_PWRON_OVRD_EN :bit1; + RX_ADAPT_FOM_OVRD_VAL :bit1; + RX_ADAPT_FOM_OVRD_EN :bit1; + end; + + TPB1_RX_GLB_OVRD_REG1=bitpacked record + RX_ADAPT_TRK_OVRD_VAL:bit1; + RX_ADAPT_TRK_OVRD_EN :bit1; + RESERVED0 :bit30; + end; + + TPB1_TX_GLB_CTRL_REG0=bitpacked record + TX_DRV_DATA_ASRT_DLY_VAL:bit3; + TX_DRV_DATA_DSRT_DLY_VAL:bit3; + RESERVED0 :bit2; + TX_CFG_RPTR_RST_VAL_GEN1:bit3; + TX_CFG_RPTR_RST_VAL_GEN2:bit3; + TX_CFG_RPTR_RST_VAL_GEN3:bit3; + TX_STAGGER_CTRL :bit2; + TX_DATA_CLK_GATING :bit1; + TX_PRESET_TABLE_BYPASS :bit1; + TX_COEFF_ROUND_EN :bit1; + TX_COEFF_ROUND_DIR_VER :bit1; + TX_DCLK_EN_LSX_ALWAYS_ON:bit1; + TX_FRONTEND_PWRON_IN_PS4:bit1; + RESERVED1 :bit7; + end; + + TPB1_TX_GLB_OVRD_REG0=bitpacked record + TX_CFG_DCLK_DIV_OVRD_VAL :bit3; + TX_CFG_DCLK_DIV_OVRD_EN :bit1; + TX_CFG_DRV0_EN_GEN1_OVRD_VAL :bit4; + TX_CFG_DRV0_EN_OVRD_EN :bit1; + TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL:bit4; + TX_CFG_DRV0_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRV1_EN_GEN1_OVRD_VAL :bit5; + TX_CFG_DRV1_EN_OVRD_EN :bit1; + TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL:bit5; + TX_CFG_DRV1_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRV2_EN_GEN1_OVRD_VAL :bit4; + TX_CFG_DRV2_EN_OVRD_EN :bit1; + RESERVED0 :bit1; + end; + + TPB1_TX_GLB_OVRD_REG1=bitpacked record + TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL:bit4; + TX_CFG_DRV2_TAP_SEL_OVRD_EN :bit1; + TX_CFG_DRVX_EN_GEN1_OVRD_VAL :bit1; + TX_CFG_DRVX_EN_OVRD_EN :bit1; + TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL:bit1; + TX_CFG_DRVX_TAP_SEL_OVRD_EN :bit1; + TX_CFG_PLLCLK_SEL_OVRD_VAL :bit1; + TX_CFG_PLLCLK_SEL_OVRD_EN :bit1; + TX_CFG_TCLK_DIV_OVRD_VAL :bit1; + TX_CFG_TCLK_DIV_OVRD_EN :bit1; + TX_CMDET_EN_OVRD_VAL :bit1; + TX_CMDET_EN_OVRD_EN :bit1; + TX_DATA_IN_OVRD_VAL :bit10; + TX_DATA_IN_OVRD_EN :bit1; + TX_RPTR_RSTN_OVRD_VAL :bit1; + TX_RPTR_RSTN_OVRD_EN :bit1; + TX_RXDET_EN_OVRD_VAL :bit1; + TX_RXDET_EN_OVRD_EN :bit1; + TX_WPTR_RSTN_OVRD_VAL :bit1; + TX_WPTR_RSTN_OVRD_EN :bit1; + end; + + TPB1_TX_GLB_OVRD_REG2=bitpacked record + TX_WRITE_EN_OVRD_VAL :bit1; + TX_WRITE_EN_OVRD_EN :bit1; + TX_CFG_GROUPX1_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX1_EN_OVRD_EN :bit1; + TX_CFG_GROUPX2_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX2_EN_OVRD_EN :bit1; + TX_CFG_GROUPX4_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX4_EN_OVRD_EN :bit1; + TX_CFG_GROUPX8_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX8_EN_OVRD_EN :bit1; + TX_CFG_GROUPX16_EN_OVRD_VAL :bit1; + TX_CFG_GROUPX16_EN_OVRD_EN :bit1; + TX_CFG_DRV0_EN_GEN2_OVRD_VAL :bit4; + TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL:bit4; + TX_CFG_DRV1_EN_GEN2_OVRD_VAL :bit5; + TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL:bit5; + RESERVED0 :bit2; + end; + + TPB1_TX_GLB_OVRD_REG3=bitpacked record + TX_CFG_DRV2_EN_GEN2_OVRD_VAL :bit4; + TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL:bit4; + TX_CFG_DRVX_EN_GEN2_OVRD_VAL :bit1; + TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL:bit1; + TX_CFG_DRV0_EN_GEN3_OVRD_VAL :bit4; + TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL:bit4; + TX_CFG_DRV1_EN_GEN3_OVRD_VAL :bit5; + TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL:bit5; + TX_CFG_DRV2_EN_GEN3_OVRD_VAL :bit4; + end; + + TPB1_TX_GLB_OVRD_REG4=bitpacked record + TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL:bit4; + TX_CFG_DRVX_EN_GEN3_OVRD_VAL :bit1; + TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL:bit1; + RESERVED0 :bit26; + end; + + TPCIE_CORR_ERR_STATUS=bitpacked record + RCV_ERR_STATUS :bit1; + RESERVED0 :bit5; + BAD_TLP_STATUS :bit1; + BAD_DLLP_STATUS :bit1; + REPLAY_NUM_ROLLOVER_STATUS :bit1; + RESERVED1 :bit3; + REPLAY_TIMER_TIMEOUT_STATUS :bit1; + ADVISORY_NONFATAL_ERR_STATUS:bit1; + CORR_INT_ERR_STATUS :bit1; + HDR_LOG_OVFL_STATUS :bit1; + RESERVED2 :bit16; + end; + + TPCIE_HOLD_TRAINING_A=bitpacked record + HOLD_TRAINING_A:bit1; + RESERVED0 :bit31; + end; + + TPCIE_MC_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_PAGE_REQ_STATUS=bitpacked record + RESPONSE_FAILURE :bit1; + UNEXPECTED_PAGE_REQ_GRP_INDEX:bit1; + RESERVED0 :bit6; + STOPPED :bit1; + RESERVED1 :bit6; + PRG_RESPONSE_PASID_REQUIRED :bit1; + RESERVED2 :bit16; + end; + + TPCIE_PERF_CNTL_TXCLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PERF_COUNT_CNTL=bitpacked record + GLOBAL_COUNT_EN :bit1; + GLOBAL_SHADOW_WR :bit1; + GLOBAL_COUNT_RESET:bit1; + RESERVED0 :bit29; + end; + + TPCIE_PWR_BUDGET_DATA=bitpacked record + BASE_POWER :bit8; + DATA_SCALE :bit2; + PM_SUB_STATE:bit3; + PM_STATE :bit2; + _TYPE :bit3; + POWER_RAIL :bit3; + RESERVED0 :bit11; + end; + + TPCIE_SRIOV_TOTAL_VFS=bitpacked record + SRIOV_TOTAL_VFS:bit16; + RESERVED0 :bit16; + end; + + TPCIE_SRIOV_VF_STRIDE=bitpacked record + SRIOV_VF_STRIDE:bit16; + RESERVED0 :bit16; + end; + + TPCIE_TLP_PREFIX_LOG0=bit32; + + TPCIE_TLP_PREFIX_LOG1=bit32; + + TPCIE_TLP_PREFIX_LOG2=bit32; + + TPCIE_TLP_PREFIX_LOG3=bit32; + + TPCIE_TX_F0_ATTR_CNTL=bitpacked record + TX_F0_IDO_OVERRIDE_P :bit2; + TX_F0_IDO_OVERRIDE_NP :bit2; + TX_F0_IDO_OVERRIDE_CPL:bit2; + TX_F0_RO_OVERRIDE_P :bit2; + TX_F0_RO_OVERRIDE_NP :bit2; + TX_F0_SNR_OVERRIDE_P :bit2; + TX_F0_SNR_OVERRIDE_NP :bit2; + RESERVED0 :bit18; + end; + + TPCIE_TX_REQUESTER_ID=bitpacked record + TX_REQUESTER_ID_FUNCTION:bit3; + TX_REQUESTER_ID_DEVICE :bit5; + TX_REQUESTER_ID_BUS :bit8; + RESERVED0 :bit16; + end; + + TPCIE_UNCORR_ERR_MASK=bitpacked record + RESERVED0 :bit4; + DLP_ERR_MASK :bit1; + SURPDN_ERR_MASK :bit1; + RESERVED1 :bit6; + PSN_ERR_MASK :bit1; + FC_ERR_MASK :bit1; + CPL_TIMEOUT_MASK :bit1; + CPL_ABORT_ERR_MASK :bit1; + UNEXP_CPL_MASK :bit1; + RCV_OVFL_MASK :bit1; + MAL_TLP_MASK :bit1; + ECRC_ERR_MASK :bit1; + UNSUPP_REQ_ERR_MASK :bit1; + ACS_VIOLATION_MASK :bit1; + UNCORR_INT_ERR_MASK :bit1; + MC_BLOCKED_TLP_MASK :bit1; + ATOMICOP_EGRESS_BLOCKED_MASK:bit1; + TLP_PREFIX_BLOCKED_ERR_MASK :bit1; + RESERVED2 :bit6; + end; + + TPCIE_VC_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPLL_SS_AMOUNT_DSFRAC=bitpacked record + PLL_SS_AMOUNT_DSFRAC:bit16; + RESERVED0 :bit16; + end; + + TPRESCALE_OVL_CONTROL=bitpacked record + OVL_PRESCALE_SELECT :bit1; + OVL_PRESCALE_CB_SIGN:bit1; + OVL_PRESCALE_Y_SIGN :bit1; + OVL_PRESCALE_CR_SIGN:bit1; + OVL_PRESCALE_BYPASS :bit1; + RESERVED0 :bit27; + end; + + TPWR_DISP_TIMER_DEBUG=bitpacked record + DISP_TIMER_INT_RUNNING:bit1; + DISP_TIMER_INT_STAT :bit1; + DISP_TIMER_INT :bit1; + RESERVED0 :bit4; + DISP_TIMER_RUN_VAL :bit25; + end; + + TRLC_GPM_DEBUG_SELECT=bitpacked record + SELECT :bit8; + F32_DEBUG_SELECT:bit2; + RESERVED :bit22; + end; + + TRLC_GPM_PERF_COUNT_0=bitpacked record + FEATURE_SEL:bit4; + SE_INDEX :bit4; + SH_INDEX :bit4; + CU_INDEX :bit4; + EVENT_SEL :bit2; + RESERVED0 :bit2; + ENABLE :bit1; + RESERVED1 :bit11; + end; + + TRLC_GPM_PERF_COUNT_1=bitpacked record + FEATURE_SEL:bit4; + SE_INDEX :bit4; + SH_INDEX :bit4; + CU_INDEX :bit4; + EVENT_SEL :bit2; + RESERVED0 :bit2; + ENABLE :bit1; + RESERVED1 :bit11; + end; + + TRLC_GPM_SCRATCH_ADDR=bitpacked record + ADDR :bit9; + RESERVED0:bit23; + end; + + TRLC_GPM_SCRATCH_DATA=bit32; + + TRLC_GPM_THREAD_RESET=bitpacked record + THREAD0_RESET:bit1; + THREAD1_RESET:bit1; + THREAD2_RESET:bit1; + THREAD3_RESET:bit1; + RESERVED :bit28; + end; + + TRLC_GPM_VMID_THREAD0=bitpacked record + RLC_VMID :bit4; + RESERVED0 :bit4; + RLC_QUEUEID:bit3; + RESERVED1 :bit21; + end; + + TRLC_GPM_VMID_THREAD1=bitpacked record + RLC_VMID :bit4; + RESERVED0 :bit4; + RLC_QUEUEID:bit3; + RESERVED1 :bit21; + end; + + TRLC_GPM_VMID_THREAD2=bitpacked record + RLC_VMID :bit4; + RESERVED0 :bit4; + RLC_QUEUEID:bit3; + RESERVED1 :bit21; + end; + + TRLC_GPU_IOV_CFG_REG1=bitpacked record + CMD_TYPE :bit4; + CMD_EXECUTE :bit1; + CMD_EXECUTE_INTR_EN:bit1; + RESERVED :bit2; + FCN_ID :bit8; + NEXT_FCN_ID :bit8; + RESERVED1 :bit8; + end; + + TRLC_GPU_IOV_CFG_REG2=bitpacked record + CMD_STATUS:bit4; + RESERVED :bit28; + end; + + TRLC_GPU_IOV_CFG_REG6=bitpacked record + CNTXT_SIZE :bit7; + CNTXT_LOCATION:bit1; + RESERVED :bit2; + CNTXT_OFFSET :bit22; + end; + + TRLC_GPU_IOV_CFG_REG8=bit32; + + TRLC_GPU_IOV_CFG_REG9=bitpacked record + ACTIVE_FCN_ID :bit8; + ACTIVE_FCN_ID_STATUS:bit4; + RESERVED :bit20; + end; + + TRLC_GPU_IOV_F32_CNTL=bitpacked record + ENABLE :bit1; + RESERVED:bit31; + end; + + TRLC_PERFMON_CLK_CNTL=bitpacked record + PERFMON_CLOCK_STATE:bit1; + RESERVED0 :bit31; + end; + + TRLC_SERDES_RD_DATA_0=bit32; + + TRLC_SERDES_RD_DATA_1=bit32; + + TRLC_SERDES_RD_DATA_2=bit32; + + TRLC_SPM_DEBUG_SELECT=bitpacked record + SELECT :bit8; + RESERVED0 :bit7; + RLC_SPM_DEBUG_MODE:bit1; + RLC_SPM_NUM_SAMPLE:bit16; + end; + + TRLC_SPM_PERFMON_CNTL=bitpacked record + RESERVED1 :bit12; + PERFMON_RING_MODE :bit2; + RESERVED0 :bit2; + PERFMON_SAMPLE_INTERVAL:bit16; + end; + + TRLC_SRM_DEBUG_SELECT=bitpacked record + SELECT :bit8; + RESERVED:bit24; + end; + + TRLC_SRM_RLCV_COMMAND=bitpacked record + OP :bit1; + RESERVED :bit3; + SIZE :bit12; + START_OFFSET:bit12; + RESERVED1 :bit3; + DEST_MEMORY :bit1; + end; + + TRLC_STATIC_PG_STATUS=bit32; + + TSCLK_DEEP_SLEEP_CNTL=bitpacked record + DIV_ID :bit3; + RAMP_DIS :bit1; + HYSTERESIS :bit12; + SCLK_RUNNING_MASK :bit1; + SELF_REFRESH_MASK :bit1; + ALLOW_NBPSTATE_MASK :bit1; + BIF_BUSY_MASK :bit1; + UVD_BUSY_MASK :bit1; + MC0SRBM_BUSY_MASK :bit1; + MC1SRBM_BUSY_MASK :bit1; + MC_ALLOW_MASK :bit1; + SMU_BUSY_MASK :bit1; + SELF_REFRESH_NLC_MASK :bit1; + FAST_EXIT_REQ_NBPSTATE:bit1; + DEEP_SLEEP_ENTRY_MODE :bit1; + MBUS2_ACTIVE_MASK :bit1; + VCE_BUSY_MASK :bit1; + AZ_BUSY_MASK :bit1; + ENABLE_DS :bit1; + end; + + TSCLV_COEF_RAM_SELECT=bitpacked record + SCL_C_RAM_TAP_PAIR_IDX:bit2; + RESERVED0 :bit6; + SCL_C_RAM_PHASE :bit7; + RESERVED1 :bit1; + SCL_C_RAM_FILTER_TYPE :bit2; + RESERVED2 :bit14; + end; + + TSCLV_TEST_DEBUG_DATA=bit32; + + TSCLV_VIEWPORT_SIZE_C=bitpacked record + VIEWPORT_HEIGHT_C:bit13; + RESERVED0 :bit3; + VIEWPORT_WIDTH_C :bit13; + RESERVED1 :bit3; + end; + + TSCL_HORZ_FILTER_INIT=bitpacked record + SCL_H_INIT_FRAC:bit24; + SCL_H_INIT_INT :bit4; + RESERVED0 :bit4; + end; + + TSCL_MODE_CHANGE_DET1=bitpacked record + SCL_MODE_CHANGE :bit1; + RESERVED0 :bit3; + SCL_MODE_CHANGE_ACK :bit1; + RESERVED1 :bit2; + SCL_ALU_H_SCALE_RATIO:bit21; + RESERVED2 :bit4; + end; + + TSCL_MODE_CHANGE_DET2=bitpacked record + SCL_ALU_V_SCALE_RATIO:bit21; + RESERVED0 :bit11; + end; + + TSCL_MODE_CHANGE_DET3=bitpacked record + SCL_ALU_SOURCE_HEIGHT:bit14; + RESERVED0 :bit2; + SCL_ALU_SOURCE_WIDTH :bit14; + RESERVED1 :bit2; + end; + + TSCL_MODE_CHANGE_MASK=bitpacked record + SCL_MODE_CHANGE_MASK:bit1; + RESERVED0 :bit31; + end; + + TSCL_TEST_DEBUG_INDEX=bitpacked record + SCL_TEST_DEBUG_INDEX :bit8; + SCL_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TSCL_VERT_FILTER_INIT=bitpacked record + SCL_V_INIT_FRAC:bit24; + SCL_V_INIT_INT :bit3; + RESERVED0 :bit5; + end; + + TSDMA0_GFX_IB_BASE_HI=bit32; + + TSDMA0_GFX_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA0_GFX_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSDMA0_PERF_REG_TYPE0=bitpacked record + SDMA0_PERFMON_CNTL :bit1; + SDMA0_PERFCOUNTER0_RESULT:bit1; + SDMA0_PERFCOUNTER1_RESULT:bit1; + RESERVED_31_3 :bit29; + end; + + TSDMA0_PHASE0_QUANTUM=bitpacked record + _UNIT :bit4; + RESERVED0:bit4; + VALUE :bit16; + RESERVED1:bit6; + PREFER :bit1; + RESERVED2:bit1; + end; + + TSDMA0_PHASE1_QUANTUM=bitpacked record + _UNIT :bit4; + RESERVED0:bit4; + VALUE :bit16; + RESERVED1:bit6; + PREFER :bit1; + RESERVED2:bit1; + end; + + TSDMA0_RLC0_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA0_RLC0_DUMMY_REG=bit32; + + TSDMA0_RLC0_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_RLC0_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA0_RLC0_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA0_RLC1_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA0_RLC1_DUMMY_REG=bit32; + + TSDMA0_RLC1_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_RLC1_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA0_RLC1_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA0_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TSDMA1_GFX_IB_BASE_HI=bit32; + + TSDMA1_GFX_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA1_GFX_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSDMA1_PERF_REG_TYPE0=bitpacked record + SDMA1_PERFMON_CNTL :bit1; + SDMA1_PERFCOUNTER0_RESULT:bit1; + SDMA1_PERFCOUNTER1_RESULT:bit1; + RESERVED_31_3 :bit29; + end; + + TSDMA1_PHASE0_QUANTUM=bitpacked record + _UNIT :bit4; + RESERVED0:bit4; + VALUE :bit16; + RESERVED1:bit6; + PREFER :bit1; + RESERVED2:bit1; + end; + + TSDMA1_PHASE1_QUANTUM=bitpacked record + _UNIT :bit4; + RESERVED0:bit4; + VALUE :bit16; + RESERVED1:bit6; + PREFER :bit1; + RESERVED2:bit1; + end; + + TSDMA1_RLC0_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA1_RLC0_DUMMY_REG=bit32; + + TSDMA1_RLC0_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_RLC0_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA1_RLC0_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA1_RLC1_APE1_CNTL=bitpacked record + BASE :bit16; + LIMIT:bit16; + end; + + TSDMA1_RLC1_DUMMY_REG=bit32; + + TSDMA1_RLC1_IB_OFFSET=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_RLC1_SKIP_CNTL=bitpacked record + SKIP_COUNT:bit14; + RESERVED0 :bit18; + end; + + TSDMA1_RLC1_WATERMARK=bitpacked record + RD_OUTSTANDING:bit12; + RESERVED0 :bit4; + WR_OUTSTANDING:bit9; + RESERVED1 :bit7; + end; + + TSDMA1_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TSE_CAC_CGTT_CLK_CTRL=bitpacked record + ON_DELAY :bit4; + OFF_HYSTERESIS :bit8; + RESERVED0 :bit18; + SOFT_OVERRIDE_DYN:bit1; + SOFT_OVERRIDE_REG:bit1; + end; + + TSH_STATIC_MEM_CONFIG=bitpacked record + SWIZZLE_ENABLE:bit1; + ELEMENT_SIZE :bit2; + INDEX_STRIDE :bit2; + PRIVATE_MTYPE :bit3; + READ_ONLY_CNTL:bit8; + RESERVED0 :bit16; + end; + + TSLAVE_COMM_DATA_REG1=bitpacked record + SLAVE_COMM_DATA_REG1_BYTE0:bit8; + SLAVE_COMM_DATA_REG1_BYTE1:bit8; + SLAVE_COMM_DATA_REG1_BYTE2:bit8; + SLAVE_COMM_DATA_REG1_BYTE3:bit8; + end; + + TSLAVE_COMM_DATA_REG2=bitpacked record + SLAVE_COMM_DATA_REG2_BYTE0:bit8; + SLAVE_COMM_DATA_REG2_BYTE1:bit8; + SLAVE_COMM_DATA_REG2_BYTE2:bit8; + SLAVE_COMM_DATA_REG2_BYTE3:bit8; + end; + + TSLAVE_COMM_DATA_REG3=bitpacked record + SLAVE_COMM_DATA_REG3_BYTE0:bit8; + SLAVE_COMM_DATA_REG3_BYTE1:bit8; + SLAVE_COMM_DATA_REG3_BYTE2:bit8; + SLAVE_COMM_DATA_REG3_BYTE3:bit8; + end; + + TSMC_SYSCON_MISC_CNTL=bitpacked record + RESERVED0 :bit1; + dma_no_outstanding:bit1; + RESERVED1 :bit30; + end; + + TSMC_SYSCON_MSG_ARG_0=bit32; + + TSMU_MAIN_PLL_OP_FREQ=bit32; + + TSMU_MP1_SRBM2P_MSG_5=bit32; + TSPI_GDBG_TRAP_CONFIG=bitpacked record ME_SEL :bit2; PIPE_SEL :bit2; @@ -9110,6 +41270,19 @@ type RESERVED0 :bit27; end; + TSQ_DEBUG_STS_GLOBAL2=bitpacked record + FIFO_LEVEL_GFX0 :bit8; + FIFO_LEVEL_GFX1 :bit8; + FIFO_LEVEL_IMMED:bit8; + FIFO_LEVEL_HOST :bit8; + end; + + TSQ_DEBUG_STS_GLOBAL3=bitpacked record + FIFO_LEVEL_HOST_CMD:bit4; + FIFO_LEVEL_HOST_REG:bit6; + RESERVED0 :bit22; + end; + TSQ_PERFCOUNTER_CTRL2=bitpacked record FORCE_EN :bit1; RESERVED0:bit31; @@ -9164,6 +41337,75 @@ type READ_OFFSET:bit2; end; + TSRBM_DEBUG_SNAPSHOT2=bitpacked record + VCE1_RDY :bit1; + RESERVED0:bit31; + end; + + TSRBM_GFX_CNTL_SELECT=bitpacked record + SRBM_GFX_CNTL_SEL:bit4; + RESERVED0 :bit28; + end; + + TSRBM_MC_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR3=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR4=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR5=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_MC_DOMAIN_ADDR6=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_PERFCOUNTER0_HI=bit32; + + TSRBM_PERFCOUNTER0_LO=bit32; + + TSRBM_PERFCOUNTER1_HI=bit32; + + TSRBM_PERFCOUNTER1_LO=bit32; + + TSRBM_SDMA_CLKEN_CNTL=bitpacked record + PREFIX_DELAY_CNT:bit4; + RESERVED0 :bit4; + POST_DELAY_CNT :bit5; + RESERVED1 :bit19; + end; + + TSWRST_COMMAND_STATUS=bitpacked record + RECONFIGURE :bit1; + ATOMIC_RESET :bit1; + RESERVED0 :bit14; + RESET_COMPLETE:bit1; + WAIT_STATE :bit1; + RESERVED1 :bit14; + end; + TSX_BLEND_OPT_CONTROL=bitpacked record MRT0_COLOR_OPT_DISABLE:bit1; MRT0_ALPHA_OPT_DISABLE:bit1; @@ -9203,6 +41445,721 @@ type MRT7_EPSILON:bit4; end; + TSYMCLKA_CLOCK_ENABLE=bitpacked record + SYMCLKA_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKA_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKA_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKB_CLOCK_ENABLE=bitpacked record + SYMCLKB_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKB_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKB_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKC_CLOCK_ENABLE=bitpacked record + SYMCLKC_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKC_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKC_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKD_CLOCK_ENABLE=bitpacked record + SYMCLKD_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKD_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKD_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKE_CLOCK_ENABLE=bitpacked record + SYMCLKE_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKE_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKE_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKF_CLOCK_ENABLE=bitpacked record + SYMCLKF_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKF_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKF_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TSYMCLKG_CLOCK_ENABLE=bitpacked record + SYMCLKG_CLOCK_ENABLE:bit1; + RESERVED0 :bit3; + SYMCLKG_FE_FORCE_EN :bit1; + RESERVED1 :bit3; + SYMCLKG_FE_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TTHM_TMON0_RDIL0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR0_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR1_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR2_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR3_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR4_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR5_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR6_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR7_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR8_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR9_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTMDS_CTL0_1_GEN_CNTL=bitpacked record + TMDS_CTL0_DATA_SEL :bit4; + TMDS_CTL0_DATA_DELAY :bit3; + TMDS_CTL0_DATA_INVERT :bit1; + TMDS_CTL0_DATA_MODULATION :bit2; + TMDS_CTL0_USE_FEEDBACK_PATH:bit1; + TMDS_CTL0_FB_SYNC_CONT :bit1; + TMDS_CTL0_PATTERN_OUT_EN :bit1; + RESERVED0 :bit3; + TMDS_CTL1_DATA_SEL :bit4; + TMDS_CTL1_DATA_DELAY :bit3; + TMDS_CTL1_DATA_INVERT :bit1; + TMDS_CTL1_DATA_MODULATION :bit2; + TMDS_CTL1_USE_FEEDBACK_PATH:bit1; + TMDS_CTL1_FB_SYNC_CONT :bit1; + TMDS_CTL1_PATTERN_OUT_EN :bit1; + RESERVED1 :bit2; + TMDS_2BIT_COUNTER_EN :bit1; + end; + + TTMDS_CTL2_3_GEN_CNTL=bitpacked record + TMDS_CTL2_DATA_SEL :bit4; + TMDS_CTL2_DATA_DELAY :bit3; + TMDS_CTL2_DATA_INVERT :bit1; + TMDS_CTL2_DATA_MODULATION :bit2; + TMDS_CTL2_USE_FEEDBACK_PATH:bit1; + TMDS_CTL2_FB_SYNC_CONT :bit1; + TMDS_CTL2_PATTERN_OUT_EN :bit1; + RESERVED0 :bit3; + TMDS_CTL3_DATA_SEL :bit4; + TMDS_CTL3_DATA_DELAY :bit3; + TMDS_CTL3_DATA_INVERT :bit1; + TMDS_CTL3_DATA_MODULATION :bit2; + TMDS_CTL3_USE_FEEDBACK_PATH:bit1; + TMDS_CTL3_FB_SYNC_CONT :bit1; + TMDS_CTL3_PATTERN_OUT_EN :bit1; + RESERVED1 :bit3; + end; + + TUNIPHY_ANG_BIST_CNTL=bitpacked record + UNIPHY_TEST_RX_EN :bit1; + UNIPHY_ANG_BIST_RESET:bit1; + RESERVED0 :bit6; + UNIPHY_RX_BIAS :bit4; + RESERVED1 :bit4; + UNIPHY_ANG_BIST_ERROR:bit5; + RESERVED2 :bit3; + UNIPHY_PRESETB :bit1; + UNIPHY_BIST_EN :bit1; + UNIPHY_CLK_CH_EN4_DFT:bit1; + RESERVED3 :bit5; + end; + + TUNIPHY_IMPCAL_PERIOD=bit32; + + TUNIPHY_IMPCAL_PSW_AB=bitpacked record + UNIPHY_IMPCAL_PSW_LINKA:bit15; + RESERVED0 :bit1; + UNIPHY_IMPCAL_PSW_LINKB:bit15; + RESERVED1 :bit1; + end; + + TUNIPHY_IMPCAL_PSW_CD=bitpacked record + UNIPHY_IMPCAL_PSW_LINKC:bit15; + RESERVED0 :bit1; + UNIPHY_IMPCAL_PSW_LINKD:bit15; + RESERVED1 :bit1; + end; + + TUNIPHY_IMPCAL_PSW_EF=bitpacked record + UNIPHY_IMPCAL_PSW_LINKE:bit15; + RESERVED0 :bit1; + UNIPHY_IMPCAL_PSW_LINKF:bit15; + RESERVED1 :bit1; + end; + + TUNIPHY_POWER_CONTROL=bitpacked record + UNIPHY_BGPDN :bit1; + UNIPHY_RST_LOGIC :bit1; + UNIPHY_BIASREF_SEL:bit1; + RESERVED0 :bit5; + UNIPHY_BGADJ1P00 :bit4; + UNIPHY_BGADJ1P25 :bit4; + UNIPHY_BGADJ0P45 :bit4; + RESERVED1 :bit12; + end; + + TUNP_GRPH_CONTROL_EXP=bitpacked record + VIDEO_FORMAT:bit3; + RESERVED0 :bit29; + end; + + TUNP_GRPH_DFQ_CONTROL=bitpacked record + GRPH_DFQ_RESET :bit1; + RESERVED0 :bit3; + GRPH_DFQ_SIZE :bit3; + RESERVED1 :bit1; + GRPH_DFQ_MIN_FREE_ENTRIES:bit3; + RESERVED2 :bit21; + end; + + TUNP_TEST_DEBUG_INDEX=bitpacked record + UNP_TEST_DEBUG_INDEX :bit8; + UNP_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TUVD_GPCOM_VCPU_DATA0=bit32; + + TUVD_GPCOM_VCPU_DATA1=bit32; + + TUVD_JPEG_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TUVD_PGFSM_READ_TILE1=bitpacked record + UVD_PGFSM_READ_TILE1_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE2=bitpacked record + UVD_PGFSM_READ_TILE2_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE3=bitpacked record + UVD_PGFSM_READ_TILE3_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE4=bitpacked record + UVD_PGFSM_READ_TILE4_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE5=bitpacked record + UVD_PGFSM_READ_TILE5_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE6=bitpacked record + UVD_PGFSM_READ_TILE6_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_PGFSM_READ_TILE7=bitpacked record + UVD_PGFSM_READ_TILE7_VALUE:bit24; + RESERVED0 :bit8; + end; + + TUVD_RBC_RB_RPTR_ADDR=bit32; + + TUVD_UDEC_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TUVD_VCPU_CACHE_SIZE0=bitpacked record + CACHE_SIZE0:bit21; + RESERVED0 :bit11; + end; + + TUVD_VCPU_CACHE_SIZE1=bitpacked record + CACHE_SIZE1:bit21; + RESERVED0 :bit11; + end; + + TUVD_VCPU_CACHE_SIZE2=bitpacked record + CACHE_SIZE2:bit21; + RESERVED0 :bit11; + end; + + TVCE_VCPU_CACHE_SIZE0=bitpacked record + SIZE :bit24; + RESERVED0:bit8; + end; + + TVCE_VCPU_CACHE_SIZE1=bitpacked record + SIZE :bit24; + RESERVED0:bit8; + end; + + TVCE_VCPU_CACHE_SIZE2=bitpacked record + SIZE :bit24; + RESERVED0:bit8; + end; + + TVGA_INTERRUPT_STATUS=bitpacked record + VGA_MEM_ACCESS_INT_STATUS :bit1; + VGA_REG_ACCESS_INT_STATUS :bit1; + VGA_DISPLAY_SWITCH_INT_STATUS :bit1; + VGA_MODE_AUTO_TRIGGER_INT_STATUS:bit1; + RESERVED0 :bit28; + end; + + TVGA_TEST_DEBUG_INDEX=bitpacked record + VGA_TEST_DEBUG_INDEX :bit8; + VGA_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + TVGT_DMA_LS_HS_CONFIG=bitpacked record RESERVED0 :bit8; HS_NUM_INPUT_CP:bit6; @@ -9260,6 +42217,230 @@ type RESERVED0 :bit19; end; + TXDMA_TEST_DEBUG_DATA=bit32; + + TAFMT_AUDIO_CRC_RESULT=bitpacked record + AFMT_AUDIO_CRC_DONE:bit1; + RESERVED0 :bit7; + AFMT_AUDIO_CRC :bit24; + end; + + TATC_L1_ADDRESS_OFFSET=bit32; + + TATC_VM_APERTURE0_CNTL=bitpacked record + ATS_ACCESS_MODE:bit2; + RESERVED0 :bit30; + end; + + TATC_VM_APERTURE1_CNTL=bitpacked record + ATS_ACCESS_MODE:bit2; + RESERVED0 :bit30; + end; + + TAUX_INTERRUPT_CONTROL=bitpacked record + AUX_SW_DONE_INT :bit1; + AUX_SW_DONE_ACK :bit1; + AUX_SW_DONE_MASK :bit1; + RESERVED0 :bit1; + AUX_LS_DONE_INT :bit1; + AUX_LS_DONE_ACK :bit1; + AUX_LS_DONE_MASK :bit1; + RESERVED1 :bit1; + AUX_GTC_SYNC_LOCK_DONE_INT :bit1; + AUX_GTC_SYNC_LOCK_DONE_ACK :bit1; + AUX_GTC_SYNC_LOCK_DONE_INT_MASK:bit1; + RESERVED2 :bit1; + AUX_GTC_SYNC_ERROR_INT :bit1; + AUX_GTC_SYNC_ERROR_ACK :bit1; + AUX_GTC_SYNC_ERROR_INT_MASK :bit1; + RESERVED3 :bit17; + end; + + TAZALIA_F0_CODEC_DEBUG=bitpacked record + DISABLE_FORMAT_COMPARISON:bit6; + CODEC_DEBUG :bit26; + end; + + TAZALIA_MEM_PWR_STATUS=bitpacked record + AZ_MEM_PWR_STATE :bit2; + AZ_INPUT_STREAM0_MEM_PWR_STATE:bit2; + AZ_INPUT_STREAM1_MEM_PWR_STATE:bit2; + AZ_INPUT_STREAM2_MEM_PWR_STATE:bit2; + AZ_INPUT_STREAM3_MEM_PWR_STATE:bit2; + AZ_INPUT_STREAM4_MEM_PWR_STATE:bit2; + AZ_INPUT_STREAM5_MEM_PWR_STATE:bit2; + RESERVED0 :bit18; + end; + + TBIF_MM_INDACCESS_CNTL=bitpacked record + RESERVED0 :bit1; + MM_INDACCESS_DIS:bit1; + RESERVED1 :bit30; + end; + + TBIF_MST_TRANS_PENDING=bit32; + + TBIF_SLV_TRANS_PENDING=bit32; + + TBIF_VDDGFX_GFX0_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX0_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX0_REG_CMP_EN :bit1; + VDDGFX_GFX0_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX0_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX0_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_GFX1_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX1_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX1_REG_CMP_EN :bit1; + VDDGFX_GFX1_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX1_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX1_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_GFX2_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX2_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX2_REG_CMP_EN :bit1; + VDDGFX_GFX2_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX2_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX2_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_GFX3_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX3_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX3_REG_CMP_EN :bit1; + VDDGFX_GFX3_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX3_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX3_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_GFX4_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX4_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX4_REG_CMP_EN :bit1; + VDDGFX_GFX4_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX4_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX4_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_GFX5_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX5_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_GFX5_REG_CMP_EN :bit1; + VDDGFX_GFX5_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_GFX5_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_GFX5_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_RSV1_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV1_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_RSV1_REG_CMP_EN :bit1; + VDDGFX_RSV1_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_RSV1_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV1_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_RSV2_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV2_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_RSV2_REG_CMP_EN :bit1; + VDDGFX_RSV2_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_RSV2_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV2_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_RSV3_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV3_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_RSV3_REG_CMP_EN :bit1; + VDDGFX_RSV3_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_RSV3_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV3_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBIF_VDDGFX_RSV4_LOWER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV4_REG_LOWER :bit16; + RESERVED1 :bit12; + VDDGFX_RSV4_REG_CMP_EN :bit1; + VDDGFX_RSV4_REG_STALL_EN:bit1; + end; + + TBIF_VDDGFX_RSV4_UPPER=bitpacked record + RESERVED0 :bit2; + VDDGFX_RSV4_REG_UPPER:bit16; + RESERVED1 :bit14; + end; + + TBL1_PWM_GRP2_REG_LOCK=bitpacked record + BL1_PWM_GRP2_REG_LOCK :bit1; + RESERVED0 :bit7; + BL1_PWM_GRP2_REG_UPDATE_PENDING :bit1; + RESERVED1 :bit7; + BL1_PWM_GRP2_UPDATE_AT_FRAME_START :bit1; + BL1_PWM_GRP2_FRAME_START_DISP_SEL :bit3; + RESERVED2 :bit4; + BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN:bit1; + RESERVED3 :bit6; + BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN :bit1; + end; + + TBLND_TEST_DEBUG_INDEX=bitpacked record + BLND_TEST_DEBUG_INDEX :bit8; + BLND_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + TCB_COLOR0_CLEAR_WORD0=bit32; TCB_COLOR0_CLEAR_WORD1=bit32; @@ -9493,6 +42674,656 @@ type RESERVED1 :bit8; end; + TCC_RB_BACKEND_DISABLE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit15; + BACKEND_DISABLE:bit8; + RESERVED2 :bit8; + end; + + TCGTS_CU0_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU0_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU10_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU11_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU13_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU14_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU15_TA_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit20; + end; + + TCGTS_CU1_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU1_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU2_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU2_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU3_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU3_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU4_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU4_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU5_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU5_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU6_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU6_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU7_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU7_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU8_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU8_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU9_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU9_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_USER_TCC_DISABLE=bitpacked record + RESERVED0 :bit16; + TCC_DISABLE:bit16; + end; + + TCG_FREQ_TRAN_VOTING_0=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_1=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_2=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_3=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_4=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_5=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_6=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_FREQ_TRAN_VOTING_7=bitpacked record + BIF_FREQ_THROTTLING_VOTE_EN :bit1; + HDP_FREQ_THROTTLING_VOTE_EN :bit1; + ROM_FREQ_THROTTLING_VOTE_EN :bit1; + IH_SEM_FREQ_THROTTLING_VOTE_EN :bit1; + PDMA_FREQ_THROTTLING_VOTE_EN :bit1; + DRM_FREQ_THROTTLING_VOTE_EN :bit1; + IDCT_FREQ_THROTTLING_VOTE_EN :bit1; + ACP_FREQ_THROTTLING_VOTE_EN :bit1; + SDMA_FREQ_THROTTLING_VOTE_EN :bit1; + UVD_FREQ_THROTTLING_VOTE_EN :bit1; + VCE_FREQ_THROTTLING_VOTE_EN :bit1; + DC_AZ_FREQ_THROTTLING_VOTE_EN :bit1; + SAM_FREQ_THROTTLING_VOTE_EN :bit1; + AVP_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_0_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_1_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_2_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_3_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_4_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_5_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_6_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_7_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_8_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_9_FREQ_THROTTLING_VOTE_EN :bit1; + GRBM_10_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_11_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_12_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_13_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_14_FREQ_THROTTLING_VOTE_EN:bit1; + GRBM_15_FREQ_THROTTLING_VOTE_EN:bit1; + RLC_FREQ_THROTTLING_VOTE_EN :bit1; + RESERVED0 :bit1; + end; + + TCG_THERMAL_INT_STATUS=bitpacked record + THERM_INTH_DETECT :bit1; + THERM_INTL_DETECT :bit1; + THERM_TRIGGER_DETECT :bit1; + THERM_TRIGGER_CNB_DETECT:bit1; + RESERVED0 :bit28; + end; + + TCOL_MAN_DEBUG_CONTROL=bitpacked record + COL_MAN_GLOBAL_PASSTHROUGH_ENABLE:bit1; + RESERVED0 :bit31; + end; + TCOMPUTE_MISC_RESERVED=bitpacked record SEND_SEID :bit2; RESERVED0 :bit3; @@ -9848,18 +43679,27 @@ type TCP_MEC_ME2_UCODE_DATA=bit32; + TCP_ME_ATOMIC_PREOP_HI=bit32; + + TCP_ME_ATOMIC_PREOP_LO=bit32; + TCP_PA_CINVOC_COUNT_HI=bit32; TCP_PA_CINVOC_COUNT_LO=bit32; + TCP_PERFCOUNTER_SELECT=bitpacked record + RESERVED0:bit6; + RESERVED1:bit26; + end; + TCP_PIPE_STATS_ADDR_HI=bitpacked record PIPE_STATS_ADDR_HI:bit16; RESERVED0 :bit16; end; TCP_PIPE_STATS_ADDR_LO=bitpacked record - PIPE_STATS_ADDR_SWAP__SI__CI:bit2; - PIPE_STATS_ADDR_LO :bit30; + PIPE_STATS_ADDR_SWAP:bit2; + PIPE_STATS_ADDR_LO :bit30; end; TCP_PIPE_STATS_CONTROL=bitpacked record @@ -9872,14 +43712,21 @@ type TCP_PQ_WPTR_POLL_CNTL1=bit32; + TCP_RING_PRIORITY_CNTS=bitpacked record + PRIORITY1_CNT :bit8; + PRIORITY2A_CNT:bit8; + PRIORITY2B_CNT:bit8; + PRIORITY3_CNT :bit8; + end; + TCP_STREAM_OUT_ADDR_HI=bitpacked record STREAM_OUT_ADDR_HI:bit16; RESERVED0 :bit16; end; TCP_STREAM_OUT_ADDR_LO=bitpacked record - STREAM_OUT_ADDR_SWAP__SI__CI:bit2; - STREAM_OUT_ADDR_LO :bit30; + STREAM_OUT_ADDR_SWAP:bit2; + STREAM_OUT_ADDR_LO :bit30; end; TCP_STREAM_OUT_CONTROL=bitpacked record @@ -9890,18 +43737,1152 @@ type RESERVED2 :bit3; end; + TCRTC0_PIXEL_RATE_CNTL=bitpacked record + CRTC0_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO0_ENABLE :bit1; + DP_DTO0_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC0_ADD_PIXEL :bit1; + CRTC0_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC0_DISPOUT_FIFO_ERROR :bit2; + CRTC0_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC1_PIXEL_RATE_CNTL=bitpacked record + CRTC1_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO1_ENABLE :bit1; + DP_DTO1_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC1_ADD_PIXEL :bit1; + CRTC1_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC1_DISPOUT_FIFO_ERROR :bit2; + CRTC1_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC2_PIXEL_RATE_CNTL=bitpacked record + CRTC2_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO2_ENABLE :bit1; + DP_DTO2_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC2_ADD_PIXEL :bit1; + CRTC2_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC2_DISPOUT_FIFO_ERROR :bit2; + CRTC2_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC3_PIXEL_RATE_CNTL=bitpacked record + CRTC3_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO3_ENABLE :bit1; + DP_DTO3_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC3_ADD_PIXEL :bit1; + CRTC3_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC3_DISPOUT_FIFO_ERROR :bit2; + CRTC3_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC4_PIXEL_RATE_CNTL=bitpacked record + CRTC4_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO4_ENABLE :bit1; + DP_DTO4_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC4_ADD_PIXEL :bit1; + CRTC4_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC4_DISPOUT_FIFO_ERROR :bit2; + CRTC4_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC5_PIXEL_RATE_CNTL=bitpacked record + CRTC5_PIXEL_RATE_SOURCE :bit2; + RESERVED0 :bit2; + DP_DTO5_ENABLE :bit1; + DP_DTO5_DS_DISABLE :bit1; + RESERVED1 :bit2; + CRTC5_ADD_PIXEL :bit1; + CRTC5_DROP_PIXEL :bit1; + RESERVED2 :bit4; + CRTC5_DISPOUT_FIFO_ERROR :bit2; + CRTC5_DISPOUT_ERROR_COUNT:bit12; + RESERVED3 :bit4; + end; + + TCRTC_BLANK_DATA_COLOR=bitpacked record + CRTC_BLANK_DATA_COLOR_BLUE_CB:bit10; + CRTC_BLANK_DATA_COLOR_GREEN_Y:bit10; + CRTC_BLANK_DATA_COLOR_RED_CR :bit10; + RESERVED0 :bit2; + end; + + TCRTC_INTERLACE_STATUS=bitpacked record + CRTC_INTERLACE_CURRENT_FIELD:bit1; + CRTC_INTERLACE_NEXT_FIELD :bit1; + RESERVED0 :bit30; + end; + + TCRTC_SNAPSHOT_CONTROL=bitpacked record + CRTC_AUTO_SNAPSHOT_TRIG_SEL:bit2; + RESERVED0 :bit30; + end; + + TCRTC_TEST_DEBUG_INDEX=bitpacked record + CRTC_TEST_DEBUG_INDEX :bit8; + CRTC_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDAC_AUTODETECT_STATUS=bitpacked record + DAC_AUTODETECT_STATUS :bit1; + RESERVED0 :bit3; + DAC_AUTODETECT_CONNECT :bit1; + RESERVED1 :bit3; + DAC_AUTODETECT_RED_SENSE :bit2; + RESERVED2 :bit6; + DAC_AUTODETECT_GREEN_SENSE:bit2; + RESERVED3 :bit6; + DAC_AUTODETECT_BLUE_SENSE :bit2; + RESERVED4 :bit6; + end; + + TDAC_COMPARATOR_ENABLE=bitpacked record + DAC_COMP_DDET_REF_EN:bit1; + RESERVED0 :bit7; + DAC_COMP_SDET_REF_EN:bit1; + RESERVED1 :bit7; + DAC_R_ASYNC_ENABLE :bit1; + DAC_G_ASYNC_ENABLE :bit1; + DAC_B_ASYNC_ENABLE :bit1; + RESERVED2 :bit13; + end; + + TDAC_COMPARATOR_OUTPUT=bitpacked record + DAC_COMPARATOR_OUTPUT :bit1; + DAC_COMPARATOR_OUTPUT_BLUE :bit1; + DAC_COMPARATOR_OUTPUT_GREEN:bit1; + DAC_COMPARATOR_OUTPUT_RED :bit1; + RESERVED0 :bit28; + end; + + TDAC_FORCE_OUTPUT_CNTL=bitpacked record + DAC_FORCE_DATA_EN :bit1; + RESERVED0 :bit7; + DAC_FORCE_DATA_SEL :bit3; + RESERVED1 :bit13; + DAC_FORCE_DATA_ON_BLANKB_ONLY:bit1; + RESERVED2 :bit7; + end; + + TDAC_STEREOSYNC_SELECT=bitpacked record + DAC_STEREOSYNC_SELECT:bit3; + RESERVED0 :bit29; + end; + TDB_STENCIL_WRITE_BASE=bit32; + TDCCG_AUDIO_DTO0_PHASE=bit32; + + TDCCG_AUDIO_DTO1_PHASE=bit32; + + TDCCG_AUDIO_DTO_SOURCE=bitpacked record + DCCG_AUDIO_DTO0_SOURCE_SEL :bit3; + RESERVED0 :bit1; + DCCG_AUDIO_DTO_SEL :bit2; + RESERVED1 :bit6; + DCCG_AUDIO_DTO2_SOURCE_SEL :bit2; + RESERVED2 :bit2; + DCCG_AUDIO_DTO2_CLOCK_EN :bit1; + RESERVED3 :bit3; + DCCG_AUDIO_DTO2_USE_512FBR_DTO:bit1; + RESERVED4 :bit3; + DCCG_AUDIO_DTO0_USE_512FBR_DTO:bit1; + RESERVED5 :bit3; + DCCG_AUDIO_DTO1_USE_512FBR_DTO:bit1; + RESERVED6 :bit3; + end; + + TDCCG_CBUS_WRCMD_DELAY=bitpacked record + CBUS_PLL_WRCMD_DELAY:bit4; + RESERVED0 :bit28; + end; + + TDCCG_TEST_DEBUG_INDEX=bitpacked record + DCCG_TEST_DEBUG_INDEX :bit8; + DCCG_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDCIO_TEST_DEBUG_INDEX=bitpacked record + DCIO_TEST_DEBUG_INDEX :bit8; + DCIO_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDCPG_TEST_DEBUG_INDEX=bitpacked record + DCPG_TEST_DEBUG_INDEX :bit8; + DCPG_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDC_ABM1_ACE_CNTL_MISC=bitpacked record + ABM1_ACE_REG_WR_MISSED_FRAME :bit1; + RESERVED0 :bit7; + ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR:bit1; + RESERVED1 :bit23; + end; + + TDC_I2C_DDC1_HW_STATUS=bitpacked record + DC_I2C_DDC1_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC1_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC1_HW_REQ :bit1; + DC_I2C_DDC1_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC1_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC1_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_DDC2_HW_STATUS=bitpacked record + DC_I2C_DDC2_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC2_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC2_HW_REQ :bit1; + DC_I2C_DDC2_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC2_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC2_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_DDC3_HW_STATUS=bitpacked record + DC_I2C_DDC3_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC3_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC3_HW_REQ :bit1; + DC_I2C_DDC3_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC3_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC3_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_DDC4_HW_STATUS=bitpacked record + DC_I2C_DDC4_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC4_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC4_HW_REQ :bit1; + DC_I2C_DDC4_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC4_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC4_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_DDC5_HW_STATUS=bitpacked record + DC_I2C_DDC5_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC5_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC5_HW_REQ :bit1; + DC_I2C_DDC5_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC5_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC5_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_DDC6_HW_STATUS=bitpacked record + DC_I2C_DDC6_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDC6_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDC6_HW_REQ :bit1; + DC_I2C_DDC6_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDC6_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDC6_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDIG_OUTPUT_CRC_RESULT=bitpacked record + DIG_OUTPUT_CRC_RESULT:bit30; + RESERVED0 :bit2; + end; + + TDISP_INTERRUPT_STATUS=bitpacked record + SCL_DISP1_MODE_CHANGE_INTERRUPT :bit1; + D1BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D1_VLINE_INTERRUPT :bit1; + LB_D1_VBLANK_INTERRUPT :bit1; + CRTC1_SNAPSHOT_INTERRUPT :bit1; + CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC1_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC1_TRIGA_INTERRUPT :bit1; + CRTC1_TRIGB_INTERRUPT :bit1; + CRTC1_VSYNC_NOM_INTERRUPT :bit1; + CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGA_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD1_INTERRUPT :bit1; + DC_HPD1_RX_INTERRUPT :bit1; + AUX1_SW_DONE_INTERRUPT :bit1; + AUX1_LS_DONE_INTERRUPT :bit1; + DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT :bit1; + DACA_AUTODETECT_INTERRUPT :bit1; + DACB_AUTODETECT_INTERRUPT :bit1; + DC_I2C_SW_DONE_INTERRUPT :bit1; + DC_I2C_HW_DONE_INTERRUPT :bit1; + DMCU_UC_INTERNAL_INT :bit1; + DMCU_SCP_INT :bit1; + ABM1_HG_READY_INT :bit1; + ABM1_LS_READY_INT :bit1; + ABM1_BL_UPDATE_INT :bit1; + DISP_INTERRUPT_STATUS_CONTINUE :bit1; + end; + + TDMCU_INTERRUPT_STATUS=bitpacked record + ABM1_HG_READY_INT_OCCURRED :bit1; + ABM1_LS_READY_INT_OCCURRED :bit1; + ABM1_BL_UPDATE_INT_OCCURRED :bit1; + MCP_INT_OCCURRED :bit1; + DCPG_IHC_DSI_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED :bit1; + RESERVED0 :bit2; + EXTERNAL_SW_INT_OCCURRED :bit1; + SCP_INT_OCCURRED :bit1; + UC_INTERNAL_INT_OCCURRED :bit1; + UC_REG_RD_TIMEOUT_INT_OCCURRED :bit1; + DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED :bit1; + DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED:bit1; + DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED:bit1; + DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED:bit1; + DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED:bit1; + DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED:bit1; + DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED:bit1; + VBLANK1_INT_OCCURRED :bit1; + VBLANK2_INT_OCCURRED :bit1; + VBLANK3_INT_OCCURRED :bit1; + VBLANK4_INT_OCCURRED :bit1; + VBLANK5_INT_OCCURRED :bit1; + VBLANK6_INT_OCCURRED :bit1; + RESERVED1 :bit2; + end; + + TDMCU_TEST_DEBUG_INDEX=bitpacked record + DMCU_TEST_DEBUG_INDEX :bit8; + DMCU_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDMIF_TEST_DEBUG_INDEX=bitpacked record + DMIF_TEST_DEBUG_INDEX :bit8; + DMIF_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDOUT_TEST_DEBUG_INDEX=bitpacked record + DOUT_TEST_DEBUG_INDEX :bit8; + DOUT_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDP_DPHY_FAST_TRAINING=bitpacked record + DPHY_RX_FAST_TRAINING_CAPABLE :bit1; + DPHY_SW_FAST_TRAINING_START :bit1; + DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN:bit1; + RESERVED0 :bit5; + DPHY_FAST_TRAINING_TP1_TIME :bit12; + DPHY_FAST_TRAINING_TP2_TIME :bit12; + end; + + TDP_FE_TEST_DEBUG_DATA=bit32; + + TDP_SEC_AUD_M_READBACK=bitpacked record + DP_SEC_AUD_M_READBACK:bit24; + RESERVED0 :bit8; + end; + + TDP_SEC_AUD_N_READBACK=bitpacked record + DP_SEC_AUD_N_READBACK:bit24; + RESERVED0 :bit8; + end; + + TDP_VID_INTERRUPT_CNTL=bitpacked record + DP_VID_STREAM_DISABLE_INT :bit1; + DP_VID_STREAM_DISABLE_ACK :bit1; + DP_VID_STREAM_DISABLE_MASK:bit1; + RESERVED0 :bit29; + end; + + TDVO_FIFO_ERROR_STATUS=bitpacked record + DVO_FIFO_LEVEL_ERROR :bit1; + DVO_FIFO_USE_OVERWRITE_LEVEL:bit1; + DVO_FIFO_OVERWRITE_LEVEL :bit6; + DVO_FIFO_ERROR_ACK :bit1; + RESERVED0 :bit1; + DVO_FIFO_CAL_AVERAGE_LEVEL :bit6; + DVO_FIFO_MAXIMUM_LEVEL :bit4; + RESERVED1 :bit2; + DVO_FIFO_MINIMUM_LEVEL :bit4; + RESERVED2 :bit3; + DVO_FIFO_CALIBRATED :bit1; + DVO_FIFO_FORCE_RECAL_AVERAGE:bit1; + DVO_FIFO_FORCE_RECOMP_MINMAX:bit1; + end; + + TENTITY_TEMPERATURES_1=bit32; + + TFMT_BIT_DEPTH_CONTROL=bitpacked record + FMT_TRUNCATE_EN :bit1; + FMT_TRUNCATE_MODE :bit1; + RESERVED0 :bit2; + FMT_TRUNCATE_DEPTH :bit2; + RESERVED1 :bit2; + FMT_SPATIAL_DITHER_EN :bit1; + FMT_SPATIAL_DITHER_MODE :bit2; + FMT_SPATIAL_DITHER_DEPTH :bit2; + FMT_FRAME_RANDOM_ENABLE :bit1; + FMT_RGB_RANDOM_ENABLE :bit1; + FMT_HIGHPASS_RANDOM_ENABLE:bit1; + FMT_TEMPORAL_DITHER_EN :bit1; + FMT_TEMPORAL_DITHER_DEPTH :bit2; + RESERVED2 :bit2; + FMT_TEMPORAL_DITHER_OFFSET:bit2; + RESERVED3 :bit1; + FMT_TEMPORAL_LEVEL :bit1; + FMT_TEMPORAL_DITHER_RESET :bit1; + FMT_25FRC_SEL :bit2; + FMT_50FRC_SEL :bit2; + FMT_75FRC_SEL :bit2; + end; + + TFMT_CLAMP_COMPONENT_B=bitpacked record + FMT_CLAMP_LOWER_B:bit16; + FMT_CLAMP_UPPER_B:bit16; + end; + + TFMT_CLAMP_COMPONENT_G=bitpacked record + FMT_CLAMP_LOWER_G:bit16; + FMT_CLAMP_UPPER_G:bit16; + end; + + TFMT_CLAMP_COMPONENT_R=bitpacked record + FMT_CLAMP_LOWER_R:bit16; + FMT_CLAMP_UPPER_R:bit16; + end; + + TFMT_CRC_SIG_RED_GREEN=bitpacked record + FMT_CRC_SIG_RED :bit16; + FMT_CRC_SIG_GREEN:bit16; + end; + + TFMT_FORCE_OUTPUT_CNTL=bitpacked record + FMT_FORCE_DATA_EN :bit1; + RESERVED0 :bit7; + FMT_FORCE_DATA_SEL_COLOR :bit3; + RESERVED1 :bit1; + FMT_FORCE_DATA_SEL_SLOT :bit4; + FMT_FORCE_DATA_ON_BLANKB_ONLY:bit1; + RESERVED2 :bit15; + end; + + TGC_CAC_LKG_AGGR_LOWER=bit32; + + TGC_CAC_LKG_AGGR_UPPER=bit32; + + TGC_USER_RB_REDUNDANCY=bitpacked record + RESERVED0 :bit8; + FAILED_RB0 :bit4; + EN_REDUNDANCY0:bit1; + RESERVED1 :bit3; + FAILED_RB1 :bit4; + EN_REDUNDANCY1:bit1; + RESERVED2 :bit11; + end; + TGDS_GWS_RESOURCE_CNTL=bitpacked record INDEX :bit6; UNUSED:bit26; end; + TGENERIC_I2C_PIN_DEBUG=bitpacked record + GENERIC_I2C_SCL_OUTPUT:bit1; + GENERIC_I2C_SCL_INPUT :bit1; + GENERIC_I2C_SCL_EN :bit1; + RESERVED0 :bit1; + GENERIC_I2C_SDA_OUTPUT:bit1; + GENERIC_I2C_SDA_INPUT :bit1; + GENERIC_I2C_SDA_EN :bit1; + RESERVED1 :bit25; + end; + + TGPU_GARLIC_FLUSH_DONE=bitpacked record + CP0 :bit1; + CP1 :bit1; + CP2 :bit1; + CP3 :bit1; + CP4 :bit1; + CP5 :bit1; + CP6 :bit1; + CP7 :bit1; + CP8 :bit1; + CP9 :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + SDMA2 :bit1; + SDMA3 :bit1; + RESERVED0:bit18; + end; + TGRBM_WAIT_IDLE_CLOCKS=bitpacked record WAIT_IDLE_CLOCKS:bit8; RESERVED0 :bit24; end; + TGRPH_INTERRUPT_STATUS=bitpacked record + GRPH_PFLIP_INT_OCCURRED:bit1; + RESERVED0 :bit7; + GRPH_PFLIP_INT_CLEAR :bit1; + RESERVED1 :bit23; + end; + + TGRPH_LUT_10BIT_BYPASS=bitpacked record + RESERVED0 :bit8; + GRPH_LUT_10BIT_BYPASS_EN :bit1; + RESERVED1 :bit7; + GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN:bit1; + RESERVED2 :bit15; + end; + + TGRPH_SURFACE_OFFSET_X=bitpacked record + GRPH_SURFACE_OFFSET_X:bit14; + RESERVED0 :bit18; + end; + + TGRPH_SURFACE_OFFSET_Y=bitpacked record + GRPH_SURFACE_OFFSET_Y:bit14; + RESERVED0 :bit18; + end; + + THDP_NONSURF_FLAGS_CLR=bitpacked record + NONSURF_WRITE_FLAG_CLR:bit1; + NONSURF_READ_FLAG_CLR :bit1; + RESERVED0 :bit30; + end; + + THDP_XDP_CGTT_BLK_CTRL=bitpacked record + CGTT_BLK_CTRL_0_ON_DELAY :bit4; + CGTT_BLK_CTRL_1_OFF_DELAY :bit8; + CGTT_BLK_CTRL_2_RSVD :bit18; + CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE:bit1; + CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE :bit1; + end; + + THDP_XDP_P2P_MBX_ADDR0=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR1=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR2=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR3=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR4=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR5=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + THDP_XDP_P2P_MBX_ADDR6=bitpacked record + VALID :bit1; + ADDR :bit20; + ADDR_39_36:bit4; + RESERVED0 :bit7; + end; + + TIDDCCIF02_DBG_DCCIF_C=bit32; + + TIDDCCIF04_DBG_DCCIF_E=bit32; + + TIDDCCIF05_DBG_DCCIF_F=bit32; + + TLB_MEMORY_SIZE_STATUS=bitpacked record + LB_MEMORY_SIZE_STATUS:bit12; + RESERVED0 :bit20; + end; + + TLB_SNAPSHOT_V_COUNTER=bitpacked record + SNAPSHOT_V_COUNTER:bit15; + RESERVED0 :bit17; + end; + + TLCLK_DEEP_SLEEP_CNTL2=bitpacked record + RFE_BUSY_MASK :bit1; + BIF_CG_LCLK_BUSY_MASK :bit1; + L1IMU_SMU_IDLE_MASK :bit1; + RESERVED0 :bit1; + SCLK_RUNNING_MASK :bit1; + SMU_BUSY_MASK :bit1; + PCIE_LCLK_IDLE1_MASK :bit1; + PCIE_LCLK_IDLE2_MASK :bit1; + PCIE_LCLK_IDLE3_MASK :bit1; + PCIE_LCLK_IDLE4_MASK :bit1; + L1IMUGPP_IDLE_MASK :bit1; + L1IMUGPPSB_IDLE_MASK :bit1; + L1IMUBIF_IDLE_MASK :bit1; + L1IMUINTGEN_IDLE_MASK :bit1; + L2IMU_IDLE_MASK :bit1; + ORB_IDLE_MASK :bit1; + ON_INB_WAKE_MASK :bit1; + ON_INB_WAKE_ACK_MASK :bit1; + ON_OUTB_WAKE_MASK :bit1; + ON_OUTB_WAKE_ACK_MASK :bit1; + DMAACTIVE_MASK :bit1; + RLC_SMU_GFXCLK_OFF_MASK:bit1; + RESERVED :bit10; + end; + + TMASTER_COMM_DATA_REG1=bitpacked record + MASTER_COMM_DATA_REG1_BYTE0:bit8; + MASTER_COMM_DATA_REG1_BYTE1:bit8; + MASTER_COMM_DATA_REG1_BYTE2:bit8; + MASTER_COMM_DATA_REG1_BYTE3:bit8; + end; + + TMASTER_COMM_DATA_REG2=bitpacked record + MASTER_COMM_DATA_REG2_BYTE0:bit8; + MASTER_COMM_DATA_REG2_BYTE1:bit8; + MASTER_COMM_DATA_REG2_BYTE2:bit8; + MASTER_COMM_DATA_REG2_BYTE3:bit8; + end; + + TMASTER_COMM_DATA_REG3=bitpacked record + MASTER_COMM_DATA_REG3_BYTE0:bit8; + MASTER_COMM_DATA_REG3_BYTE1:bit8; + MASTER_COMM_DATA_REG3_BYTE2:bit8; + MASTER_COMM_DATA_REG3_BYTE3:bit8; + end; + + TMCIF_TEST_DEBUG_INDEX=bitpacked record + MCIF_TEST_DEBUG_INDEX :bit8; + MCIF_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TMCIF_WB_BUFMGR_STATUS=bitpacked record + MCIF_WB_BUFMGR_VCE_INT_STATUS:bit1; + MCIF_WB_BUFMGR_SW_INT_STATUS :bit1; + RESERVED0 :bit2; + MCIF_WB_BUFMGR_CUR_BUF :bit3; + MCIF_WB_BUF_DUALSIZE_STATUS :bit1; + MCIF_WB_BUFMGR_BUFTAG :bit4; + MCIF_WB_BUFMGR_CUR_LINE_L :bit13; + RESERVED1 :bit3; + MCIF_WB_BUFMGR_NEXT_BUF :bit3; + RESERVED2 :bit1; + end; + + TMCIF_WB_BUF_1_STATUS2=bitpacked record + MCIF_WB_BUF_1_CUR_LINE_R :bit13; + MCIF_WB_BUF_1_NEW_CONTENT:bit1; + MCIF_WB_BUF_1_COLOR_DEPTH:bit1; + RESERVED0 :bit17; + end; + + TMCIF_WB_BUF_2_STATUS2=bitpacked record + MCIF_WB_BUF_2_CUR_LINE_R :bit13; + MCIF_WB_BUF_2_NEW_CONTENT:bit1; + MCIF_WB_BUF_2_COLOR_DEPTH:bit1; + RESERVED0 :bit17; + end; + + TMCIF_WB_BUF_3_STATUS2=bitpacked record + MCIF_WB_BUF_3_CUR_LINE_R :bit13; + MCIF_WB_BUF_3_NEW_CONTENT:bit1; + MCIF_WB_BUF_3_COLOR_DEPTH:bit1; + RESERVED0 :bit17; + end; + + TMCIF_WB_BUF_4_STATUS2=bitpacked record + MCIF_WB_BUF_4_CUR_LINE_R :bit13; + MCIF_WB_BUF_4_NEW_CONTENT:bit1; + MCIF_WB_BUF_4_COLOR_DEPTH:bit1; + RESERVED0 :bit17; + end; + + TMC_ARB_DRAM_TIMING2_1=bitpacked record + RAS2RAS :bit8; + RP :bit8; + WRPLUSRP :bit8; + BUS_TURN :bit5; + RESERVED0:bit3; + end; + + TMC_ARB_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_ARB_PERFCOUNTER_LO=bit32; + + TMC_ARB_PERF_MON_CNTL0=bitpacked record + RESERVED0:bit12; + RESERVED1:bit12; + RESERVED2:bit2; + RESERVED3:bit2; + RESERVED4:bit1; + RESERVED5:bit3; + end; + + TMC_ARB_RET_CREDITS_RD=bitpacked record + LCL :bit8; + HUB :bit8; + DISP :bit8; + RETURN_CREDIT:bit8; + end; + + TMC_ARB_RET_CREDITS_WR=bitpacked record + LCL :bit8; + HUB :bit8; + RETURN_CREDIT :bit8; + WRRET_SEQ_SKID:bit4; + WRRET_BP :bit1; + RESERVED0 :bit3; + end; + + TMC_BIST_MISMATCH_ADDR=bitpacked record + COL :bit8; + ROW :bit16; + BANK :bit4; + RESERVED0:bit4; + end; + + TMC_FUS_DRAM0_CS0_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM0_CS1_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM0_CS2_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM0_CS3_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM0_CTL_BASE=bitpacked record + DCTSEL :bit3; + DCTINTLVEN :bit4; + DCTBASEADDR:bit21; + DCTOFFSETEN:bit1; + RESERVED0 :bit1; + RESERVED1 :bit2; + end; + + TMC_FUS_DRAM1_CS0_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM1_CS1_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM1_CS2_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM1_CS3_BASE=bitpacked record + CSENABLE :bit1; + RESERVED0 :bit4; + BASEADDR21_11:bit11; + RESERVED1 :bit3; + BASEADDR38_27:bit12; + RESERVED2 :bit1; + end; + + TMC_FUS_DRAM1_CTL_BASE=bitpacked record + DCTSEL :bit3; + DCTINTLVEN :bit4; + DCTBASEADDR:bit21; + DCTOFFSETEN:bit1; + RESERVED0 :bit1; + RESERVED1 :bit2; + end; + + TMC_FUS_DRAM_APER_BASE=bitpacked record + BASE :bit20; + RESERVED0:bit12; + end; + + TMC_GRUB_PROBE_CREDITS=bitpacked record + CREDITS_LIMIT_LO :bit6; + RESERVED0 :bit2; + CREDITS_LIMIT_HI :bit6; + RESERVED1 :bit1; + INTPRB_FIFO_LEVEL :bit1; + INTPRB_TIMEOUT_THRESH:bit3; + RESERVED2 :bit1; + MEM_TIMEOUT_THRESH :bit3; + RESERVED3 :bit9; + end; + + TMC_HUB_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_HUB_PERFCOUNTER_LO=bit32; + + TMC_HUB_RDREQ_CREDITS2=bitpacked record + STOR0_PRI:bit8; + STOR1_PRI:bit8; + RESERVED0:bit16; + end; + + TMC_HUB_RDREQ_ISP_CCPU=bitpacked record + ENABLE :bit1; + PRESCALE :bit2; + BLACKOUT_EXEMPT :bit1; + STALL_MODE :bit2; + STALL_OVERRIDE :bit1; + MAXBURST :bit4; + LAZY_TIMER :bit4; + STALL_OVERRIDE_WTM :bit1; + BYPASS_AVAIL_OVERRIDE:bit1; + PRIORITY_DISABLE :bit1; + STALL_FILTER_ENABLE :bit1; + STALL_THRESHOLD :bit6; + RESERVED0 :bit7; + end; + + TMC_HUB_RDREQ_WTM_CNTL=bitpacked record + GROUP0_DECREMENT:bit3; + GROUP1_DECREMENT:bit3; + GROUP2_DECREMENT:bit3; + GROUP3_DECREMENT:bit3; + GROUP4_DECREMENT:bit3; + GROUP5_DECREMENT:bit3; + GROUP6_DECREMENT:bit3; + GROUP7_DECREMENT:bit3; + RESERVED0 :bit8; + end; + + TMC_RPB_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_RPB_PERFCOUNTER_LO=bit32; + + TMC_RPB_RD_SWITCH_CNTL=bitpacked record + QUEUE0_SWITCH_NUM:bit8; + QUEUE1_SWITCH_NUM:bit8; + QUEUE2_SWITCH_NUM:bit8; + QUEUE3_SWITCH_NUM:bit8; + end; + + TMC_RPB_WR_SWITCH_CNTL=bitpacked record + QUEUE0_SWITCH_NUM:bit8; + QUEUE1_SWITCH_NUM:bit8; + QUEUE2_SWITCH_NUM:bit8; + QUEUE3_SWITCH_NUM:bit8; + end; + + TMC_SEQ_IO_DEBUG_INDEX=bitpacked record + IO_DEBUG_INDEX:bit9; + RESERVED0 :bit23; + end; + + TMC_SEQ_MISC_TIMING_LP=bitpacked record + TRP_WRA :bit6; + TRP_RDA :bit6; + TRP :bit5; + TRFC :bit7; + RESERVED0:bit4; + RESERVED1:bit4; + end; + + TMC_VM_MARC_RELOC_HI_0=bitpacked record + MARC_RELOC_HI_0:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_RELOC_HI_1=bitpacked record + MARC_RELOC_HI_1:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_RELOC_HI_2=bitpacked record + MARC_RELOC_HI_2:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_RELOC_HI_3=bitpacked record + MARC_RELOC_HI_3:bit20; + RESERVED0 :bit12; + end; + + TMC_VM_MARC_RELOC_LO_0=bitpacked record + MARC_ENABLE_0 :bit1; + MARC_READONLY_0:bit1; + RESERVED0 :bit10; + MARC_RELOC_LO_0:bit20; + end; + + TMC_VM_MARC_RELOC_LO_1=bitpacked record + MARC_ENABLE_1 :bit1; + MARC_READONLY_1:bit1; + RESERVED0 :bit10; + MARC_RELOC_LO_1:bit20; + end; + + TMC_VM_MARC_RELOC_LO_2=bitpacked record + MARC_ENABLE_2 :bit1; + MARC_READONLY_2:bit1; + RESERVED0 :bit10; + MARC_RELOC_LO_2:bit20; + end; + + TMC_VM_MARC_RELOC_LO_3=bitpacked record + MARC_ENABLE_3 :bit1; + MARC_READONLY_3:bit1; + RESERVED0 :bit10; + MARC_RELOC_LO_3:bit20; + end; + + TMC_VM_NB_TOP_OF_DRAM3=bitpacked record + TOM3_LIMIT :bit30; + RESERVED0 :bit1; + TOM3_ENABLE:bit1; + end; + + TMC_XBAR_ARB_MAX_BURST=bitpacked record + RD_PORT0:bit4; + RD_PORT1:bit4; + RD_PORT2:bit4; + RD_PORT3:bit4; + WR_PORT0:bit4; + WR_PORT1:bit4; + WR_PORT2:bit4; + WR_PORT3:bit4; + end; + + TMC_XBAR_RDRET_CREDIT1=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMC_XBAR_RDRET_CREDIT2=bitpacked record + OUT4 :bit8; + OUT5 :bit8; + HUB_LP_RDRET_SKID:bit8; + RESERVED0 :bit8; + end; + + TMC_XBAR_WRRET_CREDIT1=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMC_XBAR_WRRET_CREDIT2=bitpacked record + OUT4 :bit8; + OUT5 :bit8; + RESERVED0:bit16; + end; + + TMC_XPB_RTR_SRC_APRTR0=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR1=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR2=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR3=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR4=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR5=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR6=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR7=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR8=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_RTR_SRC_APRTR9=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_UNC_THRESH_HST=bitpacked record + CHANGE_PREF:bit6; + STRONG_PREF:bit6; + USE_UNFULL :bit6; + RESERVED0 :bit14; + end; + + TMC_XPB_UNC_THRESH_SID=bitpacked record + CHANGE_PREF:bit6; + STRONG_PREF:bit6; + USE_UNFULL :bit6; + RESERVED0 :bit14; + end; + + TMVP_RECEIVE_CNT_CNTL1=bitpacked record + MVP_SLAVE_PIXEL_ERROR_CNT:bit13; + RESERVED0 :bit3; + MVP_SLAVE_LINE_ERROR_CNT :bit13; + RESERVED1 :bit2; + MVP_SLAVE_DATA_CHK_EN :bit1; + end; + + TMVP_RECEIVE_CNT_CNTL2=bitpacked record + MVP_SLAVE_FRAME_ERROR_CNT :bit13; + RESERVED0 :bit18; + MVP_SLAVE_FRAME_ERROR_CNT_RESET:bit1; + end; + + TOUT_CLAMP_CONTROL_G_Y=bitpacked record + OUT_CLAMP_MAX_G_Y:bit14; + RESERVED0 :bit2; + OUT_CLAMP_MIN_G_Y:bit14; + RESERVED1 :bit2; + end; + TPA_CL_VPORT_XOFFSET_1=bit32; TPA_CL_VPORT_XOFFSET_2=bit32; @@ -10064,6 +45045,699 @@ type TPA_SU_PERFCOUNTER3_LO=bit32; + TPB0_PLL_LC0_CTRL_REG0=bitpacked record + PLL_DBG_LC_ANALOG_SEL_0 :bit2; + PLL_DBG_LC_EXT_RESET_EN_0:bit1; + PLL_DBG_LC_VCTL_ADC_EN_0 :bit1; + PLL_TST_LC_USAMPLE_EN_0 :bit1; + RESERVED0 :bit27; + end; + + TPB0_PLL_LC0_OVRD_REG0=bitpacked record + PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 :bit3; + PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0:bit3; + PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 :bit1; + PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 :bit1; + PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 :bit1; + PLL_CFG_LC_FBDIV_OVRD_VAL_0 :bit8; + PLL_CFG_LC_FBDIV_OVRD_EN_0 :bit1; + PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 :bit9; + PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_LC_REFDIV_OVRD_VAL_0 :bit2; + PLL_CFG_LC_REFDIV_OVRD_EN_0 :bit1; + end; + + TPB0_PLL_LC0_OVRD_REG1=bitpacked record + PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0:bit3; + PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 :bit1; + PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1; + PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 :bit1; + PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1; + PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1; + PLL_LC_PWRON_OVRD_VAL_0 :bit1; + PLL_LC_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit4; + PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 :bit4; + PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 :bit1; + RESERVED1 :bit13; + end; + + TPB0_PLL_RO0_CTRL_REG0=bitpacked record + PLL_DBG_RO_ANALOG_SEL_0 :bit2; + PLL_DBG_RO_EXT_RESET_EN_0:bit1; + PLL_DBG_RO_VCTL_ADC_EN_0 :bit1; + PLL_DBG_RO_LF_CNTRL_0 :bit7; + PLL_TST_RO_USAMPLE_EN_0 :bit1; + RESERVED0 :bit20; + end; + + TPB0_PLL_RO0_OVRD_REG0=bitpacked record + PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 :bit8; + PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 :bit3; + PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 :bit1; + PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 :bit1; + PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 :bit1; + PLL_CFG_RO_FBDIV_OVRD_VAL_0 :bit13; + PLL_CFG_RO_FBDIV_OVRD_EN_0 :bit1; + RESERVED0 :bit1; + PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0:bit1; + PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 :bit1; + end; + + TPB0_PLL_RO0_OVRD_REG1=bitpacked record + PLL_CFG_RO_REFDIV_OVRD_VAL_0 :bit5; + PLL_CFG_RO_REFDIV_OVRD_EN_0 :bit1; + PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 :bit2; + PLL_CFG_RO_VCO_MODE_OVRD_EN_0 :bit1; + PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1; + PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 :bit1; + PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1; + PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1; + PLL_RO_PWRON_OVRD_VAL_0 :bit1; + PLL_RO_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit4; + PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0:bit3; + PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 :bit1; + RESERVED1 :bit9; + end; + + TPB1_PLL_LC0_CTRL_REG0=bitpacked record + PLL_DBG_LC_ANALOG_SEL_0 :bit2; + PLL_DBG_LC_EXT_RESET_EN_0:bit1; + PLL_DBG_LC_VCTL_ADC_EN_0 :bit1; + PLL_TST_LC_USAMPLE_EN_0 :bit1; + RESERVED0 :bit27; + end; + + TPB1_PLL_LC0_OVRD_REG0=bitpacked record + PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0 :bit3; + PLL_CFG_LC_BW_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0:bit3; + PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0 :bit1; + PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0 :bit1; + PLL_CFG_LC_CORECLK_EN_OVRD_EN_0 :bit1; + PLL_CFG_LC_FBDIV_OVRD_VAL_0 :bit8; + PLL_CFG_LC_FBDIV_OVRD_EN_0 :bit1; + PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0 :bit9; + PLL_CFG_LC_LF_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_LC_REFDIV_OVRD_VAL_0 :bit2; + PLL_CFG_LC_REFDIV_OVRD_EN_0 :bit1; + end; + + TPB1_PLL_LC0_OVRD_REG1=bitpacked record + PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0:bit3; + PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0 :bit1; + PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1; + PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0 :bit1; + PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1; + PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1; + PLL_LC_PWRON_OVRD_VAL_0 :bit1; + PLL_LC_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit4; + PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0 :bit4; + PLL_CFG_LC_VCO_TUNE_OVRD_EN_0 :bit1; + RESERVED1 :bit13; + end; + + TPB1_PLL_RO0_CTRL_REG0=bitpacked record + PLL_DBG_RO_ANALOG_SEL_0 :bit2; + PLL_DBG_RO_EXT_RESET_EN_0:bit1; + PLL_DBG_RO_VCTL_ADC_EN_0 :bit1; + PLL_DBG_RO_LF_CNTRL_0 :bit7; + PLL_TST_RO_USAMPLE_EN_0 :bit1; + RESERVED0 :bit20; + end; + + TPB1_PLL_RO0_OVRD_REG0=bitpacked record + PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0 :bit8; + PLL_CFG_RO_BW_CNTRL_OVRD_EN_0 :bit1; + PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0 :bit3; + PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0 :bit1; + PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0 :bit1; + PLL_CFG_RO_CORECLK_EN_OVRD_EN_0 :bit1; + PLL_CFG_RO_FBDIV_OVRD_VAL_0 :bit13; + PLL_CFG_RO_FBDIV_OVRD_EN_0 :bit1; + RESERVED0 :bit1; + PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0:bit1; + PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0 :bit1; + end; + + TPB1_PLL_RO0_OVRD_REG1=bitpacked record + PLL_CFG_RO_REFDIV_OVRD_VAL_0 :bit5; + PLL_CFG_RO_REFDIV_OVRD_EN_0 :bit1; + PLL_CFG_RO_VCO_MODE_OVRD_VAL_0 :bit2; + PLL_CFG_RO_VCO_MODE_OVRD_EN_0 :bit1; + PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0 :bit1; + PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0 :bit1; + PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0:bit1; + PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0 :bit1; + PLL_RO_PWRON_OVRD_VAL_0 :bit1; + PLL_RO_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit4; + PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0:bit3; + PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0 :bit1; + RESERVED1 :bit9; + end; + + TPCIEP_SRIOV_PRIV_CTRL=bitpacked record + RX_SRIOV_VF_MAPPING_MODE :bit2; + SRIOV_SAVE_VFS_ON_VFENABLE_CLR:bit2; + RESERVED0 :bit28; + end; + + TPCIE_ACS_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_ADV_ERR_CAP_CNTL=bitpacked record + FIRST_ERR_PTR :bit5; + ECRC_GEN_CAP :bit1; + ECRC_GEN_EN :bit1; + ECRC_CHECK_CAP :bit1; + ECRC_CHECK_EN :bit1; + MULTI_HDR_RECD_CAP :bit1; + MULTI_HDR_RECD_EN :bit1; + TLP_PREFIX_LOG_PRESENT:bit1; + RESERVED0 :bit20; + end; + + TPCIE_ARI_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_ATS_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_BAR_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_DPA_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_LC_TRAINING_CNTL=bitpacked record + LC_TRAINING_CNTL :bit4; + LC_COMPLIANCE_RECEIVE :bit1; + LC_LOOK_FOR_MORE_NON_MATCHING_TS1:bit1; + LC_L0S_L1_TRAINING_CNTL_EN :bit1; + LC_L1_LONG_WAKE_FIX_EN :bit1; + LC_POWER_STATE :bit3; + LC_DONT_GO_TO_L0S_IF_L1_ARMED :bit1; + LC_INIT_SPD_CHG_WITH_CSR_EN :bit1; + LC_DISABLE_TRAINING_BIT_ARCH :bit1; + LC_WAIT_FOR_SETS_IN_RCFG :bit1; + LC_HOT_RESET_QUICK_EXIT_EN :bit1; + LC_EXTEND_WAIT_FOR_SKP :bit1; + LC_AUTONOMOUS_CHANGE_OFF :bit1; + LC_UPCONFIGURE_CAP_OFF :bit1; + LC_HW_LINK_DIS_EN :bit1; + LC_LINK_DIS_BY_HW :bit1; + LC_STATIC_TX_PIPE_COUNT_EN :bit1; + LC_ASPM_L1_NAK_TIMER_SEL :bit2; + LC_DONT_DEASSERT_RX_EN_IN_R_SPEED:bit1; + LC_DONT_DEASSERT_RX_EN_IN_TEST :bit1; + LC_RESET_ASPM_L1_NAK_TIMER :bit1; + LC_SHORT_RCFG_TIMEOUT :bit1; + LC_ALLOW_TX_L1_CONTROL :bit1; + LC_WAIT_FOR_FOM_VALID_AFTER_TRACK:bit1; + LC_EXTEND_EQ_REQ_TIME :bit2; + end; + + TPCIE_LTR_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_PERF_CNTL_TXCLK2=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PORT_VC_CAP_REG1=bitpacked record + EXT_VC_COUNT :bit3; + RESERVED0 :bit1; + LOW_PRIORITY_EXT_VC_COUNT:bit3; + RESERVED1 :bit1; + REF_CLK :bit2; + PORT_ARB_TABLE_ENTRY_SIZE:bit2; + RESERVED2 :bit20; + end; + + TPCIE_PORT_VC_CAP_REG2=bitpacked record + VC_ARB_CAP :bit8; + RESERVED0 :bit16; + VC_ARB_TABLE_OFFSET:bit8; + end; + + TPCIE_P_DECODER_STATUS=bitpacked record + P_DECODE_ERR:bit16; + RESERVED0 :bit16; + end; + + TPCIE_VC0_RESOURCE_CAP=bitpacked record + PORT_ARB_CAP :bit8; + RESERVED0 :bit7; + REJECT_SNOOP_TRANS :bit1; + MAX_TIME_SLOTS :bit6; + RESERVED1 :bit2; + PORT_ARB_TABLE_OFFSET:bit8; + end; + + TPCIE_VC1_RESOURCE_CAP=bitpacked record + PORT_ARB_CAP :bit8; + RESERVED0 :bit7; + REJECT_SNOOP_TRANS :bit1; + MAX_TIME_SLOTS :bit6; + RESERVED1 :bit2; + PORT_ARB_TABLE_OFFSET:bit8; + end; + + TPCIE_VENDOR_SPECIFIC1=bit32; + + TPCIE_VENDOR_SPECIFIC2=bit32; + + TPPLL_DIV_UPDATE_DEBUG=bitpacked record + PLL_REF_DIV_CHANGED :bit1; + PLL_FB_DIV_CHANGED :bit1; + PLL_UPDATE_PENDING :bit1; + PLL_UPDATE_CURRENT_STATE:bit2; + PLL_UPDATE_ENABLE :bit1; + PLL_UPDATE_REQ :bit1; + PLL_UPDATE_ACK :bit1; + RESERVED0 :bit24; + end; + + TPRESCALE_GRPH_CONTROL=bitpacked record + GRPH_PRESCALE_SELECT:bit1; + GRPH_PRESCALE_R_SIGN:bit1; + GRPH_PRESCALE_G_SIGN:bit1; + GRPH_PRESCALE_B_SIGN:bit1; + GRPH_PRESCALE_BYPASS:bit1; + RESERVED0 :bit27; + end; + + TPRESCALE_VALUES_OVL_Y=bitpacked record + OVL_PRESCALE_BIAS_Y :bit16; + OVL_PRESCALE_SCALE_Y:bit16; + end; + + TPWR_AVFS0_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS1_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS2_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS3_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS4_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS5_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS6_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS7_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS8_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS9_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_DISP_TIMER2_DEBUG=bitpacked record + DISP_TIMER_INT_RUNNING:bit1; + DISP_TIMER_INT_STAT :bit1; + DISP_TIMER_INT :bit1; + RESERVED0 :bit4; + DISP_TIMER_RUN_VAL :bit25; + end; + + TRAS_SIGNATURE_CONTROL=bitpacked record + ENABLE :bit1; + RESERVED0:bit31; + end; + + TRLC_GPM_CU_PD_TIMEOUT=bit32; + + TRLC_GPM_INT_FORCE_TH0=bit32; + + TRLC_GPM_INT_FORCE_TH1=bit32; + + TRLC_GPM_THREAD_ENABLE=bitpacked record + THREAD0_ENABLE:bit1; + THREAD1_ENABLE:bit1; + THREAD2_ENABLE:bit1; + THREAD3_ENABLE:bit1; + RESERVED0 :bit28; + end; + + TRLC_GPU_IOV_CFG_REG10=bitpacked record + TIME_QUANTA_PF:bit16; + RESERVED :bit16; + end; + + TRLC_GPU_IOV_CFG_REG11=bit32; + + TRLC_GPU_IOV_CFG_REG12=bitpacked record + TIME_QUANTA_VF0:bit8; + TIME_QUANTA_VF1:bit8; + TIME_QUANTA_VF2:bit8; + TIME_QUANTA_VF3:bit8; + end; + + TRLC_GPU_IOV_CFG_REG13=bitpacked record + TIME_QUANTA_VF4:bit8; + TIME_QUANTA_VF5:bit8; + TIME_QUANTA_VF6:bit8; + TIME_QUANTA_VF7:bit8; + end; + + TRLC_GPU_IOV_CFG_REG14=bitpacked record + TIME_QUANTA_VF8 :bit8; + TIME_QUANTA_VF9 :bit8; + TIME_QUANTA_VF10:bit8; + TIME_QUANTA_VF11:bit8; + end; + + TRLC_GPU_IOV_CFG_REG15=bitpacked record + TIME_QUANTA_VF12:bit8; + TIME_QUANTA_VF13:bit8; + TIME_QUANTA_VF14:bit8; + TIME_QUANTA_VF15:bit8; + end; + + TRLC_GPU_IOV_F32_RESET=bitpacked record + RESET :bit1; + RESERVED:bit31; + end; + + TRLC_GPU_IOV_INT_FORCE=bit32; + + TRLC_GPU_IOV_VF_ENABLE=bitpacked record + VF_ENABLE:bit1; + RESERVED :bit15; + VF_NUM :bit16; + end; + + TRLC_LOAD_BALANCE_CNTR=bit32; + + TSCLK_DEEP_SLEEP_CNTL2=bitpacked record + RLC_BUSY_MASK :bit1; + HDP_BUSY_MASK :bit1; + ROM_BUSY_MASK :bit1; + IH_SEM_BUSY_MASK :bit1; + PDMA_BUSY_MASK :bit1; + RESERVED0 :bit1; + IDCT_BUSY_MASK :bit1; + SDMA_BUSY_MASK :bit1; + DC_AZ_BUSY_MASK :bit1; + ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK:bit1; + UVD_CG_MC_STAT_BUSY_MASK :bit1; + VCE_CG_MC_STAT_BUSY_MASK :bit1; + SAM_CG_MC_STAT_BUSY_MASK :bit1; + SAM_CG_STATUS_BUSY_MASK :bit1; + RLC_SMU_GFXCLK_OFF_MASK :bit1; + RESERVED1 :bit5; + RESERVED2 :bit1; + SHALLOW_DIV_ID :bit3; + INOUT_CUSHION :bit8; + end; + + TSCLK_DEEP_SLEEP_CNTL3=bitpacked record + GRBM_0_SMU_BUSY_MASK :bit1; + GRBM_1_SMU_BUSY_MASK :bit1; + GRBM_2_SMU_BUSY_MASK :bit1; + GRBM_3_SMU_BUSY_MASK :bit1; + GRBM_4_SMU_BUSY_MASK :bit1; + GRBM_5_SMU_BUSY_MASK :bit1; + GRBM_6_SMU_BUSY_MASK :bit1; + GRBM_7_SMU_BUSY_MASK :bit1; + GRBM_8_SMU_BUSY_MASK :bit1; + GRBM_9_SMU_BUSY_MASK :bit1; + GRBM_10_SMU_BUSY_MASK:bit1; + GRBM_11_SMU_BUSY_MASK:bit1; + GRBM_12_SMU_BUSY_MASK:bit1; + GRBM_13_SMU_BUSY_MASK:bit1; + GRBM_14_SMU_BUSY_MASK:bit1; + GRBM_15_SMU_BUSY_MASK:bit1; + RESERVED0 :bit16; + end; + + TSCLV_HORZ_FILTER_INIT=bitpacked record + SCL_H_INIT_FRAC:bit24; + SCL_H_INIT_INT :bit4; + RESERVED0 :bit4; + end; + + TSCLV_MODE_CHANGE_DET1=bitpacked record + SCL_MODE_CHANGE :bit1; + RESERVED0 :bit3; + SCL_MODE_CHANGE_ACK :bit1; + RESERVED1 :bit2; + SCL_ALU_H_SCALE_RATIO:bit21; + RESERVED2 :bit4; + end; + + TSCLV_MODE_CHANGE_DET2=bitpacked record + SCL_ALU_V_SCALE_RATIO:bit21; + RESERVED0 :bit11; + end; + + TSCLV_MODE_CHANGE_DET3=bitpacked record + SCL_ALU_SOURCE_HEIGHT:bit14; + RESERVED0 :bit2; + SCL_ALU_SOURCE_WIDTH :bit14; + RESERVED1 :bit2; + end; + + TSCLV_MODE_CHANGE_MASK=bitpacked record + SCL_MODE_CHANGE_MASK:bit1; + RESERVED0 :bit31; + end; + + TSCLV_TEST_DEBUG_INDEX=bitpacked record + SCL_TEST_DEBUG_INDEX :bit8; + SCL_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TSCLV_VERT_FILTER_INIT=bitpacked record + SCL_V_INIT_FRAC:bit24; + SCL_V_INIT_INT :bit3; + RESERVED0 :bit5; + end; + + TSCLV_VIEWPORT_START_C=bitpacked record + VIEWPORT_Y_START_C:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START_C:bit14; + RESERVED1 :bit2; + end; + + TSCL_COEF_RAM_TAP_DATA=bitpacked record + SCL_C_RAM_EVEN_TAP_COEF :bit14; + RESERVED0 :bit1; + SCL_C_RAM_EVEN_TAP_COEF_EN:bit1; + SCL_C_RAM_ODD_TAP_COEF :bit14; + RESERVED1 :bit1; + SCL_C_RAM_ODD_TAP_COEF_EN :bit1; + end; + + TSDMA0_ATOMIC_PREOP_HI=bit32; + + TSDMA0_ATOMIC_PREOP_LO=bit32; + + TSDMA0_GFX_CSA_ADDR_HI=bit32; + + TSDMA0_GFX_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_GFX_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSDMA0_IB_OFFSET_FETCH=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA0_POWER_CNTL_IDLE=bitpacked record + DELAY1:bit16; + DELAY2:bit16; + end; + + TSDMA0_RLC0_IB_BASE_HI=bit32; + + TSDMA0_RLC0_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA0_RLC0_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSDMA0_RLC1_IB_BASE_HI=bit32; + + TSDMA0_RLC1_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA0_RLC1_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSDMA1_ATOMIC_PREOP_HI=bit32; + + TSDMA1_ATOMIC_PREOP_LO=bit32; + + TSDMA1_GFX_CSA_ADDR_HI=bit32; + + TSDMA1_GFX_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_GFX_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSDMA1_IB_OFFSET_FETCH=bitpacked record + RESERVED0:bit2; + OFFSET :bit20; + RESERVED1:bit10; + end; + + TSDMA1_POWER_CNTL_IDLE=bitpacked record + DELAY1:bit16; + DELAY2:bit16; + end; + + TSDMA1_RLC0_IB_BASE_HI=bit32; + + TSDMA1_RLC0_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA1_RLC0_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSDMA1_RLC1_IB_BASE_HI=bit32; + + TSDMA1_RLC1_IB_BASE_LO=bitpacked record + RESERVED0:bit5; + ADDR :bit27; + end; + + TSDMA1_RLC1_RB_BASE_HI=bitpacked record + ADDR :bit24; + RESERVED0:bit8; + end; + + TSLAVE_REQ_CREDIT_CNTL=bitpacked record + BIF_SRBM_REQ_CREDIT:bit5; + BIF_VGA_REQ_CREDIT :bit4; + RESERVED0 :bit1; + BIF_HDP_REQ_CREDIT :bit5; + BIF_ROM_REQ_CREDIT :bit1; + RESERVED1 :bit4; + BIF_AZ_REQ_CREDIT :bit1; + RESERVED2 :bit4; + BIF_XDMA_REQ_CREDIT:bit6; + RESERVED3 :bit1; + end; + + TSMU_INTERRUPT_CONTROL=bitpacked record + DC_SMU_INT_ENABLE:bit1; + RESERVED0 :bit3; + DC_SMU_INT_STATUS:bit1; + RESERVED1 :bit11; + DC_SMU_INT_EVENT :bit16; + end; + TSPI_SHADER_COL_FORMAT=bitpacked record COL0_EXPORT_FORMAT:bit4; COL1_EXPORT_FORMAT:bit4; @@ -10088,17 +45762,456 @@ type OVERRIDE_EN:bit1; end; + TSQ_FLAT_SCRATCH_WORD0=bitpacked record + SIZE :bit19; + RESERVED0:bit13; + end; + + TSQ_FLAT_SCRATCH_WORD1=bitpacked record + OFFSET :bit24; + RESERVED0:bit8; + end; + + TSQ_INTERRUPT_MSG_CTRL=bitpacked record + STALL :bit1; + RESERVED0:bit31; + end; + + TSQ_INTERRUPT_WORD_CMN=bitpacked record + RESERVED0:bit24; + SE_ID :bit2; + ENCODING :bit2; + RESERVED1:bit4; + end; + + TSQ_LB_DATA_ALU_CYCLES=bit32; + + TSQ_LB_DATA_ALU_STALLS=bit32; + + TSQ_LB_DATA_TEX_CYCLES=bit32; + + TSQ_LB_DATA_TEX_STALLS=bit32; + TSQ_THREAD_TRACE_BASE2=bitpacked record ADDR_HI :bit4; ATC :bit1; RESERVED0:bit27; end; + TSRBM_ISP_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_ISP_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_ISP_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SAM_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SAM_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SAM_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR3=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR4=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR5=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SYS_DOMAIN_ADDR6=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_UVD_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_UVD_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_UVD_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_VCE_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_VCE_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_VCE_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_VP8_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSWRST_GENERAL_CONTROL=bitpacked record + RECONFIGURE_EN :bit1; + ATOMIC_RESET_EN :bit1; + RESET_PERIOD :bit3; + RESERVED0 :bit3; + WAIT_LINKUP :bit1; + FORCE_REGIDLE :bit1; + BLOCK_ON_IDLE :bit1; + RESERVED1 :bit1; + CONFIG_XFER_MODE :bit1; + MUXSEL_XFER_MODE :bit1; + HLDTRAIN_XFER_MODE:bit1; + RESERVED2 :bit1; + BYPASS_HOLD :bit1; + BYPASS_PIF_HOLD :bit1; + RESERVED3 :bit10; + EP_COMPLT_CHK_EN :bit1; + EP_COMPLT_WAIT_TMR:bit2; + RESERVED4 :bit1; + end; + TTA_CS_BC_BASE_ADDR_HI=bitpacked record ADDRESS :bit8; RESERVED0:bit24; end; + TTHM_TMON0_RDIL10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIL15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON0_RDIR15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIL15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON1_RDIR15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIL15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR10_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR11_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR12_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR13_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR14_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TTHM_TMON2_RDIR15_DATA=bitpacked record + Z :bit11; + VALID :bit1; + TEMP :bit12; + RESERVED0:bit8; + end; + + TUSER_SQC_BANK_DISABLE=bitpacked record + RESERVED0 :bit16; + SQC0_BANK_DISABLE:bit4; + SQC1_BANK_DISABLE:bit4; + SQC2_BANK_DISABLE:bit4; + SQC3_BANK_DISABLE:bit4; + end; + + TUVD_LMI_VMID_INTERNAL=bitpacked record + VCPU_NC0_VMID:bit4; + VCPU_NC1_VMID:bit4; + DPB_VMID :bit4; + DBW_VMID :bit4; + LBSI_VMID :bit4; + IDCT_VMID :bit4; + JPEG_VMID :bit4; + JPEG2_VMID :bit4; + end; + + TVDDGFX_IDLE_PARAMETER=bitpacked record + VDDGFX_IDLE_THRESHOLD :bit16; + VDDGFX_IDLE_THRESHOLD_UNIT:bit4; + RESERVED0 :bit12; + end; + + TVGA_INTERRUPT_CONTROL=bitpacked record + VGA_MEM_ACCESS_INT_MASK :bit1; + RESERVED0 :bit7; + VGA_REG_ACCESS_INT_MASK :bit1; + RESERVED1 :bit7; + VGA_DISPLAY_SWITCH_INT_MASK :bit1; + RESERVED2 :bit7; + VGA_MODE_AUTO_TRIGGER_INT_MASK:bit1; + RESERVED3 :bit7; + end; + TVGT_DMA_NUM_INSTANCES=bit32; TVGT_EVENT_ADDRESS_REG=bitpacked record @@ -10138,6 +46251,127 @@ type TRAP_SPLIT :bit3; end; + TVM_INVALIDATE_REQUEST=bitpacked record + INVALIDATE_DOMAIN_0 :bit1; + INVALIDATE_DOMAIN_1 :bit1; + INVALIDATE_DOMAIN_2 :bit1; + INVALIDATE_DOMAIN_3 :bit1; + INVALIDATE_DOMAIN_4 :bit1; + INVALIDATE_DOMAIN_5 :bit1; + INVALIDATE_DOMAIN_6 :bit1; + INVALIDATE_DOMAIN_7 :bit1; + INVALIDATE_DOMAIN_8 :bit1; + INVALIDATE_DOMAIN_9 :bit1; + INVALIDATE_DOMAIN_10:bit1; + INVALIDATE_DOMAIN_11:bit1; + INVALIDATE_DOMAIN_12:bit1; + INVALIDATE_DOMAIN_13:bit1; + INVALIDATE_DOMAIN_14:bit1; + INVALIDATE_DOMAIN_15:bit1; + RESERVED0 :bit16; + end; + + TXDMA_MSTR_CHANNEL_DIM=bitpacked record + XDMA_MSTR_CHANNEL_WIDTH :bit14; + RESERVED0 :bit2; + XDMA_MSTR_CHANNEL_HEIGHT:bit14; + RESERVED1 :bit2; + end; + + TXDMA_PERF_MEAS_STATUS=bitpacked record + XDMA_PERF_MEAS_STATUS:bit8; + RESERVED0 :bit24; + end; + + TXDMA_RBBMIF_RDWR_CNTL=bitpacked record + XDMA_RBBMIF_RDWR_DELAY :bit3; + XDMA_RBBMIF_RDWR_TIMEOUT_DIS:bit1; + RESERVED0 :bit11; + XDMA_RBBMIF_TIMEOUT_DELAY :bit17; + end; + + TXDMA_SLV_CHANNEL_CNTL=bitpacked record + XDMA_SLV_CHANNEL_WEIGHT :bit9; + RESERVED0 :bit7; + XDMA_SLV_STOP_TRANSFER :bit1; + XDMA_SLV_CHANNEL_SOFT_RESET:bit1; + RESERVED1 :bit6; + XDMA_SLV_CHANNEL_ACTIVE :bit1; + RESERVED2 :bit7; + end; + + TXDMA_SLV_FLIP_PENDING=bitpacked record + XDMA_SLV_FLIP_PENDING:bit1; + RESERVED0 :bit31; + end; + + TXDMA_SLV_WB_RATE_CNTL=bitpacked record + XDMA_SLV_WB_BURST_SIZE :bit9; + RESERVED0 :bit7; + XDMA_SLV_WB_BURST_PERIOD:bit16; + end; + + TXDMA_TEST_DEBUG_INDEX=bitpacked record + XDMA_TEST_DEBUG_INDEX :bit8; + XDMA_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TAFMT_AUDIO_CRC_CONTROL=bitpacked record + AFMT_AUDIO_CRC_EN :bit1; + RESERVED0 :bit3; + AFMT_AUDIO_CRC_CONT :bit1; + RESERVED1 :bit3; + AFMT_AUDIO_CRC_SOURCE:bit1; + RESERVED2 :bit3; + AFMT_AUDIO_CRC_CH_SEL:bit4; + AFMT_AUDIO_CRC_COUNT :bit16; + end; + + TAFMT_AUDIO_SRC_CONTROL=bitpacked record + AFMT_AUDIO_SRC_SELECT:bit3; + RESERVED0 :bit29; + end; + + TATC_VM_APERTURE0_CNTL2=bitpacked record + VMIDS_USING_RANGE:bit16; + RESERVED0 :bit16; + end; + + TATC_VM_APERTURE1_CNTL2=bitpacked record + VMIDS_USING_RANGE:bit16; + RESERVED0 :bit16; + end; + + TAVSYNC_COUNTER_CONTROL=bitpacked record + AVSYNC_COUNTER_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_BDL_DMA_CONTROL=bitpacked record + BDL_DMA_NON_SNOOP :bit2; + INPUT_BDL_DMA_NON_SNOOP :bit2; + BDL_DMA_ISOCHRONOUS :bit2; + INPUT_BDL_DMA_ISOCHRONOUS:bit2; + RESERVED0 :bit24; + end; + + TBLND_REG_UPDATE_STATUS=bitpacked record + DCP_BLNDC_GRPH_UPDATE_PENDING :bit1; + DCP_BLNDO_GRPH_UPDATE_PENDING :bit1; + DCP_BLNDC_GRPH_SURF_UPDATE_PENDING:bit1; + DCP_BLNDO_GRPH_SURF_UPDATE_PENDING:bit1; + DCP_BLNDC_OVL_UPDATE_PENDING :bit1; + DCP_BLNDO_OVL_UPDATE_PENDING :bit1; + DCP_BLNDC_CUR_UPDATE_PENDING :bit1; + DCP_BLNDO_CUR_UPDATE_PENDING :bit1; + SCL_BLNDC_UPDATE_PENDING :bit1; + SCL_BLNDO_UPDATE_PENDING :bit1; + BLND_BLNDC_UPDATE_PENDING :bit1; + BLND_BLNDO_UPDATE_PENDING :bit1; + RESERVED0 :bit20; + end; + TCB_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit9; RESERVED0 :bit1; @@ -10166,6 +46400,228 @@ type PERF_MODE:bit4; end; + TCC_SMU_TST_EFUSE1_MISC=bitpacked record + RESERVED0 :bit1; + RF_RM_6_2 :bit5; + RME :bit1; + MBIST_DISABLE :bit1; + HARD_REPAIR_DISABLE:bit1; + SOFT_REPAIR_DISABLE:bit1; + GPU_DIS :bit1; + SMS_PWRDWN_DISABLE :bit1; + CRBBMP1500_DISA :bit1; + CRBBMP1500_DISB :bit1; + RM_RF8 :bit1; + RESERVED1 :bit7; + DFT_SPARE1 :bit1; + DFT_SPARE2 :bit1; + DFT_SPARE3 :bit1; + VCE_DISABLE :bit1; + DCE_SCAN_DISABLE :bit1; + RESERVED2 :bit5; + end; + + TCGTS_CU10_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU10_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU11_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU11_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU12_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU12_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU13_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU13_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU14_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU14_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU15_SP0_CTRL_REG=bitpacked record + SP00 :bit7; + SP00_OVERRIDE :bit1; + SP00_BUSY_OVERRIDE :bit2; + SP00_LS_OVERRIDE :bit1; + SP00_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP01 :bit7; + SP01_OVERRIDE :bit1; + SP01_BUSY_OVERRIDE :bit2; + SP01_LS_OVERRIDE :bit1; + SP01_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU15_SP1_CTRL_REG=bitpacked record + SP10 :bit7; + SP10_OVERRIDE :bit1; + SP10_BUSY_OVERRIDE :bit2; + SP10_LS_OVERRIDE :bit1; + SP10_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SP11 :bit7; + SP11_OVERRIDE :bit1; + SP11_BUSY_OVERRIDE :bit2; + SP11_LS_OVERRIDE :bit1; + SP11_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCG_MULT_THERMAL_STATUS=bitpacked record + ASIC_MAX_TEMP:bit9; + CTF_TEMP :bit9; + RESERVED0 :bit14; + end; + + TCNV_CSC_ROUND_OFFSET_B=bitpacked record + CNV_CSC_ROUND_OFFSET_B:bit16; + RESERVED0 :bit16; + end; + + TCNV_CSC_ROUND_OFFSET_G=bitpacked record + CNV_CSC_ROUND_OFFSET_G:bit16; + RESERVED0 :bit16; + end; + + TCNV_CSC_ROUND_OFFSET_R=bitpacked record + CNV_CSC_ROUND_OFFSET_R:bit16; + RESERVED0 :bit16; + end; + TCOMPUTE_THREADGROUP_ID=bit32; TCP_CE_PRGRM_CNTR_START=bitpacked record @@ -10263,6 +46719,11 @@ type TCP_MEC_ME2_HEADER_DUMP=bit32; + TCP_ME_PRGRM_CNTR_START=bitpacked record + IP_START :bit12; + RESERVED0:bit20; + end; + TCP_PFP_ATOMIC_PREOP_HI=bit32; TCP_PFP_ATOMIC_PREOP_LO=bit32; @@ -10272,18 +46733,26 @@ type TCP_PRT_LOD_STATS_CNTL1=bit32; TCP_PRT_LOD_STATS_CNTL2=bitpacked record - BASE_HI :bit2; - INTERVAL :bit8; - RESET_CNT :bit8; - RESET_FORCE :bit1; - REPORT_AND_RESET :bit1; - MC_ENDIAN_SWAP__SI__CI:bit2; - RESERVED0 :bit1; - MC_VMID :bit4; - RESERVED1 :bit1; - CACHE_POLICY :bit1; - RESERVED2 :bit1; - MTYPE :bit2; + BASE_HI :bit2; + INTERVAL :bit8; + RESET_CNT :bit8; + RESET_FORCE :bit1; + REPORT_AND_RESET:bit1; + MC_ENDIAN_SWAP :bit2; + RESERVED0 :bit1; + MC_VMID :bit4; + RESERVED1 :bit1; + CACHE_POLICY :bit1; + RESERVED2 :bit1; + MTYPE :bit2; + end; + + TCP_RB_DOORBELL_CONTROL=bitpacked record + RESERVED0 :bit2; + DOORBELL_OFFSET:bit21; + RESERVED1 :bit7; + DOORBELL_EN :bit1; + DOORBELL_HIT :bit1; end; TCP_VGT_GSPRIM_COUNT_HI=bit32; @@ -10298,6 +46767,109 @@ type TCP_VGT_IAVERT_COUNT_LO=bit32; + TCRTC_H_BLANK_EARLY_NUM=bitpacked record + CRTC_H_BLANK_EARLY_NUM :bit10; + RESERVED0 :bit6; + CRTC_H_BLANK_EARLY_NUM_DIS:bit1; + RESERVED1 :bit15; + end; + + TCRTC_H_BLANK_START_END=bitpacked record + CRTC_H_BLANK_START:bit14; + RESERVED0 :bit2; + CRTC_H_BLANK_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_INTERLACE_CONTROL=bitpacked record + CRTC_INTERLACE_ENABLE :bit1; + RESERVED0 :bit15; + CRTC_INTERLACE_FORCE_NEXT_FIELD:bit2; + RESERVED1 :bit14; + end; + + TCRTC_INTERRUPT_CONTROL=bitpacked record + CRTC_SNAPSHOT_INT_MSK :bit1; + CRTC_SNAPSHOT_INT_TYPE :bit1; + RESERVED0 :bit2; + CRTC_V_UPDATE_INT_MSK :bit1; + CRTC_V_UPDATE_INT_TYPE :bit1; + RESERVED1 :bit2; + CRTC_FORCE_COUNT_NOW_INT_MSK :bit1; + CRTC_FORCE_COUNT_NOW_INT_TYPE :bit1; + RESERVED2 :bit6; + CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK :bit1; + CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE:bit1; + RESERVED3 :bit6; + CRTC_TRIGA_INT_MSK :bit1; + CRTC_TRIGB_INT_MSK :bit1; + CRTC_TRIGA_INT_TYPE :bit1; + CRTC_TRIGB_INT_TYPE :bit1; + CRTC_VSYNC_NOM_INT_MSK :bit1; + CRTC_VSYNC_NOM_INT_TYPE :bit1; + CRTC_GSL_VSYNC_GAP_INT_MSK :bit1; + CRTC_GSL_VSYNC_GAP_INT_TYPE :bit1; + end; + + TCRTC_NOM_VERT_POSITION=bitpacked record + CRTC_VERT_COUNT_NOM:bit14; + RESERVED0 :bit18; + end; + + TCRTC_SNAPSHOT_POSITION=bitpacked record + CRTC_SNAPSHOT_VERT_COUNT:bit14; + RESERVED0 :bit2; + CRTC_SNAPSHOT_HORZ_COUNT:bit14; + RESERVED1 :bit2; + end; + + TCRTC_TRIGA_MANUAL_TRIG=bitpacked record + CRTC_TRIGA_MANUAL_TRIG:bit1; + RESERVED0 :bit31; + end; + + TCRTC_TRIGB_MANUAL_TRIG=bitpacked record + CRTC_TRIGB_MANUAL_TRIG:bit1; + RESERVED0 :bit31; + end; + + TCRTC_VERT_SYNC_CONTROL=bitpacked record + CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED:bit1; + RESERVED0 :bit7; + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR :bit1; + RESERVED1 :bit7; + CRTC_AUTO_FORCE_VSYNC_MODE :bit2; + RESERVED2 :bit14; + end; + + TCRTC_V_BLANK_START_END=bitpacked record + CRTC_V_BLANK_START:bit14; + RESERVED0 :bit2; + CRTC_V_BLANK_END :bit14; + RESERVED1 :bit2; + end; + + TDAC_AUTODETECT_CONTROL=bitpacked record + DAC_AUTODETECT_MODE :bit2; + RESERVED0 :bit6; + DAC_AUTODETECT_FRAME_TIME_COUNTER:bit8; + DAC_AUTODETECT_CHECK_MASK :bit3; + RESERVED1 :bit13; + end; + + TDAC_AUTO_CALIB_CONTROL=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit10; + RESERVED5:bit6; + RESERVED6:bit3; + RESERVED7:bit5; + RESERVED8:bit1; + RESERVED9:bit3; + end; + TDB_OCCLUSION_COUNT0_HI=bitpacked record COUNT_HI :bit31; RESERVED0:bit1; @@ -10350,6 +46922,186 @@ type PERF_MODE :bit4; end; + TDCCG_AUDIO_DTO0_MODULE=bit32; + + TDCCG_AUDIO_DTO1_MODULE=bit32; + + TDCCG_GATE_DISABLE_CNTL=bitpacked record + DISPCLK_DCCG_GATE_DISABLE :bit1; + DISPCLK_R_DCCG_GATE_DISABLE :bit1; + SCLK_GATE_DISABLE :bit1; + DPREFCLK_GATE_DISABLE :bit1; + DACACLK_GATE_DISABLE :bit1; + DACBCLK_GATE_DISABLE :bit1; + DVOACLK_GATE_DISABLE :bit1; + DPDBG_CLK_GATE_DISABLE :bit1; + DPREFCLK_R_DCCG_GATE_DISABLE:bit1; + RESERVED0 :bit7; + PCLK_TV_GATE_DISABLE :bit1; + AOMCLK0_GATE_DISABLE :bit1; + AOMCLK1_GATE_DISABLE :bit1; + AOMCLK2_GATE_DISABLE :bit1; + DISPCLK_R_DCCG_RAMP_DISABLE :bit1; + AUDIO_DTO2_CLK_GATE_DISABLE :bit1; + DPREFCLK_GTC_GATE_DISABLE :bit1; + UNB_DB_CLK_GATE_DISABLE :bit1; + RESERVED1 :bit2; + REFCLK_GATE_DISABLE :bit1; + REFCLK_R_DIG_GATE_DISABLE :bit1; + DSICLK_GATE_DISABLE :bit1; + BYTECLK_GATE_DISABLE :bit1; + ESCCLK_GATE_DISABLE :bit1; + RESERVED2 :bit1; + end; + + TDCP_FP_CONVERTED_FIELD=bitpacked record + DCP_FP_CONVERTED_FIELD_DATA :bit18; + RESERVED0 :bit2; + DCP_FP_CONVERTED_FIELD_INDEX:bit7; + RESERVED1 :bit5; + end; + + TDC_ABM1_BL_MASTER_LOCK=bitpacked record + RESERVED0 :bit31; + ABM1_BL_MASTER_LOCK:bit1; + end; + + TDC_ABM1_HG_SAMPLE_RATE=bitpacked record + ABM1_HG_SAMPLE_RATE_COUNT_EN :bit1; + ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER :bit1; + RESERVED0 :bit6; + ABM1_HG_SAMPLE_RATE_FRAME_COUNT :bit8; + ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8; + RESERVED1 :bit7; + ABM1_HGLS_REG_LOCK :bit1; + end; + + TDC_ABM1_LS_PIXEL_COUNT=bitpacked record + ABM1_LS_PIXEL_COUNT:bit24; + RESERVED0 :bit8; + end; + + TDC_ABM1_LS_SAMPLE_RATE=bitpacked record + ABM1_LS_SAMPLE_RATE_COUNT_EN :bit1; + ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER :bit1; + RESERVED0 :bit6; + ABM1_LS_SAMPLE_RATE_FRAME_COUNT :bit8; + ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8; + RESERVED1 :bit7; + ABM1_HGLS_REG_LOCK :bit1; + end; + + TDC_ABM1_LS_SUM_OF_LUMA=bit32; + + TDC_GPIO_PAD_STRENGTH_1=bitpacked record + GENLK_STRENGTH_SN :bit4; + GENLK_STRENGTH_SP :bit4; + RX_HPD_STRENGTH_SN:bit4; + RX_HPD_STRENGTH_SP:bit4; + RESERVED0 :bit8; + SYNC_STRENGTH_SN :bit4; + SYNC_STRENGTH_SP :bit4; + end; + + TDC_GPIO_PAD_STRENGTH_2=bitpacked record + STRENGTH_SN :bit4; + STRENGTH_SP :bit4; + EXT_RESET_DRVSTRENGTH:bit3; + RESERVED0 :bit1; + REF_27_DRVSTRENGTH :bit3; + RESERVED1 :bit1; + PWRSEQ_STRENGTH_SN :bit4; + PWRSEQ_STRENGTH_SP :bit4; + RESERVED2 :bit6; + REF_27_SRC_SEL :bit2; + end; + + TDC_GPU_TIMER_READ_CNTL=bitpacked record + DC_GPU_TIMER_READ_SELECT :bit6; + RESERVED0 :bit2; + DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM:bit3; + DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM:bit3; + DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM:bit3; + DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM:bit3; + DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM:bit3; + DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM:bit3; + RESERVED1 :bit6; + end; + + TDC_HPD_FAST_TRAIN_CNTL=bitpacked record + DC_HPD_CONNECT_AUX_TX_DELAY :bit8; + RESERVED0 :bit4; + DC_HPD_CONNECT_FAST_TRAIN_DELAY:bit8; + RESERVED1 :bit4; + DC_HPD_CONNECT_AUX_TX_EN :bit1; + RESERVED2 :bit3; + DC_HPD_CONNECT_FAST_TRAIN_EN :bit1; + RESERVED3 :bit3; + end; + + TDENORM_CLAMP_RANGE_G_Y=bitpacked record + RANGE_CLAMP_MAX_G_Y:bit12; + RANGE_CLAMP_MIN_G_Y:bit12; + RESERVED0 :bit8; + end; + + TDIG_FE_TEST_DEBUG_DATA=bit32; + + TDMCU_FW_ISR_START_ADDR=bitpacked record + FW_ISR_START_ADDR_LSB:bit8; + FW_ISR_START_ADDR_MSB:bit8; + RESERVED0 :bit16; + end; + + TDP_DPHY_CRC_MST_STATUS=bitpacked record + DPHY_CRC_MST_PHASE_LOCK :bit1; + RESERVED0 :bit7; + DPHY_CRC_MST_PHASE_ERROR :bit1; + RESERVED1 :bit7; + DPHY_CRC_MST_PHASE_ERROR_ACK:bit1; + RESERVED2 :bit15; + end; + + TDP_FE_TEST_DEBUG_INDEX=bitpacked record + DP_FE_TEST_DEBUG_INDEX :bit8; + DP_FE_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TFBC_CLIENT_REGION_MASK=bitpacked record + RESERVED0 :bit16; + FBC_MEMORY_REGION_MASK:bit4; + RESERVED1 :bit12; + end; + + TFBC_DEBUG_CSR_RDATA_HI=bitpacked record + FBC_DEBUG_CSR_RDATA_HI:bit8; + RESERVED0 :bit24; + end; + + TFBC_DEBUG_CSR_WDATA_HI=bitpacked record + FBC_DEBUG_CSR_WDATA_HI:bit8; + RESERVED0 :bit24; + end; + + TFMT_DITHER_RAND_B_SEED=bitpacked record + FMT_RAND_B_SEED:bit8; + RESERVED0 :bit8; + FMT_OFFSET_B_CB:bit16; + end; + + TFMT_DITHER_RAND_G_SEED=bitpacked record + FMT_RAND_G_SEED:bit8; + RESERVED0 :bit8; + FMT_OFFSET_G_Y :bit16; + end; + + TFMT_DITHER_RAND_R_SEED=bitpacked record + FMT_RAND_R_SEED:bit8; + RESERVED0 :bit8; + FMT_OFFSET_R_CR:bit16; + end; + TGDS_GWS_RESOURCE_RESET=bitpacked record RESET :bit1; RESERVED0 :bit7; @@ -10357,6 +47109,39 @@ type RESERVED1 :bit16; end; + TGRPH_INTERRUPT_CONTROL=bitpacked record + GRPH_PFLIP_INT_MASK:bit1; + RESERVED0 :bit7; + GRPH_PFLIP_INT_TYPE:bit1; + RESERVED1 :bit23; + end; + + THDP_SC_MULTI_CHIP_CNTL=bitpacked record + LOG2_NUM_CHIPS :bit3; + MULTI_CHIP_TILE_SIZE:bit2; + RESERVED0 :bit27; + end; + + THDP_XDP_D2H_BAR_UPDATE=bitpacked record + D2H_BAR_UPDATE_ADDR :bit16; + D2H_BAR_UPDATE_FLUSH_NUM:bit4; + D2H_BAR_UPDATE_BAR_NUM :bit3; + RESERVED0 :bit9; + end; + + THDP_XDP_HDP_MBX_MC_CFG=bitpacked record + HDP_MBX_MC_CFG_TAP_WRREQ_PRIV:bit1; + HDP_MBX_MC_CFG_TAP_WRREQ_SWAP:bit2; + HDP_MBX_MC_CFG_TAP_WRREQ_TRAN:bit1; + HDP_MBX_MC_CFG_TAP_WRREQ_VMID:bit4; + RESERVED0 :bit24; + end; + + THDP_XDP_P2P_MBX_OFFSET=bitpacked record + P2P_MBX_OFFSET:bit14; + RESERVED0 :bit18; + end; + TIA_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit10; PERF_SEL1 :bit10; @@ -10383,6 +47168,577 @@ type PERF_MODE:bit4; end; + TIH_PERFCOUNTER0_RESULT=bit32; + + TIH_PERFCOUNTER1_RESULT=bit32; + + TLBV_MEMORY_SIZE_STATUS=bitpacked record + LB_MEMORY_SIZE_STATUS:bit12; + RESERVED0 :bit20; + end; + + TLBV_SNAPSHOT_V_COUNTER=bitpacked record + SNAPSHOT_V_COUNTER:bit15; + RESERVED0 :bit17; + end; + + TLB_BUFFER_LEVEL_STATUS=bitpacked record + REQ_FIFO_LEVEL :bit6; + RESERVED0 :bit4; + REQ_FIFO_FULL_CNTL :bit6; + DATA_BUFFER_LEVEL :bit12; + DATA_FIFO_FULL_CNTL:bit4; + end; + + TLB_BUFFER_URGENCY_CTRL=bitpacked record + LB_BUFFER_URGENCY_MARK_ON :bit12; + RESERVED0 :bit4; + LB_BUFFER_URGENCY_MARK_OFF:bit12; + RESERVED1 :bit4; + end; + + TLB_KEYER_COLOR_REP_G_Y=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_G_Y:bit12; + RESERVED1 :bit16; + end; + + TMAILBOX_MSGBUF_RCV_DW0=bit32; + + TMAILBOX_MSGBUF_RCV_DW1=bit32; + + TMAILBOX_MSGBUF_RCV_DW2=bit32; + + TMAILBOX_MSGBUF_RCV_DW3=bit32; + + TMAILBOX_MSGBUF_TRN_DW0=bit32; + + TMAILBOX_MSGBUF_TRN_DW1=bit32; + + TMAILBOX_MSGBUF_TRN_DW2=bit32; + + TMAILBOX_MSGBUF_TRN_DW3=bit32; + + TMCIF_WB_HVVMID_CONTROL=bitpacked record + RESERVED0 :bit8; + MCIF_WB_DEFAULT_VMID :bit4; + RESERVED1 :bit4; + MCIF_WB_ALLOWED_VMID_MASK:bit16; + end; + + TMC_ARB_HARSH_BWCNT0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_BWCNT0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_BWCNT1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_BWCNT1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_TX_HI0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_TX_HI0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_TX_HI1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_TX_HI1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_TX_LO0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_TX_LO0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_TX_LO1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_TX_LO1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_CITF_CREDITS_ARB_RD=bitpacked record + READ_LCL :bit8; + READ_HUB :bit8; + READ_PRI :bit8; + LCL_PRI :bit1; + HUB_PRI :bit1; + RESERVED0:bit6; + end; + + TMC_CITF_CREDITS_ARB_WR=bitpacked record + WRITE_LCL:bit8; + WRITE_HUB:bit8; + WRITE_PRI:bit8; + HUB_PRI :bit1; + LCL_PRI :bit1; + RESERVED0:bit6; + end; + + TMC_CITF_INT_CREDITS_WR=bitpacked record + CNTR_WR_HUB:bit6; + CNTR_WR_LCL:bit6; + RESERVED0 :bit20; + end; + + TMC_CITF_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_CITF_PERFCOUNTER_LO=bit32; + + TMC_CITF_PERF_MON_CNTL2=bitpacked record + CID :bit9; + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit18; + end; + + TMC_CITF_PERF_MON_RSLT2=bitpacked record + RESERVED0 :bit1; + CB_RD_BUSY :bit1; + DB_RD_BUSY :bit1; + TC0_RD_BUSY :bit1; + VC0_RD_BUSY :bit1; + TC1_RD_BUSY :bit1; + VC1_RD_BUSY :bit1; + CB_WR_BUSY :bit1; + DB_WR_BUSY :bit1; + SX_WR_BUSY :bit1; + TC2_RD_BUSY :bit1; + TC0_WR_BUSY :bit1; + TC1_WR_BUSY :bit1; + TC2_WR_BUSY :bit1; + TC0_ATOM_BUSY:bit1; + TC1_ATOM_BUSY:bit1; + TC2_ATOM_BUSY:bit1; + CB_ATOM_BUSY :bit1; + DB_ATOM_BUSY :bit1; + RESERVED1 :bit13; + end; + + TMC_FUS_ARB_GARLIC_CNTL=bitpacked record + RX_RDRESP_FIFO_PTR_INIT_VALUE:bit8; + RX_WRRESP_FIFO_PTR_INIT_VALUE:bit7; + EN_64_BYTE_WRITE :bit1; + EDC_RESPONSE_ENABLE :bit1; + OUTSTANDING_RDRESP_LIMIT :bit9; + OUTSTANDING_WRRESP_LIMIT :bit6; + end; + + TMC_FUS_DRAM0_CTL_LIMIT=bitpacked record + DCTLIMITADDR :bit21; + DRAMHOLEVALID:bit1; + RESERVED0 :bit10; + end; + + TMC_FUS_DRAM1_CTL_LIMIT=bitpacked record + DCTLIMITADDR :bit21; + DRAMHOLEVALID:bit1; + RESERVED0 :bit10; + end; + + TMC_GRUB_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_GRUB_PERFCOUNTER_LO=bit32; + + TMC_HUB_SHARED_DAGB_DLY=bitpacked record + DLY :bit6; + RESERVED0:bit10; + CLI :bit6; + RESERVED1:bit2; + POS :bit5; + RESERVED2:bit3; + end; + + TMC_HUB_WDP_BYPASS_GBL0=bitpacked record + ENABLE :bit1; + CID1 :bit8; + CID2 :bit8; + HDP_PRIORITY_TIME:bit7; + OTH_PRIORITY_TIME:bit7; + RESERVED0 :bit1; + end; + + TMC_HUB_WDP_BYPASS_GBL1=bitpacked record + ENABLE :bit1; + CID1 :bit8; + CID2 :bit8; + HDP_PRIORITY_TIME:bit7; + OTH_PRIORITY_TIME:bit7; + RESERVED0 :bit1; + end; + + TMC_IO_RXCNTL1_DPHY0_D0=bitpacked record + VREFCAL1_MSB:bit4; + VREFCAL2_MSB:bit4; + VREFCAL3 :bit8; + VREFSEL2 :bit1; + VREFSEL3 :bit1; + VREFPDNB_1 :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + PMD_LOOPBACK:bit3; + DLL_RSV :bit4; + end; + + TMC_IO_RXCNTL1_DPHY0_D1=bitpacked record + VREFCAL1_MSB:bit4; + VREFCAL2_MSB:bit4; + VREFCAL3 :bit8; + VREFSEL2 :bit1; + VREFSEL3 :bit1; + VREFPDNB_1 :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + PMD_LOOPBACK:bit3; + DLL_RSV :bit4; + end; + + TMC_IO_RXCNTL1_DPHY1_D0=bitpacked record + VREFCAL1_MSB:bit4; + VREFCAL2_MSB:bit4; + VREFCAL3 :bit8; + VREFSEL2 :bit1; + VREFSEL3 :bit1; + VREFPDNB_1 :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + PMD_LOOPBACK:bit3; + DLL_RSV :bit4; + end; + + TMC_IO_RXCNTL1_DPHY1_D1=bitpacked record + VREFCAL1_MSB:bit4; + VREFCAL2_MSB:bit4; + VREFCAL3 :bit8; + VREFSEL2 :bit1; + VREFSEL3 :bit1; + VREFPDNB_1 :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + PMD_LOOPBACK:bit3; + DLL_RSV :bit4; + end; + + TMC_RPB_WR_COMBINE_CNTL=bitpacked record + WC_ENABLE :bit1; + WC_MAX_PACKET_SIZE:bit2; + WC_FLUSH_TIMER :bit4; + WC_ALIGN :bit1; + RESERVED0 :bit24; + end; + + TMC_SEQ_MISC_TIMING2_LP=bitpacked record + PA2RDATA :bit3; + PA2WDATA :bit3; + FAW :bit5; + RESERVED0:bit3; + RESERVED1:bit3; + RESERVED2:bit4; + TWDATATR :bit4; + RESERVED3:bit7; + end; + + TMC_VM_MB_L1_TLB0_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MB_L1_TLB1_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MB_L1_TLB2_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MB_L1_TLB3_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MB_L1_TLS0_CNTL0=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL1=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL2=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL3=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL4=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL5=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL6=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL7=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MB_L1_TLS0_CNTL8=bitpacked record + REQ_STREAM_ID:bit9; + RESERVED0 :bit3; + EN :bit1; + PREFETCH_DONE:bit1; + RESERVED1 :bit18; + end; + + TMC_VM_MD_L1_TLB0_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MD_L1_TLB1_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MD_L1_TLB2_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_VM_MD_L1_TLB3_DEBUG=bitpacked record + INVALIDATE_L1_TLB :bit1; + RESERVED0 :bit7; + SEND_FREE_AT_RTN :bit1; + EFFECTIVE_L1_TLB_SIZE :bit3; + EFFECTIVE_L1_QUEUE_SIZE:bit3; + L1_TLB_DEBUG :bit4; + L1_TLB_FORCE_MISS :bit1; + RESERVED1 :bit12; + end; + + TMC_XBAR_FIFO_MON_CNTL0=bitpacked record + START_THRESH:bit12; + STOP_THRESH :bit12; + START_MODE :bit2; + STOP_MODE :bit2; + ALLOW_WRAP :bit1; + RESERVED0 :bit3; + end; + + TMC_XBAR_FIFO_MON_CNTL1=bitpacked record + THRESH_CNTR_ID:bit8; + START_TRIG_ID :bit8; + STOP_TRIG_ID :bit8; + RESERVED0 :bit8; + end; + + TMC_XBAR_FIFO_MON_CNTL2=bitpacked record + MON0_ID:bit8; + MON1_ID:bit8; + MON2_ID:bit8; + MON3_ID:bit8; + end; + + TMC_XBAR_FIFO_MON_RSLT0=bit32; + + TMC_XBAR_FIFO_MON_RSLT1=bit32; + + TMC_XBAR_FIFO_MON_RSLT2=bit32; + + TMC_XBAR_FIFO_MON_RSLT3=bit32; + + TMVP_AFR_FLIP_FIFO_CNTL=bitpacked record + MVP_AFR_FLIP_FIFO_NUM_ENTRIES:bit4; + MVP_AFR_FLIP_FIFO_RESET :bit1; + RESERVED0 :bit3; + MVP_AFR_FLIP_FIFO_RESET_FLAG :bit1; + RESERVED1 :bit3; + MVP_AFR_FLIP_FIFO_RESET_ACK :bit1; + RESERVED2 :bit19; + end; + + TOUT_CLAMP_CONTROL_B_CB=bitpacked record + OUT_CLAMP_MAX_B_CB:bit14; + RESERVED0 :bit2; + OUT_CLAMP_MIN_B_CB:bit14; + RESERVED1 :bit2; + end; + + TOUT_CLAMP_CONTROL_R_CR=bitpacked record + OUT_CLAMP_MAX_R_CR:bit14; + RESERVED0 :bit2; + OUT_CLAMP_MIN_R_CR:bit14; + RESERVED1 :bit2; + end; + + TOVLSCL_EDGE_PIXEL_CNTL=bitpacked record + OVLSCL_BLACK_COLOR_BCB:bit10; + OVLSCL_BLACK_COLOR_GY :bit10; + OVLSCL_BLACK_COLOR_RCR:bit10; + RESERVED0 :bit1; + OVLSCL_EDGE_PIXEL_SEL :bit1; + end; + TPA_CL_GB_HORZ_CLIP_ADJ=bit32; TPA_CL_GB_HORZ_DISC_ADJ=bit32; @@ -10442,6 +47798,1207 @@ type YMAX_BOTTOM_EXCLUSION :bit1; end; + TPB0_PIF_BIF_CMD_STATUS=bitpacked record + TXPHYSTATUS_0:bit1; + TXPHYSTATUS_1:bit1; + TXPHYSTATUS_2:bit1; + TXPHYSTATUS_3:bit1; + TXPHYSTATUS_4:bit1; + TXPHYSTATUS_5:bit1; + TXPHYSTATUS_6:bit1; + TXPHYSTATUS_7:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RXPHYSTATUS_0:bit1; + RXPHYSTATUS_1:bit1; + RXPHYSTATUS_2:bit1; + RXPHYSTATUS_3:bit1; + RXPHYSTATUS_4:bit1; + RXPHYSTATUS_5:bit1; + RXPHYSTATUS_6:bit1; + RXPHYSTATUS_7:bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + end; + + TPB0_RX_LANE0_CTRL_REG0=bitpacked record + RX_BACKUP_0 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_0:bit2; + RX_TST_BSCAN_EN_0 :bit1; + RX_CFG_OVR_PWRSF_0 :bit1; + RX_TERM_EN_0 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE1_CTRL_REG0=bitpacked record + RX_BACKUP_1 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_1:bit2; + RX_TST_BSCAN_EN_1 :bit1; + RX_CFG_OVR_PWRSF_1 :bit1; + RX_TERM_EN_1 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE2_CTRL_REG0=bitpacked record + RX_BACKUP_2 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_2:bit2; + RX_TST_BSCAN_EN_2 :bit1; + RX_CFG_OVR_PWRSF_2 :bit1; + RX_TERM_EN_2 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE3_CTRL_REG0=bitpacked record + RX_BACKUP_3 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_3:bit2; + RX_TST_BSCAN_EN_3 :bit1; + RX_CFG_OVR_PWRSF_3 :bit1; + RX_TERM_EN_3 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE4_CTRL_REG0=bitpacked record + RX_BACKUP_4 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_4:bit2; + RX_TST_BSCAN_EN_4 :bit1; + RX_CFG_OVR_PWRSF_4 :bit1; + RX_TERM_EN_4 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE5_CTRL_REG0=bitpacked record + RX_BACKUP_5 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_5:bit2; + RX_TST_BSCAN_EN_5 :bit1; + RX_CFG_OVR_PWRSF_5 :bit1; + RX_TERM_EN_5 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE6_CTRL_REG0=bitpacked record + RX_BACKUP_6 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_6:bit2; + RX_TST_BSCAN_EN_6 :bit1; + RX_CFG_OVR_PWRSF_6 :bit1; + RX_TERM_EN_6 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE7_CTRL_REG0=bitpacked record + RX_BACKUP_7 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_7:bit2; + RX_TST_BSCAN_EN_7 :bit1; + RX_CFG_OVR_PWRSF_7 :bit1; + RX_TERM_EN_7 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE8_CTRL_REG0=bitpacked record + RX_BACKUP_8 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_8:bit2; + RX_TST_BSCAN_EN_8 :bit1; + RX_CFG_OVR_PWRSF_8 :bit1; + RX_TERM_EN_8 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE9_CTRL_REG0=bitpacked record + RX_BACKUP_9 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_9:bit2; + RX_TST_BSCAN_EN_9 :bit1; + RX_CFG_OVR_PWRSF_9 :bit1; + RX_TERM_EN_9 :bit1; + RESERVED1 :bit17; + end; + + TPB0_TX_LANE0_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_0 :bit1; + TX_CFG_INV_DATA_0 :bit1; + TX_CFG_SWING_BOOST_EN_0:bit1; + TX_DBG_PRBS_EN_0 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE0_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_0 :bit1; + TX_DCLK_EN_OVRD_EN_0 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_0 :bit1; + TX_DRV_DATA_EN_OVRD_EN_0 :bit1; + TX_DRV_PWRON_OVRD_VAL_0 :bit1; + TX_DRV_PWRON_OVRD_EN_0 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_0:bit1; + TX_FRONTEND_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE1_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_1 :bit1; + TX_CFG_INV_DATA_1 :bit1; + TX_CFG_SWING_BOOST_EN_1:bit1; + TX_DBG_PRBS_EN_1 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE1_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_1 :bit1; + TX_DCLK_EN_OVRD_EN_1 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_1 :bit1; + TX_DRV_DATA_EN_OVRD_EN_1 :bit1; + TX_DRV_PWRON_OVRD_VAL_1 :bit1; + TX_DRV_PWRON_OVRD_EN_1 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_1:bit1; + TX_FRONTEND_PWRON_OVRD_EN_1 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE2_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_2 :bit1; + TX_CFG_INV_DATA_2 :bit1; + TX_CFG_SWING_BOOST_EN_2:bit1; + TX_DBG_PRBS_EN_2 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE2_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_2 :bit1; + TX_DCLK_EN_OVRD_EN_2 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_2 :bit1; + TX_DRV_DATA_EN_OVRD_EN_2 :bit1; + TX_DRV_PWRON_OVRD_VAL_2 :bit1; + TX_DRV_PWRON_OVRD_EN_2 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_2:bit1; + TX_FRONTEND_PWRON_OVRD_EN_2 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE3_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_3 :bit1; + TX_CFG_INV_DATA_3 :bit1; + TX_CFG_SWING_BOOST_EN_3:bit1; + TX_DBG_PRBS_EN_3 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE3_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_3 :bit1; + TX_DCLK_EN_OVRD_EN_3 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_3 :bit1; + TX_DRV_DATA_EN_OVRD_EN_3 :bit1; + TX_DRV_PWRON_OVRD_VAL_3 :bit1; + TX_DRV_PWRON_OVRD_EN_3 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_3:bit1; + TX_FRONTEND_PWRON_OVRD_EN_3 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE4_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_4 :bit1; + TX_CFG_INV_DATA_4 :bit1; + TX_CFG_SWING_BOOST_EN_4:bit1; + TX_DBG_PRBS_EN_4 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE4_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_4 :bit1; + TX_DCLK_EN_OVRD_EN_4 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_4 :bit1; + TX_DRV_DATA_EN_OVRD_EN_4 :bit1; + TX_DRV_PWRON_OVRD_VAL_4 :bit1; + TX_DRV_PWRON_OVRD_EN_4 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_4:bit1; + TX_FRONTEND_PWRON_OVRD_EN_4 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE5_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_5 :bit1; + TX_CFG_INV_DATA_5 :bit1; + TX_CFG_SWING_BOOST_EN_5:bit1; + TX_DBG_PRBS_EN_5 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE5_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_5 :bit1; + TX_DCLK_EN_OVRD_EN_5 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_5 :bit1; + TX_DRV_DATA_EN_OVRD_EN_5 :bit1; + TX_DRV_PWRON_OVRD_VAL_5 :bit1; + TX_DRV_PWRON_OVRD_EN_5 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_5:bit1; + TX_FRONTEND_PWRON_OVRD_EN_5 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE6_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_6 :bit1; + TX_CFG_INV_DATA_6 :bit1; + TX_CFG_SWING_BOOST_EN_6:bit1; + TX_DBG_PRBS_EN_6 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE6_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_6 :bit1; + TX_DCLK_EN_OVRD_EN_6 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_6 :bit1; + TX_DRV_DATA_EN_OVRD_EN_6 :bit1; + TX_DRV_PWRON_OVRD_VAL_6 :bit1; + TX_DRV_PWRON_OVRD_EN_6 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_6:bit1; + TX_FRONTEND_PWRON_OVRD_EN_6 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE7_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_7 :bit1; + TX_CFG_INV_DATA_7 :bit1; + TX_CFG_SWING_BOOST_EN_7:bit1; + TX_DBG_PRBS_EN_7 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE7_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_7 :bit1; + TX_DCLK_EN_OVRD_EN_7 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_7 :bit1; + TX_DRV_DATA_EN_OVRD_EN_7 :bit1; + TX_DRV_PWRON_OVRD_VAL_7 :bit1; + TX_DRV_PWRON_OVRD_EN_7 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_7:bit1; + TX_FRONTEND_PWRON_OVRD_EN_7 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE8_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_8 :bit1; + TX_CFG_INV_DATA_8 :bit1; + TX_CFG_SWING_BOOST_EN_8:bit1; + TX_DBG_PRBS_EN_8 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE8_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_8 :bit1; + TX_DCLK_EN_OVRD_EN_8 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_8 :bit1; + TX_DRV_DATA_EN_OVRD_EN_8 :bit1; + TX_DRV_PWRON_OVRD_VAL_8 :bit1; + TX_DRV_PWRON_OVRD_EN_8 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_8:bit1; + TX_FRONTEND_PWRON_OVRD_EN_8 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE9_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_9 :bit1; + TX_CFG_INV_DATA_9 :bit1; + TX_CFG_SWING_BOOST_EN_9:bit1; + TX_DBG_PRBS_EN_9 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE9_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_9 :bit1; + TX_DCLK_EN_OVRD_EN_9 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_9 :bit1; + TX_DRV_DATA_EN_OVRD_EN_9 :bit1; + TX_DRV_PWRON_OVRD_VAL_9 :bit1; + TX_DRV_PWRON_OVRD_EN_9 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_9:bit1; + TX_FRONTEND_PWRON_OVRD_EN_9 :bit1; + RESERVED0 :bit24; + end; + + TPB1_PIF_BIF_CMD_STATUS=bitpacked record + TXPHYSTATUS_0:bit1; + TXPHYSTATUS_1:bit1; + TXPHYSTATUS_2:bit1; + TXPHYSTATUS_3:bit1; + TXPHYSTATUS_4:bit1; + TXPHYSTATUS_5:bit1; + TXPHYSTATUS_6:bit1; + TXPHYSTATUS_7:bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RXPHYSTATUS_0:bit1; + RXPHYSTATUS_1:bit1; + RXPHYSTATUS_2:bit1; + RXPHYSTATUS_3:bit1; + RXPHYSTATUS_4:bit1; + RXPHYSTATUS_5:bit1; + RXPHYSTATUS_6:bit1; + RXPHYSTATUS_7:bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + end; + + TPB1_RX_LANE0_CTRL_REG0=bitpacked record + RX_BACKUP_0 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_0:bit2; + RX_TST_BSCAN_EN_0 :bit1; + RX_CFG_OVR_PWRSF_0 :bit1; + RX_TERM_EN_0 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE1_CTRL_REG0=bitpacked record + RX_BACKUP_1 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_1:bit2; + RX_TST_BSCAN_EN_1 :bit1; + RX_CFG_OVR_PWRSF_1 :bit1; + RX_TERM_EN_1 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE2_CTRL_REG0=bitpacked record + RX_BACKUP_2 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_2:bit2; + RX_TST_BSCAN_EN_2 :bit1; + RX_CFG_OVR_PWRSF_2 :bit1; + RX_TERM_EN_2 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE3_CTRL_REG0=bitpacked record + RX_BACKUP_3 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_3:bit2; + RX_TST_BSCAN_EN_3 :bit1; + RX_CFG_OVR_PWRSF_3 :bit1; + RX_TERM_EN_3 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE4_CTRL_REG0=bitpacked record + RX_BACKUP_4 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_4:bit2; + RX_TST_BSCAN_EN_4 :bit1; + RX_CFG_OVR_PWRSF_4 :bit1; + RX_TERM_EN_4 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE5_CTRL_REG0=bitpacked record + RX_BACKUP_5 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_5:bit2; + RX_TST_BSCAN_EN_5 :bit1; + RX_CFG_OVR_PWRSF_5 :bit1; + RX_TERM_EN_5 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE6_CTRL_REG0=bitpacked record + RX_BACKUP_6 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_6:bit2; + RX_TST_BSCAN_EN_6 :bit1; + RX_CFG_OVR_PWRSF_6 :bit1; + RX_TERM_EN_6 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE7_CTRL_REG0=bitpacked record + RX_BACKUP_7 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_7:bit2; + RX_TST_BSCAN_EN_7 :bit1; + RX_CFG_OVR_PWRSF_7 :bit1; + RX_TERM_EN_7 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE8_CTRL_REG0=bitpacked record + RX_BACKUP_8 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_8:bit2; + RX_TST_BSCAN_EN_8 :bit1; + RX_CFG_OVR_PWRSF_8 :bit1; + RX_TERM_EN_8 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE9_CTRL_REG0=bitpacked record + RX_BACKUP_9 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_9:bit2; + RX_TST_BSCAN_EN_9 :bit1; + RX_CFG_OVR_PWRSF_9 :bit1; + RX_TERM_EN_9 :bit1; + RESERVED1 :bit17; + end; + + TPB1_TX_LANE0_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_0 :bit1; + TX_CFG_INV_DATA_0 :bit1; + TX_CFG_SWING_BOOST_EN_0:bit1; + TX_DBG_PRBS_EN_0 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE0_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_0 :bit1; + TX_DCLK_EN_OVRD_EN_0 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_0 :bit1; + TX_DRV_DATA_EN_OVRD_EN_0 :bit1; + TX_DRV_PWRON_OVRD_VAL_0 :bit1; + TX_DRV_PWRON_OVRD_EN_0 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_0:bit1; + TX_FRONTEND_PWRON_OVRD_EN_0 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE1_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_1 :bit1; + TX_CFG_INV_DATA_1 :bit1; + TX_CFG_SWING_BOOST_EN_1:bit1; + TX_DBG_PRBS_EN_1 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE1_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_1 :bit1; + TX_DCLK_EN_OVRD_EN_1 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_1 :bit1; + TX_DRV_DATA_EN_OVRD_EN_1 :bit1; + TX_DRV_PWRON_OVRD_VAL_1 :bit1; + TX_DRV_PWRON_OVRD_EN_1 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_1:bit1; + TX_FRONTEND_PWRON_OVRD_EN_1 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE2_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_2 :bit1; + TX_CFG_INV_DATA_2 :bit1; + TX_CFG_SWING_BOOST_EN_2:bit1; + TX_DBG_PRBS_EN_2 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE2_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_2 :bit1; + TX_DCLK_EN_OVRD_EN_2 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_2 :bit1; + TX_DRV_DATA_EN_OVRD_EN_2 :bit1; + TX_DRV_PWRON_OVRD_VAL_2 :bit1; + TX_DRV_PWRON_OVRD_EN_2 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_2:bit1; + TX_FRONTEND_PWRON_OVRD_EN_2 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE3_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_3 :bit1; + TX_CFG_INV_DATA_3 :bit1; + TX_CFG_SWING_BOOST_EN_3:bit1; + TX_DBG_PRBS_EN_3 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE3_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_3 :bit1; + TX_DCLK_EN_OVRD_EN_3 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_3 :bit1; + TX_DRV_DATA_EN_OVRD_EN_3 :bit1; + TX_DRV_PWRON_OVRD_VAL_3 :bit1; + TX_DRV_PWRON_OVRD_EN_3 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_3:bit1; + TX_FRONTEND_PWRON_OVRD_EN_3 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE4_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_4 :bit1; + TX_CFG_INV_DATA_4 :bit1; + TX_CFG_SWING_BOOST_EN_4:bit1; + TX_DBG_PRBS_EN_4 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE4_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_4 :bit1; + TX_DCLK_EN_OVRD_EN_4 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_4 :bit1; + TX_DRV_DATA_EN_OVRD_EN_4 :bit1; + TX_DRV_PWRON_OVRD_VAL_4 :bit1; + TX_DRV_PWRON_OVRD_EN_4 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_4:bit1; + TX_FRONTEND_PWRON_OVRD_EN_4 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE5_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_5 :bit1; + TX_CFG_INV_DATA_5 :bit1; + TX_CFG_SWING_BOOST_EN_5:bit1; + TX_DBG_PRBS_EN_5 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE5_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_5 :bit1; + TX_DCLK_EN_OVRD_EN_5 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_5 :bit1; + TX_DRV_DATA_EN_OVRD_EN_5 :bit1; + TX_DRV_PWRON_OVRD_VAL_5 :bit1; + TX_DRV_PWRON_OVRD_EN_5 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_5:bit1; + TX_FRONTEND_PWRON_OVRD_EN_5 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE6_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_6 :bit1; + TX_CFG_INV_DATA_6 :bit1; + TX_CFG_SWING_BOOST_EN_6:bit1; + TX_DBG_PRBS_EN_6 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE6_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_6 :bit1; + TX_DCLK_EN_OVRD_EN_6 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_6 :bit1; + TX_DRV_DATA_EN_OVRD_EN_6 :bit1; + TX_DRV_PWRON_OVRD_VAL_6 :bit1; + TX_DRV_PWRON_OVRD_EN_6 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_6:bit1; + TX_FRONTEND_PWRON_OVRD_EN_6 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE7_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_7 :bit1; + TX_CFG_INV_DATA_7 :bit1; + TX_CFG_SWING_BOOST_EN_7:bit1; + TX_DBG_PRBS_EN_7 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE7_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_7 :bit1; + TX_DCLK_EN_OVRD_EN_7 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_7 :bit1; + TX_DRV_DATA_EN_OVRD_EN_7 :bit1; + TX_DRV_PWRON_OVRD_VAL_7 :bit1; + TX_DRV_PWRON_OVRD_EN_7 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_7:bit1; + TX_FRONTEND_PWRON_OVRD_EN_7 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE8_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_8 :bit1; + TX_CFG_INV_DATA_8 :bit1; + TX_CFG_SWING_BOOST_EN_8:bit1; + TX_DBG_PRBS_EN_8 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE8_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_8 :bit1; + TX_DCLK_EN_OVRD_EN_8 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_8 :bit1; + TX_DRV_DATA_EN_OVRD_EN_8 :bit1; + TX_DRV_PWRON_OVRD_VAL_8 :bit1; + TX_DRV_PWRON_OVRD_EN_8 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_8:bit1; + TX_FRONTEND_PWRON_OVRD_EN_8 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE9_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_9 :bit1; + TX_CFG_INV_DATA_9 :bit1; + TX_CFG_SWING_BOOST_EN_9:bit1; + TX_DBG_PRBS_EN_9 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE9_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_9 :bit1; + TX_DCLK_EN_OVRD_EN_9 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_9 :bit1; + TX_DRV_DATA_EN_OVRD_EN_9 :bit1; + TX_DRV_PWRON_OVRD_VAL_9 :bit1; + TX_DRV_PWRON_OVRD_EN_9 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_9:bit1; + TX_FRONTEND_PWRON_OVRD_EN_9 :bit1; + RESERVED0 :bit24; + end; + + TPCIE_LANE_ERROR_STATUS=bitpacked record + LANE_ERROR_STATUS_BITS:bit16; + RESERVED0 :bit16; + end; + + TPCIE_LC_BW_CHANGE_CNTL=bitpacked record + LC_BW_CHANGE_INT_EN :bit1; + LC_HW_INIT_SPEED_CHANGE :bit1; + LC_SW_INIT_SPEED_CHANGE :bit1; + LC_OTHER_INIT_SPEED_CHANGE :bit1; + LC_RELIABILITY_SPEED_CHANGE :bit1; + LC_FAILED_SPEED_NEG :bit1; + LC_LONG_LW_CHANGE :bit1; + LC_SHORT_LW_CHANGE :bit1; + LC_LW_CHANGE_OTHER :bit1; + LC_LW_CHANGE_FAILED :bit1; + LC_LINK_BW_NOTIFICATION_DETECT_MODE:bit1; + RESERVED0 :bit21; + end; + + TPCIE_PERF_COUNT0_TXCLK=bit32; + + TPCIE_PERF_COUNT1_TXCLK=bit32; + + TPCIE_PRBS_USER_PATTERN=bitpacked record + PRBS_USER_PATTERN:bit30; + RESERVED0 :bit2; + end; + + TPCIE_P_RCV_L0S_FTS_DET=bitpacked record + P_RCV_L0S_FTS_DET_MIN:bit8; + P_RCV_L0S_FTS_DET_MAX:bit8; + RESERVED0 :bit16; + end; + + TPCIE_SRIOV_INITIAL_VFS=bitpacked record + SRIOV_INITIAL_VFS:bit16; + RESERVED0 :bit16; + end; + + TPCIE_TX_CREDITS_ADVT_P=bitpacked record + TX_CREDITS_ADVT_PD:bit12; + RESERVED0 :bit4; + TX_CREDITS_ADVT_PH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_CREDITS_INIT_P=bitpacked record + TX_CREDITS_INIT_PD:bit12; + RESERVED0 :bit4; + TX_CREDITS_INIT_PH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_CREDITS_STATUS=bitpacked record + TX_CREDITS_ERR_PD :bit1; + TX_CREDITS_ERR_PH :bit1; + TX_CREDITS_ERR_NPD :bit1; + TX_CREDITS_ERR_NPH :bit1; + TX_CREDITS_ERR_CPLD :bit1; + TX_CREDITS_ERR_CPLH :bit1; + RESERVED0 :bit10; + TX_CREDITS_CUR_STATUS_PD :bit1; + TX_CREDITS_CUR_STATUS_PH :bit1; + TX_CREDITS_CUR_STATUS_NPD :bit1; + TX_CREDITS_CUR_STATUS_NPH :bit1; + TX_CREDITS_CUR_STATUS_CPLD:bit1; + TX_CREDITS_CUR_STATUS_CPLH:bit1; + RESERVED1 :bit10; + end; + + TPCIE_UNCORR_ERR_STATUS=bitpacked record + RESERVED0 :bit4; + DLP_ERR_STATUS :bit1; + SURPDN_ERR_STATUS :bit1; + RESERVED1 :bit6; + PSN_ERR_STATUS :bit1; + FC_ERR_STATUS :bit1; + CPL_TIMEOUT_STATUS :bit1; + CPL_ABORT_ERR_STATUS :bit1; + UNEXP_CPL_STATUS :bit1; + RCV_OVFL_STATUS :bit1; + MAL_TLP_STATUS :bit1; + ECRC_ERR_STATUS :bit1; + UNSUPP_REQ_ERR_STATUS :bit1; + ACS_VIOLATION_STATUS :bit1; + UNCORR_INT_ERR_STATUS :bit1; + MC_BLOCKED_TLP_STATUS :bit1; + ATOMICOP_EGRESS_BLOCKED_STATUS:bit1; + TLP_PREFIX_BLOCKED_ERR_STATUS :bit1; + RESERVED2 :bit6; + end; + + TPCIE_VC0_RESOURCE_CNTL=bitpacked record + TC_VC_MAP_TC0 :bit1; + TC_VC_MAP_TC1_7 :bit7; + RESERVED0 :bit8; + LOAD_PORT_ARB_TABLE:bit1; + PORT_ARB_SELECT :bit3; + RESERVED1 :bit4; + VC_ID :bit3; + RESERVED2 :bit4; + VC_ENABLE :bit1; + end; + + TPCIE_VC1_RESOURCE_CNTL=bitpacked record + TC_VC_MAP_TC0 :bit1; + TC_VC_MAP_TC1_7 :bit7; + RESERVED0 :bit8; + LOAD_PORT_ARB_TABLE:bit1; + PORT_ARB_SELECT :bit3; + RESERVED1 :bit4; + VC_ID :bit3; + RESERVED2 :bit4; + VC_ENABLE :bit1; + end; + + TPLL_UNLOCK_DETECT_CNTL=bitpacked record + PLL_UNLOCK_DETECT_ENABLE :bit1; + PLL_UNLOCK_DET_RES100_SELECT :bit1; + PLL_UNLOCK_STICKY_STATUS :bit1; + RESERVED0 :bit1; + PLL_UNLOCK_DET_COUNT :bit3; + PLL_UNLOCKED_STICKY_RST_TEST :bit1; + PLL_UNLOCKED_STICKY_TEST_READBACK:bit1; + RESERVED1 :bit23; + end; + + TPRESCALE_VALUES_GRPH_B=bitpacked record + GRPH_PRESCALE_BIAS_B :bit16; + GRPH_PRESCALE_SCALE_B:bit16; + end; + + TPRESCALE_VALUES_GRPH_G=bitpacked record + GRPH_PRESCALE_BIAS_G :bit16; + GRPH_PRESCALE_SCALE_G:bit16; + end; + + TPRESCALE_VALUES_GRPH_R=bitpacked record + GRPH_PRESCALE_BIAS_R :bit16; + GRPH_PRESCALE_SCALE_R:bit16; + end; + + TPRESCALE_VALUES_OVL_CB=bitpacked record + OVL_PRESCALE_BIAS_CB :bit16; + OVL_PRESCALE_SCALE_CB:bit16; + end; + + TPRESCALE_VALUES_OVL_CR=bitpacked record + OVL_PRESCALE_BIAS_CR :bit16; + OVL_PRESCALE_SCALE_CR:bit16; + end; + + TPWR_AVFS10_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS11_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS12_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS13_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS14_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS15_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS16_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS17_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS18_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS19_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS20_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS21_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS22_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS23_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS24_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS25_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS26_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_AVFS27_CNTL_STATUS=bitpacked record + MmDatOut :bit8; + PsmTdo :bit1; + AlarmFlag:bit1; + RESERVED0:bit22; + end; + + TPWR_DISP_TIMER_CONTROL=bitpacked record + DISP_TIMER_INT_COUNT :bit25; + DISP_TIMER_INT_ENABLE :bit1; + DISP_TIMER_INT_DISABLE:bit1; + DISP_TIMER_INT_MASK :bit1; + DISP_TIMER_INT_STAT_AK:bit1; + DISP_TIMER_INT_TYPE :bit1; + DISP_TIMER_INT_MODE :bit1; + RESERVED0 :bit1; + end; + + TREG_ADAPT_pif0_CONTROL=bitpacked record + ACCESS_MODE_pif0:bit1; + RESERVED0 :bit31; + end; + + TRLC_CGTT_MGCG_OVERRIDE=bit32; + + TRLC_GPU_IOV_UCODE_ADDR=bitpacked record + UCODE_ADDR:bit12; + RESERVED :bit20; + end; + + TRLC_GPU_IOV_UCODE_DATA=bit32; + + TRLC_HYP_GPM_UCODE_ADDR=bitpacked record + UCODE_ADDR:bit12; + RESERVED :bit20; + end; + + TRLC_HYP_GPM_UCODE_DATA=bit32; + + TRLC_JUMP_TABLE_RESTORE=bit32; + + TRLC_SPM_SE_MUXSEL_ADDR=bit32; + + TRLC_SPM_SE_MUXSEL_DATA=bit32; + + TSCLK_CGTT_BLK_CTRL_REG=bitpacked record + SCLK_TURN_ON_DELAY :bit4; + SCLK_TURN_OFF_DELAY:bit8; + CGTT_SCLK_OVERRIDE :bit1; + RESERVED0 :bit19; + end; + + TSCLV_COEF_RAM_TAP_DATA=bitpacked record + SCL_C_RAM_EVEN_TAP_COEF :bit14; + RESERVED0 :bit1; + SCL_C_RAM_EVEN_TAP_COEF_EN:bit1; + SCL_C_RAM_ODD_TAP_COEF :bit14; + RESERVED1 :bit1; + SCL_C_RAM_ODD_TAP_COEF_EN :bit1; + end; + + TSDMA0_GFX_CONTEXT_CNTL=bitpacked record + RESERVED0 :bit16; + RESUME_CTX :bit1; + RESERVED1 :bit7; + SESSION_SEL:bit4; + RESERVED2 :bit4; + end; + + TSDMA0_GFX_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA0_GFX_MIDCMD_DATA0=bit32; + + TSDMA0_GFX_MIDCMD_DATA1=bit32; + + TSDMA0_GFX_MIDCMD_DATA2=bit32; + + TSDMA0_GFX_MIDCMD_DATA3=bit32; + + TSDMA0_GFX_MIDCMD_DATA4=bit32; + + TSDMA0_GFX_MIDCMD_DATA5=bit32; + + TSDMA0_GFX_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA0_RLC0_CSA_ADDR_HI=bit32; + + TSDMA0_RLC0_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_RLC0_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSDMA0_RLC1_CSA_ADDR_HI=bit32; + + TSDMA0_RLC1_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_RLC1_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSDMA1_GFX_CONTEXT_CNTL=bitpacked record + RESERVED0 :bit16; + RESUME_CTX :bit1; + RESERVED1 :bit7; + SESSION_SEL:bit4; + RESERVED2 :bit4; + end; + + TSDMA1_GFX_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA1_GFX_MIDCMD_DATA0=bit32; + + TSDMA1_GFX_MIDCMD_DATA1=bit32; + + TSDMA1_GFX_MIDCMD_DATA2=bit32; + + TSDMA1_GFX_MIDCMD_DATA3=bit32; + + TSDMA1_GFX_MIDCMD_DATA4=bit32; + + TSDMA1_GFX_MIDCMD_DATA5=bit32; + + TSDMA1_GFX_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA1_RLC0_CSA_ADDR_HI=bit32; + + TSDMA1_RLC0_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC0_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSDMA1_RLC1_CSA_ADDR_HI=bit32; + + TSDMA1_RLC1_CSA_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC1_MIDCMD_CNTL=bitpacked record + DATA_VALID :bit1; + COPY_MODE :bit1; + RESERVED0 :bit2; + SPLIT_STATE :bit4; + ALLOW_PREEMPT:bit1; + RESERVED1 :bit23; + end; + + TSOFT_REGISTERS_TABLE_1=bit32; + + TSOFT_REGISTERS_TABLE_2=bit32; + + TSOFT_REGISTERS_TABLE_3=bit32; + + TSOFT_REGISTERS_TABLE_4=bit32; + + TSOFT_REGISTERS_TABLE_5=bit32; + + TSOFT_REGISTERS_TABLE_6=bit32; + + TSOFT_REGISTERS_TABLE_7=bit32; + + TSOFT_REGISTERS_TABLE_8=bit32; + + TSOFT_REGISTERS_TABLE_9=bit32; + + TSQC_ATC_EDC_GATCL1_CNT=bitpacked record + ICACHE_DATA_SEC:bit8; + RESERVED0 :bit8; + DCACHE_DATA_SEC:bit8; + RESERVED1 :bit8; + end; + + TSQ_INTERRUPT_AUTO_MASK=bitpacked record + MASK :bit24; + RESERVED0:bit8; + end; + + TSQ_INTERRUPT_WORD_AUTO=bitpacked record + THREAD_TRACE :bit1; + WLT :bit1; + THREAD_TRACE_BUF_FULL:bit1; + REG_TIMESTAMP :bit1; + CMD_TIMESTAMP :bit1; + HOST_CMD_OVERFLOW :bit1; + HOST_REG_OVERFLOW :bit1; + IMMED_OVERFLOW :bit1; + RESERVED0 :bit16; + SE_ID :bit2; + ENCODING :bit2; + RESERVED1 :bit4; + end; + + TSQ_INTERRUPT_WORD_WAVE=bitpacked record + DATA :bit8; + SH_ID :bit1; + PRIV :bit1; + VM_ID :bit4; + WAVE_ID :bit4; + SIMD_ID :bit2; + CU_ID :bit4; + SE_ID :bit2; + ENCODING :bit2; + RESERVED0:bit4; + end; + TSQ_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit9; RESERVED0 :bit3; @@ -10552,6 +49109,46 @@ type FULL :bit1; end; + TSRBM_SDMA_DOMAIN_ADDR0=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SDMA_DOMAIN_ADDR1=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SDMA_DOMAIN_ADDR2=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSRBM_SDMA_DOMAIN_ADDR3=bitpacked record + ADDR_LO:bit16; + ADDR_HI:bit16; + end; + + TSTREAM_SYNCHRONIZATION=bitpacked record + STREAM_0_SYNCHRONIZATION :bit1; + STREAM_1_SYNCHRONIZATION :bit1; + STREAM_2_SYNCHRONIZATION :bit1; + STREAM_3_SYNCHRONIZATION :bit1; + STREAM_4_SYNCHRONIZATION :bit1; + STREAM_5_SYNCHRONIZATION :bit1; + STREAM_6_SYNCHRONIZATION :bit1; + STREAM_7_SYNCHRONIZATION :bit1; + STREAM_8_SYNCHRONIZATION :bit1; + STREAM_9_SYNCHRONIZATION :bit1; + STREAM_10_SYNCHRONIZATION:bit1; + STREAM_11_SYNCHRONIZATION:bit1; + STREAM_12_SYNCHRONIZATION:bit1; + STREAM_13_SYNCHRONIZATION:bit1; + STREAM_14_SYNCHRONIZATION:bit1; + STREAM_15_SYNCHRONIZATION:bit1; + RESERVED0 :bit16; + end; + TSX_PERFCOUNTER0_SELECT=bitpacked record PERFCOUNTER_SELECT :bit10; PERFCOUNTER_SELECT1:bit10; @@ -10605,6 +49202,117 @@ type RESERVED0:bit24; end; + TTC_CFG_L1_LOAD_POLICY0=bitpacked record + POLICY_0 :bit2; + POLICY_1 :bit2; + POLICY_2 :bit2; + POLICY_3 :bit2; + POLICY_4 :bit2; + POLICY_5 :bit2; + POLICY_6 :bit2; + POLICY_7 :bit2; + POLICY_8 :bit2; + POLICY_9 :bit2; + POLICY_10:bit2; + POLICY_11:bit2; + POLICY_12:bit2; + POLICY_13:bit2; + POLICY_14:bit2; + POLICY_15:bit2; + end; + + TTC_CFG_L1_LOAD_POLICY1=bitpacked record + POLICY_16:bit2; + POLICY_17:bit2; + POLICY_18:bit2; + POLICY_19:bit2; + POLICY_20:bit2; + POLICY_21:bit2; + POLICY_22:bit2; + POLICY_23:bit2; + POLICY_24:bit2; + POLICY_25:bit2; + POLICY_26:bit2; + POLICY_27:bit2; + POLICY_28:bit2; + POLICY_29:bit2; + POLICY_30:bit2; + POLICY_31:bit2; + end; + + TTC_CFG_L1_STORE_POLICY=bitpacked record + POLICY_0 :bit1; + POLICY_1 :bit1; + POLICY_2 :bit1; + POLICY_3 :bit1; + POLICY_4 :bit1; + POLICY_5 :bit1; + POLICY_6 :bit1; + POLICY_7 :bit1; + POLICY_8 :bit1; + POLICY_9 :bit1; + POLICY_10:bit1; + POLICY_11:bit1; + POLICY_12:bit1; + POLICY_13:bit1; + POLICY_14:bit1; + POLICY_15:bit1; + POLICY_16:bit1; + POLICY_17:bit1; + POLICY_18:bit1; + POLICY_19:bit1; + POLICY_20:bit1; + POLICY_21:bit1; + POLICY_22:bit1; + POLICY_23:bit1; + POLICY_24:bit1; + POLICY_25:bit1; + POLICY_26:bit1; + POLICY_27:bit1; + POLICY_28:bit1; + POLICY_29:bit1; + POLICY_30:bit1; + POLICY_31:bit1; + end; + + TTC_CFG_L2_LOAD_POLICY0=bitpacked record + POLICY_0 :bit2; + POLICY_1 :bit2; + POLICY_2 :bit2; + POLICY_3 :bit2; + POLICY_4 :bit2; + POLICY_5 :bit2; + POLICY_6 :bit2; + POLICY_7 :bit2; + POLICY_8 :bit2; + POLICY_9 :bit2; + POLICY_10:bit2; + POLICY_11:bit2; + POLICY_12:bit2; + POLICY_13:bit2; + POLICY_14:bit2; + POLICY_15:bit2; + end; + + TTC_CFG_L2_LOAD_POLICY1=bitpacked record + POLICY_16:bit2; + POLICY_17:bit2; + POLICY_18:bit2; + POLICY_19:bit2; + POLICY_20:bit2; + POLICY_21:bit2; + POLICY_22:bit2; + POLICY_23:bit2; + POLICY_24:bit2; + POLICY_25:bit2; + POLICY_26:bit2; + POLICY_27:bit2; + POLICY_28:bit2; + POLICY_29:bit2; + POLICY_30:bit2; + POLICY_31:bit2; + end; + TTD_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit8; RESERVED0 :bit2; @@ -10625,6 +49333,106 @@ type PERF_MODE :bit4; end; + TTMDS_CONTROL0_FEEDBACK=bitpacked record + TMDS_CONTROL0_FEEDBACK_SELECT:bit2; + RESERVED0 :bit6; + TMDS_CONTROL0_FEEDBACK_DELAY :bit2; + RESERVED1 :bit22; + end; + + TUNIPHY_REG_TEST_OUTPUT=bitpacked record + UNIPHY_TEST_CNTL :bit5; + UNIPHY_PLL_TEST_VCTL :bit4; + UNIPHY_PLL_TEST_SSAMP_EN :bit1; + UNIPHY_PLL_TEST_UNLOCK_CLR :bit1; + RESERVED0 :bit4; + UNIPHY_DIG_BIST_RESET :bit1; + UNIPHY_DIG_BIST_SEL :bit1; + UNIPHY_TEST_VCTL_EN :bit1; + RESERVED1 :bit2; + UNIPHY_DIG_BIST_ERROR :bit5; + UNIPHY_PLL_TEST_VCTL_ADC :bit3; + UNIPHY_PLL_TEST_FREQ_LOCK :bit1; + UNIPHY_PLL_INTRESET :bit1; + UNIPHY_PLL_TEST_UNLOCK_STICKY:bit1; + UNIPHY_PLL_TEST_LOCK :bit1; + end; + + TUVD_LMI_VMID_INTERNAL2=bitpacked record + MIF_GPGPU_VMID :bit4; + MIF_CURR_VMID :bit4; + MIF_REF_VMID :bit4; + MIF_DBW_VMID :bit4; + MIF_CM_COLOC_VMID:bit4; + MIF_BSD_VMID :bit4; + MIF_BSP_VMID :bit4; + VDMA_VMID :bit4; + end; + + TUVD_LMI_VMID_INTERNAL3=bitpacked record + MIF_GEN_RD0_VMID:bit4; + MIF_GEN_RD1_VMID:bit4; + MIF_GEN_WR0_VMID:bit4; + MIF_GEN_WR1_VMID:bit4; + MIF_SCLR_VMID :bit4; + RESERVED0 :bit12; + end; + + TUVD_VCPU_CACHE_OFFSET0=bitpacked record + CACHE_OFFSET0:bit25; + RESERVED0 :bit7; + end; + + TUVD_VCPU_CACHE_OFFSET1=bitpacked record + CACHE_OFFSET1:bit25; + RESERVED0 :bit7; + end; + + TUVD_VCPU_CACHE_OFFSET2=bitpacked record + CACHE_OFFSET2:bit25; + RESERVED0 :bit7; + end; + + TVCE_UENC_DMA_DCLK_CTRL=bitpacked record + WRDMCLK_FORCEON:bit1; + RDDMCLK_FORCEON:bit1; + REGCLK_FORCEON :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit18; + end; + + TVCE_VCPU_CACHE_OFFSET0=bitpacked record + OFFSET :bit28; + RESERVED0:bit4; + end; + + TVCE_VCPU_CACHE_OFFSET1=bitpacked record + OFFSET :bit28; + RESERVED0:bit4; + end; + + TVCE_VCPU_CACHE_OFFSET2=bitpacked record + OFFSET :bit28; + RESERVED0:bit4; + end; + + TVGA_MEM_READ_PAGE_ADDR=bitpacked record + VGA_MEM_READ_PAGE0_ADDR:bit10; + RESERVED0 :bit6; + VGA_MEM_READ_PAGE1_ADDR:bit10; + RESERVED1 :bit6; + end; + TVGT_CACHE_INVALIDATION=bitpacked record CACHE_INVALIDATION :bit2; RESERVED0 :bit2; @@ -10701,6 +49509,26 @@ type RESERVED0 :bit22; end; + TVM_INVALIDATE_RESPONSE=bitpacked record + DOMAIN_INVALIDATED_0 :bit1; + DOMAIN_INVALIDATED_1 :bit1; + DOMAIN_INVALIDATED_2 :bit1; + DOMAIN_INVALIDATED_3 :bit1; + DOMAIN_INVALIDATED_4 :bit1; + DOMAIN_INVALIDATED_5 :bit1; + DOMAIN_INVALIDATED_6 :bit1; + DOMAIN_INVALIDATED_7 :bit1; + DOMAIN_INVALIDATED_8 :bit1; + DOMAIN_INVALIDATED_9 :bit1; + DOMAIN_INVALIDATED_10:bit1; + DOMAIN_INVALIDATED_11:bit1; + DOMAIN_INVALIDATED_12:bit1; + DOMAIN_INVALIDATED_13:bit1; + DOMAIN_INVALIDATED_14:bit1; + DOMAIN_INVALIDATED_15:bit1; + RESERVED0 :bit16; + end; + TWD_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit8; RESERVED0:bit20; @@ -10725,6 +49553,181 @@ type PERF_MODE:bit4; end; + TXDMA_CLOCK_GATING_CNTL=bitpacked record + XDMA_SCLK_TURN_ON_DELAY :bit4; + XDMA_SCLK_TURN_OFF_DELAY :bit8; + RESERVED0 :bit3; + XDMA_SCLK_GATE_DIS :bit1; + XDMA_SCLK_REG_GATE_DIS :bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0:bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1:bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2:bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3:bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4:bit1; + XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5:bit1; + XDMA_SCLK_G_SDYN_GATE_DIS :bit1; + XDMA_SCLK_G_MSTAT_GATE_DIS :bit1; + XDMA_SCLK_G_SSTAT_GATE_DIS :bit1; + RESERVED1 :bit6; + end; + + TXDMA_MSTR_READ_COMMAND=bitpacked record + XDMA_MSTR_REQUEST_SIZE :bit14; + RESERVED0 :bit2; + XDMA_MSTR_REQUEST_PREFETCH:bit14; + RESERVED1 :bit2; + end; + + TAFMT_AUDIO_DBG_DTO_CNTL=bitpacked record + AFMT_AUDIO_DTO_FS_DIV_SEL:bit3; + RESERVED0 :bit5; + AFMT_AUDIO_DTO_DBG_BASE :bit1; + RESERVED1 :bit3; + AFMT_AUDIO_DTO_DBG_MULTI :bit3; + RESERVED2 :bit1; + AFMT_AUDIO_DTO_DBG_DIV :bit3; + RESERVED3 :bit13; + end; + + TAFMT_INFOFRAME_CONTROL0=bitpacked record + RESERVED0 :bit6; + AFMT_AUDIO_INFO_SOURCE:bit1; + AFMT_AUDIO_INFO_UPDATE:bit1; + RESERVED1 :bit2; + AFMT_MPEG_INFO_UPDATE :bit1; + RESERVED2 :bit21; + end; + + TAFMT_VBI_PACKET_CONTROL=bitpacked record + RESERVED0 :bit2; + AFMT_GENERIC0_UPDATE:bit1; + AFMT_GENERIC2_UPDATE:bit1; + RESERVED1 :bit9; + RESERVED2 :bit1; + RESERVED3 :bit16; + AFMT_GENERIC_INDEX :bit2; + end; + + TATC_VMID0_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID1_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID2_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID3_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID4_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID5_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID6_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID7_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID8_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID9_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TAUX_DPHY_TX_REF_CONTROL=bitpacked record + AUX_TX_REF_SEL:bit1; + RESERVED0 :bit3; + AUX_TX_RATE :bit2; + RESERVED1 :bit10; + AUX_TX_REF_DIV:bit9; + RESERVED2 :bit7; + end; + + TAZALIA_CONTROLLER_DEBUG=bit32; + + TAZALIA_CORB_DMA_CONTROL=bitpacked record + CORB_DMA_NON_SNOOP :bit1; + RESERVED0 :bit3; + CORB_DMA_ISOCHRONOUS:bit1; + RESERVED1 :bit27; + end; + + TAZALIA_DATA_DMA_CONTROL=bitpacked record + DATA_DMA_NON_SNOOP :bit2; + INPUT_DATA_DMA_NON_SNOOP :bit2; + DATA_DMA_ISOCHRONOUS :bit2; + INPUT_DATA_DMA_ISOCHRONOUS :bit2; + RESERVED0 :bit6; + RESERVED1 :bit1; + RESERVED2 :bit1; + AZALIA_IOC_GENERATION_METHOD:bit1; + AZALIA_UNDERFLOW_CONTROL :bit1; + RESERVED3 :bit14; + end; + + TBIF_IOV_FUNC_IDENTIFIER=bitpacked record + FUNC_IDENTIFIER:bit1; + RESERVED0 :bit30; + IOV_ENABLE :bit1; + end; + + TBIF_PERFCOUNTER0_RESULT=bit32; + + TBIF_PERFCOUNTER1_RESULT=bit32; + + TCB_PERFCOUNTER0_SELECT0=bitpacked record + RESERVED0:bit8; + RESERVED1:bit1; + RESERVED2:bit3; + RESERVED3:bit1; + RESERVED4:bit5; + RESERVED5:bit14; + end; + TCB_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2 :bit9; RESERVED0 :bit1; @@ -10734,6 +49737,86 @@ type PERF_MODE2:bit4; end; + TCB_PERFCOUNTER1_SELECT0=bitpacked record + RESERVED0:bit8; + RESERVED1:bit1; + RESERVED2:bit3; + RESERVED3:bit1; + RESERVED4:bit5; + RESERVED5:bit14; + end; + + TCB_PERFCOUNTER1_SELECT1=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit4; + RESERVED4:bit1; + RESERVED5:bit3; + RESERVED6:bit1; + RESERVED7:bit2; + RESERVED8:bit18; + end; + + TCB_PERFCOUNTER2_SELECT0=bitpacked record + RESERVED0:bit8; + RESERVED1:bit1; + RESERVED2:bit3; + RESERVED3:bit1; + RESERVED4:bit5; + RESERVED5:bit14; + end; + + TCB_PERFCOUNTER2_SELECT1=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit4; + RESERVED4:bit1; + RESERVED5:bit3; + RESERVED6:bit1; + RESERVED7:bit2; + RESERVED8:bit18; + end; + + TCB_PERFCOUNTER3_SELECT0=bitpacked record + RESERVED0:bit8; + RESERVED1:bit1; + RESERVED2:bit3; + RESERVED3:bit1; + RESERVED4:bit5; + RESERVED5:bit14; + end; + + TCB_PERFCOUNTER3_SELECT1=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit1; + RESERVED3:bit4; + RESERVED4:bit1; + RESERVED5:bit3; + RESERVED6:bit1; + RESERVED7:bit2; + RESERVED8:bit18; + end; + + TCG_SPLL_SPREAD_SPECTRUM=bitpacked record + SSEN :bit2; + RESERVED0:bit2; + CLKS :bit12; + RESERVED1:bit12; + RESERVED2:bit4; + end; + + TCHUB_ATC_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TCHUB_ATC_PERFCOUNTER_LO=bit32; + + TCOL_MAN_TEST_DEBUG_DATA=bit32; + TCOMPUTE_RESOURCE_LIMITS=bitpacked record WAVES_PER_SH :bit10; RESERVED0 :bit2; @@ -10745,6 +49828,13 @@ type RESERVED1 :bit5; end; + TCORB_LOWER_BASE_ADDRESS=bitpacked record + CORB_LOWER_BASE_UNIMPLEMENTED_BITS:bit7; + CORB_LOWER_BASE_ADDRESS :bit25; + end; + + TCORB_UPPER_BASE_ADDRESS=bit32; + TCPC_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit6; RESERVED0:bit4; @@ -11000,6 +50090,16 @@ type RESERVED0:bit20; end; + TCP_RB_WPTR_POLL_ADDR_HI=bitpacked record + RB_WPTR_POLL_ADDR_HI:bit8; + RESERVED0 :bit24; + end; + + TCP_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0 :bit2; + RB_WPTR_POLL_ADDR_LO:bit30; + end; + TCP_SC_PSINVOC_COUNT0_HI=bit32; TCP_SC_PSINVOC_COUNT0_LO=bit32; @@ -11030,6 +50130,96 @@ type TCP_WAIT_REG_MEM_TIMEOUT=bit32; + TCRTC_DCFE_CLOCK_CONTROL=bitpacked record + RESERVED0 :bit4; + CRTC_DISPCLK_R_DCFE_GATE_DISABLE:bit1; + RESERVED1 :bit3; + CRTC_DISPCLK_G_DCP_GATE_DISABLE :bit1; + RESERVED2 :bit3; + CRTC_DISPCLK_G_SCL_GATE_DISABLE :bit1; + RESERVED3 :bit11; + CRTC_DCFE_TEST_CLK_SEL :bit5; + RESERVED4 :bit2; + CRTC_DCFE_CLOCK_ENABLE :bit1; + end; + + TCRTC_OVERSCAN_COLOR_EXT=bitpacked record + CRTC_OVERSCAN_COLOR_BLUE_EXT :bit2; + RESERVED0 :bit6; + CRTC_OVERSCAN_COLOR_GREEN_EXT:bit2; + RESERVED1 :bit6; + CRTC_OVERSCAN_COLOR_RED_EXT :bit2; + RESERVED2 :bit14; + end; + + TCRTC_START_LINE_CONTROL=bitpacked record + CRTC_PROGRESSIVE_START_LINE_EARLY:bit1; + RESERVED0 :bit7; + CRTC_INTERLACE_START_LINE_EARLY :bit1; + RESERVED1 :bit3; + CRTC_ADVANCED_START_LINE_POSITION:bit8; + CRTC_LEGACY_REQUESTOR_EN :bit1; + RESERVED2 :bit7; + CRTC_PREFETCH_EN :bit1; + RESERVED3 :bit3; + end; + + TCRTC_STATUS_FRAME_COUNT=bitpacked record + CRTC_FRAME_COUNT:bit24; + RESERVED0 :bit8; + end; + + TCRTC_TEST_PATTERN_COLOR=bitpacked record + CRTC_TEST_PATTERN_DATA:bit16; + CRTC_TEST_PATTERN_MASK:bit6; + RESERVED0 :bit10; + end; + + TCRTC_V_TOTAL_INT_STATUS=bitpacked record + CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED :bit1; + RESERVED0 :bit3; + CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT:bit1; + RESERVED1 :bit3; + CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK:bit1; + RESERVED2 :bit3; + CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK:bit1; + RESERVED3 :bit19; + end; + + TCSPRIV_THREAD_TRACE_TG0=bit32; + + TCSPRIV_THREAD_TRACE_TG1=bit32; + + TCSPRIV_THREAD_TRACE_TG2=bit32; + + TCSPRIV_THREAD_TRACE_TG3=bitpacked record + WAVE_ID_BASE :bit12; + THREADS_IN_GROUP:bit12; + PARTIAL_X_FLAG :bit1; + PARTIAL_Y_FLAG :bit1; + PARTIAL_Z_FLAG :bit1; + LAST_TG :bit1; + FIRST_TG :bit1; + RESERVED0 :bit3; + end; + + TCUR_REQUEST_FILTER_CNTL=bitpacked record + CUR_REQUEST_FILTER_DIS:bit1; + RESERVED0 :bit31; + end; + + TDAC_AUTODETECT_CONTROL2=bitpacked record + DAC_AUTODETECT_POWERUP_COUNTER:bit8; + DAC_AUTODETECT_TESTMODE :bit1; + RESERVED0 :bit23; + end; + + TDAC_AUTODETECT_CONTROL3=bitpacked record + DAC_AUTODET_COMPARATOR_IN_DELAY :bit8; + DAC_AUTODET_COMPARATOR_OUT_DELAY:bit8; + RESERVED0 :bit16; + end; + TDB_OCCLUSION_COUNT0_LOW=bit32; TDB_OCCLUSION_COUNT1_LOW=bit32; @@ -11054,6 +50244,252 @@ type PERF_MODE2:bit4; end; + TDCCG_DS_HW_CAL_INTERVAL=bit32; + + TDCIO_GSL_GENLK_PAD_CNTL=bitpacked record + DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL :bit2; + RESERVED0 :bit2; + DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL :bit2; + RESERVED1 :bit2; + DCIO_GENLK_CLK_GSL_MASK :bit2; + RESERVED2 :bit6; + DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL:bit2; + RESERVED3 :bit2; + DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL :bit2; + RESERVED4 :bit2; + DCIO_GENLK_VSYNC_GSL_MASK :bit2; + RESERVED5 :bit6; + end; + + TDCO_DCFE_EXT_VSYNC_CNTL=bitpacked record + DCO_DCFE0_EXT_VSYNC_MUX :bit3; + RESERVED0 :bit1; + DCO_DCFE1_EXT_VSYNC_MUX :bit3; + RESERVED1 :bit1; + DCO_DCFE2_EXT_VSYNC_MUX :bit3; + RESERVED2 :bit1; + DCO_DCFE3_EXT_VSYNC_MUX :bit3; + RESERVED3 :bit1; + DCO_DCFE4_EXT_VSYNC_MUX :bit3; + RESERVED4 :bit1; + DCO_DCFE5_EXT_VSYNC_MUX :bit3; + RESERVED5 :bit1; + DCO_SWAPLOCKB_EXT_VSYNC_MASK:bit3; + RESERVED6 :bit1; + DCO_GENERICB_EXT_VSYNC_MASK :bit3; + DCO_CRTC_MANUAL_FLOW_CONTROL:bit1; + end; + + TDCP_SPATIAL_DITHER_CNTL=bitpacked record + DCP_SPATIAL_DITHER_EN :bit1; + RESERVED0 :bit3; + DCP_SPATIAL_DITHER_MODE :bit2; + DCP_SPATIAL_DITHER_DEPTH :bit2; + DCP_FRAME_RANDOM_ENABLE :bit1; + DCP_RGB_RANDOM_ENABLE :bit1; + DCP_HIGHPASS_RANDOM_ENABLE:bit1; + RESERVED1 :bit21; + end; + + TDC_ABM1_IPCSC_COEFF_SEL=bitpacked record + ABM1_IPCSC_COEFF_SEL_B:bit4; + RESERVED0 :bit4; + ABM1_IPCSC_COEFF_SEL_G:bit4; + RESERVED1 :bit4; + ABM1_IPCSC_COEFF_SEL_R:bit4; + RESERVED2 :bit11; + ABM1_HGLS_REG_LOCK :bit1; + end; + + TDC_ABM1_LS_MIN_MAX_LUMA=bitpacked record + ABM1_LS_MIN_LUMA:bit10; + RESERVED0 :bit6; + ABM1_LS_MAX_LUMA:bit10; + RESERVED1 :bit6; + end; + + TDC_ABM1_LS_OVR_SCAN_BIN=bitpacked record + ABM1_LS_OVR_SCAN_BIN:bit24; + RESERVED0 :bit8; + end; + + TDC_GPIO_I2CPAD_STRENGTH=bitpacked record + I2C_STRENGTH_SN:bit4; + I2C_STRENGTH_SP:bit4; + RESERVED0 :bit24; + end; + + TDC_HPD_TOGGLE_FILT_CNTL=bitpacked record + DC_HPD_CONNECT_INT_DELAY :bit8; + RESERVED0 :bit12; + DC_HPD_DISCONNECT_INT_DELAY:bit8; + RESERVED1 :bit4; + end; + + TDC_I2C_DDCVGA_HW_STATUS=bitpacked record + DC_I2C_DDCVGA_HW_STATUS :bit2; + RESERVED0 :bit1; + DC_I2C_DDCVGA_HW_DONE :bit1; + RESERVED1 :bit12; + DC_I2C_DDCVGA_HW_REQ :bit1; + DC_I2C_DDCVGA_HW_URG :bit1; + RESERVED2 :bit2; + DC_I2C_DDCVGA_EDID_DETECT_STATUS :bit1; + RESERVED3 :bit3; + DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES:bit4; + DC_I2C_DDCVGA_EDID_DETECT_STATE :bit3; + RESERVED4 :bit1; + end; + + TDC_I2C_EDID_DETECT_CTRL=bitpacked record + DC_I2C_EDID_DETECT_WAIT_TIME :bit16; + RESERVED0 :bit4; + DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID:bit4; + RESERVED1 :bit4; + DC_I2C_EDID_DETECT_SEND_RESET :bit1; + RESERVED2 :bit3; + end; + + TDC_LUT_BLACK_OFFSET_RED=bitpacked record + DC_LUT_BLACK_OFFSET_RED:bit16; + RESERVED0 :bit16; + end; + + TDC_LUT_WHITE_OFFSET_RED=bitpacked record + DC_LUT_WHITE_OFFSET_RED:bit16; + RESERVED0 :bit16; + end; + + TDENORM_CLAMP_RANGE_B_CB=bitpacked record + RANGE_CLAMP_MAX_B_CB:bit12; + RANGE_CLAMP_MIN_B_CB:bit12; + RESERVED0 :bit8; + end; + + TDENORM_CLAMP_RANGE_R_CR=bitpacked record + RANGE_CLAMP_MAX_R_CR:bit12; + RANGE_CLAMP_MIN_R_CR:bit12; + RESERVED0 :bit8; + end; + + TDIG_DISPCLK_SWITCH_CNTL=bitpacked record + DIG_DISPCLK_SWITCH_POINT:bit1; + RESERVED0 :bit31; + end; + + TDIG_FE_TEST_DEBUG_INDEX=bitpacked record + DIG_FE_TEST_DEBUG_INDEX :bit8; + DIG_FE_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TDIG_RANDOM_PATTERN_SEED=bitpacked record + DIG_RANDOM_PATTERN_SEED :bit24; + DIG_RAN_PAT_DURING_DE_ONLY:bit1; + RESERVED0 :bit7; + end; + + TDMCU_SMU_INTERRUPT_CNTL=bitpacked record + DMCU_SMU_STATIC_SCREEN_INT :bit1; + RESERVED0 :bit15; + DMCU_SMU_STATIC_SCREEN_STATUS:bit16; + end; + + TDMCU_UC_CLK_GATING_CNTL=bitpacked record + UC_IRAM_RD_DELAY :bit3; + RESERVED0 :bit5; + UC_ERAM_RD_DELAY :bit3; + RESERVED1 :bit5; + UC_RBBM_RD_CLK_GATING_EN:bit1; + RESERVED2 :bit15; + end; + + TDPDBG_CLK_FORCE_CONTROL=bitpacked record + RESERVED0 :bit4; + DPDBG_CLK_FORCE_EN :bit1; + RESERVED1 :bit3; + DPDBG_CLK_FORCE_SRC:bit3; + RESERVED2 :bit21; + end; + + TEXT_OVERSCAN_LEFT_RIGHT=bitpacked record + EXT_OVERSCAN_RIGHT:bit13; + RESERVED0 :bit3; + EXT_OVERSCAN_LEFT :bit13; + RESERVED1 :bit3; + end; + + TEXT_OVERSCAN_TOP_BOTTOM=bitpacked record + EXT_OVERSCAN_BOTTOM:bit13; + RESERVED0 :bit3; + EXT_OVERSCAN_TOP :bit13; + RESERVED1 :bit3; + end; + + TGARLIC_COHE_CP_RB0_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_CP_RB1_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_CP_RB2_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_VCE_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_FLUSH_ADDR_END_0=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_1=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_2=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_3=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_4=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_5=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_6=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + + TGARLIC_FLUSH_ADDR_END_7=bitpacked record + RESERVED0:bit2; + ADDR_END :bit30; + end; + TGDS_COMPUTE_MAX_WAVE_ID=bitpacked record MAX_WAVE_ID:bit12; RESERVED0 :bit20; @@ -11099,6 +50535,19 @@ type ADDRESS :bit16; end; + TGENERIC_I2C_TRANSACTION=bitpacked record + GENERIC_I2C_RW :bit1; + RESERVED0 :bit7; + GENERIC_I2C_STOP_ON_NACK:bit1; + GENERIC_I2C_ACK_ON_READ :bit1; + RESERVED1 :bit2; + GENERIC_I2C_START :bit1; + GENERIC_I2C_STOP :bit1; + RESERVED2 :bit2; + GENERIC_I2C_COUNT :bit4; + RESERVED3 :bit12; + end; + TGRBM_SE0_PERFCOUNTER_HI=bit32; TGRBM_SE0_PERFCOUNTER_LO=bit32; @@ -11115,6 +50564,88 @@ type TGRBM_SE3_PERFCOUNTER_LO=bit32; + THDMI_ACR_PACKET_CONTROL=bitpacked record + HDMI_ACR_SEND :bit1; + HDMI_ACR_CONT :bit1; + RESERVED0 :bit2; + HDMI_ACR_SELECT :bit2; + RESERVED1 :bit2; + HDMI_ACR_SOURCE :bit1; + RESERVED2 :bit3; + HDMI_ACR_AUTO_SEND :bit1; + RESERVED3 :bit3; + HDMI_ACR_N_MULTIPLE :bit3; + RESERVED4 :bit12; + HDMI_ACR_AUDIO_PRIORITY:bit1; + end; + + THDMI_INFOFRAME_CONTROL0=bitpacked record + HDMI_AVI_INFO_SEND :bit1; + HDMI_AVI_INFO_CONT :bit1; + RESERVED0 :bit2; + HDMI_AUDIO_INFO_SEND:bit1; + HDMI_AUDIO_INFO_CONT:bit1; + RESERVED1 :bit2; + HDMI_MPEG_INFO_SEND :bit1; + HDMI_MPEG_INFO_CONT :bit1; + RESERVED2 :bit22; + end; + + THDMI_INFOFRAME_CONTROL1=bitpacked record + HDMI_AVI_INFO_LINE :bit6; + RESERVED0 :bit2; + HDMI_AUDIO_INFO_LINE:bit6; + RESERVED1 :bit2; + HDMI_MPEG_INFO_LINE :bit6; + RESERVED2 :bit10; + end; + + THDMI_VBI_PACKET_CONTROL=bitpacked record + HDMI_NULL_SEND:bit1; + RESERVED0 :bit3; + HDMI_GC_SEND :bit1; + HDMI_GC_CONT :bit1; + RESERVED1 :bit2; + HDMI_ISRC_SEND:bit1; + HDMI_ISRC_CONT:bit1; + RESERVED2 :bit2; + RESERVED3 :bit1; + RESERVED4 :bit3; + HDMI_ISRC_LINE:bit6; + RESERVED5 :bit2; + RESERVED6 :bit6; + RESERVED7 :bit2; + end; + + THDP_NONSURFACE_PREFETCH=bitpacked record + NONSURF_PREFETCH_PRI :bit3; + NONSURF_PREFETCH_DIR :bit3; + NONSURF_PREFETCH_NUM :bit3; + NONSURF_PREFETCH_MAX_Z:bit11; + RESERVED0 :bit7; + NONSURF_PIPE_CONFIG :bit5; + end; + + THDP_XDP_BARS_ADDR_39_36=bitpacked record + BAR0_ADDR_39_36:bit4; + BAR1_ADDR_39_36:bit4; + BAR2_ADDR_39_36:bit4; + BAR3_ADDR_39_36:bit4; + BAR4_ADDR_39_36:bit4; + BAR5_ADDR_39_36:bit4; + BAR6_ADDR_39_36:bit4; + BAR7_ADDR_39_36:bit4; + end; + + THDP_XDP_DIRECT2HDP_LAST=bit32; + + THDP_XDP_FLUSH_ARMED_STS=bit32; + + THDP_XDP_FLUSH_CNTR0_STS=bitpacked record + FLUSH_CNTR0_STS:bit26; + RESERVED0 :bit6; + end; + TIA_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2 :bit10; PERF_SEL3 :bit10; @@ -11123,6 +50654,435 @@ type PERF_MODE2:bit4; end; + TLBV_BUFFER_LEVEL_STATUS=bitpacked record + REQ_FIFO_LEVEL :bit6; + RESERVED0 :bit4; + REQ_FIFO_FULL_CNTL :bit6; + DATA_BUFFER_LEVEL :bit12; + DATA_FIFO_FULL_CNTL:bit4; + end; + + TLBV_BUFFER_URGENCY_CTRL=bitpacked record + LB_BUFFER_URGENCY_MARK_ON :bit12; + RESERVED0 :bit4; + LB_BUFFER_URGENCY_MARK_OFF:bit12; + RESERVED1 :bit4; + end; + + TLBV_KEYER_COLOR_REP_G_Y=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_G_Y:bit12; + RESERVED1 :bit16; + end; + + TLB_KEYER_COLOR_REP_B_CB=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLB_KEYER_COLOR_REP_R_CR=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_R_CR:bit12; + RESERVED1 :bit16; + end; + + TMCIF_WB_TEST_DEBUG_DATA=bit32; + + TMC_ARB_GRUB_REALTIME_RD=bitpacked record + CB0 :bit1; + CBCMASK0 :bit1; + CBFMASK0 :bit1; + DB0 :bit1; + DBHTILE0 :bit1; + DBSTEN0 :bit1; + TC0 :bit1; + IA :bit1; + ACPG :bit1; + ACPO :bit1; + DMIF :bit1; + DMIF_EXT0:bit1; + DMIF_EXT1:bit1; + DMIF_TW :bit1; + MCIF :bit1; + RLC :bit1; + VMC :bit1; + SDMA1 :bit1; + SMU :bit1; + VCE :bit1; + RESERVED0:bit1; + XDMAM :bit1; + SDMA0 :bit1; + HDP :bit1; + UMC :bit1; + UVD :bit1; + UVD_EXT0 :bit1; + UVD_EXT1 :bit1; + SEM :bit1; + SAMMSP :bit1; + VP8 :bit1; + ISP :bit1; + end; + + TMC_ARB_GRUB_REALTIME_WR=bitpacked record + CB0 :bit1; + CBCMASK0 :bit1; + CBFMASK0 :bit1; + CBIMMED0 :bit1; + DB0 :bit1; + DBHTILE0 :bit1; + DBSTEN0 :bit1; + TC0 :bit1; + SH :bit1; + ACPG :bit1; + ACPO :bit1; + MCIF :bit1; + RLC :bit1; + SDMA1 :bit1; + SMU :bit1; + VCE :bit1; + RESERVED0:bit1; + SAMMSP :bit1; + XDMA :bit1; + XDMAM :bit1; + SDMA0 :bit1; + HDP :bit1; + UMC :bit1; + UVD :bit1; + UVD_EXT0 :bit1; + UVD_EXT1 :bit1; + XDP :bit1; + SEM :bit1; + IH :bit1; + VP8 :bit1; + ISP :bit1; + RESERVED1:bit1; + end; + + TMC_ARB_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_ARB_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_ARB_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_ARB_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_CITF_CREDITS_ARB_RD2=bitpacked record + READ_MED :bit8; + RESERVED0:bit24; + end; + + TMC_FUS_DRAM_CTL_HIGH_01=bitpacked record + DCTHIGHADDROFF0:bit12; + DCTHIGHADDROFF1:bit12; + RESERVED0 :bit8; + end; + + TMC_FUS_DRAM_CTL_HIGH_23=bitpacked record + DCTHIGHADDROFF2:bit12; + DCTHIGHADDROFF3:bit12; + RESERVED0 :bit8; + end; + + TMC_HUB_MISC_IDLE_STATUS=bitpacked record + OUTSTANDING_GFX_READ :bit1; + OUTSTANDING_GFX_WRITE :bit1; + OUTSTANDING_RLC_READ :bit1; + OUTSTANDING_RLC_WRITE :bit1; + OUTSTANDING_SDMA0_READ :bit1; + OUTSTANDING_SDMA0_WRITE :bit1; + OUTSTANDING_SDMA1_READ :bit1; + OUTSTANDING_SDMA1_WRITE :bit1; + OUTSTANDING_DISP_READ :bit1; + OUTSTANDING_DISP_WRITE :bit1; + OUTSTANDING_UVD_READ :bit1; + OUTSTANDING_UVD_WRITE :bit1; + OUTSTANDING_SMU_READ :bit1; + OUTSTANDING_SMU_WRITE :bit1; + OUTSTANDING_HDP_READ :bit1; + OUTSTANDING_HDP_WRITE :bit1; + OUTSTANDING_OTH_READ :bit1; + OUTSTANDING_OTH_WRITE :bit1; + OUTSTANDING_VMC_READ :bit1; + OUTSTANDING_VMC_WRITE :bit1; + OUTSTANDING_VCE_READ :bit1; + OUTSTANDING_VCE_WRITE :bit1; + OUTSTANDING_ACP_READ :bit1; + OUTSTANDING_ACP_WRITE :bit1; + OUTSTANDING_SAMMSP_READ :bit1; + OUTSTANDING_SAMMSP_WRITE:bit1; + OUTSTANDING_XDMA_READ :bit1; + OUTSTANDING_XDMA_WRITE :bit1; + OUTSTANDING_ISP_READ :bit1; + OUTSTANDING_ISP_WRITE :bit1; + OUTSTANDING_VP8_READ :bit1; + OUTSTANDING_VP8_WRITE :bit1; + end; + + TMC_HUB_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_HUB_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_HUB_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_HUB_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_HUB_RDREQ_ACPG_LIMIT=bitpacked record + ENABLE :bit2; + LIMIT_COUNT:bit5; + RESERVED0 :bit25; + end; + + TMC_HUB_RDREQ_DMIF_LIMIT=bitpacked record + ENABLE :bit2; + LIMIT_COUNT:bit5; + RESERVED0 :bit25; + end; + + TMC_HUB_WDP_CREDITS_MCDS=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDT=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDU=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDV=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDW=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDX=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDY=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_HUB_WDP_CREDITS_MCDZ=bitpacked record + WR_PRI :bit7; + WR_PRI_STALL_THRESHOLD:bit7; + WR_URG :bit7; + WR_URG_STALL_THRESHOLD:bit7; + RESERVED0 :bit4; + end; + + TMC_MCBVM_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_MCBVM_PERFCOUNTER_LO=bit32; + + TMC_MCDVM_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_MCDVM_PERFCOUNTER_LO=bit32; + + TMC_RPB_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_RPB_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_RPB_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_RPB_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_SHARED_ACTIVE_FCN_ID=bitpacked record + VFID :bit4; + RESERVED0:bit27; + VF :bit1; + end; + + TMC_SHARED_BLACKOUT_CNTL=bitpacked record + BLACKOUT_MODE :bit3; + BLACKOUT_SEQ_FREE :bit1; + BLACKOUT_MCD_NUM :bit8; + FREE_TIE_HIGH :bit1; + SRBM_DUMMY_READ_RETURN:bit1; + RESERVED0 :bit18; + end; + + TMC_VM_L2_PERFCOUNTER_HI=bitpacked record + COUNTER_HI :bit16; + COMPARE_VALUE:bit16; + end; + + TMC_VM_L2_PERFCOUNTER_LO=bit32; + + TMC_VM_MB_L1_TLB0_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MB_L1_TLB1_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MB_L1_TLB2_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MB_L1_TLB3_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MD_L1_TLB0_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MD_L1_TLB1_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MD_L1_TLB2_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + + TMC_VM_MD_L1_TLB3_STATUS=bitpacked record + BUSY :bit1; + RESERVED0:bit31; + end; + TPA_SC_AA_MASK_X0Y0_X1Y0=bitpacked record AA_MASK_X0Y0:bit16; AA_MASK_X1Y0:bit16; @@ -11188,6 +51148,934 @@ type TPA_SU_POLY_OFFSET_CLAMP=bit32; + TPB0_DFT_DEBUG_CTRL_REG0=bitpacked record + DFT_PHY_DEBUG_EN :bit1; + DFT_PHY_DEBUG_MODE:bit5; + RESERVED0 :bit26; + end; + + TPB0_RX_LANE10_CTRL_REG0=bitpacked record + RX_BACKUP_10 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_10:bit2; + RX_TST_BSCAN_EN_10 :bit1; + RX_CFG_OVR_PWRSF_10 :bit1; + RX_TERM_EN_10 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE11_CTRL_REG0=bitpacked record + RX_BACKUP_11 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_11:bit2; + RX_TST_BSCAN_EN_11 :bit1; + RX_CFG_OVR_PWRSF_11 :bit1; + RX_TERM_EN_11 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE12_CTRL_REG0=bitpacked record + RX_BACKUP_12 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_12:bit2; + RX_TST_BSCAN_EN_12 :bit1; + RX_CFG_OVR_PWRSF_12 :bit1; + RX_TERM_EN_12 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE13_CTRL_REG0=bitpacked record + RX_BACKUP_13 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_13:bit2; + RX_TST_BSCAN_EN_13 :bit1; + RX_CFG_OVR_PWRSF_13 :bit1; + RX_TERM_EN_13 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE14_CTRL_REG0=bitpacked record + RX_BACKUP_14 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_14:bit2; + RX_TST_BSCAN_EN_14 :bit1; + RX_CFG_OVR_PWRSF_14 :bit1; + RX_TERM_EN_14 :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE15_CTRL_REG0=bitpacked record + RX_BACKUP_15 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_15:bit2; + RX_TST_BSCAN_EN_15 :bit1; + RX_CFG_OVR_PWRSF_15 :bit1; + RX_TERM_EN_15 :bit1; + RESERVED1 :bit17; + end; + + TPB0_TX_LANE10_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_10 :bit1; + TX_CFG_INV_DATA_10 :bit1; + TX_CFG_SWING_BOOST_EN_10:bit1; + TX_DBG_PRBS_EN_10 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE10_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_10 :bit1; + TX_DCLK_EN_OVRD_EN_10 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_10 :bit1; + TX_DRV_DATA_EN_OVRD_EN_10 :bit1; + TX_DRV_PWRON_OVRD_VAL_10 :bit1; + TX_DRV_PWRON_OVRD_EN_10 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_10:bit1; + TX_FRONTEND_PWRON_OVRD_EN_10 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE11_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_11 :bit1; + TX_CFG_INV_DATA_11 :bit1; + TX_CFG_SWING_BOOST_EN_11:bit1; + TX_DBG_PRBS_EN_11 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE11_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_11 :bit1; + TX_DCLK_EN_OVRD_EN_11 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_11 :bit1; + TX_DRV_DATA_EN_OVRD_EN_11 :bit1; + TX_DRV_PWRON_OVRD_VAL_11 :bit1; + TX_DRV_PWRON_OVRD_EN_11 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_11:bit1; + TX_FRONTEND_PWRON_OVRD_EN_11 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE12_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_12 :bit1; + TX_CFG_INV_DATA_12 :bit1; + TX_CFG_SWING_BOOST_EN_12:bit1; + TX_DBG_PRBS_EN_12 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE12_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_12 :bit1; + TX_DCLK_EN_OVRD_EN_12 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_12 :bit1; + TX_DRV_DATA_EN_OVRD_EN_12 :bit1; + TX_DRV_PWRON_OVRD_VAL_12 :bit1; + TX_DRV_PWRON_OVRD_EN_12 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_12:bit1; + TX_FRONTEND_PWRON_OVRD_EN_12 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE13_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_13 :bit1; + TX_CFG_INV_DATA_13 :bit1; + TX_CFG_SWING_BOOST_EN_13:bit1; + TX_DBG_PRBS_EN_13 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE13_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_13 :bit1; + TX_DCLK_EN_OVRD_EN_13 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_13 :bit1; + TX_DRV_DATA_EN_OVRD_EN_13 :bit1; + TX_DRV_PWRON_OVRD_VAL_13 :bit1; + TX_DRV_PWRON_OVRD_EN_13 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_13:bit1; + TX_FRONTEND_PWRON_OVRD_EN_13 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE14_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_14 :bit1; + TX_CFG_INV_DATA_14 :bit1; + TX_CFG_SWING_BOOST_EN_14:bit1; + TX_DBG_PRBS_EN_14 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE14_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_14 :bit1; + TX_DCLK_EN_OVRD_EN_14 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_14 :bit1; + TX_DRV_DATA_EN_OVRD_EN_14 :bit1; + TX_DRV_PWRON_OVRD_VAL_14 :bit1; + TX_DRV_PWRON_OVRD_EN_14 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_14:bit1; + TX_FRONTEND_PWRON_OVRD_EN_14 :bit1; + RESERVED0 :bit24; + end; + + TPB0_TX_LANE15_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_15 :bit1; + TX_CFG_INV_DATA_15 :bit1; + TX_CFG_SWING_BOOST_EN_15:bit1; + TX_DBG_PRBS_EN_15 :bit1; + RESERVED0 :bit28; + end; + + TPB0_TX_LANE15_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_15 :bit1; + TX_DCLK_EN_OVRD_EN_15 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_15 :bit1; + TX_DRV_DATA_EN_OVRD_EN_15 :bit1; + TX_DRV_PWRON_OVRD_VAL_15 :bit1; + TX_DRV_PWRON_OVRD_EN_15 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_15:bit1; + TX_FRONTEND_PWRON_OVRD_EN_15 :bit1; + RESERVED0 :bit24; + end; + + TPB1_DFT_DEBUG_CTRL_REG0=bitpacked record + DFT_PHY_DEBUG_EN :bit1; + DFT_PHY_DEBUG_MODE:bit5; + RESERVED0 :bit26; + end; + + TPB1_RX_LANE10_CTRL_REG0=bitpacked record + RX_BACKUP_10 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_10:bit2; + RX_TST_BSCAN_EN_10 :bit1; + RX_CFG_OVR_PWRSF_10 :bit1; + RX_TERM_EN_10 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE11_CTRL_REG0=bitpacked record + RX_BACKUP_11 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_11:bit2; + RX_TST_BSCAN_EN_11 :bit1; + RX_CFG_OVR_PWRSF_11 :bit1; + RX_TERM_EN_11 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE12_CTRL_REG0=bitpacked record + RX_BACKUP_12 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_12:bit2; + RX_TST_BSCAN_EN_12 :bit1; + RX_CFG_OVR_PWRSF_12 :bit1; + RX_TERM_EN_12 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE13_CTRL_REG0=bitpacked record + RX_BACKUP_13 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_13:bit2; + RX_TST_BSCAN_EN_13 :bit1; + RX_CFG_OVR_PWRSF_13 :bit1; + RX_TERM_EN_13 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE14_CTRL_REG0=bitpacked record + RX_BACKUP_14 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_14:bit2; + RX_TST_BSCAN_EN_14 :bit1; + RX_CFG_OVR_PWRSF_14 :bit1; + RX_TERM_EN_14 :bit1; + RESERVED1 :bit17; + end; + + TPB1_RX_LANE15_CTRL_REG0=bitpacked record + RX_BACKUP_15 :bit8; + RESERVED0 :bit2; + RX_DBG_ANALOG_SEL_15:bit2; + RX_TST_BSCAN_EN_15 :bit1; + RX_CFG_OVR_PWRSF_15 :bit1; + RX_TERM_EN_15 :bit1; + RESERVED1 :bit17; + end; + + TPB1_TX_LANE10_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_10 :bit1; + TX_CFG_INV_DATA_10 :bit1; + TX_CFG_SWING_BOOST_EN_10:bit1; + TX_DBG_PRBS_EN_10 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE10_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_10 :bit1; + TX_DCLK_EN_OVRD_EN_10 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_10 :bit1; + TX_DRV_DATA_EN_OVRD_EN_10 :bit1; + TX_DRV_PWRON_OVRD_VAL_10 :bit1; + TX_DRV_PWRON_OVRD_EN_10 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_10:bit1; + TX_FRONTEND_PWRON_OVRD_EN_10 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE11_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_11 :bit1; + TX_CFG_INV_DATA_11 :bit1; + TX_CFG_SWING_BOOST_EN_11:bit1; + TX_DBG_PRBS_EN_11 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE11_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_11 :bit1; + TX_DCLK_EN_OVRD_EN_11 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_11 :bit1; + TX_DRV_DATA_EN_OVRD_EN_11 :bit1; + TX_DRV_PWRON_OVRD_VAL_11 :bit1; + TX_DRV_PWRON_OVRD_EN_11 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_11:bit1; + TX_FRONTEND_PWRON_OVRD_EN_11 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE12_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_12 :bit1; + TX_CFG_INV_DATA_12 :bit1; + TX_CFG_SWING_BOOST_EN_12:bit1; + TX_DBG_PRBS_EN_12 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE12_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_12 :bit1; + TX_DCLK_EN_OVRD_EN_12 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_12 :bit1; + TX_DRV_DATA_EN_OVRD_EN_12 :bit1; + TX_DRV_PWRON_OVRD_VAL_12 :bit1; + TX_DRV_PWRON_OVRD_EN_12 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_12:bit1; + TX_FRONTEND_PWRON_OVRD_EN_12 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE13_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_13 :bit1; + TX_CFG_INV_DATA_13 :bit1; + TX_CFG_SWING_BOOST_EN_13:bit1; + TX_DBG_PRBS_EN_13 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE13_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_13 :bit1; + TX_DCLK_EN_OVRD_EN_13 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_13 :bit1; + TX_DRV_DATA_EN_OVRD_EN_13 :bit1; + TX_DRV_PWRON_OVRD_VAL_13 :bit1; + TX_DRV_PWRON_OVRD_EN_13 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_13:bit1; + TX_FRONTEND_PWRON_OVRD_EN_13 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE14_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_14 :bit1; + TX_CFG_INV_DATA_14 :bit1; + TX_CFG_SWING_BOOST_EN_14:bit1; + TX_DBG_PRBS_EN_14 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE14_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_14 :bit1; + TX_DCLK_EN_OVRD_EN_14 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_14 :bit1; + TX_DRV_DATA_EN_OVRD_EN_14 :bit1; + TX_DRV_PWRON_OVRD_VAL_14 :bit1; + TX_DRV_PWRON_OVRD_EN_14 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_14:bit1; + TX_FRONTEND_PWRON_OVRD_EN_14 :bit1; + RESERVED0 :bit24; + end; + + TPB1_TX_LANE15_CTRL_REG0=bitpacked record + TX_CFG_DISPCLK_MODE_15 :bit1; + TX_CFG_INV_DATA_15 :bit1; + TX_CFG_SWING_BOOST_EN_15:bit1; + TX_DBG_PRBS_EN_15 :bit1; + RESERVED0 :bit28; + end; + + TPB1_TX_LANE15_OVRD_REG0=bitpacked record + TX_DCLK_EN_OVRD_VAL_15 :bit1; + TX_DCLK_EN_OVRD_EN_15 :bit1; + TX_DRV_DATA_EN_OVRD_VAL_15 :bit1; + TX_DRV_DATA_EN_OVRD_EN_15 :bit1; + TX_DRV_PWRON_OVRD_VAL_15 :bit1; + TX_DRV_PWRON_OVRD_EN_15 :bit1; + TX_FRONTEND_PWRON_OVRD_VAL_15:bit1; + TX_FRONTEND_PWRON_OVRD_EN_15 :bit1; + RESERVED0 :bit24; + end; + + TPCIE_DEV_SERIAL_NUM_DW1=bit32; + + TPCIE_DEV_SERIAL_NUM_DW2=bit32; + + TPCIE_LC_LINK_WIDTH_CNTL=bitpacked record + LC_LINK_WIDTH :bit3; + RESERVED0 :bit1; + LC_LINK_WIDTH_RD :bit3; + LC_RECONFIG_ARC_MISSING_ESCAPE:bit1; + LC_RECONFIG_NOW :bit1; + LC_RENEGOTIATION_SUPPORT :bit1; + LC_RENEGOTIATE_EN :bit1; + LC_SHORT_RECONFIG_EN :bit1; + LC_UPCONFIGURE_SUPPORT :bit1; + LC_UPCONFIGURE_DIS :bit1; + LC_UPCFG_WAIT_FOR_RCVR_DIS :bit1; + LC_UPCFG_TIMER_SEL :bit1; + LC_DEASSERT_TX_PDNB :bit1; + LC_L1_RECONFIG_EN :bit1; + LC_DYNLINK_MST_EN :bit1; + LC_DUAL_END_RECONFIG_EN :bit1; + LC_UPCONFIGURE_CAPABLE :bit1; + LC_DYN_LANES_PWR_STATE :bit2; + LC_EQ_REVERSAL_LOGIC_EN :bit1; + LC_MULT_REVERSE_ATTEMP_EN :bit1; + LC_RESET_TSX_CNT_IN_RCONFIG_EN:bit1; + LC_WAIT_FOR_L_IDLE_IN_R_IDLE :bit1; + RESERVED1 :bit5; + end; + + TPCIE_PASID_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_PERF_COUNT0_TXCLK2=bit32; + + TPCIE_PERF_COUNT1_TXCLK2=bit32; + + TPCIE_P_PORT_LANE_STATUS=bitpacked record + PORT_LANE_REVERSAL:bit1; + PHY_LINK_WIDTH :bit6; + RESERVED0 :bit25; + end; + + TPCIE_RX_EXPECTED_SEQNUM=bitpacked record + RX_EXPECTED_SEQNUM:bit12; + RESERVED0 :bit20; + end; + + TPCIE_RX_VENDOR_SPECIFIC=bitpacked record + RX_VENDOR_DATA :bit24; + RX_VENDOR_STATUS:bit1; + RESERVED0 :bit7; + end; + + TPCIE_SRIOV_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_SRIOV_VF_DEVICE_ID=bitpacked record + SRIOV_VF_DEVICE_ID:bit16; + RESERVED0 :bit16; + end; + + TPCIE_TX_CREDITS_ADVT_NP=bitpacked record + TX_CREDITS_ADVT_NPD:bit12; + RESERVED0 :bit4; + TX_CREDITS_ADVT_NPH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_CREDITS_INIT_NP=bitpacked record + TX_CREDITS_INIT_NPD:bit12; + RESERVED0 :bit4; + TX_CREDITS_INIT_NPH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_F1_F2_ATTR_CNTL=bitpacked record + TX_F1_IDO_OVERRIDE_P :bit2; + TX_F1_IDO_OVERRIDE_NP :bit2; + TX_F1_IDO_OVERRIDE_CPL:bit2; + TX_F1_RO_OVERRIDE_P :bit2; + TX_F1_RO_OVERRIDE_NP :bit2; + TX_F1_SNR_OVERRIDE_P :bit2; + TX_F1_SNR_OVERRIDE_NP :bit2; + RESERVED0 :bit2; + TX_F2_IDO_OVERRIDE_P :bit2; + TX_F2_IDO_OVERRIDE_NP :bit2; + TX_F2_IDO_OVERRIDE_CPL:bit2; + TX_F2_RO_OVERRIDE_P :bit2; + TX_F2_RO_OVERRIDE_NP :bit2; + TX_F2_SNR_OVERRIDE_P :bit2; + TX_F2_SNR_OVERRIDE_NP :bit2; + RESERVED1 :bit2; + end; + + TPCIE_TX_VENDOR_SPECIFIC=bitpacked record + TX_VENDOR_DATA:bit24; + RESERVED0 :bit8; + end; + + TPCIE_WRAP_REG_TARG_MISC=bitpacked record + CLKEN_MASK:bit1; + RESERVED0 :bit31; + end; + + TPERFMON_CVALUE_INT_MISC=bitpacked record + PERFCOUNTER_INT0_STATUS:bit1; + PERFCOUNTER_INT1_STATUS:bit1; + PERFCOUNTER_INT2_STATUS:bit1; + PERFCOUNTER_INT3_STATUS:bit1; + PERFCOUNTER_INT4_STATUS:bit1; + PERFCOUNTER_INT5_STATUS:bit1; + PERFCOUNTER_INT6_STATUS:bit1; + PERFCOUNTER_INT7_STATUS:bit1; + PERFCOUNTER_INT0_ACK :bit1; + PERFCOUNTER_INT1_ACK :bit1; + PERFCOUNTER_INT2_ACK :bit1; + PERFCOUNTER_INT3_ACK :bit1; + PERFCOUNTER_INT4_ACK :bit1; + PERFCOUNTER_INT5_ACK :bit1; + PERFCOUNTER_INT6_ACK :bit1; + PERFCOUNTER_INT7_ACK :bit1; + PERFMON_CVALUE_HI :bit16; + end; + + TPERFMON_TEST_DEBUG_DATA=bit32; + + TPWR_DISP_TIMER2_CONTROL=bitpacked record + DISP_TIMER_INT_COUNT :bit25; + DISP_TIMER_INT_ENABLE :bit1; + DISP_TIMER_INT_DISABLE:bit1; + DISP_TIMER_INT_MASK :bit1; + DISP_TIMER_INT_STAT_AK:bit1; + DISP_TIMER_INT_TYPE :bit1; + DISP_TIMER_INT_MODE :bit1; + RESERVED0 :bit1; + end; + + TPWR_DISP_TIMER_CONTROL2=bitpacked record + DISP_TIMER_PULSE_WIDTH:bit10; + RESERVED0 :bit22; + end; + + TREGAMMA_CNTLA_END_CNTL1=bitpacked record + REGAMMA_CNTLA_EXP_REGION_END:bit16; + RESERVED0 :bit16; + end; + + TREGAMMA_CNTLA_END_CNTL2=bitpacked record + REGAMMA_CNTLA_EXP_REGION_END_SLOPE:bit16; + REGAMMA_CNTLA_EXP_REGION_END_BASE :bit16; + end; + + TREGAMMA_CNTLB_END_CNTL1=bitpacked record + REGAMMA_CNTLB_EXP_REGION_END:bit16; + RESERVED0 :bit16; + end; + + TREGAMMA_CNTLB_END_CNTL2=bitpacked record + REGAMMA_CNTLB_EXP_REGION_END_SLOPE:bit16; + REGAMMA_CNTLB_EXP_REGION_END_BASE :bit16; + end; + + TRIRB_LOWER_BASE_ADDRESS=bitpacked record + RIRB_LOWER_BASE_UNIMPLEMENTED_BITS:bit7; + RIRB_LOWER_BASE_ADDRESS :bit25; + end; + + TRIRB_UPPER_BASE_ADDRESS=bit32; + + TRLC_DRIVER_CPDMA_STATUS=bitpacked record + DRIVER_REQUEST:bit1; + RESERVED1 :bit3; + DRIVER_ACK :bit1; + RESERVED :bit27; + end; + + TRLC_GPM_INT_DISABLE_TH0=bit32; + + TRLC_GPM_INT_DISABLE_TH1=bit32; + + TRLC_GPM_THREAD_PRIORITY=bitpacked record + THREAD0_PRIORITY:bit8; + THREAD1_PRIORITY:bit8; + THREAD2_PRIORITY:bit8; + THREAD3_PRIORITY:bit8; + end; + + TRLC_GPU_CLOCK_COUNT_LSB=bit32; + + TRLC_GPU_CLOCK_COUNT_MSB=bit32; + + TRLC_GPU_IOV_INT_DISABLE=bit32; + + TRLC_PERFCOUNTER0_SELECT=bitpacked record + PERFCOUNTER_SELECT:bit8; + RESERVED0 :bit24; + end; + + TRLC_PERFCOUNTER1_SELECT=bitpacked record + PERFCOUNTER_SELECT:bit8; + RESERVED0 :bit24; + end; + + TRLC_SMU_PG_WAKE_UP_CTRL=bitpacked record + START_PG_WAKE_UP:bit1; + SPARE :bit31; + end; + + TSCLV_HORZ_FILTER_INIT_C=bitpacked record + SCL_H_INIT_FRAC_C:bit24; + SCL_H_INIT_INT_C :bit4; + RESERVED0 :bit4; + end; + + TSCLV_VERT_FILTER_INIT_C=bitpacked record + SCL_V_INIT_FRAC_C:bit24; + SCL_V_INIT_INT_C :bit3; + RESERVED0 :bit5; + end; + + TSCL_HORZ_FILTER_CONTROL=bitpacked record + SCL_H_FILTER_PICK_NEAREST :bit1; + RESERVED0 :bit7; + SCL_H_2TAP_HARDCODE_COEF_EN:bit1; + RESERVED1 :bit23; + end; + + TSCL_VERT_FILTER_CONTROL=bitpacked record + SCL_V_FILTER_PICK_NEAREST :bit1; + RESERVED0 :bit7; + SCL_V_2TAP_HARDCODE_COEF_EN:bit1; + RESERVED1 :bit23; + end; + + TSDMA0_CONTEXT_REG_TYPE0=bitpacked record + SDMA0_GFX_RB_CNTL :bit1; + SDMA0_GFX_RB_BASE :bit1; + SDMA0_GFX_RB_BASE_HI :bit1; + SDMA0_GFX_RB_RPTR :bit1; + SDMA0_GFX_RB_WPTR :bit1; + SDMA0_GFX_RB_WPTR_POLL_CNTL :bit1; + SDMA0_GFX_RB_WPTR_POLL_ADDR_HI:bit1; + SDMA0_GFX_RB_WPTR_POLL_ADDR_LO:bit1; + SDMA0_GFX_RB_RPTR_ADDR_HI :bit1; + SDMA0_GFX_RB_RPTR_ADDR_LO :bit1; + SDMA0_GFX_IB_CNTL :bit1; + SDMA0_GFX_IB_RPTR :bit1; + SDMA0_GFX_IB_OFFSET :bit1; + SDMA0_GFX_IB_BASE_LO :bit1; + SDMA0_GFX_IB_BASE_HI :bit1; + SDMA0_GFX_IB_SIZE :bit1; + SDMA0_GFX_SKIP_CNTL :bit1; + SDMA0_GFX_CONTEXT_STATUS :bit1; + SDMA0_GFX_DOORBELL :bit1; + SDMA0_GFX_CONTEXT_CNTL :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + end; + + TSDMA0_CONTEXT_REG_TYPE1=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + SDMA0_GFX_VIRTUAL_ADDR :bit1; + SDMA0_GFX_APE1_CNTL :bit1; + SDMA0_GFX_DOORBELL_LOG :bit1; + SDMA0_GFX_WATERMARK :bit1; + VOID_REG1 :bit1; + SDMA0_GFX_CSA_ADDR_LO :bit1; + SDMA0_GFX_CSA_ADDR_HI :bit1; + VOID_REG2 :bit1; + SDMA0_GFX_IB_SUB_REMAIN:bit1; + SDMA0_GFX_PREEMPT :bit1; + SDMA0_GFX_DUMMY_REG :bit1; + RESERVED :bit14; + end; + + TSDMA0_CONTEXT_REG_TYPE2=bitpacked record + SDMA0_GFX_MIDCMD_DATA0:bit1; + SDMA0_GFX_MIDCMD_DATA1:bit1; + SDMA0_GFX_MIDCMD_DATA2:bit1; + SDMA0_GFX_MIDCMD_DATA3:bit1; + SDMA0_GFX_MIDCMD_DATA4:bit1; + SDMA0_GFX_MIDCMD_DATA5:bit1; + SDMA0_GFX_MIDCMD_CNTL :bit1; + RESERVED :bit25; + end; + + TSDMA0_GFX_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSDMA0_RLC0_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA0_RLC0_MIDCMD_DATA0=bit32; + + TSDMA0_RLC0_MIDCMD_DATA1=bit32; + + TSDMA0_RLC0_MIDCMD_DATA2=bit32; + + TSDMA0_RLC0_MIDCMD_DATA3=bit32; + + TSDMA0_RLC0_MIDCMD_DATA4=bit32; + + TSDMA0_RLC0_MIDCMD_DATA5=bit32; + + TSDMA0_RLC0_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA0_RLC1_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA0_RLC1_MIDCMD_DATA0=bit32; + + TSDMA0_RLC1_MIDCMD_DATA1=bit32; + + TSDMA0_RLC1_MIDCMD_DATA2=bit32; + + TSDMA0_RLC1_MIDCMD_DATA3=bit32; + + TSDMA0_RLC1_MIDCMD_DATA4=bit32; + + TSDMA0_RLC1_MIDCMD_DATA5=bit32; + + TSDMA0_RLC1_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA1_CONTEXT_REG_TYPE0=bitpacked record + SDMA1_GFX_RB_CNTL :bit1; + SDMA1_GFX_RB_BASE :bit1; + SDMA1_GFX_RB_BASE_HI :bit1; + SDMA1_GFX_RB_RPTR :bit1; + SDMA1_GFX_RB_WPTR :bit1; + SDMA1_GFX_RB_WPTR_POLL_CNTL :bit1; + SDMA1_GFX_RB_WPTR_POLL_ADDR_HI:bit1; + SDMA1_GFX_RB_WPTR_POLL_ADDR_LO:bit1; + SDMA1_GFX_RB_RPTR_ADDR_HI :bit1; + SDMA1_GFX_RB_RPTR_ADDR_LO :bit1; + SDMA1_GFX_IB_CNTL :bit1; + SDMA1_GFX_IB_RPTR :bit1; + SDMA1_GFX_IB_OFFSET :bit1; + SDMA1_GFX_IB_BASE_LO :bit1; + SDMA1_GFX_IB_BASE_HI :bit1; + SDMA1_GFX_IB_SIZE :bit1; + SDMA1_GFX_SKIP_CNTL :bit1; + SDMA1_GFX_CONTEXT_STATUS :bit1; + SDMA1_GFX_DOORBELL :bit1; + SDMA1_GFX_CONTEXT_CNTL :bit1; + RESERVED :bit12; + end; + + TSDMA1_CONTEXT_REG_TYPE1=bitpacked record + VOID_REG0 :bit7; + SDMA1_GFX_VIRTUAL_ADDR :bit1; + SDMA1_GFX_APE1_CNTL :bit1; + SDMA1_GFX_DOORBELL_LOG :bit1; + SDMA1_GFX_WATERMARK :bit1; + VOID_REG2 :bit1; + SDMA1_GFX_CSA_ADDR_LO :bit1; + SDMA1_GFX_CSA_ADDR_HI :bit1; + VOID_REG3 :bit1; + SDMA1_GFX_IB_SUB_REMAIN:bit1; + SDMA1_GFX_PREEMPT :bit1; + SDMA1_GFX_DUMMY_REG :bit1; + RESERVED :bit14; + end; + + TSDMA1_CONTEXT_REG_TYPE2=bitpacked record + SDMA1_GFX_MIDCMD_DATA0:bit1; + SDMA1_GFX_MIDCMD_DATA1:bit1; + SDMA1_GFX_MIDCMD_DATA2:bit1; + SDMA1_GFX_MIDCMD_DATA3:bit1; + SDMA1_GFX_MIDCMD_DATA4:bit1; + SDMA1_GFX_MIDCMD_DATA5:bit1; + SDMA1_GFX_MIDCMD_CNTL :bit1; + RESERVED :bit25; + end; + + TSDMA1_GFX_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSDMA1_RLC0_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA1_RLC0_MIDCMD_DATA0=bit32; + + TSDMA1_RLC0_MIDCMD_DATA1=bit32; + + TSDMA1_RLC0_MIDCMD_DATA2=bit32; + + TSDMA1_RLC0_MIDCMD_DATA3=bit32; + + TSDMA1_RLC0_MIDCMD_DATA4=bit32; + + TSDMA1_RLC0_MIDCMD_DATA5=bit32; + + TSDMA1_RLC0_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSDMA1_RLC1_DOORBELL_LOG=bitpacked record + BE_ERROR :bit1; + RESERVED0:bit1; + DATA :bit30; + end; + + TSDMA1_RLC1_MIDCMD_DATA0=bit32; + + TSDMA1_RLC1_MIDCMD_DATA1=bit32; + + TSDMA1_RLC1_MIDCMD_DATA2=bit32; + + TSDMA1_RLC1_MIDCMD_DATA3=bit32; + + TSDMA1_RLC1_MIDCMD_DATA4=bit32; + + TSDMA1_RLC1_MIDCMD_DATA5=bit32; + + TSDMA1_RLC1_VIRTUAL_ADDR=bitpacked record + ATC :bit1; + INVAL :bit1; + RESERVED0 :bit2; + PTR32 :bit1; + RESERVED1 :bit3; + SHARED_BASE:bit3; + RESERVED2 :bit19; + VM_HOLE :bit1; + RESERVED3 :bit1; + end; + + TSEM_PERFCOUNTER0_RESULT=bit32; + + TSEM_PERFCOUNTER1_RESULT=bit32; + + TSOFT_REGISTERS_TABLE_10=bit32; + + TSOFT_REGISTERS_TABLE_11=bit32; + + TSOFT_REGISTERS_TABLE_12=bit32; + + TSOFT_REGISTERS_TABLE_13=bit32; + + TSOFT_REGISTERS_TABLE_14=bitpacked record + DisplayPhy4Config:bit8; + DisplayPhy3Config:bit8; + DisplayPhy2Config:bit8; + DisplayPhy1Config:bit8; + end; + + TSOFT_REGISTERS_TABLE_15=bitpacked record + DisplayPhy8Config:bit8; + DisplayPhy7Config:bit8; + DisplayPhy6Config:bit8; + DisplayPhy5Config:bit8; + end; + + TSOFT_REGISTERS_TABLE_16=bit32; + + TSOFT_REGISTERS_TABLE_17=bit32; + + TSOFT_REGISTERS_TABLE_18=bit32; + + TSOFT_REGISTERS_TABLE_19=bitpacked record + PCIeDpmEnabledLevels:bit8; + LClkDpmEnabledLevels:bit8; + MClkDpmEnabledLevels:bit8; + SClkDpmEnabledLevels:bit8; + end; + + TSOFT_REGISTERS_TABLE_20=bitpacked record + VCEDpmEnabledLevels :bit8; + ACPDpmEnabledLevels :bit8; + SAMUDpmEnabledLevels:bit8; + UVDDpmEnabledLevels :bit8; + end; + + TSOFT_REGISTERS_TABLE_21=bit32; + + TSOFT_REGISTERS_TABLE_22=bit32; + + TSOFT_REGISTERS_TABLE_23=bit32; + + TSOFT_REGISTERS_TABLE_24=bit32; + + TSOFT_REGISTERS_TABLE_25=bit32; + + TSOFT_REGISTERS_TABLE_26=bit32; + + TSOFT_REGISTERS_TABLE_27=bit32; + + TSOFT_REGISTERS_TABLE_28=bit32; + + TSOFT_REGISTERS_TABLE_29=bit32; + + TSOFT_REGISTERS_TABLE_30=bit32; + TSPI_COMPUTE_QUEUE_RESET=bitpacked record RESET :bit1; RESERVED0:bit31; @@ -11487,6 +52375,18 @@ type EN_WARN:bit1; end; + TSPMI_FORCE_CLOCK_GATERS=bitpacked record + RESERVED0:bit1; + RESERVED1:bit7; + RESERVED2:bit1; + RESERVED3:bit23; + end; + + TSPMI_FSM_READ_TRIGGER_0=bitpacked record + FSM_READ_TRIGGER:bit1; + RESERVED0 :bit31; + end; + TSQ_PERFCOUNTER10_SELECT=bitpacked record PERF_SEL :bit9; RESERVED0 :bit3; @@ -11552,6 +52452,37 @@ type RESERVED0:bit29; end; + TSRBM_FIREWALL_ERROR_SRC=bitpacked record + ACCESS_REQUESTER_BIF :bit1; + ACCESS_REQUESTER_ACP :bit1; + ACCESS_REQUESTER_SAMSCP :bit1; + ACCESS_REQUESTER_SAMMSP :bit1; + RESERVED0 :bit1; + ACCESS_REQUESTER_TST :bit1; + ACCESS_REQUESTER_SDMA3 :bit1; + ACCESS_REQUESTER_SDMA2 :bit1; + ACCESS_REQUESTER_SDMA1 :bit1; + ACCESS_REQUESTER_SDMA0 :bit1; + ACCESS_REQUESTER_UVD :bit1; + ACCESS_REQUESTER_VCE0 :bit1; + ACCESS_REQUESTER_GRBM :bit1; + ACCESS_REQUESTER_SMU :bit1; + ACCESS_REQUESTER_PEER :bit1; + ACCESS_REQUESTER_CPU :bit1; + ACCESS_REQUESTER_ISP :bit1; + ACCESS_REQUESTER_VCE1 :bit1; + ACCESS_REQUESTER_RLCHYP :bit1; + ACCESS_REQUESTER_SMUHYP :bit1; + ACCESS_REQUESTER_BIFHYP :bit1; + RESERVED1 :bit3; + RAERR_FIREWALL_VIOLATION :bit1; + RAERR_HAR_REGIONSIZE_OVERFLOW :bit1; + RAERR_BIF_ADDR_OVERFLOW :bit1; + RAERR_P2SRP_REGIONSIZE_OVERFLOW:bit1; + RAERR_P2SRP_FIREWALL_VIOLATION :bit1; + RESERVED2 :bit3; + end; + TSX_PERFCOUNTER0_SELECT1=bitpacked record PERFCOUNTER_SELECT2:bit10; PERFCOUNTER_SELECT3:bit10; @@ -11564,6 +52495,16 @@ type RESERVED0 :bit12; end; + TSYS_GRBM_GFX_INDEX_DATA=bitpacked record + INSTANCE_INDEX :bit8; + SH_INDEX :bit8; + SE_INDEX :bit8; + RESERVED0 :bit5; + SH_BROADCAST_WRITES :bit1; + INSTANCE_BROADCAST_WRITES:bit1; + SE_BROADCAST_WRITES :bit1; + end; + TTA_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2 :bit8; RESERVED0 :bit2; @@ -11669,6 +52610,63 @@ type PERF_MODE:bit4; end; + TTC_CFG_L2_ATOMIC_POLICY=bitpacked record + POLICY_0 :bit2; + POLICY_1 :bit2; + POLICY_2 :bit2; + POLICY_3 :bit2; + POLICY_4 :bit2; + POLICY_5 :bit2; + POLICY_6 :bit2; + POLICY_7 :bit2; + POLICY_8 :bit2; + POLICY_9 :bit2; + POLICY_10:bit2; + POLICY_11:bit2; + POLICY_12:bit2; + POLICY_13:bit2; + POLICY_14:bit2; + POLICY_15:bit2; + end; + + TTC_CFG_L2_STORE_POLICY0=bitpacked record + POLICY_0 :bit2; + POLICY_1 :bit2; + POLICY_2 :bit2; + POLICY_3 :bit2; + POLICY_4 :bit2; + POLICY_5 :bit2; + POLICY_6 :bit2; + POLICY_7 :bit2; + POLICY_8 :bit2; + POLICY_9 :bit2; + POLICY_10:bit2; + POLICY_11:bit2; + POLICY_12:bit2; + POLICY_13:bit2; + POLICY_14:bit2; + POLICY_15:bit2; + end; + + TTC_CFG_L2_STORE_POLICY1=bitpacked record + POLICY_16:bit2; + POLICY_17:bit2; + POLICY_18:bit2; + POLICY_19:bit2; + POLICY_20:bit2; + POLICY_21:bit2; + POLICY_22:bit2; + POLICY_23:bit2; + POLICY_24:bit2; + POLICY_25:bit2; + POLICY_26:bit2; + POLICY_27:bit2; + POLICY_28:bit2; + POLICY_29:bit2; + POLICY_30:bit2; + POLICY_31:bit2; + end; + TTD_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2 :bit8; RESERVED0 :bit2; @@ -11678,6 +52676,99 @@ type PERF_MODE2:bit4; end; + TTMDS_DCBALANCER_CONTROL=bitpacked record + TMDS_DCBALANCER_EN :bit1; + RESERVED0 :bit3; + TMDS_SYNC_DCBAL_EN :bit3; + RESERVED1 :bit1; + TMDS_DCBALANCER_TEST_EN:bit1; + RESERVED2 :bit7; + TMDS_DCBALANCER_TEST_IN:bit4; + RESERVED3 :bit4; + TMDS_DCBALANCER_FORCE :bit1; + RESERVED4 :bit7; + end; + + TTMDS_STEREOSYNC_CTL_SEL=bitpacked record + TMDS_STEREOSYNC_CTL_SEL:bit2; + RESERVED0 :bit30; + end; + + TUNIPHY_PLL_SS_STEP_SIZE=bitpacked record + UNIPHY_PLL_SS_STEP_SIZE:bit26; + RESERVED0 :bit6; + end; + + TUNIPHY_REG_TEST_OUTPUT2=bitpacked record + UNIPHY_TX:bit16; + RESERVED0:bit16; + end; + + TUNP_GRPH_FLIP_RATE_CNTL=bitpacked record + GRPH_FLIP_RATE :bit3; + GRPH_FLIP_RATE_ENABLE:bit1; + RESERVED0 :bit28; + end; + + TUVD_MIF_REF_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TUVD_SEMA_TIMEOUT_STATUS=bitpacked record + SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT :bit1; + SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT :bit1; + SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT:bit1; + SEMAPHORE_TIMEOUT_CLEAR :bit1; + RESERVED0 :bit28; + end; + + TUVD_UDEC_DB_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TVGA_DEBUG_READBACK_DATA=bit32; + + TVGA_MEMORY_BASE_ADDRESS=bit32; + + TVGA_MEM_WRITE_PAGE_ADDR=bitpacked record + VGA_MEM_WRITE_PAGE0_ADDR:bit10; + RESERVED0 :bit6; + VGA_MEM_WRITE_PAGE1_ADDR:bit10; + RESERVED1 :bit6; + end; + TVGT_DISPATCH_DRAW_INDEX=bit32; TVGT_DMA_DATA_FIFO_DEPTH=bitpacked record @@ -11714,6 +52805,501 @@ type PERF_MODE:bit4; end; + TVM_L2_BANK_SELECT_MASKA=bitpacked record + BANK_SELECT_MASK:bit28; + RESERVED0 :bit4; + end; + + TVM_L2_BANK_SELECT_MASKB=bitpacked record + BANK_SELECT_MASK:bit9; + RESERVED0 :bit23; + end; + + TXDMA_MSTR_CHANNEL_START=bitpacked record + XDMA_MSTR_CHANNEL_START_X:bit14; + RESERVED0 :bit2; + XDMA_MSTR_CHANNEL_START_Y:bit14; + RESERVED1 :bit2; + end; + + TXDMA_MSTR_PERFMEAS_CNTL=bitpacked record + XDMA_MSTR_CACHE_BW_MEAS_ITER :bit12; + XDMA_MSTR_CACHE_BW_SEGID_SEL :bit5; + XDMA_MSTR_CACHE_BW_COUNTER_RST:bit1; + RESERVED0 :bit1; + XDMA_MSTR_LT_MEAS_ITER :bit12; + XDMA_MSTR_LT_COUNTER_RST :bit1; + end; + + TATC_ATS_DEFAULT_PAGE_LOW=bitpacked record + DEFAULT_PAGE:bit28; + RESERVED0 :bit4; + end; + + TATC_VMID10_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID11_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID12_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID13_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID14_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TATC_VMID15_PASID_MAPPING=bitpacked record + PASID :bit16; + RESERVED0 :bit14; + NO_INVALIDATION:bit1; + VALID :bit1; + end; + + TAZALIA_AUDIO_DTO_CONTROL=bitpacked record + RESERVED0 :bit8; + AZALIA_AUDIO_FORCE_DTO:bit2; + RESERVED1 :bit22; + end; + + TAZALIA_FIFO_SIZE_CONTROL=bitpacked record + MIN_FIFO_SIZE :bit7; + RESERVED0 :bit1; + MAX_FIFO_SIZE :bit7; + RESERVED1 :bit1; + MAX_LATENCY_SUPPORT:bit8; + RESERVED2 :bit8; + end; + + TAZALIA_INPUT_CRC0_RESULT=bit32; + + TAZALIA_INPUT_CRC1_RESULT=bit32; + + TBIF_RFE_MST_BU_CMDSTATUS=bitpacked record + REG_BU_clkGate_timer :bit8; + REG_BU_clkSetup_timer:bit4; + RESERVED0 :bit4; + REG_BU_timeout_timer :bit8; + BU_RFE_mstTimeout :bit1; + RESERVED1 :bit7; + end; + + TBIF_RFE_MST_BX_CMDSTATUS=bitpacked record + REG_BX_clkGate_timer :bit8; + REG_BX_clkSetup_timer:bit4; + RESERVED0 :bit4; + REG_BX_timeout_timer :bit8; + BX_RFE_mstTimeout :bit1; + RESERVED1 :bit7; + end; + + TBIF_RFE_MST_TMOUT_STATUS=bitpacked record + MstTmoutStatus:bit1; + RESERVED0 :bit31; + end; + + TBL1_PWM_FINAL_DUTY_CYCLE=bitpacked record + BL1_PWM_FINAL_DUTY_CYCLE:bit17; + RESERVED0 :bit15; + end; + + TBL1_PWM_TARGET_ABM_LEVEL=bitpacked record + BL1_PWM_TARGET_ABM_LEVEL:bit17; + RESERVED0 :bit15; + end; + + TBLND_UNDERFLOW_INTERRUPT=bitpacked record + BLND_UNDERFLOW_INT_OCCURED :bit1; + RESERVED0 :bit7; + BLND_UNDERFLOW_INT_ACK :bit1; + RESERVED1 :bit3; + BLND_UNDERFLOW_INT_MASK :bit1; + RESERVED2 :bit3; + BLND_UNDERFLOW_INT_PIPE_INDEX:bit2; + RESERVED3 :bit14; + end; + + TCC_GC_SHADER_RATE_CONFIG=bitpacked record + RESERVED0 :bit1; + DPFP_RATE :bit2; + SQC_BALANCE_DISABLE:bit1; + HALF_LDS :bit1; + RESERVED1 :bit27; + end; + + TCGTS_CU0_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU0_TA_SQC_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + SQC :bit7; + SQC_OVERRIDE :bit1; + SQC_BUSY_OVERRIDE :bit2; + SQC_LS_OVERRIDE :bit1; + SQC_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU0_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU1_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU1_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU2_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU2_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU3_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU3_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU4_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU4_TA_SQC_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + SQC :bit7; + SQC_OVERRIDE :bit1; + SQC_BUSY_OVERRIDE :bit2; + SQC_LS_OVERRIDE :bit1; + SQC_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU4_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU5_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU5_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU6_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU6_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU7_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU7_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU8_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU8_TA_SQC_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + SQC :bit7; + SQC_OVERRIDE :bit1; + SQC_BUSY_OVERRIDE :bit2; + SQC_LS_OVERRIDE :bit1; + SQC_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU8_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU9_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU9_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCOL_MAN_TEST_DEBUG_INDEX=bitpacked record + COL_MAN_TEST_DEBUG_INDEX :bit8; + COL_MAN_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + TCOMPUTE_PERFCOUNT_ENABLE=bitpacked record PERFCOUNT_ENABLE:bit1; RESERVED0 :bit31; @@ -11773,17 +53359,201 @@ type RESERVED0:bit16; end; + TCP_ME_INTR_ROUTINE_START=bitpacked record + IR_START :bit12; + RESERVED0:bit20; + end; + TCP_PFP_COMPLETION_STATUS=bitpacked record STATUS :bit2; RESERVED0:bit30; end; + TCRTC_PIXEL_DATA_READBACK=bitpacked record + RESERVED0:bit10; + RESERVED1:bit10; + RESERVED2:bit10; + RESERVED3:bit2; + end; + + TCRTC_V_UPDATE_INT_STATUS=bitpacked record + CRTC_V_UPDATE_INT_OCCURRED:bit1; + RESERVED0 :bit7; + CRTC_V_UPDATE_INT_CLEAR :bit1; + RESERVED1 :bit23; + end; + + TCUR_SURFACE_ADDRESS_HIGH=bitpacked record + CURSOR_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TDAC_CRC_SIG_CONTROL_MASK=bitpacked record + DAC_CRC_SIG_CONTROL_MASK:bit6; + RESERVED0 :bit26; + end; + + TDAC_MACRO_CNTL_RESERVED0=bit32; + + TDAC_MACRO_CNTL_RESERVED1=bit32; + + TDAC_MACRO_CNTL_RESERVED2=bit32; + + TDAC_MACRO_CNTL_RESERVED3=bit32; + + TDCDEBUG_OUT_PIN_OVERRIDE=bitpacked record + DCDEBUG_OUT_OVERRIDE1_PIN_SEL :bit5; + DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL:bit5; + RESERVED0 :bit2; + DCDEBUG_OUT_OVERRIDE1_EN :bit1; + RESERVED1 :bit2; + DCDEBUG_OUT_OVERRIDE2_PIN_SEL :bit5; + DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL:bit5; + RESERVED2 :bit3; + DCDEBUG_OUT_OVERRIDE2_EN :bit1; + RESERVED3 :bit3; + end; + + TDCFEV_DMIFV_MEM_PWR_CTRL=bitpacked record + DMIFV_MEM_PWR_SEL :bit2; + DMIFV_MEM_PWR_LUMA_0_FORCE :bit1; + DMIFV_MEM_PWR_LUMA_1_FORCE :bit1; + DMIFV_MEM_PWR_LUMA_2_FORCE :bit1; + DMIFV_MEM_PWR_LUMA_3_FORCE :bit1; + DMIFV_MEM_PWR_LUMA_4_FORCE :bit1; + DMIFV_MEM_PWR_CHROMA_0_FORCE:bit1; + DMIFV_MEM_PWR_CHROMA_1_FORCE:bit1; + DMIFV_MEM_PWR_CHROMA_2_FORCE:bit1; + DMIFV_MEM_PWR_CHROMA_3_FORCE:bit1; + DMIFV_MEM_PWR_CHROMA_4_FORCE:bit1; + RESERVED0 :bit20; + end; + + TDC_I2C_INTERRUPT_CONTROL=bitpacked record + DC_I2C_SW_DONE_INT :bit1; + DC_I2C_SW_DONE_ACK :bit1; + DC_I2C_SW_DONE_MASK :bit1; + RESERVED0 :bit1; + DC_I2C_DDC1_HW_DONE_INT :bit1; + DC_I2C_DDC1_HW_DONE_ACK :bit1; + DC_I2C_DDC1_HW_DONE_MASK :bit1; + RESERVED1 :bit1; + DC_I2C_DDC2_HW_DONE_INT :bit1; + DC_I2C_DDC2_HW_DONE_ACK :bit1; + DC_I2C_DDC2_HW_DONE_MASK :bit1; + RESERVED2 :bit1; + DC_I2C_DDC3_HW_DONE_INT :bit1; + DC_I2C_DDC3_HW_DONE_ACK :bit1; + DC_I2C_DDC3_HW_DONE_MASK :bit1; + RESERVED3 :bit1; + DC_I2C_DDC4_HW_DONE_INT :bit1; + DC_I2C_DDC4_HW_DONE_ACK :bit1; + DC_I2C_DDC4_HW_DONE_MASK :bit1; + RESERVED4 :bit1; + DC_I2C_DDC5_HW_DONE_INT :bit1; + DC_I2C_DDC5_HW_DONE_ACK :bit1; + DC_I2C_DDC5_HW_DONE_MASK :bit1; + RESERVED5 :bit1; + DC_I2C_DDC6_HW_DONE_INT :bit1; + DC_I2C_DDC6_HW_DONE_ACK :bit1; + DC_I2C_DDC6_HW_DONE_MASK :bit1; + DC_I2C_DDCVGA_HW_DONE_INT :bit1; + DC_I2C_DDCVGA_HW_DONE_ACK :bit1; + DC_I2C_DDCVGA_HW_DONE_MASK:bit1; + RESERVED6 :bit2; + end; + + TDC_LUT_BLACK_OFFSET_BLUE=bitpacked record + DC_LUT_BLACK_OFFSET_BLUE:bit16; + RESERVED0 :bit16; + end; + + TDC_LUT_VGA_ACCESS_ENABLE=bitpacked record + DC_LUT_VGA_ACCESS_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TDC_LUT_WHITE_OFFSET_BLUE=bitpacked record + DC_LUT_WHITE_OFFSET_BLUE:bit16; + RESERVED0 :bit16; + end; + + TDISPCLK_FREQ_CHANGE_CNTL=bitpacked record + DISPCLK_STEP_DELAY :bit14; + RESERVED0 :bit2; + DISPCLK_STEP_SIZE :bit4; + DISPCLK_FREQ_RAMP_DONE :bit1; + RESERVED1 :bit4; + DISPCLK_MAX_ERRDET_CYCLES :bit3; + DCCG_FIFO_ERRDET_RESET :bit1; + DCCG_FIFO_ERRDET_STATE :bit1; + DCCG_FIFO_ERRDET_OVR_EN :bit1; + DISPCLK_CHG_FWD_CORR_DISABLE:bit1; + end; + + TDMIF_ARBITRATION_CONTROL=bitpacked record + DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD:bit16; + PIPE_SWITCH_EFFICIENCY_WEIGHT :bit16; + end; + + TDPG_PIPE_STUTTER_CONTROL=bitpacked record + STUTTER_ENABLE :bit1; + RESERVED0 :bit3; + STUTTER_IGNORE_CURSOR :bit1; + STUTTER_IGNORE_ICON :bit1; + STUTTER_IGNORE_VGA :bit1; + STUTTER_IGNORE_FBC :bit1; + STUTTER_WM_HIGH_FORCE_ON :bit1; + STUTTER_WM_HIGH_EXCLUDES_VBLANK :bit1; + STUTTER_URGENT_IN_NOT_SELF_REFRESH :bit1; + STUTTER_SELF_REFRESH_FORCE_ON :bit1; + RESERVED1 :bit4; + STUTTER_EXIT_SELF_REFRESH_WATERMARK:bit16; + end; + + TDPG_PIPE_URGENCY_CONTROL=bitpacked record + URGENCY_LOW_WATERMARK :bit16; + URGENCY_HIGH_WATERMARK:bit16; + end; + + TFBC_CSM_REGION_OFFSET_01=bitpacked record + FBC_CSM_REGION_OFFSET_0:bit10; + RESERVED0 :bit6; + FBC_CSM_REGION_OFFSET_1:bit10; + RESERVED1 :bit6; + end; + + TFBC_CSM_REGION_OFFSET_23=bitpacked record + FBC_CSM_REGION_OFFSET_2:bit10; + RESERVED0 :bit6; + FBC_CSM_REGION_OFFSET_3:bit10; + RESERVED1 :bit6; + end; + + TFMT_CRC_SIG_BLUE_CONTROL=bitpacked record + FMT_CRC_SIG_BLUE :bit16; + FMT_CRC_SIG_CONTROL:bit16; + end; + + TGARLIC_COHE_VCE_RB_WPTR2=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + TGDS_PERFCOUNTER0_SELECT1=bitpacked record PERFCOUNTER_SELECT2:bit10; PERFCOUNTER_SELECT3:bit10; RESERVED0 :bit12; end; + TGPIOPAD_EXTERN_TRIG_CNTL=bitpacked record + EXTERN_TRIG_SEL :bit5; + EXTERN_TRIG_CLR :bit1; + EXTERN_TRIG_READ:bit1; + RESERVED0 :bit25; + end; + TGRBM_PERFCOUNTER0_SELECT=bitpacked record PERF_SEL :bit6; RESERVED0 :bit4; @@ -11834,6 +53604,416 @@ type RESERVED2 :bit3; end; + THDP_XDP_DIRECT2HDP_FIRST=bit32; + + TIMMEDIATE_COMMAND_STATUS=bitpacked record + IMMEDIATE_COMMAND_BUSY:bit1; + IMMEDIATE_RESULT_VALID:bit1; + RESERVED0 :bit30; + end; + + TINPUT_PAYLOAD_CAPABILITY=bitpacked record + INPUT_PAYLOAD_CAPABILITY:bit16; + RESERVED0 :bit16; + end; + + TLBV_KEYER_COLOR_REP_B_CB=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_B_CB:bit12; + RESERVED1 :bit16; + end; + + TLBV_KEYER_COLOR_REP_R_CR=bitpacked record + RESERVED0 :bit4; + LB_KEYER_COLOR_REP_R_CR:bit12; + RESERVED1 :bit16; + end; + + TLB_BUFFER_URGENCY_STATUS=bitpacked record + LB_BUFFER_URGENCY_LEVEL:bit12; + RESERVED0 :bit4; + LB_BUFFER_URGENCY_STAT :bit1; + RESERVED1 :bit15; + end; + + TLOW_POWER_TILING_CONTROL=bitpacked record + LOW_POWER_TILING_ENABLE :bit1; + RESERVED0 :bit2; + LOW_POWER_TILING_MODE :bit2; + LOW_POWER_TILING_NUM_PIPES :bit3; + LOW_POWER_TILING_NUM_BANKS :bit3; + LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE:bit1; + LOW_POWER_TILING_ROW_SIZE :bit3; + RESERVED1 :bit1; + LOW_POWER_TILING_ROWS_PER_CHAN :bit12; + RESERVED2 :bit4; + end; + + TMCIF_WB_TEST_DEBUG_INDEX=bitpacked record + MCIF_WB_TEST_DEBUG_INDEX :bit8; + MCIF_WB_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TMC_ARB_GRUB_PRIORITY1_RD=bitpacked record + CB0 :bit2; + CBCMASK0 :bit2; + CBFMASK0 :bit2; + DB0 :bit2; + DBHTILE0 :bit2; + DBSTEN0 :bit2; + TC0 :bit2; + ACPG :bit2; + ACPO :bit2; + DMIF :bit2; + DMIF_EXT0:bit2; + DMIF_EXT1:bit2; + DMIF_TW :bit2; + MCIF :bit2; + RLC :bit2; + VMC :bit2; + end; + + TMC_ARB_GRUB_PRIORITY1_WR=bitpacked record + CB0 :bit2; + CBCMASK0:bit2; + CBFMASK0:bit2; + CBIMMED0:bit2; + DB0 :bit2; + DBHTILE0:bit2; + DBSTEN0 :bit2; + TC0 :bit2; + SH :bit2; + ACPG :bit2; + ACPO :bit2; + MCIF :bit2; + RLC :bit2; + SDMA1 :bit2; + SMU :bit2; + VCE :bit2; + end; + + TMC_ARB_GRUB_PRIORITY2_RD=bitpacked record + SDMA1 :bit2; + SMU :bit2; + VCE :bit2; + RESERVED0:bit2; + XDMAM :bit2; + SDMA0 :bit2; + HDP :bit2; + UMC :bit2; + UVD :bit2; + UVD_EXT0 :bit2; + UVD_EXT1 :bit2; + SEM :bit2; + SAMMSP :bit2; + VP8 :bit2; + ISP :bit2; + RSV2 :bit2; + end; + + TMC_ARB_GRUB_PRIORITY2_WR=bitpacked record + RESERVED0:bit2; + SAMMSP :bit2; + XDMA :bit2; + XDMAM :bit2; + SDMA0 :bit2; + HDP :bit2; + UMC :bit2; + UVD :bit2; + UVD_EXT0 :bit2; + UVD_EXT1 :bit2; + XDP :bit2; + SEM :bit2; + IH :bit2; + VP8 :bit2; + ISP :bit2; + RESERVED1:bit2; + end; + + TMC_CITF_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_CITF_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_CITF_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_CITF_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_FUS_ARB_GARLIC_WR_PRI=bitpacked record + CB_WR_PRI :bit2; + DB_WR_PRI :bit2; + TC_WR_PRI :bit2; + CP_WR_PRI :bit2; + HDP_WR_PRI :bit2; + XDP_WR_PRI :bit2; + UMC_WR_PRI :bit2; + UVD_WR_PRI :bit2; + RLC_WR_PRI :bit2; + IH_WR_PRI :bit2; + SDMA_WR_PRI:bit2; + SEM_WR_PRI :bit2; + SH_WR_PRI :bit2; + MCIF_WR_PRI:bit2; + VCE_WR_PRI :bit2; + VCEU_WR_PRI:bit2; + end; + + TMC_GRUB_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_GRUB_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_GRUB_POST_PROBE_DELAY=bitpacked record + REQ_TO_RSP_DELAY :bit5; + RESERVED0 :bit3; + REQLCL_TO_RET_DELAY:bit5; + RESERVED1 :bit3; + REQREM_TO_RET_DELAY:bit5; + RESERVED2 :bit11; + end; + + TMC_HUB_RDREQ_BYPASS_GBL0=bitpacked record + ENABLE :bit1; + CID1 :bit8; + CID2 :bit8; + RESERVED0:bit15; + end; + + TMC_RPB_CID_QUEUE_EX_DATA=bitpacked record + WRITE_ENTRIES:bit16; + READ_ENTRIES :bit16; + end; + + TMC_RPB_PERF_COUNTER_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit2; + CLEAR_SELECTED_PERF_COUNTER:bit1; + CLEAR_ALL_PERF_COUNTERS :bit1; + STOP_ON_COUNTER_SATURATION :bit1; + ENABLE_PERF_COUNTERS :bit4; + PERF_COUNTER_ASSIGN_0 :bit5; + PERF_COUNTER_ASSIGN_1 :bit5; + PERF_COUNTER_ASSIGN_2 :bit5; + PERF_COUNTER_ASSIGN_3 :bit5; + RESERVED0 :bit3; + end; + + TMC_SEQ_TRAIN_WAKEUP_CNTL=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + AUTO_REFRESH_WAKEUP_EARLY:bit1; + SW_WAKEUP :bit1; + BLOCK_ARB_RD_D0 :bit1; + BLOCK_ARB_RD_D1 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + BLOCK_ARB_WR_D0 :bit1; + BLOCK_ARB_WR_D1 :bit1; + RESERVED8 :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + TRAIN_DONE_D0 :bit1; + TRAIN_DONE_D1 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit8; + end; + + TMC_SEQ_TRAIN_WAKEUP_EDGE=bitpacked record + D0_IDLEH_WAKEUP :bit1; + D1_IDLEH_WAKEUP :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + SCLK_SRBM_READY_WAKEUP:bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + SOFTWARE_WAKEUP :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + TIMER_DONE_WAKEUP :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit1; + RESERVED22 :bit1; + RESERVED23 :bit4; + end; + + TMC_SEQ_TRAIN_WAKEUP_MASK=bitpacked record + D0_IDLEH_WAKEUP :bit1; + D1_IDLEH_WAKEUP :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + SCLK_SRBM_READY_WAKEUP:bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + SOFTWARE_WAKEUP :bit1; + RESERVED9 :bit1; + RESERVED10 :bit1; + TIMER_DONE_WAKEUP :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit1; + RESERVED22 :bit1; + RESERVED23 :bit4; + end; + + TMC_SHARED_VIRT_RESET_REQ=bitpacked record + VF :bit16; + RESERVED0:bit15; + PF :bit1; + end; + + TMC_VM_FB_SIZE_OFFSET_VF0=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF1=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF2=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF3=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF4=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF5=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF6=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF7=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF8=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF9=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_XBAR_RDREQ_PRI_CREDIT=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMVP_FLIP_LINE_NUM_INSERT=bitpacked record + MVP_FLIP_LINE_NUM_INSERT_MODE:bit2; + RESERVED0 :bit6; + MVP_FLIP_LINE_NUM_INSERT :bit15; + RESERVED1 :bit1; + MVP_FLIP_LINE_NUM_OFFSET :bit6; + MVP_FLIP_AUTO_ENABLE :bit1; + RESERVED2 :bit1; + end; + + TOVL_SURFACE_ADDRESS_HIGH=bitpacked record + OVL_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + TPA_SC_FORCE_EOV_MAX_CNTS=bitpacked record FORCE_EOV_MAX_CLK_CNT:bit16; FORCE_EOV_MAX_REZ_CNT:bit16; @@ -12017,6 +54197,522 @@ type RESERVED0 :bit8; end; + TPB0_PIF_CMD_BUS_GLB_OVRD=bitpacked record + TXMARG_OVRD_EN :bit1; + DEEMPH_OVRD_EN :bit1; + PLLFREQ_OVRD_EN :bit1; + TXMARG :bit3; + DEEMPH :bit1; + PLLFREQ :bit2; + RESPONSEMODE_PIF_OVRD:bit1; + RESERVED0 :bit6; + CMD_BUS_LANE_DIS_0 :bit1; + CMD_BUS_LANE_DIS_1 :bit1; + CMD_BUS_LANE_DIS_2 :bit1; + CMD_BUS_LANE_DIS_3 :bit1; + CMD_BUS_LANE_DIS_4 :bit1; + CMD_BUS_LANE_DIS_5 :bit1; + CMD_BUS_LANE_DIS_6 :bit1; + CMD_BUS_LANE_DIS_7 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + end; + + TPB0_PLL_RO_GLB_CTRL_REG0=bitpacked record + PLL_TST_LOSPDTST_SRC :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1; + PLL_RO_PWRON_LUT_ENTRY_LS2 :bit1; + PLL_LC_PWRON_LUT_ENTRY_LS2 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1; + PLL_RO_HSCLK_LEFT_EN_GATING_EN :bit1; + PLL_RO_HSCLK_RIGHT_EN_GATING_EN :bit1; + PLL_LC_HSCLK_LEFT_EN_GATING_EN :bit1; + PLL_LC_HSCLK_RIGHT_EN_GATING_EN :bit1; + RESERVED0 :bit13; + end; + + TPB1_PIF_CMD_BUS_GLB_OVRD=bitpacked record + TXMARG_OVRD_EN :bit1; + DEEMPH_OVRD_EN :bit1; + PLLFREQ_OVRD_EN :bit1; + TXMARG :bit3; + DEEMPH :bit1; + PLLFREQ :bit2; + RESPONSEMODE_PIF_OVRD:bit1; + RESERVED0 :bit6; + CMD_BUS_LANE_DIS_0 :bit1; + CMD_BUS_LANE_DIS_1 :bit1; + CMD_BUS_LANE_DIS_2 :bit1; + CMD_BUS_LANE_DIS_3 :bit1; + CMD_BUS_LANE_DIS_4 :bit1; + CMD_BUS_LANE_DIS_5 :bit1; + CMD_BUS_LANE_DIS_6 :bit1; + CMD_BUS_LANE_DIS_7 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + end; + + TPB1_PLL_RO_GLB_CTRL_REG0=bitpacked record + PLL_TST_LOSPDTST_SRC :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1; + PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1; + PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1; + PLL_RO_PWRON_LUT_ENTRY_LS2 :bit1; + PLL_LC_PWRON_LUT_ENTRY_LS2 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1 :bit1; + PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2 :bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0:bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1:bit1; + PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2:bit1; + PLL_RO_HSCLK_LEFT_EN_GATING_EN :bit1; + PLL_RO_HSCLK_RIGHT_EN_GATING_EN :bit1; + PLL_LC_HSCLK_LEFT_EN_GATING_EN :bit1; + PLL_LC_HSCLK_RIGHT_EN_GATING_EN :bit1; + RESERVED0 :bit13; + end; + + TPCIE_I2C_REG_ADDR_EXPAND=bitpacked record + I2C_REG_ADDR:bit17; + RESERVED0 :bit4; + RESERVED1 :bit4; + RESERVED2 :bit7; + end; + + TPCIE_LC_BEST_EQ_SETTINGS=bitpacked record + LC_BEST_PRESET :bit4; + LC_BEST_PRECURSOR :bit6; + LC_BEST_CURSOR :bit6; + LC_BEST_POSTCURSOR:bit6; + LC_BEST_FOM :bit8; + RESERVED0 :bit2; + end; + + TPCIE_PERF_CNTL_MST_C_CLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PERF_CNTL_MST_R_CLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PERF_CNTL_SLV_R_CLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_SRIOV_FUNC_DEP_LINK=bitpacked record + SRIOV_FUNC_DEP_LINK:bit8; + RESERVED0 :bit24; + end; + + TPCIE_TX_CREDITS_ADVT_CPL=bitpacked record + TX_CREDITS_ADVT_CPLD:bit12; + RESERVED0 :bit4; + TX_CREDITS_ADVT_CPLH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_CREDITS_INIT_CPL=bitpacked record + TX_CREDITS_INIT_CPLD:bit12; + RESERVED0 :bit4; + TX_CREDITS_INIT_CPLH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_REQUEST_NUM_CNTL=bitpacked record + RESERVED0 :bit6; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit6; + RESERVED4 :bit1; + RESERVED5 :bit1; + RESERVED6 :bit6; + RESERVED7 :bit1; + RESERVED8 :bit1; + TX_NUM_OUTSTANDING_NP :bit6; + TX_NUM_OUTSTANDING_NP_VC1_EN:bit1; + TX_NUM_OUTSTANDING_NP_EN :bit1; + end; + + TPCIE_UNCORR_ERR_SEVERITY=bitpacked record + RESERVED0 :bit4; + DLP_ERR_SEVERITY :bit1; + SURPDN_ERR_SEVERITY :bit1; + RESERVED1 :bit6; + PSN_ERR_SEVERITY :bit1; + FC_ERR_SEVERITY :bit1; + CPL_TIMEOUT_SEVERITY :bit1; + CPL_ABORT_ERR_SEVERITY :bit1; + UNEXP_CPL_SEVERITY :bit1; + RCV_OVFL_SEVERITY :bit1; + MAL_TLP_SEVERITY :bit1; + ECRC_ERR_SEVERITY :bit1; + UNSUPP_REQ_ERR_SEVERITY :bit1; + ACS_VIOLATION_SEVERITY :bit1; + UNCORR_INT_ERR_SEVERITY :bit1; + MC_BLOCKED_TLP_SEVERITY :bit1; + ATOMICOP_EGRESS_BLOCKED_SEVERITY:bit1; + TLP_PREFIX_BLOCKED_ERR_SEVERITY :bit1; + RESERVED2 :bit6; + end; + + TPCIE_VC0_RESOURCE_STATUS=bitpacked record + PORT_ARB_TABLE_STATUS :bit1; + VC_NEGOTIATION_PENDING:bit1; + RESERVED0 :bit30; + end; + + TPCIE_VC1_RESOURCE_STATUS=bitpacked record + PORT_ARB_TABLE_STATUS :bit1; + VC_NEGOTIATION_PENDING:bit1; + RESERVED0 :bit30; + end; + + TPCIE_VENDOR_SPECIFIC_HDR=bitpacked record + VSEC_ID :bit16; + VSEC_REV :bit4; + VSEC_LENGTH:bit12; + end; + + TPERFMON_TEST_DEBUG_INDEX=bitpacked record + PERFMON_TEST_DEBUG_INDEX :bit8; + PERFMON_TEST_DEBUG_WRITE_EN:bit1; + RESERVED0 :bit23; + end; + + TPLL_MACRO_CNTL_RESERVED0=bit32; + + TPLL_MACRO_CNTL_RESERVED1=bit32; + + TPLL_MACRO_CNTL_RESERVED2=bit32; + + TPLL_MACRO_CNTL_RESERVED3=bit32; + + TPLL_MACRO_CNTL_RESERVED4=bit32; + + TPLL_MACRO_CNTL_RESERVED5=bit32; + + TPLL_MACRO_CNTL_RESERVED6=bit32; + + TPLL_MACRO_CNTL_RESERVED7=bit32; + + TPLL_MACRO_CNTL_RESERVED8=bit32; + + TPLL_MACRO_CNTL_RESERVED9=bit32; + + TREFCLK_CGTT_BLK_CTRL_REG=bitpacked record + REFCLK_TURN_ON_DELAY :bit4; + REFCLK_TURN_OFF_DELAY:bit8; + RESERVED0 :bit20; + end; + + TREGAMMA_CNTLA_REGION_0_1=bitpacked record + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_2_3=bitpacked record + REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_4_5=bitpacked record + REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_6_7=bitpacked record + REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_8_9=bitpacked record + REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_SLOPE_CNTL=bitpacked record + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE:bit18; + RESERVED0 :bit14; + end; + + TREGAMMA_CNTLA_START_CNTL=bitpacked record + REGAMMA_CNTLA_EXP_REGION_START :bit18; + RESERVED0 :bit2; + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT:bit7; + RESERVED1 :bit5; + end; + + TREGAMMA_CNTLB_REGION_0_1=bitpacked record + REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_2_3=bitpacked record + REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_4_5=bitpacked record + REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_6_7=bitpacked record + REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_8_9=bitpacked record + REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_SLOPE_CNTL=bitpacked record + REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE:bit18; + RESERVED0 :bit14; + end; + + TREGAMMA_CNTLB_START_CNTL=bitpacked record + REGAMMA_CNTLB_EXP_REGION_START :bit18; + RESERVED0 :bit2; + REGAMMA_CNTLB_EXP_REGION_START_SEGMENT:bit7; + RESERVED1 :bit5; + end; + + TREG_ADAPT_pwregr_CONTROL=bitpacked record + ACCESS_MODE_pwregr:bit1; + RESERVED0 :bit31; + end; + + TREG_ADAPT_pwregt_CONTROL=bitpacked record + ACCESS_MODE_pwregt:bit1; + RESERVED0 :bit31; + end; + + TREMAP_HDP_MEM_FLUSH_CNTL=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TREMAP_HDP_REG_FLUSH_CNTL=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TRESPONSE_INTERRUPT_COUNT=bitpacked record + N_RESPONSE_INTERRUPT_COUNT:bit8; + RESERVED0 :bit24; + end; + + TRLC_GPU_CLOCK_32_RES_SEL=bitpacked record + RES_SEL :bit6; + RESERVED:bit26; + end; + + TRLC_GPU_IOV_RLC_RESPONSE=bit32; + + TRLC_GPU_IOV_SCRATCH_ADDR=bitpacked record + ADDR :bit9; + RESERVED:bit23; + end; + + TRLC_GPU_IOV_SCRATCH_DATA=bit32; + + TRLC_GPU_IOV_SDMA0_STATUS=bitpacked record + PREEMPTED:bit1; + RESERVED :bit7; + SAVED :bit1; + RESERVED1:bit3; + RESTORED :bit1; + RESERVED2:bit19; + end; + + TRLC_GPU_IOV_SDMA1_STATUS=bitpacked record + PREEMPTED:bit1; + RESERVED :bit7; + SAVED :bit1; + RESERVED1:bit3; + RESTORED :bit1; + RESERVED2:bit19; + end; + + TRLC_GPU_IOV_SMU_RESPONSE=bit32; + + TRLC_PG_ALWAYS_ON_CU_MASK=bit32; + + TSCLV_HORZ_FILTER_CONTROL=bitpacked record + RESERVED0 :bit8; + SCL_H_2TAP_HARDCODE_COEF_EN:bit1; + RESERVED1 :bit23; + end; + + TSCLV_VERT_FILTER_CONTROL=bitpacked record + RESERVED0 :bit8; + SCL_V_2TAP_HARDCODE_COEF_EN:bit1; + RESERVED1 :bit23; + end; + + TSCL_VERT_FILTER_INIT_BOT=bitpacked record + SCL_V_INIT_FRAC_BOT:bit24; + SCL_V_INIT_INT_BOT :bit3; + RESERVED0 :bit5; + end; + + TSDMA0_GFX_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSDMA0_RLC0_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSDMA0_RLC1_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSDMA1_GFX_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSDMA1_RLC0_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSDMA1_RLC1_IB_SUB_REMAIN=bitpacked record + SIZE :bit14; + RESERVED0:bit18; + end; + + TSEM_MAILBOX_CLIENTCONFIG=bitpacked record + CP_CLIENT0 :bit3; + CP_CLIENT1 :bit3; + CP_CLIENT2 :bit3; + CP_CLIENT3 :bit3; + SDMA_CLIENT0 :bit3; + UVD_CLIENT0 :bit3; + SDMA1_CLIENT0:bit3; + VCE_CLIENT0 :bit3; + RESERVED0 :bit8; + end; + TSPI_CSQ_WF_ACTIVE_STATUS=bit32; TSPI_PERFCOUNTER0_SELECT1=bitpacked record @@ -12048,6 +54744,21 @@ type RESERVED0:bit26; end; + TSPI_STATIC_THREAD_MGMT_1=bitpacked record + RESERVED0:bit16; + RESERVED1:bit16; + end; + + TSPI_STATIC_THREAD_MGMT_2=bitpacked record + RESERVED0:bit16; + RESERVED1:bit16; + end; + + TSPI_STATIC_THREAD_MGMT_3=bitpacked record + LSHS_CU_EN:bit16; + RESERVED0 :bit16; + end; + TSPI_WCL_PIPE_PERCENT_CS0=bitpacked record VALUE :bit7; RESERVED0:bit25; @@ -12147,6 +54858,48 @@ type INT_SENT:bit1; end; + TSPMI_FSM_RESET_TRIGGER_0=bitpacked record + FSM_RESET_TRIGGER:bit1; + RESERVED0 :bit31; + end; + + TSPMI_FSM_WRITE_TRIGGER_0=bitpacked record + FSM_WRITE_TRIGGER:bit1; + RESERVED0 :bit31; + end; + + TSQ_THREAD_TRACE_WORD_CMN=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + RESERVED0 :bit27; + end; + + TSRBM_CREDIT_RECOVER_CNTL=bitpacked record + CREDIT_RECOVER_TIME :bit12; + RESERVED0 :bit19; + CREDIT_RECOVER_ENABLE:bit1; + end; + + TSRBM_FIREWALL_ERROR_ADDR=bitpacked record + RESERVED0 :bit2; + ACCESS_ADDRESS :bit16; + RESERVED1 :bit1; + ACCESS_VF :bit1; + ACCESS_VFID :bit4; + RESERVED2 :bit7; + FIREWALL_VIOLATION:bit1; + end; + + TSRBM_PERFCOUNTER0_SELECT=bitpacked record + PERF_SEL :bit6; + RESERVED0:bit26; + end; + + TSRBM_PERFCOUNTER1_SELECT=bitpacked record + PERF_SEL :bit6; + RESERVED0:bit26; + end; + TTCA_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2 :bit10; PERF_SEL3 :bit10; @@ -12195,6 +54948,96 @@ type PERF_MODE2:bit4; end; + TUNP_GRPH_STEREOSYNC_FLIP=bitpacked record + GRPH_STEREOSYNC_FLIP_EN :bit1; + RESERVED0 :bit3; + GRPH_STEREOSYNC_FLIP_MODE :bit2; + RESERVED1 :bit2; + GRPH_STACK_INTERLACE_FLIP_EN :bit1; + RESERVED2 :bit3; + GRPH_STACK_INTERLACE_FLIP_MODE :bit2; + RESERVED3 :bit2; + GRPH_PRIMARY_SURFACE_PENDING :bit1; + GRPH_SECONDARY_SURFACE_PENDING :bit1; + GRPH_PRIMARY_BOTTOM_SURFACE_PENDING :bit1; + GRPH_SECONDARY_BOTTOM_SURFACE_PENDING:bit1; + RESERVED4 :bit8; + GRPH_STEREOSYNC_SELECT_DISABLE :bit1; + RESERVED5 :bit3; + end; + + TUVD_MIF_CURR_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TUVD_MIF_SCLR_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TUVD_UDEC_DBW_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + + TVGA_DEBUG_READBACK_INDEX=bitpacked record + VGA_DEBUG_READBACK_INDEX:bit8; + RESERVED0 :bit24; + end; + + TVGA_SURFACE_PITCH_SELECT=bitpacked record + VGA_SURFACE_PITCH_SELECT :bit2; + RESERVED0 :bit6; + VGA_SURFACE_HEIGHT_SELECT:bit2; + RESERVED1 :bit22; + end; + TVGT_DRAW_INIT_FIFO_DEPTH=bitpacked record DRAW_INIT_FIFO_DEPTH:bit6; RESERVED0 :bit26; @@ -12240,6 +55083,399 @@ type RESERVED0:bit22; end; + TVIEWPORT_START_SECONDARY=bitpacked record + VIEWPORT_Y_START_SECONDARY:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START_SECONDARY:bit14; + RESERVED1 :bit2; + end; + + TVM_DUMMY_PAGE_FAULT_ADDR=bitpacked record + DUMMY_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TVM_DUMMY_PAGE_FAULT_CNTL=bitpacked record + DUMMY_PAGE_FAULT_ENABLE :bit1; + DUMMY_PAGE_ADDRESS_LOGICAL:bit1; + DUMMY_PAGE_COMPARE_MASK :bit2; + RESERVED0 :bit28; + end; + + TWALL_CLOCK_COUNTER_ALIAS=bit32; + + TXDMA_AON_TEST_DEBUG_DATA=bit32; + + TXDMA_SLV_MEM_NACK_STATUS=bitpacked record + XDMA_SLV_MEM_NACK_TAG:bit16; + XDMA_SLV_MEM_NACK :bit2; + RESERVED0 :bit13; + XDMA_SLV_MEM_NACK_CLR:bit1; + end; + + TAFMT_AUDIO_PACKET_CONTROL=bitpacked record + AFMT_AUDIO_SAMPLE_SEND :bit1; + RESERVED0 :bit10; + AFMT_RESET_FIFO_WHEN_AUDIO_DIS :bit1; + AFMT_AUDIO_TEST_EN :bit1; + RESERVED1 :bit1; + AFMT_AUDIO_TEST_MODE :bit1; + RESERVED2 :bit8; + AFMT_AUDIO_FIFO_OVERFLOW_ACK :bit1; + AFMT_AUDIO_CHANNEL_SWAP :bit1; + RESERVED3 :bit1; + AFMT_60958_CS_UPDATE :bit1; + RESERVED4 :bit3; + AFMT_AZ_AUDIO_ENABLE_CHG_ACK :bit1; + AFMT_BLANK_TEST_DATA_ON_ENC_ENB:bit1; + end; + + TATC_ATS_DEFAULT_PAGE_CNTL=bitpacked record + SEND_DEFAULT_PAGE:bit1; + RESERVED0 :bit1; + DEFAULT_PAGE_HIGH:bit4; + RESERVED1 :bit26; + end; + + TATC_ATS_FAULT_STATUS_ADDR=bit32; + + TATC_ATS_FAULT_STATUS_INFO=bitpacked record + FAULT_TYPE :bit9; + RESERVED0 :bit1; + VMID :bit5; + EXTRA_INFO :bit1; + EXTRA_INFO2 :bit1; + INVALIDATION :bit1; + PAGE_REQUEST :bit1; + STATUS :bit5; + PAGE_ADDR_HIGH:bit4; + RESERVED1 :bit4; + end; + + TATC_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TATC_VM_APERTURE0_LOW_ADDR=bitpacked record + VIRTUAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TATC_VM_APERTURE1_LOW_ADDR=bitpacked record + VIRTUAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TAZALIA_CYCLIC_BUFFER_SYNC=bitpacked record + CYCLIC_BUFFER_SYNC_ENABLE:bit1; + RESERVED0 :bit31; + end; + + TBIF_FEATURES_CONTROL_MISC=bitpacked record + MST_BIF_REQ_EP_DIS :bit1; + SLV_BIF_CPL_EP_DIS :bit1; + BIF_SLV_REQ_EP_DIS :bit1; + BIF_MST_CPL_EP_DIS :bit1; + UR_PSN_PKT_REPORT_POISON_DIS :bit1; + POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS :bit1; + POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS:bit1; + PLL_SWITCH_IMPCTL_CAL_DONE_DIS :bit1; + IGNORE_BE_CHECK_GASKET_COMB_DIS :bit1; + MC_BIF_REQ_ID_ROUTING_DIS :bit1; + AZ_BIF_REQ_ID_ROUTING_DIS :bit1; + ATC_PRG_RESP_PASID_UR_EN :bit1; + BIF_RB_SET_OVERFLOW_EN :bit1; + ATOMIC_ERR_INT_DIS :bit1; + RESERVED0 :bit1; + BME_HDL_NONVIR_EN :bit1; + INIT_PFFLR_CRS_RET_DIS :bit1; + FLR_MST_PEND_CHK_DIS :bit1; + FLR_SLV_PEND_CHK_DIS :bit1; + SOFT_PF_FLR_UR_CFG_EN :bit1; + FLR_OSTD_UR_DIS :bit1; + FLR_OSTD_HDL_DIS :bit1; + FLR_NEWREQ_HDL_DIS :bit1; + FLR_CRS_CFG_DIS :bit1; + RESERVED1 :bit8; + end; + + TBIF_GPUIOV_VM_INIT_STATUS=bit32; + + TBL1_PWM_CURRENT_ABM_LEVEL=bitpacked record + BL1_PWM_CURRENT_ABM_LEVEL:bit17; + RESERVED0 :bit15; + end; + + TCC_GC_SHADER_ARRAY_CONFIG=bitpacked record + RESERVED0 :bit1; + DPFP_RATE :bit2; + SQC_BALANCE_DISABLE:bit1; + HALF_LDS :bit1; + RESERVED1 :bit11; + INACTIVE_CUS :bit16; + end; + + TCC_SYS_RB_BACKEND_DISABLE=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit15; + BACKEND_DISABLE:bit8; + RESERVED2 :bit8; + end; + + TCGTS_CU10_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU10_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU11_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU11_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU12_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU12_TA_SQC_CTRL_REG=bitpacked record + TA :bit7; + TA_OVERRIDE :bit1; + TA_BUSY_OVERRIDE :bit2; + TA_LS_OVERRIDE :bit1; + TA_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + SQC :bit7; + SQC_OVERRIDE :bit1; + SQC_BUSY_OVERRIDE :bit2; + SQC_LS_OVERRIDE :bit1; + SQC_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU12_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU13_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU13_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU14_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU14_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU15_LDS_SQ_CTRL_REG=bitpacked record + LDS :bit7; + LDS_OVERRIDE :bit1; + LDS_BUSY_OVERRIDE :bit2; + LDS_LS_OVERRIDE :bit1; + LDS_SIMDBUSY_OVERRIDE:bit1; + RESERVED0 :bit4; + SQ :bit7; + SQ_OVERRIDE :bit1; + SQ_BUSY_OVERRIDE :bit2; + SQ_LS_OVERRIDE :bit1; + SQ_SIMDBUSY_OVERRIDE :bit1; + RESERVED1 :bit4; + end; + + TCGTS_CU15_TD_TCP_CTRL_REG=bitpacked record + TD :bit7; + TD_OVERRIDE :bit1; + TD_BUSY_OVERRIDE :bit2; + TD_LS_OVERRIDE :bit1; + TD_SIMDBUSY_OVERRIDE :bit1; + RESERVED0 :bit4; + TCP :bit7; + TCP_OVERRIDE :bit1; + TCP_BUSY_OVERRIDE :bit2; + TCP_LS_OVERRIDE :bit1; + TCP_SIMDBUSY_OVERRIDE:bit1; + RESERVED1 :bit4; + end; + + TCG_SPLL_SPREAD_SPECTRUM_2=bitpacked record + CLKV :bit26; + RESERVED0:bit6; + end; + + TCHUB_ATC_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TCHUB_ATC_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TCOL_MAN_INPUT_CSC_CONTROL=bitpacked record + INPUT_CSC_MODE :bit2; + INPUT_CSC_INPUT_TYPE :bit2; + INPUT_CSC_CONVERSION_MODE:bit1; + RESERVED0 :bit27; + end; + + TCPLL_MACRO_CNTL_RESERVED0=bit32; + + TCPLL_MACRO_CNTL_RESERVED1=bit32; + + TCPLL_MACRO_CNTL_RESERVED2=bit32; + + TCPLL_MACRO_CNTL_RESERVED3=bit32; + + TCPLL_MACRO_CNTL_RESERVED4=bit32; + + TCPLL_MACRO_CNTL_RESERVED5=bit32; + + TCPLL_MACRO_CNTL_RESERVED6=bit32; + + TCPLL_MACRO_CNTL_RESERVED7=bit32; + + TCPLL_MACRO_CNTL_RESERVED8=bit32; + + TCPLL_MACRO_CNTL_RESERVED9=bit32; + TCP_DRAW_INDX_INDR_ADDR_HI=bitpacked record ADDR_HI :bit16; RESERVED0:bit16; @@ -12283,6 +55519,651 @@ type TCP_PFP_METADATA_BASE_ADDR=bit32; + TCRTC_3D_STRUCTURE_CONTROL=bitpacked record + CRTC_3D_STRUCTURE_EN :bit1; + RESERVED0 :bit3; + CRTC_3D_STRUCTURE_EN_DB :bit1; + RESERVED1 :bit3; + CRTC_3D_STRUCTURE_V_UPDATE_MODE :bit2; + RESERVED2 :bit2; + CRTC_3D_STRUCTURE_STEREO_SEL_OVR :bit1; + RESERVED3 :bit3; + CRTC_3D_STRUCTURE_F_COUNT_RESET :bit1; + CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING:bit1; + CRTC_3D_STRUCTURE_F_COUNT :bit2; + RESERVED4 :bit12; + end; + + TCRTC_ALLOW_STOP_OFF_V_CNT=bitpacked record + CRTC_ALLOW_STOP_OFF_V_CNT :bit8; + RESERVED0 :bit8; + CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT:bit1; + RESERVED1 :bit15; + end; + + TCRTC_BLANK_DATA_COLOR_EXT=bitpacked record + CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT:bit2; + RESERVED0 :bit6; + CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT:bit2; + RESERVED1 :bit6; + CRTC_BLANK_DATA_COLOR_RED_CR_EXT :bit2; + RESERVED2 :bit14; + end; + + TCRTC_FORCE_COUNT_NOW_CNTL=bitpacked record + CRTC_FORCE_COUNT_NOW_MODE :bit2; + RESERVED0 :bit2; + CRTC_FORCE_COUNT_NOW_CHECK :bit1; + RESERVED1 :bit3; + CRTC_FORCE_COUNT_NOW_TRIG_SEL:bit1; + RESERVED2 :bit7; + CRTC_FORCE_COUNT_NOW_OCCURRED:bit1; + RESERVED3 :bit7; + CRTC_FORCE_COUNT_NOW_CLEAR :bit1; + RESERVED4 :bit7; + end; + + TCRTC_PIXEL_DATA_READBACK0=bitpacked record + CRTC_PIXEL_DATA_BLUE_CB:bit12; + RESERVED0 :bit4; + CRTC_PIXEL_DATA_GREEN_Y:bit12; + RESERVED1 :bit4; + end; + + TCRTC_PIXEL_DATA_READBACK1=bitpacked record + CRTC_PIXEL_DATA_RED_CR:bit12; + RESERVED0 :bit20; + end; + + TCRTC_TEST_PATTERN_CONTROL=bitpacked record + CRTC_TEST_PATTERN_EN :bit1; + RESERVED0 :bit7; + CRTC_TEST_PATTERN_MODE :bit3; + RESERVED1 :bit5; + CRTC_TEST_PATTERN_DYNAMIC_RANGE:bit1; + RESERVED2 :bit7; + CRTC_TEST_PATTERN_COLOR_FORMAT :bit8; + end; + + TCRTC_VSYNC_NOM_INT_STATUS=bitpacked record + CRTC_VSYNC_NOM :bit1; + RESERVED0 :bit3; + CRTC_VSYNC_NOM_INT_CLEAR:bit1; + RESERVED1 :bit27; + end; + + TCSPRIV_THREAD_TRACE_EVENT=bitpacked record + EVENT_ID :bit5; + RESERVED0:bit27; + end; + + TCUR2_SURFACE_ADDRESS_HIGH=bitpacked record + CURSOR2_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TDAC_SYNC_TRISTATE_CONTROL=bitpacked record + DAC_HSYNCA_TRISTATE:bit1; + RESERVED0 :bit7; + DAC_VSYNCA_TRISTATE:bit1; + RESERVED1 :bit7; + DAC_SYNCA_TRISTATE :bit1; + RESERVED2 :bit15; + end; + + TDCFEV_DMIFV_CLOCK_CONTROL=bitpacked record + RESERVED0 :bit3; + DMIFV_SCLK_G_DMIFTRK_GATE_DIS :bit1; + DMIFV_DISPCLK_G_DMIFVL_GATE_DIS:bit1; + DMIFV_DISPCLK_G_DMIFVC_GATE_DIS:bit1; + DMIFV_SOFT_RESET :bit1; + RESERVED1 :bit17; + DMIFV_TEST_CLK_SEL :bit5; + RESERVED2 :bit2; + DMIFV_BUFFER_MODE :bit1; + end; + + TDCO_POWER_MANAGEMENT_CNTL=bitpacked record + PM_ASSERT_RESET:bit1; + RESERVED0 :bit7; + PM_ALL_BUSY_OFF:bit1; + RESERVED1 :bit23; + end; + + TDC_LUT_BLACK_OFFSET_GREEN=bitpacked record + DC_LUT_BLACK_OFFSET_GREEN:bit16; + RESERVED0 :bit16; + end; + + TDC_LUT_WHITE_OFFSET_GREEN=bitpacked record + DC_LUT_WHITE_OFFSET_GREEN:bit16; + RESERVED0 :bit16; + end; + + TDIG_DISPCLK_SWITCH_STATUS=bitpacked record + DIG_DISPCLK_SWITCH_ALLOWED :bit1; + RESERVED0 :bit3; + DIG_DISPCLK_SWITCH_ALLOWED_INT :bit1; + RESERVED1 :bit3; + DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK :bit1; + RESERVED2 :bit3; + DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK:bit1; + RESERVED3 :bit19; + end; + + TDISPCLK_CGTT_BLK_CTRL_REG=bitpacked record + DISPCLK_TURN_ON_DELAY :bit4; + DISPCLK_TURN_OFF_DELAY:bit8; + CGTT_DISPCLK_OVERRIDE :bit1; + RESERVED0 :bit19; + end; + + TDPHY_MACRO_CNTL_RESERVED0=bit32; + + TDPHY_MACRO_CNTL_RESERVED1=bit32; + + TDPHY_MACRO_CNTL_RESERVED2=bit32; + + TDPHY_MACRO_CNTL_RESERVED3=bit32; + + TDPHY_MACRO_CNTL_RESERVED4=bit32; + + TDPHY_MACRO_CNTL_RESERVED5=bit32; + + TDPHY_MACRO_CNTL_RESERVED6=bit32; + + TDPHY_MACRO_CNTL_RESERVED7=bit32; + + TDPHY_MACRO_CNTL_RESERVED8=bit32; + + TDPHY_MACRO_CNTL_RESERVED9=bit32; + + TDP_MSA_V_TIMING_OVERRIDE1=bitpacked record + DP_MSA_V_TIMING_OVERRIDE_EN:bit1; + RESERVED0 :bit3; + DP_MSA_V_TOTAL_OVERRIDE :bit14; + RESERVED1 :bit14; + end; + + TDP_MSA_V_TIMING_OVERRIDE2=bitpacked record + DP_MSA_V_BLANK_START_OVERRIDE:bit14; + RESERVED0 :bit2; + DP_MSA_V_BLANK_END_OVERRIDE :bit14; + RESERVED1 :bit2; + end; + + TFBC_IDLE_FORCE_CLEAR_MASK=bit32; + + TGARLIC_FLUSH_ADDR_START_0=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_1=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_2=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_3=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_4=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_5=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_6=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGARLIC_FLUSH_ADDR_START_7=bitpacked record + ENABLE :bit1; + MODE :bit1; + ADDR_START:bit30; + end; + + TGCK_ADFS_CLK_BYPASS_CNTL1=bitpacked record + ECLK_BYPASS_CNTL :bit3; + SCLK_BYPASS_CNTL :bit3; + LCLK_BYPASS_CNTL :bit3; + DCLK_BYPASS_CNTL :bit3; + VCLK_BYPASS_CNTL :bit3; + DISPCLK_BYPASS_CNTL :bit3; + DRREFCLK_BYPASS_CNTL:bit3; + ACLK_BYPASS_CNTL :bit3; + SAMCLK_BYPASS_CNTL :bit3; + ACLK_DIV_BYPASS_CNTL:bit3; + RESERVED0 :bit2; + end; + + TGENERIC_I2C_PIN_SELECTION=bitpacked record + GENERIC_I2C_SCL_PIN_SEL:bit7; + RESERVED0 :bit1; + GENERIC_I2C_SDA_PIN_SEL:bit7; + RESERVED1 :bit17; + end; + + THDMI_AUDIO_PACKET_CONTROL=bitpacked record + RESERVED0 :bit4; + HDMI_AUDIO_DELAY_EN :bit2; + RESERVED1 :bit2; + HDMI_AUDIO_SEND_MAX_PACKETS:bit1; + RESERVED2 :bit7; + HDMI_AUDIO_PACKETS_PER_LINE:bit5; + RESERVED3 :bit11; + end; + + TIH_DSM_MATCH_DATA_CONTROL=bitpacked record + VALUE :bit28; + RESERVED0:bit4; + end; + + TLBV_BUFFER_URGENCY_STATUS=bitpacked record + LB_BUFFER_URGENCY_LEVEL:bit12; + RESERVED0 :bit4; + LB_BUFFER_URGENCY_STAT :bit1; + RESERVED1 :bit15; + end; + + TMCARB_DRAM_TIMING_TABLE_1=bit32; + + TMCARB_DRAM_TIMING_TABLE_2=bit32; + + TMCARB_DRAM_TIMING_TABLE_3=bitpacked record + entries_0_0_padding_2 :bit8; + entries_0_0_padding_1 :bit8; + entries_0_0_padding_0 :bit8; + entries_0_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_4=bit32; + + TMCARB_DRAM_TIMING_TABLE_5=bit32; + + TMCARB_DRAM_TIMING_TABLE_6=bitpacked record + entries_0_1_padding_2 :bit8; + entries_0_1_padding_1 :bit8; + entries_0_1_padding_0 :bit8; + entries_0_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_7=bit32; + + TMCARB_DRAM_TIMING_TABLE_8=bit32; + + TMCARB_DRAM_TIMING_TABLE_9=bitpacked record + entries_0_2_padding_2 :bit8; + entries_0_2_padding_1 :bit8; + entries_0_2_padding_0 :bit8; + entries_0_2_McArbBurstTime:bit8; + end; + + TMCIF_WB_BUFMGR_CUR_LINE_R=bitpacked record + MCIF_WB_BUFMGR_CUR_LINE_R:bit13; + RESERVED0 :bit19; + end; + + TMCIF_WB_BUFMGR_SW_CONTROL=bitpacked record + MCIF_WB_BUFMGR_ENABLE :bit1; + MCIF_WB_BUF_DUALSIZE_REQ :bit1; + RESERVED0 :bit2; + MCIF_WB_BUFMGR_SW_INT_EN :bit1; + MCIF_WB_BUFMGR_SW_INT_ACK :bit1; + MCIF_WB_BUFMGR_SW_SLICE_INT_EN:bit1; + RESERVED1 :bit1; + MCIF_WB_BUFMGR_SW_LOCK :bit4; + RESERVED2 :bit4; + MCIF_WB_P_VMID :bit4; + RESERVED3 :bit12; + end; + + TMCIF_WB_URGENCY_WATERMARK=bitpacked record + MCIF_WB_CLIENT0_URGENCY_WATERMARK:bit16; + MCIF_WB_CLIENT1_URGENCY_WATERMARK:bit16; + end; + + TMC_ARB_HARSH_BWPERIOD0_RD=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_BWPERIOD0_WR=bitpacked record + GROUP0:bit8; + GROUP1:bit8; + GROUP2:bit8; + GROUP3:bit8; + end; + + TMC_ARB_HARSH_BWPERIOD1_RD=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_ARB_HARSH_BWPERIOD1_WR=bitpacked record + GROUP4:bit8; + GROUP5:bit8; + GROUP6:bit8; + GROUP7:bit8; + end; + + TMC_FUS_ARB_GARLIC_WR_PRI2=bitpacked record + SMU_WR_PRI:bit2; + SAM_WR_PRI:bit2; + ACP_WR_PRI:bit2; + RESERVED0 :bit26; + end; + + TMC_MCBVM_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCBVM_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCBVM_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCBVM_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCDVM_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCDVM_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCDVM_PERFCOUNTER2_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_MCDVM_PERFCOUNTER3_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_SEQ_TRAIN_WAKEUP_CLEAR=bitpacked record + D0_IDLEH_WAKEUP :bit1; + D1_IDLEH_WAKEUP :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit1; + RESERVED5 :bit1; + SCLK_SRBM_READY_WAKEUP:bit1; + RESERVED6 :bit1; + RESERVED7 :bit1; + RESERVED8 :bit1; + SOFTWARE_WAKEUP :bit1; + RESERVED9 :bit2; + TIMER_DONE_WAKEUP :bit1; + CLEARALL :bit1; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit1; + RESERVED13 :bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit1; + RESERVED18 :bit1; + RESERVED19 :bit1; + RESERVED20 :bit1; + RESERVED21 :bit4; + end; + + TMC_VM_FB_SIZE_OFFSET_VF10=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF11=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF12=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF13=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF14=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_FB_SIZE_OFFSET_VF15=bitpacked record + VF_FB_SIZE :bit16; + VF_FB_OFFSET:bit16; + end; + + TMC_VM_L2_PERFCOUNTER0_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_VM_L2_PERFCOUNTER1_CFG=bitpacked record + PERF_SEL :bit8; + PERF_SEL_END:bit8; + RESERVED0 :bit8; + PERF_MODE :bit4; + ENABLE :bit1; + CLEAR :bit1; + RESERVED1 :bit2; + end; + + TMC_XBAR_FIFO_MON_MAX_THSH=bitpacked record + MON0:bit8; + MON1:bit8; + MON2:bit8; + MON3:bit8; + end; + + TMC_XBAR_RDRET_PRI_CREDIT1=bitpacked record + OUT0:bit8; + OUT1:bit8; + OUT2:bit8; + OUT3:bit8; + end; + + TMC_XBAR_RDRET_PRI_CREDIT2=bitpacked record + OUT4 :bit8; + OUT5 :bit8; + RESERVED0:bit16; + end; + + TMC_XPB_XDMA_PEER_SYS_BAR0=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_XDMA_PEER_SYS_BAR1=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_XDMA_PEER_SYS_BAR2=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_XDMA_PEER_SYS_BAR3=bitpacked record + VALID :bit1; + SIDE_OK :bit1; + ADDR :bit25; + RESERVED0:bit5; + end; + + TMC_XPB_XDMA_RTR_DEST_MAP0=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_XDMA_RTR_DEST_MAP1=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_XDMA_RTR_DEST_MAP2=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMC_XPB_XDMA_RTR_DEST_MAP3=bitpacked record + NMR :bit1; + DEST_OFFSET :bit19; + DEST_SEL :bit4; + DEST_SEL_RPB:bit1; + SIDE_OK :bit1; + APRTR_SIZE :bit5; + RESERVED0 :bit1; + end; + + TMICROSECOND_TIME_BASE_DIV=bitpacked record + MICROSECOND_TIME_BASE_DIV :bit7; + RESERVED0 :bit1; + XTAL_REF_DIV :bit7; + RESERVED1 :bit1; + XTAL_REF_SEL :bit1; + XTAL_REF_CLOCK_SOURCE_SEL :bit1; + RESERVED2 :bit2; + MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL:bit1; + RESERVED3 :bit3; + RESERVED4 :bit1; + RESERVED5 :bit3; + RESERVED6 :bit1; + RESERVED7 :bit3; + end; + + TMILLISECOND_TIME_BASE_DIV=bitpacked record + MILLISECOND_TIME_BASE_DIV :bit17; + RESERVED0 :bit3; + MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL:bit1; + RESERVED1 :bit11; + end; + + TMVP_CRC_RESULT_BLUE_GREEN=bitpacked record + MVP_CRC_BLUE_RESULT :bit16; + MVP_CRC_GREEN_RESULT:bit16; + end; + + TOUTPUT_PAYLOAD_CAPABILITY=bitpacked record + OUTPUT_PAYLOAD_CAPABILITY:bit16; + RESERVED0 :bit16; + end; + + TOVL_SURFACE_ADDRESS_INUSE=bitpacked record + RESERVED0 :bit8; + OVL_SURFACE_ADDRESS_INUSE:bit24; + end; + TPA_SC_CENTROID_PRIORITY_0=bitpacked record DISTANCE_0:bit4; DISTANCE_1:bit4; @@ -12464,6 +56345,386 @@ type RESERVED1:bit8; end; + TPB0_DFT_JIT_INJ_STAT_REG0=bitpacked record + DFT_STAT_DECR :bit8; + DFT_STAT_INCR :bit8; + DFT_STAT_FINISHED:bit1; + RESERVED0 :bit15; + end; + + TPB0_TX_GLB_LANE_SKEW_CTRL=bitpacked record + TX_CFG_GROUPX1_EN_0 :bit1; + TX_CFG_GROUPX1_EN_1 :bit1; + TX_CFG_GROUPX1_EN_2 :bit1; + TX_CFG_GROUPX1_EN_3 :bit1; + TX_CFG_GROUPX1_EN_4 :bit1; + TX_CFG_GROUPX1_EN_5 :bit1; + TX_CFG_GROUPX1_EN_6 :bit1; + TX_CFG_GROUPX1_EN_7 :bit1; + TX_CFG_GROUPX1_EN_8 :bit1; + TX_CFG_GROUPX1_EN_9 :bit1; + TX_CFG_GROUPX1_EN_10 :bit1; + TX_CFG_GROUPX1_EN_11 :bit1; + TX_CFG_GROUPX1_EN_12 :bit1; + TX_CFG_GROUPX1_EN_13 :bit1; + TX_CFG_GROUPX1_EN_14 :bit1; + TX_CFG_GROUPX1_EN_15 :bit1; + TX_CFG_GROUPX2_EN_L0T1 :bit1; + TX_CFG_GROUPX2_EN_L2T3 :bit1; + TX_CFG_GROUPX2_EN_L4T5 :bit1; + TX_CFG_GROUPX2_EN_L6T7 :bit1; + TX_CFG_GROUPX2_EN_L8T9 :bit1; + TX_CFG_GROUPX2_EN_L10T11:bit1; + TX_CFG_GROUPX2_EN_L12T13:bit1; + TX_CFG_GROUPX2_EN_L14T15:bit1; + TX_CFG_GROUPX4_EN_L0T3 :bit1; + TX_CFG_GROUPX4_EN_L4T7 :bit1; + TX_CFG_GROUPX4_EN_L8T11 :bit1; + TX_CFG_GROUPX4_EN_L12T15:bit1; + TX_CFG_GROUPX8_EN_L0T7 :bit1; + TX_CFG_GROUPX8_EN_L8T15 :bit1; + TX_CFG_GROUPX16_EN_L0T15:bit1; + RESERVED0 :bit1; + end; + + TPB1_DFT_JIT_INJ_STAT_REG0=bitpacked record + DFT_STAT_DECR :bit8; + DFT_STAT_INCR :bit8; + DFT_STAT_FINISHED:bit1; + RESERVED0 :bit15; + end; + + TPB1_TX_GLB_LANE_SKEW_CTRL=bitpacked record + TX_CFG_GROUPX1_EN_0 :bit1; + TX_CFG_GROUPX1_EN_1 :bit1; + TX_CFG_GROUPX1_EN_2 :bit1; + TX_CFG_GROUPX1_EN_3 :bit1; + TX_CFG_GROUPX1_EN_4 :bit1; + TX_CFG_GROUPX1_EN_5 :bit1; + TX_CFG_GROUPX1_EN_6 :bit1; + TX_CFG_GROUPX1_EN_7 :bit1; + TX_CFG_GROUPX1_EN_8 :bit1; + TX_CFG_GROUPX1_EN_9 :bit1; + TX_CFG_GROUPX1_EN_10 :bit1; + TX_CFG_GROUPX1_EN_11 :bit1; + TX_CFG_GROUPX1_EN_12 :bit1; + TX_CFG_GROUPX1_EN_13 :bit1; + TX_CFG_GROUPX1_EN_14 :bit1; + TX_CFG_GROUPX1_EN_15 :bit1; + TX_CFG_GROUPX2_EN_L0T1 :bit1; + TX_CFG_GROUPX2_EN_L2T3 :bit1; + TX_CFG_GROUPX2_EN_L4T5 :bit1; + TX_CFG_GROUPX2_EN_L6T7 :bit1; + TX_CFG_GROUPX2_EN_L8T9 :bit1; + TX_CFG_GROUPX2_EN_L10T11:bit1; + TX_CFG_GROUPX2_EN_L12T13:bit1; + TX_CFG_GROUPX2_EN_L14T15:bit1; + TX_CFG_GROUPX4_EN_L0T3 :bit1; + TX_CFG_GROUPX4_EN_L4T7 :bit1; + TX_CFG_GROUPX4_EN_L8T11 :bit1; + TX_CFG_GROUPX4_EN_L12T15:bit1; + TX_CFG_GROUPX8_EN_L0T7 :bit1; + TX_CFG_GROUPX8_EN_L8T15 :bit1; + TX_CFG_GROUPX16_EN_L0T15:bit1; + RESERVED0 :bit1; + end; + + TPCIE_RX_NUM_NAK_GENERATED=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_0=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_1=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_2=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_3=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_4=bit32; + + TPCIE_SRIOV_VF_BASE_ADDR_5=bit32; + + TPCIE_TX_ACK_LATENCY_LIMIT=bitpacked record + TX_ACK_LATENCY_LIMIT :bit12; + TX_ACK_LATENCY_LIMIT_OVERWRITE:bit1; + RESERVED0 :bit19; + end; + + TPIPE0_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPIPE1_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPIPE2_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPIPE3_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPIPE4_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPIPE5_DMIF_BUFFER_CONTROL=bitpacked record + DMIF_BUFFERS_ALLOCATED :bit3; + RESERVED0 :bit1; + DMIF_BUFFERS_ALLOCATION_COMPLETED:bit1; + RESERVED1 :bit27; + end; + + TPLL_MACRO_CNTL_RESERVED10=bit32; + + TPLL_MACRO_CNTL_RESERVED11=bit32; + + TPLL_MACRO_CNTL_RESERVED12=bit32; + + TPLL_MACRO_CNTL_RESERVED13=bit32; + + TPLL_MACRO_CNTL_RESERVED14=bit32; + + TPLL_MACRO_CNTL_RESERVED15=bit32; + + TPLL_MACRO_CNTL_RESERVED16=bit32; + + TPLL_MACRO_CNTL_RESERVED17=bit32; + + TPLL_MACRO_CNTL_RESERVED18=bit32; + + TPLL_MACRO_CNTL_RESERVED19=bit32; + + TPLL_MACRO_CNTL_RESERVED20=bit32; + + TPLL_MACRO_CNTL_RESERVED21=bit32; + + TPLL_MACRO_CNTL_RESERVED22=bit32; + + TPLL_MACRO_CNTL_RESERVED23=bit32; + + TPLL_MACRO_CNTL_RESERVED24=bit32; + + TPLL_MACRO_CNTL_RESERVED25=bit32; + + TPLL_MACRO_CNTL_RESERVED26=bit32; + + TPLL_MACRO_CNTL_RESERVED27=bit32; + + TPLL_MACRO_CNTL_RESERVED28=bit32; + + TPLL_MACRO_CNTL_RESERVED29=bit32; + + TPLL_MACRO_CNTL_RESERVED30=bit32; + + TPLL_MACRO_CNTL_RESERVED31=bit32; + + TPLL_MACRO_CNTL_RESERVED32=bit32; + + TPLL_MACRO_CNTL_RESERVED33=bit32; + + TPLL_MACRO_CNTL_RESERVED34=bit32; + + TPLL_MACRO_CNTL_RESERVED35=bit32; + + TPLL_MACRO_CNTL_RESERVED36=bit32; + + TPLL_MACRO_CNTL_RESERVED37=bit32; + + TPLL_MACRO_CNTL_RESERVED38=bit32; + + TPLL_MACRO_CNTL_RESERVED39=bit32; + + TPLL_MACRO_CNTL_RESERVED40=bit32; + + TPLL_MACRO_CNTL_RESERVED41=bit32; + + TREGAMMA_LUT_WRITE_EN_MASK=bitpacked record + REGAMMA_LUT_WRITE_EN_MASK:bit3; + RESERVED0 :bit29; + end; + + TRLC_GPU_IOV_ACTIVE_FCN_ID=bitpacked record + VF_ID :bit4; + RESERVED:bit27; + PF_VF :bit1; + end; + + TRLC_SAVE_AND_RESTORE_BASE=bit32; + + TRLC_SERDES_CU_MASTER_BUSY=bit32; + + TRLC_SPM_PERFMON_RING_SIZE=bit32; + + TRLC_SPM_SEGMENT_THRESHOLD=bit32; + + TRLC_SRM_INDEX_CNTL_ADDR_0=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_1=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_2=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_3=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_4=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_5=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_6=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_ADDR_7=bitpacked record + ADDRESS :bit16; + RESERVED:bit16; + end; + + TRLC_SRM_INDEX_CNTL_DATA_0=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_1=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_2=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_3=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_4=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_5=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_6=bit32; + + TRLC_SRM_INDEX_CNTL_DATA_7=bit32; + + TSCLK_DEEP_SLEEP_MISC_CNTL=bitpacked record + DPM_DS_DIV_ID:bit3; + DPM_SS_DIV_ID:bit3; + RESERVED0 :bit10; + OCP_ENABLE :bit1; + OCP_DS_DIV_ID:bit3; + OCP_SS_DIV_ID:bit3; + RESERVED1 :bit9; + end; + + TSCLV_VERT_FILTER_INIT_BOT=bitpacked record + SCL_V_INIT_FRAC_BOT:bit24; + SCL_V_INIT_INT_BOT :bit3; + RESERVED0 :bit5; + end; + + TSDMA0_GFX_RB_RPTR_ADDR_HI=bit32; + + TSDMA0_GFX_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_PERFCOUNTER0_RESULT=bit32; + + TSDMA0_PERFCOUNTER1_RESULT=bit32; + + TSDMA0_RLC0_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSDMA0_RLC1_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSDMA1_GFX_RB_RPTR_ADDR_HI=bit32; + + TSDMA1_GFX_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_PERFCOUNTER0_RESULT=bit32; + + TSDMA1_PERFCOUNTER1_RESULT=bit32; + + TSDMA1_RLC0_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSDMA1_RLC1_CONTEXT_STATUS=bitpacked record + SELECTED :bit1; + RESERVED0 :bit1; + IDLE :bit1; + EXPIRED :bit1; + EXCEPTION :bit3; + CTXSW_ABLE :bit1; + CTXSW_READY :bit1; + PREEMPTED :bit1; + PREEMPT_DISABLE:bit1; + RESERVED1 :bit21; + end; + + TSMU_BIF_VDDGFX_PWR_STATUS=bitpacked record + VDDGFX_GFX_PWR_OFF:bit1; + RESERVED0 :bit31; + end; + TSPI_CSQ_WF_ACTIVE_COUNT_0=bitpacked record COUNT :bit11; RESERVED0:bit21; @@ -12783,6 +57044,46 @@ type SH1_MASK:bit16; end; + TSQ_THREAD_TRACE_WORD_INST=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + WAVE_ID :bit4; + SIMD_ID :bit2; + INST_TYPE :bit5; + RESERVED0 :bit16; + end; + + TSQ_THREAD_TRACE_WORD_MISC=bitpacked record + TOKEN_TYPE :bit4; + TIME_DELTA :bit8; + SH_ID :bit1; + MISC_TOKEN_TYPE:bit3; + RESERVED0 :bit16; + end; + + TSQ_THREAD_TRACE_WORD_TIME=bitpacked record + RESERVED0:bit4; + RESERVED1:bit10; + RESERVED2:bit1; + RESERVED3:bit1; + RESERVED4:bit16; + end; + + TSQ_THREAD_TRACE_WORD_WAVE=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + SH_ID :bit1; + CU_ID :bit4; + WAVE_ID :bit4; + SIMD_ID :bit2; + RESERVED0 :bit16; + end; + + TSYS_GRBM_GFX_INDEX_SELECT=bitpacked record + SYS_GRBM_GFX_INDEX_SEL:bit4; + RESERVED0 :bit28; + end; + TTCP_BUFFER_ADDR_HASH_CNTL=bitpacked record CHANNEL_BITS :bit3; RESERVED0 :bit5; @@ -12794,6 +57095,114 @@ type RESERVED3 :bit5; end; + TUNIPHYA_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYB_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYC_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYD_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYE_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYF_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNIPHYG_CHANNEL_XBAR_CNTL=bitpacked record + UNIPHY_CHANNEL0_XBAR_SOURCE:bit2; + RESERVED0 :bit6; + UNIPHY_CHANNEL1_XBAR_SOURCE:bit2; + RESERVED1 :bit6; + UNIPHY_CHANNEL2_XBAR_SOURCE:bit2; + RESERVED2 :bit6; + UNIPHY_CHANNEL3_XBAR_SOURCE:bit2; + RESERVED3 :bit2; + UNIPHY_LINK_ENABLE :bit1; + RESERVED4 :bit3; + end; + + TUNP_GRPH_INTERRUPT_STATUS=bitpacked record + GRPH_PFLIP_INT_OCCURRED:bit1; + RESERVED0 :bit7; + GRPH_PFLIP_INT_CLEAR :bit1; + RESERVED1 :bit23; + end; + + TVGA_DISPBUF1_SURFACE_ADDR=bitpacked record + VGA_DISPBUF1_SURFACE_ADDR:bit25; + RESERVED0 :bit7; + end; + + TVGA_DISPBUF2_SURFACE_ADDR=bitpacked record + VGA_DISPBUF2_SURFACE_ADDR:bit25; + RESERVED0 :bit7; + end; + TVGT_GROUP_VECT_0_FMT_CNTL=bitpacked record X_CONV :bit4; X_OFFSET:bit4; @@ -12837,6 +57246,328 @@ type TVGT_STRMOUT_BUFFER_SIZE_3=bit32; + TVM_PRT_APERTURE0_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE1_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE2_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE3_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TXDMA_AON_TEST_DEBUG_INDEX=bitpacked record + XDMA_AON_TEST_DEBUG_INDEX :bit8; + XDMA_AON_TEST_DEBUG_WRITE_EN:bit1; + XDMA_DEBUG_SEL :bit1; + XDMA_DEBUG_OUT_EN :bit1; + RESERVED0 :bit21; + end; + + TXDMA_MSTR_CACHE_BASE_ADDR=bit32; + + TXDMA_MSTR_CMD_URGENT_CNTL=bitpacked record + XDMA_MSTR_CMD_CLIENT_STALL:bit1; + RESERVED0 :bit7; + XDMA_MSTR_CMD_URGENT_LEVEL:bit4; + XDMA_MSTR_CMD_STALL_DELAY :bit4; + RESERVED1 :bit16; + end; + + TXDMA_MSTR_MEM_NACK_STATUS=bitpacked record + XDMA_MSTR_MEM_NACK_TAG:bit10; + RESERVED0 :bit2; + XDMA_MSTR_MEM_NACK :bit2; + RESERVED1 :bit2; + XDMA_MSTR_MEM_NACK_CLR:bit1; + RESERVED2 :bit15; + end; + + TXDMA_MSTR_MEM_URGENT_CNTL=bitpacked record + XDMA_MSTR_MEM_CLIENT_STALL:bit1; + RESERVED0 :bit3; + XDMA_MSTR_MEM_URGENT_LIMIT:bit4; + XDMA_MSTR_MEM_URGENT_LEVEL:bit4; + XDMA_MSTR_MEM_STALL_DELAY :bit4; + XDMA_MSTR_MEM_URGENT_TIMER:bit16; + end; + + TXDMA_MSTR_PERFMEAS_STATUS=bitpacked record + XDMA_MSTR_PERFMEAS_DATA :bit24; + XDMA_MSTR_PERFMEAS_INDEX :bit3; + RESERVED0 :bit3; + XDMA_MSTR_PERFMEAS_INDEX_MODE:bit2; + end; + + TXDMA_MSTR_VSYNC_GSL_CHECK=bitpacked record + XDMA_MSTR_VSYNC_GSL_CHECK_SEL :bit3; + RESERVED0 :bit5; + XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT:bit14; + RESERVED1 :bit10; + end; + + TXDMA_SLV_PCIE_NACK_STATUS=bitpacked record + XDMA_SLV_PCIE_NACK_TAG:bit10; + RESERVED0 :bit2; + XDMA_SLV_PCIE_NACK :bit2; + RESERVED1 :bit2; + XDMA_SLV_PCIE_NACK_CLR:bit1; + RESERVED2 :bit15; + end; + + TXDMA_SLV_RDRET_BUF_STATUS=bitpacked record + XDMA_SLV_RDRET_FREE_ENTRIES:bit10; + RESERVED0 :bit2; + XDMA_SLV_RDRET_BUF_SIZE :bit10; + XDMA_SLV_RDRET_PG_STATE :bit2; + XDMA_SLV_RDRET_PG_TRANS :bit1; + RESERVED1 :bit7; + end; + + TXDMA_SLV_READ_LATENCY_AVE=bitpacked record + XDMA_SLV_READ_LATENCY_ACC :bit20; + XDMA_SLV_READ_LATENCY_COUNT:bit12; + end; + + TXDMA_SLV_READ_URGENT_CNTL=bitpacked record + XDMA_SLV_READ_CLIENT_STALL:bit1; + RESERVED0 :bit3; + XDMA_SLV_READ_URGENT_LIMIT:bit4; + XDMA_SLV_READ_URGENT_LEVEL:bit4; + XDMA_SLV_READ_STALL_DELAY :bit4; + XDMA_SLV_READ_URGENT_TIMER:bit16; + end; + + TAFMT_AUDIO_PACKET_CONTROL2=bitpacked record + AFMT_AUDIO_LAYOUT_OVRD :bit1; + AFMT_AUDIO_LAYOUT_SELECT :bit1; + RESERVED0 :bit6; + AFMT_AUDIO_CHANNEL_ENABLE:bit8; + AFMT_DP_AUDIO_STREAM_ID :bit8; + AFMT_HBR_ENABLE_OVRD :bit1; + RESERVED1 :bit3; + AFMT_60958_OSF_OVRD :bit1; + RESERVED2 :bit3; + end; + + TATC_ATS_FAULT_STATUS_INFO2=bitpacked record + VF :bit1; + VFID :bit5; + RESERVED0:bit3; + L1_ID :bit8; + RESERVED1:bit15; + end; + + TATC_VM_APERTURE0_HIGH_ADDR=bitpacked record + VIRTUAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TATC_VM_APERTURE1_HIGH_ADDR=bitpacked record + VIRTUAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TAUX_GTC_SYNC_ERROR_CONTROL=bitpacked record + AUX_GTC_POTENTIAL_ERROR_THRESHOLD :bit5; + RESERVED0 :bit3; + AUX_GTC_DEFINITE_ERROR_THRESHOLD :bit5; + RESERVED1 :bit3; + AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN :bit2; + RESERVED2 :bit2; + AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT:bit2; + RESERVED3 :bit10; + end; + + TAZALIA_GLOBAL_CAPABILITIES=bitpacked record + RESERVED0 :bit1; + NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS:bit2; + RESERVED1 :bit29; + end; + + TAZALIA_INPUT_CRC0_CHANNEL0=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL1=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL2=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL3=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL4=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL5=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL6=bit32; + + TAZALIA_INPUT_CRC0_CHANNEL7=bit32; + + TAZALIA_INPUT_CRC0_CONTROL0=bitpacked record + INPUT_CRC_EN :bit1; + RESERVED0 :bit3; + INPUT_CRC_BLOCK_MODE :bit1; + RESERVED1 :bit3; + INPUT_CRC_INSTANCE_SEL:bit3; + RESERVED2 :bit21; + end; + + TAZALIA_INPUT_CRC0_CONTROL1=bit32; + + TAZALIA_INPUT_CRC0_CONTROL2=bitpacked record + INPUT_CRC_BLOCK_ITERATION:bit16; + RESERVED0 :bit16; + end; + + TAZALIA_INPUT_CRC0_CONTROL3=bitpacked record + INPUT_CRC_COMPLETE :bit1; + RESERVED0 :bit3; + INPUT_CRC_BLOCK_COMPLETE_PHASE:bit1; + RESERVED1 :bit3; + INPUT_CRC_CHANNEL_RESULT_SEL :bit3; + RESERVED2 :bit21; + end; + + TAZALIA_INPUT_CRC1_CHANNEL0=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL1=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL2=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL3=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL4=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL5=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL6=bit32; + + TAZALIA_INPUT_CRC1_CHANNEL7=bit32; + + TAZALIA_INPUT_CRC1_CONTROL0=bitpacked record + INPUT_CRC_EN :bit1; + RESERVED0 :bit3; + INPUT_CRC_BLOCK_MODE :bit1; + RESERVED1 :bit3; + INPUT_CRC_INSTANCE_SEL:bit3; + RESERVED2 :bit21; + end; + + TAZALIA_INPUT_CRC1_CONTROL1=bit32; + + TAZALIA_INPUT_CRC1_CONTROL2=bitpacked record + INPUT_CRC_BLOCK_ITERATION:bit16; + RESERVED0 :bit16; + end; + + TAZALIA_INPUT_CRC1_CONTROL3=bitpacked record + INPUT_CRC_COMPLETE :bit1; + RESERVED0 :bit3; + INPUT_CRC_BLOCK_COMPLETE_PHASE:bit1; + RESERVED1 :bit3; + INPUT_CRC_CHANNEL_RESULT_SEL :bit3; + RESERVED2 :bit21; + end; + + TAZALIA_RIRB_AND_DP_CONTROL=bitpacked record + RIRB_NON_SNOOP :bit1; + RESERVED0 :bit3; + DP_DMA_NON_SNOOP :bit1; + DP_UPDATE_FREQ_DIVIDER:bit4; + RESERVED1 :bit23; + end; + + TBL1_PWM_MINIMUM_DUTY_CYCLE=bitpacked record + BL1_PWM_MINIMUM_DUTY_CYCLE:bit17; + RESERVED0 :bit15; + end; + + TCG_STATIC_SCREEN_PARAMETER=bitpacked record + STATIC_SCREEN_THRESHOLD :bit16; + STATIC_SCREEN_THRESHOLD_UNIT:bit4; + RESERVED0 :bit12; + end; + + TCOL_MAN_FP_CONVERTED_FIELD=bitpacked record + COL_MAN_FP_CONVERTED_FIELD_DATA :bit18; + RESERVED0 :bit2; + COL_MAN_FP_CONVERTED_FIELD_INDEX:bit6; + RESERVED1 :bit6; + end; + + TCOL_MAN_OUTPUT_CSC_CONTROL=bitpacked record + OUTPUT_CSC_MODE:bit3; + RESERVED0 :bit29; + end; + + TCOMM_MATRIXA_TRANS_C11_C12=bitpacked record + COMM_MATRIXA_TRANS_C11:bit16; + COMM_MATRIXA_TRANS_C12:bit16; + end; + + TCOMM_MATRIXA_TRANS_C13_C14=bitpacked record + COMM_MATRIXA_TRANS_C13:bit16; + COMM_MATRIXA_TRANS_C14:bit16; + end; + + TCOMM_MATRIXA_TRANS_C21_C22=bitpacked record + COMM_MATRIXA_TRANS_C21:bit16; + COMM_MATRIXA_TRANS_C22:bit16; + end; + + TCOMM_MATRIXA_TRANS_C23_C24=bitpacked record + COMM_MATRIXA_TRANS_C23:bit16; + COMM_MATRIXA_TRANS_C24:bit16; + end; + + TCOMM_MATRIXA_TRANS_C31_C32=bitpacked record + COMM_MATRIXA_TRANS_C31:bit16; + COMM_MATRIXA_TRANS_C32:bit16; + end; + + TCOMM_MATRIXA_TRANS_C33_C34=bitpacked record + COMM_MATRIXA_TRANS_C33:bit16; + COMM_MATRIXA_TRANS_C34:bit16; + end; + + TCOMM_MATRIXB_TRANS_C11_C12=bitpacked record + COMM_MATRIXB_TRANS_C11:bit16; + COMM_MATRIXB_TRANS_C12:bit16; + end; + + TCOMM_MATRIXB_TRANS_C13_C14=bitpacked record + COMM_MATRIXB_TRANS_C13:bit16; + COMM_MATRIXB_TRANS_C14:bit16; + end; + + TCOMM_MATRIXB_TRANS_C21_C22=bitpacked record + COMM_MATRIXB_TRANS_C21:bit16; + COMM_MATRIXB_TRANS_C22:bit16; + end; + + TCOMM_MATRIXB_TRANS_C23_C24=bitpacked record + COMM_MATRIXB_TRANS_C23:bit16; + COMM_MATRIXB_TRANS_C24:bit16; + end; + + TCOMM_MATRIXB_TRANS_C31_C32=bitpacked record + COMM_MATRIXB_TRANS_C31:bit16; + COMM_MATRIXB_TRANS_C32:bit16; + end; + + TCOMM_MATRIXB_TRANS_C33_C34=bitpacked record + COMM_MATRIXB_TRANS_C33:bit16; + COMM_MATRIXB_TRANS_C34:bit16; + end; + TCOMPUTE_DISPATCH_INITIATOR=bitpacked record COMPUTE_SHADER_EN :bit1; PARTIAL_TG_EN :bit1; @@ -12854,6 +57585,10 @@ type RESERVED1 :bit17; end; + TCPLL_MACRO_CNTL_RESERVED10=bit32; + + TCPLL_MACRO_CNTL_RESERVED11=bit32; + TCP_HQD_PQ_DOORBELL_CONTROL=bitpacked record DOORBELL_MODE :bit1; DOORBELL_BIF_DROP :bit1; @@ -12881,6 +57616,67 @@ type RESERVED0:bit16; end; + TCP_ME_GDS_ATOMIC0_PREOP_HI=bit32; + + TCP_ME_GDS_ATOMIC0_PREOP_LO=bit32; + + TCP_ME_GDS_ATOMIC1_PREOP_HI=bit32; + + TCP_ME_GDS_ATOMIC1_PREOP_LO=bit32; + + TCP_RB_DOORBELL_RANGE_LOWER=bitpacked record + RESERVED0 :bit2; + DOORBELL_RANGE_LOWER:bit21; + RESERVED1 :bit9; + end; + + TCP_RB_DOORBELL_RANGE_UPPER=bitpacked record + RESERVED0 :bit2; + DOORBELL_RANGE_UPPER:bit21; + RESERVED1 :bit9; + end; + + TCRTC_DOUBLE_BUFFER_CONTROL=bitpacked record + CRTC_UPDATE_PENDING :bit1; + RESERVED0 :bit7; + CRTC_UPDATE_INSTANTLY :bit1; + RESERVED1 :bit7; + CRTC_BLANK_DATA_DOUBLE_BUFFER_EN:bit1; + RESERVED2 :bit15; + end; + + TCRTC_STATIC_SCREEN_CONTROL=bitpacked record + CRTC_STATIC_SCREEN_EVENT_MASK :bit16; + CRTC_STATIC_SCREEN_FRAME_COUNT:bit8; + CRTC_CPU_SS_INT_ENABLE :bit1; + CRTC_SS_STATUS :bit1; + CRTC_CPU_SS_INT_STATUS :bit1; + CRTC_CPU_SS_INT_CLEAR :bit1; + CRTC_CPU_SS_INT_TYPE :bit1; + RESERVED0 :bit3; + end; + + TCRTC_STEREO_FORCE_NEXT_EYE=bitpacked record + CRTC_STEREO_FORCE_NEXT_EYE:bit2; + RESERVED0 :bit6; + CRTC_AVSYNC_FRAME_COUNTER :bit8; + CRTC_AVSYNC_LINE_COUNTER :bit13; + RESERVED1 :bit3; + end; + + TDAC_AUTODETECT_INT_CONTROL=bitpacked record + DAC_AUTODETECT_ACK :bit1; + RESERVED0 :bit15; + DAC_AUTODETECT_INT_ENABLE:bit1; + RESERVED1 :bit15; + end; + + TDBG_SMB_BYPASS_SRBM_ACCESS=bitpacked record + DBG_SMB_BYPASS_SRBM_EN:bit1; + RESERVED0 :bit4; + RESERVED1 :bit27; + end; + TDB_SRESULTS_COMPARE_STATE0=bitpacked record COMPAREFUNC0 :bit3; RESERVED0 :bit1; @@ -12901,6 +57697,731 @@ type RESERVED2 :bit7; end; + TDCFEV_DMIFV_MEM_PWR_STATUS=bitpacked record + DMIFV_MEM_PWR_LUMA_0_STATE :bit2; + DMIFV_MEM_PWR_LUMA_1_STATE :bit2; + DMIFV_MEM_PWR_LUMA_2_STATE :bit2; + DMIFV_MEM_PWR_LUMA_3_STATE :bit2; + DMIFV_MEM_PWR_LUMA_4_STATE :bit2; + DMIFV_MEM_PWR_CHROMA_0_STATE:bit2; + DMIFV_MEM_PWR_CHROMA_1_STATE:bit2; + DMIFV_MEM_PWR_CHROMA_2_STATE:bit2; + DMIFV_MEM_PWR_CHROMA_3_STATE:bit2; + DMIFV_MEM_PWR_CHROMA_4_STATE:bit2; + RESERVED0 :bit12; + end; + + TDCIO_GSL_SWAPLOCK_PAD_CNTL=bitpacked record + DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL:bit2; + RESERVED0 :bit2; + DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL :bit2; + RESERVED1 :bit2; + DCIO_SWAPLOCK_A_GSL_MASK :bit2; + RESERVED2 :bit6; + DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL:bit2; + RESERVED3 :bit2; + DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL :bit2; + RESERVED4 :bit2; + DCIO_SWAPLOCK_B_GSL_MASK :bit2; + RESERVED5 :bit6; + end; + + TDC_ABM1_ACE_OFFSET_SLOPE_0=bitpacked record + ABM1_ACE_SLOPE_0 :bit15; + RESERVED0 :bit1; + ABM1_ACE_OFFSET_0:bit11; + RESERVED1 :bit4; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_ACE_OFFSET_SLOPE_1=bitpacked record + ABM1_ACE_SLOPE_1 :bit15; + RESERVED0 :bit1; + ABM1_ACE_OFFSET_1:bit11; + RESERVED1 :bit4; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_ACE_OFFSET_SLOPE_2=bitpacked record + ABM1_ACE_SLOPE_2 :bit15; + RESERVED0 :bit1; + ABM1_ACE_OFFSET_2:bit11; + RESERVED1 :bit4; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_ACE_OFFSET_SLOPE_3=bitpacked record + ABM1_ACE_SLOPE_3 :bit15; + RESERVED0 :bit1; + ABM1_ACE_OFFSET_3:bit11; + RESERVED1 :bit4; + ABM1_ACE_LOCK :bit1; + end; + + TDC_ABM1_ACE_OFFSET_SLOPE_4=bitpacked record + ABM1_ACE_SLOPE_4 :bit15; + RESERVED0 :bit1; + ABM1_ACE_OFFSET_4:bit11; + RESERVED1 :bit4; + ABM1_ACE_LOCK :bit1; + end; + + TDC_MEM_GLOBAL_PWR_REQ_CNTL=bitpacked record + DC_MEM_GLOBAL_PWR_REQ_DIS:bit1; + RESERVED0 :bit31; + end; + + TDOUT_POWER_MANAGEMENT_CNTL=bitpacked record + RESERVED0 :bit1; + RESERVED1 :bit3; + RESERVED2 :bit1; + RESERVED3 :bit1; + RESERVED4 :bit2; + RESERVED5 :bit1; + RESERVED6 :bit1; + RESERVED7 :bit2; + RESERVED8 :bit1; + RESERVED9 :bit3; + RESERVED10 :bit1; + RESERVED11 :bit1; + RESERVED12 :bit2; + RESERVED13 :bit1; + PM_ASSERT_RESET:bit1; + RESERVED14 :bit1; + RESERVED15 :bit1; + RESERVED16 :bit1; + RESERVED17 :bit3; + RESERVED18 :bit4; + end; + + TDPG_WATERMARK_MASK_CONTROL=bitpacked record + STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK:bit2; + RESERVED0 :bit6; + URGENCY_WATERMARK_MASK :bit2; + RESERVED1 :bit6; + NB_PSTATE_CHANGE_WATERMARK_MASK :bit2; + RESERVED2 :bit14; + end; + + TDPHY_MACRO_CNTL_RESERVED10=bit32; + + TDPHY_MACRO_CNTL_RESERVED11=bit32; + + TDPHY_MACRO_CNTL_RESERVED12=bit32; + + TDPHY_MACRO_CNTL_RESERVED13=bit32; + + TDPHY_MACRO_CNTL_RESERVED14=bit32; + + TDPHY_MACRO_CNTL_RESERVED15=bit32; + + TDPHY_MACRO_CNTL_RESERVED16=bit32; + + TDPHY_MACRO_CNTL_RESERVED17=bit32; + + TDPHY_MACRO_CNTL_RESERVED18=bit32; + + TDPHY_MACRO_CNTL_RESERVED19=bit32; + + TDPHY_MACRO_CNTL_RESERVED20=bit32; + + TDPHY_MACRO_CNTL_RESERVED21=bit32; + + TDPHY_MACRO_CNTL_RESERVED22=bit32; + + TDPHY_MACRO_CNTL_RESERVED23=bit32; + + TDPHY_MACRO_CNTL_RESERVED24=bit32; + + TDPHY_MACRO_CNTL_RESERVED25=bit32; + + TDPHY_MACRO_CNTL_RESERVED26=bit32; + + TDPHY_MACRO_CNTL_RESERVED27=bit32; + + TDPHY_MACRO_CNTL_RESERVED28=bit32; + + TDPHY_MACRO_CNTL_RESERVED29=bit32; + + TDPHY_MACRO_CNTL_RESERVED30=bit32; + + TDPHY_MACRO_CNTL_RESERVED31=bit32; + + TDPHY_MACRO_CNTL_RESERVED32=bit32; + + TDPHY_MACRO_CNTL_RESERVED33=bit32; + + TDPHY_MACRO_CNTL_RESERVED34=bit32; + + TDPHY_MACRO_CNTL_RESERVED35=bit32; + + TDPHY_MACRO_CNTL_RESERVED36=bit32; + + TDPHY_MACRO_CNTL_RESERVED37=bit32; + + TDPHY_MACRO_CNTL_RESERVED38=bit32; + + TDPHY_MACRO_CNTL_RESERVED39=bit32; + + TDPHY_MACRO_CNTL_RESERVED40=bit32; + + TDPHY_MACRO_CNTL_RESERVED41=bit32; + + TDPHY_MACRO_CNTL_RESERVED42=bit32; + + TDPHY_MACRO_CNTL_RESERVED43=bit32; + + TDPHY_MACRO_CNTL_RESERVED44=bit32; + + TDPHY_MACRO_CNTL_RESERVED45=bit32; + + TDPHY_MACRO_CNTL_RESERVED46=bit32; + + TDPHY_MACRO_CNTL_RESERVED47=bit32; + + TDPHY_MACRO_CNTL_RESERVED48=bit32; + + TDPHY_MACRO_CNTL_RESERVED49=bit32; + + TDPHY_MACRO_CNTL_RESERVED50=bit32; + + TDPHY_MACRO_CNTL_RESERVED51=bit32; + + TDPHY_MACRO_CNTL_RESERVED52=bit32; + + TDPHY_MACRO_CNTL_RESERVED53=bit32; + + TDPHY_MACRO_CNTL_RESERVED54=bit32; + + TDPHY_MACRO_CNTL_RESERVED55=bit32; + + TDPHY_MACRO_CNTL_RESERVED56=bit32; + + TDPHY_MACRO_CNTL_RESERVED57=bit32; + + TDPHY_MACRO_CNTL_RESERVED58=bit32; + + TDPHY_MACRO_CNTL_RESERVED59=bit32; + + TDPHY_MACRO_CNTL_RESERVED60=bit32; + + TDPHY_MACRO_CNTL_RESERVED61=bit32; + + TDPHY_MACRO_CNTL_RESERVED62=bit32; + + TDPHY_MACRO_CNTL_RESERVED63=bit32; + + TDPREFCLK_CGTT_BLK_CTRL_REG=bitpacked record + DPREFCLK_TURN_ON_DELAY :bit4; + DPREFCLK_TURN_OFF_DELAY:bit8; + RESERVED0 :bit20; + end; + + TFMT_CRC_SIG_RED_GREEN_MASK=bitpacked record + FMT_CRC_SIG_RED_MASK :bit16; + FMT_CRC_SIG_GREEN_MASK:bit16; + end; + + TGAMMA_CORR_CNTLA_END_CNTL1=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION_END:bit16; + RESERVED0 :bit16; + end; + + TGAMMA_CORR_CNTLA_END_CNTL2=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE:bit16; + GAMMA_CORR_CNTLA_EXP_REGION_END_BASE :bit16; + end; + + TGAMMA_CORR_CNTLB_END_CNTL1=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION_END:bit16; + RESERVED0 :bit16; + end; + + TGAMMA_CORR_CNTLB_END_CNTL2=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE:bit16; + GAMMA_CORR_CNTLB_EXP_REGION_END_BASE :bit16; + end; + + TGC_USER_RB_BACKEND_DISABLE=bitpacked record + RESERVED0 :bit16; + BACKEND_DISABLE:bit8; + RESERVED1 :bit8; + end; + + TGC_USER_SHADER_RATE_CONFIG=bitpacked record + RESERVED0 :bit1; + DPFP_RATE :bit2; + SQC_BALANCE_DISABLE:bit1; + HALF_LDS :bit1; + RESERVED1 :bit27; + end; + + TGRPH_SURFACE_ADDRESS_INUSE=bitpacked record + RESERVED0 :bit8; + GRPH_SURFACE_ADDRESS_INUSE:bit24; + end; + + TIH_DSM_MATCH_FIELD_CONTROL=bitpacked record + SRC_EN :bit1; + FCNID_EN :bit1; + TIMESTAMP_EN:bit1; + RINGID_EN :bit1; + VMID_EN :bit1; + PASID_EN :bit1; + RESERVED0 :bit26; + end; + + TMCARB_DRAM_TIMING_TABLE_10=bit32; + + TMCARB_DRAM_TIMING_TABLE_11=bit32; + + TMCARB_DRAM_TIMING_TABLE_12=bitpacked record + entries_0_3_padding_2 :bit8; + entries_0_3_padding_1 :bit8; + entries_0_3_padding_0 :bit8; + entries_0_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_13=bit32; + + TMCARB_DRAM_TIMING_TABLE_14=bit32; + + TMCARB_DRAM_TIMING_TABLE_15=bitpacked record + entries_1_0_padding_2 :bit8; + entries_1_0_padding_1 :bit8; + entries_1_0_padding_0 :bit8; + entries_1_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_16=bit32; + + TMCARB_DRAM_TIMING_TABLE_17=bit32; + + TMCARB_DRAM_TIMING_TABLE_18=bitpacked record + entries_1_1_padding_2 :bit8; + entries_1_1_padding_1 :bit8; + entries_1_1_padding_0 :bit8; + entries_1_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_19=bit32; + + TMCARB_DRAM_TIMING_TABLE_20=bit32; + + TMCARB_DRAM_TIMING_TABLE_21=bitpacked record + entries_1_2_padding_2 :bit8; + entries_1_2_padding_1 :bit8; + entries_1_2_padding_0 :bit8; + entries_1_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_22=bit32; + + TMCARB_DRAM_TIMING_TABLE_23=bit32; + + TMCARB_DRAM_TIMING_TABLE_24=bitpacked record + entries_1_3_padding_2 :bit8; + entries_1_3_padding_1 :bit8; + entries_1_3_padding_0 :bit8; + entries_1_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_25=bit32; + + TMCARB_DRAM_TIMING_TABLE_26=bit32; + + TMCARB_DRAM_TIMING_TABLE_27=bitpacked record + entries_2_0_padding_2 :bit8; + entries_2_0_padding_1 :bit8; + entries_2_0_padding_0 :bit8; + entries_2_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_28=bit32; + + TMCARB_DRAM_TIMING_TABLE_29=bit32; + + TMCARB_DRAM_TIMING_TABLE_30=bitpacked record + entries_2_1_padding_2 :bit8; + entries_2_1_padding_1 :bit8; + entries_2_1_padding_0 :bit8; + entries_2_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_31=bit32; + + TMCARB_DRAM_TIMING_TABLE_32=bit32; + + TMCARB_DRAM_TIMING_TABLE_33=bitpacked record + entries_2_2_padding_2 :bit8; + entries_2_2_padding_1 :bit8; + entries_2_2_padding_0 :bit8; + entries_2_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_34=bit32; + + TMCARB_DRAM_TIMING_TABLE_35=bit32; + + TMCARB_DRAM_TIMING_TABLE_36=bitpacked record + entries_2_3_padding_2 :bit8; + entries_2_3_padding_1 :bit8; + entries_2_3_padding_0 :bit8; + entries_2_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_37=bit32; + + TMCARB_DRAM_TIMING_TABLE_38=bit32; + + TMCARB_DRAM_TIMING_TABLE_39=bitpacked record + entries_3_0_padding_2 :bit8; + entries_3_0_padding_1 :bit8; + entries_3_0_padding_0 :bit8; + entries_3_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_40=bit32; + + TMCARB_DRAM_TIMING_TABLE_41=bit32; + + TMCARB_DRAM_TIMING_TABLE_42=bitpacked record + entries_3_1_padding_2 :bit8; + entries_3_1_padding_1 :bit8; + entries_3_1_padding_0 :bit8; + entries_3_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_43=bit32; + + TMCARB_DRAM_TIMING_TABLE_44=bit32; + + TMCARB_DRAM_TIMING_TABLE_45=bitpacked record + entries_3_2_padding_2 :bit8; + entries_3_2_padding_1 :bit8; + entries_3_2_padding_0 :bit8; + entries_3_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_46=bit32; + + TMCARB_DRAM_TIMING_TABLE_47=bit32; + + TMCARB_DRAM_TIMING_TABLE_48=bitpacked record + entries_3_3_padding_2 :bit8; + entries_3_3_padding_1 :bit8; + entries_3_3_padding_0 :bit8; + entries_3_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_49=bit32; + + TMCARB_DRAM_TIMING_TABLE_50=bit32; + + TMCARB_DRAM_TIMING_TABLE_51=bitpacked record + entries_4_0_padding_2 :bit8; + entries_4_0_padding_1 :bit8; + entries_4_0_padding_0 :bit8; + entries_4_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_52=bit32; + + TMCARB_DRAM_TIMING_TABLE_53=bit32; + + TMCARB_DRAM_TIMING_TABLE_54=bitpacked record + entries_4_1_padding_2 :bit8; + entries_4_1_padding_1 :bit8; + entries_4_1_padding_0 :bit8; + entries_4_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_55=bit32; + + TMCARB_DRAM_TIMING_TABLE_56=bit32; + + TMCARB_DRAM_TIMING_TABLE_57=bitpacked record + entries_4_2_padding_2 :bit8; + entries_4_2_padding_1 :bit8; + entries_4_2_padding_0 :bit8; + entries_4_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_58=bit32; + + TMCARB_DRAM_TIMING_TABLE_59=bit32; + + TMCARB_DRAM_TIMING_TABLE_60=bitpacked record + entries_4_3_padding_2 :bit8; + entries_4_3_padding_1 :bit8; + entries_4_3_padding_0 :bit8; + entries_4_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_61=bit32; + + TMCARB_DRAM_TIMING_TABLE_62=bit32; + + TMCARB_DRAM_TIMING_TABLE_63=bitpacked record + entries_5_0_padding_2 :bit8; + entries_5_0_padding_1 :bit8; + entries_5_0_padding_0 :bit8; + entries_5_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_64=bit32; + + TMCARB_DRAM_TIMING_TABLE_65=bit32; + + TMCARB_DRAM_TIMING_TABLE_66=bitpacked record + entries_5_1_padding_2 :bit8; + entries_5_1_padding_1 :bit8; + entries_5_1_padding_0 :bit8; + entries_5_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_67=bit32; + + TMCARB_DRAM_TIMING_TABLE_68=bit32; + + TMCARB_DRAM_TIMING_TABLE_69=bitpacked record + entries_5_2_padding_2 :bit8; + entries_5_2_padding_1 :bit8; + entries_5_2_padding_0 :bit8; + entries_5_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_70=bit32; + + TMCARB_DRAM_TIMING_TABLE_71=bit32; + + TMCARB_DRAM_TIMING_TABLE_72=bitpacked record + entries_5_3_padding_2 :bit8; + entries_5_3_padding_1 :bit8; + entries_5_3_padding_0 :bit8; + entries_5_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_73=bit32; + + TMCARB_DRAM_TIMING_TABLE_74=bit32; + + TMCARB_DRAM_TIMING_TABLE_75=bitpacked record + entries_6_0_padding_2 :bit8; + entries_6_0_padding_1 :bit8; + entries_6_0_padding_0 :bit8; + entries_6_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_76=bit32; + + TMCARB_DRAM_TIMING_TABLE_77=bit32; + + TMCARB_DRAM_TIMING_TABLE_78=bitpacked record + entries_6_1_padding_2 :bit8; + entries_6_1_padding_1 :bit8; + entries_6_1_padding_0 :bit8; + entries_6_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_79=bit32; + + TMCARB_DRAM_TIMING_TABLE_80=bit32; + + TMCARB_DRAM_TIMING_TABLE_81=bitpacked record + entries_6_2_padding_2 :bit8; + entries_6_2_padding_1 :bit8; + entries_6_2_padding_0 :bit8; + entries_6_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_82=bit32; + + TMCARB_DRAM_TIMING_TABLE_83=bit32; + + TMCARB_DRAM_TIMING_TABLE_84=bitpacked record + entries_6_3_padding_2 :bit8; + entries_6_3_padding_1 :bit8; + entries_6_3_padding_0 :bit8; + entries_6_3_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_85=bit32; + + TMCARB_DRAM_TIMING_TABLE_86=bit32; + + TMCARB_DRAM_TIMING_TABLE_87=bitpacked record + entries_7_0_padding_2 :bit8; + entries_7_0_padding_1 :bit8; + entries_7_0_padding_0 :bit8; + entries_7_0_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_88=bit32; + + TMCARB_DRAM_TIMING_TABLE_89=bit32; + + TMCARB_DRAM_TIMING_TABLE_90=bitpacked record + entries_7_1_padding_2 :bit8; + entries_7_1_padding_1 :bit8; + entries_7_1_padding_0 :bit8; + entries_7_1_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_91=bit32; + + TMCARB_DRAM_TIMING_TABLE_92=bit32; + + TMCARB_DRAM_TIMING_TABLE_93=bitpacked record + entries_7_2_padding_2 :bit8; + entries_7_2_padding_1 :bit8; + entries_7_2_padding_0 :bit8; + entries_7_2_McArbBurstTime:bit8; + end; + + TMCARB_DRAM_TIMING_TABLE_94=bit32; + + TMCARB_DRAM_TIMING_TABLE_95=bit32; + + TMCARB_DRAM_TIMING_TABLE_96=bitpacked record + entries_7_3_padding_2 :bit8; + entries_7_3_padding_1 :bit8; + entries_7_3_padding_0 :bit8; + entries_7_3_McArbBurstTime:bit8; + end; + + TMCIF_WB_BUFMGR_VCE_CONTROL=bitpacked record + MCIF_WB_BUFMGR_VCE_LOCK_IGNORE :bit1; + RESERVED0 :bit3; + MCIF_WB_BUFMGR_VCE_INT_EN :bit1; + MCIF_WB_BUFMGR_VCE_INT_ACK :bit1; + MCIF_WB_BUFMGR_VCE_SLICE_INT_EN:bit1; + RESERVED1 :bit1; + MCIF_WB_BUFMGR_VCE_LOCK :bit4; + RESERVED2 :bit4; + MCIF_WB_BUFMGR_SLICE_SIZE :bit13; + RESERVED3 :bit3; + end; + + TMCIF_WRITE_COMBINE_CONTROL=bitpacked record + MCIF_WRITE_COMBINE_TIMEOUT:bit8; + VIP_WRITE_COMBINE_TIMEOUT :bit8; + RESERVED0 :bit16; + end; + + TMC_FUS_ARB_GARLIC_ISOC_PRI=bitpacked record + DMIF_RD_TOKURG_EN :bit1; + UVD_RD_TOKURG_EN :bit1; + VCE_RD_TOKURG_EN :bit1; + ACP_RD_TOKURG_EN :bit1; + DMIF_RD_PRIURG_EN :bit1; + UVD_RD_PRIURG_EN :bit1; + VCE_RD_PRIURG_EN :bit1; + ACP_RD_PRIURG_EN :bit1; + DMIF_RD_ISOC_EN :bit1; + UVD_RD_ISOC_EN :bit1; + VCE_RD_ISOC_EN :bit1; + MCIF_RD_ISOC_EN :bit1; + UMC_RD_ISOC_EN :bit1; + VCEU_RD_ISOC_EN :bit1; + ACP_RD_ISOC_EN :bit1; + REQPRI_OVERRIDE_EN :bit1; + REQPRI_OVERRIDE_VAL :bit2; + PRIPRMTE_OVERRIDE_EN :bit1; + TOKURG_OVERRIDE_EN :bit1; + PRIURG_OVERRIDE_EN :bit1; + PRIPRMTE_OVERRIDE_VAL:bit1; + TOKURG_OVERRIDE_VAL :bit1; + PRIURG_OVERRIDE_VAL :bit1; + GARLIC_REQ_CREDITS :bit5; + MM_REL_LATE :bit1; + RESERVED0 :bit2; + end; + + TMC_RPB_PERF_COUNTER_STATUS=bit32; + + TMC_VM_MB_L1_TLS0_END_ADDR0=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR1=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR2=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR3=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR4=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR5=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR6=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR7=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_MB_L1_TLS0_END_ADDR8=bitpacked record + END_ADDR :bit28; + RESERVED0:bit4; + end; + + TMC_VM_NB_TOP_OF_DRAM_SLOT1=bitpacked record + RESERVED0 :bit23; + TOP_OF_DRAM:bit9; + end; + + TMC_XPB_P2P_BAR_DELTA_ABOVE=bitpacked record + EN :bit8; + DELTA :bit20; + RESERVED0:bit4; + end; + + TMC_XPB_P2P_BAR_DELTA_BELOW=bitpacked record + EN :bit8; + DELTA :bit20; + RESERVED0:bit4; + end; + + TMC_XPB_XDMA_RTR_SRC_APRTR0=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_XDMA_RTR_SRC_APRTR1=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_XDMA_RTR_SRC_APRTR2=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + + TMC_XPB_XDMA_RTR_SRC_APRTR3=bitpacked record + BASE_ADDR:bit25; + RESERVED0:bit7; + end; + TPA_SC_PERFCOUNTER0_SELECT1=bitpacked record PERF_SEL2:bit10; PERF_SEL3:bit10; @@ -12919,6 +58440,423 @@ type RESERVED0:bit12; end; + TPB0_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_ALL_CBI_UPDT_L0T3 :bit1; + IGNR_ALL_CBI_UPDT_L4T7 :bit1; + IGNR_ALL_CBI_UPDT_L8T11 :bit1; + IGNR_ALL_CBI_UPDT_L12T15 :bit1; + IGNR_IMPCAL_ACTIVE_CBI_UPDT:bit1; + RESERVED0 :bit3; + TXNIMP :bit4; + TXPIMP :bit4; + RXIMP :bit4; + IMPCAL_ACTIVE :bit1; + RESERVED1 :bit11; + end; + + TPB0_GLB_SCI_STAT_OVRD_REG1=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L0T3:bit1; + IGNR_FREQDIV_CBI_UPDT_L0T3 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L0T3 :bit1; + RESERVED0 :bit9; + DLL_LOCK_0 :bit1; + DLL_LOCK_1 :bit1; + DLL_LOCK_2 :bit1; + DLL_LOCK_3 :bit1; + LINKSPEED_0 :bit2; + FREQDIV_0 :bit2; + LINKSPEED_1 :bit2; + FREQDIV_1 :bit2; + LINKSPEED_2 :bit2; + FREQDIV_2 :bit2; + LINKSPEED_3 :bit2; + FREQDIV_3 :bit2; + end; + + TPB0_GLB_SCI_STAT_OVRD_REG2=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L4T7:bit1; + IGNR_FREQDIV_CBI_UPDT_L4T7 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L4T7 :bit1; + RESERVED0 :bit9; + DLL_LOCK_4 :bit1; + DLL_LOCK_5 :bit1; + DLL_LOCK_6 :bit1; + DLL_LOCK_7 :bit1; + LINKSPEED_4 :bit2; + FREQDIV_4 :bit2; + LINKSPEED_5 :bit2; + FREQDIV_5 :bit2; + LINKSPEED_6 :bit2; + FREQDIV_6 :bit2; + LINKSPEED_7 :bit2; + FREQDIV_7 :bit2; + end; + + TPB0_GLB_SCI_STAT_OVRD_REG3=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L8T11:bit1; + IGNR_FREQDIV_CBI_UPDT_L8T11 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L8T11 :bit1; + RESERVED0 :bit9; + DLL_LOCK_8 :bit1; + DLL_LOCK_9 :bit1; + DLL_LOCK_10 :bit1; + DLL_LOCK_11 :bit1; + LINKSPEED_8 :bit2; + FREQDIV_8 :bit2; + LINKSPEED_9 :bit2; + FREQDIV_9 :bit2; + LINKSPEED_10 :bit2; + FREQDIV_10 :bit2; + LINKSPEED_11 :bit2; + FREQDIV_11 :bit2; + end; + + TPB0_GLB_SCI_STAT_OVRD_REG4=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L12T15:bit1; + IGNR_FREQDIV_CBI_UPDT_L12T15 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit9; + DLL_LOCK_12 :bit1; + DLL_LOCK_13 :bit1; + DLL_LOCK_14 :bit1; + DLL_LOCK_15 :bit1; + LINKSPEED_12 :bit2; + FREQDIV_12 :bit2; + LINKSPEED_13 :bit2; + FREQDIV_13 :bit2; + LINKSPEED_14 :bit2; + FREQDIV_14 :bit2; + LINKSPEED_15 :bit2; + FREQDIV_15 :bit2; + end; + + TPB1_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_ALL_CBI_UPDT_L0T3 :bit1; + IGNR_ALL_CBI_UPDT_L4T7 :bit1; + IGNR_ALL_CBI_UPDT_L8T11 :bit1; + IGNR_ALL_CBI_UPDT_L12T15 :bit1; + IGNR_IMPCAL_ACTIVE_CBI_UPDT:bit1; + RESERVED0 :bit3; + TXNIMP :bit4; + TXPIMP :bit4; + RXIMP :bit4; + IMPCAL_ACTIVE :bit1; + RESERVED1 :bit11; + end; + + TPB1_GLB_SCI_STAT_OVRD_REG1=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L0T3:bit1; + IGNR_FREQDIV_CBI_UPDT_L0T3 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L0T3 :bit1; + RESERVED0 :bit9; + DLL_LOCK_0 :bit1; + DLL_LOCK_1 :bit1; + DLL_LOCK_2 :bit1; + DLL_LOCK_3 :bit1; + LINKSPEED_0 :bit2; + FREQDIV_0 :bit2; + LINKSPEED_1 :bit2; + FREQDIV_1 :bit2; + LINKSPEED_2 :bit2; + FREQDIV_2 :bit2; + LINKSPEED_3 :bit2; + FREQDIV_3 :bit2; + end; + + TPB1_GLB_SCI_STAT_OVRD_REG2=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L4T7:bit1; + IGNR_FREQDIV_CBI_UPDT_L4T7 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L4T7 :bit1; + RESERVED0 :bit9; + DLL_LOCK_4 :bit1; + DLL_LOCK_5 :bit1; + DLL_LOCK_6 :bit1; + DLL_LOCK_7 :bit1; + LINKSPEED_4 :bit2; + FREQDIV_4 :bit2; + LINKSPEED_5 :bit2; + FREQDIV_5 :bit2; + LINKSPEED_6 :bit2; + FREQDIV_6 :bit2; + LINKSPEED_7 :bit2; + FREQDIV_7 :bit2; + end; + + TPB1_GLB_SCI_STAT_OVRD_REG3=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L8T11:bit1; + IGNR_FREQDIV_CBI_UPDT_L8T11 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L8T11 :bit1; + RESERVED0 :bit9; + DLL_LOCK_8 :bit1; + DLL_LOCK_9 :bit1; + DLL_LOCK_10 :bit1; + DLL_LOCK_11 :bit1; + LINKSPEED_8 :bit2; + FREQDIV_8 :bit2; + LINKSPEED_9 :bit2; + FREQDIV_9 :bit2; + LINKSPEED_10 :bit2; + FREQDIV_10 :bit2; + LINKSPEED_11 :bit2; + FREQDIV_11 :bit2; + end; + + TPB1_GLB_SCI_STAT_OVRD_REG4=bitpacked record + IGNR_LINKSPEED_CBI_UPDT_L12T15:bit1; + IGNR_FREQDIV_CBI_UPDT_L12T15 :bit1; + IGNR_DLL_LOCK_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit9; + DLL_LOCK_12 :bit1; + DLL_LOCK_13 :bit1; + DLL_LOCK_14 :bit1; + DLL_LOCK_15 :bit1; + LINKSPEED_12 :bit2; + FREQDIV_12 :bit2; + LINKSPEED_13 :bit2; + FREQDIV_13 :bit2; + LINKSPEED_14 :bit2; + FREQDIV_14 :bit2; + LINKSPEED_15 :bit2; + FREQDIV_15 :bit2; + end; + + TPCIE_DPA_LATENCY_INDICATOR=bitpacked record + TRANS_LAT_INDICATOR_BITS:bit8; + RESERVED0 :bit24; + end; + + TPCIE_LC_FORCE_EQ_REQ_COEFF=bitpacked record + LC_FORCE_COEFF_IN_EQ_REQ_PHASE:bit1; + LC_FORCE_PRE_CURSOR_REQ :bit6; + LC_FORCE_CURSOR_REQ :bit6; + LC_FORCE_POST_CURSOR_REQ :bit6; + LC_FS_OTHER_END :bit6; + LC_LF_OTHER_END :bit6; + RESERVED0 :bit1; + end; + + TPCIE_PAGE_REQ_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_PERF_CNTL_SLV_S_C_CLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PERF_COUNT0_MST_C_CLK=bit32; + + TPCIE_PERF_COUNT0_MST_R_CLK=bit32; + + TPCIE_PERF_COUNT0_SLV_R_CLK=bit32; + + TPCIE_PERF_COUNT1_MST_C_CLK=bit32; + + TPCIE_PERF_COUNT1_MST_R_CLK=bit32; + + TPCIE_PERF_COUNT1_SLV_R_CLK=bit32; + + TPCIE_SRIOV_FIRST_VF_OFFSET=bitpacked record + SRIOV_FIRST_VF_OFFSET:bit16; + RESERVED0 :bit16; + end; + + TPCIE_TPH_REQR_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPIPE0_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE1_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE2_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE3_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE4_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE5_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE6_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TPIPE7_ARBITRATION_CONTROL3=bitpacked record + EFFICIENCY_WEIGHT:bit16; + RESERVED0 :bit16; + end; + + TREGAMMA_CNTLA_REGION_10_11=bitpacked record + REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_12_13=bitpacked record + REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLA_REGION_14_15=bitpacked record + REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_10_11=bitpacked record + REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_12_13=bitpacked record + REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TREGAMMA_CNTLB_REGION_14_15=bitpacked record + REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET :bit9; + RESERVED0 :bit3; + REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET :bit9; + RESERVED2 :bit3; + REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS:bit3; + RESERVED3 :bit1; + end; + + TRLC_GPU_IOV_VIRT_RESET_REQ=bitpacked record + VF_FLR :bit16; + RESERVED :bit15; + SOFT_PF_FLR:bit1; + end; + + TRLC_SERDES_RD_MASTER_INDEX=bitpacked record + CU_ID :bit4; + SH_ID :bit2; + SE_ID :bit3; + SE_NONCU_ID:bit1; + SE_NONCU :bit1; + NON_SE :bit4; + DATA_REG_ID:bit2; + SPARE :bit15; + end; + + TRLC_SMU_GRBM_REG_SAVE_CTRL=bitpacked record + START_GRBM_REG_SAVE:bit1; + SPARE :bit31; + end; + + TRLC_SPM_GLOBAL_MUXSEL_ADDR=bit32; + + TRLC_SPM_GLOBAL_MUXSEL_DATA=bit32; + + TRLC_SRM_GPM_COMMAND_STATUS=bitpacked record + FIFO_EMPTY:bit1; + FIFO_FULL :bit1; + RESERVED :bit30; + end; + + TSAM_IH_EXT_ERR_INTR_STATUS=bitpacked record + UVD :bit1; + VCE :bit1; + ISP :bit1; + RESERVED0:bit29; + end; + + TSCL_AUTOMATIC_MODE_CONTROL=bitpacked record + SCL_V_CALC_AUTO_RATIO_EN:bit1; + RESERVED0 :bit15; + SCL_H_CALC_AUTO_RATIO_EN:bit1; + RESERVED1 :bit15; + end; + + TSDMA0_RLC0_RB_RPTR_ADDR_HI=bit32; + + TSDMA0_RLC0_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_RLC1_RB_RPTR_ADDR_HI=bit32; + + TSDMA0_RLC1_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC0_RB_RPTR_ADDR_HI=bit32; + + TSDMA1_RLC0_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC1_RB_RPTR_ADDR_HI=bit32; + + TSDMA1_RLC1_RB_RPTR_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSLAVE_HANG_PROTECTION_CNTL=bitpacked record + RESERVED0 :bit1; + HANG_PROTECTION_TIMER_SEL:bit3; + RESERVED1 :bit28; + end; + TSPI_P0_TRAP_SCREEN_GPR_MIN=bitpacked record VGPR_MIN :bit6; SGPR_MIN :bit4; @@ -13154,11 +59092,227 @@ type TSQ_THREAD_TRACE_USERDATA_3=bit32; + TSQ_THREAD_TRACE_WORD_EVENT=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + SH_ID :bit1; + STAGE :bit3; + RESERVED0 :bit1; + EVENT_TYPE:bit6; + RESERVED1 :bit16; + end; + + TSQ_THREAD_TRACE_WORD_ISSUE=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + SIMD_ID :bit2; + RESERVED0 :bit1; + INST0 :bit2; + INST1 :bit2; + INST2 :bit2; + INST3 :bit2; + INST4 :bit2; + INST5 :bit2; + INST6 :bit2; + INST7 :bit2; + INST8 :bit2; + INST9 :bit2; + RESERVED1 :bit4; + end; + + TTMDS_SYNC_CHAR_PATTERN_0_1=bitpacked record + TMDS_SYNC_CHAR_PATTERN0:bit10; + RESERVED0 :bit6; + TMDS_SYNC_CHAR_PATTERN1:bit10; + RESERVED1 :bit6; + end; + + TTMDS_SYNC_CHAR_PATTERN_2_3=bitpacked record + TMDS_SYNC_CHAR_PATTERN2:bit10; + RESERVED0 :bit6; + TMDS_SYNC_CHAR_PATTERN3:bit10; + RESERVED1 :bit6; + end; + + TUNP_GRPH_INTERRUPT_CONTROL=bitpacked record + GRPH_PFLIP_INT_MASK:bit1; + RESERVED0 :bit7; + GRPH_PFLIP_INT_TYPE:bit1; + RESERVED1 :bit23; + end; + + TUVD_MIF_RECON1_ADDR_CONFIG=bitpacked record + NUM_PIPES :bit3; + RESERVED0 :bit1; + PIPE_INTERLEAVE_SIZE :bit3; + RESERVED1 :bit1; + BANK_INTERLEAVE_SIZE :bit3; + RESERVED2 :bit1; + NUM_SHADER_ENGINES :bit2; + RESERVED3 :bit2; + SHADER_ENGINE_TILE_SIZE:bit3; + RESERVED4 :bit1; + NUM_GPUS :bit3; + RESERVED5 :bit1; + MULTI_GPU_TILE_SIZE :bit2; + RESERVED6 :bit2; + ROW_SIZE :bit2; + NUM_LOWER_PIPES :bit1; + RESERVED7 :bit1; + end; + TVGT_MULTI_PRIM_IB_RESET_EN=bitpacked record RESET_EN :bit1; RESERVED0:bit31; end; + TVM_PRT_APERTURE0_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE1_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE2_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_PRT_APERTURE3_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TXDMA_LOCAL_SURFACE_TILING1=bitpacked record + XDMA_LOCAL_ARRAY_MODE :bit4; + XDMA_LOCAL_TILE_SPLIT :bit3; + RESERVED0 :bit1; + XDMA_LOCAL_BANK_WIDTH :bit2; + XDMA_LOCAL_BANK_HEIGHT :bit2; + XDMA_LOCAL_MACRO_TILE_ASPECT:bit2; + RESERVED1 :bit6; + XDMA_LOCAL_NUM_BANKS :bit2; + RESERVED2 :bit10; + end; + + TXDMA_LOCAL_SURFACE_TILING2=bitpacked record + XDMA_LOCAL_PIPE_INTERLEAVE_SIZE:bit3; + RESERVED0 :bit17; + XDMA_LOCAL_MICRO_TILE_MODE :bit3; + RESERVED1 :bit4; + XDMA_LOCAL_PIPE_CONFIG :bit5; + end; + + TXDMA_MC_PCIE_CLIENT_CONFIG=bitpacked record + RESERVED0 :bit8; + XDMA_MC_PCIE_SWAP:bit2; + RESERVED1 :bit2; + XDMA_MC_PCIE_VMID:bit4; + XDMA_MC_PCIE_PRIV:bit1; + RESERVED2 :bit15; + end; + + TXDMA_MSTR_PCIE_NACK_STATUS=bitpacked record + XDMA_MSTR_PCIE_NACK_TAG:bit10; + RESERVED0 :bit2; + XDMA_MSTR_PCIE_NACK :bit2; + RESERVED1 :bit2; + XDMA_MSTR_PCIE_NACK_CLR:bit1; + RESERVED2 :bit15; + end; + + TXDMA_SLV_MEM_CLIENT_CONFIG=bitpacked record + RESERVED0 :bit8; + XDMA_SLV_MEM_CLIENT_SWAP:bit2; + RESERVED1 :bit2; + XDMA_SLV_MEM_CLIENT_VMID:bit4; + XDMA_SLV_MEM_CLIENT_PRIV:bit1; + RESERVED2 :bit15; + end; + + TXDMA_SLV_WRITE_URGENT_CNTL=bitpacked record + XDMA_SLV_WRITE_STALL :bit1; + RESERVED0 :bit7; + XDMA_SLV_WRITE_URGENT_LEVEL:bit4; + XDMA_SLV_WRITE_STALL_DELAY :bit4; + RESERVED1 :bit16; + end; + + TAZALIA_F0_GTC_GROUP_OFFSET0=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET1=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET2=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET3=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET4=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET5=bit32; + + TAZALIA_F0_GTC_GROUP_OFFSET6=bit32; + + TBIF_CC_RFE_IMP_OVERRIDECNTL=bitpacked record + RESERVED0 :bit1; + STRAP_PLL_RX_IMPVAL :bit4; + STRAP_PLL_RX_IMPVAL_EN :bit1; + STRAP_PLL_TX_IMPVAL_PD :bit4; + STRAP_PLL_TX_IMPVAL_EN_PD :bit1; + STRAP_PLL_TX_IMPVAL_PU :bit4; + STRAP_PLL_TX_IMPVAL_EN_PU :bit1; + STRAP_PLL_IMP_DBG_ANALOG_EN :bit1; + STRAP_PLL_IMP_IGNORE_QUICKSIM:bit1; + RESERVED1 :bit14; + end; + + TBIF_DOORBELL_GBLAPER1_LOWER=bitpacked record + RESERVED0 :bit2; + DOORBELL_GBLAPER1_LOWER:bit10; + RESERVED1 :bit19; + DOORBELL_GBLAPER1_EN :bit1; + end; + + TBIF_DOORBELL_GBLAPER1_UPPER=bitpacked record + RESERVED0 :bit2; + DOORBELL_GBLAPER1_UPPER:bit10; + RESERVED1 :bit20; + end; + + TBIF_DOORBELL_GBLAPER2_LOWER=bitpacked record + RESERVED0 :bit2; + DOORBELL_GBLAPER2_LOWER:bit10; + RESERVED1 :bit19; + DOORBELL_GBLAPER2_EN :bit1; + end; + + TBIF_DOORBELL_GBLAPER2_UPPER=bitpacked record + RESERVED0 :bit2; + DOORBELL_GBLAPER2_UPPER:bit10; + RESERVED1 :bit20; + end; + + TBIF_GPUIOV_FB_TOTAL_FB_INFO=bitpacked record + TOTAL_FB_AVAILABLE:bit16; + TOTAL_FB_CONSUMED :bit16; + end; + + TBIF_RFE_MST_SMBUS_CMDSTATUS=bitpacked record + REG_SMBUS_clkGate_timer :bit8; + REG_SMBUS_clkSetup_timer:bit4; + RESERVED0 :bit4; + REG_SMBUS_timeout_timer :bit8; + SMBUS_RFE_mstTimeout :bit1; + RESERVED1 :bit7; + end; + + TBL1_PWM_AMBIENT_LIGHT_LEVEL=bitpacked record + BL1_PWM_AMBIENT_LIGHT_LEVEL:bit17; + RESERVED0 :bit15; + end; + TCOMPUTE_PIPELINESTAT_ENABLE=bitpacked record PIPELINESTAT_ENABLE:bit1; RESERVED0 :bit31; @@ -13199,6 +59353,286 @@ type TCP_PFP_GDS_ATOMIC1_PREOP_LO=bit32; + TCRTC_CRC0_WINDOWA_X_CONTROL=bitpacked record + CRTC_CRC0_WINDOWA_X_START:bit14; + RESERVED0 :bit2; + CRTC_CRC0_WINDOWA_X_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC0_WINDOWA_Y_CONTROL=bitpacked record + CRTC_CRC0_WINDOWA_Y_START:bit14; + RESERVED0 :bit2; + CRTC_CRC0_WINDOWA_Y_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC0_WINDOWB_X_CONTROL=bitpacked record + CRTC_CRC0_WINDOWB_X_START:bit14; + RESERVED0 :bit2; + CRTC_CRC0_WINDOWB_X_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC0_WINDOWB_Y_CONTROL=bitpacked record + CRTC_CRC0_WINDOWB_Y_START:bit14; + RESERVED0 :bit2; + CRTC_CRC0_WINDOWB_Y_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC1_WINDOWA_X_CONTROL=bitpacked record + CRTC_CRC1_WINDOWA_X_START:bit14; + RESERVED0 :bit2; + CRTC_CRC1_WINDOWA_X_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC1_WINDOWA_Y_CONTROL=bitpacked record + CRTC_CRC1_WINDOWA_Y_START:bit14; + RESERVED0 :bit2; + CRTC_CRC1_WINDOWA_Y_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC1_WINDOWB_X_CONTROL=bitpacked record + CRTC_CRC1_WINDOWB_X_START:bit14; + RESERVED0 :bit2; + CRTC_CRC1_WINDOWB_X_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_CRC1_WINDOWB_Y_CONTROL=bitpacked record + CRTC_CRC1_WINDOWB_Y_START:bit14; + RESERVED0 :bit2; + CRTC_CRC1_WINDOWB_Y_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_MVP_INBAND_CNTL_INSERT=bitpacked record + CRTC_MVP_INBAND_OUT_MODE :bit2; + RESERVED0 :bit6; + CRTC_MVP_INBAND_CNTL_CHAR_INSERT:bit24; + end; + + TDCFEV0_CRTC_PIXEL_RATE_CNTL=bitpacked record + DCFEV0_CRTC_PIXEL_RATE_SOURCE:bit2; + RESERVED0 :bit30; + end; + + TDC_GPU_TIMER_START_POSITION=bitpacked record + RESERVED0:bit3; + RESERVED1:bit13; + RESERVED2:bit3; + RESERVED3:bit13; + end; + + TDMCU_DPRX_INTERRUPT_STATUS1=bitpacked record + DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED :bit1; + DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED :bit1; + DPRX_SD0P0_VERTICAL_INT0_OCCURRED :bit1; + DPRX_SD0P0_VERTICAL_INT1_OCCURRED :bit1; + DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED :bit1; + DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED :bit1; + DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED :bit1; + DPRX_SD1P0_VERTICAL_INT0_OCCURRED :bit1; + DPRX_SD1P0_VERTICAL_INT1_OCCURRED :bit1; + DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED:bit1; + DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED :bit1; + DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED :bit1; + DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED :bit1; + DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED :bit1; + DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED :bit1; + DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED :bit1; + DPRX_AUX_P0_AUX_INT_OCCURRED :bit1; + DPRX_AUX_P0_I2C_INT_OCCURRED :bit1; + DPRX_AUX_P0_CPU_INT_OCCURRED :bit1; + DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED :bit1; + DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED :bit1; + DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED :bit1; + DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + end; + + TDMCU_UC_INTERNAL_INT_STATUS=bitpacked record + UC_INT_IRQ_N_PIN :bit1; + UC_INT_XIRQ_N_PIN :bit1; + UC_INT_SOFTWARE_INTERRUPT :bit1; + UC_INT_ILLEGAL_OPCODE_TRAP :bit1; + UC_INT_TIMER_OUTPUT_COMPARE_4 :bit1; + UC_INT_TIMER_OUTPUT_COMPARE_3 :bit1; + UC_INT_TIMER_OUTPUT_COMPARE_2 :bit1; + UC_INT_TIMER_OUTPUT_COMPARE_1 :bit1; + UC_INT_TIMER_OVERFLOW :bit1; + UC_INT_REAL_TIME_INTERRUPT :bit1; + UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5:bit1; + UC_INT_TIMER_INPUT_CAPTURE_3 :bit1; + UC_INT_TIMER_INPUT_CAPTURE_2 :bit1; + UC_INT_TIMER_INPUT_CAPTURE_1 :bit1; + UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE :bit1; + UC_INT_PULSE_ACCUMULATOR_OVERFLOW :bit1; + RESERVED0 :bit16; + end; + + TGAMMA_CORR_CNTLA_REGION_0_1=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_2_3=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_4_5=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_6_7=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_8_9=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_SLOPE_CNTL=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE:bit18; + RESERVED0 :bit14; + end; + + TGAMMA_CORR_CNTLA_START_CNTL=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION_START :bit18; + RESERVED0 :bit2; + GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT:bit7; + RESERVED1 :bit5; + end; + + TGAMMA_CORR_CNTLB_REGION_0_1=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_2_3=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_4_5=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_6_7=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_8_9=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_SLOPE_CNTL=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE:bit18; + RESERVED0 :bit14; + end; + + TGAMMA_CORR_CNTLB_START_CNTL=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION_START :bit18; + RESERVED0 :bit2; + GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT:bit7; + RESERVED1 :bit5; + end; + + TGARLIC_COHE_UVD_RBC_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_VCE_OUT_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGC_USER_SHADER_ARRAY_CONFIG=bitpacked record + RESERVED0 :bit16; + INACTIVE_CUS:bit16; + end; + TGRBM_SE0_PERFCOUNTER_SELECT=bitpacked record PERF_SEL :bit6; RESERVED0 :bit4; @@ -13271,6 +59705,97 @@ type RESERVED2 :bit10; end; + THDMI_GENERIC_PACKET_CONTROL=bitpacked record + RESERVED0:bit1; + RESERVED1:bit1; + RESERVED2:bit2; + RESERVED3:bit1; + RESERVED4:bit1; + RESERVED5:bit10; + RESERVED6:bit6; + RESERVED7:bit2; + RESERVED8:bit6; + RESERVED9:bit2; + end; + + TIH_DSM_MATCH_VALUE_BIT_31_0=bit32; + + TMCIF_WB_ARBITRATION_CONTROL=bitpacked record + MCIF_WB_CLIENT_ARBITRATION_SLICE:bit2; + RESERVED0 :bit24; + MCIF_WB_TIME_PER_PIXEL :bit6; + end; + + TMCIF_WB_BUF_1_ADDR_C_OFFSET=bitpacked record + MCIF_WB_BUF_1_ADDR_C_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_1_ADDR_Y_OFFSET=bitpacked record + MCIF_WB_BUF_1_ADDR_Y_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_2_ADDR_C_OFFSET=bitpacked record + MCIF_WB_BUF_2_ADDR_C_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_2_ADDR_Y_OFFSET=bitpacked record + MCIF_WB_BUF_2_ADDR_Y_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_3_ADDR_C_OFFSET=bitpacked record + MCIF_WB_BUF_3_ADDR_C_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_3_ADDR_Y_OFFSET=bitpacked record + MCIF_WB_BUF_3_ADDR_Y_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_4_ADDR_C_OFFSET=bitpacked record + MCIF_WB_BUF_4_ADDR_C_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMCIF_WB_BUF_4_ADDR_Y_OFFSET=bitpacked record + MCIF_WB_BUF_4_ADDR_Y_OFFSET:bit18; + RESERVED0 :bit14; + end; + + TMC_DC_INTERFACE_NACK_STATUS=bitpacked record + DMIF_RDRET_NACK_OCCURRED:bit1; + RESERVED0 :bit3; + DMIF_RDRET_NACK_CLEAR :bit1; + RESERVED1 :bit3; + VIP_WRRET_NACK_OCCURRED :bit1; + RESERVED2 :bit3; + VIP_WRRET_NACK_CLEAR :bit1; + RESERVED3 :bit3; + MCIF_RDRET_NACK_OCCURRED:bit1; + RESERVED4 :bit3; + MCIF_RDRET_NACK_CLEAR :bit1; + RESERVED5 :bit3; + MCIF_WRRET_NACK_OCCURRED:bit1; + RESERVED6 :bit3; + MCIF_WRRET_NACK_CLEAR :bit1; + RESERVED7 :bit3; + end; + + TMC_VM_NB_LOWER_TOP_OF_DRAM2=bitpacked record + ENABLE :bit1; + RESERVED0 :bit22; + LOWER_TOM2:bit9; + end; + + TMC_VM_NB_UPPER_TOP_OF_DRAM2=bitpacked record + UPPER_TOM2:bit8; + RESERVED0 :bit24; + end; + TPA_SC_P3D_TRAP_SCREEN_COUNT=bitpacked record COUNT :bit16; RESERVED0:bit16; @@ -13282,8 +59807,183 @@ type RESERVED0 :bit30; end; + TPCIEP_ERROR_INJECT_PHYSICAL=bitpacked record + ERROR_INJECT_PL_LANE_ERR :bit2; + ERROR_INJECT_PL_FRAMING_ERR :bit2; + ERROR_INJECT_PL_BAD_PARITY_IN_SKP :bit2; + ERROR_INJECT_PL_BAD_LFSR_IN_SKP :bit2; + ERROR_INJECT_PL_LOOPBACK_UFLOW :bit2; + ERROR_INJECT_PL_LOOPBACK_OFLOW :bit2; + ERROR_INJECT_PL_DESKEW_ERR :bit2; + ERROR_INJECT_PL_8B10B_DISPARITY_ERR:bit2; + ERROR_INJECT_PL_8B10B_DECODE_ERR :bit2; + ERROR_INJECT_PL_SKP_OS_ERROR :bit2; + ERROR_INJECT_PL_INV_OS_IDENTIFIER :bit2; + ERROR_INJECT_PL_BAD_SYNC_HEADER :bit2; + RESERVED0 :bit8; + end; + + TPCIE_PERF_CNTL_SLV_NS_C_CLK=bitpacked record + EVENT0_SEL :bit8; + EVENT1_SEL :bit8; + COUNTER0_UPPER:bit8; + COUNTER1_UPPER:bit8; + end; + + TPCIE_PWR_BUDGET_DATA_SELECT=bitpacked record + DATA_SELECT:bit8; + RESERVED0 :bit24; + end; + + TPCIE_RX_CREDITS_ALLOCATED_P=bitpacked record + RX_CREDITS_ALLOCATED_PD:bit12; + RESERVED0 :bit4; + RX_CREDITS_ALLOCATED_PH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_SECONDARY_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_SRIOV_SYSTEM_PAGE_SIZE=bit32; + + TREG_ADAPT_pciecore0_CONTROL=bitpacked record + ACCESS_MODE_pciecore0:bit1; + RESERVED0 :bit31; + end; + + TRLC_CAPTURE_GPU_CLOCK_COUNT=bitpacked record + CAPTURE :bit1; + RESERVED:bit31; + end; + + TRLC_SRM_RLCV_COMMAND_STATUS=bitpacked record + FIFO_EMPTY:bit1; + FIFO_FULL :bit1; + RESERVED :bit30; + end; + + TSCLV_AUTOMATIC_MODE_CONTROL=bitpacked record + SCL_V_CALC_AUTO_RATIO_EN:bit1; + RESERVED0 :bit15; + SCL_H_CALC_AUTO_RATIO_EN:bit1; + RESERVED1 :bit15; + end; + + TSCLV_VERT_FILTER_INIT_BOT_C=bitpacked record + SCL_V_INIT_FRAC_BOT_C:bit24; + SCL_V_INIT_INT_BOT_C :bit3; + RESERVED0 :bit5; + end; + + TSCL_HORZ_FILTER_SCALE_RATIO=bitpacked record + SCL_H_SCALE_RATIO:bit26; + RESERVED0 :bit6; + end; + + TSCL_VERT_FILTER_SCALE_RATIO=bitpacked record + SCL_V_SCALE_RATIO:bit26; + RESERVED0 :bit6; + end; + + TSDMA0_GFX_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + + TSDMA1_GFX_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + + TSH_HIDDEN_PRIVATE_BASE_VMID=bit32; + TSQ_THREAD_TRACE_TOKEN_MASK2=bit32; + TUNIPHY_DATA_SYNCHRONIZATION=bitpacked record + UNIPHY_DSYNSEL :bit1; + RESERVED0 :bit3; + UNIPHY_DSYN_LEVEL :bit2; + UNIPHY_DSYN_ERROR :bit1; + RESERVED1 :bit1; + UNIPHY_SOURCE_SELECT :bit1; + RESERVED2 :bit7; + UNIPHY_DUAL_LINK_PHASE:bit1; + RESERVED3 :bit15; + end; + + TUNIPHY_MACRO_CNTL_RESERVED0=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED1=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED2=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED3=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED4=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED5=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED6=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED7=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED8=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED9=bit32; + + TUNP_GRPH_SURFACE_OFFSET_X_C=bitpacked record + GRPH_SURFACE_OFFSET_X_C:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_SURFACE_OFFSET_X_L=bitpacked record + GRPH_SURFACE_OFFSET_X_L:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_SURFACE_OFFSET_Y_C=bitpacked record + GRPH_SURFACE_OFFSET_Y_C:bit14; + RESERVED0 :bit18; + end; + + TUNP_GRPH_SURFACE_OFFSET_Y_L=bitpacked record + GRPH_SURFACE_OFFSET_Y_L:bit14; + RESERVED0 :bit18; + end; + + TVGA_SEQUENCER_RESET_CONTROL=bitpacked record + D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET :bit1; + RESERVED0 :bit2; + D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET:bit1; + RESERVED1 :bit2; + VGA_MODE_AUTO_TRIGGER_ENABLE :bit1; + VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT :bit1; + VGA_MODE_AUTO_TRIGGER_INDEX_SELECT :bit6; + RESERVED2 :bit8; + end; + TVGT_STRMOUT_BUFFER_OFFSET_0=bit32; TVGT_STRMOUT_BUFFER_OFFSET_1=bit32; @@ -13297,6 +59997,35 @@ type RESERVED0 :bit24; end; + TXDMA_MSTR_MEM_CLIENT_CONFIG=bitpacked record + RESERVED0 :bit8; + XDMA_MSTR_MEM_CLIENT_SWAP:bit2; + RESERVED1 :bit2; + XDMA_MSTR_MEM_CLIENT_VMID:bit4; + XDMA_MSTR_MEM_CLIENT_PRIV:bit1; + RESERVED2 :bit15; + end; + + TXDMA_SLV_READ_LATENCY_TIMER=bitpacked record + XDMA_SLV_READ_LATENCY_TIMER:bit16; + RESERVED0 :bit16; + end; + + TXDMA_SLV_REMOTE_GPU_ADDRESS=bit32; + + TBPHYC_DAC_AUTO_CALIB_CONTROL=bitpacked record + BPHYC_DAC_CAL_INITB :bit1; + BPHYC_DAC_CAL_EN :bit1; + BPHYC_DAC_CAL_DACADJ_EN :bit1; + RESERVED0 :bit1; + BPHYC_DAC_CAL_WAIT_ADJUST:bit10; + RESERVED1 :bit6; + BPHYC_DAC_CAL_MASK :bit3; + RESERVED2 :bit5; + BPHYC_DAC_CAL_COMPLETE :bit1; + RESERVED3 :bit3; + end; + TCOMPUTE_WAVE_RESTORE_ADDR_HI=bitpacked record ADDR :bit16; RESERVED0:bit16; @@ -13347,6 +60076,280 @@ type RESERVED0:bit16; end; + TCRTC_DTMTEST_STATUS_POSITION=bitpacked record + CRTC_DTMTEST_VERT_COUNT:bit14; + RESERVED0 :bit2; + CRTC_DTMTEST_HORZ_COUNT:bit14; + RESERVED1 :bit2; + end; + + TCRTC_EXT_TIMING_SYNC_CONTROL=bitpacked record + CRTC_EXT_TIMING_SYNC_ENABLE :bit2; + RESERVED0 :bit1; + CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE :bit1; + CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE:bit1; + CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW:bit2; + RESERVED1 :bit1; + CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE :bit1; + CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE :bit1; + RESERVED2 :bit2; + CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY :bit1; + CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY :bit1; + CRTC_EXT_TIMING_SYNC_INTERLACE_MODE :bit1; + RESERVED3 :bit9; + CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE :bit3; + RESERVED4 :bit1; + CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE :bit3; + RESERVED5 :bit1; + end; + + TCRTC_TEST_PATTERN_PARAMETERS=bitpacked record + CRTC_TEST_PATTERN_INC0 :bit4; + CRTC_TEST_PATTERN_INC1 :bit4; + CRTC_TEST_PATTERN_VRES :bit4; + CRTC_TEST_PATTERN_HRES :bit4; + CRTC_TEST_PATTERN_RAMP0_OFFSET:bit16; + end; + + TDC_ABM1_OVERSCAN_PIXEL_VALUE=bitpacked record + ABM1_OVERSCAN_R_PIXEL_VALUE:bit10; + ABM1_OVERSCAN_G_PIXEL_VALUE:bit10; + ABM1_OVERSCAN_B_PIXEL_VALUE:bit10; + RESERVED0 :bit2; + end; + + TDMCU_INTERRUPT_TO_UC_EN_MASK=bitpacked record + ABM1_HG_READY_INT_TO_UC_EN :bit1; + ABM1_LS_READY_INT_TO_UC_EN :bit1; + ABM1_BL_UPDATE_INT_TO_UC_EN :bit1; + MCP_INT_TO_UC_EN :bit1; + DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN :bit1; + STATIC_SCREEN1_INT_TO_UC_EN :bit1; + STATIC_SCREEN2_INT_TO_UC_EN :bit1; + EXTERNAL_SW_INT_TO_UC_EN :bit1; + STATIC_SCREEN3_INT_TO_UC_EN :bit1; + STATIC_SCREEN4_INT_TO_UC_EN :bit1; + STATIC_SCREEN5_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN :bit1; + DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN:bit1; + DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN:bit1; + DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN:bit1; + DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN:bit1; + DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN:bit1; + DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN:bit1; + VBLANK1_INT_TO_UC_EN :bit1; + VBLANK2_INT_TO_UC_EN :bit1; + VBLANK3_INT_TO_UC_EN :bit1; + VBLANK4_INT_TO_UC_EN :bit1; + VBLANK5_INT_TO_UC_EN :bit1; + VBLANK6_INT_TO_UC_EN :bit1; + STATIC_SCREEN6_INT_TO_UC_EN :bit1; + RESERVED0 :bit1; + end; + + TDP_DPHY_FAST_TRAINING_STATUS=bitpacked record + DPHY_FAST_TRAINING_STATE :bit3; + RESERVED0 :bit1; + DPHY_FAST_TRAINING_COMPLETE_OCCURRED:bit1; + RESERVED1 :bit3; + DPHY_FAST_TRAINING_COMPLETE_MASK :bit1; + RESERVED2 :bit3; + DPHY_FAST_TRAINING_COMPLETE_ACK :bit1; + RESERVED3 :bit19; + end; + + TDP_DPHY_TRAINING_PATTERN_SEL=bitpacked record + DPHY_TRAINING_PATTERN_SEL:bit2; + RESERVED0 :bit30; + end; + + TGAMMA_CORR_LUT_WRITE_EN_MASK=bitpacked record + GAMMA_CORR_LUT_WRITE_EN_MASK:bit3; + RESERVED0 :bit29; + end; + + TGARLIC_COHE_GARLIC_FLUSH_REQ=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SAM_SAB_RBI_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SAM_SAB_RBO_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGRPH_PRIMARY_SURFACE_ADDRESS=bitpacked record + GRPH_PRIMARY_DFQ_ENABLE :bit1; + RESERVED0 :bit7; + GRPH_PRIMARY_SURFACE_ADDRESS:bit24; + end; + + THDMI_GENERIC_PACKET_CONTROL0=bitpacked record + HDMI_GENERIC0_SEND:bit1; + HDMI_GENERIC0_CONT:bit1; + RESERVED0 :bit2; + HDMI_GENERIC1_SEND:bit1; + HDMI_GENERIC1_CONT:bit1; + RESERVED1 :bit10; + HDMI_GENERIC0_LINE:bit6; + RESERVED2 :bit2; + HDMI_GENERIC1_LINE:bit6; + RESERVED3 :bit2; + end; + + THDMI_GENERIC_PACKET_CONTROL1=bitpacked record + HDMI_GENERIC2_SEND:bit1; + HDMI_GENERIC2_CONT:bit1; + RESERVED0 :bit2; + HDMI_GENERIC3_SEND:bit1; + HDMI_GENERIC3_CONT:bit1; + RESERVED1 :bit10; + HDMI_GENERIC2_LINE:bit6; + RESERVED2 :bit2; + HDMI_GENERIC3_LINE:bit6; + RESERVED3 :bit2; + end; + + THDP_MEM_COHERENCY_FLUSH_CNTL=bitpacked record + HDP_MEM_FLUSH_ADDR:bit1; + RESERVED0 :bit31; + end; + + THDP_REG_COHERENCY_FLUSH_CNTL=bitpacked record + HDP_REG_FLUSH_ADDR:bit1; + RESERVED0 :bit31; + end; + + TIH_DSM_MATCH_VALUE_BIT_63_32=bit32; + + TIH_DSM_MATCH_VALUE_BIT_95_64=bit32; + + TIH_RESET_INCOMPLETE_INT_CNTL=bitpacked record + CG :bit1; + DC :bit1; + RESERVED0 :bit1; + SAMMSP :bit1; + RLC :bit1; + ROM :bit1; + SRBM :bit1; + VMC :bit1; + UVD :bit1; + BIF :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + ISP :bit1; + VCE0 :bit1; + VCE1 :bit1; + ATC :bit1; + XDMA :bit1; + ACP :bit1; + SH :bit1; + SH1 :bit1; + SH2 :bit1; + SH3 :bit1; + RESET_ENABLE :bit1; + RESERVED1 :bit1; + INCOMPLETE_CNT:bit4; + RESERVED2 :bit4; + end; + + TLB_NO_OUTSTANDING_REQ_STATUS=bitpacked record + LB_NO_OUTSTANDING_REQ_STAT:bit1; + RESERVED0 :bit31; + end; + + TMC_ARB_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_HUB_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_RPB_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR0=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR1=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR2=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR3=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR4=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR5=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR6=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR7=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_MB_L1_TLS0_START_ADDR8=bitpacked record + START_ADDR:bit28; + RESERVED0 :bit4; + end; + TPA_SC_HP3D_TRAP_SCREEN_COUNT=bitpacked record COUNT :bit16; RESERVED0:bit16; @@ -13372,6 +60375,141 @@ type TPA_SU_POLY_OFFSET_BACK_SCALE=bit32; + TPCIE_MC_BLOCK_UNTRANSLATED_0=bit32; + + TPCIE_MC_BLOCK_UNTRANSLATED_1=bit32; + + TPCIE_OUTSTAND_PAGE_REQ_ALLOC=bit32; + + TPCIE_PERF_COUNT0_SLV_S_C_CLK=bit32; + + TPCIE_PERF_COUNT1_SLV_S_C_CLK=bit32; + + TPCIE_PWR_BUDGET_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_RX_CREDITS_ALLOCATED_NP=bitpacked record + RX_CREDITS_ALLOCATED_NPD:bit12; + RESERVED0 :bit4; + RX_CREDITS_ALLOCATED_NPH:bit8; + RESERVED1 :bit8; + end; + + TRLC_LB_ALWAYS_ACTIVE_CU_MASK=bit32; + + TRLC_SERDES_NONCU_MASTER_BUSY=bitpacked record + SE_MASTER_BUSY :bit16; + GC_MASTER_BUSY :bit1; + GC_GFX_MASTER_BUSY:bit1; + TC0_MASTER_BUSY :bit1; + TC1_MASTER_BUSY :bit1; + SPARE0_MASTER_BUSY:bit1; + SPARE1_MASTER_BUSY:bit1; + SPARE2_MASTER_BUSY:bit1; + SPARE3_MASTER_BUSY:bit1; + RESERVED :bit8; + end; + + TRLC_SERDES_WR_CU_MASTER_MASK=bit32; + + TRLC_SPM_PERFMON_RING_BASE_HI=bitpacked record + RING_BASE_HI:bit16; + RESERVED0 :bit16; + end; + + TRLC_SPM_PERFMON_RING_BASE_LO=bit32; + + TRLC_SPM_PERFMON_SEGMENT_SIZE=bitpacked record + PERFMON_SEGMENT_SIZE:bit8; + RESERVED0 :bit3; + GLOBAL_NUM_LINE :bit5; + SE0_NUM_LINE :bit5; + SE1_NUM_LINE :bit5; + SE2_NUM_LINE :bit5; + RESERVED1 :bit1; + end; + + TSCLV_EXT_OVERSCAN_LEFT_RIGHT=bitpacked record + EXT_OVERSCAN_RIGHT:bit13; + RESERVED0 :bit3; + EXT_OVERSCAN_LEFT :bit13; + RESERVED1 :bit3; + end; + + TSCLV_EXT_OVERSCAN_TOP_BOTTOM=bitpacked record + EXT_OVERSCAN_BOTTOM:bit13; + RESERVED0 :bit3; + EXT_OVERSCAN_TOP :bit13; + RESERVED1 :bit3; + end; + + TSCLV_HORZ_FILTER_SCALE_RATIO=bitpacked record + SCL_H_SCALE_RATIO:bit26; + RESERVED0 :bit6; + end; + + TSCLV_VERT_FILTER_SCALE_RATIO=bitpacked record + SCL_V_SCALE_RATIO:bit26; + RESERVED0 :bit6; + end; + + TSCL_COEF_RAM_CONFLICT_STATUS=bitpacked record + SCL_HOST_CONFLICT_FLAG :bit1; + RESERVED0 :bit7; + SCL_HOST_CONFLICT_ACK :bit1; + RESERVED1 :bit3; + SCL_HOST_CONFLICT_MASK :bit1; + RESERVED2 :bit3; + SCL_HOST_CONFLICT_INT_STATUS:bit1; + RESERVED3 :bit15; + end; + + TSCL_MANUAL_REPLICATE_CONTROL=bitpacked record + SCL_V_MANUAL_REPLICATE_FACTOR:bit4; + RESERVED0 :bit4; + SCL_H_MANUAL_REPLICATE_FACTOR:bit4; + RESERVED1 :bit20; + end; + + TSDMA0_RLC0_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + + TSDMA0_RLC1_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + + TSDMA1_RLC0_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + + TSDMA1_RLC1_RB_WPTR_POLL_CNTL=bitpacked record + ENABLE :bit1; + SWAP_ENABLE :bit1; + F32_POLL_ENABLE:bit1; + RESERVED0 :bit1; + FREQUENCY :bit12; + IDLE_POLL_COUNT:bit16; + end; + TSPI_PG_ENABLE_STATIC_CU_MASK=bitpacked record CU_MASK :bit16; RESERVED0:bit16; @@ -13457,8 +60595,92 @@ type RESERVED0 :bit7; end; + TUNIPHY_MACRO_CNTL_RESERVED10=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED11=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED12=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED13=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED14=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED15=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED16=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED17=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED18=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED19=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED20=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED21=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED22=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED23=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED24=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED25=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED26=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED27=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED28=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED29=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED30=bit32; + + TUNIPHY_MACRO_CNTL_RESERVED31=bit32; + + TUVD_LMI_RBC_IB_64BIT_BAR_LOW=bit32; + + TUVD_LMI_RBC_RB_64BIT_BAR_LOW=bit32; + + TVCE_LMI_VCPU_CACHE_40BIT_BAR=bit32; + + TVGA_MEMORY_BASE_ADDRESS_HIGH=bitpacked record + VGA_MEMORY_BASE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + TVGT_MULTI_PRIM_IB_RESET_INDX=bit32; + TXDMA_MSTR_REMOTE_GPU_ADDRESS=bit32; + + TXDMA_SLV_READ_LATENCY_MINMAX=bitpacked record + XDMA_SLV_READ_LATENCY_MIN:bit16; + XDMA_SLV_READ_LATENCY_MAX:bit16; + end; + + TAZALIA_F0_AUDIO_ENABLE_STATUS=bitpacked record + AUDIO_ENABLE_STATUS:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F0_CODEC_ENDPOINT_DATA=bit32; + + TBIF_GPUIOV_RESET_NOTIFICATION=bitpacked record + RESET_NOTIFICATION:bit17; + RESERVED0 :bit15; + end; + + TBL1_PWM_BL_UPDATE_SAMPLE_RATE=bitpacked record + BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN :bit1; + BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER :bit1; + RESERVED0 :bit6; + BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT :bit8; + BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET:bit8; + RESERVED1 :bit7; + ABM1_HGLS_REG_LOCK :bit1; + end; + TCP_HQD_PQ_RPTR_REPORT_ADDR_HI=bitpacked record RPTR_REPORT_ADDR_HI:bit16; RESERVED0 :bit16; @@ -13480,6 +60702,226 @@ type TCP_NUM_PRIM_WRITTEN_COUNT3_LO=bit32; + TCRTC_FIELD_INDICATION_CONTROL=bitpacked record + CRTC_FIELD_INDICATION_OUTPUT_POLARITY:bit1; + CRTC_FIELD_ALIGNMENT :bit1; + RESERVED0 :bit30; + end; + + TDCP_LB_DATA_GAP_BETWEEN_CHUNK=bitpacked record + DCP_LB_GAP_BETWEEN_CHUNK_20BPP:bit4; + DCP_LB_GAP_BETWEEN_CHUNK_30BPP:bit5; + RESERVED0 :bit23; + end; + + TDCRX_PHY_MACRO_CNTL_RESERVED0=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED1=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED2=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED3=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED4=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED5=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED6=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED7=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED8=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED9=bit32; + + TDMCU_SS_INTERRUPT_CNTL_STATUS=bitpacked record + RESERVED0 :bit13; + STATIC_SCREEN1_INT_STATUS :bit1; + STATIC_SCREEN1_INT_OCCURRED:bit1; + STATIC_SCREEN2_INT_STATUS :bit1; + STATIC_SCREEN2_INT_OCCURRED:bit1; + STATIC_SCREEN3_INT_STATUS :bit1; + STATIC_SCREEN3_INT_OCCURRED:bit1; + STATIC_SCREEN4_INT_STATUS :bit1; + STATIC_SCREEN4_INT_OCCURRED:bit1; + STATIC_SCREEN5_INT_STATUS :bit1; + STATIC_SCREEN5_INT_OCCURRED:bit1; + STATIC_SCREEN6_INT_STATUS :bit1; + STATIC_SCREEN6_INT_OCCURRED:bit1; + RESERVED1 :bit7; + end; + + TDPG_PIPE_ARBITRATION_CONTROL1=bitpacked record + PIXEL_DURATION:bit16; + BASE_WEIGHT :bit16; + end; + + TDPG_PIPE_ARBITRATION_CONTROL2=bitpacked record + TIME_WEIGHT :bit16; + URGENCY_WEIGHT:bit16; + end; + + TFMT_CRC_SIG_BLUE_CONTROL_MASK=bitpacked record + FMT_CRC_SIG_BLUE_MASK :bit16; + FMT_CRC_SIG_CONTROL_MASK:bit16; + end; + + TGAMMA_CORR_CNTLA_REGION_10_11=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_12_13=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLA_REGION_14_15=bitpacked record + GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_10_11=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_12_13=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGAMMA_CORR_CNTLB_REGION_14_15=bitpacked record + GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET :bit8; + RESERVED0 :bit3; + GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS:bit3; + RESERVED1 :bit1; + GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET :bit8; + RESERVED2 :bit4; + GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS:bit3; + RESERVED3 :bit2; + end; + + TGARLIC_COHE_CP_DMA_ME_COMMAND=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SDMA0_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SDMA1_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SDMA2_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_SDMA3_GFX_RB_WPTR=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGENERIC_I2C_INTERRUPT_CONTROL=bitpacked record + GENERIC_I2C_DONE_INT :bit1; + GENERIC_I2C_DONE_ACK :bit1; + GENERIC_I2C_DONE_MASK:bit1; + RESERVED0 :bit29; + end; + + TGRPH_COMPRESS_SURFACE_ADDRESS=bitpacked record + RESERVED0 :bit8; + GRPH_COMPRESS_SURFACE_ADDRESS:bit24; + end; + + TLBV_NO_OUTSTANDING_REQ_STATUS=bitpacked record + LB_NO_OUTSTANDING_REQ_STAT:bit1; + RESERVED0 :bit31; + end; + + TLBV_SNAPSHOT_V_COUNTER_CHROMA=bitpacked record + SNAPSHOT_V_COUNTER_CHROMA:bit15; + RESERVED0 :bit17; + end; + + TMC_CITF_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_GRUB_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_VM_MB_L2ARBITER_L2_CREDITS=bitpacked record + L2_IF_CREDITS:bit6; + RESERVED0 :bit26; + end; + + TMC_VM_MD_L2ARBITER_L2_CREDITS=bitpacked record + L2_IF_CREDITS:bit6; + RESERVED0 :bit26; + end; + + TOVL_SECONDARY_SURFACE_ADDRESS=bitpacked record + OVL_SECONDARY_DFQ_ENABLE :bit1; + RESERVED0 :bit7; + OVL_SECONDARY_SURFACE_ADDRESS:bit24; + end; + TPA_SC_P3D_TRAP_SCREEN_HV_LOCK=bitpacked record DISABLE_NON_PRIV_WRITES:bit1; RESERVED0 :bit31; @@ -13495,6 +60937,281 @@ type TPA_SU_POLY_OFFSET_FRONT_SCALE=bit32; + TPB0_RX_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_RXPWR_CBI_UPDT_L0T3 :bit1; + IGNR_RXPWR_CBI_UPDT_L4T7 :bit1; + IGNR_RXPWR_CBI_UPDT_L8T11 :bit1; + IGNR_RXPWR_CBI_UPDT_L12T15 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15:bit1; + IGNR_REQUESTTRK_CBI_UPDT_L0T3 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L4T7 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L8T11 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L12T15 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L0T3 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L4T7 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L8T11 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L12T15 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L0T3 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L4T7 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L8T11 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L12T15 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L0T3 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L4T7 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L8T11 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit8; + end; + + TPB0_TX_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_TXPWR_CBI_UPDT_L0T3 :bit1; + IGNR_TXPWR_CBI_UPDT_L4T7 :bit1; + IGNR_TXPWR_CBI_UPDT_L8T11 :bit1; + IGNR_TXPWR_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit4; + IGNR_COEFFICIENTID_CBI_UPDT_L0T3 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L4T7 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L8T11 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L12T15:bit1; + IGNR_COEFFICIENT_CBI_UPDT_L0T3 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L4T7 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L8T11 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L12T15 :bit1; + RESERVED1 :bit16; + end; + + TPB1_RX_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_RXPWR_CBI_UPDT_L0T3 :bit1; + IGNR_RXPWR_CBI_UPDT_L4T7 :bit1; + IGNR_RXPWR_CBI_UPDT_L8T11 :bit1; + IGNR_RXPWR_CBI_UPDT_L12T15 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11 :bit1; + IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15:bit1; + IGNR_REQUESTTRK_CBI_UPDT_L0T3 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L4T7 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L8T11 :bit1; + IGNR_REQUESTTRK_CBI_UPDT_L12T15 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L0T3 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L4T7 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L8T11 :bit1; + IGNR_ENABLEFOM_CBI_UPDT_L12T15 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L0T3 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L4T7 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L8T11 :bit1; + IGNR_REQUESTFOM_CBI_UPDT_L12T15 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L0T3 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L4T7 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L8T11 :bit1; + IGNR_RESPONSEMODE_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit8; + end; + + TPB1_TX_GLB_SCI_STAT_OVRD_REG0=bitpacked record + IGNR_TXPWR_CBI_UPDT_L0T3 :bit1; + IGNR_TXPWR_CBI_UPDT_L4T7 :bit1; + IGNR_TXPWR_CBI_UPDT_L8T11 :bit1; + IGNR_TXPWR_CBI_UPDT_L12T15 :bit1; + RESERVED0 :bit4; + IGNR_COEFFICIENTID_CBI_UPDT_L0T3 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L4T7 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L8T11 :bit1; + IGNR_COEFFICIENTID_CBI_UPDT_L12T15:bit1; + IGNR_COEFFICIENT_CBI_UPDT_L0T3 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L4T7 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L8T11 :bit1; + IGNR_COEFFICIENT_CBI_UPDT_L12T15 :bit1; + RESERVED1 :bit16; + end; + + TPCIE_ADV_ERR_RPT_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_0=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_1=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_2=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_3=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_4=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_5=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_6=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_DPA_SUBSTATE_PWR_ALLOC_7=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_LATENCY_INDICATOR=bitpacked record + TRANS_LAT_INDICATOR_BITS:bit8; + RESERVED0 :bit24; + end; + + TPCIE_LANE_0_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_1_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_2_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_3_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_4_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_5_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_6_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_7_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_8_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_9_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_PERF_COUNT0_SLV_NS_C_CLK=bit32; + + TPCIE_PERF_COUNT1_SLV_NS_C_CLK=bit32; + + TPCIE_RX_CREDITS_ALLOCATED_CPL=bitpacked record + RX_CREDITS_ALLOCATED_CPLD:bit12; + RESERVED0 :bit4; + RX_CREDITS_ALLOCATED_CPLH:bit8; + RESERVED1 :bit8; + end; + + TPCIE_TX_CREDITS_FCU_THRESHOLD=bitpacked record + TX_FCU_THRESHOLD_P_VC0 :bit3; + RESERVED0 :bit1; + TX_FCU_THRESHOLD_NP_VC0 :bit3; + RESERVED1 :bit1; + TX_FCU_THRESHOLD_CPL_VC0:bit3; + RESERVED2 :bit5; + TX_FCU_THRESHOLD_P_VC1 :bit3; + RESERVED3 :bit1; + TX_FCU_THRESHOLD_NP_VC1 :bit3; + RESERVED4 :bit1; + TX_FCU_THRESHOLD_CPL_VC1:bit3; + RESERVED5 :bit5; + end; + + TRLC_GPU_IOV_SDMA0_BUSY_STATUS=bit32; + + TRLC_GPU_IOV_SDMA1_BUSY_STATUS=bit32; + + TSCLV_MANUAL_REPLICATE_CONTROL=bitpacked record + SCL_V_MANUAL_REPLICATE_FACTOR:bit4; + RESERVED0 :bit4; + SCL_H_MANUAL_REPLICATE_FACTOR:bit4; + RESERVED1 :bit20; + end; + + TSCLV_VIEWPORT_START_SECONDARY=bitpacked record + VIEWPORT_Y_START_SECONDARY:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START_SECONDARY:bit14; + RESERVED1 :bit2; + end; + TSPI_RESOURCE_RESERVE_EN_CU_10=bitpacked record EN :bit1; TYPE_MASK :bit15; @@ -13543,6 +61260,89 @@ type RESERVED0 :bit7; end; + TUNP_LB_DATA_GAP_BETWEEN_CHUNK=bitpacked record + RESERVED0 :bit4; + UNP_LB_GAP_BETWEEN_CHUNK:bit5; + RESERVED1 :bit23; + end; + + TUVD_LMI_RBC_IB_64BIT_BAR_HIGH=bit32; + + TUVD_LMI_RBC_RB_64BIT_BAR_HIGH=bit32; + + TXDMA_MSTR_LOCAL_SURFACE_PITCH=bitpacked record + XDMA_MSTR_LOCAL_SURFACE_PITCH:bit14; + RESERVED0 :bit18; + end; + + TXDMA_MSTR_REMOTE_SURFACE_BASE=bit32; + + TAUX_GTC_SYNC_CONTROLLER_STATUS=bitpacked record + AUX_GTC_SYNC_LOCK_ACQ_COMPLETE :bit1; + RESERVED0 :bit3; + AUX_GTC_SYNC_LOCK_LOST :bit1; + RESERVED1 :bit3; + AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED :bit1; + AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE :bit4; + RESERVED2 :bit3; + AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL :bit1; + RESERVED3 :bit3; + AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED :bit1; + AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK :bit1; + AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED :bit1; + AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK:bit1; + AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED :bit1; + AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK :bit1; + RESERVED4 :bit2; + AUX_GTC_SYNC_CTRL_STATE :bit4; + end; + + TAZALIA_CONTROLLER_CLOCK_GATING=bitpacked record + ENABLE_CLOCK_GATING:bit1; + RESERVED0 :bit3; + CLOCK_ON_STATE :bit1; + RESERVED1 :bit27; + end; + + TAZALIA_F0_CODEC_ENDPOINT_INDEX=bitpacked record + AZALIA_ENDPOINT_REG_INDEX:bit14; + RESERVED0 :bit18; + end; + + TAZALIA_LATENCY_COUNTER_CONTROL=bitpacked record + AZALIA_LATENCY_COUNTER_RESET:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_UNDERFLOW_FILLER_SAMPLE=bit32; + + TAZALIA_WORSTCASE_LATENCY_COUNT=bit32; + + TBIF_RFE_CLIENT_SOFTRST_TRIGGER=bitpacked record + CLIENT0_RFE_RFEWDBIF_rst:bit1; + CLIENT1_RFE_RFEWDBIF_rst:bit1; + RESERVED0 :bit30; + end; + + TBIF_RFE_MASTER_SOFTRST_TRIGGER=bitpacked record + BU_rst :bit1; + RWREG_RFEWDBIF_rst:bit1; + SMBUS_rst :bit1; + BX_rst :bit1; + RESERVED0 :bit28; + end; + + TCHUB_ATC_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + TCOMPUTE_STATIC_THREAD_MGMT_SE0=bitpacked record SH0_CU_EN:bit16; SH1_CU_EN:bit16; @@ -13563,6 +61363,511 @@ type SH1_CU_EN:bit16; end; + TDCRX_PHY_MACRO_CNTL_RESERVED10=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED11=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED12=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED13=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED14=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED15=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED16=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED17=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED18=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED19=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED20=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED21=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED22=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED23=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED24=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED25=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED26=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED27=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED28=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED29=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED30=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED31=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED32=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED33=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED34=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED35=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED36=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED37=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED38=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED39=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED40=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED41=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED42=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED43=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED44=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED45=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED46=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED47=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED48=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED49=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED50=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED51=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED52=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED53=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED54=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED55=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED56=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED57=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED58=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED59=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED60=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED61=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED62=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED63=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED64=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED65=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED66=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED67=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED68=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED69=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED70=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED71=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED72=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED73=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED74=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED75=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED76=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED77=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED78=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED79=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED80=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED81=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED82=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED83=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED84=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED85=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED86=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED87=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED88=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED89=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED90=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED91=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED92=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED93=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED94=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED95=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED96=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED97=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED98=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED99=bit32; + + TDC_ABM1_HGLS_REG_READ_PROGRESS=bitpacked record + ABM1_HG_REG_READ_IN_PROGRESS :bit1; + ABM1_LS_REG_READ_IN_PROGRESS :bit1; + ABM1_BL_REG_READ_IN_PROGRESS :bit1; + RESERVED0 :bit5; + ABM1_HG_REG_READ_MISSED_FRAME :bit1; + ABM1_LS_REG_READ_MISSED_FRAME :bit1; + ABM1_BL_REG_READ_MISSED_FRAME :bit1; + RESERVED1 :bit5; + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR:bit1; + RESERVED2 :bit7; + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR:bit1; + RESERVED3 :bit6; + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR:bit1; + end; + + TDC_ABM1_HG_BIN_1_32_SHIFT_FLAG=bit32; + + TDC_ABM1_HG_BIN_1_8_SHIFT_INDEX=bit32; + + TDISP_INTERRUPT_STATUS_CONTINUE=bitpacked record + SCL_DISP2_MODE_CHANGE_INTERRUPT :bit1; + D2BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D2_VLINE_INTERRUPT :bit1; + LB_D2_VBLANK_INTERRUPT :bit1; + CRTC2_SNAPSHOT_INTERRUPT :bit1; + CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC2_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC2_TRIGA_INTERRUPT :bit1; + CRTC2_TRIGB_INTERRUPT :bit1; + CRTC2_VSYNC_NOM_INTERRUPT :bit1; + CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGB_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD2_INTERRUPT :bit1; + DC_HPD2_RX_INTERRUPT :bit1; + AUX2_SW_DONE_INTERRUPT :bit1; + AUX2_LS_DONE_INTERRUPT :bit1; + LB_D1_VLINE2_INTERRUPT :bit1; + LB_D2_VLINE2_INTERRUPT :bit1; + LB_D3_VLINE2_INTERRUPT :bit1; + RESERVED4 :bit1; + CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC1_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC1_VERTICAL_INTERRUPT0 :bit1; + CRTC1_VERTICAL_INTERRUPT1 :bit1; + CRTC1_VERTICAL_INTERRUPT2 :bit1; + DISP_INTERRUPT_STATUS_CONTINUE2 :bit1; + end; + + TDMCU_FW_CHECKSUM_SMPL_BYTE_POS=bitpacked record + DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS:bit2; + DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS:bit2; + RESERVED0 :bit28; + end; + + TDMCU_INTERRUPT_TO_HOST_EN_MASK=bitpacked record + ABM1_HG_READY_INT_MASK :bit1; + ABM1_LS_READY_INT_MASK :bit1; + ABM1_BL_UPDATE_INT_MASK :bit1; + RESERVED0 :bit1; + DCPG_IHC_DSI_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DSI_POWER_DOWN_INT_MASK :bit1; + RESERVED1 :bit3; + SCP_INT_MASK :bit1; + UC_INTERNAL_INT_MASK :bit1; + UC_REG_RD_TIMEOUT_INT_MASK :bit1; + DCPG_IHC_DCFE0_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE1_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE2_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE3_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE4_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE5_POWER_UP_INT_MASK :bit1; + DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK:bit1; + DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK:bit1; + DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK:bit1; + DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK:bit1; + DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK:bit1; + DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK:bit1; + RESERVED2 :bit8; + end; + + TDMCU_PERFMON_INTERRUPT_STATUS1=bitpacked record + DCI_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCI_PERFMON_COUNTER_OFF_INT_OCCURRED :bit1; + DCO_PERFMON_COUNTER_OFF_INT_OCCURRED :bit1; + DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_STATUS2=bitpacked record + DCFE0_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE1_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE2_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_STATUS3=bitpacked record + DCFE3_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE4_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFE5_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_STATUS4=bitpacked record + WB_PERFMON_COUNTER0_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER1_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER2_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER3_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER4_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER5_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER6_INT_OCCURRED :bit1; + WB_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER7_INT_OCCURRED :bit1; + RESERVED0 :bit8; + WB_PERFMON_COUNTER_OFF_INT_OCCURRED :bit1; + DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + RESERVED1 :bit6; + end; + + TDMCU_PERFMON_INTERRUPT_STATUS5=bitpacked record + DCFEV_PERFMON_COUNTER0_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER1_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER2_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER3_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER4_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER5_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER6_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER7_INT_OCCURRED :bit1; + DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED:bit1; + RESERVED0 :bit23; + end; + + TGARLIC_COHE_CP_DMA_PFP_COMMAND=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGARLIC_COHE_CP_DMA_PIO_COMMAND=bitpacked record + RESERVED0:bit2; + ADDRESS :bit17; + RESERVED1:bit13; + end; + + TGC_USER_SYS_RB_BACKEND_DISABLE=bitpacked record + RESERVED0 :bit16; + BACKEND_DISABLE:bit8; + RESERVED1 :bit8; + end; + + TGRPH_SECONDARY_SURFACE_ADDRESS=bitpacked record + GRPH_SECONDARY_DFQ_ENABLE :bit1; + RESERVED0 :bit7; + GRPH_SECONDARY_SURFACE_ADDRESS:bit24; + end; + + TMC_FUS_DRAM0_BANK_ADDR_MAPPING=bitpacked record + DIMM0ADDRMAP :bit4; + DIMM1ADDRMAP :bit4; + BANKSWIZZLEMODE:bit1; + BANKSWAP :bit1; + RESERVED0 :bit22; + end; + + TMC_FUS_DRAM1_BANK_ADDR_MAPPING=bitpacked record + DIMM0ADDRMAP :bit4; + DIMM1ADDRMAP :bit4; + BANKSWIZZLEMODE:bit1; + BANKSWAP :bit1; + RESERVED0 :bit22; + end; + + TMC_HUB_MISC_ATOMIC_IDLE_STATUS=bitpacked record + OUTSTANDING_GFX_ATOMIC :bit1; + OUTSTANDING_RLC_ATOMIC :bit1; + OUTSTANDING_SDMA0_ATOMIC :bit1; + OUTSTANDING_SDMA1_ATOMIC :bit1; + OUTSTANDING_DISP_ATOMIC :bit1; + OUTSTANDING_UVD_ATOMIC :bit1; + OUTSTANDING_SMU_ATOMIC :bit1; + OUTSTANDING_HDP_ATOMIC :bit1; + OUTSTANDING_OTH_ATOMIC :bit1; + OUTSTANDING_VMC_ATOMIC :bit1; + OUTSTANDING_VCE_ATOMIC :bit1; + OUTSTANDING_ACP_ATOMIC :bit1; + OUTSTANDING_SAMMSP_ATOMIC:bit1; + OUTSTANDING_XDMA_ATOMIC :bit1; + OUTSTANDING_ISP_ATOMIC :bit1; + OUTSTANDING_VP8_ATOMIC :bit1; + OUTSTANDING_VIN0_READ :bit1; + OUTSTANDING_VIN0_WRITE :bit1; + OUTSTANDING_VIN0_ATOMIC :bit1; + OUTSTANDING_TLS_READ :bit1; + OUTSTANDING_TLS_WRITE :bit1; + OUTSTANDING_TLS_ATOMIC :bit1; + RESERVED0 :bit10; + end; + + TMC_MCBVM_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_MCDVM_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_VM_L2_PERFCOUNTER_RSLT_CNTL=bitpacked record + PERF_COUNTER_SELECT :bit4; + RESERVED0 :bit4; + START_TRIGGER :bit8; + STOP_TRIGGER :bit8; + ENABLE_ANY :bit1; + CLEAR_ALL :bit1; + STOP_ALL_ON_SATURATE:bit1; + RESERVED1 :bit5; + end; + + TMC_VM_SYSTEM_APERTURE_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TOVL_SURFACE_ADDRESS_HIGH_INUSE=bitpacked record + OVL_SURFACE_ADDRESS_HIGH_INUSE:bit8; + RESERVED0 :bit24; + end; + TPA_SC_HP3D_TRAP_SCREEN_HV_LOCK=bitpacked record DISABLE_NON_PRIV_WRITES:bit1; RESERVED0 :bit31; @@ -13570,6 +61875,267 @@ type TPA_SU_POLY_OFFSET_FRONT_OFFSET=bit32; + TPB0_PLL_LC0_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC0_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC0_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB0_PLL_LC1_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC1_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC1_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB0_PLL_LC2_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC2_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC2_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB0_PLL_LC3_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC3_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC3_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB0_PLL_RO0_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO0_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO0_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO0_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO0_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB0_PLL_RO1_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO1_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO1_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO1_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO1_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB0_PLL_RO2_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO2_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO2_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO2_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO2_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB0_PLL_RO3_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO3_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO3_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO3_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO3_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB1_PLL_LC0_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC0_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC0_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB1_PLL_LC1_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC1_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC1_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB1_PLL_LC2_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC2_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC2_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB1_PLL_LC3_SCI_STAT_OVRD_REG0=bitpacked record + PLL_LC3_IGNR_PLLPWR_CBI_UPDT:bit1; + RESERVED0 :bit3; + PLL_LC3_PLLPWR :bit3; + RESERVED1 :bit25; + end; + + TPB1_PLL_RO0_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO0_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO0_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO0_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO0_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB1_PLL_RO1_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO1_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO1_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO1_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO1_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB1_PLL_RO2_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO2_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO2_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO2_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO2_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPB1_PLL_RO3_SCI_STAT_OVRD_REG0=bitpacked record + PLL_RO3_IGNR_PLLPWR_CBI_UPDT :bit1; + PLL_RO3_IGNR_PLLFREQ_CBI_UPDT:bit1; + RESERVED0 :bit2; + PLL_RO3_PLLPWR :bit3; + RESERVED1 :bit1; + PLL_RO3_PLLFREQ :bit2; + RESERVED2 :bit22; + end; + + TPCIEP_ERROR_INJECT_TRANSACTION=bitpacked record + ERROR_INJECT_TL_FLOW_CTL_ERR :bit2; + ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER:bit2; + ERROR_INJECT_TL_BAD_DLLP :bit2; + ERROR_INJECT_TL_BAD_TLP :bit2; + ERROR_INJECT_TL_UNSUPPORTED_REQ :bit2; + ERROR_INJECT_TL_ECRC_ERROR :bit2; + ERROR_INJECT_TL_MALFORMED_TLP :bit2; + ERROR_INJECT_TL_UNEXPECTED_CMPLT :bit2; + ERROR_INJECT_TL_COMPLETER_ABORT :bit2; + ERROR_INJECT_TL_COMPLETION_TIMEOUT :bit2; + RESERVED0 :bit12; + end; + + TPCIE_LANE_10_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_11_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_12_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_13_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_14_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_LANE_15_EQUALIZATION_CNTL=bitpacked record + DOWNSTREAM_PORT_TX_PRESET :bit4; + DOWNSTREAM_PORT_RX_PRESET_HINT:bit3; + RESERVED0 :bit1; + UPSTREAM_PORT_TX_PRESET :bit4; + UPSTREAM_PORT_RX_PRESET_HINT :bit3; + RESERVED1 :bit17; + end; + + TPCIE_PERF_CNTL_EVENT0_PORT_SEL=bitpacked record + PERF0_PORT_SEL_TXCLK :bit4; + PERF0_PORT_SEL_MST_R_CLK :bit4; + PERF0_PORT_SEL_MST_C_CLK :bit4; + PERF0_PORT_SEL_SLV_R_CLK :bit4; + PERF0_PORT_SEL_SLV_S_C_CLK :bit4; + PERF0_PORT_SEL_SLV_NS_C_CLK:bit4; + PERF0_PORT_SEL_TXCLK2 :bit4; + RESERVED0 :bit4; + end; + + TPCIE_PERF_CNTL_EVENT1_PORT_SEL=bitpacked record + PERF1_PORT_SEL_TXCLK :bit4; + PERF1_PORT_SEL_MST_R_CLK :bit4; + PERF1_PORT_SEL_MST_C_CLK :bit4; + PERF1_PORT_SEL_SLV_R_CLK :bit4; + PERF1_PORT_SEL_SLV_S_C_CLK :bit4; + PERF1_PORT_SEL_SLV_NS_C_CLK:bit4; + PERF1_PORT_SEL_TXCLK2 :bit4; + RESERVED0 :bit4; + end; + + TPCIE_SRIOV_SUPPORTED_PAGE_SIZE=bit32; + + TSCLV_HORZ_FILTER_SCALE_RATIO_C=bitpacked record + SCL_H_SCALE_RATIO_C:bit26; + RESERVED0 :bit6; + end; + + TSCLV_VERT_FILTER_SCALE_RATIO_C=bitpacked record + SCL_V_SCALE_RATIO_C:bit26; + RESERVED0 :bit6; + end; + + TSDMA0_GFX_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA0_GFX_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_SEM_WAIT_FAIL_TIMER_CNTL=bit32; + + TSDMA1_GFX_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA1_GFX_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_SEM_WAIT_FAIL_TIMER_CNTL=bit32; + + TSEM_MAILBOX_CLIENTCONFIG_EXTRA=bitpacked record + VCE1_CLIENT0:bit5; + RESERVED0 :bit27; + end; + TSPI_SX_SCOREBOARD_BUFFER_SIZES=bitpacked record COLOR_SCOREBOARD_SIZE :bit16; POSITION_SCOREBOARD_SIZE:bit16; @@ -13577,11 +62143,2010 @@ type TVGT_STRMOUT_DRAW_OPAQUE_OFFSET=bit32; + TVM_L2_BANK_SELECT_RESERVED_CID=bitpacked record + RESERVED_READ_CLIENT_ID :bit9; + RESERVED0 :bit1; + RESERVED_WRITE_CLIENT_ID :bit9; + RESERVED1 :bit1; + ENABLE :bit1; + RESERVED2 :bit3; + RESERVED_CACHE_INVALIDATION_MODE :bit1; + RESERVED_CACHE_PRIVATE_INVALIDATION:bit1; + RESERVED3 :bit6; + end; + + TXDMA_MSTR_CACHE_BASE_ADDR_HIGH=bitpacked record + XDMA_MSTR_CACHE_BASE_ADDR_HIGH:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_CUMULATIVE_LATENCY_COUNT=bit32; + + TAZALIA_CUMULATIVE_REQUEST_COUNT=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_HBR=bitpacked record + HBR_CAPABLE:bit1; + RESERVED0 :bit3; + HBR_ENABLE :bit1; + RESERVED1 :bit27; + end; + + TAZALIA_INPUT_PAYLOAD_CAPABILITY=bitpacked record + INPUT_PAYLOAD_CAPABILITY:bit16; + INSTRMPAY :bit16; + end; + + TCRTC_EXT_TIMING_SYNC_WINDOW_END=bitpacked record + CRTC_EXT_TIMING_SYNC_WINDOW_END_X:bit14; + RESERVED0 :bit2; + CRTC_EXT_TIMING_SYNC_WINDOW_END_Y:bit14; + RESERVED1 :bit2; + end; + + TCRTC_VGA_PARAMETER_CAPTURE_MODE=bitpacked record + CRTC_VGA_PARAMETER_CAPTURE_MODE:bit1; + RESERVED0 :bit31; + end; + + TDCRX_PHY_MACRO_CNTL_RESERVED100=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED101=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED102=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED103=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED104=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED105=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED106=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED107=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED108=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED109=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED110=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED111=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED112=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED113=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED114=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED115=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED116=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED117=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED118=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED119=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED120=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED121=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED122=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED123=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED124=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED125=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED126=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED127=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED128=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED129=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED130=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED131=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED132=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED133=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED134=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED135=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED136=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED137=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED138=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED139=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED140=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED141=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED142=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED143=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED144=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED145=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED146=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED147=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED148=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED149=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED150=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED151=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED152=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED153=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED154=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED155=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED156=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED157=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED158=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED159=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED160=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED161=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED162=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED163=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED164=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED165=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED166=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED167=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED168=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED169=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED170=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED171=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED172=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED173=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED174=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED175=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED176=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED177=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED178=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED179=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED180=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED181=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED182=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED183=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED184=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED185=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED186=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED187=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED188=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED189=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED190=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED191=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED192=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED193=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED194=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED195=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED196=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED197=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED198=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED199=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED200=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED201=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED202=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED203=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED204=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED205=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED206=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED207=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED208=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED209=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED210=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED211=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED212=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED213=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED214=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED215=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED216=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED217=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED218=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED219=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED220=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED221=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED222=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED223=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED224=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED225=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED226=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED227=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED228=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED229=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED230=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED231=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED232=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED233=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED234=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED235=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED236=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED237=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED238=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED239=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED240=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED241=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED242=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED243=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED244=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED245=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED246=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED247=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED248=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED249=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED250=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED251=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED252=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED253=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED254=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED255=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED256=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED257=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED258=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED259=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED260=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED261=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED262=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED263=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED264=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED265=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED266=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED267=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED268=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED269=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED270=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED271=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED272=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED273=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED274=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED275=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED276=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED277=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED278=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED279=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED280=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED281=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED282=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED283=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED284=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED285=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED286=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED287=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED288=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED289=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED290=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED291=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED292=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED293=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED294=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED295=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED296=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED297=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED298=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED299=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED300=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED301=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED302=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED303=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED304=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED305=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED306=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED307=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED308=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED309=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED310=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED311=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED312=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED313=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED314=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED315=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED316=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED317=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED318=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED319=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED320=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED321=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED322=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED323=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED324=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED325=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED326=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED327=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED328=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED329=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED330=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED331=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED332=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED333=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED334=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED335=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED336=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED337=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED338=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED339=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED340=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED341=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED342=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED343=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED344=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED345=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED346=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED347=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED348=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED349=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED350=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED351=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED352=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED353=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED354=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED355=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED356=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED357=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED358=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED359=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED360=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED361=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED362=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED363=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED364=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED365=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED366=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED367=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED368=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED369=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED370=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED371=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED372=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED373=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED374=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED375=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED376=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED377=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED378=bit32; + + TDCRX_PHY_MACRO_CNTL_RESERVED379=bit32; + + TDC_ABM1_HG_BIN_9_16_SHIFT_INDEX=bit32; + + TDISP_INTERRUPT_STATUS_CONTINUE2=bitpacked record + SCL_DISP3_MODE_CHANGE_INTERRUPT :bit1; + D3BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D3_VLINE_INTERRUPT :bit1; + LB_D3_VBLANK_INTERRUPT :bit1; + CRTC3_SNAPSHOT_INTERRUPT :bit1; + CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC3_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC3_TRIGA_INTERRUPT :bit1; + CRTC3_TRIGB_INTERRUPT :bit1; + CRTC3_VSYNC_NOM_INTERRUPT :bit1; + CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGC_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD3_INTERRUPT :bit1; + DC_HPD3_RX_INTERRUPT :bit1; + AUX3_SW_DONE_INTERRUPT :bit1; + AUX3_LS_DONE_INTERRUPT :bit1; + LB_D4_VLINE2_INTERRUPT :bit1; + LB_D5_VLINE2_INTERRUPT :bit1; + LB_D6_VLINE2_INTERRUPT :bit1; + RESERVED4 :bit1; + CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC2_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC2_VERTICAL_INTERRUPT0 :bit1; + CRTC2_VERTICAL_INTERRUPT1 :bit1; + CRTC2_VERTICAL_INTERRUPT2 :bit1; + DISP_INTERRUPT_STATUS_CONTINUE3 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE3=bitpacked record + SCL_DISP4_MODE_CHANGE_INTERRUPT :bit1; + D4BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D4_VLINE_INTERRUPT :bit1; + LB_D4_VBLANK_INTERRUPT :bit1; + CRTC4_SNAPSHOT_INTERRUPT :bit1; + CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC4_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC4_TRIGA_INTERRUPT :bit1; + CRTC4_TRIGB_INTERRUPT :bit1; + CRTC4_VSYNC_NOM_INTERRUPT :bit1; + CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGD_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD4_INTERRUPT :bit1; + DC_HPD4_RX_INTERRUPT :bit1; + AUX4_SW_DONE_INTERRUPT :bit1; + AUX4_LS_DONE_INTERRUPT :bit1; + BUFMGR_IHIF_INTERRUPT :bit1; + WBSCL_HOST_CONFLICT_INTERRUPT :bit1; + WBSCL_DATA_OVERFLOW_INTERRUPT :bit1; + RESERVED4 :bit1; + CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC3_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC3_VERTICAL_INTERRUPT0 :bit1; + CRTC3_VERTICAL_INTERRUPT1 :bit1; + CRTC3_VERTICAL_INTERRUPT2 :bit1; + DISP_INTERRUPT_STATUS_CONTINUE4 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE4=bitpacked record + SCL_DISP5_MODE_CHANGE_INTERRUPT :bit1; + D5BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D5_VLINE_INTERRUPT :bit1; + LB_D5_VBLANK_INTERRUPT :bit1; + CRTC5_SNAPSHOT_INTERRUPT :bit1; + CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC5_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC5_TRIGA_INTERRUPT :bit1; + CRTC5_TRIGB_INTERRUPT :bit1; + CRTC5_VSYNC_NOM_INTERRUPT :bit1; + CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGE_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD5_INTERRUPT :bit1; + DC_HPD5_RX_INTERRUPT :bit1; + AUX5_SW_DONE_INTERRUPT :bit1; + AUX5_LS_DONE_INTERRUPT :bit1; + RESERVED4 :bit1; + CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC4_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC5_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC4_VERTICAL_INTERRUPT0 :bit1; + CRTC4_VERTICAL_INTERRUPT1 :bit1; + CRTC4_VERTICAL_INTERRUPT2 :bit1; + DISP_INTERRUPT_STATUS_CONTINUE5 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE5=bitpacked record + SCL_DISP6_MODE_CHANGE_INTERRUPT :bit1; + D6BLND_DATA_UNDERFLOW_INTERRUPT :bit1; + LB_D6_VLINE_INTERRUPT :bit1; + LB_D6_VBLANK_INTERRUPT :bit1; + CRTC6_SNAPSHOT_INTERRUPT :bit1; + CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT :bit1; + CRTC6_FORCE_COUNT_NOW_INTERRUPT :bit1; + CRTC6_TRIGA_INTERRUPT :bit1; + CRTC6_TRIGB_INTERRUPT :bit1; + CRTC6_VSYNC_NOM_INTERRUPT :bit1; + CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGF_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + DC_HPD6_INTERRUPT :bit1; + DC_HPD6_RX_INTERRUPT :bit1; + AUX6_SW_DONE_INTERRUPT :bit1; + AUX6_LS_DONE_INTERRUPT :bit1; + RESERVED4 :bit1; + CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT :bit1; + CRTC6_EXT_TIMING_SYNC_INTERRUPT :bit1; + CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT :bit1; + CRTC5_VERTICAL_INTERRUPT0 :bit1; + CRTC5_VERTICAL_INTERRUPT1 :bit1; + CRTC5_VERTICAL_INTERRUPT2 :bit1; + CRTC6_VERTICAL_INTERRUPT0 :bit1; + CRTC6_VERTICAL_INTERRUPT1 :bit1; + CRTC6_VERTICAL_INTERRUPT2 :bit1; + DISP_INTERRUPT_STATUS_CONTINUE6 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE6=bitpacked record + DCRX_PERFMON_COUNTER0_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER1_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER2_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER3_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER4_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER5_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER6_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER7_INTERRUPT :bit1; + DCRX_PERFMON_COUNTER_OFF_INTERRUPT :bit1; + BUFMGR_CWB0_IHIF_INTERRUPT :bit1; + BUFMGR_CWB1_IHIF_INTERRUPT :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + RESERVED3 :bit1; + DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT:bit1; + DIGG_DP_VID_STREAM_DISABLE_INTERRUPT :bit1; + AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX1_GTC_SYNC_ERROR_INTERRUPT :bit1; + AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX2_GTC_SYNC_ERROR_INTERRUPT :bit1; + AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX3_GTC_SYNC_ERROR_INTERRUPT :bit1; + AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX4_GTC_SYNC_ERROR_INTERRUPT :bit1; + AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX5_GTC_SYNC_ERROR_INTERRUPT :bit1; + AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT :bit1; + AUX6_GTC_SYNC_ERROR_INTERRUPT :bit1; + RESERVED4 :bit2; + DISP_INTERRUPT_STATUS_CONTINUE7 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE7=bitpacked record + DCCG_PERFMON_COUNTER0_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER1_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER2_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER3_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER4_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER5_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER6_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER7_INTERRUPT :bit1; + DCCG_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + DCI_PERFMON_COUNTER0_INTERRUPT :bit1; + DCI_PERFMON_COUNTER1_INTERRUPT :bit1; + DCI_PERFMON_COUNTER2_INTERRUPT :bit1; + DCI_PERFMON_COUNTER3_INTERRUPT :bit1; + DCI_PERFMON_COUNTER4_INTERRUPT :bit1; + DCI_PERFMON_COUNTER5_INTERRUPT :bit1; + DCI_PERFMON_COUNTER6_INTERRUPT :bit1; + DCI_PERFMON_COUNTER7_INTERRUPT :bit1; + DCI_PERFMON_COUNTER_OFF_INTERRUPT :bit1; + DCO_PERFMON_COUNTER0_INTERRUPT :bit1; + DCO_PERFMON_COUNTER1_INTERRUPT :bit1; + DCO_PERFMON_COUNTER2_INTERRUPT :bit1; + DCO_PERFMON_COUNTER3_INTERRUPT :bit1; + DCO_PERFMON_COUNTER4_INTERRUPT :bit1; + DCO_PERFMON_COUNTER5_INTERRUPT :bit1; + DCO_PERFMON_COUNTER6_INTERRUPT :bit1; + DCO_PERFMON_COUNTER7_INTERRUPT :bit1; + DCO_PERFMON_COUNTER_OFF_INTERRUPT :bit1; + WB_PERFMON_COUNTER0_INTERRUPT :bit1; + WB_PERFMON_COUNTER1_INTERRUPT :bit1; + WB_PERFMON_COUNTER2_INTERRUPT :bit1; + WB_PERFMON_COUNTER3_INTERRUPT :bit1; + DISP_INTERRUPT_STATUS_CONTINUE8 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE8=bitpacked record + DCFE0_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE0_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + DCFE1_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE1_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + DCFE2_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE2_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + WB_PERFMON_COUNTER4_INTERRUPT :bit1; + WB_PERFMON_COUNTER5_INTERRUPT :bit1; + WB_PERFMON_COUNTER6_INTERRUPT :bit1; + WB_PERFMON_COUNTER7_INTERRUPT :bit1; + DISP_INTERRUPT_STATUS_CONTINUE9 :bit1; + end; + + TDISP_INTERRUPT_STATUS_CONTINUE9=bitpacked record + DCFE3_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE3_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + DCFE4_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE4_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + DCFE5_PERFMON_COUNTER0_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER1_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER2_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER3_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER4_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER5_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER6_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER7_INTERRUPT :bit1; + DCFE5_PERFMON_COUNTER_OFF_INTERRUPT:bit1; + WB_PERFMON_COUNTER_OFF_INTERRUPT :bit1; + RESERVED0 :bit4; + end; + + TDMA_POSITION_LOWER_BASE_ADDRESS=bitpacked record + DMA_POSITION_BUFFER_ENABLE :bit1; + DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS:bit6; + DMA_POSITION_LOWER_BASE_ADDRESS :bit25; + end; + + TDMA_POSITION_UPPER_BASE_ADDRESS=bit32; + + TGRPH_SURFACE_ADDRESS_HIGH_INUSE=bitpacked record + GRPH_SURFACE_ADDRESS_HIGH_INUSE:bit8; + RESERVED0 :bit24; + end; + + TINPUT_STREAM_PAYLOAD_CAPABILITY=bitpacked record + INSTRMPAY:bit16; + RESERVED0:bit16; + end; + + TMC_VM_SYSTEM_APERTURE_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TMC_XPB_MAP_INVERT_FLUSH_NUM_LSB=bitpacked record + ALTER_FLUSH_NUM:bit16; + RESERVED0 :bit16; + end; + + TOUTPUT_STREAM_DESCRIPTOR_FORMAT=bitpacked record + NUMBER_OF_CHANNELS :bit4; + BITS_PER_SAMPLE :bit3; + RESERVED0 :bit1; + SAMPLE_BASE_DIVISOR :bit3; + SAMPLE_BASE_MULTIPLE:bit3; + SAMPLE_BASE_RATE :bit1; + RESERVED1 :bit17; + end; + + TPB0_RX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_0 :bit3; + ELECIDLEDETEN_0:bit1; + RESERVED0 :bit2; + REQUESTTRK_0 :bit1; + ENABLEFOM_0 :bit1; + REQUESTFOM_0 :bit1; + RESPONSEMODE_0 :bit1; + RXEYEFOM_0 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_1 :bit3; + ELECIDLEDETEN_1:bit1; + RESERVED0 :bit2; + REQUESTTRK_1 :bit1; + ENABLEFOM_1 :bit1; + REQUESTFOM_1 :bit1; + RESPONSEMODE_1 :bit1; + RXEYEFOM_1 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_2 :bit3; + ELECIDLEDETEN_2:bit1; + RESERVED0 :bit2; + REQUESTTRK_2 :bit1; + ENABLEFOM_2 :bit1; + REQUESTFOM_2 :bit1; + RESPONSEMODE_2 :bit1; + RXEYEFOM_2 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_3 :bit3; + ELECIDLEDETEN_3:bit1; + RESERVED0 :bit2; + REQUESTTRK_3 :bit1; + ENABLEFOM_3 :bit1; + REQUESTFOM_3 :bit1; + RESPONSEMODE_3 :bit1; + RXEYEFOM_3 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_4 :bit3; + ELECIDLEDETEN_4:bit1; + RESERVED0 :bit2; + REQUESTTRK_4 :bit1; + ENABLEFOM_4 :bit1; + REQUESTFOM_4 :bit1; + RESPONSEMODE_4 :bit1; + RXEYEFOM_4 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_5 :bit3; + ELECIDLEDETEN_5:bit1; + RESERVED0 :bit2; + REQUESTTRK_5 :bit1; + ENABLEFOM_5 :bit1; + REQUESTFOM_5 :bit1; + RESPONSEMODE_5 :bit1; + RXEYEFOM_5 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_6 :bit3; + ELECIDLEDETEN_6:bit1; + RESERVED0 :bit2; + REQUESTTRK_6 :bit1; + ENABLEFOM_6 :bit1; + REQUESTFOM_6 :bit1; + RESPONSEMODE_6 :bit1; + RXEYEFOM_6 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_7 :bit3; + ELECIDLEDETEN_7:bit1; + RESERVED0 :bit2; + REQUESTTRK_7 :bit1; + ENABLEFOM_7 :bit1; + REQUESTFOM_7 :bit1; + RESPONSEMODE_7 :bit1; + RXEYEFOM_7 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_8 :bit3; + ELECIDLEDETEN_8:bit1; + RESERVED0 :bit2; + REQUESTTRK_8 :bit1; + ENABLEFOM_8 :bit1; + REQUESTFOM_8 :bit1; + RESPONSEMODE_8 :bit1; + RXEYEFOM_8 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_9 :bit3; + ELECIDLEDETEN_9:bit1; + RESERVED0 :bit2; + REQUESTTRK_9 :bit1; + ENABLEFOM_9 :bit1; + REQUESTFOM_9 :bit1; + RESPONSEMODE_9 :bit1; + RXEYEFOM_9 :bit8; + RESERVED1 :bit14; + end; + + TPB0_TX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_0 :bit3; + INCOHERENTCK_0 :bit1; + TXMARG_0 :bit3; + DEEMPH_0 :bit1; + COEFFICIENTID_0:bit2; + COEFFICIENT_0 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_1 :bit3; + INCOHERENTCK_1 :bit1; + TXMARG_1 :bit3; + DEEMPH_1 :bit1; + COEFFICIENTID_1:bit2; + COEFFICIENT_1 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_2 :bit3; + INCOHERENTCK_2 :bit1; + TXMARG_2 :bit3; + DEEMPH_2 :bit1; + COEFFICIENTID_2:bit2; + COEFFICIENT_2 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_3 :bit3; + INCOHERENTCK_3 :bit1; + TXMARG_3 :bit3; + DEEMPH_3 :bit1; + COEFFICIENTID_3:bit2; + COEFFICIENT_3 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_4 :bit3; + INCOHERENTCK_4 :bit1; + TXMARG_4 :bit3; + DEEMPH_4 :bit1; + COEFFICIENTID_4:bit2; + COEFFICIENT_4 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_5 :bit3; + INCOHERENTCK_5 :bit1; + TXMARG_5 :bit3; + DEEMPH_5 :bit1; + COEFFICIENTID_5:bit2; + COEFFICIENT_5 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_6 :bit3; + INCOHERENTCK_6 :bit1; + TXMARG_6 :bit3; + DEEMPH_6 :bit1; + COEFFICIENTID_6:bit2; + COEFFICIENT_6 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_7 :bit3; + INCOHERENTCK_7 :bit1; + TXMARG_7 :bit3; + DEEMPH_7 :bit1; + COEFFICIENTID_7:bit2; + COEFFICIENT_7 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_8 :bit3; + INCOHERENTCK_8 :bit1; + TXMARG_8 :bit3; + DEEMPH_8 :bit1; + COEFFICIENTID_8:bit2; + COEFFICIENT_8 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_9 :bit3; + INCOHERENTCK_9 :bit1; + TXMARG_9 :bit3; + DEEMPH_9 :bit1; + COEFFICIENTID_9:bit2; + COEFFICIENT_9 :bit6; + RESERVED0 :bit16; + end; + + TPB1_RX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_0 :bit3; + ELECIDLEDETEN_0:bit1; + RESERVED0 :bit2; + REQUESTTRK_0 :bit1; + ENABLEFOM_0 :bit1; + REQUESTFOM_0 :bit1; + RESPONSEMODE_0 :bit1; + RXEYEFOM_0 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_1 :bit3; + ELECIDLEDETEN_1:bit1; + RESERVED0 :bit2; + REQUESTTRK_1 :bit1; + ENABLEFOM_1 :bit1; + REQUESTFOM_1 :bit1; + RESPONSEMODE_1 :bit1; + RXEYEFOM_1 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_2 :bit3; + ELECIDLEDETEN_2:bit1; + RESERVED0 :bit2; + REQUESTTRK_2 :bit1; + ENABLEFOM_2 :bit1; + REQUESTFOM_2 :bit1; + RESPONSEMODE_2 :bit1; + RXEYEFOM_2 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_3 :bit3; + ELECIDLEDETEN_3:bit1; + RESERVED0 :bit2; + REQUESTTRK_3 :bit1; + ENABLEFOM_3 :bit1; + REQUESTFOM_3 :bit1; + RESPONSEMODE_3 :bit1; + RXEYEFOM_3 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_4 :bit3; + ELECIDLEDETEN_4:bit1; + RESERVED0 :bit2; + REQUESTTRK_4 :bit1; + ENABLEFOM_4 :bit1; + REQUESTFOM_4 :bit1; + RESPONSEMODE_4 :bit1; + RXEYEFOM_4 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_5 :bit3; + ELECIDLEDETEN_5:bit1; + RESERVED0 :bit2; + REQUESTTRK_5 :bit1; + ENABLEFOM_5 :bit1; + REQUESTFOM_5 :bit1; + RESPONSEMODE_5 :bit1; + RXEYEFOM_5 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_6 :bit3; + ELECIDLEDETEN_6:bit1; + RESERVED0 :bit2; + REQUESTTRK_6 :bit1; + ENABLEFOM_6 :bit1; + REQUESTFOM_6 :bit1; + RESPONSEMODE_6 :bit1; + RXEYEFOM_6 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_7 :bit3; + ELECIDLEDETEN_7:bit1; + RESERVED0 :bit2; + REQUESTTRK_7 :bit1; + ENABLEFOM_7 :bit1; + REQUESTFOM_7 :bit1; + RESPONSEMODE_7 :bit1; + RXEYEFOM_7 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_8 :bit3; + ELECIDLEDETEN_8:bit1; + RESERVED0 :bit2; + REQUESTTRK_8 :bit1; + ENABLEFOM_8 :bit1; + REQUESTFOM_8 :bit1; + RESPONSEMODE_8 :bit1; + RXEYEFOM_8 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_9 :bit3; + ELECIDLEDETEN_9:bit1; + RESERVED0 :bit2; + REQUESTTRK_9 :bit1; + ENABLEFOM_9 :bit1; + REQUESTFOM_9 :bit1; + RESPONSEMODE_9 :bit1; + RXEYEFOM_9 :bit8; + RESERVED1 :bit14; + end; + + TPB1_TX_LANE0_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_0 :bit3; + INCOHERENTCK_0 :bit1; + TXMARG_0 :bit3; + DEEMPH_0 :bit1; + COEFFICIENTID_0:bit2; + COEFFICIENT_0 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE1_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_1 :bit3; + INCOHERENTCK_1 :bit1; + TXMARG_1 :bit3; + DEEMPH_1 :bit1; + COEFFICIENTID_1:bit2; + COEFFICIENT_1 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE2_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_2 :bit3; + INCOHERENTCK_2 :bit1; + TXMARG_2 :bit3; + DEEMPH_2 :bit1; + COEFFICIENTID_2:bit2; + COEFFICIENT_2 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE3_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_3 :bit3; + INCOHERENTCK_3 :bit1; + TXMARG_3 :bit3; + DEEMPH_3 :bit1; + COEFFICIENTID_3:bit2; + COEFFICIENT_3 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE4_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_4 :bit3; + INCOHERENTCK_4 :bit1; + TXMARG_4 :bit3; + DEEMPH_4 :bit1; + COEFFICIENTID_4:bit2; + COEFFICIENT_4 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE5_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_5 :bit3; + INCOHERENTCK_5 :bit1; + TXMARG_5 :bit3; + DEEMPH_5 :bit1; + COEFFICIENTID_5:bit2; + COEFFICIENT_5 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE6_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_6 :bit3; + INCOHERENTCK_6 :bit1; + TXMARG_6 :bit3; + DEEMPH_6 :bit1; + COEFFICIENTID_6:bit2; + COEFFICIENT_6 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE7_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_7 :bit3; + INCOHERENTCK_7 :bit1; + TXMARG_7 :bit3; + DEEMPH_7 :bit1; + COEFFICIENTID_7:bit2; + COEFFICIENT_7 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE8_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_8 :bit3; + INCOHERENTCK_8 :bit1; + TXMARG_8 :bit3; + DEEMPH_8 :bit1; + COEFFICIENTID_8:bit2; + COEFFICIENT_8 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE9_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_9 :bit3; + INCOHERENTCK_9 :bit1; + TXMARG_9 :bit3; + DEEMPH_9 :bit1; + COEFFICIENTID_9:bit2; + COEFFICIENT_9 :bit6; + RESERVED0 :bit16; + end; + + TPCIE_OUTSTAND_PAGE_REQ_CAPACITY=bit32; + + TPCIE_VENDOR_SPECIFIC_HDR_GPUIOV=bitpacked record + VSEC_ID :bit16; + VSEC_REV :bit4; + VSEC_LENGTH:bit12; + end; + + TPCIE_WRAP_TURNAROUND_DAISYCHAIN=bitpacked record + END_BIFCORE_REGISTER_DAISYCHAIN:bit1; + END_WRAPPER_REGISTER_DAISYCHAIN:bit1; + RESERVED0 :bit30; + end; + + TRLC_SERDES_WR_NONCU_MASTER_MASK=bitpacked record + SE_MASTER_MASK :bit16; + GC_MASTER_MASK :bit1; + GC_GFX_MASTER_MASK:bit1; + TC0_MASTER_MASK :bit1; + TC1_MASTER_MASK :bit1; + SPARE0_MASTER_MASK:bit1; + SPARE1_MASTER_MASK:bit1; + SPARE2_MASTER_MASK:bit1; + SPARE3_MASTER_MASK:bit1; + RESERVED :bit8; + end; + + TRLC_SPM_CB_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_DB_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_IA_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_PA_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_SC_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_SX_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_TA_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_TD_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TSCLV_VIEWPORT_START_SECONDARY_C=bitpacked record + VIEWPORT_Y_START_SECONDARY_C:bit14; + RESERVED0 :bit2; + VIEWPORT_X_START_SECONDARY_C:bit14; + RESERVED1 :bit2; + end; + + TSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI=bit32; + + TSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO=bitpacked record + RESERVED0:bit2; + ADDR :bit30; + end; + + TSQ_THREAD_TRACE_WORD_REG_1_OF_2=bitpacked record + TOKEN_TYPE :bit4; + TIME_DELTA :bit1; + PIPE_ID :bit2; + ME_ID :bit2; + REG_DROPPED_PREV:bit1; + REG_TYPE :bit3; + RESERVED0 :bit1; + REG_PRIV :bit1; + REG_OP :bit1; + REG_ADDR :bit16; + end; + + TSQ_THREAD_TRACE_WORD_REG_2_OF_2=bit32; + + TSQ_THREAD_TRACE_WORD_WAVE_START=bitpacked record + TOKEN_TYPE :bit4; + TIME_DELTA :bit1; + SH_ID :bit1; + CU_ID :bit4; + WAVE_ID :bit4; + SIMD_ID :bit2; + DISPATCHER :bit5; + VS_NO_ALLOC_OR_GROUPED:bit1; + COUNT :bit7; + TG_ID :bit3; + end; + + TVM_CONTEXT0_PAGE_TABLE_END_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT1_PAGE_TABLE_END_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_L2_BANK_SELECT_RESERVED_CID2=bitpacked record + RESERVED_READ_CLIENT_ID :bit9; + RESERVED0 :bit1; + RESERVED_WRITE_CLIENT_ID :bit9; + RESERVED1 :bit1; + ENABLE :bit1; + RESERVED2 :bit3; + RESERVED_CACHE_INVALIDATION_MODE :bit1; + RESERVED_CACHE_PRIVATE_INVALIDATION:bit1; + RESERVED3 :bit6; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_LPIB=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_LPIB=bit32; + + TAZALIA_OUTPUT_PAYLOAD_CAPABILITY=bitpacked record + OUTPUT_PAYLOAD_CAPABILITY:bit16; + OUTSTRMPAY :bit16; + end; + + TCRTC_VERTICAL_INTERRUPT0_CONTROL=bitpacked record + RESERVED0 :bit4; + CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY:bit1; + RESERVED1 :bit3; + CRTC_VERTICAL_INTERRUPT0_INT_ENABLE :bit1; + RESERVED2 :bit3; + CRTC_VERTICAL_INTERRUPT0_STATUS :bit1; + RESERVED3 :bit3; + CRTC_VERTICAL_INTERRUPT0_INT_STATUS :bit1; + RESERVED4 :bit3; + CRTC_VERTICAL_INTERRUPT0_CLEAR :bit1; + RESERVED5 :bit3; + CRTC_VERTICAL_INTERRUPT0_INT_TYPE :bit1; + RESERVED6 :bit7; + end; + + TCRTC_VERTICAL_INTERRUPT1_CONTROL=bitpacked record + RESERVED0 :bit8; + CRTC_VERTICAL_INTERRUPT1_INT_ENABLE:bit1; + RESERVED1 :bit3; + CRTC_VERTICAL_INTERRUPT1_STATUS :bit1; + RESERVED2 :bit3; + CRTC_VERTICAL_INTERRUPT1_INT_STATUS:bit1; + RESERVED3 :bit3; + CRTC_VERTICAL_INTERRUPT1_CLEAR :bit1; + RESERVED4 :bit3; + CRTC_VERTICAL_INTERRUPT1_INT_TYPE :bit1; + RESERVED5 :bit7; + end; + + TCRTC_VERTICAL_INTERRUPT2_CONTROL=bitpacked record + RESERVED0 :bit8; + CRTC_VERTICAL_INTERRUPT2_INT_ENABLE:bit1; + RESERVED1 :bit3; + CRTC_VERTICAL_INTERRUPT2_STATUS :bit1; + RESERVED2 :bit3; + CRTC_VERTICAL_INTERRUPT2_INT_STATUS:bit1; + RESERVED3 :bit3; + CRTC_VERTICAL_INTERRUPT2_CLEAR :bit1; + RESERVED4 :bit3; + CRTC_VERTICAL_INTERRUPT2_INT_TYPE :bit1; + RESERVED5 :bit7; + end; + + TDC_ABM1_HG_BIN_17_24_SHIFT_INDEX=bit32; + + TDC_ABM1_HG_BIN_25_32_SHIFT_INDEX=bit32; + + TDC_ABM1_LS_FILTERED_MIN_MAX_LUMA=bitpacked record + ABM1_LS_FILTERED_MIN_LUMA:bit10; + RESERVED0 :bit6; + ABM1_LS_FILTERED_MAX_LUMA:bit10; + RESERVED1 :bit6; + end; + + TDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT=bitpacked record + ABM1_LS_MAX_PIXEL_VALUE_COUNT:bit24; + RESERVED0 :bit8; + end; + + TDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT=bitpacked record + ABM1_LS_MIN_PIXEL_VALUE_COUNT:bit24; + RESERVED0 :bit8; + end; + + TOUTPUT_STREAM_PAYLOAD_CAPABILITY=bitpacked record + OUTSTRMPAY:bit16; + RESERVED0 :bit16; + end; + TPA_SC_P3D_TRAP_SCREEN_OCCURRENCE=bitpacked record COUNT :bit16; RESERVED0:bit16; end; + TPB0_RX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_10 :bit3; + ELECIDLEDETEN_10:bit1; + RESERVED0 :bit2; + REQUESTTRK_10 :bit1; + ENABLEFOM_10 :bit1; + REQUESTFOM_10 :bit1; + RESPONSEMODE_10 :bit1; + RXEYEFOM_10 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_11 :bit3; + ELECIDLEDETEN_11:bit1; + RESERVED0 :bit2; + REQUESTTRK_11 :bit1; + ENABLEFOM_11 :bit1; + REQUESTFOM_11 :bit1; + RESPONSEMODE_11 :bit1; + RXEYEFOM_11 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_12 :bit3; + ELECIDLEDETEN_12:bit1; + RESERVED0 :bit2; + REQUESTTRK_12 :bit1; + ENABLEFOM_12 :bit1; + REQUESTFOM_12 :bit1; + RESPONSEMODE_12 :bit1; + RXEYEFOM_12 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_13 :bit3; + ELECIDLEDETEN_13:bit1; + RESERVED0 :bit2; + REQUESTTRK_13 :bit1; + ENABLEFOM_13 :bit1; + REQUESTFOM_13 :bit1; + RESPONSEMODE_13 :bit1; + RXEYEFOM_13 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_14 :bit3; + ELECIDLEDETEN_14:bit1; + RESERVED0 :bit2; + REQUESTTRK_14 :bit1; + ENABLEFOM_14 :bit1; + REQUESTFOM_14 :bit1; + RESPONSEMODE_14 :bit1; + RXEYEFOM_14 :bit8; + RESERVED1 :bit14; + end; + + TPB0_RX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_15 :bit3; + ELECIDLEDETEN_15:bit1; + RESERVED0 :bit2; + REQUESTTRK_15 :bit1; + ENABLEFOM_15 :bit1; + REQUESTFOM_15 :bit1; + RESPONSEMODE_15 :bit1; + RXEYEFOM_15 :bit8; + RESERVED1 :bit14; + end; + + TPB0_TX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_10 :bit3; + INCOHERENTCK_10 :bit1; + TXMARG_10 :bit3; + DEEMPH_10 :bit1; + COEFFICIENTID_10:bit2; + COEFFICIENT_10 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_11 :bit3; + INCOHERENTCK_11 :bit1; + TXMARG_11 :bit3; + DEEMPH_11 :bit1; + COEFFICIENTID_11:bit2; + COEFFICIENT_11 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_12 :bit3; + INCOHERENTCK_12 :bit1; + TXMARG_12 :bit3; + DEEMPH_12 :bit1; + COEFFICIENTID_12:bit2; + COEFFICIENT_12 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_13 :bit3; + INCOHERENTCK_13 :bit1; + TXMARG_13 :bit3; + DEEMPH_13 :bit1; + COEFFICIENTID_13:bit2; + COEFFICIENT_13 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_14 :bit3; + INCOHERENTCK_14 :bit1; + TXMARG_14 :bit3; + DEEMPH_14 :bit1; + COEFFICIENTID_14:bit2; + COEFFICIENT_14 :bit6; + RESERVED0 :bit16; + end; + + TPB0_TX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_15 :bit3; + INCOHERENTCK_15 :bit1; + TXMARG_15 :bit3; + DEEMPH_15 :bit1; + COEFFICIENTID_15:bit2; + COEFFICIENT_15 :bit6; + RESERVED0 :bit16; + end; + + TPB1_RX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_10 :bit3; + ELECIDLEDETEN_10:bit1; + RESERVED0 :bit2; + REQUESTTRK_10 :bit1; + ENABLEFOM_10 :bit1; + REQUESTFOM_10 :bit1; + RESPONSEMODE_10 :bit1; + RXEYEFOM_10 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_11 :bit3; + ELECIDLEDETEN_11:bit1; + RESERVED0 :bit2; + REQUESTTRK_11 :bit1; + ENABLEFOM_11 :bit1; + REQUESTFOM_11 :bit1; + RESPONSEMODE_11 :bit1; + RXEYEFOM_11 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_12 :bit3; + ELECIDLEDETEN_12:bit1; + RESERVED0 :bit2; + REQUESTTRK_12 :bit1; + ENABLEFOM_12 :bit1; + REQUESTFOM_12 :bit1; + RESPONSEMODE_12 :bit1; + RXEYEFOM_12 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_13 :bit3; + ELECIDLEDETEN_13:bit1; + RESERVED0 :bit2; + REQUESTTRK_13 :bit1; + ENABLEFOM_13 :bit1; + REQUESTFOM_13 :bit1; + RESPONSEMODE_13 :bit1; + RXEYEFOM_13 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_14 :bit3; + ELECIDLEDETEN_14:bit1; + RESERVED0 :bit2; + REQUESTTRK_14 :bit1; + ENABLEFOM_14 :bit1; + REQUESTFOM_14 :bit1; + RESPONSEMODE_14 :bit1; + RXEYEFOM_14 :bit8; + RESERVED1 :bit14; + end; + + TPB1_RX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record + RXPWR_15 :bit3; + ELECIDLEDETEN_15:bit1; + RESERVED0 :bit2; + REQUESTTRK_15 :bit1; + ENABLEFOM_15 :bit1; + REQUESTFOM_15 :bit1; + RESPONSEMODE_15 :bit1; + RXEYEFOM_15 :bit8; + RESERVED1 :bit14; + end; + + TPB1_TX_LANE10_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_10 :bit3; + INCOHERENTCK_10 :bit1; + TXMARG_10 :bit3; + DEEMPH_10 :bit1; + COEFFICIENTID_10:bit2; + COEFFICIENT_10 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE11_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_11 :bit3; + INCOHERENTCK_11 :bit1; + TXMARG_11 :bit3; + DEEMPH_11 :bit1; + COEFFICIENTID_11:bit2; + COEFFICIENT_11 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE12_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_12 :bit3; + INCOHERENTCK_12 :bit1; + TXMARG_12 :bit3; + DEEMPH_12 :bit1; + COEFFICIENTID_12:bit2; + COEFFICIENT_12 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE13_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_13 :bit3; + INCOHERENTCK_13 :bit1; + TXMARG_13 :bit3; + DEEMPH_13 :bit1; + COEFFICIENTID_13:bit2; + COEFFICIENT_13 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE14_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_14 :bit3; + INCOHERENTCK_14 :bit1; + TXMARG_14 :bit3; + DEEMPH_14 :bit1; + COEFFICIENTID_14:bit2; + COEFFICIENT_14 :bit6; + RESERVED0 :bit16; + end; + + TPB1_TX_LANE15_SCI_STAT_OVRD_REG0=bitpacked record + TXPWR_15 :bit3; + INCOHERENTCK_15 :bit1; + TXMARG_15 :bit3; + DEEMPH_15 :bit1; + COEFFICIENTID_15:bit2; + COEFFICIENT_15 :bit6; + RESERVED0 :bit16; + end; + + TPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7=bitpacked record + SUBSTATE_PWR_ALLOC:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_CPC_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_CPF_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_CPG_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_GDS_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_SPI_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_SQG_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_TCA_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_TCC_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_TCP_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TRLC_SPM_VGT_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED0 :bit24; + end; + + TSQ_THREAD_TRACE_WORD_PERF_1_OF_2=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + SH_ID :bit1; + CU_ID :bit4; + CNTR_BANK :bit2; + CNTR0 :bit13; + CNTR1_LO :bit7; + end; + + TSQ_THREAD_TRACE_WORD_PERF_2_OF_2=bitpacked record + CNTR1_HI:bit6; + CNTR2 :bit13; + CNTR3 :bit13; + end; + + TTARGET_AND_CURRENT_PROFILE_INDEX=bitpacked record + TARGET_STATE :bit4; + CURRENT_STATE :bit4; + CURR_MCLK_INDEX:bit4; + TARG_MCLK_INDEX:bit4; + CURR_SCLK_INDEX:bit5; + TARG_SCLK_INDEX:bit5; + CURR_LCLK_INDEX:bit3; + TARG_LCLK_INDEX:bit3; + end; + + TUNP_GRPH_SURFACE_ADDRESS_INUSE_C=bitpacked record + RESERVED0 :bit8; + GRPH_SURFACE_ADDRESS_INUSE_C:bit24; + end; + + TUNP_GRPH_SURFACE_ADDRESS_INUSE_L=bitpacked record + RESERVED0 :bit8; + GRPH_SURFACE_ADDRESS_INUSE_L:bit24; + end; + + TUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW=bit32; + + TUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=bitpacked record + WAIT_FAULT_EN :bit1; + WAIT_FAULT_COUNT:bit20; + RESERVED0 :bit3; + RESEND_TIMER :bit3; + RESERVED1 :bit5; + end; + TVGT_STRMOUT_BUFFER_FILLED_SIZE_0=bit32; TVGT_STRMOUT_BUFFER_FILLED_SIZE_1=bit32; @@ -13590,6 +64155,209 @@ type TVGT_STRMOUT_BUFFER_FILLED_SIZE_3=bit32; + TVM_CONTEXT0_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT1_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT2_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT3_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT4_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT5_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT6_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT7_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT8_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT9_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH=bitpacked record + XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TCC_RCU_DC_AUDIO_PORT_CONNECTIVITY=bitpacked record + PORT_CONNECTIVITY :bit3; + RESERVED0 :bit1; + PORT_CONNECTIVITY_OVERRIDE_ENABLE:bit1; + RESERVED1 :bit27; + end; + + TCRTC_EXT_TIMING_SYNC_WINDOW_START=bitpacked record + CRTC_EXT_TIMING_SYNC_WINDOW_START_X:bit14; + RESERVED0 :bit2; + CRTC_EXT_TIMING_SYNC_WINDOW_START_Y:bit14; + RESERVED1 :bit2; + end; + + TCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE=bitpacked record + CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE:bit1; + RESERVED0 :bit31; + end; + + TCRTC_MVP_INBAND_CNTL_INSERT_TIMER=bitpacked record + CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER:bit8; + RESERVED0 :bit24; + end; + + TCRTC_VERTICAL_INTERRUPT0_POSITION=bitpacked record + CRTC_VERTICAL_INTERRUPT0_LINE_START:bit14; + RESERVED0 :bit2; + CRTC_VERTICAL_INTERRUPT0_LINE_END :bit14; + RESERVED1 :bit2; + end; + + TCRTC_VERTICAL_INTERRUPT1_POSITION=bitpacked record + CRTC_VERTICAL_INTERRUPT1_LINE_START:bit14; + RESERVED0 :bit18; + end; + + TCRTC_VERTICAL_INTERRUPT2_POSITION=bitpacked record + CRTC_VERTICAL_INTERRUPT2_LINE_START:bit14; + RESERVED0 :bit18; + end; + + TDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL=bitpacked record + ABM1_HG_READY_INT_XIRQ_IRQ_SEL :bit1; + ABM1_LS_READY_INT_XIRQ_IRQ_SEL :bit1; + ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL :bit1; + MCP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN1_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN2_INT_XIRQ_IRQ_SEL :bit1; + EXTERNAL_SW_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN3_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN4_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN5_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL :bit1; + DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL:bit1; + VBLANK1_INT_XIRQ_IRQ_SEL :bit1; + VBLANK2_INT_XIRQ_IRQ_SEL :bit1; + VBLANK3_INT_XIRQ_IRQ_SEL :bit1; + VBLANK4_INT_XIRQ_IRQ_SEL :bit1; + VBLANK5_INT_XIRQ_IRQ_SEL :bit1; + VBLANK6_INT_XIRQ_IRQ_SEL :bit1; + STATIC_SCREEN6_INT_XIRQ_IRQ_SEL :bit1; + RESERVED0 :bit1; + end; + + TDPG_PIPE_NB_PSTATE_CHANGE_CONTROL=bitpacked record + NB_PSTATE_CHANGE_ENABLE :bit1; + RESERVED0 :bit3; + NB_PSTATE_CHANGE_URGENT_DURING_REQUEST :bit1; + RESERVED1 :bit3; + NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST:bit1; + NB_PSTATE_CHANGE_FORCE_ON :bit1; + NB_PSTATE_ALLOW_FOR_URGENT :bit1; + RESERVED2 :bit5; + NB_PSTATE_CHANGE_WATERMARK :bit16; + end; + + TDPG_PIPE_STUTTER_CONTROL_NONLPTCH=bitpacked record + STUTTER_ENABLE_NONLPTCH :bit1; + RESERVED0 :bit3; + STUTTER_IGNORE_CURSOR_NONLPTCH :bit1; + STUTTER_IGNORE_ICON_NONLPTCH :bit1; + STUTTER_IGNORE_VGA_NONLPTCH :bit1; + STUTTER_IGNORE_FBC_NONLPTCH :bit1; + STUTTER_WM_HIGH_FORCE_ON_NONLPTCH :bit1; + STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH :bit1; + STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH:bit1; + STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH :bit1; + RESERVED1 :bit20; + end; + + TGMCON_STCTRL_REGISTER_SAVE_RANGE0=bitpacked record + STCTRL_REGISTER_SAVE_BASE0 :bit16; + STCTRL_REGISTER_SAVE_LIMIT0:bit16; + end; + + TGMCON_STCTRL_REGISTER_SAVE_RANGE1=bitpacked record + STCTRL_REGISTER_SAVE_BASE1 :bit16; + STCTRL_REGISTER_SAVE_LIMIT1:bit16; + end; + + TGMCON_STCTRL_REGISTER_SAVE_RANGE2=bitpacked record + STCTRL_REGISTER_SAVE_BASE2 :bit16; + STCTRL_REGISTER_SAVE_LIMIT2:bit16; + end; + + TGRPH_PRIMARY_SURFACE_ADDRESS_HIGH=bitpacked record + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TIH_CLIENT_MAY_SEND_INCOMPLETE_INT=bitpacked record + CG :bit1; + DC :bit1; + RESERVED0:bit1; + SAMMSP :bit1; + RLC :bit1; + ROM :bit1; + SRBM :bit1; + VMC :bit1; + UVD :bit1; + BIF :bit1; + SDMA0 :bit1; + SDMA1 :bit1; + ISP :bit1; + VCE0 :bit1; + VCE1 :bit1; + ATC :bit1; + XDMA :bit1; + ACP :bit1; + SH :bit1; + SH1 :bit1; + SH2 :bit1; + SH3 :bit1; + RESERVED1:bit10; + end; + TPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0=bitpacked record S0_X:bit4; S0_Y:bit4; @@ -13771,13 +64539,2929 @@ type RESERVED0:bit16; end; + TPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED :bit24; + end; + + TRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED :bit24; + end; + + TRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED :bit24; + end; + + TRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY=bitpacked record + PERFMON_SAMPLE_DELAY:bit8; + RESERVED :bit24; + end; + + TUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH=bit32; + + TVM_CONTEXT0_PAGE_TABLE_START_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT0_PROTECTION_FAULT_ADDR=bitpacked record + LOGICAL_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT10_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT11_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT12_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT13_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT14_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT15_PAGE_TABLE_BASE_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT1_PAGE_TABLE_START_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT1_PROTECTION_FAULT_ADDR=bitpacked record + LOGICAL_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR=bit32; + + TXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH=bitpacked record + XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE=bitpacked record + AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN :bit1; + RESERVED0 :bit3; + AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE:bit16; + RESERVED1 :bit12; + end; + + TAZALIA_F0_AUDIO_ENABLED_INT_STATUS=bitpacked record + AUDIO_ENABLED_FLAG:bit1; + RESERVED0 :bit3; + AUDIO_ENABLED_MASK:bit1; + RESERVED1 :bit3; + AUDIO_ENABLED_TYPE:bit1; + RESERVED2 :bit23; + end; + + TDC_GPU_TIMER_START_POSITION_P_FLIP=bitpacked record + DC_GPU_TIMER_START_POSITION_D1_P_FLIP:bit3; + RESERVED0 :bit1; + DC_GPU_TIMER_START_POSITION_D2_P_FLIP:bit3; + RESERVED1 :bit1; + DC_GPU_TIMER_START_POSITION_D3_P_FLIP:bit3; + RESERVED2 :bit1; + DC_GPU_TIMER_START_POSITION_D4_P_FLIP:bit3; + RESERVED3 :bit1; + DC_GPU_TIMER_START_POSITION_D5_P_FLIP:bit3; + RESERVED4 :bit1; + DC_GPU_TIMER_START_POSITION_D6_P_FLIP:bit3; + RESERVED5 :bit9; + end; + + TDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1=bitpacked record + DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN :bit1; + DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN :bit1; + DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN :bit1; + DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN :bit1; + DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN :bit1; + DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN :bit1; + DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN :bit1; + DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN :bit1; + DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN :bit1; + DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN:bit1; + DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN :bit1; + DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_AUX_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_I2C_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_CPU_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN :bit1; + DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + end; + + TGRPH_COMPRESS_SURFACE_ADDRESS_HIGH=bitpacked record + GRPH_COMPRESS_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL=bitpacked record + GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN :bit1; + GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE :bit1; + RESERVED0 :bit2; + GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT:bit13; + RESERVED1 :bit15; + end; + + TGRPH_XDMA_RECOVERY_SURFACE_ADDRESS=bitpacked record + RESERVED0 :bit8; + GRPH_XDMA_RECOVERY_SURFACE_ADDRESS:bit24; + end; + + TIMMEDIATE_COMMAND_OUTPUT_INTERFACE=bitpacked record + IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD:bit28; + IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS :bit4; + end; + + TIMMEDIATE_RESPONSE_INPUT_INTERFACE=bit32; + + TMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=bitpacked record + PHYSICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE=bitpacked record + FIFO_SIZE:bit16; + RESERVED0:bit16; + end; + + TOVL_SECONDARY_SURFACE_ADDRESS_HIGH=bitpacked record + OVL_SECONDARY_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0=bitpacked record + ACCEPT_ENTRY_0 :bit1; + ACCEPT_ENTRY_1 :bit1; + ACCEPT_ENTRY_2 :bit1; + ACCEPT_ENTRY_3 :bit1; + ACCEPT_ENTRY_4 :bit1; + ACCEPT_ENTRY_5 :bit1; + ACCEPT_ENTRY_6 :bit1; + ACCEPT_ENTRY_7 :bit1; + ACCEPT_ENTRY_8 :bit1; + ACCEPT_ENTRY_9 :bit1; + ACCEPT_ENTRY_10:bit1; + ACCEPT_ENTRY_11:bit1; + ACCEPT_ENTRY_12:bit1; + ACCEPT_ENTRY_13:bit1; + ACCEPT_ENTRY_14:bit1; + ACCEPT_ENTRY_15:bit1; + ACCEPT_ENTRY_16:bit1; + ACCEPT_ENTRY_17:bit1; + ACCEPT_ENTRY_18:bit1; + ACCEPT_ENTRY_19:bit1; + ACCEPT_ENTRY_20:bit1; + ACCEPT_ENTRY_21:bit1; + ACCEPT_ENTRY_22:bit1; + ACCEPT_ENTRY_23:bit1; + ACCEPT_ENTRY_24:bit1; + ACCEPT_ENTRY_25:bit1; + ACCEPT_ENTRY_26:bit1; + ACCEPT_ENTRY_27:bit1; + ACCEPT_ENTRY_28:bit1; + ACCEPT_ENTRY_29:bit1; + ACCEPT_ENTRY_30:bit1; + ACCEPT_ENTRY_31:bit1; + end; + + TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1=bitpacked record + ACCEPT_ENTRY_32:bit1; + ACCEPT_ENTRY_33:bit1; + ACCEPT_ENTRY_34:bit1; + ACCEPT_ENTRY_35:bit1; + ACCEPT_ENTRY_36:bit1; + ACCEPT_ENTRY_37:bit1; + ACCEPT_ENTRY_38:bit1; + ACCEPT_ENTRY_39:bit1; + ACCEPT_ENTRY_40:bit1; + ACCEPT_ENTRY_41:bit1; + ACCEPT_ENTRY_42:bit1; + ACCEPT_ENTRY_43:bit1; + ACCEPT_ENTRY_44:bit1; + ACCEPT_ENTRY_45:bit1; + ACCEPT_ENTRY_46:bit1; + ACCEPT_ENTRY_47:bit1; + ACCEPT_ENTRY_48:bit1; + ACCEPT_ENTRY_49:bit1; + ACCEPT_ENTRY_50:bit1; + ACCEPT_ENTRY_51:bit1; + ACCEPT_ENTRY_52:bit1; + ACCEPT_ENTRY_53:bit1; + ACCEPT_ENTRY_54:bit1; + ACCEPT_ENTRY_55:bit1; + ACCEPT_ENTRY_56:bit1; + ACCEPT_ENTRY_57:bit1; + ACCEPT_ENTRY_58:bit1; + ACCEPT_ENTRY_59:bit1; + ACCEPT_ENTRY_60:bit1; + ACCEPT_ENTRY_61:bit1; + ACCEPT_ENTRY_62:bit1; + ACCEPT_ENTRY_63:bit1; + end; + + TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2=bitpacked record + ACCEPT_ENTRY_64:bit1; + ACCEPT_ENTRY_65:bit1; + ACCEPT_ENTRY_66:bit1; + ACCEPT_ENTRY_67:bit1; + ACCEPT_ENTRY_68:bit1; + ACCEPT_ENTRY_69:bit1; + ACCEPT_ENTRY_70:bit1; + ACCEPT_ENTRY_71:bit1; + ACCEPT_ENTRY_72:bit1; + ACCEPT_ENTRY_73:bit1; + ACCEPT_ENTRY_74:bit1; + ACCEPT_ENTRY_75:bit1; + ACCEPT_ENTRY_76:bit1; + ACCEPT_ENTRY_77:bit1; + ACCEPT_ENTRY_78:bit1; + ACCEPT_ENTRY_79:bit1; + ACCEPT_ENTRY_80:bit1; + ACCEPT_ENTRY_81:bit1; + ACCEPT_ENTRY_82:bit1; + ACCEPT_ENTRY_83:bit1; + ACCEPT_ENTRY_84:bit1; + ACCEPT_ENTRY_85:bit1; + ACCEPT_ENTRY_86:bit1; + ACCEPT_ENTRY_87:bit1; + ACCEPT_ENTRY_88:bit1; + ACCEPT_ENTRY_89:bit1; + ACCEPT_ENTRY_90:bit1; + ACCEPT_ENTRY_91:bit1; + ACCEPT_ENTRY_92:bit1; + ACCEPT_ENTRY_93:bit1; + ACCEPT_ENTRY_94:bit1; + ACCEPT_ENTRY_95:bit1; + end; + + TPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3=bitpacked record + ACCEPT_ENTRY_96 :bit1; + ACCEPT_ENTRY_97 :bit1; + ACCEPT_ENTRY_98 :bit1; + ACCEPT_ENTRY_99 :bit1; + ACCEPT_ENTRY_100:bit1; + ACCEPT_ENTRY_101:bit1; + ACCEPT_ENTRY_102:bit1; + ACCEPT_ENTRY_103:bit1; + ACCEPT_ENTRY_104:bit1; + ACCEPT_ENTRY_105:bit1; + ACCEPT_ENTRY_106:bit1; + ACCEPT_ENTRY_107:bit1; + ACCEPT_ENTRY_108:bit1; + ACCEPT_ENTRY_109:bit1; + RESERVED0 :bit18; + end; + + TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0=bitpacked record + ACCEPT_ENTRY_0 :bit1; + ACCEPT_ENTRY_1 :bit1; + ACCEPT_ENTRY_2 :bit1; + ACCEPT_ENTRY_3 :bit1; + ACCEPT_ENTRY_4 :bit1; + ACCEPT_ENTRY_5 :bit1; + ACCEPT_ENTRY_6 :bit1; + ACCEPT_ENTRY_7 :bit1; + ACCEPT_ENTRY_8 :bit1; + ACCEPT_ENTRY_9 :bit1; + ACCEPT_ENTRY_10:bit1; + ACCEPT_ENTRY_11:bit1; + ACCEPT_ENTRY_12:bit1; + ACCEPT_ENTRY_13:bit1; + ACCEPT_ENTRY_14:bit1; + ACCEPT_ENTRY_15:bit1; + ACCEPT_ENTRY_16:bit1; + ACCEPT_ENTRY_17:bit1; + ACCEPT_ENTRY_18:bit1; + ACCEPT_ENTRY_19:bit1; + ACCEPT_ENTRY_20:bit1; + ACCEPT_ENTRY_21:bit1; + ACCEPT_ENTRY_22:bit1; + ACCEPT_ENTRY_23:bit1; + ACCEPT_ENTRY_24:bit1; + ACCEPT_ENTRY_25:bit1; + ACCEPT_ENTRY_26:bit1; + ACCEPT_ENTRY_27:bit1; + ACCEPT_ENTRY_28:bit1; + ACCEPT_ENTRY_29:bit1; + ACCEPT_ENTRY_30:bit1; + ACCEPT_ENTRY_31:bit1; + end; + + TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1=bitpacked record + ACCEPT_ENTRY_32:bit1; + ACCEPT_ENTRY_33:bit1; + ACCEPT_ENTRY_34:bit1; + ACCEPT_ENTRY_35:bit1; + ACCEPT_ENTRY_36:bit1; + ACCEPT_ENTRY_37:bit1; + ACCEPT_ENTRY_38:bit1; + ACCEPT_ENTRY_39:bit1; + ACCEPT_ENTRY_40:bit1; + ACCEPT_ENTRY_41:bit1; + ACCEPT_ENTRY_42:bit1; + ACCEPT_ENTRY_43:bit1; + ACCEPT_ENTRY_44:bit1; + ACCEPT_ENTRY_45:bit1; + ACCEPT_ENTRY_46:bit1; + ACCEPT_ENTRY_47:bit1; + ACCEPT_ENTRY_48:bit1; + ACCEPT_ENTRY_49:bit1; + ACCEPT_ENTRY_50:bit1; + ACCEPT_ENTRY_51:bit1; + ACCEPT_ENTRY_52:bit1; + ACCEPT_ENTRY_53:bit1; + ACCEPT_ENTRY_54:bit1; + ACCEPT_ENTRY_55:bit1; + ACCEPT_ENTRY_56:bit1; + ACCEPT_ENTRY_57:bit1; + ACCEPT_ENTRY_58:bit1; + ACCEPT_ENTRY_59:bit1; + ACCEPT_ENTRY_60:bit1; + ACCEPT_ENTRY_61:bit1; + ACCEPT_ENTRY_62:bit1; + ACCEPT_ENTRY_63:bit1; + end; + + TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2=bitpacked record + ACCEPT_ENTRY_64:bit1; + ACCEPT_ENTRY_65:bit1; + ACCEPT_ENTRY_66:bit1; + ACCEPT_ENTRY_67:bit1; + ACCEPT_ENTRY_68:bit1; + ACCEPT_ENTRY_69:bit1; + ACCEPT_ENTRY_70:bit1; + ACCEPT_ENTRY_71:bit1; + ACCEPT_ENTRY_72:bit1; + ACCEPT_ENTRY_73:bit1; + ACCEPT_ENTRY_74:bit1; + ACCEPT_ENTRY_75:bit1; + ACCEPT_ENTRY_76:bit1; + ACCEPT_ENTRY_77:bit1; + ACCEPT_ENTRY_78:bit1; + ACCEPT_ENTRY_79:bit1; + ACCEPT_ENTRY_80:bit1; + ACCEPT_ENTRY_81:bit1; + ACCEPT_ENTRY_82:bit1; + ACCEPT_ENTRY_83:bit1; + ACCEPT_ENTRY_84:bit1; + ACCEPT_ENTRY_85:bit1; + ACCEPT_ENTRY_86:bit1; + ACCEPT_ENTRY_87:bit1; + ACCEPT_ENTRY_88:bit1; + ACCEPT_ENTRY_89:bit1; + ACCEPT_ENTRY_90:bit1; + ACCEPT_ENTRY_91:bit1; + ACCEPT_ENTRY_92:bit1; + ACCEPT_ENTRY_93:bit1; + ACCEPT_ENTRY_94:bit1; + ACCEPT_ENTRY_95:bit1; + end; + + TPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3=bitpacked record + ACCEPT_ENTRY_96 :bit1; + ACCEPT_ENTRY_97 :bit1; + ACCEPT_ENTRY_98 :bit1; + ACCEPT_ENTRY_99 :bit1; + ACCEPT_ENTRY_100:bit1; + ACCEPT_ENTRY_101:bit1; + ACCEPT_ENTRY_102:bit1; + ACCEPT_ENTRY_103:bit1; + ACCEPT_ENTRY_104:bit1; + ACCEPT_ENTRY_105:bit1; + ACCEPT_ENTRY_106:bit1; + ACCEPT_ENTRY_107:bit1; + ACCEPT_ENTRY_108:bit1; + ACCEPT_ENTRY_109:bit1; + RESERVED0 :bit18; + end; + + TSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + PIPE_ID :bit2; + ME_ID :bit2; + REG_ADDR :bit7; + DATA_LO :bit16; + end; + + TSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2=bitpacked record + DATA_HI :bit16; + RESERVED0:bit16; + end; + + TTARGET_AND_CURRENT_PROFILE_INDEX_1=bitpacked record + CURR_VDDCI_INDEX:bit4; + TARG_VDDCI_INDEX:bit4; + CURR_MVDD_INDEX :bit4; + TARG_MVDD_INDEX :bit4; + CURR_VDDC_INDEX :bit4; + TARG_VDDC_INDEX :bit4; + CURR_PCIE_INDEX :bit4; + TARG_PCIE_INDEX :bit4; + end; + + TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C=bitpacked record + GRPH_PRIMARY_DFQ_ENABLE_C :bit1; + RESERVED0 :bit7; + GRPH_PRIMARY_SURFACE_ADDRESS_C:bit24; + end; + + TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L=bitpacked record + GRPH_PRIMARY_DFQ_ENABLE_L :bit1; + RESERVED0 :bit7; + GRPH_PRIMARY_SURFACE_ADDRESS_L:bit24; + end; + + TXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH=bitpacked record + XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F0_AUDIO_DISABLED_INT_STATUS=bitpacked record + AUDIO_DISABLED_FLAG:bit1; + RESERVED0 :bit3; + AUDIO_DISABLED_MASK:bit1; + RESERVED1 :bit3; + AUDIO_DISABLED_TYPE:bit1; + RESERVED2 :bit23; + end; + + TAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG=bit32; + + TAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA=bit32; + + TAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL=bitpacked record + RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW:bit6; + RESERVED0 :bit26; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC=bitpacked record + VIDEO_LIPSYNC:bit8; + AUDIO_LIPSYNC:bit8; + RESERVED0 :bit16; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_PORTID0=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_PORTID1=bit32; + + TFMT_TEMPORAL_DITHER_PATTERN_CONTROL=bitpacked record + FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT :bit1; + RESERVED0 :bit3; + FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0:bit1; + RESERVED1 :bit27; + end; + + TGRPH_SECONDARY_SURFACE_ADDRESS_HIGH=bitpacked record + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + WAVE_ID :bit4; + SIMD_ID :bit2; + RESERVED0 :bit5; + PC_LO :bit16; + end; + + TSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2=bitpacked record + PC_HI :bit24; + RESERVED0:bit8; + end; + + TVM_CONTEXT0_PROTECTION_FAULT_STATUS=bitpacked record + PROTECTIONS :bit8; + RESERVED0 :bit4; + MEMORY_CLIENT_ID:bit9; + RESERVED1 :bit3; + MEMORY_CLIENT_RW:bit1; + VMID :bit4; + ATOMIC :bit1; + RESERVED2 :bit2; + end; + + TVM_CONTEXT1_PROTECTION_FAULT_STATUS=bitpacked record + PROTECTIONS :bit8; + RESERVED0 :bit4; + MEMORY_CLIENT_ID:bit9; + RESERVED1 :bit3; + MEMORY_CLIENT_RW:bit1; + VMID :bit4; + ATOMIC :bit1; + RESERVED2 :bit2; + end; + + TATC_VMID_PASID_MAPPING_UPDATE_STATUS=bitpacked record + VMID0_REMAPPING_FINISHED :bit1; + VMID1_REMAPPING_FINISHED :bit1; + VMID2_REMAPPING_FINISHED :bit1; + VMID3_REMAPPING_FINISHED :bit1; + VMID4_REMAPPING_FINISHED :bit1; + VMID5_REMAPPING_FINISHED :bit1; + VMID6_REMAPPING_FINISHED :bit1; + VMID7_REMAPPING_FINISHED :bit1; + VMID8_REMAPPING_FINISHED :bit1; + VMID9_REMAPPING_FINISHED :bit1; + VMID10_REMAPPING_FINISHED:bit1; + VMID11_REMAPPING_FINISHED:bit1; + VMID12_REMAPPING_FINISHED:bit1; + VMID13_REMAPPING_FINISHED:bit1; + VMID14_REMAPPING_FINISHED:bit1; + VMID15_REMAPPING_FINISHED:bit1; + RESERVED0 :bit16; + end; + + TAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX=bitpacked record + AZALIA_INPUT_ENDPOINT_REG_INDEX:bit14; + RESERVED0 :bit18; + end; + + TAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO=bit32; + + TAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO=bit32; + + TAZALIA_OUTPUT_STREAM_ARBITER_CONTROL=bitpacked record + LATENCY_HIDING_LEVEL :bit8; + SYS_MEM_ACTIVE_ENABLE :bit1; + RESERVED0 :bit7; + INPUT_LATENCY_HIDING_LEVEL:bit8; + RESERVED1 :bit8; + end; + + TBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS=bitpacked record + REG_RWREG_RFEWDBIF_clkGate_timer :bit8; + REG_RWREG_RFEWDBIF_clkSetup_timer:bit4; + RESERVED0 :bit4; + REG_RWREG_RFEWDBIF_timeout_timer :bit8; + RWREG_RFEWDBIF_RFE_mstTimeout :bit1; + RESERVED1 :bit7; + end; + + TDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES=bitpacked record + ABM1_LS_MIN_PIXEL_VALUE_THRES:bit10; + RESERVED0 :bit6; + ABM1_LS_MAX_PIXEL_VALUE_THRES:bit10; + RESERVED1 :bit5; + ABM1_HGLS_REG_LOCK :bit1; + end; + + TDC_GPU_TIMER_START_POSITION_V_UPDATE=bitpacked record + DC_GPU_TIMER_START_POSITION_D1_V_UPDATE:bit3; + RESERVED0 :bit1; + DC_GPU_TIMER_START_POSITION_D2_V_UPDATE:bit3; + RESERVED1 :bit1; + DC_GPU_TIMER_START_POSITION_D3_V_UPDATE:bit3; + RESERVED2 :bit1; + DC_GPU_TIMER_START_POSITION_D4_V_UPDATE:bit3; + RESERVED3 :bit1; + DC_GPU_TIMER_START_POSITION_D5_V_UPDATE:bit3; + RESERVED4 :bit1; + DC_GPU_TIMER_START_POSITION_D6_V_UPDATE:bit3; + RESERVED5 :bit9; + end; + + TGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0=bitpacked record + STCTRL_REGISTER_SAVE_EXCL0:bit16; + STCTRL_REGISTER_SAVE_EXCL1:bit16; + end; + + TGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1=bitpacked record + STCTRL_REGISTER_SAVE_EXCL2:bit16; + STCTRL_REGISTER_SAVE_EXCL3:bit16; + end; + + TGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS=bitpacked record + GRPH_XDMA_CACHE_UNDERFLOW_CNT :bit20; + RESERVED0 :bit4; + GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS:bit1; + GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK:bit1; + GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK :bit1; + RESERVED1 :bit1; + GRPH_XDMA_CACHE_UNDERFLOW_INT :bit1; + GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK :bit1; + GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK :bit1; + RESERVED2 :bit1; + end; + + TMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C=bitpacked record + GRPH_SECONDARY_DFQ_ENABLE_C :bit1; + RESERVED0 :bit7; + GRPH_SECONDARY_SURFACE_ADDRESS_C:bit24; + end; + + TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L=bitpacked record + GRPH_SECONDARY_DFQ_ENABLE_L :bit1; + RESERVED0 :bit7; + GRPH_SECONDARY_SURFACE_ADDRESS_L:bit24; + end; + + TAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL=bitpacked record + HBR_CHANNEL_COUNT :bit3; + RESERVED0 :bit1; + COMPRESSED_CHANNEL_COUNT:bit3; + RESERVED1 :bit25; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR=bitpacked record + HBR_CAPABLE:bit1; + RESERVED0 :bit3; + HBR_ENABLE :bit1; + RESERVED1 :bit27; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1=bitpacked record + DCI_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN :bit1; + DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN :bit1; + DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2=bitpacked record + DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3=bitpacked record + DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4=bitpacked record + WB_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + WB_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + RESERVED0 :bit8; + WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN :bit1; + DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + RESERVED1 :bit6; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5=bitpacked record + DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN :bit1; + DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN:bit1; + RESERVED0 :bit23; + end; + + TMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR=bitpacked record + PHYSICAL_ADDRESS:bit28; + RESERVED0 :bit4; + end; + + TSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2=bitpacked record + TOKEN_TYPE:bit4; + RESERVED0 :bit12; + TIME_LO :bit16; + end; + + TSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2=bit32; + + TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C=bitpacked record + GRPH_SURFACE_ADDRESS_HIGH_INUSE_C:bit8; + RESERVED0 :bit24; + end; + + TUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L=bitpacked record + GRPH_SURFACE_ADDRESS_HIGH_INUSE_L:bit8; + RESERVED0 :bit24; + end; + + TUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=bitpacked record + WAIT_INCOMPLETE_EN :bit1; + WAIT_INCOMPLETE_COUNT:bit20; + RESERVED0 :bit3; + RESEND_TIMER :bit3; + RESERVED1 :bit5; + end; + TVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE=bitpacked record VERTEX_STRIDE:bit9; RESERVED0 :bit23; end; + TVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT=bit32; + + TVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT=bit32; + + TAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET=bitpacked record + CODEC_RESET:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0=bitpacked record + MANUFACTURER_ID:bit16; + PRODUCT_ID :bit16; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1=bitpacked record + SINK_DESCRIPTION_LEN:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4=bitpacked record + DESCRIPTION0:bit8; + DESCRIPTION1:bit8; + DESCRIPTION2:bit8; + DESCRIPTION3:bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5=bitpacked record + DESCRIPTION4:bit8; + DESCRIPTION5:bit8; + DESCRIPTION6:bit8; + DESCRIPTION7:bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6=bitpacked record + DESCRIPTION8 :bit8; + DESCRIPTION9 :bit8; + DESCRIPTION10:bit8; + DESCRIPTION11:bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7=bitpacked record + DESCRIPTION12:bit8; + DESCRIPTION13:bit8; + DESCRIPTION14:bit8; + DESCRIPTION15:bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8=bitpacked record + DESCRIPTION16:bit8; + DESCRIPTION17:bit8; + RESERVED0 :bit16; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET=bitpacked record + CODEC_RESET:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID=bitpacked record + PRODUCT_ID:bit16; + RESERVED0 :bit16; + end; + + TCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL=bitpacked record + CRTC_EXT_TIMING_SYNC_INT_ENABLE:bit1; + RESERVED0 :bit3; + CRTC_EXT_TIMING_SYNC_STATUS :bit1; + RESERVED1 :bit3; + CRTC_EXT_TIMING_SYNC_INT_STATUS:bit1; + RESERVED2 :bit7; + CRTC_EXT_TIMING_SYNC_CLEAR :bit1; + RESERVED3 :bit3; + CRTC_EXT_TIMING_SYNC_INT_TYPE :bit1; + RESERVED4 :bit11; + end; + + TMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR=bitpacked record + LOGICAL_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=bitpacked record + PHYSICAL_PAGE_OFFSET:bit28; + RESERVED0 :bit4; + end; + + TXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH=bitpacked record + XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE=bitpacked record + CODING_TYPE:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE=bitpacked record + CODING_TYPE:bit8; + RESERVED0 :bit24; + end; + + TCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY=bitpacked record + INPUT_PORT_CONNECTIVITY :bit3; + RESERVED0 :bit1; + INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE:bit1; + RESERVED1 :bit27; + end; + + TDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1=bitpacked record + DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL :bit1; + DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL :bit1; + DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL :bit1; + DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL :bit1; + DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL:bit1; + DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL :bit1; + DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL :bit1; + DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL :bit1; + RESERVED0 :bit1; + RESERVED1 :bit1; + RESERVED2 :bit1; + end; + + TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1=bitpacked record + DCI_PERFMON_COUNTER0_INT_MASK :bit1; + DCI_PERFMON_COUNTER1_INT_MASK :bit1; + DCI_PERFMON_COUNTER2_INT_MASK :bit1; + DCI_PERFMON_COUNTER3_INT_MASK :bit1; + DCI_PERFMON_COUNTER4_INT_MASK :bit1; + DCI_PERFMON_COUNTER5_INT_MASK :bit1; + DCI_PERFMON_COUNTER6_INT_MASK :bit1; + DCI_PERFMON_COUNTER7_INT_MASK :bit1; + DCO_PERFMON_COUNTER0_INT_MASK :bit1; + DCO_PERFMON_COUNTER1_INT_MASK :bit1; + DCO_PERFMON_COUNTER2_INT_MASK :bit1; + DCO_PERFMON_COUNTER3_INT_MASK :bit1; + DCO_PERFMON_COUNTER4_INT_MASK :bit1; + DCO_PERFMON_COUNTER5_INT_MASK :bit1; + DCO_PERFMON_COUNTER6_INT_MASK :bit1; + DCO_PERFMON_COUNTER7_INT_MASK :bit1; + DCCG_PERFMON_COUNTER0_INT_MASK :bit1; + DCCG_PERFMON_COUNTER1_INT_MASK :bit1; + DCCG_PERFMON_COUNTER2_INT_MASK :bit1; + DCCG_PERFMON_COUNTER3_INT_MASK :bit1; + DCCG_PERFMON_COUNTER4_INT_MASK :bit1; + DCCG_PERFMON_COUNTER5_INT_MASK :bit1; + DCCG_PERFMON_COUNTER6_INT_MASK :bit1; + DCCG_PERFMON_COUNTER7_INT_MASK :bit1; + DCI_PERFMON_COUNTER_OFF_INT_MASK :bit1; + DCO_PERFMON_COUNTER_OFF_INT_MASK :bit1; + DCCG_PERFMON_COUNTER_OFF_INT_MASK:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2=bitpacked record + DCFE0_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE1_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE2_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE0_PERFMON_COUNTER_OFF_INT_MASK:bit1; + DCFE1_PERFMON_COUNTER_OFF_INT_MASK:bit1; + DCFE2_PERFMON_COUNTER_OFF_INT_MASK:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3=bitpacked record + DCFE3_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE4_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER0_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER1_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER2_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER3_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER4_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER5_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER6_INT_MASK :bit1; + DCFE5_PERFMON_COUNTER7_INT_MASK :bit1; + DCFE3_PERFMON_COUNTER_OFF_INT_MASK:bit1; + DCFE4_PERFMON_COUNTER_OFF_INT_MASK:bit1; + DCFE5_PERFMON_COUNTER_OFF_INT_MASK:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4=bitpacked record + WB_PERFMON_COUNTER0_INT_MASK :bit1; + WB_PERFMON_COUNTER1_INT_MASK :bit1; + WB_PERFMON_COUNTER2_INT_MASK :bit1; + WB_PERFMON_COUNTER3_INT_MASK :bit1; + WB_PERFMON_COUNTER4_INT_MASK :bit1; + WB_PERFMON_COUNTER5_INT_MASK :bit1; + WB_PERFMON_COUNTER6_INT_MASK :bit1; + WB_PERFMON_COUNTER7_INT_MASK :bit1; + DCRX_PERFMON_COUNTER0_INT_MASK :bit1; + DCRX_PERFMON_COUNTER1_INT_MASK :bit1; + DCRX_PERFMON_COUNTER2_INT_MASK :bit1; + DCRX_PERFMON_COUNTER3_INT_MASK :bit1; + DCRX_PERFMON_COUNTER4_INT_MASK :bit1; + DCRX_PERFMON_COUNTER5_INT_MASK :bit1; + DCRX_PERFMON_COUNTER6_INT_MASK :bit1; + DCRX_PERFMON_COUNTER7_INT_MASK :bit1; + RESERVED0 :bit8; + WB_PERFMON_COUNTER_OFF_INT_MASK :bit1; + DCRX_PERFMON_COUNTER_OFF_INT_MASK:bit1; + RESERVED1 :bit6; + end; + + TDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5=bitpacked record + DCFEV_PERFMON_COUNTER0_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER1_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER2_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER3_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER4_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER5_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER6_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER7_INT_MASK :bit1; + DCFEV_PERFMON_COUNTER_OFF_INT_MASK:bit1; + RESERVED0 :bit23; + end; + + TGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH=bitpacked record + GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH:bit8; + RESERVED0 :bit24; + end; + + TIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32; + + TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C=bitpacked record + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C:bit8; + RESERVED0 :bit24; + end; + + TUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L=bitpacked record + GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L:bit8; + RESERVED0 :bit24; + end; + + TUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=bitpacked record + SIGNAL_INCOMPLETE_EN :bit1; + SIGNAL_INCOMPLETE_COUNT:bit20; + RESERVED0 :bit3; + RESEND_TIMER :bit3; + RESERVED1 :bit5; + end; + + TAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL=bitpacked record + STRIPE_CONTROL :bit2; + RESERVED0 :bit18; + STRIPE_CAPABILITY:bit3; + RESERVED1 :bit9; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR=bitpacked record + HBR_CAPABLE:bit1; + RESERVED0 :bit3; + HBR_ENABLE :bit1; + RESERVED1 :bit27; + end; + + TAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL=bitpacked record + STRIPE_CONTROL :bit2; + RESERVED0 :bit18; + STRIPE_CAPABILITY:bit3; + RESERVED1 :bit9; + end; + + TBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD=bit32; + + TIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record + IMMEDIATE_COMMAND_WRITE:bit16; + RESERVED0 :bit16; + end; + + TMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS=bitpacked record + PROTECTIONS :bit8; + RESERVED0 :bit4; + MEMORY_CLIENT_ID:bit9; + RESERVED1 :bit3; + MEMORY_CLIENT_RW:bit1; + VMID :bit4; + ATOMIC :bit1; + RESERVED2 :bit2; + end; + + TPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV=bitpacked record + CAP_ID :bit16; + CAP_VER :bit4; + NEXT_PTR:bit12; + end; + + TAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS=bitpacked record + AUDIO_FORMAT_CHANGED_FLAG:bit1; + RESERVED0 :bit3; + AUDIO_FORMAT_CHANGED_MASK:bit1; + RESERVED1 :bit3; + AUDIO_FORMAT_CHANGED_TYPE:bit1; + RESERVED2 :bit23; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG=bit32; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0=bitpacked record + IEC_60958_CS_MODE :bit2; + IEC_60958_CS_SOURCE_NUMBER:bit4; + RESERVED0 :bit26; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1=bitpacked record + IEC_60958_CS_CLOCK_ACCURACY :bit2; + IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN:bit1; + IEC_60958_CS_WORD_LENGTH :bit4; + IEC_60958_CS_WORD_LENGTH_OVRRD_EN :bit1; + RESERVED0 :bit24; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2=bitpacked record + IEC_60958_CS_SAMPLING_FREQUENCY :bit6; + IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN:bit1; + RESERVED0 :bit25; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3=bitpacked record + IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY :bit4; + IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN:bit1; + RESERVED0 :bit27; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4=bitpacked record + IEC_60958_CS_SAMPLING_FREQUENCY_COEFF:bit4; + IEC_60958_CS_MPEG_SURROUND_INFO :bit1; + IEC_60958_CS_CGMS_A :bit2; + IEC_60958_CS_CGMS_A_VALID :bit1; + RESERVED0 :bit24; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_L:bit4; + IEC_60958_CS_CHANNEL_NUMBER_R:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_2:bit4; + IEC_60958_CS_CHANNEL_NUMBER_3:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_4:bit4; + IEC_60958_CS_CHANNEL_NUMBER_5:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_6:bit4; + IEC_60958_CS_CHANNEL_NUMBER_7:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO=bitpacked record + LFE_PLAYBACK_LEVEL:bit2; + RESERVED0 :bit1; + LEVEL_SHIFT :bit4; + DOWN_MIX_INHIBIT :bit1; + RESERVED1 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0=bitpacked record + IEC_60958_CS_MODE :bit2; + IEC_60958_CS_SOURCE_NUMBER:bit4; + RESERVED0 :bit26; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1=bitpacked record + IEC_60958_CS_CLOCK_ACCURACY :bit2; + IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN:bit1; + IEC_60958_CS_WORD_LENGTH :bit4; + IEC_60958_CS_WORD_LENGTH_OVRRD_EN :bit1; + RESERVED0 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2=bitpacked record + IEC_60958_CS_SAMPLING_FREQUENCY :bit6; + IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN:bit1; + RESERVED0 :bit25; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3=bitpacked record + IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY :bit4; + IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN:bit1; + RESERVED0 :bit27; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4=bitpacked record + IEC_60958_CS_SAMPLING_FREQUENCY_COEFF:bit4; + IEC_60958_CS_MPEG_SURROUND_INFO :bit1; + IEC_60958_CS_CGMS_A :bit2; + IEC_60958_CS_CGMS_A_VALID :bit1; + RESERVED0 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_L:bit4; + IEC_60958_CS_CHANNEL_NUMBER_R:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_2:bit4; + IEC_60958_CS_CHANNEL_NUMBER_3:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_4:bit4; + IEC_60958_CS_CHANNEL_NUMBER_5:bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8=bitpacked record + IEC_60958_CS_CHANNEL_NUMBER_6:bit4; + IEC_60958_CS_CHANNEL_NUMBER_7:bit4; + RESERVED0 :bit24; + end; + + TOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX=bitpacked record + LAST_VALID_INDEX:bit8; + RESERVED0 :bit24; + end; + + TSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2=bitpacked record + TOKEN_TYPE:bit4; + TIME_DELTA:bit1; + SH_ID :bit1; + CU_ID :bit4; + WAVE_ID :bit4; + SIMD_ID :bit2; + DATA_LO :bit16; + end; + + TSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2=bitpacked record + DATA_HI :bit16; + RESERVED0:bit16; + end; + + TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C=bitpacked record + GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C :bit1; + RESERVED0 :bit7; + GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C:bit24; + end; + + TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L=bitpacked record + GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L :bit1; + RESERVED0 :bit7; + GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L:bit24; + end; + + TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C=bitpacked record + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C:bit8; + RESERVED0 :bit24; + end; + + TUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L=bitpacked record + GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L:bit8; + RESERVED0 :bit24; + end; + + TVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=bitpacked record + PHYSICAL_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=bitpacked record + PHYSICAL_PAGE_ADDR:bit28; + RESERVED0 :bit4; + end; + + TVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED=bitpacked record + FORMAT_CHANGED :bit1; + FORMAT_CHANGED_ACK_UR_ENABLE:bit1; + RESERVED0 :bit6; + FORMAT_CHANGE_REASON :bit8; + FORMAT_CHANGE_RESPONSE :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL=bitpacked record + RESERVED0 :bit6; + OUT_ENABLE:bit1; + RESERVED1 :bit25; + end; + + TAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES=bitpacked record + IMPEDANCE_SENSE_CAPABLE :bit1; + TRIGGER_REQUIRED :bit1; + JACK_DETECTION_CAPABILITY:bit1; + HEADPHONE_DRIVE_CAPABLE :bit1; + OUTPUT_CAPABLE :bit1; + INPUT_CAPABLE :bit1; + BALANCED_I_O_PINS :bit1; + HDMI :bit1; + VREF_CONTROL :bit8; + EAPD_CAPABLE :bit1; + RESERVED0 :bit7; + DP :bit1; + RESERVED1 :bit7; + end; + + TAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED=bitpacked record + FORMAT_CHANGED :bit1; + FORMAT_CHANGED_ACK_UR_ENABLE:bit1; + RESERVED0 :bit6; + FORMAT_CHANGE_REASON :bit8; + FORMAT_CHANGE_RESPONSE :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL=bitpacked record + RESERVED0 :bit6; + OUT_ENABLE:bit1; + RESERVED1 :bit25; + end; + + TAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES=bitpacked record + IMPEDANCE_SENSE_CAPABLE :bit1; + TRIGGER_REQUIRED :bit1; + JACK_DETECTION_CAPABILITY:bit1; + HEADPHONE_DRIVE_CAPABLE :bit1; + OUTPUT_CAPABLE :bit1; + INPUT_CAPABLE :bit1; + BALANCED_I_O_PINS :bit1; + HDMI :bit1; + VREF_CONTROL :bit8; + EAPD_CAPABLE :bit1; + RESERVED0 :bit7; + DP :bit1; + RESERVED1 :bit7; + end; + + TAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID=bit32; + + TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1=bitpacked record + DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL :bit1; + DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL :bit1; + DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2=bitpacked record + DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3=bitpacked record + DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + RESERVED0 :bit5; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4=bitpacked record + WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + RESERVED0 :bit8; + WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL :bit1; + DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + RESERVED1 :bit6; + end; + + TDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5=bitpacked record + DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL :bit1; + DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL:bit1; + RESERVED0 :bit23; + end; + + TPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET=bit32; + TVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE=bit32; + TVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=bitpacked record + LOGICAL_PAGE_NUMBER:bit28; + RESERVED0 :bit4; + end; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE=bitpacked record + RAMP_RATE:bit8; + RESERVED0:bit24; + end; + + TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA=bit32; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME=bitpacked record + CHANNEL_COUNT :bit3; + RESERVED0 :bit5; + CHANNEL_ALLOCATION:bit8; + INFOFRAME_BYTE_5 :bit8; + RESERVED1 :bit7; + INFOFRAME_VALID :bit1; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER=bitpacked record + SPEAKER_ALLOCATION :bit7; + RESERVED0 :bit1; + CHANNEL_ALLOCATION :bit8; + HDMI_CONNECTION :bit1; + DP_CONNECTION :bit1; + EXTRA_CONNECTION_INFO:bit6; + LFE_PLAYBACK_LEVEL :bit2; + RESERVED1 :bit1; + LEVEL_SHIFT :bit4; + DOWN_MIX_INHIBIT :bit1; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE=bitpacked record + RAMP_RATE:bit8; + RESERVED0:bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME=bitpacked record + CHANNEL_COUNT :bit3; + RESERVED0 :bit5; + CHANNEL_ALLOCATION:bit8; + INFOFRAME_BYTE_5 :bit8; + RESERVED1 :bit7; + INFOFRAME_VALID :bit1; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID=bitpacked record + MANUFACTURER_ID:bit16; + RESERVED0 :bit16; + end; + + TCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL=bitpacked record + CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE :bit1; + RESERVED0 :bit3; + CRTC_EXT_TIMING_SYNC_LOSS_STATUS :bit1; + RESERVED1 :bit3; + CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS :bit1; + RESERVED2 :bit7; + CRTC_EXT_TIMING_SYNC_LOSS_CLEAR :bit1; + RESERVED3 :bit3; + CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE :bit1; + RESERVED4 :bit8; + CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT:bit3; + end; + + TOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS=bitpacked record + STREAM_RESET :bit1; + STREAM_RUN :bit1; + INTERRUPT_ON_COMPLETION_ENABLE :bit1; + FIFO_ERROR_INTERRUPT_ENABLE :bit1; + DESCRIPTOR_ERROR_INTERRUPT_ENABLE :bit1; + RESERVED0 :bit11; + STRIPE_CONTROL :bit2; + TRAFFIC_PRIORITY :bit1; + RESERVED1 :bit1; + STREAM_NUMBER :bit4; + RESERVED2 :bit2; + BUFFER_COMPLETION_INTERRUPT_STATUS:bit1; + FIFO_ERROR :bit1; + DESCRIPTOR_ERROR :bit1; + FIFO_READY :bit1; + RESERVED3 :bit2; + end; + + TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C=bitpacked record + GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C :bit1; + RESERVED0 :bit7; + GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C:bit24; + end; + + TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L=bitpacked record + GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L :bit1; + RESERVED0 :bit7; + GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L:bit24; + end; + + TAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER=bit32; + + TAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE=bitpacked record + POWER_STATE_SET :bit4; + POWER_STATE_ACT :bit4; + RESERVED0 :bit1; + CLKSTOPOK :bit1; + POWER_STATE_SETTINGS_RESET:bit1; + RESERVED1 :bit21; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL=bitpacked record + CLOCK_GATING_DISABLE:bit1; + RESERVED0 :bit3; + CLOCK_ON_STATE :bit1; + RESERVED1 :bit26; + AUDIO_ENABLED :bit1; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE=bitpacked record + REMOTE_KEEP_ALIVE_ENABLE :bit1; + RESERVED0 :bit3; + REMOTE_KEEP_ALIVE_CAPABILITY:bit1; + RESERVED1 :bit27; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC=bitpacked record + VIDEO_LIPSYNC:bit8; + AUDIO_LIPSYNC:bit8; + RESERVED0 :bit16; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE=bitpacked record + POWER_STATE_SET :bit4; + POWER_STATE_ACT :bit4; + RESERVED0 :bit1; + CLKSTOPOK :bit1; + POWER_STATE_SETTINGS_RESET:bit1; + RESERVED1 :bit21; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR=bitpacked record + MAX_CHANNELS :bit3; + FORMAT_CODE :bit4; + RESERVED0 :bit1; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE=bitpacked record + REMOTE_KEEP_ALIVE_ENABLE :bit1; + RESERVED0 :bit3; + REMOTE_KEEP_ALIVE_CAPABILITY:bit1; + RESERVED1 :bit27; + end; + + TAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES :bit8; + DESCRIPTOR_BYTE_2 :bit8; + SUPPORTED_FREQUENCIES_STEREO:bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE=bitpacked record + MULTICHANNEL_MODE:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE=bitpacked record + MULTICHANNEL_MODE:bit1; + RESERVED0 :bit31; + end; + + TCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL=bitpacked record + CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE:bit1; + RESERVED0 :bit3; + CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS :bit1; + RESERVED1 :bit3; + CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS:bit1; + RESERVED2 :bit7; + CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR :bit1; + RESERVED3 :bit3; + CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE :bit1; + RESERVED4 :bit11; + end; + + TOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH=bit32; + + TPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL=bitpacked record + SOFT_PF_FLR:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR=bitpacked record + HBR_CAPABLE:bit1; + RESERVED0 :bit3; + HBR_ENABLE :bit1; + RESERVED1 :bit27; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13=bitpacked record + MAX_CHANNELS :bit3; + RESERVED0 :bit5; + SUPPORTED_FREQUENCIES:bit8; + DESCRIPTOR_BYTE_2 :bit8; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record + IMPEDANCE_SENSE:bit31; + RESERVED0 :bit1; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record + CHANNEL_ALLOCATION:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record + IMPEDANCE_SENSE:bit31; + PRESENCE_DETECT:bit1; + end; + + TAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32; + + TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C=bitpacked record + GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C:bit8; + RESERVED0 :bit24; + end; + + TUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L=bitpacked record + GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING=bitpacked record + PRESENTATION_TIME_EMBEDDING_ENABLE:bit1; + PRESENTATION_TIME_OFFSET_CHANGED :bit1; + CLEAR_GTC_COUNTER_MIN_MAX_DELTA :bit1; + RESERVED0 :bit1; + PRESENTATION_TIME_EMBEDDING_GROUP :bit3; + RESERVED1 :bit25; + end; + + TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX=bit32; + + TAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN=bit32; + + TAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES=bitpacked record + AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES:bit30; + CLKSTOP :bit1; + EPSS :bit1; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE=bitpacked record + MULTICHANNEL01_ENABLE :bit1; + MULTICHANNEL01_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL01_CHANNEL_ID:bit4; + MULTICHANNEL23_ENABLE :bit1; + MULTICHANNEL23_MUTE :bit1; + RESERVED1 :bit2; + MULTICHANNEL23_CHANNEL_ID:bit4; + MULTICHANNEL45_ENABLE :bit1; + MULTICHANNEL45_MUTE :bit1; + RESERVED2 :bit2; + MULTICHANNEL45_CHANNEL_ID:bit4; + MULTICHANNEL67_ENABLE :bit1; + MULTICHANNEL67_MUTE :bit1; + RESERVED3 :bit2; + MULTICHANNEL67_CHANNEL_ID:bit4; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING=bitpacked record + PRESENTATION_TIME_EMBEDDING_ENABLE:bit1; + PRESENTATION_TIME_OFFSET_CHANGED :bit1; + RESERVED0 :bit2; + PRESENTATION_TIME_EMBEDDING_GROUP :bit3; + RESERVED1 :bit25; + end; + + TAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES=bitpacked record + AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES:bit30; + CLKSTOP :bit1; + EPSS :bit1; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32; + + TAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record + IMMEDIATE_COMMAND_WRITE:bit17; + RESERVED0 :bit15; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL=bitpacked record + RESERVED0:bit5; + IN_ENABLE:bit1; + RESERVED1:bit26; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES=bitpacked record + IMPEDANCE_SENSE_CAPABLE :bit1; + TRIGGER_REQUIRED :bit1; + JACK_DETECTION_CAPABILITY:bit1; + HEADPHONE_DRIVE_CAPABLE :bit1; + OUTPUT_CAPABLE :bit1; + INPUT_CAPABLE :bit1; + BALANCED_I_O_PINS :bit1; + HDMI :bit1; + VREF_CONTROL :bit8; + EAPD_CAPABLE :bit1; + RESERVED0 :bit7; + DP :bit1; + RESERVED1 :bit7; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2=bitpacked record + MULTICHANNEL1_ENABLE :bit1; + MULTICHANNEL1_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL1_CHANNEL_ID:bit4; + MULTICHANNEL3_ENABLE :bit1; + MULTICHANNEL3_MUTE :bit1; + RESERVED1 :bit2; + MULTICHANNEL3_CHANNEL_ID:bit4; + MULTICHANNEL5_ENABLE :bit1; + MULTICHANNEL5_MUTE :bit1; + RESERVED2 :bit2; + MULTICHANNEL5_CHANNEL_ID:bit4; + MULTICHANNEL7_ENABLE :bit1; + MULTICHANNEL7_MUTE :bit1; + RESERVED3 :bit2; + MULTICHANNEL7_CHANNEL_ID:bit4; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record + TAG :bit6; + RESERVED0:bit1; + ENABLE :bit1; + RESERVED1:bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL=bitpacked record + RESERVED0:bit5; + IN_ENABLE:bit1; + RESERVED1:bit26; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES=bitpacked record + IMPEDANCE_SENSE_CAPABLE :bit1; + TRIGGER_REQUIRED :bit1; + JACK_DETECTION_CAPABILITY:bit1; + HEADPHONE_DRIVE_CAPABLE :bit1; + OUTPUT_CAPABLE :bit1; + INPUT_CAPABLE :bit1; + BALANCED_I_O_PINS :bit1; + HDMI :bit1; + VREF_CONTROL :bit8; + EAPD_CAPABLE :bit1; + RESERVED0 :bit7; + DP :bit1; + RESERVED1 :bit7; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE=bitpacked record + MULTICHANNEL1_ENABLE :bit1; + MULTICHANNEL1_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL1_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE=bitpacked record + MULTICHANNEL3_ENABLE :bit1; + MULTICHANNEL3_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL3_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE=bitpacked record + MULTICHANNEL5_ENABLE :bit1; + MULTICHANNEL5_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL5_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE=bitpacked record + MULTICHANNEL7_ENABLE :bit1; + MULTICHANNEL7_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL7_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN=bitpacked record + SINK_DESCRIPTION_LEN:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record + TAG :bit6; + RESERVED0:bit1; + ENABLE :bit1; + RESERVED1:bit24; + end; + + TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C=bitpacked record + GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C:bit8; + RESERVED0 :bit24; + end; + + TUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L=bitpacked record + GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS=bitpacked record + OUTPUT_ACTIVE:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record + LPIB_SNAPSHOT_LOCK :bit1; + RESERVED0 :bit7; + CYCLIC_BUFFER_WRAP_COUNT:bit8; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA=bit32; + + TAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX=bitpacked record + SINK_INFO_INDEX:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS=bitpacked record + OUTPUT_ACTIVE:bit1; + RESERVED0 :bit31; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record + LPIB_SNAPSHOT_LOCK :bit1; + RESERVED0 :bit7; + CYCLIC_BUFFER_WRAP_COUNT:bit8; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE=bitpacked record + MULTICHANNEL01_ENABLE :bit1; + MULTICHANNEL01_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL01_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE=bitpacked record + MULTICHANNEL23_ENABLE :bit1; + MULTICHANNEL23_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL23_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE=bitpacked record + MULTICHANNEL45_ENABLE :bit1; + MULTICHANNEL45_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL45_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE=bitpacked record + MULTICHANNEL67_ENABLE :bit1; + MULTICHANNEL67_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL67_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA=bit32; + + TFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX=bit32; + + TFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX=bit32; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record + NUMBER_OF_CHANNELS :bit4; + BITS_PER_SAMPLE :bit3; + RESERVED0 :bit1; + SAMPLE_BASE_DIVISOR :bit3; + SAMPLE_BASE_MULTIPLE:bit3; + SAMPLE_BASE_RATE :bit1; + STREAM_TYPE :bit1; + RESERVED1 :bit16; + end; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG=bit32; + + TAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS=bit32; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL=bitpacked record + CLOCK_GATING_DISABLE:bit1; + RESERVED0 :bit3; + CLOCK_ON_STATE :bit1; + RESERVED1 :bit26; + AUDIO_ENABLED :bit1; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record + NUMBER_OF_CHANNELS :bit4; + BITS_PER_SAMPLE :bit3; + RESERVED0 :bit1; + SAMPLE_BASE_DIVISOR :bit3; + SAMPLE_BASE_MULTIPLE:bit3; + SAMPLE_BASE_RATE :bit1; + STREAM_TYPE :bit1; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS=bit32; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H=bit32; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L=bit32; + + TAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX=bitpacked record + IMMEDIATE_COMMAND_WRITE:bit17; + RESERVED0 :bit15; + end; + + TAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA=bit32; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record + CHANNEL_ID:bit4; + STREAM_ID :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record + DIGEN :bit1; + V :bit1; + VCFG :bit1; + PRE :bit1; + COPY :bit1; + NON_AUDIO:bit1; + PRO :bit1; + L :bit1; + CC :bit7; + RESERVED0:bit8; + KEEPALIVE:bit1; + RESERVED1:bit8; + end; + + TAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID=bit32; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record + CHANNEL_ID:bit4; + STREAM_ID :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record + DIGEN :bit1; + V :bit1; + VCFG :bit1; + PRE :bit1; + COPY :bit1; + NON_AUDIO:bit1; + PRO :bit1; + L :bit1; + CC :bit7; + RESERVED0:bit8; + KEEPALIVE:bit1; + RESERVED1:bit8; + end; + + TAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID=bit32; + + TAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX=bitpacked record + IMMEDIATE_COMMAND_WRITE:bit17; + RESERVED0 :bit15; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record + CHANNEL_ALLOCATION:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION=bitpacked record + CHANNEL_ALLOCATION:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE=bitpacked record + IMPEDANCE_SENSE:bit31; + PRESENCE_DETECT:bit1; + end; + + TAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH=bit32; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE=bitpacked record + MULTICHANNEL0_ENABLE :bit1; + MULTICHANNEL0_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL0_CHANNEL_ID:bit4; + MULTICHANNEL1_ENABLE :bit1; + MULTICHANNEL1_MUTE :bit1; + RESERVED1 :bit2; + MULTICHANNEL1_CHANNEL_ID:bit4; + MULTICHANNEL2_ENABLE :bit1; + MULTICHANNEL2_MUTE :bit1; + RESERVED2 :bit2; + MULTICHANNEL2_CHANNEL_ID:bit4; + MULTICHANNEL3_ENABLE :bit1; + MULTICHANNEL3_MUTE :bit1; + RESERVED3 :bit2; + MULTICHANNEL3_CHANNEL_ID:bit4; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2=bitpacked record + CC :bit7; + RESERVED0:bit25; + end; + + TAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3=bitpacked record + RESERVED0:bit7; + KEEPALIVE:bit1; + RESERVED1:bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT=bit32; + + TAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT=bit32; + + TAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID=bitpacked record + SUBSYSTEM_ID_BYTE0:bit8; + SUBSYSTEM_ID_BYTE1:bit8; + SUBSYSTEM_ID_BYTE2:bit8; + SUBSYSTEM_ID_BYTE3:bit8; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL=bitpacked record + INPUT_ACTIVITY :bit1; + CHANNEL_LAYOUT :bit2; + RESERVED0 :bit1; + INPUT_ACTIVITY_UR_ENABLE :bit1; + INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE:bit1; + RESERVED1 :bit26; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2=bitpacked record + MULTICHANNEL4_ENABLE :bit1; + MULTICHANNEL4_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL4_CHANNEL_ID:bit4; + MULTICHANNEL5_ENABLE :bit1; + MULTICHANNEL5_MUTE :bit1; + RESERVED1 :bit2; + MULTICHANNEL5_CHANNEL_ID:bit4; + MULTICHANNEL6_ENABLE :bit1; + MULTICHANNEL6_MUTE :bit1; + RESERVED2 :bit2; + MULTICHANNEL6_CHANNEL_ID:bit4; + MULTICHANNEL7_ENABLE :bit1; + MULTICHANNEL7_MUTE :bit1; + RESERVED3 :bit2; + MULTICHANNEL7_CHANNEL_ID:bit4; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record + TAG :bit6; + RESERVED0:bit1; + ENABLE :bit1; + RESERVED1:bit24; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE=bitpacked record + UNSOLICITED_RESPONSE_PAYLOAD:bit26; + RESERVED0 :bit2; + UNSOLICITED_RESPONSE_FORCE :bit1; + RESERVED1 :bit3; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID=bitpacked record + SUBSYSTEM_ID_BYTE0:bit8; + SUBSYSTEM_ID_BYTE1:bit8; + SUBSYSTEM_ID_BYTE2:bit8; + SUBSYSTEM_ID_BYTE3:bit8; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL=bitpacked record + INPUT_ACTIVITY :bit1; + CHANNEL_LAYOUT :bit2; + RESERVED0 :bit1; + INPUT_ACTIVITY_UR_ENABLE :bit1; + INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE:bit1; + RESERVED1 :bit26; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE=bitpacked record + MULTICHANNEL0_ENABLE :bit1; + MULTICHANNEL0_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL0_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE=bitpacked record + MULTICHANNEL1_ENABLE :bit1; + MULTICHANNEL1_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL1_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE=bitpacked record + MULTICHANNEL2_ENABLE :bit1; + MULTICHANNEL2_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL2_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE=bitpacked record + MULTICHANNEL3_ENABLE :bit1; + MULTICHANNEL3_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL3_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE=bitpacked record + MULTICHANNEL4_ENABLE :bit1; + MULTICHANNEL4_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL4_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE=bitpacked record + MULTICHANNEL5_ENABLE :bit1; + MULTICHANNEL5_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL5_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE=bitpacked record + MULTICHANNEL6_ENABLE :bit1; + MULTICHANNEL6_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL6_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE=bitpacked record + MULTICHANNEL7_ENABLE :bit1; + MULTICHANNEL7_MUTE :bit1; + RESERVED0 :bit2; + MULTICHANNEL7_CHANNEL_ID:bit4; + RESERVED1 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE=bitpacked record + TAG :bit6; + RESERVED0:bit1; + ENABLE :bit1; + RESERVED1:bit24; + end; + + TAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record + LPIB_SNAPSHOT_LOCK :bit1; + RESERVED0 :bit7; + CYCLIC_BUFFER_WRAP_COUNT:bit8; + RESERVED1 :bit16; + end; + + TAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + RESERVED0 :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED1 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED2 :bit8; + end; + + TAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL=bitpacked record + LPIB_SNAPSHOT_LOCK :bit1; + RESERVED0 :bit7; + CYCLIC_BUFFER_WRAP_COUNT:bit8; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION=bitpacked record + SPEAKER_ALLOCATION :bit7; + RESERVED0 :bit1; + HDMI_CONNECTION :bit1; + DP_CONNECTION :bit1; + EXTRA_CONNECTION_INFO:bit6; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + RESERVED0 :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED1 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED2 :bit8; + end; + + TOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS=bitpacked record + BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS:bit7; + BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS :bit25; + end; + + TOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS=bit32; + + TAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record + NUMBER_OF_CHANNELS :bit4; + BITS_PER_SAMPLE :bit3; + RESERVED0 :bit1; + SAMPLE_BASE_DIVISOR :bit3; + SAMPLE_BASE_MULTIPLE:bit3; + SAMPLE_BASE_RATE :bit1; + STREAM_TYPE :bit1; + RESERVED1 :bit16; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS=bit32; + + TAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2=bitpacked record + SUBSYSTEM_ID_BYTE1:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3=bitpacked record + SUBSYSTEM_ID_BYTE2:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4=bitpacked record + SUBSYSTEM_ID_BYTE3:bit8; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT=bitpacked record + NUMBER_OF_CHANNELS :bit4; + BITS_PER_SAMPLE :bit3; + RESERVED0 :bit1; + SAMPLE_BASE_DIVISOR :bit3; + SAMPLE_BASE_MULTIPLE:bit3; + SAMPLE_BASE_RATE :bit1; + STREAM_TYPE :bit1; + RESERVED1 :bit16; + end; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS=bit32; + + TOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER=bit32; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record + CHANNEL_ID:bit4; + STREAM_ID :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record + DIGEN :bit1; + V :bit1; + VCFG :bit1; + PRE :bit1; + COPY :bit1; + NON_AUDIO:bit1; + PRO :bit1; + L :bit1; + CC :bit7; + RESERVED0:bit8; + KEEPALIVE:bit1; + RESERVED1:bit8; + end; + + TAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT=bit32; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID=bitpacked record + CHANNEL_ID:bit4; + STREAM_ID :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER=bitpacked record + DIGEN :bit1; + V :bit1; + VCFG :bit1; + PRE :bit1; + COPY :bit1; + NON_AUDIO:bit1; + PRO :bit1; + L :bit1; + CC :bit7; + RESERVED0:bit8; + KEEPALIVE:bit1; + RESERVED1:bit8; + end; + + TAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION=bitpacked record + CONVERTER_SYNCHRONIZATION:bit7; + RESERVED0 :bit25; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE=bitpacked record + IMPEDANCE_SENSE:bit31; + PRESENCE_DETECT:bit1; + end; + + TAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record + SEQUENCE :bit4; + DEFAULT_ASSOCIATION:bit4; + MISC :bit4; + COLOR :bit4; + CONNECTION_TYPE :bit4; + DEFAULT_DEVICE :bit4; + LOCATION :bit6; + PORT_CONNECTIVITY :bit2; + end; + + TAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION=bitpacked record + CONVERTER_SYNCHRONIZATION:bit7; + RESERVED0 :bit25; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record + SEQUENCE :bit4; + DEFAULT_ASSOCIATION:bit4; + MISC :bit4; + COLOR :bit4; + CONNECTION_TYPE :bit4; + DEFAULT_DEVICE :bit4; + LOCATION :bit6; + PORT_CONNECTIVITY :bit2; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY=bit32; + + TAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION=bitpacked record + WIRELESS_DISPLAY_IDENTIFICATION:bit2; + RESERVED0 :bit30; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION=bitpacked record + WIRELESS_DISPLAY_IDENTIFICATION:bit2; + RESERVED0 :bit30; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE=bitpacked record + UNSOLICITED_RESPONSE_PAYLOAD:bit26; + RESERVED0 :bit2; + UNSOLICITED_RESPONSE_FORCE :bit1; + RESERVED1 :bit3; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2=bitpacked record + MISC :bit4; + COLOR :bit4; + RESERVED0:bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3=bitpacked record + CONNECTION_TYPE:bit4; + DEFAULT_DEVICE :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4=bitpacked record + LOCATION :bit6; + PORT_CONNECTIVITY:bit2; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + FORMAT_OVERRIDE :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED0 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED1 :bit8; + end; + + TAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + RESERVED0 :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED1 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED2 :bit8; + end; + + TAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + FORMAT_OVERRIDE :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED0 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED1 :bit8; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + RESERVED0 :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED1 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED2 :bit8; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES=bitpacked record + AUDIO_RATE_CAPABILITIES:bit12; + RESERVED0 :bit4; + AUDIO_BIT_CAPABILITIES :bit5; + RESERVED1 :bit11; + end; + + TOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS=bit32; + + TAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record + SEQUENCE :bit4; + DEFAULT_ASSOCIATION:bit4; + MISC :bit4; + COLOR :bit4; + CONNECTION_TYPE :bit4; + DEFAULT_DEVICE :bit4; + LOCATION :bit6; + PORT_CONNECTIVITY :bit2; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT=bitpacked record + SEQUENCE :bit4; + DEFAULT_ASSOCIATION:bit4; + MISC :bit4; + COLOR :bit4; + CONNECTION_TYPE :bit4; + DEFAULT_DEVICE :bit4; + LOCATION :bit6; + PORT_CONNECTIVITY :bit2; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2=bitpacked record + MISC :bit4; + COLOR :bit4; + RESERVED0:bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3=bitpacked record + CONNECTION_TYPE:bit4; + DEFAULT_DEVICE :bit4; + RESERVED0 :bit24; + end; + + TAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4=bitpacked record + LOCATION :bit6; + PORT_CONNECTIVITY:bit2; + RESERVED0 :bit24; + end; + + TAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + FORMAT_OVERRIDE :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED0 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED1 :bit8; + end; + + TAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES=bitpacked record + AUDIO_CHANNEL_CAPABILITIES :bit1; + INPUT_AMPLIFIER_PRESENT :bit1; + OUTPUT_AMPLIFIER_PRESENT :bit1; + AMPLIFIER_PARAMETER_OVERRIDE :bit1; + FORMAT_OVERRIDE :bit1; + STRIPE :bit1; + PROCESSING_WIDGET :bit1; + UNSOLICITED_RESPONSE_CAPABILITY:bit1; + CONNECTION_LIST :bit1; + DIGITAL :bit1; + POWER_CONTROL :bit1; + LR_SWAP :bit1; + RESERVED0 :bit4; + AUDIO_WIDGET_CAPABILITIES_DELAY:bit4; + _TYPE :bit4; + RESERVED1 :bit8; + end; + implementation diff --git a/tools/gfx6_chip/chip.lpr b/tools/gfx6_chip/chip.lpr index a7ecef51..9a8afcc6 100644 --- a/tools/gfx6_chip/chip.lpr +++ b/tools/gfx6_chip/chip.lpr @@ -3,13 +3,35 @@ uses gset, gmap, - Classes,SysUtils; + Classes, + SysUtils; type TRawStrCompare=class class function c(var a,b:RawByteString):boolean; static; end; + TSeries=object + __SI :Boolean; //Southern Islands 1 + __SI__CI:Boolean; + __SI__VI:Boolean; + __VI :Boolean; //Volcanic Islands 2 + __CI__VI:Boolean; + __CI :Boolean; //Caribbean Islands 3 + function get_prio:Integer; + Procedure Apply(var name:RawByteString); + function print_name(const name:RawByteString):RawByteString; + end; + + TConstOffset=class + Name :RawByteString; + Value :RawByteString; + Series:TSeries; + function print_name:RawByteString; + end; + + TMapConstOffset=specialize TMap; + TMapStr=specialize TMap; TSetStr=specialize TSet; @@ -124,11 +146,15 @@ begin end; end; -Procedure CutEnd(var Value:RawByteString;const S:RawByteString); +function CutEnd(var Value:RawByteString;const S:RawByteString):Boolean; begin if Copy(Value,Length(Value)-Length(S)+1,Length(S))=S then begin Delete(Value,Length(Value)-Length(S)+1,Length(S)); + Result:=True; + end else + begin + Result:=False; end; end; @@ -151,12 +177,8 @@ begin end; Var - RMNV_offsets:TMapStr; - RMVN_offsets:TMapStr; - RMNV_default:TMapStr; - RMVN_default:TMapStr; - - Excl_default:TSetStr; + RMNV_offsets:TMapConstOffset; + RMVN_offsets:TMapConstOffset; const MIN_OFFSET=$2000; // $20AD; @@ -246,17 +268,155 @@ begin end; end; +function TSeries.get_prio:Integer; +begin + if __SI then + begin + Result:=1; + end else + if __SI__CI then + begin + Result:=5; + end else + if __SI__VI then + begin + Result:=2; + end else + if __VI then + begin + Result:=3; + end else + if __CI__VI then + begin + Result:=4; + end else + if __CI then + begin + Result:=-1; + end else + begin + Result:=0; + end; +end; + +Procedure TSeries.Apply(var name:RawByteString); +begin + __SI__CI:=CutEnd(Name,'__SI__CI'); + __SI__VI:=CutEnd(Name,'__SI__VI'); + __CI__VI:=CutEnd(Name,'__CI__VI'); + __SI :=CutEnd(Name,'__SI'); + __VI :=CutEnd(Name,'__VI'); + __CI :=CutEnd(Name,'__CI'); +end; + +function TSeries.print_name(const name:RawByteString):RawByteString; +begin + Result:=Name; + if __SI then Result:=Result+'__SI' ; + if __SI__CI then Result:=Result+'__SI__CI'; + if __SI__VI then Result:=Result+'__SI__VI'; + if __VI then Result:=Result+'__VI' ; + if __CI__VI then Result:=Result+'__CI__VI'; + if __CI then Result:=Result+'__CI' ; +end; + +function NewConstOffset(const Name,Value:RawByteString):TConstOffset; +begin + Result:=TConstOffset.Create; + // + Result.Name :=Name; + Result.Value:=Value; + Result.Series.Apply(Result.Name); +end; + +function TConstOffset.print_name:RawByteString; +begin + Result:=Series.print_name(name); +end; + +function NormalizeName(const Name:RawByteString):RawByteString; +begin + Result:=Name; + CutEnd(Result,'__SI__CI'); + CutEnd(Result,'__SI__VI'); + CutEnd(Result,'__CI__VI'); + CutEnd(Result,'__SI'); + CutEnd(Result,'__VI'); + CutEnd(Result,'__CI'); +end; + +function prior_double(const n1:TConstOffset;n2:RawByteString):Byte; +var + tmp:TSeries; +begin + tmp:=Default(TSeries); + tmp.Apply(n2); + + if BeginIs(n1.name,'mmDCP0_') then + begin + Result:=0; + end else + if BeginIs(n2,'mmDCP0_') then + begin + Result:=1; + end else + + if BeginIs(n1.name,'mmCRTC0_') then + begin + Result:=0; + end else + if BeginIs(n2,'mmCRTC0_') then + begin + Result:=1; + end else + + if (n1.name='mmSQ_DS_0') then + begin + Result:=0; + end else + if (n2='mmSQ_DS_0') then + begin + Result:=1; + end else + + if BeginIs(n1.name,'mmCP_RB0_') then + begin + Result:=0; + end else + if BeginIs(n2,'mmCP_RB0_') then + begin + Result:=1; + end else + + if (n1.Series.get_prio>tmp.get_prio) then + begin + Result:=0; + end else + if (n1.Series.get_priovalue if Assigned(It) then begin - if (It.Value<>Value) then - Writeln('Double:',Name,'=',Value,'<>',It.Value); + if (It.Value.Value<>Value) then + begin + Goto _double; + end; FreeAndNil(It); end else begin - it:=RMVN_offsets.Find(Value); + it:=RMVN_offsets.Find(Value); //value->name if Assigned(It) then begin - if (It.Value<>Name) then - Writeln('Double:',Name,'=',Value,'<>',It.Value); - FreeAndNil(It); + if (It.Value.Name<>Name) then + begin + _double: + + ConstOffset:=It.Value; + FreeAndNil(It); + + case prior_double(ConstOffset,Name) of + 0: + begin + Writeln('Double1:',Name,'=',Value,'<>',ConstOffset.print_name); + //nothing + end; + 1: + begin + Writeln('Double2:',Name,'=',Value,'<>',ConstOffset.print_name); + + RMNV_offsets.Delete(ConstOffset.Name); //name->value + RMVN_offsets.Delete(ConstOffset.Value); //value->name + + FreeAndNil(ConstOffset); + + goto _new_values; + end; + else + begin + Writeln('Double3:',Name,'=',Value,'<>',ConstOffset.print_name); + Writeln(''); + end; + end; + + //Writeln('Double:',Name,'=',Value,'<>',It.Value); + end; + end else + begin + _new_values: + + ConstOffset:=NewConstOffset(Name,Value); + + RMNV_offsets.Insert(ConstOffset.Name ,ConstOffset); //name->value + RMVN_offsets.Insert(ConstOffset.Value,ConstOffset); //value->name end; - if Length(Name)>maxlen then maxlen:=Length(Name); - RMNV_offsets.Insert(Name,Value); - RMVN_offsets.Insert(Value,Name); + // end; end; @@ -362,11 +523,25 @@ begin 'const'#13#10; FileWrite(F,Pchar(S)^,Length(S)); + //calc maxlen + maxlen:=0; It:=RMVN_offsets.Min; if Assigned(It) then begin repeat - S:=' '+It.Value+Space(maxlen-Length(It.Value))+'='+It.Key+';'#13#10; + ConstOffset:=It.Value; + if Length(ConstOffset.Name)>maxlen then maxlen:=Length(ConstOffset.Name); + until not It.Next; + FreeAndNil(It); + end; + //calc maxlen + + It:=RMVN_offsets.Min; + if Assigned(It) then + begin + repeat + ConstOffset:=It.Value; + S:=' '+ConstOffset.Name+Space(maxlen-Length(ConstOffset.Name))+'='+ConstOffset.Value+';'#13#10; FileWrite(F,Pchar(S)^,Length(S)); until not It.Next; FreeAndNil(It); @@ -383,7 +558,8 @@ begin if Assigned(It) then begin repeat - S:=' '+It.Value+Space(maxlen-Length(It.Value))+':Result:='#$27+It.Value+#$27';'#13#10; + ConstOffset:=It.Value; + S:=' '+ConstOffset.Name+Space(maxlen-Length(ConstOffset.Name))+':Result:='#$27+ConstOffset.Name+#$27';'#13#10; FileWrite(F,Pchar(S)^,Length(S)); until not It.Next; FreeAndNil(It); @@ -404,7 +580,8 @@ end; type TUnionList=class(TStringList) public - name:RawByteString; + name :RawByteString; + Series :TSeries; bit_size:ptruint; end; TStructList=TUnionList; @@ -414,7 +591,31 @@ type var UnionList:TMapUnionList; +function is_valid_reg_by_offset(const Name:RawByteString):Boolean; +var + It:TMapConstOffset.TIterator; + ConstOffset:TConstOffset; +begin + it:=RMNV_offsets.Find('mm'+NormalizeName(Name)); //name->value + if Assigned(it) then + begin + ConstOffset:=it.Value; + FreeAndNil(it); + + Result:=(ConstOffset.Series.__SI =EndIs(Name,'__SI' )) and + (ConstOffset.Series.__SI__CI=EndIs(Name,'__SI__CI')) and + (ConstOffset.Series.__VI =EndIs(Name,'__VI' )) and + (ConstOffset.Series.__CI__VI=EndIs(Name,'__CI__VI')) and + (ConstOffset.Series.__CI =EndIs(Name,'__CI' )); + end else + begin + Result:=False; + end; +end; + Procedure load_registers(const fname:RawByteString); +label + _new_values; var L:TStringList; maxlen:Integer; @@ -426,6 +627,7 @@ var is_union,is_struct:Boolean; reserved:Integer; union_field:TUnionList; + uprev_field:TUnionList; struct_field:TStructList; name,value:RawByteString; @@ -444,87 +646,42 @@ begin begin name:=FetchAny(S,[' ',#9],[]); - { - if (not EndIs(Name,'__SI')) and - (not EndIs(Name,'__CI')) and - (not EndIs(Name,'__SI__CI')) and - (not BeginIs(Name,'mmDBG')) and - ( - BeginIs(Name,'CB') or - BeginIs(Name,'DB') or - BeginIs(Name,'GB') or - BeginIs(Name,'GRBM') or - BeginIs(Name,'PA') or - BeginIs(Name,'SPI') or - BeginIs(Name,'SX') or - BeginIs(Name,'SQ') or - BeginIs(Name,'TA') or - BeginIs(Name,'VGT') or - BeginIs(Name,'IA') or - BeginIs(Name,'COMPUTE')) then - } - - if (not EndIs(Name,'__SI')) and - (not EndIs(Name,'__SI__CI')) and - (not EndIs(Name,'__CI')) and - - //((not EndIs(Name,'__VI')) or EndIs(Name,'__CI__VI')) and - - (not BeginIs(Name,'DBG')) and - (not BeginIs(Name,'CP_ME_')) and - (not BeginIs(Name,'CP_RB_')) and - (not BeginIs(Name,'CP_RING')) and - (not BeginIs(Name,'SQ_THREAD_TRACE_WORD_')) and - - ( - BeginIs(Name,'CB_') or - BeginIs(Name,'COMPUTE_') or - BeginIs(Name,'CPC_') or - BeginIs(Name,'CPF_') or - BeginIs(Name,'CPG_') or - BeginIs(Name,'CP_') or - BeginIs(Name,'DB_') or - BeginIs(Name,'GDS_') or - BeginIs(Name,'GRBM_') or - BeginIs(Name,'IA_') or - BeginIs(Name,'PA_') or - BeginIs(Name,'SPI_') or - BeginIs(Name,'SQ_BUF_') or - BeginIs(Name,'SQ_IMG_') or - BeginIs(Name,'SQ_THREAD_') or - BeginIs(Name,'SQ_PERFCOUNTER') or - BeginIs(Name,'SX_') or - BeginIs(Name,'TA_') or - BeginIs(Name,'TCA_') or - BeginIs(Name,'TCC_') or - BeginIs(Name,'TCP_') or - BeginIs(Name,'TD_') or - BeginIs(Name,'VGT_') or - BeginIs(Name,'WD_') - ) then - + if (not EndIs(Name,'__CI')) then begin - CutEnd(Name,'__CI__VI'); - CutEnd(Name,'__VI'); - is_union:=True; + is_union :=True; is_struct:=false; reserved:=0; union_field:=TUnionList.Create; union_field.name:=name; + union_field.Series.Apply(union_field.name); end; end; '};': if is_union then begin - is_union:=false; + is_union :=false; is_struct:=false; It:=UnionList.Find(union_field.name); If Assigned(It) then begin - Writeln('Double:',union_field.name); + uprev_field:=It.Value; FreeAndNil(It); + + Writeln('Double:',union_field.name); + + if (union_field.Series.get_prio>uprev_field.Series.get_prio) then + begin + UnionList.Delete(uprev_field.name); + FreeAndNil(uprev_field); + goto _new_values; + end else + begin + FreeAndNil(union_field); + end; + end else begin + _new_values: UnionList.Insert(union_field.name,union_field); end; union_field:=nil; @@ -541,9 +698,7 @@ begin begin is_struct:=False; Name:=FetchAny(S,[' ',#9,',',';'],[]); - CutEnd(Name,'__CI__VI'); - CutEnd(Name,'__VI'); - CutEnd(Name,'__SI'); + Name:=NormalizeName(Name); struct_field.name:=Name; union_field.AddObject(struct_field.name,struct_field); @@ -570,13 +725,13 @@ begin begin Writeln('wtf?:',i); end; - CutEnd(Name,'__CI__VI'); - CutEnd(Name,'__VI'); - CutEnd(Name,'__SI'); + Name:=NormalizeName(Name); Case name of 'INTERFACE', 'OVERRIDE', - 'TYPE':name:='_'+name; + 'TYPE', + 'UNIT', + 'END':name:='_'+name; end; value:=FetchAny(S,[' ',#9,';'],[]); struct_field.Add(name+':bit'+value); @@ -756,9 +911,7 @@ begin (not EndIs(Name,'__SI__CI')) then if FetchAny(S,[' ',#9],[])='=' then begin - CutEnd(Name,'__CI__VI'); - CutEnd(Name,'__VI'); - CutEnd(Name,'__SI'); + Name:=NormalizeName(Name); value:=FetchAny(S,[' ',#9,','],[]); if BeginIs(Value,'0x') then begin @@ -868,7 +1021,7 @@ end; Procedure load_groups(const fname:RawByteString); var - It:TMapStr.TIterator; + ItC:TMapConstOffset.TIterator; ItU:TMapUnionList.TIterator; S,name,value:RawByteString; i,g,v,maxlen_name,maxlen_type,count:Integer; @@ -879,12 +1032,12 @@ var begin FillChar(groups,sizeof(groups),0); - It:=RMVN_offsets.Min; - if Assigned(It) then + ItC:=RMVN_offsets.Min; + if Assigned(ItC) then begin repeat - name :=It.Value; - value:=It.Key; + name :=ItC.Value.Name; + value:=ItC.Value.Value; CutBegin(name,'mm'); @@ -915,8 +1068,8 @@ begin //Writeln('N:',name,' ',value); end; - until not It.Next; - FreeAndNil(It); + until not ItC.Next; + FreeAndNil(ItC); end; //