+

chip/pm4_me.pas

@@ -2896,14 +2896,6 @@ begin
    begin
     ctx.InsertLabel('PERFCOUNTER_SAMPLE');
    end;
-  PIXEL_PIPE_STAT_CONTROL: //[OcclusionQuery] to set up the pixel pipe to perform the dump.
-   begin
-    Writeln(stderr,'TODO:PIXEL_PIPE_STAT_CONTROL');
-   end;
-  PIXEL_PIPE_STAT_DUMP: //[OcclusionQuery] to trigger the actual dump of pixel pipe data.
-   begin
-    Writeln(stderr,'TODO:PIXEL_PIPE_STAT_DUMP');
-   end;
   PIXEL_PIPE_STAT_RESET: //[OcclusionQuery] Reset this query
    begin
     Writeln(stderr,'TODO:PIXEL_PIPE_STAT_RESET');
@@ -2923,25 +2915,46 @@ var
 
 procedure pm4_PipeStatDump(var ctx:t_me_render_context;node:p_pm4_node_PipeStatDump);
 const
- stride=16; //128_BIT  <-TODO:PIPE_STAT_CONTROL
  c_db_counts:array[0..1] of Byte=(8,16);
- c_ready_mask=QWORD(1) shl 63;
+ c_db_stride:array[0..3] of Byte=(4,8,16,32);
+ c_ready_mask_64=QWORD(1) shl 63;
+ c_ready_mask_32=QWORD(1) shl 31;
 var
- i,count:Byte;
+ i,count,stride:Byte;
+ instance_mask :Word;
  addr_dmem:Pointer;
 begin
  if not ctx.WaitConfirmOrSwitch then Exit;
 
- count:=c_db_counts[p_neomode and 1];
+ count :=c_db_counts[p_neomode and 1];
+ stride:=c_db_stride[node^.Control.stride];
+ instance_mask:=node^.Control.instance_enable;
 
  addr_dmem:=get_dmem_ptr(Pointer(node^.address));
 
  fake_zpass_counter:=fake_zpass_counter+1;
 
- For i:=0 to count-1 do
+ if (stride=4) then
  begin
-  PQWORD(addr_dmem)^:=c_ready_mask or fake_zpass_counter;
-  addr_dmem:=addr_dmem+stride;
+
+  For i:=0 to count-1 do
+   if (instance_mask and (1 shl i))<>0 then
+   begin
+    PDWORD(addr_dmem)[i]:=c_ready_mask_32 or fake_zpass_counter;
+   end;
+
+ end else
+ begin
+
+  For i:=0 to count-1 do
+  begin
+   if (instance_mask and (1 shl i))<>0 then
+   begin
+    PQWORD(addr_dmem)^:=c_ready_mask_64 or fake_zpass_counter;
+   end;
+   addr_dmem:=addr_dmem+stride;
+  end;
+
  end;
 
 end;

chip/pm4_pfp.pas

@@ -51,6 +51,8 @@ type
   //
   ASC_COMPUTE:array[0..63] of TSH_REG_COMPUTE_GROUP;
   //
+  PixelPipeStatControl:TPixelPipeStatControl;
+  //
   curr_ibuf :p_pm4_ibuffer;
   //
   LastSetReg:Word;
@@ -1110,8 +1112,8 @@ begin
  Case Body^.eventType of
   PIXEL_PIPE_STAT_CONTROL:
    begin
-    Writeln('  counter_id=',Body^.u.counter_id);
-    Writeln('  stride    =',c_p_stride[Body^.u.stride]);
+    Writeln('  counter_id=',Body^.u.Control.counter_id);
+    Writeln('  stride    =',c_p_stride[Body^.u.Control.stride]);
    end;
   PIXEL_PIPE_STAT_DUMP:
    begin
@@ -1120,9 +1122,13 @@ begin
  end;
 
  Case Body^.eventType of
+  PIXEL_PIPE_STAT_CONTROL:
+   begin
+    pctx^.PixelPipeStatControl:=Body^.u.Control;
+   end;
   PIXEL_PIPE_STAT_DUMP:
    begin
-    pctx^.stream[stGfxDcb].PipeStatDump(Body^.u.address and QWORD($FFFFFFFFF8));
+    pctx^.stream[stGfxDcb].PipeStatDump(Body^.u.address and QWORD($FFFFFFFFF8),pctx^.PixelPipeStatControl);
    end;
   else
    begin

chip/pm4_stream.pas

@@ -281,7 +281,8 @@ type
 
  p_pm4_node_PipeStatDump=^t_pm4_node_PipeStatDump;
  t_pm4_node_PipeStatDump=packed object(t_pm4_node)
-  address:QWORD;
+  Address:QWORD;
+  Control:TPixelPipeStatControl;
  end;
 
  p_pm4_node_EventWriteEop=^t_pm4_node_EventWriteEop;
@@ -419,7 +420,7 @@ type
   procedure WaitOnCECounter();
   procedure WaitOnDECounterDiff(diff:DWORD);
   procedure EventWrite   (eventType:Byte);
-  procedure PipeStatDump (address:QWORD);
+  procedure PipeStatDump (Address:QWORD;Control:TPixelPipeStatControl);
   procedure EventWriteEop(addr:Pointer;data:QWORD;eventType,dataSel,intSel:Byte);
   procedure EventWriteEos(addr:Pointer;data:DWORD;eventType,command:Byte);
   procedure SubmitFlipEop(eop_value:QWORD;intSel:Byte);
@@ -1031,7 +1032,7 @@ begin
  add_node(node);
 end;
 
-procedure t_pm4_stream.PipeStatDump(address:QWORD);
+procedure t_pm4_stream.PipeStatDump(Address:QWORD;Control:TPixelPipeStatControl);
 var
  node:p_pm4_node_PipeStatDump;
 begin
@@ -1039,7 +1040,8 @@ begin
 
  node^.ntype  :=ntPipeStatDump;
  node^.scope  :=Default(t_pm4_resource_curr_scope);
- node^.address:=address;
+ node^.Address:=Address;
+ node^.Control:=Control;
 
  add_node(node);
 end;

chip/pm4defs.pas

@@ -529,6 +529,14 @@ const
  EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT     = 7;
 
 type
+ TPixelPipeStatControl=bitpacked record //[0x7 fc 00] or [0x7 ff fc 00]
+  reserved1      :bit3;
+  counter_id     :bit6;  //00 -> PIXEL_PIPE_OCCLUSION_COUNT_0 // Enum of which counts to dump
+  stride         :bit2;  //02 -> PIXEL_PIPE_STRIDE_128_BITS   // PixelPipeStride enum
+  instance_enable:bit16; //[FF] or [FFFF]                     // Mask of which of the RBs must dump the data.
+  reserved2      :bit5;
+ end;
+
  PTPM4CMDEVENTWRITE=^PM4CMDEVENTWRITE;
  PM4CMDEVENTWRITE=bitpacked record
   header           :PM4_TYPE_3_HEADER;
@@ -548,15 +556,9 @@ type
   u:bitpacked record
    case Byte of
     //PIXEL_PIPE_STAT_DUMP
-    0:(address:QWORD);       // 8 byte aligned (40bit) (0xff fffffff8)
+    0:(Address:QWORD);       // 8 byte aligned (40bit) (0xff fffffff8)
     //PIXEL_PIPE_STAT_CONTROL
-    1:(                      //[0x7 fc 00] or [0x7 ff fc 00]
-       reserved2      :bit3;
-       counter_id     :bit6;  //00 -> PIXEL_PIPE_OCCLUSION_COUNT_0
-       stride         :bit2;  //02 -> PIXEL_PIPE_STRIDE_128_BITS
-       instance_enable:bit16; //[FF] or [FFFF]
-       reserved3      :bit5;
-      );
+    1:(Control:TPixelPipeStatControl);
   end;
  end;