+

spirv/emit_post_op.pas

@@ -2005,6 +2005,29 @@ begin
   pLine:=src.pLine;
 
   vint6:=NewImm_i(dtInt32,6);
+
+  Case count of
+   1:
+     begin
+      rvec[0]:=NewReg(dtInt32);
+
+      pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
+
+      src:=rvec[0];
+     end;
+   2:
+     begin
+      rvec[0]:=NewReg(dtInt32);
+      rvec[1]:=NewReg(dtInt32);
+
+      pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
+      pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[1],src,NewImm_i(dtInt32, 8),vint6);
+
+      src:=NewReg(dtVec2i);
+      pLine:=OpMakeCon(pLine,src,@rvec);
+     end;
+   3:
+     begin
       rvec[0]:=NewReg(dtInt32);
       rvec[1]:=NewReg(dtInt32);
       rvec[2]:=NewReg(dtInt32);
@@ -2015,8 +2038,12 @@ begin
 
       src:=NewReg(dtVec3i);
       pLine:=OpMakeCon(pLine,src,@rvec);
+     end;
+   else
+    Assert(False);
+  end;
 
-  dst.dtype  :=dtVec3i;
+  dst.dtype  :=src.dtype;
   dst.pWriter:=src;
 
   node.mark_not_used;

spirv/srPrivate.pas

@@ -861,7 +861,7 @@ begin
  cur:=RegDownSlot(pSlot^.current);
  prv:=RegDownSlot(prev);
 
- Assert(CompareReg(RegDownSlot(orig),RegDownSlot(prev)));
+ //Assert(CompareReg(RegDownSlot(orig),RegDownSlot(prev)));
 
  if CompareReg(cur,prv) then
  begin

sys/kern/kern_budget.pas

@@ -284,9 +284,10 @@ var
 begin
  ret:=is_sce_prog_attr_20_800000(@g_appinfo);
 
+ if (ret) then
+ begin
   size:=$a0000000; //2GB
-
+ end else
- if (ret=False) then
  begin
   ret:=is_sce_prog_attr_20_400000(@g_appinfo);