mirror of https://github.com/red-prig/fpPS4.git
This commit is contained in:
parent
737c568bf9
commit
c95a363157
|
@ -2005,18 +2005,45 @@ begin
|
|||
pLine:=src.pLine;
|
||||
|
||||
vint6:=NewImm_i(dtInt32,6);
|
||||
rvec[0]:=NewReg(dtInt32);
|
||||
rvec[1]:=NewReg(dtInt32);
|
||||
rvec[2]:=NewReg(dtInt32);
|
||||
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[1],src,NewImm_i(dtInt32, 8),vint6);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[2],src,NewImm_i(dtInt32,16),vint6);
|
||||
Case count of
|
||||
1:
|
||||
begin
|
||||
rvec[0]:=NewReg(dtInt32);
|
||||
|
||||
src:=NewReg(dtVec3i);
|
||||
pLine:=OpMakeCon(pLine,src,@rvec);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
|
||||
|
||||
dst.dtype :=dtVec3i;
|
||||
src:=rvec[0];
|
||||
end;
|
||||
2:
|
||||
begin
|
||||
rvec[0]:=NewReg(dtInt32);
|
||||
rvec[1]:=NewReg(dtInt32);
|
||||
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[1],src,NewImm_i(dtInt32, 8),vint6);
|
||||
|
||||
src:=NewReg(dtVec2i);
|
||||
pLine:=OpMakeCon(pLine,src,@rvec);
|
||||
end;
|
||||
3:
|
||||
begin
|
||||
rvec[0]:=NewReg(dtInt32);
|
||||
rvec[1]:=NewReg(dtInt32);
|
||||
rvec[2]:=NewReg(dtInt32);
|
||||
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[0],src,NewImm_i(dtInt32, 0),vint6);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[1],src,NewImm_i(dtInt32, 8),vint6);
|
||||
pLine:=_Op3(pLine,Op.OpBitFieldSExtract,rvec[2],src,NewImm_i(dtInt32,16),vint6);
|
||||
|
||||
src:=NewReg(dtVec3i);
|
||||
pLine:=OpMakeCon(pLine,src,@rvec);
|
||||
end;
|
||||
else
|
||||
Assert(False);
|
||||
end;
|
||||
|
||||
dst.dtype :=src.dtype;
|
||||
dst.pWriter:=src;
|
||||
|
||||
node.mark_not_used;
|
||||
|
|
|
@ -861,7 +861,7 @@ begin
|
|||
cur:=RegDownSlot(pSlot^.current);
|
||||
prv:=RegDownSlot(prev);
|
||||
|
||||
Assert(CompareReg(RegDownSlot(orig),RegDownSlot(prev)));
|
||||
//Assert(CompareReg(RegDownSlot(orig),RegDownSlot(prev)));
|
||||
|
||||
if CompareReg(cur,prv) then
|
||||
begin
|
||||
|
|
|
@ -284,9 +284,10 @@ var
|
|||
begin
|
||||
ret:=is_sce_prog_attr_20_800000(@g_appinfo);
|
||||
|
||||
size:=$a0000000; //2GB
|
||||
|
||||
if (ret=False) then
|
||||
if (ret) then
|
||||
begin
|
||||
size:=$a0000000; //2GB
|
||||
end else
|
||||
begin
|
||||
ret:=is_sce_prog_attr_20_400000(@g_appinfo);
|
||||
|
||||
|
|
Loading…
Reference in New Issue